openbcm

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fields_u.i (298153B)

      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        fields_u.i
     12  * Purpose:     Field declarations.
     13  */
     14 
     15 #if defined(BCM_88790_A0)
     16 soc_field_info_t soc_U0_LED_ACCU_CTRLr_fields[] = {
     17     { LAST_PORTf, 10, 2, SOCF_LE },
     18     { LED_ACCU_ENf, 1, 0, 0 },
     19     { PORT_ENDIANNESSf, 1, 1, 0 },
     20     { USE_SW_CNFG_LINKf, 1, 12, 0 }
     21 };
     22 
     23 #endif
     24 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
     25     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
     26     defined(BCM_56980_B0)
     27 soc_field_info_t soc_U0_LED_ACCU_CTRL_BCM56870_A0r_fields[] = {
     28     { LAST_PORTf, 10, 2, SOCF_LE },
     29     { LED_ACCU_ENf, 1, 0, 0 },
     30     { PORT_ENDIANNESSf, 1, 1, 0 },
     31     { USE_SW_CNFG_LINKf, 1, 12, 0 }
     32 };
     33 
     34 #endif
     35 #if defined(BCM_88690_A0)
     36 soc_field_info_t soc_U0_LED_ACCU_CTRL_BCM88690_A0r_fields[] = {
     37     { LAST_PORTf, 10, 2, SOCF_LE },
     38     { LED_ACCU_ENf, 1, 0, 0 },
     39     { PORT_ENDIANNESSf, 1, 1, 0 },
     40     { USE_SW_CNFG_LINKf, 1, 12, 0 }
     41 };
     42 
     43 #endif
     44 #if defined(BCM_88690_B0)
     45 soc_field_info_t soc_U0_LED_ACCU_CTRL_BCM88690_B0r_fields[] = {
     46     { LAST_PORTf, 10, 2, SOCF_LE },
     47     { LED_ACCU_ENf, 1, 0, 0 },
     48     { PORT_ENDIANNESSf, 1, 1, 0 },
     49     { USE_SW_CNFG_LINKf, 1, 12, 0 }
     50 };
     51 
     52 #endif
     53 #if defined(BCM_88790_A0)
     54 soc_field_info_t soc_U0_LED_ACCU_STATUSr_fields[] = {
     55     { ACCU_DONEf, 1, 0, 0 }
     56 };
     57 
     58 #endif
     59 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
     60     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
     61     defined(BCM_56980_B0)
     62 soc_field_info_t soc_U0_LED_ACCU_STATUS_BCM56870_A0r_fields[] = {
     63     { ACCU_DONEf, 1, 0, 0 }
     64 };
     65 
     66 #endif
     67 #if defined(BCM_88690_A0)
     68 soc_field_info_t soc_U0_LED_ACCU_STATUS_BCM88690_A0r_fields[] = {
     69     { ACCU_DONEf, 1, 0, 0 }
     70 };
     71 
     72 #endif
     73 #if defined(BCM_88690_B0)
     74 soc_field_info_t soc_U0_LED_ACCU_STATUS_BCM88690_B0r_fields[] = {
     75     { ACCU_DONEf, 1, 0, 0 }
     76 };
     77 
     78 #endif
     79 #if defined(BCM_88790_A0)
     80 soc_field_info_t soc_U0_LED_CLK_DIV_CTRLr_fields[] = {
     81     { LEDCLK_HALF_PERIODf, 16, 0, SOCF_LE }
     82 };
     83 
     84 #endif
     85 #if defined(BCM_88690_A0)
     86 soc_field_info_t soc_U0_LED_CLK_DIV_CTRL_BCM88690_A0r_fields[] = {
     87     { LEDCLK_HALF_PERIODf, 16, 0, SOCF_LE }
     88 };
     89 
     90 #endif
     91 #if defined(BCM_88690_B0)
     92 soc_field_info_t soc_U0_LED_CLK_DIV_CTRL_BCM88690_B0r_fields[] = {
     93     { LEDCLK_HALF_PERIODf, 16, 0, SOCF_LE }
     94 };
     95 
     96 #endif
     97 #if defined(BCM_88790_A0)
     98 soc_field_info_t soc_U0_LED_INTR_ENABLEr_fields[] = {
     99     { ACCU_DONEf, 1, 0, 0 },
    100     { DOUBLE_BIT_ERR_BNK_0f, 1, 3, 0 },
    101     { DOUBLE_BIT_ERR_BNK_1f, 1, 5, 0 },
    102     { SEND_DONEf, 1, 1, 0 },
    103     { SINGLE_BIT_ERR_BNK_0f, 1, 2, 0 },
    104     { SINGLE_BIT_ERR_BNK_1f, 1, 4, 0 }
    105 };
    106 
    107 #endif
    108 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    109     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    110     defined(BCM_56980_B0)
    111 soc_field_info_t soc_U0_LED_INTR_ENABLE_BCM56870_A0r_fields[] = {
    112     { ACCU_DONEf, 1, 0, 0 },
    113     { DOUBLE_BIT_ERR_BNK_0f, 1, 3, 0 },
    114     { DOUBLE_BIT_ERR_BNK_1f, 1, 5, 0 },
    115     { SEND_DONEf, 1, 1, 0 },
    116     { SINGLE_BIT_ERR_BNK_0f, 1, 2, 0 },
    117     { SINGLE_BIT_ERR_BNK_1f, 1, 4, 0 }
    118 };
    119 
    120 #endif
    121 #if defined(BCM_88690_A0)
    122 soc_field_info_t soc_U0_LED_INTR_ENABLE_BCM88690_A0r_fields[] = {
    123     { ACCU_DONEf, 1, 0, 0 },
    124     { DOUBLE_BIT_ERR_BNK_0f, 1, 3, 0 },
    125     { DOUBLE_BIT_ERR_BNK_1f, 1, 5, 0 },
    126     { SEND_DONEf, 1, 1, 0 },
    127     { SINGLE_BIT_ERR_BNK_0f, 1, 2, 0 },
    128     { SINGLE_BIT_ERR_BNK_1f, 1, 4, 0 }
    129 };
    130 
    131 #endif
    132 #if defined(BCM_88690_B0)
    133 soc_field_info_t soc_U0_LED_INTR_ENABLE_BCM88690_B0r_fields[] = {
    134     { ACCU_DONEf, 1, 0, 0 },
    135     { DOUBLE_BIT_ERR_BNK_0f, 1, 3, 0 },
    136     { DOUBLE_BIT_ERR_BNK_1f, 1, 5, 0 },
    137     { SEND_DONEf, 1, 1, 0 },
    138     { SINGLE_BIT_ERR_BNK_0f, 1, 2, 0 },
    139     { SINGLE_BIT_ERR_BNK_1f, 1, 4, 0 }
    140 };
    141 
    142 #endif
    143 #if defined(BCM_88790_A0)
    144 soc_field_info_t soc_U0_LED_REFRESH_CTRLr_fields[] = {
    145     { REFRESH_CYCLE_PERIODf, 32, 0, SOCF_LE }
    146 };
    147 
    148 #endif
    149 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    150     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    151     defined(BCM_56980_B0)
    152 soc_field_info_t soc_U0_LED_REFRESH_CTRL_BCM56870_A0r_fields[] = {
    153     { REFRESH_CYCLE_PERIODf, 32, 0, SOCF_LE }
    154 };
    155 
    156 #endif
    157 #if defined(BCM_88690_A0)
    158 soc_field_info_t soc_U0_LED_REFRESH_CTRL_BCM88690_A0r_fields[] = {
    159     { REFRESH_CYCLE_PERIODf, 32, 0, SOCF_LE }
    160 };
    161 
    162 #endif
    163 #if defined(BCM_88690_B0)
    164 soc_field_info_t soc_U0_LED_REFRESH_CTRL_BCM88690_B0r_fields[] = {
    165     { REFRESH_CYCLE_PERIODf, 32, 0, SOCF_LE }
    166 };
    167 
    168 #endif
    169 #if defined(BCM_88790_A0)
    170 soc_field_info_t soc_U0_LED_SEND_CTRLr_fields[] = {
    171     { LED_SEND_ENf, 5, 0, SOCF_LE }
    172 };
    173 
    174 #endif
    175 #if defined(BCM_88790_A0)
    176 soc_field_info_t soc_U0_LED_SEND_CTRL_0r_fields[] = {
    177     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    178     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    179     { LED_START_ADDRf, 10, 1, SOCF_LE }
    180 };
    181 
    182 #endif
    183 #if defined(BCM_88790_A0)
    184 soc_field_info_t soc_U0_LED_SEND_CTRL_1r_fields[] = {
    185     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    186     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    187     { LED_START_ADDRf, 10, 1, SOCF_LE }
    188 };
    189 
    190 #endif
    191 #if defined(BCM_88790_A0)
    192 soc_field_info_t soc_U0_LED_SEND_CTRL_2r_fields[] = {
    193     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    194     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    195     { LED_START_ADDRf, 10, 1, SOCF_LE }
    196 };
    197 
    198 #endif
    199 #if defined(BCM_88790_A0)
    200 soc_field_info_t soc_U0_LED_SEND_CTRL_3r_fields[] = {
    201     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    202     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    203     { LED_START_ADDRf, 10, 1, SOCF_LE }
    204 };
    205 
    206 #endif
    207 #if defined(BCM_88790_A0)
    208 soc_field_info_t soc_U0_LED_SEND_CTRL_4r_fields[] = {
    209     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    210     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    211     { LED_START_ADDRf, 10, 1, SOCF_LE }
    212 };
    213 
    214 #endif
    215 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    216     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    217     defined(BCM_56980_B0)
    218 soc_field_info_t soc_U0_LED_SEND_CTRL_0_BCM56870_A0r_fields[] = {
    219     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    220     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    221     { LED_START_ADDRf, 10, 1, SOCF_LE }
    222 };
    223 
    224 #endif
    225 #if defined(BCM_88690_A0)
    226 soc_field_info_t soc_U0_LED_SEND_CTRL_0_BCM88690_A0r_fields[] = {
    227     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    228     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    229     { LED_START_ADDRf, 10, 1, SOCF_LE }
    230 };
    231 
    232 #endif
    233 #if defined(BCM_88690_B0)
    234 soc_field_info_t soc_U0_LED_SEND_CTRL_0_BCM88690_B0r_fields[] = {
    235     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    236     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    237     { LED_START_ADDRf, 10, 1, SOCF_LE }
    238 };
    239 
    240 #endif
    241 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    242     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    243     defined(BCM_56980_B0)
    244 soc_field_info_t soc_U0_LED_SEND_CTRL_1_BCM56870_A0r_fields[] = {
    245     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    246     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    247     { LED_START_ADDRf, 10, 1, SOCF_LE }
    248 };
    249 
    250 #endif
    251 #if defined(BCM_88690_A0)
    252 soc_field_info_t soc_U0_LED_SEND_CTRL_1_BCM88690_A0r_fields[] = {
    253     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    254     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    255     { LED_START_ADDRf, 10, 1, SOCF_LE }
    256 };
    257 
    258 #endif
    259 #if defined(BCM_88690_B0)
    260 soc_field_info_t soc_U0_LED_SEND_CTRL_1_BCM88690_B0r_fields[] = {
    261     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    262     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    263     { LED_START_ADDRf, 10, 1, SOCF_LE }
    264 };
    265 
    266 #endif
    267 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    268     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    269     defined(BCM_56980_B0)
    270 soc_field_info_t soc_U0_LED_SEND_CTRL_2_BCM56870_A0r_fields[] = {
    271     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    272     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    273     { LED_START_ADDRf, 10, 1, SOCF_LE }
    274 };
    275 
    276 #endif
    277 #if defined(BCM_88690_A0)
    278 soc_field_info_t soc_U0_LED_SEND_CTRL_2_BCM88690_A0r_fields[] = {
    279     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    280     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    281     { LED_START_ADDRf, 10, 1, SOCF_LE }
    282 };
    283 
    284 #endif
    285 #if defined(BCM_88690_B0)
    286 soc_field_info_t soc_U0_LED_SEND_CTRL_2_BCM88690_B0r_fields[] = {
    287     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    288     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    289     { LED_START_ADDRf, 10, 1, SOCF_LE }
    290 };
    291 
    292 #endif
    293 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    294     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    295     defined(BCM_56980_B0)
    296 soc_field_info_t soc_U0_LED_SEND_CTRL_3_BCM56870_A0r_fields[] = {
    297     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    298     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    299     { LED_START_ADDRf, 10, 1, SOCF_LE }
    300 };
    301 
    302 #endif
    303 #if defined(BCM_88690_A0)
    304 soc_field_info_t soc_U0_LED_SEND_CTRL_3_BCM88690_A0r_fields[] = {
    305     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    306     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    307     { LED_START_ADDRf, 10, 1, SOCF_LE }
    308 };
    309 
    310 #endif
    311 #if defined(BCM_88690_B0)
    312 soc_field_info_t soc_U0_LED_SEND_CTRL_3_BCM88690_B0r_fields[] = {
    313     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    314     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    315     { LED_START_ADDRf, 10, 1, SOCF_LE }
    316 };
    317 
    318 #endif
    319 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    320     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    321     defined(BCM_56980_B0)
    322 soc_field_info_t soc_U0_LED_SEND_CTRL_4_BCM56870_A0r_fields[] = {
    323     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    324     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    325     { LED_START_ADDRf, 10, 1, SOCF_LE }
    326 };
    327 
    328 #endif
    329 #if defined(BCM_88690_A0)
    330 soc_field_info_t soc_U0_LED_SEND_CTRL_4_BCM88690_A0r_fields[] = {
    331     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    332     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    333     { LED_START_ADDRf, 10, 1, SOCF_LE }
    334 };
    335 
    336 #endif
    337 #if defined(BCM_88690_B0)
    338 soc_field_info_t soc_U0_LED_SEND_CTRL_4_BCM88690_B0r_fields[] = {
    339     { LED_NUM_OF_BITS_PER_LOCf, 5, 22, SOCF_LE },
    340     { LED_NUM_OF_LOCSf, 11, 11, SOCF_LE },
    341     { LED_START_ADDRf, 10, 1, SOCF_LE }
    342 };
    343 
    344 #endif
    345 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    346     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    347     defined(BCM_56980_B0)
    348 soc_field_info_t soc_U0_LED_SEND_CTRL_BCM56870_A0r_fields[] = {
    349     { LED_SEND_ENf, 5, 0, SOCF_LE }
    350 };
    351 
    352 #endif
    353 #if defined(BCM_88690_A0)
    354 soc_field_info_t soc_U0_LED_SEND_CTRL_BCM88690_A0r_fields[] = {
    355     { LED_SEND_ENf, 5, 0, SOCF_LE }
    356 };
    357 
    358 #endif
    359 #if defined(BCM_88690_B0)
    360 soc_field_info_t soc_U0_LED_SEND_CTRL_BCM88690_B0r_fields[] = {
    361     { LED_SEND_ENf, 5, 0, SOCF_LE }
    362 };
    363 
    364 #endif
    365 #if defined(BCM_88790_A0)
    366 soc_field_info_t soc_U0_LED_SEND_STATUSr_fields[] = {
    367     { SEND_DONEf, 1, 0, 0 }
    368 };
    369 
    370 #endif
    371 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    372     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    373     defined(BCM_56980_B0)
    374 soc_field_info_t soc_U0_LED_SEND_STATUS_BCM56870_A0r_fields[] = {
    375     { SEND_DONEf, 1, 0, 0 }
    376 };
    377 
    378 #endif
    379 #if defined(BCM_88690_A0)
    380 soc_field_info_t soc_U0_LED_SEND_STATUS_BCM88690_A0r_fields[] = {
    381     { SEND_DONEf, 1, 0, 0 }
    382 };
    383 
    384 #endif
    385 #if defined(BCM_88690_B0)
    386 soc_field_info_t soc_U0_LED_SEND_STATUS_BCM88690_B0r_fields[] = {
    387     { SEND_DONEf, 1, 0, 0 }
    388 };
    389 
    390 #endif
    391 #if defined(BCM_88790_A0)
    392 soc_field_info_t soc_U0_LED_SRAM_CTRLr_fields[] = {
    393     { LED_TMf, 7, 0, SOCF_LE }
    394 };
    395 
    396 #endif
    397 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    398     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    399     defined(BCM_56980_B0)
    400 soc_field_info_t soc_U0_LED_SRAM_CTRL_BCM56870_A0r_fields[] = {
    401     { LED_TMf, 7, 0, SOCF_LE|SOCF_RES }
    402 };
    403 
    404 #endif
    405 #if defined(BCM_88690_A0)
    406 soc_field_info_t soc_U0_LED_SRAM_CTRL_BCM88690_A0r_fields[] = {
    407     { LED_TMf, 7, 0, SOCF_LE }
    408 };
    409 
    410 #endif
    411 #if defined(BCM_88690_B0)
    412 soc_field_info_t soc_U0_LED_SRAM_CTRL_BCM88690_B0r_fields[] = {
    413     { LED_TMf, 7, 0, SOCF_LE }
    414 };
    415 
    416 #endif
    417 #if defined(BCM_88790_A0)
    418 soc_field_info_t soc_U0_LED_SRAM_ECC_CTRLr_fields[] = {
    419     { LED_ECC_ENf, 2, 0, SOCF_LE },
    420     { LED_FORCE_DOUBLE_BIT_ERRf, 2, 4, SOCF_LE },
    421     { LED_FORCE_SINGLE_BIT_ERRf, 2, 2, SOCF_LE }
    422 };
    423 
    424 #endif
    425 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    426     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    427     defined(BCM_56980_B0)
    428 soc_field_info_t soc_U0_LED_SRAM_ECC_CTRL_BCM56870_A0r_fields[] = {
    429     { LED_ECC_ENf, 2, 0, SOCF_LE },
    430     { LED_FORCE_DOUBLE_BIT_ERRf, 2, 4, SOCF_LE },
    431     { LED_FORCE_SINGLE_BIT_ERRf, 2, 2, SOCF_LE }
    432 };
    433 
    434 #endif
    435 #if defined(BCM_88690_A0)
    436 soc_field_info_t soc_U0_LED_SRAM_ECC_CTRL_BCM88690_A0r_fields[] = {
    437     { LED_ECC_ENf, 2, 0, SOCF_LE },
    438     { LED_FORCE_DOUBLE_BIT_ERRf, 2, 4, SOCF_LE },
    439     { LED_FORCE_SINGLE_BIT_ERRf, 2, 2, SOCF_LE }
    440 };
    441 
    442 #endif
    443 #if defined(BCM_88690_B0)
    444 soc_field_info_t soc_U0_LED_SRAM_ECC_CTRL_BCM88690_B0r_fields[] = {
    445     { LED_ECC_ENf, 2, 0, SOCF_LE },
    446     { LED_FORCE_DOUBLE_BIT_ERRf, 2, 4, SOCF_LE },
    447     { LED_FORCE_SINGLE_BIT_ERRf, 2, 2, SOCF_LE }
    448 };
    449 
    450 #endif
    451 #if defined(BCM_88790_A0)
    452 soc_field_info_t soc_U0_LED_SRAM_ECC_STATUSr_fields[] = {
    453     { DOUBLE_BIT_ERR_BNK_0f, 1, 2, 0 },
    454     { DOUBLE_BIT_ERR_BNK_1f, 1, 18, 0 },
    455     { ECC_ERR_BNK_0f, 1, 0, 0 },
    456     { ECC_ERR_BNK_1f, 1, 16, 0 },
    457     { ENTRY_IDX_BNK_0f, 10, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
    458     { ENTRY_IDX_BNK_1f, 10, 19, SOCF_LE|SOCF_RO|SOCF_SIG },
    459     { MULTIPLE_ERR_BNK_0f, 1, 1, 0 },
    460     { MULTIPLE_ERR_BNK_1f, 1, 17, 0 }
    461 };
    462 
    463 #endif
    464 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    465     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
    466     defined(BCM_56980_B0)
    467 soc_field_info_t soc_U0_LED_SRAM_ECC_STATUS_BCM56870_A0r_fields[] = {
    468     { DOUBLE_BIT_ERR_BNK_0f, 1, 2, 0 },
    469     { DOUBLE_BIT_ERR_BNK_1f, 1, 18, 0 },
    470     { ECC_ERR_BNK_0f, 1, 0, 0 },
    471     { ECC_ERR_BNK_1f, 1, 16, 0 },
    472     { ENTRY_IDX_BNK_0f, 10, 3, SOCF_LE|SOCF_RO },
    473     { ENTRY_IDX_BNK_1f, 10, 19, SOCF_LE|SOCF_RO },
    474     { MULTIPLE_ERR_BNK_0f, 1, 1, 0 },
    475     { MULTIPLE_ERR_BNK_1f, 1, 17, 0 }
    476 };
    477 
    478 #endif
    479 #if defined(BCM_88690_A0)
    480 soc_field_info_t soc_U0_LED_SRAM_ECC_STATUS_BCM88690_A0r_fields[] = {
    481     { DOUBLE_BIT_ERR_BNK_0f, 1, 2, 0 },
    482     { DOUBLE_BIT_ERR_BNK_1f, 1, 18, 0 },
    483     { ECC_ERR_BNK_0f, 1, 0, 0 },
    484     { ECC_ERR_BNK_1f, 1, 16, 0 },
    485     { ENTRY_IDX_BNK_0f, 10, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
    486     { ENTRY_IDX_BNK_1f, 10, 19, SOCF_LE|SOCF_RO|SOCF_SIG },
    487     { MULTIPLE_ERR_BNK_0f, 1, 1, 0 },
    488     { MULTIPLE_ERR_BNK_1f, 1, 17, 0 }
    489 };
    490 
    491 #endif
    492 #if defined(BCM_88690_B0)
    493 soc_field_info_t soc_U0_LED_SRAM_ECC_STATUS_BCM88690_B0r_fields[] = {
    494     { DOUBLE_BIT_ERR_BNK_0f, 1, 2, 0 },
    495     { DOUBLE_BIT_ERR_BNK_1f, 1, 18, 0 },
    496     { ECC_ERR_BNK_0f, 1, 0, 0 },
    497     { ECC_ERR_BNK_1f, 1, 16, 0 },
    498     { ENTRY_IDX_BNK_0f, 10, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
    499     { ENTRY_IDX_BNK_1f, 10, 19, SOCF_LE|SOCF_RO|SOCF_SIG },
    500     { MULTIPLE_ERR_BNK_0f, 1, 1, 0 },
    501     { MULTIPLE_ERR_BNK_1f, 1, 17, 0 }
    502 };
    503 
    504 #endif
    505 #if defined(BCM_88790_A0)
    506 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_1023_992r_fields[] = {
    507     { STATUSf, 32, 0, SOCF_LE }
    508 };
    509 
    510 #endif
    511 #if defined(BCM_88690_A0)
    512 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_1023_992_BCM88690_A0r_fields[] = {
    513     { STATUSf, 32, 0, SOCF_LE }
    514 };
    515 
    516 #endif
    517 #if defined(BCM_88690_B0)
    518 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_1023_992_BCM88690_B0r_fields[] = {
    519     { STATUSf, 32, 0, SOCF_LE }
    520 };
    521 
    522 #endif
    523 #if defined(BCM_88790_A0)
    524 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_127_96r_fields[] = {
    525     { STATUSf, 32, 0, SOCF_LE }
    526 };
    527 
    528 #endif
    529 #if defined(BCM_88690_A0)
    530 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_127_96_BCM88690_A0r_fields[] = {
    531     { STATUSf, 32, 0, SOCF_LE }
    532 };
    533 
    534 #endif
    535 #if defined(BCM_88690_B0)
    536 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_127_96_BCM88690_B0r_fields[] = {
    537     { STATUSf, 32, 0, SOCF_LE }
    538 };
    539 
    540 #endif
    541 #if defined(BCM_88790_A0)
    542 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_159_128r_fields[] = {
    543     { STATUSf, 32, 0, SOCF_LE }
    544 };
    545 
    546 #endif
    547 #if defined(BCM_88690_A0)
    548 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_159_128_BCM88690_A0r_fields[] = {
    549     { STATUSf, 32, 0, SOCF_LE }
    550 };
    551 
    552 #endif
    553 #if defined(BCM_88690_B0)
    554 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_159_128_BCM88690_B0r_fields[] = {
    555     { STATUSf, 32, 0, SOCF_LE }
    556 };
    557 
    558 #endif
    559 #if defined(BCM_88790_A0)
    560 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_191_160r_fields[] = {
    561     { STATUSf, 32, 0, SOCF_LE }
    562 };
    563 
    564 #endif
    565 #if defined(BCM_88690_A0)
    566 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_191_160_BCM88690_A0r_fields[] = {
    567     { STATUSf, 32, 0, SOCF_LE }
    568 };
    569 
    570 #endif
    571 #if defined(BCM_88690_B0)
    572 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_191_160_BCM88690_B0r_fields[] = {
    573     { STATUSf, 32, 0, SOCF_LE }
    574 };
    575 
    576 #endif
    577 #if defined(BCM_88790_A0)
    578 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_223_192r_fields[] = {
    579     { STATUSf, 32, 0, SOCF_LE }
    580 };
    581 
    582 #endif
    583 #if defined(BCM_88690_A0)
    584 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_223_192_BCM88690_A0r_fields[] = {
    585     { STATUSf, 32, 0, SOCF_LE }
    586 };
    587 
    588 #endif
    589 #if defined(BCM_88690_B0)
    590 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_223_192_BCM88690_B0r_fields[] = {
    591     { STATUSf, 32, 0, SOCF_LE }
    592 };
    593 
    594 #endif
    595 #if defined(BCM_88790_A0)
    596 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_255_224r_fields[] = {
    597     { STATUSf, 32, 0, SOCF_LE }
    598 };
    599 
    600 #endif
    601 #if defined(BCM_88690_A0)
    602 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_255_224_BCM88690_A0r_fields[] = {
    603     { STATUSf, 32, 0, SOCF_LE }
    604 };
    605 
    606 #endif
    607 #if defined(BCM_88690_B0)
    608 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_255_224_BCM88690_B0r_fields[] = {
    609     { STATUSf, 32, 0, SOCF_LE }
    610 };
    611 
    612 #endif
    613 #if defined(BCM_88790_A0)
    614 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_287_256r_fields[] = {
    615     { STATUSf, 32, 0, SOCF_LE }
    616 };
    617 
    618 #endif
    619 #if defined(BCM_88690_A0)
    620 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_287_256_BCM88690_A0r_fields[] = {
    621     { STATUSf, 32, 0, SOCF_LE }
    622 };
    623 
    624 #endif
    625 #if defined(BCM_88690_B0)
    626 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_287_256_BCM88690_B0r_fields[] = {
    627     { STATUSf, 32, 0, SOCF_LE }
    628 };
    629 
    630 #endif
    631 #if defined(BCM_88790_A0)
    632 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_319_288r_fields[] = {
    633     { STATUSf, 32, 0, SOCF_LE }
    634 };
    635 
    636 #endif
    637 #if defined(BCM_88690_A0)
    638 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_319_288_BCM88690_A0r_fields[] = {
    639     { STATUSf, 32, 0, SOCF_LE }
    640 };
    641 
    642 #endif
    643 #if defined(BCM_88690_B0)
    644 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_319_288_BCM88690_B0r_fields[] = {
    645     { STATUSf, 32, 0, SOCF_LE }
    646 };
    647 
    648 #endif
    649 #if defined(BCM_88790_A0)
    650 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_31_0r_fields[] = {
    651     { STATUSf, 32, 0, SOCF_LE }
    652 };
    653 
    654 #endif
    655 #if defined(BCM_88690_A0)
    656 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_31_0_BCM88690_A0r_fields[] = {
    657     { STATUSf, 32, 0, SOCF_LE }
    658 };
    659 
    660 #endif
    661 #if defined(BCM_88690_B0)
    662 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_31_0_BCM88690_B0r_fields[] = {
    663     { STATUSf, 32, 0, SOCF_LE }
    664 };
    665 
    666 #endif
    667 #if defined(BCM_88790_A0)
    668 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_351_320r_fields[] = {
    669     { STATUSf, 32, 0, SOCF_LE }
    670 };
    671 
    672 #endif
    673 #if defined(BCM_88690_A0)
    674 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_351_320_BCM88690_A0r_fields[] = {
    675     { STATUSf, 32, 0, SOCF_LE }
    676 };
    677 
    678 #endif
    679 #if defined(BCM_88690_B0)
    680 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_351_320_BCM88690_B0r_fields[] = {
    681     { STATUSf, 32, 0, SOCF_LE }
    682 };
    683 
    684 #endif
    685 #if defined(BCM_88790_A0)
    686 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_383_352r_fields[] = {
    687     { STATUSf, 32, 0, SOCF_LE }
    688 };
    689 
    690 #endif
    691 #if defined(BCM_88690_A0)
    692 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_383_352_BCM88690_A0r_fields[] = {
    693     { STATUSf, 32, 0, SOCF_LE }
    694 };
    695 
    696 #endif
    697 #if defined(BCM_88690_B0)
    698 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_383_352_BCM88690_B0r_fields[] = {
    699     { STATUSf, 32, 0, SOCF_LE }
    700 };
    701 
    702 #endif
    703 #if defined(BCM_88790_A0)
    704 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_415_384r_fields[] = {
    705     { STATUSf, 32, 0, SOCF_LE }
    706 };
    707 
    708 #endif
    709 #if defined(BCM_88690_A0)
    710 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_415_384_BCM88690_A0r_fields[] = {
    711     { STATUSf, 32, 0, SOCF_LE }
    712 };
    713 
    714 #endif
    715 #if defined(BCM_88690_B0)
    716 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_415_384_BCM88690_B0r_fields[] = {
    717     { STATUSf, 32, 0, SOCF_LE }
    718 };
    719 
    720 #endif
    721 #if defined(BCM_88790_A0)
    722 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_447_416r_fields[] = {
    723     { STATUSf, 32, 0, SOCF_LE }
    724 };
    725 
    726 #endif
    727 #if defined(BCM_88690_A0)
    728 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_447_416_BCM88690_A0r_fields[] = {
    729     { STATUSf, 32, 0, SOCF_LE }
    730 };
    731 
    732 #endif
    733 #if defined(BCM_88690_B0)
    734 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_447_416_BCM88690_B0r_fields[] = {
    735     { STATUSf, 32, 0, SOCF_LE }
    736 };
    737 
    738 #endif
    739 #if defined(BCM_88790_A0)
    740 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_479_448r_fields[] = {
    741     { STATUSf, 32, 0, SOCF_LE }
    742 };
    743 
    744 #endif
    745 #if defined(BCM_88690_A0)
    746 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_479_448_BCM88690_A0r_fields[] = {
    747     { STATUSf, 32, 0, SOCF_LE }
    748 };
    749 
    750 #endif
    751 #if defined(BCM_88690_B0)
    752 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_479_448_BCM88690_B0r_fields[] = {
    753     { STATUSf, 32, 0, SOCF_LE }
    754 };
    755 
    756 #endif
    757 #if defined(BCM_88790_A0)
    758 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_511_480r_fields[] = {
    759     { STATUSf, 32, 0, SOCF_LE }
    760 };
    761 
    762 #endif
    763 #if defined(BCM_88690_A0)
    764 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_511_480_BCM88690_A0r_fields[] = {
    765     { STATUSf, 32, 0, SOCF_LE }
    766 };
    767 
    768 #endif
    769 #if defined(BCM_88690_B0)
    770 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_511_480_BCM88690_B0r_fields[] = {
    771     { STATUSf, 32, 0, SOCF_LE }
    772 };
    773 
    774 #endif
    775 #if defined(BCM_88790_A0)
    776 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_543_512r_fields[] = {
    777     { STATUSf, 32, 0, SOCF_LE }
    778 };
    779 
    780 #endif
    781 #if defined(BCM_88690_A0)
    782 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_543_512_BCM88690_A0r_fields[] = {
    783     { STATUSf, 32, 0, SOCF_LE }
    784 };
    785 
    786 #endif
    787 #if defined(BCM_88690_B0)
    788 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_543_512_BCM88690_B0r_fields[] = {
    789     { STATUSf, 32, 0, SOCF_LE }
    790 };
    791 
    792 #endif
    793 #if defined(BCM_88790_A0)
    794 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_575_544r_fields[] = {
    795     { STATUSf, 32, 0, SOCF_LE }
    796 };
    797 
    798 #endif
    799 #if defined(BCM_88690_A0)
    800 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_575_544_BCM88690_A0r_fields[] = {
    801     { STATUSf, 32, 0, SOCF_LE }
    802 };
    803 
    804 #endif
    805 #if defined(BCM_88690_B0)
    806 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_575_544_BCM88690_B0r_fields[] = {
    807     { STATUSf, 32, 0, SOCF_LE }
    808 };
    809 
    810 #endif
    811 #if defined(BCM_88790_A0)
    812 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_607_576r_fields[] = {
    813     { STATUSf, 32, 0, SOCF_LE }
    814 };
    815 
    816 #endif
    817 #if defined(BCM_88690_A0)
    818 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_607_576_BCM88690_A0r_fields[] = {
    819     { STATUSf, 32, 0, SOCF_LE }
    820 };
    821 
    822 #endif
    823 #if defined(BCM_88690_B0)
    824 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_607_576_BCM88690_B0r_fields[] = {
    825     { STATUSf, 32, 0, SOCF_LE }
    826 };
    827 
    828 #endif
    829 #if defined(BCM_88790_A0)
    830 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_639_608r_fields[] = {
    831     { STATUSf, 32, 0, SOCF_LE }
    832 };
    833 
    834 #endif
    835 #if defined(BCM_88690_A0)
    836 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_639_608_BCM88690_A0r_fields[] = {
    837     { STATUSf, 32, 0, SOCF_LE }
    838 };
    839 
    840 #endif
    841 #if defined(BCM_88690_B0)
    842 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_639_608_BCM88690_B0r_fields[] = {
    843     { STATUSf, 32, 0, SOCF_LE }
    844 };
    845 
    846 #endif
    847 #if defined(BCM_88790_A0)
    848 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_63_32r_fields[] = {
    849     { STATUSf, 32, 0, SOCF_LE }
    850 };
    851 
    852 #endif
    853 #if defined(BCM_88690_A0)
    854 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_63_32_BCM88690_A0r_fields[] = {
    855     { STATUSf, 32, 0, SOCF_LE }
    856 };
    857 
    858 #endif
    859 #if defined(BCM_88690_B0)
    860 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_63_32_BCM88690_B0r_fields[] = {
    861     { STATUSf, 32, 0, SOCF_LE }
    862 };
    863 
    864 #endif
    865 #if defined(BCM_88790_A0)
    866 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_671_640r_fields[] = {
    867     { STATUSf, 32, 0, SOCF_LE }
    868 };
    869 
    870 #endif
    871 #if defined(BCM_88690_A0)
    872 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_671_640_BCM88690_A0r_fields[] = {
    873     { STATUSf, 32, 0, SOCF_LE }
    874 };
    875 
    876 #endif
    877 #if defined(BCM_88690_B0)
    878 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_671_640_BCM88690_B0r_fields[] = {
    879     { STATUSf, 32, 0, SOCF_LE }
    880 };
    881 
    882 #endif
    883 #if defined(BCM_88790_A0)
    884 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_703_672r_fields[] = {
    885     { STATUSf, 32, 0, SOCF_LE }
    886 };
    887 
    888 #endif
    889 #if defined(BCM_88690_A0)
    890 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_703_672_BCM88690_A0r_fields[] = {
    891     { STATUSf, 32, 0, SOCF_LE }
    892 };
    893 
    894 #endif
    895 #if defined(BCM_88690_B0)
    896 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_703_672_BCM88690_B0r_fields[] = {
    897     { STATUSf, 32, 0, SOCF_LE }
    898 };
    899 
    900 #endif
    901 #if defined(BCM_88790_A0)
    902 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_735_704r_fields[] = {
    903     { STATUSf, 32, 0, SOCF_LE }
    904 };
    905 
    906 #endif
    907 #if defined(BCM_88690_A0)
    908 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_735_704_BCM88690_A0r_fields[] = {
    909     { STATUSf, 32, 0, SOCF_LE }
    910 };
    911 
    912 #endif
    913 #if defined(BCM_88690_B0)
    914 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_735_704_BCM88690_B0r_fields[] = {
    915     { STATUSf, 32, 0, SOCF_LE }
    916 };
    917 
    918 #endif
    919 #if defined(BCM_88790_A0)
    920 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_767_736r_fields[] = {
    921     { STATUSf, 32, 0, SOCF_LE }
    922 };
    923 
    924 #endif
    925 #if defined(BCM_88690_A0)
    926 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_767_736_BCM88690_A0r_fields[] = {
    927     { STATUSf, 32, 0, SOCF_LE }
    928 };
    929 
    930 #endif
    931 #if defined(BCM_88690_B0)
    932 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_767_736_BCM88690_B0r_fields[] = {
    933     { STATUSf, 32, 0, SOCF_LE }
    934 };
    935 
    936 #endif
    937 #if defined(BCM_88790_A0)
    938 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_799_768r_fields[] = {
    939     { STATUSf, 32, 0, SOCF_LE }
    940 };
    941 
    942 #endif
    943 #if defined(BCM_88690_A0)
    944 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_799_768_BCM88690_A0r_fields[] = {
    945     { STATUSf, 32, 0, SOCF_LE }
    946 };
    947 
    948 #endif
    949 #if defined(BCM_88690_B0)
    950 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_799_768_BCM88690_B0r_fields[] = {
    951     { STATUSf, 32, 0, SOCF_LE }
    952 };
    953 
    954 #endif
    955 #if defined(BCM_88790_A0)
    956 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_831_800r_fields[] = {
    957     { STATUSf, 32, 0, SOCF_LE }
    958 };
    959 
    960 #endif
    961 #if defined(BCM_88690_A0)
    962 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_831_800_BCM88690_A0r_fields[] = {
    963     { STATUSf, 32, 0, SOCF_LE }
    964 };
    965 
    966 #endif
    967 #if defined(BCM_88690_B0)
    968 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_831_800_BCM88690_B0r_fields[] = {
    969     { STATUSf, 32, 0, SOCF_LE }
    970 };
    971 
    972 #endif
    973 #if defined(BCM_88790_A0)
    974 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_863_832r_fields[] = {
    975     { STATUSf, 32, 0, SOCF_LE }
    976 };
    977 
    978 #endif
    979 #if defined(BCM_88690_A0)
    980 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_863_832_BCM88690_A0r_fields[] = {
    981     { STATUSf, 32, 0, SOCF_LE }
    982 };
    983 
    984 #endif
    985 #if defined(BCM_88690_B0)
    986 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_863_832_BCM88690_B0r_fields[] = {
    987     { STATUSf, 32, 0, SOCF_LE }
    988 };
    989 
    990 #endif
    991 #if defined(BCM_88790_A0)
    992 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_895_864r_fields[] = {
    993     { STATUSf, 32, 0, SOCF_LE }
    994 };
    995 
    996 #endif
    997 #if defined(BCM_88690_A0)
    998 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_895_864_BCM88690_A0r_fields[] = {
    999     { STATUSf, 32, 0, SOCF_LE }
   1000 };
   1001 
   1002 #endif
   1003 #if defined(BCM_88690_B0)
   1004 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_895_864_BCM88690_B0r_fields[] = {
   1005     { STATUSf, 32, 0, SOCF_LE }
   1006 };
   1007 
   1008 #endif
   1009 #if defined(BCM_88790_A0)
   1010 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_927_896r_fields[] = {
   1011     { STATUSf, 32, 0, SOCF_LE }
   1012 };
   1013 
   1014 #endif
   1015 #if defined(BCM_88690_A0)
   1016 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_927_896_BCM88690_A0r_fields[] = {
   1017     { STATUSf, 32, 0, SOCF_LE }
   1018 };
   1019 
   1020 #endif
   1021 #if defined(BCM_88690_B0)
   1022 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_927_896_BCM88690_B0r_fields[] = {
   1023     { STATUSf, 32, 0, SOCF_LE }
   1024 };
   1025 
   1026 #endif
   1027 #if defined(BCM_88790_A0)
   1028 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_959_928r_fields[] = {
   1029     { STATUSf, 32, 0, SOCF_LE }
   1030 };
   1031 
   1032 #endif
   1033 #if defined(BCM_88690_A0)
   1034 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_959_928_BCM88690_A0r_fields[] = {
   1035     { STATUSf, 32, 0, SOCF_LE }
   1036 };
   1037 
   1038 #endif
   1039 #if defined(BCM_88690_B0)
   1040 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_959_928_BCM88690_B0r_fields[] = {
   1041     { STATUSf, 32, 0, SOCF_LE }
   1042 };
   1043 
   1044 #endif
   1045 #if defined(BCM_88790_A0)
   1046 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_95_64r_fields[] = {
   1047     { STATUSf, 32, 0, SOCF_LE }
   1048 };
   1049 
   1050 #endif
   1051 #if defined(BCM_88690_A0)
   1052 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_95_64_BCM88690_A0r_fields[] = {
   1053     { STATUSf, 32, 0, SOCF_LE }
   1054 };
   1055 
   1056 #endif
   1057 #if defined(BCM_88690_B0)
   1058 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_95_64_BCM88690_B0r_fields[] = {
   1059     { STATUSf, 32, 0, SOCF_LE }
   1060 };
   1061 
   1062 #endif
   1063 #if defined(BCM_88790_A0)
   1064 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_991_960r_fields[] = {
   1065     { STATUSf, 32, 0, SOCF_LE }
   1066 };
   1067 
   1068 #endif
   1069 #if defined(BCM_88690_A0)
   1070 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_991_960_BCM88690_A0r_fields[] = {
   1071     { STATUSf, 32, 0, SOCF_LE }
   1072 };
   1073 
   1074 #endif
   1075 #if defined(BCM_88690_B0)
   1076 soc_field_info_t soc_U0_LED_SW_CNFG_LINK_991_960_BCM88690_B0r_fields[] = {
   1077     { STATUSf, 32, 0, SOCF_LE }
   1078 };
   1079 
   1080 #endif
   1081 #if defined(BCM_56370_A0)
   1082 soc_field_info_t soc_U0_M0SSQ_ADDR_REMAP_WINDOW_0_LSBr_fields[] = {
   1083     { VALf, 10, 0, SOCF_LE }
   1084 };
   1085 
   1086 #endif
   1087 #if defined(BCM_88790_A0)
   1088 soc_field_info_t soc_U0_M0SSQ_CTRLr_fields[] = {
   1089     { M0SS_CLK_ENf, 4, 8, SOCF_LE },
   1090     { M0SS_SOFT_RESETf, 4, 16, SOCF_LE },
   1091     { SRAM_128K_CLK_ENf, 1, 7, 0 },
   1092     { SRAM_128K_SOFT_RESETf, 1, 15, 0 },
   1093     { TCM_TMf, 7, 0, SOCF_LE }
   1094 };
   1095 
   1096 #endif
   1097 #if defined(BCM_56370_A0)
   1098 soc_field_info_t soc_U0_M0SSQ_CTRL_BCM56370_A0r_fields[] = {
   1099     { M0SS_CLK_ENf, 4, 8, SOCF_LE },
   1100     { M0SS_SOFT_RESETf, 4, 16, SOCF_LE },
   1101     { SRAM_128K_CLK_ENf, 1, 7, 0 },
   1102     { SRAM_128K_SOFT_RESETf, 1, 15, 0 }
   1103 };
   1104 
   1105 #endif
   1106 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1107     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1108 soc_field_info_t soc_U0_M0SSQ_CTRL_BCM56870_A0r_fields[] = {
   1109     { M0SS_CLK_ENf, 4, 8, SOCF_LE },
   1110     { M0SS_SOFT_RESETf, 4, 16, SOCF_LE },
   1111     { SRAM_128K_CLK_ENf, 1, 7, 0 },
   1112     { SRAM_128K_SOFT_RESETf, 1, 15, 0 },
   1113     { TCM_TMf, 7, 0, SOCF_LE|SOCF_RES }
   1114 };
   1115 
   1116 #endif
   1117 #if defined(BCM_88690_A0)
   1118 soc_field_info_t soc_U0_M0SSQ_CTRL_BCM88690_A0r_fields[] = {
   1119     { M0SS_CLK_ENf, 4, 8, SOCF_LE },
   1120     { M0SS_SOFT_RESETf, 4, 16, SOCF_LE },
   1121     { SRAM_128K_CLK_ENf, 1, 7, 0 },
   1122     { SRAM_128K_SOFT_RESETf, 1, 15, 0 },
   1123     { TCM_TMf, 7, 0, SOCF_LE }
   1124 };
   1125 
   1126 #endif
   1127 #if defined(BCM_88690_B0)
   1128 soc_field_info_t soc_U0_M0SSQ_CTRL_BCM88690_B0r_fields[] = {
   1129     { M0SS_CLK_ENf, 4, 8, SOCF_LE },
   1130     { M0SS_SOFT_RESETf, 4, 16, SOCF_LE },
   1131     { SRAM_128K_CLK_ENf, 1, 7, 0 },
   1132     { SRAM_128K_SOFT_RESETf, 1, 15, 0 },
   1133     { TCM_TMf, 7, 0, SOCF_LE }
   1134 };
   1135 
   1136 #endif
   1137 #if defined(BCM_88790_A0)
   1138 soc_field_info_t soc_U0_M0SSQ_ECC_CTRLr_fields[] = {
   1139     { TCM_ECC_ENf, 1, 0, 0 },
   1140     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   1141     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   1142 };
   1143 
   1144 #endif
   1145 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   1146     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
   1147     defined(BCM_56980_B0)
   1148 soc_field_info_t soc_U0_M0SSQ_ECC_CTRL_BCM56870_A0r_fields[] = {
   1149     { TCM_ECC_ENf, 1, 0, 0 },
   1150     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   1151     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   1152 };
   1153 
   1154 #endif
   1155 #if defined(BCM_88690_A0)
   1156 soc_field_info_t soc_U0_M0SSQ_ECC_CTRL_BCM88690_A0r_fields[] = {
   1157     { TCM_ECC_ENf, 1, 0, 0 },
   1158     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   1159     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   1160 };
   1161 
   1162 #endif
   1163 #if defined(BCM_88690_B0)
   1164 soc_field_info_t soc_U0_M0SSQ_ECC_CTRL_BCM88690_B0r_fields[] = {
   1165     { TCM_ECC_ENf, 1, 0, 0 },
   1166     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   1167     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   1168 };
   1169 
   1170 #endif
   1171 #if defined(BCM_88790_A0)
   1172 soc_field_info_t soc_U0_M0SSQ_ECC_STATUSr_fields[] = {
   1173     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   1174     { ECC_ERRf, 1, 0, 0 },
   1175     { ENTRY_IDXf, 15, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   1176     { MULTIPLE_ERRf, 1, 1, 0 }
   1177 };
   1178 
   1179 #endif
   1180 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1181     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1182 soc_field_info_t soc_U0_M0SSQ_ECC_STATUS_BCM56870_A0r_fields[] = {
   1183     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   1184     { ECC_ERRf, 1, 0, 0 },
   1185     { ENTRY_IDXf, 15, 3, SOCF_LE|SOCF_RO },
   1186     { MULTIPLE_ERRf, 1, 1, 0 }
   1187 };
   1188 
   1189 #endif
   1190 #if defined(BCM_88690_A0)
   1191 soc_field_info_t soc_U0_M0SSQ_ECC_STATUS_BCM88690_A0r_fields[] = {
   1192     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   1193     { ECC_ERRf, 1, 0, 0 },
   1194     { ENTRY_IDXf, 15, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   1195     { MULTIPLE_ERRf, 1, 1, 0 }
   1196 };
   1197 
   1198 #endif
   1199 #if defined(BCM_88690_B0)
   1200 soc_field_info_t soc_U0_M0SSQ_ECC_STATUS_BCM88690_B0r_fields[] = {
   1201     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   1202     { ECC_ERRf, 1, 0, 0 },
   1203     { ENTRY_IDXf, 15, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   1204     { MULTIPLE_ERRf, 1, 1, 0 }
   1205 };
   1206 
   1207 #endif
   1208 #if defined(BCM_88790_A0)
   1209 soc_field_info_t soc_U0_M0SSQ_INTR_ENABLEr_fields[] = {
   1210     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   1211     { SINGLE_BIT_ERRf, 1, 0, 0 }
   1212 };
   1213 
   1214 #endif
   1215 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   1216     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
   1217     defined(BCM_56980_B0)
   1218 soc_field_info_t soc_U0_M0SSQ_INTR_ENABLE_BCM56870_A0r_fields[] = {
   1219     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   1220     { SINGLE_BIT_ERRf, 1, 0, 0 }
   1221 };
   1222 
   1223 #endif
   1224 #if defined(BCM_88690_A0)
   1225 soc_field_info_t soc_U0_M0SSQ_INTR_ENABLE_BCM88690_A0r_fields[] = {
   1226     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   1227     { SINGLE_BIT_ERRf, 1, 0, 0 }
   1228 };
   1229 
   1230 #endif
   1231 #if defined(BCM_88690_B0)
   1232 soc_field_info_t soc_U0_M0SSQ_INTR_ENABLE_BCM88690_B0r_fields[] = {
   1233     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   1234     { SINGLE_BIT_ERRf, 1, 0, 0 }
   1235 };
   1236 
   1237 #endif
   1238 #if defined(BCM_88790_A0)
   1239 soc_field_info_t soc_U0_M0SS_CONTROLr_fields[] = {
   1240     { SOFT_RESETf, 1, 0, 0 },
   1241     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   1242     { SYS_TICK_CLKENf, 1, 1, 0 }
   1243 };
   1244 
   1245 #endif
   1246 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   1247     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
   1248     defined(BCM_56980_B0)
   1249 soc_field_info_t soc_U0_M0SS_CONTROL_BCM56870_A0r_fields[] = {
   1250     { SOFT_RESETf, 1, 0, 0 },
   1251     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   1252     { SYS_TICK_CLKENf, 1, 1, 0 }
   1253 };
   1254 
   1255 #endif
   1256 #if defined(BCM_88690_A0)
   1257 soc_field_info_t soc_U0_M0SS_CONTROL_BCM88690_A0r_fields[] = {
   1258     { SOFT_RESETf, 1, 0, 0 },
   1259     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   1260     { SYS_TICK_CLKENf, 1, 1, 0 }
   1261 };
   1262 
   1263 #endif
   1264 #if defined(BCM_88690_B0)
   1265 soc_field_info_t soc_U0_M0SS_CONTROL_BCM88690_B0r_fields[] = {
   1266     { SOFT_RESETf, 1, 0, 0 },
   1267     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   1268     { SYS_TICK_CLKENf, 1, 1, 0 }
   1269 };
   1270 
   1271 #endif
   1272 #if defined(BCM_88790_A0)
   1273 soc_field_info_t soc_U0_M0SS_DEBUG_CONTROLr_fields[] = {
   1274     { DBGRESTARTf, 1, 1, 0 },
   1275     { EDBGRQf, 1, 0, 0 }
   1276 };
   1277 
   1278 #endif
   1279 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   1280     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
   1281     defined(BCM_56980_B0)
   1282 soc_field_info_t soc_U0_M0SS_DEBUG_CONTROL_BCM56870_A0r_fields[] = {
   1283     { DBGRESTARTf, 1, 1, 0 },
   1284     { EDBGRQf, 1, 0, 0 }
   1285 };
   1286 
   1287 #endif
   1288 #if defined(BCM_88690_A0)
   1289 soc_field_info_t soc_U0_M0SS_DEBUG_CONTROL_BCM88690_A0r_fields[] = {
   1290     { DBGRESTARTf, 1, 1, 0 },
   1291     { EDBGRQf, 1, 0, 0 }
   1292 };
   1293 
   1294 #endif
   1295 #if defined(BCM_88690_B0)
   1296 soc_field_info_t soc_U0_M0SS_DEBUG_CONTROL_BCM88690_B0r_fields[] = {
   1297     { DBGRESTARTf, 1, 1, 0 },
   1298     { EDBGRQf, 1, 0, 0 }
   1299 };
   1300 
   1301 #endif
   1302 #if defined(BCM_88790_A0)
   1303 soc_field_info_t soc_U0_M0SS_ECC_CTRLr_fields[] = {
   1304     { TCM_ECC_ENf, 1, 0, 0 },
   1305     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   1306     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   1307 };
   1308 
   1309 #endif
   1310 #if defined(BCM_88690_A0)
   1311 soc_field_info_t soc_U0_M0SS_ECC_CTRL_BCM88690_A0r_fields[] = {
   1312     { TCM_ECC_ENf, 1, 0, 0 },
   1313     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   1314     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   1315 };
   1316 
   1317 #endif
   1318 #if defined(BCM_88690_B0)
   1319 soc_field_info_t soc_U0_M0SS_ECC_CTRL_BCM88690_B0r_fields[] = {
   1320     { TCM_ECC_ENf, 1, 0, 0 },
   1321     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   1322     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   1323 };
   1324 
   1325 #endif
   1326 #if defined(BCM_88790_A0)
   1327 soc_field_info_t soc_U0_M0SS_ECC_STATUSr_fields[] = {
   1328     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   1329     { ECC_ERRf, 1, 0, 0 },
   1330     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   1331     { MULTIPLE_ERRf, 1, 1, 0 }
   1332 };
   1333 
   1334 #endif
   1335 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   1336     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
   1337     defined(BCM_56980_B0)
   1338 soc_field_info_t soc_U0_M0SS_ECC_STATUS_BCM56870_A0r_fields[] = {
   1339     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   1340     { ECC_ERRf, 1, 0, 0 },
   1341     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO },
   1342     { MULTIPLE_ERRf, 1, 1, 0 }
   1343 };
   1344 
   1345 #endif
   1346 #if defined(BCM_88690_A0)
   1347 soc_field_info_t soc_U0_M0SS_ECC_STATUS_BCM88690_A0r_fields[] = {
   1348     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   1349     { ECC_ERRf, 1, 0, 0 },
   1350     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   1351     { MULTIPLE_ERRf, 1, 1, 0 }
   1352 };
   1353 
   1354 #endif
   1355 #if defined(BCM_88690_B0)
   1356 soc_field_info_t soc_U0_M0SS_ECC_STATUS_BCM88690_B0r_fields[] = {
   1357     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   1358     { ECC_ERRf, 1, 0, 0 },
   1359     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   1360     { MULTIPLE_ERRf, 1, 1, 0 }
   1361 };
   1362 
   1363 #endif
   1364 #if defined(BCM_88790_A0)
   1365 soc_field_info_t soc_U0_M0SS_ECOr_fields[] = {
   1366     { REV_NUMf, 20, 0, SOCF_LE }
   1367 };
   1368 
   1369 #endif
   1370 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   1371     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
   1372     defined(BCM_56980_B0)
   1373 soc_field_info_t soc_U0_M0SS_ECO_BCM56870_A0r_fields[] = {
   1374     { REV_NUMf, 20, 0, SOCF_LE }
   1375 };
   1376 
   1377 #endif
   1378 #if defined(BCM_88690_A0)
   1379 soc_field_info_t soc_U0_M0SS_ECO_BCM88690_A0r_fields[] = {
   1380     { REV_NUMf, 20, 0, SOCF_LE }
   1381 };
   1382 
   1383 #endif
   1384 #if defined(BCM_88690_B0)
   1385 soc_field_info_t soc_U0_M0SS_ECO_BCM88690_B0r_fields[] = {
   1386     { REV_NUMf, 20, 0, SOCF_LE }
   1387 };
   1388 
   1389 #endif
   1390 #if defined(BCM_88790_A0)
   1391 soc_field_info_t soc_U0_M0SS_INTR_127_96r_fields[] = {
   1392     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1393 };
   1394 
   1395 #endif
   1396 #if defined(BCM_88690_A0)
   1397 soc_field_info_t soc_U0_M0SS_INTR_127_96_BCM88690_A0r_fields[] = {
   1398     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1399 };
   1400 
   1401 #endif
   1402 #if defined(BCM_88690_B0)
   1403 soc_field_info_t soc_U0_M0SS_INTR_127_96_BCM88690_B0r_fields[] = {
   1404     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1405 };
   1406 
   1407 #endif
   1408 #if defined(BCM_88790_A0)
   1409 soc_field_info_t soc_U0_M0SS_INTR_159_128r_fields[] = {
   1410     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1411 };
   1412 
   1413 #endif
   1414 #if defined(BCM_88690_A0)
   1415 soc_field_info_t soc_U0_M0SS_INTR_159_128_BCM88690_A0r_fields[] = {
   1416     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1417 };
   1418 
   1419 #endif
   1420 #if defined(BCM_88690_B0)
   1421 soc_field_info_t soc_U0_M0SS_INTR_159_128_BCM88690_B0r_fields[] = {
   1422     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1423 };
   1424 
   1425 #endif
   1426 #if defined(BCM_88790_A0)
   1427 soc_field_info_t soc_U0_M0SS_INTR_191_160r_fields[] = {
   1428     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1429 };
   1430 
   1431 #endif
   1432 #if defined(BCM_88690_A0)
   1433 soc_field_info_t soc_U0_M0SS_INTR_191_160_BCM88690_A0r_fields[] = {
   1434     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1435 };
   1436 
   1437 #endif
   1438 #if defined(BCM_88690_B0)
   1439 soc_field_info_t soc_U0_M0SS_INTR_191_160_BCM88690_B0r_fields[] = {
   1440     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1441 };
   1442 
   1443 #endif
   1444 #if defined(BCM_88790_A0)
   1445 soc_field_info_t soc_U0_M0SS_INTR_223_192r_fields[] = {
   1446     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1447 };
   1448 
   1449 #endif
   1450 #if defined(BCM_88690_A0)
   1451 soc_field_info_t soc_U0_M0SS_INTR_223_192_BCM88690_A0r_fields[] = {
   1452     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1453 };
   1454 
   1455 #endif
   1456 #if defined(BCM_88690_B0)
   1457 soc_field_info_t soc_U0_M0SS_INTR_223_192_BCM88690_B0r_fields[] = {
   1458     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1459 };
   1460 
   1461 #endif
   1462 #if defined(BCM_88790_A0)
   1463 soc_field_info_t soc_U0_M0SS_INTR_255_224r_fields[] = {
   1464     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1465 };
   1466 
   1467 #endif
   1468 #if defined(BCM_88690_A0)
   1469 soc_field_info_t soc_U0_M0SS_INTR_255_224_BCM88690_A0r_fields[] = {
   1470     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1471 };
   1472 
   1473 #endif
   1474 #if defined(BCM_88690_B0)
   1475 soc_field_info_t soc_U0_M0SS_INTR_255_224_BCM88690_B0r_fields[] = {
   1476     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1477 };
   1478 
   1479 #endif
   1480 #if defined(BCM_88790_A0)
   1481 soc_field_info_t soc_U0_M0SS_INTR_31_0r_fields[] = {
   1482     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1483 };
   1484 
   1485 #endif
   1486 #if defined(BCM_88690_A0)
   1487 soc_field_info_t soc_U0_M0SS_INTR_31_0_BCM88690_A0r_fields[] = {
   1488     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1489 };
   1490 
   1491 #endif
   1492 #if defined(BCM_88690_B0)
   1493 soc_field_info_t soc_U0_M0SS_INTR_31_0_BCM88690_B0r_fields[] = {
   1494     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1495 };
   1496 
   1497 #endif
   1498 #if defined(BCM_88790_A0)
   1499 soc_field_info_t soc_U0_M0SS_INTR_63_32r_fields[] = {
   1500     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1501 };
   1502 
   1503 #endif
   1504 #if defined(BCM_88690_A0)
   1505 soc_field_info_t soc_U0_M0SS_INTR_63_32_BCM88690_A0r_fields[] = {
   1506     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1507 };
   1508 
   1509 #endif
   1510 #if defined(BCM_88690_B0)
   1511 soc_field_info_t soc_U0_M0SS_INTR_63_32_BCM88690_B0r_fields[] = {
   1512     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1513 };
   1514 
   1515 #endif
   1516 #if defined(BCM_88790_A0)
   1517 soc_field_info_t soc_U0_M0SS_INTR_95_64r_fields[] = {
   1518     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1519 };
   1520 
   1521 #endif
   1522 #if defined(BCM_88690_A0)
   1523 soc_field_info_t soc_U0_M0SS_INTR_95_64_BCM88690_A0r_fields[] = {
   1524     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1525 };
   1526 
   1527 #endif
   1528 #if defined(BCM_88690_B0)
   1529 soc_field_info_t soc_U0_M0SS_INTR_95_64_BCM88690_B0r_fields[] = {
   1530     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1531 };
   1532 
   1533 #endif
   1534 #if defined(BCM_88790_A0)
   1535 soc_field_info_t soc_U0_M0SS_INTR_CONTROLr_fields[] = {
   1536     { IRQLATENCYf, 8, 0, SOCF_LE },
   1537     { SLEEPHOLDREQNf, 1, 8, 0 },
   1538     { WICENREQf, 1, 9, 0 }
   1539 };
   1540 
   1541 #endif
   1542 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   1543     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
   1544     defined(BCM_56980_B0)
   1545 soc_field_info_t soc_U0_M0SS_INTR_CONTROL_BCM56870_A0r_fields[] = {
   1546     { IRQLATENCYf, 8, 0, SOCF_LE },
   1547     { SLEEPHOLDREQNf, 1, 8, 0 },
   1548     { WICENREQf, 1, 9, 0 }
   1549 };
   1550 
   1551 #endif
   1552 #if defined(BCM_88690_A0)
   1553 soc_field_info_t soc_U0_M0SS_INTR_CONTROL_BCM88690_A0r_fields[] = {
   1554     { IRQLATENCYf, 8, 0, SOCF_LE },
   1555     { SLEEPHOLDREQNf, 1, 8, 0 },
   1556     { WICENREQf, 1, 9, 0 }
   1557 };
   1558 
   1559 #endif
   1560 #if defined(BCM_88690_B0)
   1561 soc_field_info_t soc_U0_M0SS_INTR_CONTROL_BCM88690_B0r_fields[] = {
   1562     { IRQLATENCYf, 8, 0, SOCF_LE },
   1563     { SLEEPHOLDREQNf, 1, 8, 0 },
   1564     { WICENREQf, 1, 9, 0 }
   1565 };
   1566 
   1567 #endif
   1568 #if defined(BCM_88790_A0)
   1569 soc_field_info_t soc_U0_M0SS_INTR_ENABLEr_fields[] = {
   1570     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   1571     { SINGLE_BIT_ERRf, 1, 0, 0 }
   1572 };
   1573 
   1574 #endif
   1575 #if defined(BCM_88690_A0)
   1576 soc_field_info_t soc_U0_M0SS_INTR_ENABLE_BCM88690_A0r_fields[] = {
   1577     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   1578     { SINGLE_BIT_ERRf, 1, 0, 0 }
   1579 };
   1580 
   1581 #endif
   1582 #if defined(BCM_88690_B0)
   1583 soc_field_info_t soc_U0_M0SS_INTR_ENABLE_BCM88690_B0r_fields[] = {
   1584     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   1585     { SINGLE_BIT_ERRf, 1, 0, 0 }
   1586 };
   1587 
   1588 #endif
   1589 #if defined(BCM_88790_A0)
   1590 soc_field_info_t soc_U0_M0SS_INTR_MASK_127_96r_fields[] = {
   1591     { CNFGf, 32, 0, SOCF_LE }
   1592 };
   1593 
   1594 #endif
   1595 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   1596     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
   1597     defined(BCM_56980_B0)
   1598 soc_field_info_t soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields[] = {
   1599     { CNFGf, 32, 0, SOCF_LE }
   1600 };
   1601 
   1602 #endif
   1603 #if defined(BCM_88690_A0)
   1604 soc_field_info_t soc_U0_M0SS_INTR_MASK_127_96_BCM88690_A0r_fields[] = {
   1605     { CNFGf, 32, 0, SOCF_LE }
   1606 };
   1607 
   1608 #endif
   1609 #if defined(BCM_88690_B0)
   1610 soc_field_info_t soc_U0_M0SS_INTR_MASK_127_96_BCM88690_B0r_fields[] = {
   1611     { CNFGf, 32, 0, SOCF_LE }
   1612 };
   1613 
   1614 #endif
   1615 #if defined(BCM_88790_A0)
   1616 soc_field_info_t soc_U0_M0SS_INTR_MASK_159_128r_fields[] = {
   1617     { CNFGf, 32, 0, SOCF_LE }
   1618 };
   1619 
   1620 #endif
   1621 #if defined(BCM_88690_A0)
   1622 soc_field_info_t soc_U0_M0SS_INTR_MASK_159_128_BCM88690_A0r_fields[] = {
   1623     { CNFGf, 32, 0, SOCF_LE }
   1624 };
   1625 
   1626 #endif
   1627 #if defined(BCM_88690_B0)
   1628 soc_field_info_t soc_U0_M0SS_INTR_MASK_159_128_BCM88690_B0r_fields[] = {
   1629     { CNFGf, 32, 0, SOCF_LE }
   1630 };
   1631 
   1632 #endif
   1633 #if defined(BCM_88790_A0)
   1634 soc_field_info_t soc_U0_M0SS_INTR_MASK_191_160r_fields[] = {
   1635     { CNFGf, 32, 0, SOCF_LE }
   1636 };
   1637 
   1638 #endif
   1639 #if defined(BCM_88690_A0)
   1640 soc_field_info_t soc_U0_M0SS_INTR_MASK_191_160_BCM88690_A0r_fields[] = {
   1641     { CNFGf, 32, 0, SOCF_LE }
   1642 };
   1643 
   1644 #endif
   1645 #if defined(BCM_88690_B0)
   1646 soc_field_info_t soc_U0_M0SS_INTR_MASK_191_160_BCM88690_B0r_fields[] = {
   1647     { CNFGf, 32, 0, SOCF_LE }
   1648 };
   1649 
   1650 #endif
   1651 #if defined(BCM_88790_A0)
   1652 soc_field_info_t soc_U0_M0SS_INTR_MASK_223_192r_fields[] = {
   1653     { CNFGf, 32, 0, SOCF_LE }
   1654 };
   1655 
   1656 #endif
   1657 #if defined(BCM_88690_A0)
   1658 soc_field_info_t soc_U0_M0SS_INTR_MASK_223_192_BCM88690_A0r_fields[] = {
   1659     { CNFGf, 32, 0, SOCF_LE }
   1660 };
   1661 
   1662 #endif
   1663 #if defined(BCM_88690_B0)
   1664 soc_field_info_t soc_U0_M0SS_INTR_MASK_223_192_BCM88690_B0r_fields[] = {
   1665     { CNFGf, 32, 0, SOCF_LE }
   1666 };
   1667 
   1668 #endif
   1669 #if defined(BCM_88790_A0)
   1670 soc_field_info_t soc_U0_M0SS_INTR_MASK_255_224r_fields[] = {
   1671     { CNFGf, 32, 0, SOCF_LE }
   1672 };
   1673 
   1674 #endif
   1675 #if defined(BCM_88690_A0)
   1676 soc_field_info_t soc_U0_M0SS_INTR_MASK_255_224_BCM88690_A0r_fields[] = {
   1677     { CNFGf, 32, 0, SOCF_LE }
   1678 };
   1679 
   1680 #endif
   1681 #if defined(BCM_88690_B0)
   1682 soc_field_info_t soc_U0_M0SS_INTR_MASK_255_224_BCM88690_B0r_fields[] = {
   1683     { CNFGf, 32, 0, SOCF_LE }
   1684 };
   1685 
   1686 #endif
   1687 #if defined(BCM_88790_A0)
   1688 soc_field_info_t soc_U0_M0SS_INTR_MASK_31_0r_fields[] = {
   1689     { CNFGf, 32, 0, SOCF_LE }
   1690 };
   1691 
   1692 #endif
   1693 #if defined(BCM_88690_A0)
   1694 soc_field_info_t soc_U0_M0SS_INTR_MASK_31_0_BCM88690_A0r_fields[] = {
   1695     { CNFGf, 32, 0, SOCF_LE }
   1696 };
   1697 
   1698 #endif
   1699 #if defined(BCM_88690_B0)
   1700 soc_field_info_t soc_U0_M0SS_INTR_MASK_31_0_BCM88690_B0r_fields[] = {
   1701     { CNFGf, 32, 0, SOCF_LE }
   1702 };
   1703 
   1704 #endif
   1705 #if defined(BCM_88790_A0)
   1706 soc_field_info_t soc_U0_M0SS_INTR_MASK_63_32r_fields[] = {
   1707     { CNFGf, 32, 0, SOCF_LE }
   1708 };
   1709 
   1710 #endif
   1711 #if defined(BCM_88690_A0)
   1712 soc_field_info_t soc_U0_M0SS_INTR_MASK_63_32_BCM88690_A0r_fields[] = {
   1713     { CNFGf, 32, 0, SOCF_LE }
   1714 };
   1715 
   1716 #endif
   1717 #if defined(BCM_88690_B0)
   1718 soc_field_info_t soc_U0_M0SS_INTR_MASK_63_32_BCM88690_B0r_fields[] = {
   1719     { CNFGf, 32, 0, SOCF_LE }
   1720 };
   1721 
   1722 #endif
   1723 #if defined(BCM_88790_A0)
   1724 soc_field_info_t soc_U0_M0SS_INTR_MASK_95_64r_fields[] = {
   1725     { CNFGf, 32, 0, SOCF_LE }
   1726 };
   1727 
   1728 #endif
   1729 #if defined(BCM_88690_A0)
   1730 soc_field_info_t soc_U0_M0SS_INTR_MASK_95_64_BCM88690_A0r_fields[] = {
   1731     { CNFGf, 32, 0, SOCF_LE }
   1732 };
   1733 
   1734 #endif
   1735 #if defined(BCM_88690_B0)
   1736 soc_field_info_t soc_U0_M0SS_INTR_MASK_95_64_BCM88690_B0r_fields[] = {
   1737     { CNFGf, 32, 0, SOCF_LE }
   1738 };
   1739 
   1740 #endif
   1741 #if defined(BCM_88790_A0)
   1742 soc_field_info_t soc_U0_M0SS_RAW_INTR_127_96r_fields[] = {
   1743     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1744 };
   1745 
   1746 #endif
   1747 #if defined(BCM_88690_A0)
   1748 soc_field_info_t soc_U0_M0SS_RAW_INTR_127_96_BCM88690_A0r_fields[] = {
   1749     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1750 };
   1751 
   1752 #endif
   1753 #if defined(BCM_88690_B0)
   1754 soc_field_info_t soc_U0_M0SS_RAW_INTR_127_96_BCM88690_B0r_fields[] = {
   1755     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1756 };
   1757 
   1758 #endif
   1759 #if defined(BCM_88790_A0)
   1760 soc_field_info_t soc_U0_M0SS_RAW_INTR_159_128r_fields[] = {
   1761     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1762 };
   1763 
   1764 #endif
   1765 #if defined(BCM_88690_A0)
   1766 soc_field_info_t soc_U0_M0SS_RAW_INTR_159_128_BCM88690_A0r_fields[] = {
   1767     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1768 };
   1769 
   1770 #endif
   1771 #if defined(BCM_88690_B0)
   1772 soc_field_info_t soc_U0_M0SS_RAW_INTR_159_128_BCM88690_B0r_fields[] = {
   1773     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1774 };
   1775 
   1776 #endif
   1777 #if defined(BCM_88790_A0)
   1778 soc_field_info_t soc_U0_M0SS_RAW_INTR_191_160r_fields[] = {
   1779     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1780 };
   1781 
   1782 #endif
   1783 #if defined(BCM_88690_A0)
   1784 soc_field_info_t soc_U0_M0SS_RAW_INTR_191_160_BCM88690_A0r_fields[] = {
   1785     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1786 };
   1787 
   1788 #endif
   1789 #if defined(BCM_88690_B0)
   1790 soc_field_info_t soc_U0_M0SS_RAW_INTR_191_160_BCM88690_B0r_fields[] = {
   1791     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1792 };
   1793 
   1794 #endif
   1795 #if defined(BCM_88790_A0)
   1796 soc_field_info_t soc_U0_M0SS_RAW_INTR_223_192r_fields[] = {
   1797     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1798 };
   1799 
   1800 #endif
   1801 #if defined(BCM_88690_A0)
   1802 soc_field_info_t soc_U0_M0SS_RAW_INTR_223_192_BCM88690_A0r_fields[] = {
   1803     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1804 };
   1805 
   1806 #endif
   1807 #if defined(BCM_88690_B0)
   1808 soc_field_info_t soc_U0_M0SS_RAW_INTR_223_192_BCM88690_B0r_fields[] = {
   1809     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1810 };
   1811 
   1812 #endif
   1813 #if defined(BCM_88790_A0)
   1814 soc_field_info_t soc_U0_M0SS_RAW_INTR_255_224r_fields[] = {
   1815     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1816 };
   1817 
   1818 #endif
   1819 #if defined(BCM_88690_A0)
   1820 soc_field_info_t soc_U0_M0SS_RAW_INTR_255_224_BCM88690_A0r_fields[] = {
   1821     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1822 };
   1823 
   1824 #endif
   1825 #if defined(BCM_88690_B0)
   1826 soc_field_info_t soc_U0_M0SS_RAW_INTR_255_224_BCM88690_B0r_fields[] = {
   1827     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1828 };
   1829 
   1830 #endif
   1831 #if defined(BCM_88790_A0)
   1832 soc_field_info_t soc_U0_M0SS_RAW_INTR_31_0r_fields[] = {
   1833     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1834 };
   1835 
   1836 #endif
   1837 #if defined(BCM_88690_A0)
   1838 soc_field_info_t soc_U0_M0SS_RAW_INTR_31_0_BCM88690_A0r_fields[] = {
   1839     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1840 };
   1841 
   1842 #endif
   1843 #if defined(BCM_88690_B0)
   1844 soc_field_info_t soc_U0_M0SS_RAW_INTR_31_0_BCM88690_B0r_fields[] = {
   1845     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1846 };
   1847 
   1848 #endif
   1849 #if defined(BCM_88790_A0)
   1850 soc_field_info_t soc_U0_M0SS_RAW_INTR_63_32r_fields[] = {
   1851     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1852 };
   1853 
   1854 #endif
   1855 #if defined(BCM_88690_A0)
   1856 soc_field_info_t soc_U0_M0SS_RAW_INTR_63_32_BCM88690_A0r_fields[] = {
   1857     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1858 };
   1859 
   1860 #endif
   1861 #if defined(BCM_88690_B0)
   1862 soc_field_info_t soc_U0_M0SS_RAW_INTR_63_32_BCM88690_B0r_fields[] = {
   1863     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1864 };
   1865 
   1866 #endif
   1867 #if defined(BCM_88790_A0)
   1868 soc_field_info_t soc_U0_M0SS_RAW_INTR_95_64r_fields[] = {
   1869     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1870 };
   1871 
   1872 #endif
   1873 #if defined(BCM_88690_A0)
   1874 soc_field_info_t soc_U0_M0SS_RAW_INTR_95_64_BCM88690_A0r_fields[] = {
   1875     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1876 };
   1877 
   1878 #endif
   1879 #if defined(BCM_88690_B0)
   1880 soc_field_info_t soc_U0_M0SS_RAW_INTR_95_64_BCM88690_B0r_fields[] = {
   1881     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   1882 };
   1883 
   1884 #endif
   1885 #if defined(BCM_88790_A0)
   1886 soc_field_info_t soc_U0_M0SS_STATUSr_fields[] = {
   1887     { DBGRESTARTEDf, 1, 0, 0 },
   1888     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   1889     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   1890     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   1891     { SLEEPHOLDACKf, 1, 2, 0 },
   1892     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   1893     { SYSRESETREQf, 1, 1, 0 },
   1894     { TXEVf, 16, 16, SOCF_LE },
   1895     { WAKEUPf, 1, 4, 0 },
   1896     { WICENACKf, 1, 3, 0 }
   1897 };
   1898 
   1899 #endif
   1900 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   1901     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
   1902     defined(BCM_56980_B0)
   1903 soc_field_info_t soc_U0_M0SS_STATUS_BCM56870_A0r_fields[] = {
   1904     { DBGRESTARTEDf, 1, 0, 0 },
   1905     { HALTEDf, 1, 8, SOCF_RO },
   1906     { LOCKUPf, 1, 9, SOCF_RO },
   1907     { SLEEPDEEPf, 1, 10, SOCF_RO },
   1908     { SLEEPHOLDACKf, 1, 2, 0 },
   1909     { SLEEPINGf, 1, 11, SOCF_RO },
   1910     { SYSRESETREQf, 1, 1, 0 },
   1911     { TXEVf, 16, 16, SOCF_LE },
   1912     { WAKEUPf, 1, 4, 0 },
   1913     { WICENACKf, 1, 3, 0 }
   1914 };
   1915 
   1916 #endif
   1917 #if defined(BCM_88690_A0)
   1918 soc_field_info_t soc_U0_M0SS_STATUS_BCM88690_A0r_fields[] = {
   1919     { DBGRESTARTEDf, 1, 0, 0 },
   1920     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   1921     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   1922     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   1923     { SLEEPHOLDACKf, 1, 2, 0 },
   1924     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   1925     { SYSRESETREQf, 1, 1, 0 },
   1926     { TXEVf, 16, 16, SOCF_LE },
   1927     { WAKEUPf, 1, 4, 0 },
   1928     { WICENACKf, 1, 3, 0 }
   1929 };
   1930 
   1931 #endif
   1932 #if defined(BCM_88690_B0)
   1933 soc_field_info_t soc_U0_M0SS_STATUS_BCM88690_B0r_fields[] = {
   1934     { DBGRESTARTEDf, 1, 0, 0 },
   1935     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   1936     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   1937     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   1938     { SLEEPHOLDACKf, 1, 2, 0 },
   1939     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   1940     { SYSRESETREQf, 1, 1, 0 },
   1941     { TXEVf, 16, 16, SOCF_LE },
   1942     { WAKEUPf, 1, 4, 0 },
   1943     { WICENACKf, 1, 3, 0 }
   1944 };
   1945 
   1946 #endif
   1947 #if defined(BCM_88790_A0)
   1948 soc_field_info_t soc_U0_M0SS_TCM_CTRLr_fields[] = {
   1949     { TCM_TMf, 7, 0, SOCF_LE }
   1950 };
   1951 
   1952 #endif
   1953 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   1954     defined(BCM_56870_A0) || defined(BCM_56980_A0) || \
   1955     defined(BCM_56980_B0)
   1956 soc_field_info_t soc_U0_M0SS_TCM_CTRL_BCM56870_A0r_fields[] = {
   1957     { TCM_TMf, 7, 0, SOCF_LE|SOCF_RES }
   1958 };
   1959 
   1960 #endif
   1961 #if defined(BCM_88690_A0)
   1962 soc_field_info_t soc_U0_M0SS_TCM_CTRL_BCM88690_A0r_fields[] = {
   1963     { TCM_TMf, 7, 0, SOCF_LE }
   1964 };
   1965 
   1966 #endif
   1967 #if defined(BCM_88690_B0)
   1968 soc_field_info_t soc_U0_M0SS_TCM_CTRL_BCM88690_B0r_fields[] = {
   1969     { TCM_TMf, 7, 0, SOCF_LE }
   1970 };
   1971 
   1972 #endif
   1973 #if defined(BCM_88790_A0)
   1974 soc_field_info_t soc_U1_M0SS_CONTROLr_fields[] = {
   1975     { SOFT_RESETf, 1, 0, 0 },
   1976     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   1977     { SYS_TICK_CLKENf, 1, 1, 0 }
   1978 };
   1979 
   1980 #endif
   1981 #if defined(BCM_88690_A0)
   1982 soc_field_info_t soc_U1_M0SS_CONTROL_BCM88690_A0r_fields[] = {
   1983     { SOFT_RESETf, 1, 0, 0 },
   1984     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   1985     { SYS_TICK_CLKENf, 1, 1, 0 }
   1986 };
   1987 
   1988 #endif
   1989 #if defined(BCM_88690_B0)
   1990 soc_field_info_t soc_U1_M0SS_CONTROL_BCM88690_B0r_fields[] = {
   1991     { SOFT_RESETf, 1, 0, 0 },
   1992     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   1993     { SYS_TICK_CLKENf, 1, 1, 0 }
   1994 };
   1995 
   1996 #endif
   1997 #if defined(BCM_88790_A0)
   1998 soc_field_info_t soc_U1_M0SS_DEBUG_CONTROLr_fields[] = {
   1999     { DBGRESTARTf, 1, 1, 0 },
   2000     { EDBGRQf, 1, 0, 0 }
   2001 };
   2002 
   2003 #endif
   2004 #if defined(BCM_88690_A0)
   2005 soc_field_info_t soc_U1_M0SS_DEBUG_CONTROL_BCM88690_A0r_fields[] = {
   2006     { DBGRESTARTf, 1, 1, 0 },
   2007     { EDBGRQf, 1, 0, 0 }
   2008 };
   2009 
   2010 #endif
   2011 #if defined(BCM_88690_B0)
   2012 soc_field_info_t soc_U1_M0SS_DEBUG_CONTROL_BCM88690_B0r_fields[] = {
   2013     { DBGRESTARTf, 1, 1, 0 },
   2014     { EDBGRQf, 1, 0, 0 }
   2015 };
   2016 
   2017 #endif
   2018 #if defined(BCM_88790_A0)
   2019 soc_field_info_t soc_U1_M0SS_ECC_CTRLr_fields[] = {
   2020     { TCM_ECC_ENf, 1, 0, 0 },
   2021     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   2022     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   2023 };
   2024 
   2025 #endif
   2026 #if defined(BCM_88690_A0)
   2027 soc_field_info_t soc_U1_M0SS_ECC_CTRL_BCM88690_A0r_fields[] = {
   2028     { TCM_ECC_ENf, 1, 0, 0 },
   2029     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   2030     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   2031 };
   2032 
   2033 #endif
   2034 #if defined(BCM_88690_B0)
   2035 soc_field_info_t soc_U1_M0SS_ECC_CTRL_BCM88690_B0r_fields[] = {
   2036     { TCM_ECC_ENf, 1, 0, 0 },
   2037     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   2038     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   2039 };
   2040 
   2041 #endif
   2042 #if defined(BCM_88790_A0)
   2043 soc_field_info_t soc_U1_M0SS_ECC_STATUSr_fields[] = {
   2044     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   2045     { ECC_ERRf, 1, 0, 0 },
   2046     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   2047     { MULTIPLE_ERRf, 1, 1, 0 }
   2048 };
   2049 
   2050 #endif
   2051 #if defined(BCM_88690_A0)
   2052 soc_field_info_t soc_U1_M0SS_ECC_STATUS_BCM88690_A0r_fields[] = {
   2053     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   2054     { ECC_ERRf, 1, 0, 0 },
   2055     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   2056     { MULTIPLE_ERRf, 1, 1, 0 }
   2057 };
   2058 
   2059 #endif
   2060 #if defined(BCM_88690_B0)
   2061 soc_field_info_t soc_U1_M0SS_ECC_STATUS_BCM88690_B0r_fields[] = {
   2062     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   2063     { ECC_ERRf, 1, 0, 0 },
   2064     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   2065     { MULTIPLE_ERRf, 1, 1, 0 }
   2066 };
   2067 
   2068 #endif
   2069 #if defined(BCM_88790_A0)
   2070 soc_field_info_t soc_U1_M0SS_ECOr_fields[] = {
   2071     { REV_NUMf, 20, 0, SOCF_LE }
   2072 };
   2073 
   2074 #endif
   2075 #if defined(BCM_88690_A0)
   2076 soc_field_info_t soc_U1_M0SS_ECO_BCM88690_A0r_fields[] = {
   2077     { REV_NUMf, 20, 0, SOCF_LE }
   2078 };
   2079 
   2080 #endif
   2081 #if defined(BCM_88690_B0)
   2082 soc_field_info_t soc_U1_M0SS_ECO_BCM88690_B0r_fields[] = {
   2083     { REV_NUMf, 20, 0, SOCF_LE }
   2084 };
   2085 
   2086 #endif
   2087 #if defined(BCM_88790_A0)
   2088 soc_field_info_t soc_U1_M0SS_INTR_127_96r_fields[] = {
   2089     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2090 };
   2091 
   2092 #endif
   2093 #if defined(BCM_88690_A0)
   2094 soc_field_info_t soc_U1_M0SS_INTR_127_96_BCM88690_A0r_fields[] = {
   2095     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2096 };
   2097 
   2098 #endif
   2099 #if defined(BCM_88690_B0)
   2100 soc_field_info_t soc_U1_M0SS_INTR_127_96_BCM88690_B0r_fields[] = {
   2101     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2102 };
   2103 
   2104 #endif
   2105 #if defined(BCM_88790_A0)
   2106 soc_field_info_t soc_U1_M0SS_INTR_159_128r_fields[] = {
   2107     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2108 };
   2109 
   2110 #endif
   2111 #if defined(BCM_88690_A0)
   2112 soc_field_info_t soc_U1_M0SS_INTR_159_128_BCM88690_A0r_fields[] = {
   2113     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2114 };
   2115 
   2116 #endif
   2117 #if defined(BCM_88690_B0)
   2118 soc_field_info_t soc_U1_M0SS_INTR_159_128_BCM88690_B0r_fields[] = {
   2119     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2120 };
   2121 
   2122 #endif
   2123 #if defined(BCM_88790_A0)
   2124 soc_field_info_t soc_U1_M0SS_INTR_191_160r_fields[] = {
   2125     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2126 };
   2127 
   2128 #endif
   2129 #if defined(BCM_88690_A0)
   2130 soc_field_info_t soc_U1_M0SS_INTR_191_160_BCM88690_A0r_fields[] = {
   2131     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2132 };
   2133 
   2134 #endif
   2135 #if defined(BCM_88690_B0)
   2136 soc_field_info_t soc_U1_M0SS_INTR_191_160_BCM88690_B0r_fields[] = {
   2137     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2138 };
   2139 
   2140 #endif
   2141 #if defined(BCM_88790_A0)
   2142 soc_field_info_t soc_U1_M0SS_INTR_223_192r_fields[] = {
   2143     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2144 };
   2145 
   2146 #endif
   2147 #if defined(BCM_88690_A0)
   2148 soc_field_info_t soc_U1_M0SS_INTR_223_192_BCM88690_A0r_fields[] = {
   2149     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2150 };
   2151 
   2152 #endif
   2153 #if defined(BCM_88690_B0)
   2154 soc_field_info_t soc_U1_M0SS_INTR_223_192_BCM88690_B0r_fields[] = {
   2155     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2156 };
   2157 
   2158 #endif
   2159 #if defined(BCM_88790_A0)
   2160 soc_field_info_t soc_U1_M0SS_INTR_255_224r_fields[] = {
   2161     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2162 };
   2163 
   2164 #endif
   2165 #if defined(BCM_88690_A0)
   2166 soc_field_info_t soc_U1_M0SS_INTR_255_224_BCM88690_A0r_fields[] = {
   2167     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2168 };
   2169 
   2170 #endif
   2171 #if defined(BCM_88690_B0)
   2172 soc_field_info_t soc_U1_M0SS_INTR_255_224_BCM88690_B0r_fields[] = {
   2173     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2174 };
   2175 
   2176 #endif
   2177 #if defined(BCM_88790_A0)
   2178 soc_field_info_t soc_U1_M0SS_INTR_31_0r_fields[] = {
   2179     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2180 };
   2181 
   2182 #endif
   2183 #if defined(BCM_88690_A0)
   2184 soc_field_info_t soc_U1_M0SS_INTR_31_0_BCM88690_A0r_fields[] = {
   2185     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2186 };
   2187 
   2188 #endif
   2189 #if defined(BCM_88690_B0)
   2190 soc_field_info_t soc_U1_M0SS_INTR_31_0_BCM88690_B0r_fields[] = {
   2191     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2192 };
   2193 
   2194 #endif
   2195 #if defined(BCM_88790_A0)
   2196 soc_field_info_t soc_U1_M0SS_INTR_63_32r_fields[] = {
   2197     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2198 };
   2199 
   2200 #endif
   2201 #if defined(BCM_88690_A0)
   2202 soc_field_info_t soc_U1_M0SS_INTR_63_32_BCM88690_A0r_fields[] = {
   2203     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2204 };
   2205 
   2206 #endif
   2207 #if defined(BCM_88690_B0)
   2208 soc_field_info_t soc_U1_M0SS_INTR_63_32_BCM88690_B0r_fields[] = {
   2209     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2210 };
   2211 
   2212 #endif
   2213 #if defined(BCM_88790_A0)
   2214 soc_field_info_t soc_U1_M0SS_INTR_95_64r_fields[] = {
   2215     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2216 };
   2217 
   2218 #endif
   2219 #if defined(BCM_88690_A0)
   2220 soc_field_info_t soc_U1_M0SS_INTR_95_64_BCM88690_A0r_fields[] = {
   2221     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2222 };
   2223 
   2224 #endif
   2225 #if defined(BCM_88690_B0)
   2226 soc_field_info_t soc_U1_M0SS_INTR_95_64_BCM88690_B0r_fields[] = {
   2227     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2228 };
   2229 
   2230 #endif
   2231 #if defined(BCM_88790_A0)
   2232 soc_field_info_t soc_U1_M0SS_INTR_CONTROLr_fields[] = {
   2233     { IRQLATENCYf, 8, 0, SOCF_LE },
   2234     { SLEEPHOLDREQNf, 1, 8, 0 },
   2235     { WICENREQf, 1, 9, 0 }
   2236 };
   2237 
   2238 #endif
   2239 #if defined(BCM_88690_A0)
   2240 soc_field_info_t soc_U1_M0SS_INTR_CONTROL_BCM88690_A0r_fields[] = {
   2241     { IRQLATENCYf, 8, 0, SOCF_LE },
   2242     { SLEEPHOLDREQNf, 1, 8, 0 },
   2243     { WICENREQf, 1, 9, 0 }
   2244 };
   2245 
   2246 #endif
   2247 #if defined(BCM_88690_B0)
   2248 soc_field_info_t soc_U1_M0SS_INTR_CONTROL_BCM88690_B0r_fields[] = {
   2249     { IRQLATENCYf, 8, 0, SOCF_LE },
   2250     { SLEEPHOLDREQNf, 1, 8, 0 },
   2251     { WICENREQf, 1, 9, 0 }
   2252 };
   2253 
   2254 #endif
   2255 #if defined(BCM_88790_A0)
   2256 soc_field_info_t soc_U1_M0SS_INTR_ENABLEr_fields[] = {
   2257     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   2258     { SINGLE_BIT_ERRf, 1, 0, 0 }
   2259 };
   2260 
   2261 #endif
   2262 #if defined(BCM_88690_A0)
   2263 soc_field_info_t soc_U1_M0SS_INTR_ENABLE_BCM88690_A0r_fields[] = {
   2264     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   2265     { SINGLE_BIT_ERRf, 1, 0, 0 }
   2266 };
   2267 
   2268 #endif
   2269 #if defined(BCM_88690_B0)
   2270 soc_field_info_t soc_U1_M0SS_INTR_ENABLE_BCM88690_B0r_fields[] = {
   2271     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   2272     { SINGLE_BIT_ERRf, 1, 0, 0 }
   2273 };
   2274 
   2275 #endif
   2276 #if defined(BCM_88790_A0)
   2277 soc_field_info_t soc_U1_M0SS_INTR_MASK_127_96r_fields[] = {
   2278     { CNFGf, 32, 0, SOCF_LE }
   2279 };
   2280 
   2281 #endif
   2282 #if defined(BCM_88690_A0)
   2283 soc_field_info_t soc_U1_M0SS_INTR_MASK_127_96_BCM88690_A0r_fields[] = {
   2284     { CNFGf, 32, 0, SOCF_LE }
   2285 };
   2286 
   2287 #endif
   2288 #if defined(BCM_88690_B0)
   2289 soc_field_info_t soc_U1_M0SS_INTR_MASK_127_96_BCM88690_B0r_fields[] = {
   2290     { CNFGf, 32, 0, SOCF_LE }
   2291 };
   2292 
   2293 #endif
   2294 #if defined(BCM_88790_A0)
   2295 soc_field_info_t soc_U1_M0SS_INTR_MASK_159_128r_fields[] = {
   2296     { CNFGf, 32, 0, SOCF_LE }
   2297 };
   2298 
   2299 #endif
   2300 #if defined(BCM_88690_A0)
   2301 soc_field_info_t soc_U1_M0SS_INTR_MASK_159_128_BCM88690_A0r_fields[] = {
   2302     { CNFGf, 32, 0, SOCF_LE }
   2303 };
   2304 
   2305 #endif
   2306 #if defined(BCM_88690_B0)
   2307 soc_field_info_t soc_U1_M0SS_INTR_MASK_159_128_BCM88690_B0r_fields[] = {
   2308     { CNFGf, 32, 0, SOCF_LE }
   2309 };
   2310 
   2311 #endif
   2312 #if defined(BCM_88790_A0)
   2313 soc_field_info_t soc_U1_M0SS_INTR_MASK_191_160r_fields[] = {
   2314     { CNFGf, 32, 0, SOCF_LE }
   2315 };
   2316 
   2317 #endif
   2318 #if defined(BCM_88690_A0)
   2319 soc_field_info_t soc_U1_M0SS_INTR_MASK_191_160_BCM88690_A0r_fields[] = {
   2320     { CNFGf, 32, 0, SOCF_LE }
   2321 };
   2322 
   2323 #endif
   2324 #if defined(BCM_88690_B0)
   2325 soc_field_info_t soc_U1_M0SS_INTR_MASK_191_160_BCM88690_B0r_fields[] = {
   2326     { CNFGf, 32, 0, SOCF_LE }
   2327 };
   2328 
   2329 #endif
   2330 #if defined(BCM_88790_A0)
   2331 soc_field_info_t soc_U1_M0SS_INTR_MASK_223_192r_fields[] = {
   2332     { CNFGf, 32, 0, SOCF_LE }
   2333 };
   2334 
   2335 #endif
   2336 #if defined(BCM_88690_A0)
   2337 soc_field_info_t soc_U1_M0SS_INTR_MASK_223_192_BCM88690_A0r_fields[] = {
   2338     { CNFGf, 32, 0, SOCF_LE }
   2339 };
   2340 
   2341 #endif
   2342 #if defined(BCM_88690_B0)
   2343 soc_field_info_t soc_U1_M0SS_INTR_MASK_223_192_BCM88690_B0r_fields[] = {
   2344     { CNFGf, 32, 0, SOCF_LE }
   2345 };
   2346 
   2347 #endif
   2348 #if defined(BCM_88790_A0)
   2349 soc_field_info_t soc_U1_M0SS_INTR_MASK_255_224r_fields[] = {
   2350     { CNFGf, 32, 0, SOCF_LE }
   2351 };
   2352 
   2353 #endif
   2354 #if defined(BCM_88690_A0)
   2355 soc_field_info_t soc_U1_M0SS_INTR_MASK_255_224_BCM88690_A0r_fields[] = {
   2356     { CNFGf, 32, 0, SOCF_LE }
   2357 };
   2358 
   2359 #endif
   2360 #if defined(BCM_88690_B0)
   2361 soc_field_info_t soc_U1_M0SS_INTR_MASK_255_224_BCM88690_B0r_fields[] = {
   2362     { CNFGf, 32, 0, SOCF_LE }
   2363 };
   2364 
   2365 #endif
   2366 #if defined(BCM_88790_A0)
   2367 soc_field_info_t soc_U1_M0SS_INTR_MASK_31_0r_fields[] = {
   2368     { CNFGf, 32, 0, SOCF_LE }
   2369 };
   2370 
   2371 #endif
   2372 #if defined(BCM_88690_A0)
   2373 soc_field_info_t soc_U1_M0SS_INTR_MASK_31_0_BCM88690_A0r_fields[] = {
   2374     { CNFGf, 32, 0, SOCF_LE }
   2375 };
   2376 
   2377 #endif
   2378 #if defined(BCM_88690_B0)
   2379 soc_field_info_t soc_U1_M0SS_INTR_MASK_31_0_BCM88690_B0r_fields[] = {
   2380     { CNFGf, 32, 0, SOCF_LE }
   2381 };
   2382 
   2383 #endif
   2384 #if defined(BCM_88790_A0)
   2385 soc_field_info_t soc_U1_M0SS_INTR_MASK_63_32r_fields[] = {
   2386     { CNFGf, 32, 0, SOCF_LE }
   2387 };
   2388 
   2389 #endif
   2390 #if defined(BCM_88690_A0)
   2391 soc_field_info_t soc_U1_M0SS_INTR_MASK_63_32_BCM88690_A0r_fields[] = {
   2392     { CNFGf, 32, 0, SOCF_LE }
   2393 };
   2394 
   2395 #endif
   2396 #if defined(BCM_88690_B0)
   2397 soc_field_info_t soc_U1_M0SS_INTR_MASK_63_32_BCM88690_B0r_fields[] = {
   2398     { CNFGf, 32, 0, SOCF_LE }
   2399 };
   2400 
   2401 #endif
   2402 #if defined(BCM_88790_A0)
   2403 soc_field_info_t soc_U1_M0SS_INTR_MASK_95_64r_fields[] = {
   2404     { CNFGf, 32, 0, SOCF_LE }
   2405 };
   2406 
   2407 #endif
   2408 #if defined(BCM_88690_A0)
   2409 soc_field_info_t soc_U1_M0SS_INTR_MASK_95_64_BCM88690_A0r_fields[] = {
   2410     { CNFGf, 32, 0, SOCF_LE }
   2411 };
   2412 
   2413 #endif
   2414 #if defined(BCM_88690_B0)
   2415 soc_field_info_t soc_U1_M0SS_INTR_MASK_95_64_BCM88690_B0r_fields[] = {
   2416     { CNFGf, 32, 0, SOCF_LE }
   2417 };
   2418 
   2419 #endif
   2420 #if defined(BCM_88790_A0)
   2421 soc_field_info_t soc_U1_M0SS_RAW_INTR_127_96r_fields[] = {
   2422     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2423 };
   2424 
   2425 #endif
   2426 #if defined(BCM_88690_A0)
   2427 soc_field_info_t soc_U1_M0SS_RAW_INTR_127_96_BCM88690_A0r_fields[] = {
   2428     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2429 };
   2430 
   2431 #endif
   2432 #if defined(BCM_88690_B0)
   2433 soc_field_info_t soc_U1_M0SS_RAW_INTR_127_96_BCM88690_B0r_fields[] = {
   2434     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2435 };
   2436 
   2437 #endif
   2438 #if defined(BCM_88790_A0)
   2439 soc_field_info_t soc_U1_M0SS_RAW_INTR_159_128r_fields[] = {
   2440     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2441 };
   2442 
   2443 #endif
   2444 #if defined(BCM_88690_A0)
   2445 soc_field_info_t soc_U1_M0SS_RAW_INTR_159_128_BCM88690_A0r_fields[] = {
   2446     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2447 };
   2448 
   2449 #endif
   2450 #if defined(BCM_88690_B0)
   2451 soc_field_info_t soc_U1_M0SS_RAW_INTR_159_128_BCM88690_B0r_fields[] = {
   2452     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2453 };
   2454 
   2455 #endif
   2456 #if defined(BCM_88790_A0)
   2457 soc_field_info_t soc_U1_M0SS_RAW_INTR_191_160r_fields[] = {
   2458     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2459 };
   2460 
   2461 #endif
   2462 #if defined(BCM_88690_A0)
   2463 soc_field_info_t soc_U1_M0SS_RAW_INTR_191_160_BCM88690_A0r_fields[] = {
   2464     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2465 };
   2466 
   2467 #endif
   2468 #if defined(BCM_88690_B0)
   2469 soc_field_info_t soc_U1_M0SS_RAW_INTR_191_160_BCM88690_B0r_fields[] = {
   2470     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2471 };
   2472 
   2473 #endif
   2474 #if defined(BCM_88790_A0)
   2475 soc_field_info_t soc_U1_M0SS_RAW_INTR_223_192r_fields[] = {
   2476     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2477 };
   2478 
   2479 #endif
   2480 #if defined(BCM_88690_A0)
   2481 soc_field_info_t soc_U1_M0SS_RAW_INTR_223_192_BCM88690_A0r_fields[] = {
   2482     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2483 };
   2484 
   2485 #endif
   2486 #if defined(BCM_88690_B0)
   2487 soc_field_info_t soc_U1_M0SS_RAW_INTR_223_192_BCM88690_B0r_fields[] = {
   2488     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2489 };
   2490 
   2491 #endif
   2492 #if defined(BCM_88790_A0)
   2493 soc_field_info_t soc_U1_M0SS_RAW_INTR_255_224r_fields[] = {
   2494     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2495 };
   2496 
   2497 #endif
   2498 #if defined(BCM_88690_A0)
   2499 soc_field_info_t soc_U1_M0SS_RAW_INTR_255_224_BCM88690_A0r_fields[] = {
   2500     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2501 };
   2502 
   2503 #endif
   2504 #if defined(BCM_88690_B0)
   2505 soc_field_info_t soc_U1_M0SS_RAW_INTR_255_224_BCM88690_B0r_fields[] = {
   2506     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2507 };
   2508 
   2509 #endif
   2510 #if defined(BCM_88790_A0)
   2511 soc_field_info_t soc_U1_M0SS_RAW_INTR_31_0r_fields[] = {
   2512     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2513 };
   2514 
   2515 #endif
   2516 #if defined(BCM_88690_A0)
   2517 soc_field_info_t soc_U1_M0SS_RAW_INTR_31_0_BCM88690_A0r_fields[] = {
   2518     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2519 };
   2520 
   2521 #endif
   2522 #if defined(BCM_88690_B0)
   2523 soc_field_info_t soc_U1_M0SS_RAW_INTR_31_0_BCM88690_B0r_fields[] = {
   2524     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2525 };
   2526 
   2527 #endif
   2528 #if defined(BCM_88790_A0)
   2529 soc_field_info_t soc_U1_M0SS_RAW_INTR_63_32r_fields[] = {
   2530     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2531 };
   2532 
   2533 #endif
   2534 #if defined(BCM_88690_A0)
   2535 soc_field_info_t soc_U1_M0SS_RAW_INTR_63_32_BCM88690_A0r_fields[] = {
   2536     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2537 };
   2538 
   2539 #endif
   2540 #if defined(BCM_88690_B0)
   2541 soc_field_info_t soc_U1_M0SS_RAW_INTR_63_32_BCM88690_B0r_fields[] = {
   2542     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2543 };
   2544 
   2545 #endif
   2546 #if defined(BCM_88790_A0)
   2547 soc_field_info_t soc_U1_M0SS_RAW_INTR_95_64r_fields[] = {
   2548     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2549 };
   2550 
   2551 #endif
   2552 #if defined(BCM_88690_A0)
   2553 soc_field_info_t soc_U1_M0SS_RAW_INTR_95_64_BCM88690_A0r_fields[] = {
   2554     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2555 };
   2556 
   2557 #endif
   2558 #if defined(BCM_88690_B0)
   2559 soc_field_info_t soc_U1_M0SS_RAW_INTR_95_64_BCM88690_B0r_fields[] = {
   2560     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2561 };
   2562 
   2563 #endif
   2564 #if defined(BCM_88790_A0)
   2565 soc_field_info_t soc_U1_M0SS_STATUSr_fields[] = {
   2566     { DBGRESTARTEDf, 1, 0, 0 },
   2567     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   2568     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   2569     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   2570     { SLEEPHOLDACKf, 1, 2, 0 },
   2571     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   2572     { SYSRESETREQf, 1, 1, 0 },
   2573     { TXEVf, 16, 16, SOCF_LE },
   2574     { WAKEUPf, 1, 4, 0 },
   2575     { WICENACKf, 1, 3, 0 }
   2576 };
   2577 
   2578 #endif
   2579 #if defined(BCM_88690_A0)
   2580 soc_field_info_t soc_U1_M0SS_STATUS_BCM88690_A0r_fields[] = {
   2581     { DBGRESTARTEDf, 1, 0, 0 },
   2582     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   2583     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   2584     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   2585     { SLEEPHOLDACKf, 1, 2, 0 },
   2586     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   2587     { SYSRESETREQf, 1, 1, 0 },
   2588     { TXEVf, 16, 16, SOCF_LE },
   2589     { WAKEUPf, 1, 4, 0 },
   2590     { WICENACKf, 1, 3, 0 }
   2591 };
   2592 
   2593 #endif
   2594 #if defined(BCM_88690_B0)
   2595 soc_field_info_t soc_U1_M0SS_STATUS_BCM88690_B0r_fields[] = {
   2596     { DBGRESTARTEDf, 1, 0, 0 },
   2597     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   2598     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   2599     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   2600     { SLEEPHOLDACKf, 1, 2, 0 },
   2601     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   2602     { SYSRESETREQf, 1, 1, 0 },
   2603     { TXEVf, 16, 16, SOCF_LE },
   2604     { WAKEUPf, 1, 4, 0 },
   2605     { WICENACKf, 1, 3, 0 }
   2606 };
   2607 
   2608 #endif
   2609 #if defined(BCM_88790_A0)
   2610 soc_field_info_t soc_U1_M0SS_TCM_CTRLr_fields[] = {
   2611     { TCM_TMf, 7, 0, SOCF_LE }
   2612 };
   2613 
   2614 #endif
   2615 #if defined(BCM_88690_A0)
   2616 soc_field_info_t soc_U1_M0SS_TCM_CTRL_BCM88690_A0r_fields[] = {
   2617     { TCM_TMf, 7, 0, SOCF_LE }
   2618 };
   2619 
   2620 #endif
   2621 #if defined(BCM_88690_B0)
   2622 soc_field_info_t soc_U1_M0SS_TCM_CTRL_BCM88690_B0r_fields[] = {
   2623     { TCM_TMf, 7, 0, SOCF_LE }
   2624 };
   2625 
   2626 #endif
   2627 #if defined(BCM_88790_A0)
   2628 soc_field_info_t soc_U2_M0SS_CONTROLr_fields[] = {
   2629     { SOFT_RESETf, 1, 0, 0 },
   2630     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   2631     { SYS_TICK_CLKENf, 1, 1, 0 }
   2632 };
   2633 
   2634 #endif
   2635 #if defined(BCM_88690_A0)
   2636 soc_field_info_t soc_U2_M0SS_CONTROL_BCM88690_A0r_fields[] = {
   2637     { SOFT_RESETf, 1, 0, 0 },
   2638     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   2639     { SYS_TICK_CLKENf, 1, 1, 0 }
   2640 };
   2641 
   2642 #endif
   2643 #if defined(BCM_88690_B0)
   2644 soc_field_info_t soc_U2_M0SS_CONTROL_BCM88690_B0r_fields[] = {
   2645     { SOFT_RESETf, 1, 0, 0 },
   2646     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   2647     { SYS_TICK_CLKENf, 1, 1, 0 }
   2648 };
   2649 
   2650 #endif
   2651 #if defined(BCM_88790_A0)
   2652 soc_field_info_t soc_U2_M0SS_DEBUG_CONTROLr_fields[] = {
   2653     { DBGRESTARTf, 1, 1, 0 },
   2654     { EDBGRQf, 1, 0, 0 }
   2655 };
   2656 
   2657 #endif
   2658 #if defined(BCM_88690_A0)
   2659 soc_field_info_t soc_U2_M0SS_DEBUG_CONTROL_BCM88690_A0r_fields[] = {
   2660     { DBGRESTARTf, 1, 1, 0 },
   2661     { EDBGRQf, 1, 0, 0 }
   2662 };
   2663 
   2664 #endif
   2665 #if defined(BCM_88690_B0)
   2666 soc_field_info_t soc_U2_M0SS_DEBUG_CONTROL_BCM88690_B0r_fields[] = {
   2667     { DBGRESTARTf, 1, 1, 0 },
   2668     { EDBGRQf, 1, 0, 0 }
   2669 };
   2670 
   2671 #endif
   2672 #if defined(BCM_88790_A0)
   2673 soc_field_info_t soc_U2_M0SS_ECC_CTRLr_fields[] = {
   2674     { TCM_ECC_ENf, 1, 0, 0 },
   2675     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   2676     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   2677 };
   2678 
   2679 #endif
   2680 #if defined(BCM_88690_A0)
   2681 soc_field_info_t soc_U2_M0SS_ECC_CTRL_BCM88690_A0r_fields[] = {
   2682     { TCM_ECC_ENf, 1, 0, 0 },
   2683     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   2684     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   2685 };
   2686 
   2687 #endif
   2688 #if defined(BCM_88690_B0)
   2689 soc_field_info_t soc_U2_M0SS_ECC_CTRL_BCM88690_B0r_fields[] = {
   2690     { TCM_ECC_ENf, 1, 0, 0 },
   2691     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   2692     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   2693 };
   2694 
   2695 #endif
   2696 #if defined(BCM_88790_A0)
   2697 soc_field_info_t soc_U2_M0SS_ECC_STATUSr_fields[] = {
   2698     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   2699     { ECC_ERRf, 1, 0, 0 },
   2700     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   2701     { MULTIPLE_ERRf, 1, 1, 0 }
   2702 };
   2703 
   2704 #endif
   2705 #if defined(BCM_88690_A0)
   2706 soc_field_info_t soc_U2_M0SS_ECC_STATUS_BCM88690_A0r_fields[] = {
   2707     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   2708     { ECC_ERRf, 1, 0, 0 },
   2709     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   2710     { MULTIPLE_ERRf, 1, 1, 0 }
   2711 };
   2712 
   2713 #endif
   2714 #if defined(BCM_88690_B0)
   2715 soc_field_info_t soc_U2_M0SS_ECC_STATUS_BCM88690_B0r_fields[] = {
   2716     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   2717     { ECC_ERRf, 1, 0, 0 },
   2718     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   2719     { MULTIPLE_ERRf, 1, 1, 0 }
   2720 };
   2721 
   2722 #endif
   2723 #if defined(BCM_88790_A0)
   2724 soc_field_info_t soc_U2_M0SS_ECOr_fields[] = {
   2725     { REV_NUMf, 20, 0, SOCF_LE }
   2726 };
   2727 
   2728 #endif
   2729 #if defined(BCM_88690_A0)
   2730 soc_field_info_t soc_U2_M0SS_ECO_BCM88690_A0r_fields[] = {
   2731     { REV_NUMf, 20, 0, SOCF_LE }
   2732 };
   2733 
   2734 #endif
   2735 #if defined(BCM_88690_B0)
   2736 soc_field_info_t soc_U2_M0SS_ECO_BCM88690_B0r_fields[] = {
   2737     { REV_NUMf, 20, 0, SOCF_LE }
   2738 };
   2739 
   2740 #endif
   2741 #if defined(BCM_88790_A0)
   2742 soc_field_info_t soc_U2_M0SS_INTR_127_96r_fields[] = {
   2743     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2744 };
   2745 
   2746 #endif
   2747 #if defined(BCM_88690_A0)
   2748 soc_field_info_t soc_U2_M0SS_INTR_127_96_BCM88690_A0r_fields[] = {
   2749     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2750 };
   2751 
   2752 #endif
   2753 #if defined(BCM_88690_B0)
   2754 soc_field_info_t soc_U2_M0SS_INTR_127_96_BCM88690_B0r_fields[] = {
   2755     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2756 };
   2757 
   2758 #endif
   2759 #if defined(BCM_88790_A0)
   2760 soc_field_info_t soc_U2_M0SS_INTR_159_128r_fields[] = {
   2761     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2762 };
   2763 
   2764 #endif
   2765 #if defined(BCM_88690_A0)
   2766 soc_field_info_t soc_U2_M0SS_INTR_159_128_BCM88690_A0r_fields[] = {
   2767     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2768 };
   2769 
   2770 #endif
   2771 #if defined(BCM_88690_B0)
   2772 soc_field_info_t soc_U2_M0SS_INTR_159_128_BCM88690_B0r_fields[] = {
   2773     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2774 };
   2775 
   2776 #endif
   2777 #if defined(BCM_88790_A0)
   2778 soc_field_info_t soc_U2_M0SS_INTR_191_160r_fields[] = {
   2779     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2780 };
   2781 
   2782 #endif
   2783 #if defined(BCM_88690_A0)
   2784 soc_field_info_t soc_U2_M0SS_INTR_191_160_BCM88690_A0r_fields[] = {
   2785     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2786 };
   2787 
   2788 #endif
   2789 #if defined(BCM_88690_B0)
   2790 soc_field_info_t soc_U2_M0SS_INTR_191_160_BCM88690_B0r_fields[] = {
   2791     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2792 };
   2793 
   2794 #endif
   2795 #if defined(BCM_88790_A0)
   2796 soc_field_info_t soc_U2_M0SS_INTR_223_192r_fields[] = {
   2797     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2798 };
   2799 
   2800 #endif
   2801 #if defined(BCM_88690_A0)
   2802 soc_field_info_t soc_U2_M0SS_INTR_223_192_BCM88690_A0r_fields[] = {
   2803     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2804 };
   2805 
   2806 #endif
   2807 #if defined(BCM_88690_B0)
   2808 soc_field_info_t soc_U2_M0SS_INTR_223_192_BCM88690_B0r_fields[] = {
   2809     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2810 };
   2811 
   2812 #endif
   2813 #if defined(BCM_88790_A0)
   2814 soc_field_info_t soc_U2_M0SS_INTR_255_224r_fields[] = {
   2815     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2816 };
   2817 
   2818 #endif
   2819 #if defined(BCM_88690_A0)
   2820 soc_field_info_t soc_U2_M0SS_INTR_255_224_BCM88690_A0r_fields[] = {
   2821     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2822 };
   2823 
   2824 #endif
   2825 #if defined(BCM_88690_B0)
   2826 soc_field_info_t soc_U2_M0SS_INTR_255_224_BCM88690_B0r_fields[] = {
   2827     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2828 };
   2829 
   2830 #endif
   2831 #if defined(BCM_88790_A0)
   2832 soc_field_info_t soc_U2_M0SS_INTR_31_0r_fields[] = {
   2833     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2834 };
   2835 
   2836 #endif
   2837 #if defined(BCM_88690_A0)
   2838 soc_field_info_t soc_U2_M0SS_INTR_31_0_BCM88690_A0r_fields[] = {
   2839     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2840 };
   2841 
   2842 #endif
   2843 #if defined(BCM_88690_B0)
   2844 soc_field_info_t soc_U2_M0SS_INTR_31_0_BCM88690_B0r_fields[] = {
   2845     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2846 };
   2847 
   2848 #endif
   2849 #if defined(BCM_88790_A0)
   2850 soc_field_info_t soc_U2_M0SS_INTR_63_32r_fields[] = {
   2851     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2852 };
   2853 
   2854 #endif
   2855 #if defined(BCM_88690_A0)
   2856 soc_field_info_t soc_U2_M0SS_INTR_63_32_BCM88690_A0r_fields[] = {
   2857     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2858 };
   2859 
   2860 #endif
   2861 #if defined(BCM_88690_B0)
   2862 soc_field_info_t soc_U2_M0SS_INTR_63_32_BCM88690_B0r_fields[] = {
   2863     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2864 };
   2865 
   2866 #endif
   2867 #if defined(BCM_88790_A0)
   2868 soc_field_info_t soc_U2_M0SS_INTR_95_64r_fields[] = {
   2869     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2870 };
   2871 
   2872 #endif
   2873 #if defined(BCM_88690_A0)
   2874 soc_field_info_t soc_U2_M0SS_INTR_95_64_BCM88690_A0r_fields[] = {
   2875     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2876 };
   2877 
   2878 #endif
   2879 #if defined(BCM_88690_B0)
   2880 soc_field_info_t soc_U2_M0SS_INTR_95_64_BCM88690_B0r_fields[] = {
   2881     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   2882 };
   2883 
   2884 #endif
   2885 #if defined(BCM_88790_A0)
   2886 soc_field_info_t soc_U2_M0SS_INTR_CONTROLr_fields[] = {
   2887     { IRQLATENCYf, 8, 0, SOCF_LE },
   2888     { SLEEPHOLDREQNf, 1, 8, 0 },
   2889     { WICENREQf, 1, 9, 0 }
   2890 };
   2891 
   2892 #endif
   2893 #if defined(BCM_88690_A0)
   2894 soc_field_info_t soc_U2_M0SS_INTR_CONTROL_BCM88690_A0r_fields[] = {
   2895     { IRQLATENCYf, 8, 0, SOCF_LE },
   2896     { SLEEPHOLDREQNf, 1, 8, 0 },
   2897     { WICENREQf, 1, 9, 0 }
   2898 };
   2899 
   2900 #endif
   2901 #if defined(BCM_88690_B0)
   2902 soc_field_info_t soc_U2_M0SS_INTR_CONTROL_BCM88690_B0r_fields[] = {
   2903     { IRQLATENCYf, 8, 0, SOCF_LE },
   2904     { SLEEPHOLDREQNf, 1, 8, 0 },
   2905     { WICENREQf, 1, 9, 0 }
   2906 };
   2907 
   2908 #endif
   2909 #if defined(BCM_88790_A0)
   2910 soc_field_info_t soc_U2_M0SS_INTR_ENABLEr_fields[] = {
   2911     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   2912     { SINGLE_BIT_ERRf, 1, 0, 0 }
   2913 };
   2914 
   2915 #endif
   2916 #if defined(BCM_88690_A0)
   2917 soc_field_info_t soc_U2_M0SS_INTR_ENABLE_BCM88690_A0r_fields[] = {
   2918     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   2919     { SINGLE_BIT_ERRf, 1, 0, 0 }
   2920 };
   2921 
   2922 #endif
   2923 #if defined(BCM_88690_B0)
   2924 soc_field_info_t soc_U2_M0SS_INTR_ENABLE_BCM88690_B0r_fields[] = {
   2925     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   2926     { SINGLE_BIT_ERRf, 1, 0, 0 }
   2927 };
   2928 
   2929 #endif
   2930 #if defined(BCM_88790_A0)
   2931 soc_field_info_t soc_U2_M0SS_INTR_MASK_127_96r_fields[] = {
   2932     { CNFGf, 32, 0, SOCF_LE }
   2933 };
   2934 
   2935 #endif
   2936 #if defined(BCM_88690_A0)
   2937 soc_field_info_t soc_U2_M0SS_INTR_MASK_127_96_BCM88690_A0r_fields[] = {
   2938     { CNFGf, 32, 0, SOCF_LE }
   2939 };
   2940 
   2941 #endif
   2942 #if defined(BCM_88690_B0)
   2943 soc_field_info_t soc_U2_M0SS_INTR_MASK_127_96_BCM88690_B0r_fields[] = {
   2944     { CNFGf, 32, 0, SOCF_LE }
   2945 };
   2946 
   2947 #endif
   2948 #if defined(BCM_88790_A0)
   2949 soc_field_info_t soc_U2_M0SS_INTR_MASK_159_128r_fields[] = {
   2950     { CNFGf, 32, 0, SOCF_LE }
   2951 };
   2952 
   2953 #endif
   2954 #if defined(BCM_88690_A0)
   2955 soc_field_info_t soc_U2_M0SS_INTR_MASK_159_128_BCM88690_A0r_fields[] = {
   2956     { CNFGf, 32, 0, SOCF_LE }
   2957 };
   2958 
   2959 #endif
   2960 #if defined(BCM_88690_B0)
   2961 soc_field_info_t soc_U2_M0SS_INTR_MASK_159_128_BCM88690_B0r_fields[] = {
   2962     { CNFGf, 32, 0, SOCF_LE }
   2963 };
   2964 
   2965 #endif
   2966 #if defined(BCM_88790_A0)
   2967 soc_field_info_t soc_U2_M0SS_INTR_MASK_191_160r_fields[] = {
   2968     { CNFGf, 32, 0, SOCF_LE }
   2969 };
   2970 
   2971 #endif
   2972 #if defined(BCM_88690_A0)
   2973 soc_field_info_t soc_U2_M0SS_INTR_MASK_191_160_BCM88690_A0r_fields[] = {
   2974     { CNFGf, 32, 0, SOCF_LE }
   2975 };
   2976 
   2977 #endif
   2978 #if defined(BCM_88690_B0)
   2979 soc_field_info_t soc_U2_M0SS_INTR_MASK_191_160_BCM88690_B0r_fields[] = {
   2980     { CNFGf, 32, 0, SOCF_LE }
   2981 };
   2982 
   2983 #endif
   2984 #if defined(BCM_88790_A0)
   2985 soc_field_info_t soc_U2_M0SS_INTR_MASK_223_192r_fields[] = {
   2986     { CNFGf, 32, 0, SOCF_LE }
   2987 };
   2988 
   2989 #endif
   2990 #if defined(BCM_88690_A0)
   2991 soc_field_info_t soc_U2_M0SS_INTR_MASK_223_192_BCM88690_A0r_fields[] = {
   2992     { CNFGf, 32, 0, SOCF_LE }
   2993 };
   2994 
   2995 #endif
   2996 #if defined(BCM_88690_B0)
   2997 soc_field_info_t soc_U2_M0SS_INTR_MASK_223_192_BCM88690_B0r_fields[] = {
   2998     { CNFGf, 32, 0, SOCF_LE }
   2999 };
   3000 
   3001 #endif
   3002 #if defined(BCM_88790_A0)
   3003 soc_field_info_t soc_U2_M0SS_INTR_MASK_255_224r_fields[] = {
   3004     { CNFGf, 32, 0, SOCF_LE }
   3005 };
   3006 
   3007 #endif
   3008 #if defined(BCM_88690_A0)
   3009 soc_field_info_t soc_U2_M0SS_INTR_MASK_255_224_BCM88690_A0r_fields[] = {
   3010     { CNFGf, 32, 0, SOCF_LE }
   3011 };
   3012 
   3013 #endif
   3014 #if defined(BCM_88690_B0)
   3015 soc_field_info_t soc_U2_M0SS_INTR_MASK_255_224_BCM88690_B0r_fields[] = {
   3016     { CNFGf, 32, 0, SOCF_LE }
   3017 };
   3018 
   3019 #endif
   3020 #if defined(BCM_88790_A0)
   3021 soc_field_info_t soc_U2_M0SS_INTR_MASK_31_0r_fields[] = {
   3022     { CNFGf, 32, 0, SOCF_LE }
   3023 };
   3024 
   3025 #endif
   3026 #if defined(BCM_88690_A0)
   3027 soc_field_info_t soc_U2_M0SS_INTR_MASK_31_0_BCM88690_A0r_fields[] = {
   3028     { CNFGf, 32, 0, SOCF_LE }
   3029 };
   3030 
   3031 #endif
   3032 #if defined(BCM_88690_B0)
   3033 soc_field_info_t soc_U2_M0SS_INTR_MASK_31_0_BCM88690_B0r_fields[] = {
   3034     { CNFGf, 32, 0, SOCF_LE }
   3035 };
   3036 
   3037 #endif
   3038 #if defined(BCM_88790_A0)
   3039 soc_field_info_t soc_U2_M0SS_INTR_MASK_63_32r_fields[] = {
   3040     { CNFGf, 32, 0, SOCF_LE }
   3041 };
   3042 
   3043 #endif
   3044 #if defined(BCM_88690_A0)
   3045 soc_field_info_t soc_U2_M0SS_INTR_MASK_63_32_BCM88690_A0r_fields[] = {
   3046     { CNFGf, 32, 0, SOCF_LE }
   3047 };
   3048 
   3049 #endif
   3050 #if defined(BCM_88690_B0)
   3051 soc_field_info_t soc_U2_M0SS_INTR_MASK_63_32_BCM88690_B0r_fields[] = {
   3052     { CNFGf, 32, 0, SOCF_LE }
   3053 };
   3054 
   3055 #endif
   3056 #if defined(BCM_88790_A0)
   3057 soc_field_info_t soc_U2_M0SS_INTR_MASK_95_64r_fields[] = {
   3058     { CNFGf, 32, 0, SOCF_LE }
   3059 };
   3060 
   3061 #endif
   3062 #if defined(BCM_88690_A0)
   3063 soc_field_info_t soc_U2_M0SS_INTR_MASK_95_64_BCM88690_A0r_fields[] = {
   3064     { CNFGf, 32, 0, SOCF_LE }
   3065 };
   3066 
   3067 #endif
   3068 #if defined(BCM_88690_B0)
   3069 soc_field_info_t soc_U2_M0SS_INTR_MASK_95_64_BCM88690_B0r_fields[] = {
   3070     { CNFGf, 32, 0, SOCF_LE }
   3071 };
   3072 
   3073 #endif
   3074 #if defined(BCM_88790_A0)
   3075 soc_field_info_t soc_U2_M0SS_RAW_INTR_127_96r_fields[] = {
   3076     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3077 };
   3078 
   3079 #endif
   3080 #if defined(BCM_88690_A0)
   3081 soc_field_info_t soc_U2_M0SS_RAW_INTR_127_96_BCM88690_A0r_fields[] = {
   3082     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3083 };
   3084 
   3085 #endif
   3086 #if defined(BCM_88690_B0)
   3087 soc_field_info_t soc_U2_M0SS_RAW_INTR_127_96_BCM88690_B0r_fields[] = {
   3088     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3089 };
   3090 
   3091 #endif
   3092 #if defined(BCM_88790_A0)
   3093 soc_field_info_t soc_U2_M0SS_RAW_INTR_159_128r_fields[] = {
   3094     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3095 };
   3096 
   3097 #endif
   3098 #if defined(BCM_88690_A0)
   3099 soc_field_info_t soc_U2_M0SS_RAW_INTR_159_128_BCM88690_A0r_fields[] = {
   3100     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3101 };
   3102 
   3103 #endif
   3104 #if defined(BCM_88690_B0)
   3105 soc_field_info_t soc_U2_M0SS_RAW_INTR_159_128_BCM88690_B0r_fields[] = {
   3106     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3107 };
   3108 
   3109 #endif
   3110 #if defined(BCM_88790_A0)
   3111 soc_field_info_t soc_U2_M0SS_RAW_INTR_191_160r_fields[] = {
   3112     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3113 };
   3114 
   3115 #endif
   3116 #if defined(BCM_88690_A0)
   3117 soc_field_info_t soc_U2_M0SS_RAW_INTR_191_160_BCM88690_A0r_fields[] = {
   3118     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3119 };
   3120 
   3121 #endif
   3122 #if defined(BCM_88690_B0)
   3123 soc_field_info_t soc_U2_M0SS_RAW_INTR_191_160_BCM88690_B0r_fields[] = {
   3124     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3125 };
   3126 
   3127 #endif
   3128 #if defined(BCM_88790_A0)
   3129 soc_field_info_t soc_U2_M0SS_RAW_INTR_223_192r_fields[] = {
   3130     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3131 };
   3132 
   3133 #endif
   3134 #if defined(BCM_88690_A0)
   3135 soc_field_info_t soc_U2_M0SS_RAW_INTR_223_192_BCM88690_A0r_fields[] = {
   3136     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3137 };
   3138 
   3139 #endif
   3140 #if defined(BCM_88690_B0)
   3141 soc_field_info_t soc_U2_M0SS_RAW_INTR_223_192_BCM88690_B0r_fields[] = {
   3142     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3143 };
   3144 
   3145 #endif
   3146 #if defined(BCM_88790_A0)
   3147 soc_field_info_t soc_U2_M0SS_RAW_INTR_255_224r_fields[] = {
   3148     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3149 };
   3150 
   3151 #endif
   3152 #if defined(BCM_88690_A0)
   3153 soc_field_info_t soc_U2_M0SS_RAW_INTR_255_224_BCM88690_A0r_fields[] = {
   3154     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3155 };
   3156 
   3157 #endif
   3158 #if defined(BCM_88690_B0)
   3159 soc_field_info_t soc_U2_M0SS_RAW_INTR_255_224_BCM88690_B0r_fields[] = {
   3160     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3161 };
   3162 
   3163 #endif
   3164 #if defined(BCM_88790_A0)
   3165 soc_field_info_t soc_U2_M0SS_RAW_INTR_31_0r_fields[] = {
   3166     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3167 };
   3168 
   3169 #endif
   3170 #if defined(BCM_88690_A0)
   3171 soc_field_info_t soc_U2_M0SS_RAW_INTR_31_0_BCM88690_A0r_fields[] = {
   3172     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3173 };
   3174 
   3175 #endif
   3176 #if defined(BCM_88690_B0)
   3177 soc_field_info_t soc_U2_M0SS_RAW_INTR_31_0_BCM88690_B0r_fields[] = {
   3178     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3179 };
   3180 
   3181 #endif
   3182 #if defined(BCM_88790_A0)
   3183 soc_field_info_t soc_U2_M0SS_RAW_INTR_63_32r_fields[] = {
   3184     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3185 };
   3186 
   3187 #endif
   3188 #if defined(BCM_88690_A0)
   3189 soc_field_info_t soc_U2_M0SS_RAW_INTR_63_32_BCM88690_A0r_fields[] = {
   3190     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3191 };
   3192 
   3193 #endif
   3194 #if defined(BCM_88690_B0)
   3195 soc_field_info_t soc_U2_M0SS_RAW_INTR_63_32_BCM88690_B0r_fields[] = {
   3196     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3197 };
   3198 
   3199 #endif
   3200 #if defined(BCM_88790_A0)
   3201 soc_field_info_t soc_U2_M0SS_RAW_INTR_95_64r_fields[] = {
   3202     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3203 };
   3204 
   3205 #endif
   3206 #if defined(BCM_88690_A0)
   3207 soc_field_info_t soc_U2_M0SS_RAW_INTR_95_64_BCM88690_A0r_fields[] = {
   3208     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3209 };
   3210 
   3211 #endif
   3212 #if defined(BCM_88690_B0)
   3213 soc_field_info_t soc_U2_M0SS_RAW_INTR_95_64_BCM88690_B0r_fields[] = {
   3214     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3215 };
   3216 
   3217 #endif
   3218 #if defined(BCM_88790_A0)
   3219 soc_field_info_t soc_U2_M0SS_STATUSr_fields[] = {
   3220     { DBGRESTARTEDf, 1, 0, 0 },
   3221     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   3222     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   3223     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   3224     { SLEEPHOLDACKf, 1, 2, 0 },
   3225     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   3226     { SYSRESETREQf, 1, 1, 0 },
   3227     { TXEVf, 16, 16, SOCF_LE },
   3228     { WAKEUPf, 1, 4, 0 },
   3229     { WICENACKf, 1, 3, 0 }
   3230 };
   3231 
   3232 #endif
   3233 #if defined(BCM_88690_A0)
   3234 soc_field_info_t soc_U2_M0SS_STATUS_BCM88690_A0r_fields[] = {
   3235     { DBGRESTARTEDf, 1, 0, 0 },
   3236     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   3237     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   3238     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   3239     { SLEEPHOLDACKf, 1, 2, 0 },
   3240     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   3241     { SYSRESETREQf, 1, 1, 0 },
   3242     { TXEVf, 16, 16, SOCF_LE },
   3243     { WAKEUPf, 1, 4, 0 },
   3244     { WICENACKf, 1, 3, 0 }
   3245 };
   3246 
   3247 #endif
   3248 #if defined(BCM_88690_B0)
   3249 soc_field_info_t soc_U2_M0SS_STATUS_BCM88690_B0r_fields[] = {
   3250     { DBGRESTARTEDf, 1, 0, 0 },
   3251     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   3252     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   3253     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   3254     { SLEEPHOLDACKf, 1, 2, 0 },
   3255     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   3256     { SYSRESETREQf, 1, 1, 0 },
   3257     { TXEVf, 16, 16, SOCF_LE },
   3258     { WAKEUPf, 1, 4, 0 },
   3259     { WICENACKf, 1, 3, 0 }
   3260 };
   3261 
   3262 #endif
   3263 #if defined(BCM_88790_A0)
   3264 soc_field_info_t soc_U2_M0SS_TCM_CTRLr_fields[] = {
   3265     { TCM_TMf, 7, 0, SOCF_LE }
   3266 };
   3267 
   3268 #endif
   3269 #if defined(BCM_88690_A0)
   3270 soc_field_info_t soc_U2_M0SS_TCM_CTRL_BCM88690_A0r_fields[] = {
   3271     { TCM_TMf, 7, 0, SOCF_LE }
   3272 };
   3273 
   3274 #endif
   3275 #if defined(BCM_88690_B0)
   3276 soc_field_info_t soc_U2_M0SS_TCM_CTRL_BCM88690_B0r_fields[] = {
   3277     { TCM_TMf, 7, 0, SOCF_LE }
   3278 };
   3279 
   3280 #endif
   3281 #if defined(BCM_88790_A0)
   3282 soc_field_info_t soc_U3_M0SS_CONTROLr_fields[] = {
   3283     { SOFT_RESETf, 1, 0, 0 },
   3284     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   3285     { SYS_TICK_CLKENf, 1, 1, 0 }
   3286 };
   3287 
   3288 #endif
   3289 #if defined(BCM_88690_A0)
   3290 soc_field_info_t soc_U3_M0SS_CONTROL_BCM88690_A0r_fields[] = {
   3291     { SOFT_RESETf, 1, 0, 0 },
   3292     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   3293     { SYS_TICK_CLKENf, 1, 1, 0 }
   3294 };
   3295 
   3296 #endif
   3297 #if defined(BCM_88690_B0)
   3298 soc_field_info_t soc_U3_M0SS_CONTROL_BCM88690_B0r_fields[] = {
   3299     { SOFT_RESETf, 1, 0, 0 },
   3300     { SYS_TICK_CALIBf, 26, 2, SOCF_LE },
   3301     { SYS_TICK_CLKENf, 1, 1, 0 }
   3302 };
   3303 
   3304 #endif
   3305 #if defined(BCM_88790_A0)
   3306 soc_field_info_t soc_U3_M0SS_DEBUG_CONTROLr_fields[] = {
   3307     { DBGRESTARTf, 1, 1, 0 },
   3308     { EDBGRQf, 1, 0, 0 }
   3309 };
   3310 
   3311 #endif
   3312 #if defined(BCM_88690_A0)
   3313 soc_field_info_t soc_U3_M0SS_DEBUG_CONTROL_BCM88690_A0r_fields[] = {
   3314     { DBGRESTARTf, 1, 1, 0 },
   3315     { EDBGRQf, 1, 0, 0 }
   3316 };
   3317 
   3318 #endif
   3319 #if defined(BCM_88690_B0)
   3320 soc_field_info_t soc_U3_M0SS_DEBUG_CONTROL_BCM88690_B0r_fields[] = {
   3321     { DBGRESTARTf, 1, 1, 0 },
   3322     { EDBGRQf, 1, 0, 0 }
   3323 };
   3324 
   3325 #endif
   3326 #if defined(BCM_88790_A0)
   3327 soc_field_info_t soc_U3_M0SS_ECC_CTRLr_fields[] = {
   3328     { TCM_ECC_ENf, 1, 0, 0 },
   3329     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   3330     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   3331 };
   3332 
   3333 #endif
   3334 #if defined(BCM_88690_A0)
   3335 soc_field_info_t soc_U3_M0SS_ECC_CTRL_BCM88690_A0r_fields[] = {
   3336     { TCM_ECC_ENf, 1, 0, 0 },
   3337     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   3338     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   3339 };
   3340 
   3341 #endif
   3342 #if defined(BCM_88690_B0)
   3343 soc_field_info_t soc_U3_M0SS_ECC_CTRL_BCM88690_B0r_fields[] = {
   3344     { TCM_ECC_ENf, 1, 0, 0 },
   3345     { TCM_FORCE_DOUBLE_BIT_ERRf, 1, 2, 0 },
   3346     { TCM_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 }
   3347 };
   3348 
   3349 #endif
   3350 #if defined(BCM_88790_A0)
   3351 soc_field_info_t soc_U3_M0SS_ECC_STATUSr_fields[] = {
   3352     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   3353     { ECC_ERRf, 1, 0, 0 },
   3354     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   3355     { MULTIPLE_ERRf, 1, 1, 0 }
   3356 };
   3357 
   3358 #endif
   3359 #if defined(BCM_88690_A0)
   3360 soc_field_info_t soc_U3_M0SS_ECC_STATUS_BCM88690_A0r_fields[] = {
   3361     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   3362     { ECC_ERRf, 1, 0, 0 },
   3363     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   3364     { MULTIPLE_ERRf, 1, 1, 0 }
   3365 };
   3366 
   3367 #endif
   3368 #if defined(BCM_88690_B0)
   3369 soc_field_info_t soc_U3_M0SS_ECC_STATUS_BCM88690_B0r_fields[] = {
   3370     { DOUBLE_BIT_ERRf, 1, 2, 0 },
   3371     { ECC_ERRf, 1, 0, 0 },
   3372     { ENTRY_IDXf, 13, 3, SOCF_LE|SOCF_RO|SOCF_SIG },
   3373     { MULTIPLE_ERRf, 1, 1, 0 }
   3374 };
   3375 
   3376 #endif
   3377 #if defined(BCM_88790_A0)
   3378 soc_field_info_t soc_U3_M0SS_ECOr_fields[] = {
   3379     { REV_NUMf, 20, 0, SOCF_LE }
   3380 };
   3381 
   3382 #endif
   3383 #if defined(BCM_88690_A0)
   3384 soc_field_info_t soc_U3_M0SS_ECO_BCM88690_A0r_fields[] = {
   3385     { REV_NUMf, 20, 0, SOCF_LE }
   3386 };
   3387 
   3388 #endif
   3389 #if defined(BCM_88690_B0)
   3390 soc_field_info_t soc_U3_M0SS_ECO_BCM88690_B0r_fields[] = {
   3391     { REV_NUMf, 20, 0, SOCF_LE }
   3392 };
   3393 
   3394 #endif
   3395 #if defined(BCM_88790_A0)
   3396 soc_field_info_t soc_U3_M0SS_INTR_127_96r_fields[] = {
   3397     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3398 };
   3399 
   3400 #endif
   3401 #if defined(BCM_88690_A0)
   3402 soc_field_info_t soc_U3_M0SS_INTR_127_96_BCM88690_A0r_fields[] = {
   3403     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3404 };
   3405 
   3406 #endif
   3407 #if defined(BCM_88690_B0)
   3408 soc_field_info_t soc_U3_M0SS_INTR_127_96_BCM88690_B0r_fields[] = {
   3409     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3410 };
   3411 
   3412 #endif
   3413 #if defined(BCM_88790_A0)
   3414 soc_field_info_t soc_U3_M0SS_INTR_159_128r_fields[] = {
   3415     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3416 };
   3417 
   3418 #endif
   3419 #if defined(BCM_88690_A0)
   3420 soc_field_info_t soc_U3_M0SS_INTR_159_128_BCM88690_A0r_fields[] = {
   3421     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3422 };
   3423 
   3424 #endif
   3425 #if defined(BCM_88690_B0)
   3426 soc_field_info_t soc_U3_M0SS_INTR_159_128_BCM88690_B0r_fields[] = {
   3427     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3428 };
   3429 
   3430 #endif
   3431 #if defined(BCM_88790_A0)
   3432 soc_field_info_t soc_U3_M0SS_INTR_191_160r_fields[] = {
   3433     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3434 };
   3435 
   3436 #endif
   3437 #if defined(BCM_88690_A0)
   3438 soc_field_info_t soc_U3_M0SS_INTR_191_160_BCM88690_A0r_fields[] = {
   3439     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3440 };
   3441 
   3442 #endif
   3443 #if defined(BCM_88690_B0)
   3444 soc_field_info_t soc_U3_M0SS_INTR_191_160_BCM88690_B0r_fields[] = {
   3445     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3446 };
   3447 
   3448 #endif
   3449 #if defined(BCM_88790_A0)
   3450 soc_field_info_t soc_U3_M0SS_INTR_223_192r_fields[] = {
   3451     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3452 };
   3453 
   3454 #endif
   3455 #if defined(BCM_88690_A0)
   3456 soc_field_info_t soc_U3_M0SS_INTR_223_192_BCM88690_A0r_fields[] = {
   3457     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3458 };
   3459 
   3460 #endif
   3461 #if defined(BCM_88690_B0)
   3462 soc_field_info_t soc_U3_M0SS_INTR_223_192_BCM88690_B0r_fields[] = {
   3463     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3464 };
   3465 
   3466 #endif
   3467 #if defined(BCM_88790_A0)
   3468 soc_field_info_t soc_U3_M0SS_INTR_255_224r_fields[] = {
   3469     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3470 };
   3471 
   3472 #endif
   3473 #if defined(BCM_88690_A0)
   3474 soc_field_info_t soc_U3_M0SS_INTR_255_224_BCM88690_A0r_fields[] = {
   3475     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3476 };
   3477 
   3478 #endif
   3479 #if defined(BCM_88690_B0)
   3480 soc_field_info_t soc_U3_M0SS_INTR_255_224_BCM88690_B0r_fields[] = {
   3481     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3482 };
   3483 
   3484 #endif
   3485 #if defined(BCM_88790_A0)
   3486 soc_field_info_t soc_U3_M0SS_INTR_31_0r_fields[] = {
   3487     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3488 };
   3489 
   3490 #endif
   3491 #if defined(BCM_88690_A0)
   3492 soc_field_info_t soc_U3_M0SS_INTR_31_0_BCM88690_A0r_fields[] = {
   3493     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3494 };
   3495 
   3496 #endif
   3497 #if defined(BCM_88690_B0)
   3498 soc_field_info_t soc_U3_M0SS_INTR_31_0_BCM88690_B0r_fields[] = {
   3499     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3500 };
   3501 
   3502 #endif
   3503 #if defined(BCM_88790_A0)
   3504 soc_field_info_t soc_U3_M0SS_INTR_63_32r_fields[] = {
   3505     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3506 };
   3507 
   3508 #endif
   3509 #if defined(BCM_88690_A0)
   3510 soc_field_info_t soc_U3_M0SS_INTR_63_32_BCM88690_A0r_fields[] = {
   3511     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3512 };
   3513 
   3514 #endif
   3515 #if defined(BCM_88690_B0)
   3516 soc_field_info_t soc_U3_M0SS_INTR_63_32_BCM88690_B0r_fields[] = {
   3517     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3518 };
   3519 
   3520 #endif
   3521 #if defined(BCM_88790_A0)
   3522 soc_field_info_t soc_U3_M0SS_INTR_95_64r_fields[] = {
   3523     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3524 };
   3525 
   3526 #endif
   3527 #if defined(BCM_88690_A0)
   3528 soc_field_info_t soc_U3_M0SS_INTR_95_64_BCM88690_A0r_fields[] = {
   3529     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3530 };
   3531 
   3532 #endif
   3533 #if defined(BCM_88690_B0)
   3534 soc_field_info_t soc_U3_M0SS_INTR_95_64_BCM88690_B0r_fields[] = {
   3535     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3536 };
   3537 
   3538 #endif
   3539 #if defined(BCM_88790_A0)
   3540 soc_field_info_t soc_U3_M0SS_INTR_CONTROLr_fields[] = {
   3541     { IRQLATENCYf, 8, 0, SOCF_LE },
   3542     { SLEEPHOLDREQNf, 1, 8, 0 },
   3543     { WICENREQf, 1, 9, 0 }
   3544 };
   3545 
   3546 #endif
   3547 #if defined(BCM_88690_A0)
   3548 soc_field_info_t soc_U3_M0SS_INTR_CONTROL_BCM88690_A0r_fields[] = {
   3549     { IRQLATENCYf, 8, 0, SOCF_LE },
   3550     { SLEEPHOLDREQNf, 1, 8, 0 },
   3551     { WICENREQf, 1, 9, 0 }
   3552 };
   3553 
   3554 #endif
   3555 #if defined(BCM_88690_B0)
   3556 soc_field_info_t soc_U3_M0SS_INTR_CONTROL_BCM88690_B0r_fields[] = {
   3557     { IRQLATENCYf, 8, 0, SOCF_LE },
   3558     { SLEEPHOLDREQNf, 1, 8, 0 },
   3559     { WICENREQf, 1, 9, 0 }
   3560 };
   3561 
   3562 #endif
   3563 #if defined(BCM_88790_A0)
   3564 soc_field_info_t soc_U3_M0SS_INTR_ENABLEr_fields[] = {
   3565     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   3566     { SINGLE_BIT_ERRf, 1, 0, 0 }
   3567 };
   3568 
   3569 #endif
   3570 #if defined(BCM_88690_A0)
   3571 soc_field_info_t soc_U3_M0SS_INTR_ENABLE_BCM88690_A0r_fields[] = {
   3572     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   3573     { SINGLE_BIT_ERRf, 1, 0, 0 }
   3574 };
   3575 
   3576 #endif
   3577 #if defined(BCM_88690_B0)
   3578 soc_field_info_t soc_U3_M0SS_INTR_ENABLE_BCM88690_B0r_fields[] = {
   3579     { DOUBLE_BIT_ERRf, 1, 1, 0 },
   3580     { SINGLE_BIT_ERRf, 1, 0, 0 }
   3581 };
   3582 
   3583 #endif
   3584 #if defined(BCM_88790_A0)
   3585 soc_field_info_t soc_U3_M0SS_INTR_MASK_127_96r_fields[] = {
   3586     { CNFGf, 32, 0, SOCF_LE }
   3587 };
   3588 
   3589 #endif
   3590 #if defined(BCM_88690_A0)
   3591 soc_field_info_t soc_U3_M0SS_INTR_MASK_127_96_BCM88690_A0r_fields[] = {
   3592     { CNFGf, 32, 0, SOCF_LE }
   3593 };
   3594 
   3595 #endif
   3596 #if defined(BCM_88690_B0)
   3597 soc_field_info_t soc_U3_M0SS_INTR_MASK_127_96_BCM88690_B0r_fields[] = {
   3598     { CNFGf, 32, 0, SOCF_LE }
   3599 };
   3600 
   3601 #endif
   3602 #if defined(BCM_88790_A0)
   3603 soc_field_info_t soc_U3_M0SS_INTR_MASK_159_128r_fields[] = {
   3604     { CNFGf, 32, 0, SOCF_LE }
   3605 };
   3606 
   3607 #endif
   3608 #if defined(BCM_88690_A0)
   3609 soc_field_info_t soc_U3_M0SS_INTR_MASK_159_128_BCM88690_A0r_fields[] = {
   3610     { CNFGf, 32, 0, SOCF_LE }
   3611 };
   3612 
   3613 #endif
   3614 #if defined(BCM_88690_B0)
   3615 soc_field_info_t soc_U3_M0SS_INTR_MASK_159_128_BCM88690_B0r_fields[] = {
   3616     { CNFGf, 32, 0, SOCF_LE }
   3617 };
   3618 
   3619 #endif
   3620 #if defined(BCM_88790_A0)
   3621 soc_field_info_t soc_U3_M0SS_INTR_MASK_191_160r_fields[] = {
   3622     { CNFGf, 32, 0, SOCF_LE }
   3623 };
   3624 
   3625 #endif
   3626 #if defined(BCM_88690_A0)
   3627 soc_field_info_t soc_U3_M0SS_INTR_MASK_191_160_BCM88690_A0r_fields[] = {
   3628     { CNFGf, 32, 0, SOCF_LE }
   3629 };
   3630 
   3631 #endif
   3632 #if defined(BCM_88690_B0)
   3633 soc_field_info_t soc_U3_M0SS_INTR_MASK_191_160_BCM88690_B0r_fields[] = {
   3634     { CNFGf, 32, 0, SOCF_LE }
   3635 };
   3636 
   3637 #endif
   3638 #if defined(BCM_88790_A0)
   3639 soc_field_info_t soc_U3_M0SS_INTR_MASK_223_192r_fields[] = {
   3640     { CNFGf, 32, 0, SOCF_LE }
   3641 };
   3642 
   3643 #endif
   3644 #if defined(BCM_88690_A0)
   3645 soc_field_info_t soc_U3_M0SS_INTR_MASK_223_192_BCM88690_A0r_fields[] = {
   3646     { CNFGf, 32, 0, SOCF_LE }
   3647 };
   3648 
   3649 #endif
   3650 #if defined(BCM_88690_B0)
   3651 soc_field_info_t soc_U3_M0SS_INTR_MASK_223_192_BCM88690_B0r_fields[] = {
   3652     { CNFGf, 32, 0, SOCF_LE }
   3653 };
   3654 
   3655 #endif
   3656 #if defined(BCM_88790_A0)
   3657 soc_field_info_t soc_U3_M0SS_INTR_MASK_255_224r_fields[] = {
   3658     { CNFGf, 32, 0, SOCF_LE }
   3659 };
   3660 
   3661 #endif
   3662 #if defined(BCM_88690_A0)
   3663 soc_field_info_t soc_U3_M0SS_INTR_MASK_255_224_BCM88690_A0r_fields[] = {
   3664     { CNFGf, 32, 0, SOCF_LE }
   3665 };
   3666 
   3667 #endif
   3668 #if defined(BCM_88690_B0)
   3669 soc_field_info_t soc_U3_M0SS_INTR_MASK_255_224_BCM88690_B0r_fields[] = {
   3670     { CNFGf, 32, 0, SOCF_LE }
   3671 };
   3672 
   3673 #endif
   3674 #if defined(BCM_88790_A0)
   3675 soc_field_info_t soc_U3_M0SS_INTR_MASK_31_0r_fields[] = {
   3676     { CNFGf, 32, 0, SOCF_LE }
   3677 };
   3678 
   3679 #endif
   3680 #if defined(BCM_88690_A0)
   3681 soc_field_info_t soc_U3_M0SS_INTR_MASK_31_0_BCM88690_A0r_fields[] = {
   3682     { CNFGf, 32, 0, SOCF_LE }
   3683 };
   3684 
   3685 #endif
   3686 #if defined(BCM_88690_B0)
   3687 soc_field_info_t soc_U3_M0SS_INTR_MASK_31_0_BCM88690_B0r_fields[] = {
   3688     { CNFGf, 32, 0, SOCF_LE }
   3689 };
   3690 
   3691 #endif
   3692 #if defined(BCM_88790_A0)
   3693 soc_field_info_t soc_U3_M0SS_INTR_MASK_63_32r_fields[] = {
   3694     { CNFGf, 32, 0, SOCF_LE }
   3695 };
   3696 
   3697 #endif
   3698 #if defined(BCM_88690_A0)
   3699 soc_field_info_t soc_U3_M0SS_INTR_MASK_63_32_BCM88690_A0r_fields[] = {
   3700     { CNFGf, 32, 0, SOCF_LE }
   3701 };
   3702 
   3703 #endif
   3704 #if defined(BCM_88690_B0)
   3705 soc_field_info_t soc_U3_M0SS_INTR_MASK_63_32_BCM88690_B0r_fields[] = {
   3706     { CNFGf, 32, 0, SOCF_LE }
   3707 };
   3708 
   3709 #endif
   3710 #if defined(BCM_88790_A0)
   3711 soc_field_info_t soc_U3_M0SS_INTR_MASK_95_64r_fields[] = {
   3712     { CNFGf, 32, 0, SOCF_LE }
   3713 };
   3714 
   3715 #endif
   3716 #if defined(BCM_88690_A0)
   3717 soc_field_info_t soc_U3_M0SS_INTR_MASK_95_64_BCM88690_A0r_fields[] = {
   3718     { CNFGf, 32, 0, SOCF_LE }
   3719 };
   3720 
   3721 #endif
   3722 #if defined(BCM_88690_B0)
   3723 soc_field_info_t soc_U3_M0SS_INTR_MASK_95_64_BCM88690_B0r_fields[] = {
   3724     { CNFGf, 32, 0, SOCF_LE }
   3725 };
   3726 
   3727 #endif
   3728 #if defined(BCM_88790_A0)
   3729 soc_field_info_t soc_U3_M0SS_RAW_INTR_127_96r_fields[] = {
   3730     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3731 };
   3732 
   3733 #endif
   3734 #if defined(BCM_88690_A0)
   3735 soc_field_info_t soc_U3_M0SS_RAW_INTR_127_96_BCM88690_A0r_fields[] = {
   3736     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3737 };
   3738 
   3739 #endif
   3740 #if defined(BCM_88690_B0)
   3741 soc_field_info_t soc_U3_M0SS_RAW_INTR_127_96_BCM88690_B0r_fields[] = {
   3742     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3743 };
   3744 
   3745 #endif
   3746 #if defined(BCM_88790_A0)
   3747 soc_field_info_t soc_U3_M0SS_RAW_INTR_159_128r_fields[] = {
   3748     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3749 };
   3750 
   3751 #endif
   3752 #if defined(BCM_88690_A0)
   3753 soc_field_info_t soc_U3_M0SS_RAW_INTR_159_128_BCM88690_A0r_fields[] = {
   3754     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3755 };
   3756 
   3757 #endif
   3758 #if defined(BCM_88690_B0)
   3759 soc_field_info_t soc_U3_M0SS_RAW_INTR_159_128_BCM88690_B0r_fields[] = {
   3760     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3761 };
   3762 
   3763 #endif
   3764 #if defined(BCM_88790_A0)
   3765 soc_field_info_t soc_U3_M0SS_RAW_INTR_191_160r_fields[] = {
   3766     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3767 };
   3768 
   3769 #endif
   3770 #if defined(BCM_88690_A0)
   3771 soc_field_info_t soc_U3_M0SS_RAW_INTR_191_160_BCM88690_A0r_fields[] = {
   3772     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3773 };
   3774 
   3775 #endif
   3776 #if defined(BCM_88690_B0)
   3777 soc_field_info_t soc_U3_M0SS_RAW_INTR_191_160_BCM88690_B0r_fields[] = {
   3778     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3779 };
   3780 
   3781 #endif
   3782 #if defined(BCM_88790_A0)
   3783 soc_field_info_t soc_U3_M0SS_RAW_INTR_223_192r_fields[] = {
   3784     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3785 };
   3786 
   3787 #endif
   3788 #if defined(BCM_88690_A0)
   3789 soc_field_info_t soc_U3_M0SS_RAW_INTR_223_192_BCM88690_A0r_fields[] = {
   3790     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3791 };
   3792 
   3793 #endif
   3794 #if defined(BCM_88690_B0)
   3795 soc_field_info_t soc_U3_M0SS_RAW_INTR_223_192_BCM88690_B0r_fields[] = {
   3796     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3797 };
   3798 
   3799 #endif
   3800 #if defined(BCM_88790_A0)
   3801 soc_field_info_t soc_U3_M0SS_RAW_INTR_255_224r_fields[] = {
   3802     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3803 };
   3804 
   3805 #endif
   3806 #if defined(BCM_88690_A0)
   3807 soc_field_info_t soc_U3_M0SS_RAW_INTR_255_224_BCM88690_A0r_fields[] = {
   3808     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3809 };
   3810 
   3811 #endif
   3812 #if defined(BCM_88690_B0)
   3813 soc_field_info_t soc_U3_M0SS_RAW_INTR_255_224_BCM88690_B0r_fields[] = {
   3814     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3815 };
   3816 
   3817 #endif
   3818 #if defined(BCM_88790_A0)
   3819 soc_field_info_t soc_U3_M0SS_RAW_INTR_31_0r_fields[] = {
   3820     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3821 };
   3822 
   3823 #endif
   3824 #if defined(BCM_88690_A0)
   3825 soc_field_info_t soc_U3_M0SS_RAW_INTR_31_0_BCM88690_A0r_fields[] = {
   3826     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3827 };
   3828 
   3829 #endif
   3830 #if defined(BCM_88690_B0)
   3831 soc_field_info_t soc_U3_M0SS_RAW_INTR_31_0_BCM88690_B0r_fields[] = {
   3832     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3833 };
   3834 
   3835 #endif
   3836 #if defined(BCM_88790_A0)
   3837 soc_field_info_t soc_U3_M0SS_RAW_INTR_63_32r_fields[] = {
   3838     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3839 };
   3840 
   3841 #endif
   3842 #if defined(BCM_88690_A0)
   3843 soc_field_info_t soc_U3_M0SS_RAW_INTR_63_32_BCM88690_A0r_fields[] = {
   3844     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3845 };
   3846 
   3847 #endif
   3848 #if defined(BCM_88690_B0)
   3849 soc_field_info_t soc_U3_M0SS_RAW_INTR_63_32_BCM88690_B0r_fields[] = {
   3850     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3851 };
   3852 
   3853 #endif
   3854 #if defined(BCM_88790_A0)
   3855 soc_field_info_t soc_U3_M0SS_RAW_INTR_95_64r_fields[] = {
   3856     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3857 };
   3858 
   3859 #endif
   3860 #if defined(BCM_88690_A0)
   3861 soc_field_info_t soc_U3_M0SS_RAW_INTR_95_64_BCM88690_A0r_fields[] = {
   3862     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3863 };
   3864 
   3865 #endif
   3866 #if defined(BCM_88690_B0)
   3867 soc_field_info_t soc_U3_M0SS_RAW_INTR_95_64_BCM88690_B0r_fields[] = {
   3868     { STATUSf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }
   3869 };
   3870 
   3871 #endif
   3872 #if defined(BCM_88790_A0)
   3873 soc_field_info_t soc_U3_M0SS_STATUSr_fields[] = {
   3874     { DBGRESTARTEDf, 1, 0, 0 },
   3875     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   3876     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   3877     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   3878     { SLEEPHOLDACKf, 1, 2, 0 },
   3879     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   3880     { SYSRESETREQf, 1, 1, 0 },
   3881     { TXEVf, 16, 16, SOCF_LE },
   3882     { WAKEUPf, 1, 4, 0 },
   3883     { WICENACKf, 1, 3, 0 }
   3884 };
   3885 
   3886 #endif
   3887 #if defined(BCM_88690_A0)
   3888 soc_field_info_t soc_U3_M0SS_STATUS_BCM88690_A0r_fields[] = {
   3889     { DBGRESTARTEDf, 1, 0, 0 },
   3890     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   3891     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   3892     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   3893     { SLEEPHOLDACKf, 1, 2, 0 },
   3894     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   3895     { SYSRESETREQf, 1, 1, 0 },
   3896     { TXEVf, 16, 16, SOCF_LE },
   3897     { WAKEUPf, 1, 4, 0 },
   3898     { WICENACKf, 1, 3, 0 }
   3899 };
   3900 
   3901 #endif
   3902 #if defined(BCM_88690_B0)
   3903 soc_field_info_t soc_U3_M0SS_STATUS_BCM88690_B0r_fields[] = {
   3904     { DBGRESTARTEDf, 1, 0, 0 },
   3905     { HALTEDf, 1, 8, SOCF_RO|SOCF_SIG },
   3906     { LOCKUPf, 1, 9, SOCF_RO|SOCF_SIG },
   3907     { SLEEPDEEPf, 1, 10, SOCF_RO|SOCF_SIG },
   3908     { SLEEPHOLDACKf, 1, 2, 0 },
   3909     { SLEEPINGf, 1, 11, SOCF_RO|SOCF_SIG },
   3910     { SYSRESETREQf, 1, 1, 0 },
   3911     { TXEVf, 16, 16, SOCF_LE },
   3912     { WAKEUPf, 1, 4, 0 },
   3913     { WICENACKf, 1, 3, 0 }
   3914 };
   3915 
   3916 #endif
   3917 #if defined(BCM_88790_A0)
   3918 soc_field_info_t soc_U3_M0SS_TCM_CTRLr_fields[] = {
   3919     { TCM_TMf, 7, 0, SOCF_LE }
   3920 };
   3921 
   3922 #endif
   3923 #if defined(BCM_88690_A0)
   3924 soc_field_info_t soc_U3_M0SS_TCM_CTRL_BCM88690_A0r_fields[] = {
   3925     { TCM_TMf, 7, 0, SOCF_LE }
   3926 };
   3927 
   3928 #endif
   3929 #if defined(BCM_88690_B0)
   3930 soc_field_info_t soc_U3_M0SS_TCM_CTRL_BCM88690_B0r_fields[] = {
   3931     { TCM_TMf, 7, 0, SOCF_LE }
   3932 };
   3933 
   3934 #endif
   3935 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \
   3936     defined(BCM_56850_A0) || defined(BCM_56860_A0)
   3937 soc_field_info_t soc_UCQDBMEMDEBUGr_fields[] = {
   3938     { TMf, 1, 0, SOCF_RES }
   3939 };
   3940 
   3941 #endif
   3942 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   3943 soc_field_info_t soc_UCQ_CONFIGr_fields[] = {
   3944     { WAMU_QUEUE_BASEf, 10, 0, SOCF_LE }
   3945 };
   3946 
   3947 #endif
   3948 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3949 soc_field_info_t soc_UCQ_COS_EMPTY_REGr_fields[] = {
   3950     { UCQ_COS_QEMPTYf, 10, 0, SOCF_LE|SOCF_RO }
   3951 };
   3952 
   3953 #endif
   3954 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3955 soc_field_info_t soc_UCQ_EXTCOS1_EMPTY_REGr_fields[] = {
   3956     { UCQ_EXTCOS1_QEMPTYf, 64, 0, SOCF_LE|SOCF_RO }
   3957 };
   3958 
   3959 #endif
   3960 #if defined(BCM_56640_A0)
   3961 soc_field_info_t soc_UCQ_FREE_MEMDEBUGr_fields[] = {
   3962     { TMf, 10, 0, SOCF_LE|SOCF_RES }
   3963 };
   3964 
   3965 #endif
   3966 #if defined(BCM_56640_A0)
   3967 soc_field_info_t soc_UCQ_FREE_MEMECC_ERRPTRr_fields[] = {
   3968     { RDPTRf, 10, 0, SOCF_LE|SOCF_RO }
   3969 };
   3970 
   3971 #endif
   3972 #if defined(BCM_56640_A0)
   3973 soc_field_info_t soc_UCQ_UCQE_MEMECC_ERRPTRr_fields[] = {
   3974     { RDPTRf, 15, 0, SOCF_LE|SOCF_RO }
   3975 };
   3976 
   3977 #endif
   3978 #if defined(BCM_88650_A0)
   3979 soc_field_info_t soc_UC_0_CONFIGr_fields[] = {
   3980     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_SIG },
   3981     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_SIG },
   3982     { CFGEEf, 1, 1, SOCF_SIG },
   3983     { CFGIEf, 1, 2, SOCF_SIG },
   3984     { CFGNMFIf, 1, 4, SOCF_SIG },
   3985     { CFG_WDOGINT_MASKf, 1, 27, SOCF_SIG },
   3986     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_SIG },
   3987     { INITRAMAf, 1, 15, SOCF_SIG },
   3988     { INITRAMBf, 1, 16, SOCF_SIG },
   3989     { OVERWRITE_OTP_CONFIGf, 1, 31, SOCF_SIG },
   3990     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_SIG },
   3991     { PARLVRAMf, 1, 21, SOCF_SIG },
   3992     { RESERVED_0f, 2, 29, SOCF_LE|SOCF_RO|SOCF_RES },
   3993     { RESERVED_1f, 1, 0, SOCF_SIG|SOCF_RES },
   3994     { RESERVED_2f, 1, 13, SOCF_SIG|SOCF_RES },
   3995     { RESERVED_3f, 1, 17, SOCF_SIG|SOCF_RES },
   3996     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_SIG },
   3997     { SLBTCMSBf, 1, 14, SOCF_SIG },
   3998     { SW_AUTOLOADf, 1, 28, SOCF_SIG },
   3999     { TEINITf, 1, 3, SOCF_SIG }
   4000 };
   4001 
   4002 #endif
   4003 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4004 soc_field_info_t soc_UC_0_CONFIG_BCM56440_A0r_fields[] = {
   4005     { CFGATCMSZf, 4, 5, SOCF_LE },
   4006     { CFGBTCMSZf, 4, 9, SOCF_LE },
   4007     { CFGEEf, 1, 1, 0 },
   4008     { CFGIEf, 1, 2, 0 },
   4009     { CFGNMFIf, 1, 4, 0 },
   4010     { CFG_WDOGINT_MASKf, 1, 27, 0 },
   4011     { ERRENRAMf, 3, 22, SOCF_LE },
   4012     { INITRAMAf, 1, 15, 0 },
   4013     { INITRAMBf, 1, 16, 0 },
   4014     { OVERWRITE_OTP_CONFIGf, 1, 31, 0 },
   4015     { PARECCENRAMf, 3, 18, SOCF_LE },
   4016     { PARLVRAMf, 1, 21, 0 },
   4017     { RESERVED_0f, 2, 29, SOCF_LE|SOCF_RO|SOCF_RES },
   4018     { RESERVED_1f, 1, 0, SOCF_RES },
   4019     { RESERVED_2f, 1, 13, SOCF_RES },
   4020     { RESERVED_3f, 1, 17, SOCF_RES },
   4021     { RMWENRAMf, 2, 25, SOCF_LE },
   4022     { SLBTCMSBf, 1, 14, 0 },
   4023     { SW_AUTOLOADf, 1, 28, 0 },
   4024     { TEINITf, 1, 3, 0 }
   4025 };
   4026 
   4027 #endif
   4028 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4029     defined(BCM_56860_A0)
   4030 soc_field_info_t soc_UC_0_CONFIG_BCM56640_A0r_fields[] = {
   4031     { CFGATCMSZf, 4, 5, SOCF_LE },
   4032     { CFGBTCMSZf, 4, 9, SOCF_LE },
   4033     { CFGEEf, 1, 1, 0 },
   4034     { CFGIEf, 1, 2, 0 },
   4035     { CFGNMFIf, 1, 4, 0 },
   4036     { CFG_WDOGINT_MASKf, 1, 27, 0 },
   4037     { ERRENRAMf, 3, 22, SOCF_LE },
   4038     { INITRAMAf, 1, 15, 0 },
   4039     { INITRAMBf, 1, 16, 0 },
   4040     { OVERWRITE_OTP_CONFIGf, 1, 31, 0 },
   4041     { PARECCENRAMf, 3, 18, SOCF_LE },
   4042     { PARLVRAMf, 1, 21, 0 },
   4043     { RESERVED_0f, 2, 29, SOCF_LE|SOCF_RO|SOCF_RES },
   4044     { RESERVED_1f, 1, 0, SOCF_RES },
   4045     { RESERVED_2f, 1, 13, SOCF_RES },
   4046     { RESERVED_3f, 1, 17, SOCF_RES },
   4047     { RMWENRAMf, 2, 25, SOCF_LE },
   4048     { SLBTCMSBf, 1, 14, 0 },
   4049     { SW_AUTOLOADf, 1, 28, 0 },
   4050     { TEINITf, 1, 3, 0 }
   4051 };
   4052 
   4053 #endif
   4054 #if defined(BCM_88202_A0)
   4055 soc_field_info_t soc_UC_0_CONFIG_BCM88202_A0r_fields[] = {
   4056     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_SIG },
   4057     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_SIG },
   4058     { CFGEEf, 1, 1, SOCF_SIG },
   4059     { CFGIEf, 1, 2, SOCF_SIG },
   4060     { CFGNMFIf, 1, 4, SOCF_SIG },
   4061     { CFG_WDOGINT_MASKf, 1, 27, SOCF_SIG },
   4062     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_SIG },
   4063     { FIELD_0_0f, 1, 0, SOCF_SIG },
   4064     { FIELD_13_13f, 1, 13, SOCF_SIG },
   4065     { FIELD_17_17f, 1, 17, SOCF_SIG },
   4066     { FIELD_29_30f, 2, 29, SOCF_LE|SOCF_RO },
   4067     { INITRAMAf, 1, 15, SOCF_SIG },
   4068     { INITRAMBf, 1, 16, SOCF_SIG },
   4069     { OVERWRITE_OTP_CONFIGf, 1, 31, SOCF_SIG },
   4070     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_SIG },
   4071     { PARLVRAMf, 1, 21, SOCF_SIG },
   4072     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_SIG },
   4073     { SLBTCMSBf, 1, 14, SOCF_SIG },
   4074     { SW_AUTOLOADf, 1, 28, SOCF_SIG },
   4075     { TEINITf, 1, 3, SOCF_SIG }
   4076 };
   4077 
   4078 #endif
   4079 #if defined(BCM_88650_B0)
   4080 soc_field_info_t soc_UC_0_CONFIG_BCM88650_B0r_fields[] = {
   4081     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_SIG },
   4082     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_SIG },
   4083     { CFGEEf, 1, 1, SOCF_SIG },
   4084     { CFGIEf, 1, 2, SOCF_SIG },
   4085     { CFGNMFIf, 1, 4, SOCF_SIG },
   4086     { CFG_WDOGINT_MASKf, 1, 27, SOCF_SIG },
   4087     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_SIG },
   4088     { INITRAMAf, 1, 15, SOCF_SIG },
   4089     { INITRAMBf, 1, 16, SOCF_SIG },
   4090     { OVERWRITE_OTP_CONFIGf, 1, 31, SOCF_SIG },
   4091     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_SIG },
   4092     { PARLVRAMf, 1, 21, SOCF_SIG },
   4093     { RESERVED_0f, 2, 29, SOCF_LE|SOCF_RO|SOCF_RES },
   4094     { RESERVED_1f, 1, 0, SOCF_SIG|SOCF_RES },
   4095     { RESERVED_2f, 1, 13, SOCF_SIG|SOCF_RES },
   4096     { RESERVED_3f, 1, 17, SOCF_SIG|SOCF_RES },
   4097     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_SIG },
   4098     { SLBTCMSBf, 1, 14, SOCF_SIG },
   4099     { SW_AUTOLOADf, 1, 28, SOCF_SIG },
   4100     { TEINITf, 1, 3, SOCF_SIG }
   4101 };
   4102 
   4103 #endif
   4104 #if defined(BCM_88660_A0)
   4105 soc_field_info_t soc_UC_0_CONFIG_BCM88660_A0r_fields[] = {
   4106     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_SIG },
   4107     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_SIG },
   4108     { CFGEEf, 1, 1, SOCF_SIG },
   4109     { CFGIEf, 1, 2, SOCF_SIG },
   4110     { CFGNMFIf, 1, 4, SOCF_SIG },
   4111     { CFG_WDOGINT_MASKf, 1, 27, SOCF_SIG },
   4112     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_SIG },
   4113     { INITRAMAf, 1, 15, SOCF_SIG },
   4114     { INITRAMBf, 1, 16, SOCF_SIG },
   4115     { OVERWRITE_OTP_CONFIGf, 1, 31, SOCF_SIG },
   4116     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_SIG },
   4117     { PARLVRAMf, 1, 21, SOCF_SIG },
   4118     { RESERVED_0f, 2, 29, SOCF_LE|SOCF_RO|SOCF_RES },
   4119     { RESERVED_1f, 1, 0, SOCF_SIG|SOCF_RES },
   4120     { RESERVED_2f, 1, 13, SOCF_SIG|SOCF_RES },
   4121     { RESERVED_3f, 1, 17, SOCF_SIG|SOCF_RES },
   4122     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_SIG },
   4123     { SLBTCMSBf, 1, 14, SOCF_SIG },
   4124     { SW_AUTOLOADf, 1, 28, SOCF_SIG },
   4125     { TEINITf, 1, 3, SOCF_SIG }
   4126 };
   4127 
   4128 #endif
   4129 #if defined(BCM_88650_A0)
   4130 soc_field_info_t soc_UC_0_DEBUG_CONFIGr_fields[] = {
   4131     { DBGENf, 1, 0, SOCF_SIG },
   4132     { DBGRESTARTf, 1, 4, SOCF_SIG },
   4133     { DBG_UNLOCKf, 1, 5, SOCF_SIG },
   4134     { EDBGRQf, 1, 2, SOCF_SIG },
   4135     { NIDENf, 1, 1, SOCF_SIG },
   4136     { PCLKENDBGf, 1, 3, SOCF_SIG },
   4137     { RESERVED_0f, 26, 6, SOCF_LE|SOCF_RO|SOCF_RES }
   4138 };
   4139 
   4140 #endif
   4141 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4142 soc_field_info_t soc_UC_0_DEBUG_CONFIG_BCM56440_A0r_fields[] = {
   4143     { DBGENf, 1, 0, 0 },
   4144     { DBGRESTARTf, 1, 4, 0 },
   4145     { DBG_UNLOCKf, 1, 5, 0 },
   4146     { EDBGRQf, 1, 2, 0 },
   4147     { NIDENf, 1, 1, 0 },
   4148     { PCLKENDBGf, 1, 3, 0 },
   4149     { RESERVED_0f, 26, 6, SOCF_LE|SOCF_RO|SOCF_RES }
   4150 };
   4151 
   4152 #endif
   4153 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4154     defined(BCM_56860_A0)
   4155 soc_field_info_t soc_UC_0_DEBUG_CONFIG_BCM56640_A0r_fields[] = {
   4156     { DBGENf, 1, 0, 0 },
   4157     { DBGRESTARTf, 1, 4, 0 },
   4158     { DBG_UNLOCKf, 1, 5, 0 },
   4159     { EDBGRQf, 1, 2, 0 },
   4160     { NIDENf, 1, 1, 0 },
   4161     { PCLKENDBGf, 1, 3, 0 },
   4162     { RESERVED_0f, 26, 6, SOCF_LE|SOCF_RO|SOCF_RES }
   4163 };
   4164 
   4165 #endif
   4166 #if defined(BCM_88202_A0)
   4167 soc_field_info_t soc_UC_0_DEBUG_CONFIG_BCM88202_A0r_fields[] = {
   4168     { DBGENf, 1, 0, SOCF_SIG },
   4169     { DBGRESTARTf, 1, 4, SOCF_SIG },
   4170     { DBG_UNLOCKf, 1, 5, SOCF_SIG },
   4171     { EDBGRQf, 1, 2, SOCF_SIG },
   4172     { FIELD_6_31f, 26, 6, SOCF_LE|SOCF_RO },
   4173     { NIDENf, 1, 1, SOCF_SIG },
   4174     { PCLKENDBGf, 1, 3, SOCF_SIG }
   4175 };
   4176 
   4177 #endif
   4178 #if defined(BCM_88650_B0)
   4179 soc_field_info_t soc_UC_0_DEBUG_CONFIG_BCM88650_B0r_fields[] = {
   4180     { DBGENf, 1, 0, SOCF_SIG },
   4181     { DBGRESTARTf, 1, 4, SOCF_SIG },
   4182     { DBG_UNLOCKf, 1, 5, SOCF_SIG },
   4183     { EDBGRQf, 1, 2, SOCF_SIG },
   4184     { NIDENf, 1, 1, SOCF_SIG },
   4185     { PCLKENDBGf, 1, 3, SOCF_SIG },
   4186     { RESERVED_0f, 26, 6, SOCF_LE|SOCF_RO|SOCF_RES }
   4187 };
   4188 
   4189 #endif
   4190 #if defined(BCM_88660_A0)
   4191 soc_field_info_t soc_UC_0_DEBUG_CONFIG_BCM88660_A0r_fields[] = {
   4192     { DBGENf, 1, 0, SOCF_SIG },
   4193     { DBGRESTARTf, 1, 4, SOCF_SIG },
   4194     { DBG_UNLOCKf, 1, 5, SOCF_SIG },
   4195     { EDBGRQf, 1, 2, SOCF_SIG },
   4196     { NIDENf, 1, 1, SOCF_SIG },
   4197     { PCLKENDBGf, 1, 3, SOCF_SIG },
   4198     { RESERVED_0f, 26, 6, SOCF_LE|SOCF_RO|SOCF_RES }
   4199 };
   4200 
   4201 #endif
   4202 #if defined(BCM_88650_A0)
   4203 soc_field_info_t soc_UC_0_DEBUG_STATUSr_fields[] = {
   4204     { CPUHALT_Nf, 1, 4, SOCF_RO },
   4205     { DBGACKf, 1, 0, SOCF_RO },
   4206     { DBGRESTARTEDf, 1, 6, SOCF_RO },
   4207     { DBGRSTREQf, 1, 1, SOCF_RO },
   4208     { RESERVED_0f, 25, 7, SOCF_LE|SOCF_RO|SOCF_RES },
   4209     { RESET_Nf, 1, 2, SOCF_RO },
   4210     { STANDBYWFIf, 1, 5, SOCF_RO },
   4211     { SYSPORESET_Nf, 1, 3, SOCF_RO }
   4212 };
   4213 
   4214 #endif
   4215 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4216 soc_field_info_t soc_UC_0_DEBUG_STATUS_BCM56440_A0r_fields[] = {
   4217     { CPUHALT_Nf, 1, 4, SOCF_RO },
   4218     { DBGACKf, 1, 0, SOCF_RO },
   4219     { DBGRESTARTEDf, 1, 6, SOCF_RO },
   4220     { DBGRSTREQf, 1, 1, SOCF_RO },
   4221     { RESERVED_0f, 25, 7, SOCF_LE|SOCF_RO|SOCF_RES },
   4222     { RESET_Nf, 1, 2, SOCF_RO },
   4223     { STANDBYWFIf, 1, 5, SOCF_RO },
   4224     { SYSPORESET_Nf, 1, 3, SOCF_RO }
   4225 };
   4226 
   4227 #endif
   4228 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4229     defined(BCM_56860_A0)
   4230 soc_field_info_t soc_UC_0_DEBUG_STATUS_BCM56640_A0r_fields[] = {
   4231     { CPUHALT_Nf, 1, 4, SOCF_RO },
   4232     { DBGACKf, 1, 0, SOCF_RO },
   4233     { DBGRESTARTEDf, 1, 6, SOCF_RO },
   4234     { DBGRSTREQf, 1, 1, SOCF_RO },
   4235     { RESERVED_0f, 25, 7, SOCF_LE|SOCF_RO|SOCF_RES },
   4236     { RESET_Nf, 1, 2, SOCF_RO },
   4237     { STANDBYWFIf, 1, 5, SOCF_RO },
   4238     { SYSPORESET_Nf, 1, 3, SOCF_RO }
   4239 };
   4240 
   4241 #endif
   4242 #if defined(BCM_88202_A0)
   4243 soc_field_info_t soc_UC_0_DEBUG_STATUS_BCM88202_A0r_fields[] = {
   4244     { CPUHALT_Nf, 1, 4, SOCF_RO },
   4245     { DBGACKf, 1, 0, SOCF_RO },
   4246     { DBGRESTARTEDf, 1, 6, SOCF_RO },
   4247     { DBGRSTREQf, 1, 1, SOCF_RO },
   4248     { FIELD_7_31f, 25, 7, SOCF_LE|SOCF_RO },
   4249     { RESET_Nf, 1, 2, SOCF_RO },
   4250     { STANDBYWFIf, 1, 5, SOCF_RO },
   4251     { SYSPORESET_Nf, 1, 3, SOCF_RO }
   4252 };
   4253 
   4254 #endif
   4255 #if defined(BCM_88650_B0)
   4256 soc_field_info_t soc_UC_0_DEBUG_STATUS_BCM88650_B0r_fields[] = {
   4257     { CPUHALT_Nf, 1, 4, SOCF_RO },
   4258     { DBGACKf, 1, 0, SOCF_RO },
   4259     { DBGRESTARTEDf, 1, 6, SOCF_RO },
   4260     { DBGRSTREQf, 1, 1, SOCF_RO },
   4261     { RESERVED_0f, 25, 7, SOCF_LE|SOCF_RO|SOCF_RES },
   4262     { RESET_Nf, 1, 2, SOCF_RO },
   4263     { STANDBYWFIf, 1, 5, SOCF_RO },
   4264     { SYSPORESET_Nf, 1, 3, SOCF_RO }
   4265 };
   4266 
   4267 #endif
   4268 #if defined(BCM_88660_A0)
   4269 soc_field_info_t soc_UC_0_DEBUG_STATUS_BCM88660_A0r_fields[] = {
   4270     { CPUHALT_Nf, 1, 4, SOCF_RO },
   4271     { DBGACKf, 1, 0, SOCF_RO },
   4272     { DBGRESTARTEDf, 1, 6, SOCF_RO },
   4273     { DBGRSTREQf, 1, 1, SOCF_RO },
   4274     { RESERVED_0f, 25, 7, SOCF_LE|SOCF_RO|SOCF_RES },
   4275     { RESET_Nf, 1, 2, SOCF_RO },
   4276     { STANDBYWFIf, 1, 5, SOCF_RO },
   4277     { SYSPORESET_Nf, 1, 3, SOCF_RO }
   4278 };
   4279 
   4280 #endif
   4281 #if defined(BCM_88650_A0)
   4282 soc_field_info_t soc_UC_0_RST_CONTROLr_fields[] = {
   4283     { BYPASS_RSTFSM_CTRLf, 1, 31, SOCF_SIG },
   4284     { CORE_RESET_Nf, 1, 0, SOCF_SIG },
   4285     { CPUHALT_Nf, 1, 2, SOCF_SIG },
   4286     { DEBUG_RESET_Nf, 1, 3, SOCF_SIG },
   4287     { RESERVED_0f, 27, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   4288     { SYS_PORESET_Nf, 1, 1, SOCF_SIG }
   4289 };
   4290 
   4291 #endif
   4292 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4293 soc_field_info_t soc_UC_0_RST_CONTROL_BCM56440_A0r_fields[] = {
   4294     { BYPASS_RSTFSM_CTRLf, 1, 31, 0 },
   4295     { CORE_RESET_Nf, 1, 0, 0 },
   4296     { CPUHALT_Nf, 1, 2, 0 },
   4297     { DEBUG_RESET_Nf, 1, 3, 0 },
   4298     { RESERVED_0f, 27, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   4299     { SYS_PORESET_Nf, 1, 1, 0 }
   4300 };
   4301 
   4302 #endif
   4303 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4304     defined(BCM_56860_A0)
   4305 soc_field_info_t soc_UC_0_RST_CONTROL_BCM56640_A0r_fields[] = {
   4306     { BYPASS_RSTFSM_CTRLf, 1, 31, 0 },
   4307     { CORE_RESET_Nf, 1, 0, 0 },
   4308     { CPUHALT_Nf, 1, 2, 0 },
   4309     { DEBUG_RESET_Nf, 1, 3, 0 },
   4310     { RESERVED_0f, 27, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   4311     { SYS_PORESET_Nf, 1, 1, 0 }
   4312 };
   4313 
   4314 #endif
   4315 #if defined(BCM_88202_A0)
   4316 soc_field_info_t soc_UC_0_RST_CONTROL_BCM88202_A0r_fields[] = {
   4317     { BYPASS_RSTFSM_CTRLf, 1, 31, SOCF_SIG },
   4318     { CORE_RESET_Nf, 1, 0, SOCF_SIG },
   4319     { CPUHALT_Nf, 1, 2, SOCF_SIG },
   4320     { DEBUG_RESET_Nf, 1, 3, SOCF_SIG },
   4321     { FIELD_4_30f, 27, 4, SOCF_LE|SOCF_RO },
   4322     { SYS_PORESET_Nf, 1, 1, SOCF_SIG }
   4323 };
   4324 
   4325 #endif
   4326 #if defined(BCM_88650_B0)
   4327 soc_field_info_t soc_UC_0_RST_CONTROL_BCM88650_B0r_fields[] = {
   4328     { BYPASS_RSTFSM_CTRLf, 1, 31, SOCF_SIG },
   4329     { CORE_RESET_Nf, 1, 0, SOCF_SIG },
   4330     { CPUHALT_Nf, 1, 2, SOCF_SIG },
   4331     { DEBUG_RESET_Nf, 1, 3, SOCF_SIG },
   4332     { RESERVED_0f, 27, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   4333     { SYS_PORESET_Nf, 1, 1, SOCF_SIG }
   4334 };
   4335 
   4336 #endif
   4337 #if defined(BCM_88660_A0)
   4338 soc_field_info_t soc_UC_0_RST_CONTROL_BCM88660_A0r_fields[] = {
   4339     { BYPASS_RSTFSM_CTRLf, 1, 31, SOCF_SIG },
   4340     { CORE_RESET_Nf, 1, 0, SOCF_SIG },
   4341     { CPUHALT_Nf, 1, 2, SOCF_SIG },
   4342     { DEBUG_RESET_Nf, 1, 3, SOCF_SIG },
   4343     { RESERVED_0f, 27, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   4344     { SYS_PORESET_Nf, 1, 1, SOCF_SIG }
   4345 };
   4346 
   4347 #endif
   4348 #if defined(BCM_88650_A0)
   4349 soc_field_info_t soc_UC_0_STATUSr_fields[] = {
   4350     { AUTOLOAD_DONEf, 1, 27, SOCF_RO },
   4351     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   4352     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   4353     { CFGEEf, 1, 1, SOCF_RO },
   4354     { CFGIEf, 1, 2, SOCF_RO },
   4355     { CFGNMFIf, 1, 4, SOCF_RO },
   4356     { ENTCM1IFf, 1, 13, SOCF_RO },
   4357     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   4358     { INITRAMAf, 1, 15, SOCF_RO },
   4359     { INITRAMBf, 1, 16, SOCF_RO },
   4360     { LOCZRAMAf, 1, 17, SOCF_RO },
   4361     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   4362     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   4363     { PARLVRAMf, 1, 21, SOCF_RO },
   4364     { RESERVED_0f, 3, 28, SOCF_LE|SOCF_RO|SOCF_RES },
   4365     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   4366     { SLBTCMSBf, 1, 14, SOCF_RO },
   4367     { TEINITf, 1, 3, SOCF_RO },
   4368     { VINITHIf, 1, 0, SOCF_RO }
   4369 };
   4370 
   4371 #endif
   4372 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4373 soc_field_info_t soc_UC_0_STATUS_BCM56440_A0r_fields[] = {
   4374     { AUTOLOAD_DONEf, 1, 27, SOCF_RO },
   4375     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   4376     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   4377     { CFGEEf, 1, 1, SOCF_RO },
   4378     { CFGIEf, 1, 2, SOCF_RO },
   4379     { CFGNMFIf, 1, 4, SOCF_RO },
   4380     { ENTCM1IFf, 1, 13, SOCF_RO },
   4381     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   4382     { INITRAMAf, 1, 15, SOCF_RO },
   4383     { INITRAMBf, 1, 16, SOCF_RO },
   4384     { LOCZRAMAf, 1, 17, SOCF_RO },
   4385     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   4386     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   4387     { PARLVRAMf, 1, 21, SOCF_RO },
   4388     { RESERVED_0f, 3, 28, SOCF_LE|SOCF_RO|SOCF_RES },
   4389     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   4390     { SLBTCMSBf, 1, 14, SOCF_RO },
   4391     { TEINITf, 1, 3, SOCF_RO },
   4392     { VINITHIf, 1, 0, SOCF_RO }
   4393 };
   4394 
   4395 #endif
   4396 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4397     defined(BCM_56860_A0)
   4398 soc_field_info_t soc_UC_0_STATUS_BCM56640_A0r_fields[] = {
   4399     { AUTOLOAD_DONEf, 1, 27, SOCF_RO },
   4400     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   4401     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   4402     { CFGEEf, 1, 1, SOCF_RO },
   4403     { CFGIEf, 1, 2, SOCF_RO },
   4404     { CFGNMFIf, 1, 4, SOCF_RO },
   4405     { ENTCM1IFf, 1, 13, SOCF_RO },
   4406     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   4407     { INITRAMAf, 1, 15, SOCF_RO },
   4408     { INITRAMBf, 1, 16, SOCF_RO },
   4409     { LOCZRAMAf, 1, 17, SOCF_RO },
   4410     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   4411     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   4412     { PARLVRAMf, 1, 21, SOCF_RO },
   4413     { RESERVED_0f, 3, 28, SOCF_LE|SOCF_RO|SOCF_RES },
   4414     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   4415     { SLBTCMSBf, 1, 14, SOCF_RO },
   4416     { TEINITf, 1, 3, SOCF_RO },
   4417     { VINITHIf, 1, 0, SOCF_RO }
   4418 };
   4419 
   4420 #endif
   4421 #if defined(BCM_88202_A0)
   4422 soc_field_info_t soc_UC_0_STATUS_BCM88202_A0r_fields[] = {
   4423     { AUTOLOAD_DONEf, 1, 27, SOCF_RO },
   4424     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   4425     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   4426     { CFGEEf, 1, 1, SOCF_RO },
   4427     { CFGIEf, 1, 2, SOCF_RO },
   4428     { CFGNMFIf, 1, 4, SOCF_RO },
   4429     { ENTCM1IFf, 1, 13, SOCF_RO },
   4430     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   4431     { FIELD_28_30f, 3, 28, SOCF_LE|SOCF_RO },
   4432     { INITRAMAf, 1, 15, SOCF_RO },
   4433     { INITRAMBf, 1, 16, SOCF_RO },
   4434     { LOCZRAMAf, 1, 17, SOCF_RO },
   4435     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   4436     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   4437     { PARLVRAMf, 1, 21, SOCF_RO },
   4438     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   4439     { SLBTCMSBf, 1, 14, SOCF_RO },
   4440     { TEINITf, 1, 3, SOCF_RO },
   4441     { VINITHIf, 1, 0, SOCF_RO }
   4442 };
   4443 
   4444 #endif
   4445 #if defined(BCM_88650_B0)
   4446 soc_field_info_t soc_UC_0_STATUS_BCM88650_B0r_fields[] = {
   4447     { AUTOLOAD_DONEf, 1, 27, SOCF_RO },
   4448     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   4449     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   4450     { CFGEEf, 1, 1, SOCF_RO },
   4451     { CFGIEf, 1, 2, SOCF_RO },
   4452     { CFGNMFIf, 1, 4, SOCF_RO },
   4453     { ENTCM1IFf, 1, 13, SOCF_RO },
   4454     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   4455     { INITRAMAf, 1, 15, SOCF_RO },
   4456     { INITRAMBf, 1, 16, SOCF_RO },
   4457     { LOCZRAMAf, 1, 17, SOCF_RO },
   4458     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   4459     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   4460     { PARLVRAMf, 1, 21, SOCF_RO },
   4461     { RESERVED_0f, 3, 28, SOCF_LE|SOCF_RO|SOCF_RES },
   4462     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   4463     { SLBTCMSBf, 1, 14, SOCF_RO },
   4464     { TEINITf, 1, 3, SOCF_RO },
   4465     { VINITHIf, 1, 0, SOCF_RO }
   4466 };
   4467 
   4468 #endif
   4469 #if defined(BCM_88660_A0)
   4470 soc_field_info_t soc_UC_0_STATUS_BCM88660_A0r_fields[] = {
   4471     { AUTOLOAD_DONEf, 1, 27, SOCF_RO },
   4472     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   4473     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   4474     { CFGEEf, 1, 1, SOCF_RO },
   4475     { CFGIEf, 1, 2, SOCF_RO },
   4476     { CFGNMFIf, 1, 4, SOCF_RO },
   4477     { ENTCM1IFf, 1, 13, SOCF_RO },
   4478     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   4479     { INITRAMAf, 1, 15, SOCF_RO },
   4480     { INITRAMBf, 1, 16, SOCF_RO },
   4481     { LOCZRAMAf, 1, 17, SOCF_RO },
   4482     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   4483     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   4484     { PARLVRAMf, 1, 21, SOCF_RO },
   4485     { RESERVED_0f, 3, 28, SOCF_LE|SOCF_RO|SOCF_RES },
   4486     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   4487     { SLBTCMSBf, 1, 14, SOCF_RO },
   4488     { TEINITf, 1, 3, SOCF_RO },
   4489     { VINITHIf, 1, 0, SOCF_RO }
   4490 };
   4491 
   4492 #endif
   4493 #if defined(BCM_88650_A0)
   4494 soc_field_info_t soc_UC_0_TIMER_INTR_MASKr_fields[] = {
   4495     { RESERVED_0f, 12, 20, SOCF_LE|SOCF_RO|SOCF_RES },
   4496     { UC_0_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, SOCF_SIG },
   4497     { UC_0_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, SOCF_SIG },
   4498     { UC_0_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, SOCF_SIG },
   4499     { UC_0_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, SOCF_SIG },
   4500     { UC_0_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, SOCF_SIG },
   4501     { UC_0_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, SOCF_SIG },
   4502     { UC_0_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, SOCF_SIG },
   4503     { UC_0_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, SOCF_SIG },
   4504     { UC_0_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, SOCF_SIG },
   4505     { UC_0_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, SOCF_SIG },
   4506     { UC_0_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, SOCF_SIG },
   4507     { UC_0_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, SOCF_SIG },
   4508     { UC_0_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, SOCF_SIG },
   4509     { UC_0_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, SOCF_SIG },
   4510     { UC_0_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, SOCF_SIG },
   4511     { UC_0_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, SOCF_SIG },
   4512     { UC_0_MASK_FOR_TIM0_INTR1f, 1, 0, SOCF_SIG },
   4513     { UC_0_MASK_FOR_TIM0_INTR2f, 1, 1, SOCF_SIG },
   4514     { UC_0_MASK_FOR_TIM1_INTR1f, 1, 2, SOCF_SIG },
   4515     { UC_0_MASK_FOR_TIM1_INTR2f, 1, 3, SOCF_SIG }
   4516 };
   4517 
   4518 #endif
   4519 #if defined(BCM_56440_A0)
   4520 soc_field_info_t soc_UC_0_TIMER_INTR_MASK_BCM56440_A0r_fields[] = {
   4521     { RESERVED_0f, 28, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   4522     { UC_0_MASK_FOR_TIM0_INTR1f, 1, 0, 0 },
   4523     { UC_0_MASK_FOR_TIM0_INTR2f, 1, 1, 0 },
   4524     { UC_0_MASK_FOR_TIM1_INTR1f, 1, 2, 0 },
   4525     { UC_0_MASK_FOR_TIM1_INTR2f, 1, 3, 0 }
   4526 };
   4527 
   4528 #endif
   4529 #if defined(BCM_56440_B0)
   4530 soc_field_info_t soc_UC_0_TIMER_INTR_MASK_BCM56440_B0r_fields[] = {
   4531     { RESERVED_0f, 12, 20, SOCF_LE|SOCF_RO|SOCF_RES },
   4532     { UC_0_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, 0 },
   4533     { UC_0_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, 0 },
   4534     { UC_0_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, 0 },
   4535     { UC_0_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, 0 },
   4536     { UC_0_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, 0 },
   4537     { UC_0_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, 0 },
   4538     { UC_0_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, 0 },
   4539     { UC_0_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, 0 },
   4540     { UC_0_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, 0 },
   4541     { UC_0_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, 0 },
   4542     { UC_0_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, 0 },
   4543     { UC_0_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, 0 },
   4544     { UC_0_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, 0 },
   4545     { UC_0_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, 0 },
   4546     { UC_0_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, 0 },
   4547     { UC_0_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, 0 },
   4548     { UC_0_MASK_FOR_TIM0_INTR1f, 1, 0, 0 },
   4549     { UC_0_MASK_FOR_TIM0_INTR2f, 1, 1, 0 },
   4550     { UC_0_MASK_FOR_TIM1_INTR1f, 1, 2, 0 },
   4551     { UC_0_MASK_FOR_TIM1_INTR2f, 1, 3, 0 }
   4552 };
   4553 
   4554 #endif
   4555 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4556     defined(BCM_56860_A0)
   4557 soc_field_info_t soc_UC_0_TIMER_INTR_MASK_BCM56640_A0r_fields[] = {
   4558     { RESERVED_0f, 12, 20, SOCF_LE|SOCF_RO|SOCF_RES },
   4559     { UC_0_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, 0 },
   4560     { UC_0_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, 0 },
   4561     { UC_0_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, 0 },
   4562     { UC_0_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, 0 },
   4563     { UC_0_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, 0 },
   4564     { UC_0_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, 0 },
   4565     { UC_0_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, 0 },
   4566     { UC_0_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, 0 },
   4567     { UC_0_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, 0 },
   4568     { UC_0_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, 0 },
   4569     { UC_0_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, 0 },
   4570     { UC_0_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, 0 },
   4571     { UC_0_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, 0 },
   4572     { UC_0_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, 0 },
   4573     { UC_0_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, 0 },
   4574     { UC_0_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, 0 },
   4575     { UC_0_MASK_FOR_TIM0_INTR1f, 1, 0, 0 },
   4576     { UC_0_MASK_FOR_TIM0_INTR2f, 1, 1, 0 },
   4577     { UC_0_MASK_FOR_TIM1_INTR1f, 1, 2, 0 },
   4578     { UC_0_MASK_FOR_TIM1_INTR2f, 1, 3, 0 }
   4579 };
   4580 
   4581 #endif
   4582 #if defined(BCM_88202_A0)
   4583 soc_field_info_t soc_UC_0_TIMER_INTR_MASK_BCM88202_A0r_fields[] = {
   4584     { FIELD_20_31f, 12, 20, SOCF_LE|SOCF_RO },
   4585     { UC_0_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, SOCF_SIG },
   4586     { UC_0_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, SOCF_SIG },
   4587     { UC_0_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, SOCF_SIG },
   4588     { UC_0_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, SOCF_SIG },
   4589     { UC_0_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, SOCF_SIG },
   4590     { UC_0_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, SOCF_SIG },
   4591     { UC_0_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, SOCF_SIG },
   4592     { UC_0_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, SOCF_SIG },
   4593     { UC_0_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, SOCF_SIG },
   4594     { UC_0_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, SOCF_SIG },
   4595     { UC_0_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, SOCF_SIG },
   4596     { UC_0_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, SOCF_SIG },
   4597     { UC_0_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, SOCF_SIG },
   4598     { UC_0_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, SOCF_SIG },
   4599     { UC_0_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, SOCF_SIG },
   4600     { UC_0_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, SOCF_SIG },
   4601     { UC_0_MASK_FOR_TIM0_INTR1f, 1, 0, SOCF_SIG },
   4602     { UC_0_MASK_FOR_TIM0_INTR2f, 1, 1, SOCF_SIG },
   4603     { UC_0_MASK_FOR_TIM1_INTR1f, 1, 2, SOCF_SIG },
   4604     { UC_0_MASK_FOR_TIM1_INTR2f, 1, 3, SOCF_SIG }
   4605 };
   4606 
   4607 #endif
   4608 #if defined(BCM_88650_B0)
   4609 soc_field_info_t soc_UC_0_TIMER_INTR_MASK_BCM88650_B0r_fields[] = {
   4610     { RESERVED_0f, 12, 20, SOCF_LE|SOCF_RO|SOCF_RES },
   4611     { UC_0_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, SOCF_SIG },
   4612     { UC_0_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, SOCF_SIG },
   4613     { UC_0_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, SOCF_SIG },
   4614     { UC_0_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, SOCF_SIG },
   4615     { UC_0_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, SOCF_SIG },
   4616     { UC_0_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, SOCF_SIG },
   4617     { UC_0_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, SOCF_SIG },
   4618     { UC_0_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, SOCF_SIG },
   4619     { UC_0_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, SOCF_SIG },
   4620     { UC_0_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, SOCF_SIG },
   4621     { UC_0_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, SOCF_SIG },
   4622     { UC_0_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, SOCF_SIG },
   4623     { UC_0_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, SOCF_SIG },
   4624     { UC_0_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, SOCF_SIG },
   4625     { UC_0_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, SOCF_SIG },
   4626     { UC_0_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, SOCF_SIG },
   4627     { UC_0_MASK_FOR_TIM0_INTR1f, 1, 0, SOCF_SIG },
   4628     { UC_0_MASK_FOR_TIM0_INTR2f, 1, 1, SOCF_SIG },
   4629     { UC_0_MASK_FOR_TIM1_INTR1f, 1, 2, SOCF_SIG },
   4630     { UC_0_MASK_FOR_TIM1_INTR2f, 1, 3, SOCF_SIG }
   4631 };
   4632 
   4633 #endif
   4634 #if defined(BCM_88660_A0)
   4635 soc_field_info_t soc_UC_0_TIMER_INTR_MASK_BCM88660_A0r_fields[] = {
   4636     { RESERVED_0f, 12, 20, SOCF_LE|SOCF_RO|SOCF_RES },
   4637     { UC_0_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, SOCF_SIG },
   4638     { UC_0_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, SOCF_SIG },
   4639     { UC_0_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, SOCF_SIG },
   4640     { UC_0_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, SOCF_SIG },
   4641     { UC_0_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, SOCF_SIG },
   4642     { UC_0_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, SOCF_SIG },
   4643     { UC_0_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, SOCF_SIG },
   4644     { UC_0_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, SOCF_SIG },
   4645     { UC_0_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, SOCF_SIG },
   4646     { UC_0_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, SOCF_SIG },
   4647     { UC_0_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, SOCF_SIG },
   4648     { UC_0_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, SOCF_SIG },
   4649     { UC_0_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, SOCF_SIG },
   4650     { UC_0_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, SOCF_SIG },
   4651     { UC_0_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, SOCF_SIG },
   4652     { UC_0_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, SOCF_SIG },
   4653     { UC_0_MASK_FOR_TIM0_INTR1f, 1, 0, SOCF_SIG },
   4654     { UC_0_MASK_FOR_TIM0_INTR2f, 1, 1, SOCF_SIG },
   4655     { UC_0_MASK_FOR_TIM1_INTR1f, 1, 2, SOCF_SIG },
   4656     { UC_0_MASK_FOR_TIM1_INTR2f, 1, 3, SOCF_SIG }
   4657 };
   4658 
   4659 #endif
   4660 #if defined(BCM_88650_A0)
   4661 soc_field_info_t soc_UC_1_CONFIGr_fields[] = {
   4662     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_SIG },
   4663     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_SIG },
   4664     { CFGEEf, 1, 1, SOCF_SIG },
   4665     { CFGIEf, 1, 2, SOCF_SIG },
   4666     { CFGNMFIf, 1, 4, SOCF_SIG },
   4667     { CFG_WDOGINT_MASKf, 1, 27, SOCF_SIG },
   4668     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_SIG },
   4669     { INITRAMAf, 1, 15, SOCF_SIG },
   4670     { INITRAMBf, 1, 16, SOCF_SIG },
   4671     { OVERWRITE_OTP_CONFIGf, 1, 31, SOCF_SIG },
   4672     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_SIG },
   4673     { PARLVRAMf, 1, 21, SOCF_SIG },
   4674     { RESERVED_0f, 3, 28, SOCF_LE|SOCF_RO|SOCF_RES },
   4675     { RESERVED_1f, 1, 0, SOCF_SIG|SOCF_RES },
   4676     { RESERVED_2f, 1, 13, SOCF_SIG|SOCF_RES },
   4677     { RESERVED_3f, 1, 17, SOCF_SIG|SOCF_RES },
   4678     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_SIG },
   4679     { SLBTCMSBf, 1, 14, SOCF_SIG },
   4680     { TEINITf, 1, 3, SOCF_SIG }
   4681 };
   4682 
   4683 #endif
   4684 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4685 soc_field_info_t soc_UC_1_CONFIG_BCM56440_A0r_fields[] = {
   4686     { CFGATCMSZf, 4, 5, SOCF_LE },
   4687     { CFGBTCMSZf, 4, 9, SOCF_LE },
   4688     { CFGEEf, 1, 1, 0 },
   4689     { CFGIEf, 1, 2, 0 },
   4690     { CFGNMFIf, 1, 4, 0 },
   4691     { CFG_WDOGINT_MASKf, 1, 27, 0 },
   4692     { ERRENRAMf, 3, 22, SOCF_LE },
   4693     { INITRAMAf, 1, 15, 0 },
   4694     { INITRAMBf, 1, 16, 0 },
   4695     { OVERWRITE_OTP_CONFIGf, 1, 31, 0 },
   4696     { PARECCENRAMf, 3, 18, SOCF_LE },
   4697     { PARLVRAMf, 1, 21, 0 },
   4698     { RESERVED_0f, 3, 28, SOCF_LE|SOCF_RO|SOCF_RES },
   4699     { RESERVED_1f, 1, 0, SOCF_RES },
   4700     { RESERVED_2f, 1, 13, SOCF_RES },
   4701     { RESERVED_3f, 1, 17, SOCF_RES },
   4702     { RMWENRAMf, 2, 25, SOCF_LE },
   4703     { SLBTCMSBf, 1, 14, 0 },
   4704     { TEINITf, 1, 3, 0 }
   4705 };
   4706 
   4707 #endif
   4708 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4709     defined(BCM_56860_A0)
   4710 soc_field_info_t soc_UC_1_CONFIG_BCM56640_A0r_fields[] = {
   4711     { CFGATCMSZf, 4, 5, SOCF_LE },
   4712     { CFGBTCMSZf, 4, 9, SOCF_LE },
   4713     { CFGEEf, 1, 1, 0 },
   4714     { CFGIEf, 1, 2, 0 },
   4715     { CFGNMFIf, 1, 4, 0 },
   4716     { CFG_WDOGINT_MASKf, 1, 27, 0 },
   4717     { ERRENRAMf, 3, 22, SOCF_LE },
   4718     { INITRAMAf, 1, 15, 0 },
   4719     { INITRAMBf, 1, 16, 0 },
   4720     { OVERWRITE_OTP_CONFIGf, 1, 31, 0 },
   4721     { PARECCENRAMf, 3, 18, SOCF_LE },
   4722     { PARLVRAMf, 1, 21, 0 },
   4723     { RESERVED_0f, 3, 28, SOCF_LE|SOCF_RO|SOCF_RES },
   4724     { RESERVED_1f, 1, 0, SOCF_RES },
   4725     { RESERVED_2f, 1, 13, SOCF_RES },
   4726     { RESERVED_3f, 1, 17, SOCF_RES },
   4727     { RMWENRAMf, 2, 25, SOCF_LE },
   4728     { SLBTCMSBf, 1, 14, 0 },
   4729     { TEINITf, 1, 3, 0 }
   4730 };
   4731 
   4732 #endif
   4733 #if defined(BCM_88202_A0)
   4734 soc_field_info_t soc_UC_1_CONFIG_BCM88202_A0r_fields[] = {
   4735     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_SIG },
   4736     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_SIG },
   4737     { CFGEEf, 1, 1, SOCF_SIG },
   4738     { CFGIEf, 1, 2, SOCF_SIG },
   4739     { CFGNMFIf, 1, 4, SOCF_SIG },
   4740     { CFG_WDOGINT_MASKf, 1, 27, SOCF_SIG },
   4741     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_SIG },
   4742     { FIELD_0_0f, 1, 0, SOCF_SIG },
   4743     { FIELD_13_13f, 1, 13, SOCF_SIG },
   4744     { FIELD_17_17f, 1, 17, SOCF_SIG },
   4745     { FIELD_28_30f, 3, 28, SOCF_LE|SOCF_RO },
   4746     { INITRAMAf, 1, 15, SOCF_SIG },
   4747     { INITRAMBf, 1, 16, SOCF_SIG },
   4748     { OVERWRITE_OTP_CONFIGf, 1, 31, SOCF_SIG },
   4749     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_SIG },
   4750     { PARLVRAMf, 1, 21, SOCF_SIG },
   4751     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_SIG },
   4752     { SLBTCMSBf, 1, 14, SOCF_SIG },
   4753     { TEINITf, 1, 3, SOCF_SIG }
   4754 };
   4755 
   4756 #endif
   4757 #if defined(BCM_88650_B0)
   4758 soc_field_info_t soc_UC_1_CONFIG_BCM88650_B0r_fields[] = {
   4759     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_SIG },
   4760     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_SIG },
   4761     { CFGEEf, 1, 1, SOCF_SIG },
   4762     { CFGIEf, 1, 2, SOCF_SIG },
   4763     { CFGNMFIf, 1, 4, SOCF_SIG },
   4764     { CFG_WDOGINT_MASKf, 1, 27, SOCF_SIG },
   4765     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_SIG },
   4766     { INITRAMAf, 1, 15, SOCF_SIG },
   4767     { INITRAMBf, 1, 16, SOCF_SIG },
   4768     { OVERWRITE_OTP_CONFIGf, 1, 31, SOCF_SIG },
   4769     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_SIG },
   4770     { PARLVRAMf, 1, 21, SOCF_SIG },
   4771     { RESERVED_0f, 3, 28, SOCF_LE|SOCF_RO|SOCF_RES },
   4772     { RESERVED_1f, 1, 0, SOCF_SIG|SOCF_RES },
   4773     { RESERVED_2f, 1, 13, SOCF_SIG|SOCF_RES },
   4774     { RESERVED_3f, 1, 17, SOCF_SIG|SOCF_RES },
   4775     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_SIG },
   4776     { SLBTCMSBf, 1, 14, SOCF_SIG },
   4777     { TEINITf, 1, 3, SOCF_SIG }
   4778 };
   4779 
   4780 #endif
   4781 #if defined(BCM_88660_A0)
   4782 soc_field_info_t soc_UC_1_CONFIG_BCM88660_A0r_fields[] = {
   4783     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_SIG },
   4784     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_SIG },
   4785     { CFGEEf, 1, 1, SOCF_SIG },
   4786     { CFGIEf, 1, 2, SOCF_SIG },
   4787     { CFGNMFIf, 1, 4, SOCF_SIG },
   4788     { CFG_WDOGINT_MASKf, 1, 27, SOCF_SIG },
   4789     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_SIG },
   4790     { INITRAMAf, 1, 15, SOCF_SIG },
   4791     { INITRAMBf, 1, 16, SOCF_SIG },
   4792     { OVERWRITE_OTP_CONFIGf, 1, 31, SOCF_SIG },
   4793     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_SIG },
   4794     { PARLVRAMf, 1, 21, SOCF_SIG },
   4795     { RESERVED_0f, 3, 28, SOCF_LE|SOCF_RO|SOCF_RES },
   4796     { RESERVED_1f, 1, 0, SOCF_SIG|SOCF_RES },
   4797     { RESERVED_2f, 1, 13, SOCF_SIG|SOCF_RES },
   4798     { RESERVED_3f, 1, 17, SOCF_SIG|SOCF_RES },
   4799     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_SIG },
   4800     { SLBTCMSBf, 1, 14, SOCF_SIG },
   4801     { TEINITf, 1, 3, SOCF_SIG }
   4802 };
   4803 
   4804 #endif
   4805 #if defined(BCM_88650_A0)
   4806 soc_field_info_t soc_UC_1_DEBUG_CONFIGr_fields[] = {
   4807     { DBGENf, 1, 0, SOCF_SIG },
   4808     { DBGRESTARTf, 1, 4, SOCF_SIG },
   4809     { DBG_UNLOCKf, 1, 5, SOCF_SIG },
   4810     { EDBGRQf, 1, 2, SOCF_SIG },
   4811     { NIDENf, 1, 1, SOCF_SIG },
   4812     { PCLKENDBGf, 1, 3, SOCF_SIG },
   4813     { RESERVED_0f, 26, 6, SOCF_LE|SOCF_RO|SOCF_RES }
   4814 };
   4815 
   4816 #endif
   4817 #if defined(BCM_88202_A0)
   4818 soc_field_info_t soc_UC_1_DEBUG_CONFIG_BCM88202_A0r_fields[] = {
   4819     { DBGENf, 1, 0, SOCF_SIG },
   4820     { DBGRESTARTf, 1, 4, SOCF_SIG },
   4821     { DBG_UNLOCKf, 1, 5, SOCF_SIG },
   4822     { EDBGRQf, 1, 2, SOCF_SIG },
   4823     { FIELD_6_31f, 26, 6, SOCF_LE|SOCF_RO },
   4824     { NIDENf, 1, 1, SOCF_SIG },
   4825     { PCLKENDBGf, 1, 3, SOCF_SIG }
   4826 };
   4827 
   4828 #endif
   4829 #if defined(BCM_88650_B0)
   4830 soc_field_info_t soc_UC_1_DEBUG_CONFIG_BCM88650_B0r_fields[] = {
   4831     { DBGENf, 1, 0, SOCF_SIG },
   4832     { DBGRESTARTf, 1, 4, SOCF_SIG },
   4833     { DBG_UNLOCKf, 1, 5, SOCF_SIG },
   4834     { EDBGRQf, 1, 2, SOCF_SIG },
   4835     { NIDENf, 1, 1, SOCF_SIG },
   4836     { PCLKENDBGf, 1, 3, SOCF_SIG },
   4837     { RESERVED_0f, 26, 6, SOCF_LE|SOCF_RO|SOCF_RES }
   4838 };
   4839 
   4840 #endif
   4841 #if defined(BCM_88660_A0)
   4842 soc_field_info_t soc_UC_1_DEBUG_CONFIG_BCM88660_A0r_fields[] = {
   4843     { DBGENf, 1, 0, SOCF_SIG },
   4844     { DBGRESTARTf, 1, 4, SOCF_SIG },
   4845     { DBG_UNLOCKf, 1, 5, SOCF_SIG },
   4846     { EDBGRQf, 1, 2, SOCF_SIG },
   4847     { NIDENf, 1, 1, SOCF_SIG },
   4848     { PCLKENDBGf, 1, 3, SOCF_SIG },
   4849     { RESERVED_0f, 26, 6, SOCF_LE|SOCF_RO|SOCF_RES }
   4850 };
   4851 
   4852 #endif
   4853 #if defined(BCM_88650_A0)
   4854 soc_field_info_t soc_UC_1_DEBUG_STATUSr_fields[] = {
   4855     { CPUHALT_Nf, 1, 4, SOCF_RO },
   4856     { DBGACKf, 1, 0, SOCF_RO },
   4857     { DBGRESTARTEDf, 1, 6, SOCF_RO },
   4858     { DBGRSTREQf, 1, 1, SOCF_RO },
   4859     { RESERVED_0f, 25, 7, SOCF_LE|SOCF_RO|SOCF_RES },
   4860     { RESET_Nf, 1, 2, SOCF_RO },
   4861     { STANDBYWFIf, 1, 5, SOCF_RO },
   4862     { SYSPORESET_Nf, 1, 3, SOCF_RO }
   4863 };
   4864 
   4865 #endif
   4866 #if defined(BCM_88202_A0)
   4867 soc_field_info_t soc_UC_1_DEBUG_STATUS_BCM88202_A0r_fields[] = {
   4868     { CPUHALT_Nf, 1, 4, SOCF_RO },
   4869     { DBGACKf, 1, 0, SOCF_RO },
   4870     { DBGRESTARTEDf, 1, 6, SOCF_RO },
   4871     { DBGRSTREQf, 1, 1, SOCF_RO },
   4872     { FIELD_7_31f, 25, 7, SOCF_LE|SOCF_RO },
   4873     { RESET_Nf, 1, 2, SOCF_RO },
   4874     { STANDBYWFIf, 1, 5, SOCF_RO },
   4875     { SYSPORESET_Nf, 1, 3, SOCF_RO }
   4876 };
   4877 
   4878 #endif
   4879 #if defined(BCM_88650_B0)
   4880 soc_field_info_t soc_UC_1_DEBUG_STATUS_BCM88650_B0r_fields[] = {
   4881     { CPUHALT_Nf, 1, 4, SOCF_RO },
   4882     { DBGACKf, 1, 0, SOCF_RO },
   4883     { DBGRESTARTEDf, 1, 6, SOCF_RO },
   4884     { DBGRSTREQf, 1, 1, SOCF_RO },
   4885     { RESERVED_0f, 25, 7, SOCF_LE|SOCF_RO|SOCF_RES },
   4886     { RESET_Nf, 1, 2, SOCF_RO },
   4887     { STANDBYWFIf, 1, 5, SOCF_RO },
   4888     { SYSPORESET_Nf, 1, 3, SOCF_RO }
   4889 };
   4890 
   4891 #endif
   4892 #if defined(BCM_88660_A0)
   4893 soc_field_info_t soc_UC_1_DEBUG_STATUS_BCM88660_A0r_fields[] = {
   4894     { CPUHALT_Nf, 1, 4, SOCF_RO },
   4895     { DBGACKf, 1, 0, SOCF_RO },
   4896     { DBGRESTARTEDf, 1, 6, SOCF_RO },
   4897     { DBGRSTREQf, 1, 1, SOCF_RO },
   4898     { RESERVED_0f, 25, 7, SOCF_LE|SOCF_RO|SOCF_RES },
   4899     { RESET_Nf, 1, 2, SOCF_RO },
   4900     { STANDBYWFIf, 1, 5, SOCF_RO },
   4901     { SYSPORESET_Nf, 1, 3, SOCF_RO }
   4902 };
   4903 
   4904 #endif
   4905 #if defined(BCM_88650_A0)
   4906 soc_field_info_t soc_UC_1_RST_CONTROLr_fields[] = {
   4907     { CORE_RESET_Nf, 1, 0, SOCF_SIG },
   4908     { CPUHALT_Nf, 1, 2, SOCF_SIG },
   4909     { DEBUG_RESET_Nf, 1, 3, SOCF_SIG },
   4910     { RESERVED_0f, 28, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   4911     { SYS_PORESET_Nf, 1, 1, SOCF_SIG }
   4912 };
   4913 
   4914 #endif
   4915 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4916 soc_field_info_t soc_UC_1_RST_CONTROL_BCM56440_A0r_fields[] = {
   4917     { CORE_RESET_Nf, 1, 0, 0 },
   4918     { CPUHALT_Nf, 1, 2, 0 },
   4919     { DEBUG_RESET_Nf, 1, 3, 0 },
   4920     { RESERVED_0f, 28, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   4921     { SYS_PORESET_Nf, 1, 1, 0 }
   4922 };
   4923 
   4924 #endif
   4925 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4926     defined(BCM_56860_A0)
   4927 soc_field_info_t soc_UC_1_RST_CONTROL_BCM56640_A0r_fields[] = {
   4928     { CORE_RESET_Nf, 1, 0, 0 },
   4929     { CPUHALT_Nf, 1, 2, 0 },
   4930     { DEBUG_RESET_Nf, 1, 3, 0 },
   4931     { RESERVED_0f, 28, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   4932     { SYS_PORESET_Nf, 1, 1, 0 }
   4933 };
   4934 
   4935 #endif
   4936 #if defined(BCM_88202_A0)
   4937 soc_field_info_t soc_UC_1_RST_CONTROL_BCM88202_A0r_fields[] = {
   4938     { CORE_RESET_Nf, 1, 0, SOCF_SIG },
   4939     { CPUHALT_Nf, 1, 2, SOCF_SIG },
   4940     { DEBUG_RESET_Nf, 1, 3, SOCF_SIG },
   4941     { FIELD_4_31f, 28, 4, SOCF_LE|SOCF_RO },
   4942     { SYS_PORESET_Nf, 1, 1, SOCF_SIG }
   4943 };
   4944 
   4945 #endif
   4946 #if defined(BCM_88650_B0)
   4947 soc_field_info_t soc_UC_1_RST_CONTROL_BCM88650_B0r_fields[] = {
   4948     { CORE_RESET_Nf, 1, 0, SOCF_SIG },
   4949     { CPUHALT_Nf, 1, 2, SOCF_SIG },
   4950     { DEBUG_RESET_Nf, 1, 3, SOCF_SIG },
   4951     { RESERVED_0f, 28, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   4952     { SYS_PORESET_Nf, 1, 1, SOCF_SIG }
   4953 };
   4954 
   4955 #endif
   4956 #if defined(BCM_88660_A0)
   4957 soc_field_info_t soc_UC_1_RST_CONTROL_BCM88660_A0r_fields[] = {
   4958     { CORE_RESET_Nf, 1, 0, SOCF_SIG },
   4959     { CPUHALT_Nf, 1, 2, SOCF_SIG },
   4960     { DEBUG_RESET_Nf, 1, 3, SOCF_SIG },
   4961     { RESERVED_0f, 28, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   4962     { SYS_PORESET_Nf, 1, 1, SOCF_SIG }
   4963 };
   4964 
   4965 #endif
   4966 #if defined(BCM_88650_A0)
   4967 soc_field_info_t soc_UC_1_STATUSr_fields[] = {
   4968     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   4969     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   4970     { CFGEEf, 1, 1, SOCF_RO },
   4971     { CFGIEf, 1, 2, SOCF_RO },
   4972     { CFGNMFIf, 1, 4, SOCF_RO },
   4973     { ENTCM1IFf, 1, 13, SOCF_RO },
   4974     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   4975     { INITRAMAf, 1, 15, SOCF_RO },
   4976     { INITRAMBf, 1, 16, SOCF_RO },
   4977     { LOCZRAMAf, 1, 17, SOCF_RO },
   4978     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   4979     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   4980     { PARLVRAMf, 1, 21, SOCF_RO },
   4981     { RESERVED_0f, 4, 27, SOCF_LE|SOCF_RO|SOCF_RES },
   4982     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   4983     { SLBTCMSBf, 1, 14, SOCF_RO },
   4984     { TEINITf, 1, 3, SOCF_RO },
   4985     { VINITHIf, 1, 0, SOCF_RO }
   4986 };
   4987 
   4988 #endif
   4989 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4990 soc_field_info_t soc_UC_1_STATUS_BCM56440_A0r_fields[] = {
   4991     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   4992     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   4993     { CFGEEf, 1, 1, SOCF_RO },
   4994     { CFGIEf, 1, 2, SOCF_RO },
   4995     { CFGNMFIf, 1, 4, SOCF_RO },
   4996     { ENTCM1IFf, 1, 13, SOCF_RO },
   4997     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   4998     { INITRAMAf, 1, 15, SOCF_RO },
   4999     { INITRAMBf, 1, 16, SOCF_RO },
   5000     { LOCZRAMAf, 1, 17, SOCF_RO },
   5001     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   5002     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   5003     { PARLVRAMf, 1, 21, SOCF_RO },
   5004     { RESERVED_0f, 4, 27, SOCF_LE|SOCF_RO|SOCF_RES },
   5005     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   5006     { SLBTCMSBf, 1, 14, SOCF_RO },
   5007     { TEINITf, 1, 3, SOCF_RO },
   5008     { VINITHIf, 1, 0, SOCF_RO }
   5009 };
   5010 
   5011 #endif
   5012 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   5013     defined(BCM_56860_A0)
   5014 soc_field_info_t soc_UC_1_STATUS_BCM56640_A0r_fields[] = {
   5015     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   5016     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   5017     { CFGEEf, 1, 1, SOCF_RO },
   5018     { CFGIEf, 1, 2, SOCF_RO },
   5019     { CFGNMFIf, 1, 4, SOCF_RO },
   5020     { ENTCM1IFf, 1, 13, SOCF_RO },
   5021     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   5022     { INITRAMAf, 1, 15, SOCF_RO },
   5023     { INITRAMBf, 1, 16, SOCF_RO },
   5024     { LOCZRAMAf, 1, 17, SOCF_RO },
   5025     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   5026     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   5027     { PARLVRAMf, 1, 21, SOCF_RO },
   5028     { RESERVED_0f, 4, 27, SOCF_LE|SOCF_RO|SOCF_RES },
   5029     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   5030     { SLBTCMSBf, 1, 14, SOCF_RO },
   5031     { TEINITf, 1, 3, SOCF_RO },
   5032     { VINITHIf, 1, 0, SOCF_RO }
   5033 };
   5034 
   5035 #endif
   5036 #if defined(BCM_88202_A0)
   5037 soc_field_info_t soc_UC_1_STATUS_BCM88202_A0r_fields[] = {
   5038     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   5039     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   5040     { CFGEEf, 1, 1, SOCF_RO },
   5041     { CFGIEf, 1, 2, SOCF_RO },
   5042     { CFGNMFIf, 1, 4, SOCF_RO },
   5043     { ENTCM1IFf, 1, 13, SOCF_RO },
   5044     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   5045     { FIELD_27_30f, 4, 27, SOCF_LE|SOCF_RO },
   5046     { INITRAMAf, 1, 15, SOCF_RO },
   5047     { INITRAMBf, 1, 16, SOCF_RO },
   5048     { LOCZRAMAf, 1, 17, SOCF_RO },
   5049     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   5050     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   5051     { PARLVRAMf, 1, 21, SOCF_RO },
   5052     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   5053     { SLBTCMSBf, 1, 14, SOCF_RO },
   5054     { TEINITf, 1, 3, SOCF_RO },
   5055     { VINITHIf, 1, 0, SOCF_RO }
   5056 };
   5057 
   5058 #endif
   5059 #if defined(BCM_88650_B0)
   5060 soc_field_info_t soc_UC_1_STATUS_BCM88650_B0r_fields[] = {
   5061     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   5062     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   5063     { CFGEEf, 1, 1, SOCF_RO },
   5064     { CFGIEf, 1, 2, SOCF_RO },
   5065     { CFGNMFIf, 1, 4, SOCF_RO },
   5066     { ENTCM1IFf, 1, 13, SOCF_RO },
   5067     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   5068     { INITRAMAf, 1, 15, SOCF_RO },
   5069     { INITRAMBf, 1, 16, SOCF_RO },
   5070     { LOCZRAMAf, 1, 17, SOCF_RO },
   5071     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   5072     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   5073     { PARLVRAMf, 1, 21, SOCF_RO },
   5074     { RESERVED_0f, 4, 27, SOCF_LE|SOCF_RO|SOCF_RES },
   5075     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   5076     { SLBTCMSBf, 1, 14, SOCF_RO },
   5077     { TEINITf, 1, 3, SOCF_RO },
   5078     { VINITHIf, 1, 0, SOCF_RO }
   5079 };
   5080 
   5081 #endif
   5082 #if defined(BCM_88660_A0)
   5083 soc_field_info_t soc_UC_1_STATUS_BCM88660_A0r_fields[] = {
   5084     { CFGATCMSZf, 4, 5, SOCF_LE|SOCF_RO },
   5085     { CFGBTCMSZf, 4, 9, SOCF_LE|SOCF_RO },
   5086     { CFGEEf, 1, 1, SOCF_RO },
   5087     { CFGIEf, 1, 2, SOCF_RO },
   5088     { CFGNMFIf, 1, 4, SOCF_RO },
   5089     { ENTCM1IFf, 1, 13, SOCF_RO },
   5090     { ERRENRAMf, 3, 22, SOCF_LE|SOCF_RO },
   5091     { INITRAMAf, 1, 15, SOCF_RO },
   5092     { INITRAMBf, 1, 16, SOCF_RO },
   5093     { LOCZRAMAf, 1, 17, SOCF_RO },
   5094     { OVERWRITE_OTP_STATUSf, 1, 31, SOCF_RO },
   5095     { PARECCENRAMf, 3, 18, SOCF_LE|SOCF_RO },
   5096     { PARLVRAMf, 1, 21, SOCF_RO },
   5097     { RESERVED_0f, 4, 27, SOCF_LE|SOCF_RO|SOCF_RES },
   5098     { RMWENRAMf, 2, 25, SOCF_LE|SOCF_RO },
   5099     { SLBTCMSBf, 1, 14, SOCF_RO },
   5100     { TEINITf, 1, 3, SOCF_RO },
   5101     { VINITHIf, 1, 0, SOCF_RO }
   5102 };
   5103 
   5104 #endif
   5105 #if defined(BCM_88650_A0)
   5106 soc_field_info_t soc_UC_1_TIMER_INTR_MASKr_fields[] = {
   5107     { RESERVED_0f, 12, 20, SOCF_LE|SOCF_RO|SOCF_RES },
   5108     { UC_1_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, SOCF_SIG },
   5109     { UC_1_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, SOCF_SIG },
   5110     { UC_1_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, SOCF_SIG },
   5111     { UC_1_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, SOCF_SIG },
   5112     { UC_1_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, SOCF_SIG },
   5113     { UC_1_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, SOCF_SIG },
   5114     { UC_1_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, SOCF_SIG },
   5115     { UC_1_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, SOCF_SIG },
   5116     { UC_1_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, SOCF_SIG },
   5117     { UC_1_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, SOCF_SIG },
   5118     { UC_1_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, SOCF_SIG },
   5119     { UC_1_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, SOCF_SIG },
   5120     { UC_1_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, SOCF_SIG },
   5121     { UC_1_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, SOCF_SIG },
   5122     { UC_1_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, SOCF_SIG },
   5123     { UC_1_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, SOCF_SIG },
   5124     { UC_1_MASK_FOR_TIM0_INTR1f, 1, 0, SOCF_SIG },
   5125     { UC_1_MASK_FOR_TIM0_INTR2f, 1, 1, SOCF_SIG },
   5126     { UC_1_MASK_FOR_TIM1_INTR1f, 1, 2, SOCF_SIG },
   5127     { UC_1_MASK_FOR_TIM1_INTR2f, 1, 3, SOCF_SIG }
   5128 };
   5129 
   5130 #endif
   5131 #if defined(BCM_56440_A0)
   5132 soc_field_info_t soc_UC_1_TIMER_INTR_MASK_BCM56440_A0r_fields[] = {
   5133     { RESERVED_0f, 28, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   5134     { UC_1_MASK_FOR_TIM0_INTR1f, 1, 0, 0 },
   5135     { UC_1_MASK_FOR_TIM0_INTR2f, 1, 1, 0 },
   5136     { UC_1_MASK_FOR_TIM1_INTR1f, 1, 2, 0 },
   5137     { UC_1_MASK_FOR_TIM1_INTR2f, 1, 3, 0 }
   5138 };
   5139 
   5140 #endif
   5141 #if defined(BCM_56440_B0)
   5142 soc_field_info_t soc_UC_1_TIMER_INTR_MASK_BCM56440_B0r_fields[] = {
   5143     { RESERVED_0f, 12, 20, SOCF_LE|SOCF_RO|SOCF_RES },
   5144     { UC_1_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, 0 },
   5145     { UC_1_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, 0 },
   5146     { UC_1_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, 0 },
   5147     { UC_1_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, 0 },
   5148     { UC_1_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, 0 },
   5149     { UC_1_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, 0 },
   5150     { UC_1_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, 0 },
   5151     { UC_1_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, 0 },
   5152     { UC_1_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, 0 },
   5153     { UC_1_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, 0 },
   5154     { UC_1_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, 0 },
   5155     { UC_1_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, 0 },
   5156     { UC_1_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, 0 },
   5157     { UC_1_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, 0 },
   5158     { UC_1_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, 0 },
   5159     { UC_1_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, 0 },
   5160     { UC_1_MASK_FOR_TIM0_INTR1f, 1, 0, 0 },
   5161     { UC_1_MASK_FOR_TIM0_INTR2f, 1, 1, 0 },
   5162     { UC_1_MASK_FOR_TIM1_INTR1f, 1, 2, 0 },
   5163     { UC_1_MASK_FOR_TIM1_INTR2f, 1, 3, 0 }
   5164 };
   5165 
   5166 #endif
   5167 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   5168     defined(BCM_56860_A0)
   5169 soc_field_info_t soc_UC_1_TIMER_INTR_MASK_BCM56640_A0r_fields[] = {
   5170     { RESERVED_0f, 12, 20, SOCF_LE|SOCF_RO|SOCF_RES },
   5171     { UC_1_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, 0 },
   5172     { UC_1_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, 0 },
   5173     { UC_1_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, 0 },
   5174     { UC_1_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, 0 },
   5175     { UC_1_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, 0 },
   5176     { UC_1_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, 0 },
   5177     { UC_1_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, 0 },
   5178     { UC_1_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, 0 },
   5179     { UC_1_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, 0 },
   5180     { UC_1_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, 0 },
   5181     { UC_1_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, 0 },
   5182     { UC_1_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, 0 },
   5183     { UC_1_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, 0 },
   5184     { UC_1_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, 0 },
   5185     { UC_1_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, 0 },
   5186     { UC_1_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, 0 },
   5187     { UC_1_MASK_FOR_TIM0_INTR1f, 1, 0, 0 },
   5188     { UC_1_MASK_FOR_TIM0_INTR2f, 1, 1, 0 },
   5189     { UC_1_MASK_FOR_TIM1_INTR1f, 1, 2, 0 },
   5190     { UC_1_MASK_FOR_TIM1_INTR2f, 1, 3, 0 }
   5191 };
   5192 
   5193 #endif
   5194 #if defined(BCM_88202_A0)
   5195 soc_field_info_t soc_UC_1_TIMER_INTR_MASK_BCM88202_A0r_fields[] = {
   5196     { FIELD_20_31f, 12, 20, SOCF_LE|SOCF_RO },
   5197     { UC_1_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, SOCF_SIG },
   5198     { UC_1_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, SOCF_SIG },
   5199     { UC_1_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, SOCF_SIG },
   5200     { UC_1_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, SOCF_SIG },
   5201     { UC_1_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, SOCF_SIG },
   5202     { UC_1_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, SOCF_SIG },
   5203     { UC_1_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, SOCF_SIG },
   5204     { UC_1_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, SOCF_SIG },
   5205     { UC_1_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, SOCF_SIG },
   5206     { UC_1_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, SOCF_SIG },
   5207     { UC_1_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, SOCF_SIG },
   5208     { UC_1_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, SOCF_SIG },
   5209     { UC_1_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, SOCF_SIG },
   5210     { UC_1_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, SOCF_SIG },
   5211     { UC_1_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, SOCF_SIG },
   5212     { UC_1_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, SOCF_SIG },
   5213     { UC_1_MASK_FOR_TIM0_INTR1f, 1, 0, SOCF_SIG },
   5214     { UC_1_MASK_FOR_TIM0_INTR2f, 1, 1, SOCF_SIG },
   5215     { UC_1_MASK_FOR_TIM1_INTR1f, 1, 2, SOCF_SIG },
   5216     { UC_1_MASK_FOR_TIM1_INTR2f, 1, 3, SOCF_SIG }
   5217 };
   5218 
   5219 #endif
   5220 #if defined(BCM_88650_B0)
   5221 soc_field_info_t soc_UC_1_TIMER_INTR_MASK_BCM88650_B0r_fields[] = {
   5222     { RESERVED_0f, 12, 20, SOCF_LE|SOCF_RO|SOCF_RES },
   5223     { UC_1_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, SOCF_SIG },
   5224     { UC_1_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, SOCF_SIG },
   5225     { UC_1_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, SOCF_SIG },
   5226     { UC_1_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, SOCF_SIG },
   5227     { UC_1_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, SOCF_SIG },
   5228     { UC_1_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, SOCF_SIG },
   5229     { UC_1_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, SOCF_SIG },
   5230     { UC_1_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, SOCF_SIG },
   5231     { UC_1_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, SOCF_SIG },
   5232     { UC_1_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, SOCF_SIG },
   5233     { UC_1_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, SOCF_SIG },
   5234     { UC_1_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, SOCF_SIG },
   5235     { UC_1_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, SOCF_SIG },
   5236     { UC_1_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, SOCF_SIG },
   5237     { UC_1_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, SOCF_SIG },
   5238     { UC_1_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, SOCF_SIG },
   5239     { UC_1_MASK_FOR_TIM0_INTR1f, 1, 0, SOCF_SIG },
   5240     { UC_1_MASK_FOR_TIM0_INTR2f, 1, 1, SOCF_SIG },
   5241     { UC_1_MASK_FOR_TIM1_INTR1f, 1, 2, SOCF_SIG },
   5242     { UC_1_MASK_FOR_TIM1_INTR2f, 1, 3, SOCF_SIG }
   5243 };
   5244 
   5245 #endif
   5246 #if defined(BCM_88660_A0)
   5247 soc_field_info_t soc_UC_1_TIMER_INTR_MASK_BCM88660_A0r_fields[] = {
   5248     { RESERVED_0f, 12, 20, SOCF_LE|SOCF_RO|SOCF_RES },
   5249     { UC_1_MASK_FOR_SRAM_0_ECC_COR_1B_INTRf, 1, 4, SOCF_SIG },
   5250     { UC_1_MASK_FOR_SRAM_0_ECC_DET_2B_INTRf, 1, 5, SOCF_SIG },
   5251     { UC_1_MASK_FOR_SRAM_1_ECC_COR_1B_INTRf, 1, 6, SOCF_SIG },
   5252     { UC_1_MASK_FOR_SRAM_1_ECC_DET_2B_INTRf, 1, 7, SOCF_SIG },
   5253     { UC_1_MASK_FOR_SRAM_2_ECC_COR_1B_INTRf, 1, 8, SOCF_SIG },
   5254     { UC_1_MASK_FOR_SRAM_2_ECC_DET_2B_INTRf, 1, 9, SOCF_SIG },
   5255     { UC_1_MASK_FOR_SRAM_3_ECC_COR_1B_INTRf, 1, 10, SOCF_SIG },
   5256     { UC_1_MASK_FOR_SRAM_3_ECC_DET_2B_INTRf, 1, 11, SOCF_SIG },
   5257     { UC_1_MASK_FOR_SRAM_4_ECC_COR_1B_INTRf, 1, 12, SOCF_SIG },
   5258     { UC_1_MASK_FOR_SRAM_4_ECC_DET_2B_INTRf, 1, 13, SOCF_SIG },
   5259     { UC_1_MASK_FOR_SRAM_5_ECC_COR_1B_INTRf, 1, 14, SOCF_SIG },
   5260     { UC_1_MASK_FOR_SRAM_5_ECC_DET_2B_INTRf, 1, 15, SOCF_SIG },
   5261     { UC_1_MASK_FOR_SRAM_6_ECC_COR_1B_INTRf, 1, 16, SOCF_SIG },
   5262     { UC_1_MASK_FOR_SRAM_6_ECC_DET_2B_INTRf, 1, 17, SOCF_SIG },
   5263     { UC_1_MASK_FOR_SRAM_7_ECC_COR_1B_INTRf, 1, 18, SOCF_SIG },
   5264     { UC_1_MASK_FOR_SRAM_7_ECC_DET_2B_INTRf, 1, 19, SOCF_SIG },
   5265     { UC_1_MASK_FOR_TIM0_INTR1f, 1, 0, SOCF_SIG },
   5266     { UC_1_MASK_FOR_TIM0_INTR2f, 1, 1, SOCF_SIG },
   5267     { UC_1_MASK_FOR_TIM1_INTR1f, 1, 2, SOCF_SIG },
   5268     { UC_1_MASK_FOR_TIM1_INTR2f, 1, 3, SOCF_SIG }
   5269 };
   5270 
   5271 #endif
   5272 #if defined(BCM_56370_A0)
   5273 soc_field_info_t soc_UC_HG_QUEUE_MODEr_fields[] = {
   5274     { BIT_WIDTHf, 1, 0, 0 },
   5275     { QUEUE_MODEf, 1, 0, 0 }
   5276 };
   5277 
   5278 #endif
   5279 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   5280     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
   5281     defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   5282     defined(BCM_56860_A0)
   5283 soc_field_info_t soc_UDF_CAM_DBGCTRLr_fields[] = {
   5284     { BIST_ENf, 1, 0, SOCF_RES },
   5285     { DEBUG_ENf, 1, 1, SOCF_RES },
   5286     { TMf, 11, 2, SOCF_LE|SOCF_RES }
   5287 };
   5288 
   5289 #endif
   5290 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   5291     defined(BCM_56670_A0) || defined(BCM_56670_B0) || \
   5292     defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5293 soc_field_info_t soc_UDF_CAM_DBGCTRL_BCM56960_A0r_fields[] = {
   5294     { BIST_ENf, 1, 0, SOCF_RES },
   5295     { DEBUG_ENf, 1, 1, SOCF_RES },
   5296     { TMf, 11, 2, SOCF_LE|SOCF_RES }
   5297 };
   5298 
   5299 #endif
   5300 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   5301     defined(BCM_56224_A0) || defined(BCM_56224_B0) || \
   5302     defined(BCM_56314_A0) || defined(BCM_56334_A0) || \
   5303     defined(BCM_56334_B0) || defined(BCM_56504_B0) || \
   5304     defined(BCM_56514_A0) || defined(BCM_56624_A0) || \
   5305     defined(BCM_56624_B0) || defined(BCM_56680_A0) || \
   5306     defined(BCM_56680_B0) || defined(BCM_56725_A0) || \
   5307     defined(BCM_56800_A0) || defined(BCM_56820_A0)
   5308 soc_field_info_t soc_UDF_ETHERTYPE_MATCHr_fields[] = {
   5309     { ENABLEf, 1, 19, 0 },
   5310     { ETHERTYPEf, 16, 0, SOCF_LE },
   5311     { L2_PACKET_FORMATf, 2, 17, SOCF_LE },
   5312     { RESERVED0f, 1, 16, SOCF_RES }
   5313 };
   5314 
   5315 #endif
   5316 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5317     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   5318     defined(BCM_56160_A0)
   5319 soc_field_info_t soc_UDF_ETHERTYPE_MATCH_BCM53400_A0r_fields[] = {
   5320     { ENABLEf, 1, 19, 0 },
   5321     { ETHERTYPEf, 16, 0, SOCF_LE },
   5322     { L2_PACKET_FORMATf, 2, 17, SOCF_LE },
   5323     { RESERVED0f, 1, 16, SOCF_RES }
   5324 };
   5325 
   5326 #endif
   5327 #if defined(BCM_56142_A0)
   5328 soc_field_info_t soc_UDF_ETHERTYPE_MATCH_BCM56142_A0r_fields[] = {
   5329     { ENABLEf, 1, 19, 0 },
   5330     { ETHERTYPEf, 16, 0, SOCF_LE },
   5331     { L2_PACKET_FORMATf, 2, 17, SOCF_LE }
   5332 };
   5333 
   5334 #endif
   5335 #if defined(BCM_56150_A0)
   5336 soc_field_info_t soc_UDF_ETHERTYPE_MATCH_BCM56150_A0r_fields[] = {
   5337     { ENABLEf, 1, 19, 0 },
   5338     { ETHERTYPEf, 16, 0, SOCF_LE },
   5339     { L2_PACKET_FORMATf, 2, 17, SOCF_LE },
   5340     { RESERVED0f, 1, 16, SOCF_RES }
   5341 };
   5342 
   5343 #endif
   5344 #if defined(BCM_88732_A0)
   5345 soc_field_info_t soc_UDF_ETHERTYPE_MATCH_BCM88732_A0r_fields[] = {
   5346     { ENABLEf, 1, 18, 0 },
   5347     { ETHERTYPEf, 16, 0, SOCF_LE },
   5348     { L2_PACKET_FORMATf, 2, 16, SOCF_LE }
   5349 };
   5350 
   5351 #endif
   5352 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   5353     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   5354     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
   5355     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   5356     defined(BCM_56504_B0) || defined(BCM_56514_A0) || \
   5357     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   5358     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   5359     defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   5360     defined(BCM_56820_A0) || defined(BCM_88732_A0)
   5361 soc_field_info_t soc_UDF_IPPROTO_MATCHr_fields[] = {
   5362     { IPV4ENABLEf, 1, 9, 0 },
   5363     { IPV6ENABLEf, 1, 8, 0 },
   5364     { PROTOCOLf, 8, 0, SOCF_LE }
   5365 };
   5366 
   5367 #endif
   5368 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5369     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   5370     defined(BCM_56160_A0)
   5371 soc_field_info_t soc_UDF_IPPROTO_MATCH_BCM53400_A0r_fields[] = {
   5372     { IPV4ENABLEf, 1, 9, 0 },
   5373     { IPV6ENABLEf, 1, 8, 0 },
   5374     { PROTOCOLf, 8, 0, SOCF_LE }
   5375 };
   5376 
   5377 #endif
   5378 #if defined(BCM_56150_A0)
   5379 soc_field_info_t soc_UDF_IPPROTO_MATCH_BCM56150_A0r_fields[] = {
   5380     { IPV4ENABLEf, 1, 9, 0 },
   5381     { IPV6ENABLEf, 1, 8, 0 },
   5382     { PROTOCOLf, 8, 0, SOCF_LE }
   5383 };
   5384 
   5385 #endif
   5386 #if defined(BCM_88732_A0)
   5387 soc_field_info_t soc_UFLOW_AGED_COUNTr_fields[] = {
   5388     { COUNTf, 32, 0, SOCF_LE|SOCF_COR }
   5389 };
   5390 
   5391 #endif
   5392 #if defined(BCM_88732_A0)
   5393 soc_field_info_t soc_UFLOW_DEBUG_RANGEr_fields[] = {
   5394     { MAX_IDXf, 16, 16, SOCF_LE },
   5395     { MIN_IDXf, 16, 0, SOCF_LE }
   5396 };
   5397 
   5398 #endif
   5399 #if defined(BCM_88732_A0)
   5400 soc_field_info_t soc_UFLOW_HASH_CONTROL_RTAG7r_fields[] = {
   5401     { IPV4_DST_HASH_ENABLEf, 1, 21, 0 },
   5402     { IPV4_SRC_HASH_ENABLEf, 1, 22, 0 },
   5403     { IPV4_TCP_UDP_HASH_ENABLEf, 1, 20, 0 },
   5404     { IPV4_VLAN_HASH_ENABLEf, 1, 19, 0 },
   5405     { IPV6_DST_HASH_ENABLEf, 1, 17, 0 },
   5406     { IPV6_SRC_HASH_ENABLEf, 1, 18, 0 },
   5407     { IPV6_TCP_UDP_HASH_ENABLEf, 1, 16, 0 },
   5408     { IPV6_VLAN_HASH_ENABLEf, 1, 14, 0 },
   5409     { L2_DST_HASH_ENABLEf, 1, 1, 0 },
   5410     { L2_SRC_HASH_ENABLEf, 1, 2, 0 },
   5411     { L2_VLAN_HASH_ENABLEf, 1, 0, 0 },
   5412     { L3_HASH_ENABLEf, 1, 23, 0 },
   5413     { MPLS_HASH_ENABLEf, 1, 13, 0 },
   5414     { MPLS_LABEL_HASH_ENABLEf, 2, 9, SOCF_LE },
   5415     { MPLS_VLAN_HASH_ENABLEf, 1, 8, 0 },
   5416     { POLY_SELECTf, 1, 24, 0 }
   5417 };
   5418 
   5419 #endif
   5420 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   5421     defined(BCM_88732_A0)
   5422 soc_field_info_t soc_UFLOW_INACTIVE_COUNTr_fields[] = {
   5423     { COUNTf, 32, 0, SOCF_LE|SOCF_COR }
   5424 };
   5425 
   5426 #endif
   5427 #if defined(BCM_88732_A0)
   5428 soc_field_info_t soc_UFLOW_LFSR_CONTROLr_fields[] = {
   5429     { ENABLEf, 1, 32, 0 },
   5430     { LFSRf, 32, 0, SOCF_LE|SOCF_RWBW }
   5431 };
   5432 
   5433 #endif
   5434 #if defined(BCM_88732_A0)
   5435 soc_field_info_t soc_UFLOW_PORT_CONTROLr_fields[] = {
   5436     { DEST_PORTf, 5, 0, SOCF_LE },
   5437     { HASH_MODEf, 1, 6, 0 }
   5438 };
   5439 
   5440 #endif
   5441 #if defined(BCM_88732_A0)
   5442 soc_field_info_t soc_UFLOW_TABLE_CONTROLr_fields[] = {
   5443     { MODEf, 2, 18, SOCF_LE },
   5444     { PHASEf, 1, 17, 0 },
   5445     { PORT_ALLOW_MASKf, 16, 0, SOCF_LE }
   5446 };
   5447 
   5448 #endif
   5449 #if defined(BCM_88732_A0)
   5450 soc_field_info_t soc_UFLOW_TABLE_SIZEr_fields[] = {
   5451     { SIZE_Af, 4, 0, SOCF_LE },
   5452     { SIZE_Bf, 4, 4, SOCF_LE }
   5453 };
   5454 
   5455 #endif
   5456 #if defined(BCM_88732_A0)
   5457 soc_field_info_t soc_UFLOW_TIMER_CONTROLr_fields[] = {
   5458     { CYCLES_PER_TICKf, 16, 0, SOCF_LE },
   5459     { INACTIVITY_DURATION_Af, 9, 16, SOCF_LE },
   5460     { INACTIVITY_DURATION_Bf, 9, 32, SOCF_LE },
   5461     { TIMER_ENABLEf, 2, 41, SOCF_LE }
   5462 };
   5463 
   5464 #endif
   5465 #if defined(BCM_88732_A0)
   5466 soc_field_info_t soc_UFLOW_TIMER_STATUSr_fields[] = {
   5467     { CURRENT_TIME_Af, 10, 0, SOCF_LE|SOCF_RO },
   5468     { CURRENT_TIME_Bf, 10, 10, SOCF_LE|SOCF_RO }
   5469 };
   5470 
   5471 #endif
   5472 #if defined(BCM_53324_A0)
   5473 soc_field_info_t soc_UMAC_EEE_CTRLr_fields[] = {
   5474     { DIS_EEE_10Mf, 1, 6, 0 },
   5475     { ECO_EEE_LINKUP_CONFIG_ENf, 1, 2, 0 },
   5476     { EEE_ENf, 1, 3, 0 },
   5477     { EEE_TXCLK_DISf, 1, 5, 0 },
   5478     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   5479     { RX_FIFO_CHECKf, 1, 4, 0 }
   5480 };
   5481 
   5482 #endif
   5483 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5484     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   5485     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   5486     defined(BCM_56260_B0) || defined(BCM_56370_A0)
   5487 soc_field_info_t soc_UMAC_EEE_CTRL_BCM53400_A0r_fields[] = {
   5488     { DIS_EEE_10Mf, 1, 6, 0 },
   5489     { EEE_ENf, 1, 3, 0 },
   5490     { EEE_TXCLK_DISf, 1, 5, 0 },
   5491     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   5492     { RX_FIFO_CHECKf, 1, 4, 0 }
   5493 };
   5494 
   5495 #endif
   5496 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5497 soc_field_info_t soc_UMAC_EEE_CTRL_BCM53570_A0r_fields[] = {
   5498     { DIS_EEE_10Mf, 1, 6, 0 },
   5499     { EEE_ENf, 1, 3, 0 },
   5500     { EEE_TXCLK_DISf, 1, 5, 0 },
   5501     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   5502     { RSVD_1f, 3, 0, SOCF_LE|SOCF_RES },
   5503     { RX_FIFO_CHECKf, 1, 4, 0 }
   5504 };
   5505 
   5506 #endif
   5507 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5508 soc_field_info_t soc_UMAC_EEE_CTRL_BCM56440_A0r_fields[] = {
   5509     { DIS_EEE_10Mf, 1, 6, 0 },
   5510     { EEE_ENf, 1, 3, 0 },
   5511     { EEE_TXCLK_DISf, 1, 5, 0 },
   5512     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   5513     { RX_FIFO_CHECKf, 1, 4, 0 }
   5514 };
   5515 
   5516 #endif
   5517 #if defined(BCM_56142_A0) || defined(BCM_56840_A0) || \
   5518     defined(BCM_56840_B0) || defined(BCM_88732_A0)
   5519 soc_field_info_t soc_UMAC_EEE_CTRL_BCM56840_A0r_fields[] = {
   5520     { DIS_EEE_10Mf, 1, 6, 0 },
   5521     { EEE_DISABLE_RX_PAUSE_ACTIVEf, 1, 0, SOCF_SC },
   5522     { EEE_DISABLE_TX_PAUSE_XOFFf, 1, 2, SOCF_SC },
   5523     { EEE_DISABLE_TX_PFC_XOFFf, 1, 1, SOCF_SC },
   5524     { EEE_ENf, 1, 3, 0 },
   5525     { EEE_TXCLK_DISf, 1, 5, 0 },
   5526     { RX_FIFO_CHECKf, 1, 4, 0 }
   5527 };
   5528 
   5529 #endif
   5530 #if defined(BCM_88375_A0)
   5531 soc_field_info_t soc_UMAC_EEE_CTRL_BCM88375_A0r_fields[] = {
   5532     { DIS_EEE_10Mf, 1, 6, 0 },
   5533     { EEE_ENf, 1, 3, 0 },
   5534     { EEE_TXCLK_DISf, 1, 5, 0 },
   5535     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   5536     { RX_FIFO_CHECKf, 1, 4, 0 }
   5537 };
   5538 
   5539 #endif
   5540 #if defined(BCM_88375_B0)
   5541 soc_field_info_t soc_UMAC_EEE_CTRL_BCM88375_B0r_fields[] = {
   5542     { DIS_EEE_10Mf, 1, 6, 0 },
   5543     { EEE_ENf, 1, 3, 0 },
   5544     { EEE_TXCLK_DISf, 1, 5, 0 },
   5545     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   5546     { RX_FIFO_CHECKf, 1, 4, 0 }
   5547 };
   5548 
   5549 #endif
   5550 #if defined(BCM_88470_A0)
   5551 soc_field_info_t soc_UMAC_EEE_CTRL_BCM88470_A0r_fields[] = {
   5552     { DIS_EEE_10Mf, 1, 6, 0 },
   5553     { EEE_ENf, 1, 3, 0 },
   5554     { EEE_TXCLK_DISf, 1, 5, 0 },
   5555     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   5556     { RX_FIFO_CHECKf, 1, 4, 0 }
   5557 };
   5558 
   5559 #endif
   5560 #if defined(BCM_88470_B0)
   5561 soc_field_info_t soc_UMAC_EEE_CTRL_BCM88470_B0r_fields[] = {
   5562     { DIS_EEE_10Mf, 1, 6, 0 },
   5563     { EEE_ENf, 1, 3, 0 },
   5564     { EEE_TXCLK_DISf, 1, 5, 0 },
   5565     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   5566     { RX_FIFO_CHECKf, 1, 4, 0 }
   5567 };
   5568 
   5569 #endif
   5570 #if defined(BCM_88675_A0)
   5571 soc_field_info_t soc_UMAC_EEE_CTRL_BCM88675_A0r_fields[] = {
   5572     { DIS_EEE_10Mf, 1, 6, 0 },
   5573     { EEE_ENf, 1, 3, 0 },
   5574     { EEE_TXCLK_DISf, 1, 5, 0 },
   5575     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   5576     { RX_FIFO_CHECKf, 1, 4, 0 }
   5577 };
   5578 
   5579 #endif
   5580 #if defined(BCM_88675_B0)
   5581 soc_field_info_t soc_UMAC_EEE_CTRL_BCM88675_B0r_fields[] = {
   5582     { DIS_EEE_10Mf, 1, 6, 0 },
   5583     { EEE_ENf, 1, 3, 0 },
   5584     { EEE_TXCLK_DISf, 1, 5, 0 },
   5585     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   5586     { RX_FIFO_CHECKf, 1, 4, 0 }
   5587 };
   5588 
   5589 #endif
   5590 #if defined(BCM_88680_A0)
   5591 soc_field_info_t soc_UMAC_EEE_CTRL_BCM88680_A0r_fields[] = {
   5592     { DIS_EEE_10Mf, 1, 6, 0 },
   5593     { EEE_ENf, 1, 3, 0 },
   5594     { EEE_TXCLK_DISf, 1, 5, 0 },
   5595     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   5596     { RX_FIFO_CHECKf, 1, 4, 0 }
   5597 };
   5598 
   5599 #endif
   5600 #if defined(BCM_53324_A0) || defined(BCM_56142_A0) || \
   5601     defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   5602     defined(BCM_56840_A0) || defined(BCM_56840_B0) || \
   5603     defined(BCM_88732_A0)
   5604 soc_field_info_t soc_UMAC_EEE_REF_COUNTr_fields[] = {
   5605     { EEE_REF_COUNTf, 16, 0, SOCF_LE }
   5606 };
   5607 
   5608 #endif
   5609 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5610     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   5611     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   5612     defined(BCM_56260_B0) || defined(BCM_56370_A0)
   5613 soc_field_info_t soc_UMAC_EEE_REF_COUNT_BCM53400_A0r_fields[] = {
   5614     { EEE_REF_COUNTf, 16, 0, SOCF_LE }
   5615 };
   5616 
   5617 #endif
   5618 #if defined(BCM_88375_A0)
   5619 soc_field_info_t soc_UMAC_EEE_REF_COUNT_BCM88375_A0r_fields[] = {
   5620     { EEE_REF_COUNTf, 16, 0, SOCF_LE }
   5621 };
   5622 
   5623 #endif
   5624 #if defined(BCM_88375_B0)
   5625 soc_field_info_t soc_UMAC_EEE_REF_COUNT_BCM88375_B0r_fields[] = {
   5626     { EEE_REF_COUNTf, 16, 0, SOCF_LE }
   5627 };
   5628 
   5629 #endif
   5630 #if defined(BCM_88470_A0)
   5631 soc_field_info_t soc_UMAC_EEE_REF_COUNT_BCM88470_A0r_fields[] = {
   5632     { EEE_REF_COUNTf, 16, 0, SOCF_LE }
   5633 };
   5634 
   5635 #endif
   5636 #if defined(BCM_88470_B0)
   5637 soc_field_info_t soc_UMAC_EEE_REF_COUNT_BCM88470_B0r_fields[] = {
   5638     { EEE_REF_COUNTf, 16, 0, SOCF_LE }
   5639 };
   5640 
   5641 #endif
   5642 #if defined(BCM_88675_A0)
   5643 soc_field_info_t soc_UMAC_EEE_REF_COUNT_BCM88675_A0r_fields[] = {
   5644     { EEE_REF_COUNTf, 16, 0, SOCF_LE }
   5645 };
   5646 
   5647 #endif
   5648 #if defined(BCM_88675_B0)
   5649 soc_field_info_t soc_UMAC_EEE_REF_COUNT_BCM88675_B0r_fields[] = {
   5650     { EEE_REF_COUNTf, 16, 0, SOCF_LE }
   5651 };
   5652 
   5653 #endif
   5654 #if defined(BCM_88680_A0)
   5655 soc_field_info_t soc_UMAC_EEE_REF_COUNT_BCM88680_A0r_fields[] = {
   5656     { EEE_REF_COUNTf, 16, 0, SOCF_LE }
   5657 };
   5658 
   5659 #endif
   5660 #if defined(BCM_88675_A0)
   5661 soc_field_info_t soc_UMAC_REV_IDr_fields[] = {
   5662     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   5663     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   5664     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   5665 };
   5666 
   5667 #endif
   5668 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5669     defined(BCM_56160_A0) || defined(BCM_56370_A0)
   5670 soc_field_info_t soc_UMAC_REV_ID_BCM53400_A0r_fields[] = {
   5671     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   5672     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   5673     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   5674 };
   5675 
   5676 #endif
   5677 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5678 soc_field_info_t soc_UMAC_REV_ID_BCM53570_A0r_fields[] = {
   5679     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   5680     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   5681     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   5682 };
   5683 
   5684 #endif
   5685 #if defined(BCM_56150_A0)
   5686 soc_field_info_t soc_UMAC_REV_ID_BCM56150_A0r_fields[] = {
   5687     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   5688     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   5689     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   5690 };
   5691 
   5692 #endif
   5693 #if defined(BCM_88375_A0)
   5694 soc_field_info_t soc_UMAC_REV_ID_BCM88375_A0r_fields[] = {
   5695     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   5696     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   5697     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   5698 };
   5699 
   5700 #endif
   5701 #if defined(BCM_88375_B0)
   5702 soc_field_info_t soc_UMAC_REV_ID_BCM88375_B0r_fields[] = {
   5703     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   5704     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   5705     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   5706 };
   5707 
   5708 #endif
   5709 #if defined(BCM_88470_A0)
   5710 soc_field_info_t soc_UMAC_REV_ID_BCM88470_A0r_fields[] = {
   5711     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   5712     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   5713     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   5714 };
   5715 
   5716 #endif
   5717 #if defined(BCM_88470_B0)
   5718 soc_field_info_t soc_UMAC_REV_ID_BCM88470_B0r_fields[] = {
   5719     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   5720     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   5721     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   5722 };
   5723 
   5724 #endif
   5725 #if defined(BCM_88675_B0)
   5726 soc_field_info_t soc_UMAC_REV_ID_BCM88675_B0r_fields[] = {
   5727     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   5728     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   5729     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   5730 };
   5731 
   5732 #endif
   5733 #if defined(BCM_88680_A0)
   5734 soc_field_info_t soc_UMAC_REV_ID_BCM88680_A0r_fields[] = {
   5735     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   5736     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   5737     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   5738 };
   5739 
   5740 #endif
   5741 #if defined(BCM_88675_A0)
   5742 soc_field_info_t soc_UMAC_RX_PKT_DROP_STATUSr_fields[] = {
   5743     { RX_IPG_INVALf, 1, 0, 0 }
   5744 };
   5745 
   5746 #endif
   5747 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5748     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   5749     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   5750     defined(BCM_56260_B0) || defined(BCM_56370_A0)
   5751 soc_field_info_t soc_UMAC_RX_PKT_DROP_STATUS_BCM53400_A0r_fields[] = {
   5752     { RX_IPG_INVALf, 1, 0, 0 }
   5753 };
   5754 
   5755 #endif
   5756 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5757 soc_field_info_t soc_UMAC_RX_PKT_DROP_STATUS_BCM56440_A0r_fields[] = {
   5758     { RX_IPG_INVALf, 1, 0, 0 }
   5759 };
   5760 
   5761 #endif
   5762 #if defined(BCM_88375_A0)
   5763 soc_field_info_t soc_UMAC_RX_PKT_DROP_STATUS_BCM88375_A0r_fields[] = {
   5764     { RX_IPG_INVALf, 1, 0, 0 }
   5765 };
   5766 
   5767 #endif
   5768 #if defined(BCM_88375_B0)
   5769 soc_field_info_t soc_UMAC_RX_PKT_DROP_STATUS_BCM88375_B0r_fields[] = {
   5770     { RX_IPG_INVALf, 1, 0, 0 }
   5771 };
   5772 
   5773 #endif
   5774 #if defined(BCM_88470_A0)
   5775 soc_field_info_t soc_UMAC_RX_PKT_DROP_STATUS_BCM88470_A0r_fields[] = {
   5776     { RX_IPG_INVALf, 1, 0, 0 }
   5777 };
   5778 
   5779 #endif
   5780 #if defined(BCM_88470_B0)
   5781 soc_field_info_t soc_UMAC_RX_PKT_DROP_STATUS_BCM88470_B0r_fields[] = {
   5782     { RX_IPG_INVALf, 1, 0, 0 }
   5783 };
   5784 
   5785 #endif
   5786 #if defined(BCM_88675_B0)
   5787 soc_field_info_t soc_UMAC_RX_PKT_DROP_STATUS_BCM88675_B0r_fields[] = {
   5788     { RX_IPG_INVALf, 1, 0, 0 }
   5789 };
   5790 
   5791 #endif
   5792 #if defined(BCM_88680_A0)
   5793 soc_field_info_t soc_UMAC_RX_PKT_DROP_STATUS_BCM88680_A0r_fields[] = {
   5794     { RX_IPG_INVALf, 1, 0, 0 }
   5795 };
   5796 
   5797 #endif
   5798 #if defined(BCM_53324_A0) || defined(BCM_56440_A0) || \
   5799     defined(BCM_56440_B0)
   5800 soc_field_info_t soc_UMAC_SYMMETRIC_IDLE_THRESHOLDr_fields[] = {
   5801     { THRESHOLD_VALUEf, 16, 0, SOCF_LE }
   5802 };
   5803 
   5804 #endif
   5805 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5806     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   5807     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   5808     defined(BCM_56260_B0) || defined(BCM_56370_A0)
   5809 soc_field_info_t soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53400_A0r_fields[] = {
   5810     { THRESHOLD_VALUEf, 16, 0, SOCF_LE }
   5811 };
   5812 
   5813 #endif
   5814 #if defined(BCM_88375_A0)
   5815 soc_field_info_t soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88375_A0r_fields[] = {
   5816     { THRESHOLD_VALUEf, 16, 0, SOCF_LE }
   5817 };
   5818 
   5819 #endif
   5820 #if defined(BCM_88375_B0)
   5821 soc_field_info_t soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88375_B0r_fields[] = {
   5822     { THRESHOLD_VALUEf, 16, 0, SOCF_LE }
   5823 };
   5824 
   5825 #endif
   5826 #if defined(BCM_88470_A0)
   5827 soc_field_info_t soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88470_A0r_fields[] = {
   5828     { THRESHOLD_VALUEf, 16, 0, SOCF_LE }
   5829 };
   5830 
   5831 #endif
   5832 #if defined(BCM_88470_B0)
   5833 soc_field_info_t soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88470_B0r_fields[] = {
   5834     { THRESHOLD_VALUEf, 16, 0, SOCF_LE }
   5835 };
   5836 
   5837 #endif
   5838 #if defined(BCM_88675_A0)
   5839 soc_field_info_t soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88675_A0r_fields[] = {
   5840     { THRESHOLD_VALUEf, 16, 0, SOCF_LE }
   5841 };
   5842 
   5843 #endif
   5844 #if defined(BCM_88675_B0)
   5845 soc_field_info_t soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88675_B0r_fields[] = {
   5846     { THRESHOLD_VALUEf, 16, 0, SOCF_LE }
   5847 };
   5848 
   5849 #endif
   5850 #if defined(BCM_88680_A0)
   5851 soc_field_info_t soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88680_A0r_fields[] = {
   5852     { THRESHOLD_VALUEf, 16, 0, SOCF_LE }
   5853 };
   5854 
   5855 #endif
   5856 #if defined(BCM_88675_A0)
   5857 soc_field_info_t soc_UMAC_TIMESTAMP_ADJUSTr_fields[] = {
   5858     { ADJUSTf, 9, 0, SOCF_LE },
   5859     { AUTO_ADJUSTf, 1, 10, 0 },
   5860     { EN_1588f, 1, 9, 0 }
   5861 };
   5862 
   5863 #endif
   5864 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5865     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   5866     defined(BCM_56160_A0) || defined(BCM_56370_A0)
   5867 soc_field_info_t soc_UMAC_TIMESTAMP_ADJUST_BCM53400_A0r_fields[] = {
   5868     { ADJUSTf, 9, 0, SOCF_LE },
   5869     { AUTO_ADJUSTf, 1, 10, 0 },
   5870     { EN_1588f, 1, 9, 0 }
   5871 };
   5872 
   5873 #endif
   5874 #if defined(BCM_56150_A0)
   5875 soc_field_info_t soc_UMAC_TIMESTAMP_ADJUST_BCM56150_A0r_fields[] = {
   5876     { ADJUSTf, 9, 0, SOCF_LE },
   5877     { AUTO_ADJUSTf, 1, 10, 0 },
   5878     { EN_1588f, 1, 9, 0 }
   5879 };
   5880 
   5881 #endif
   5882 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5883 soc_field_info_t soc_UMAC_TIMESTAMP_ADJUST_BCM56440_A0r_fields[] = {
   5884     { ADJUSTf, 9, 0, SOCF_LE },
   5885     { AUTO_ADJUSTf, 1, 10, 0 },
   5886     { EN_1588f, 1, 9, 0 }
   5887 };
   5888 
   5889 #endif
   5890 #if defined(BCM_88375_A0)
   5891 soc_field_info_t soc_UMAC_TIMESTAMP_ADJUST_BCM88375_A0r_fields[] = {
   5892     { ADJUSTf, 9, 0, SOCF_LE },
   5893     { AUTO_ADJUSTf, 1, 10, 0 },
   5894     { EN_1588f, 1, 9, 0 }
   5895 };
   5896 
   5897 #endif
   5898 #if defined(BCM_88375_B0)
   5899 soc_field_info_t soc_UMAC_TIMESTAMP_ADJUST_BCM88375_B0r_fields[] = {
   5900     { ADJUSTf, 9, 0, SOCF_LE },
   5901     { AUTO_ADJUSTf, 1, 10, 0 },
   5902     { EN_1588f, 1, 9, 0 }
   5903 };
   5904 
   5905 #endif
   5906 #if defined(BCM_88470_A0)
   5907 soc_field_info_t soc_UMAC_TIMESTAMP_ADJUST_BCM88470_A0r_fields[] = {
   5908     { ADJUSTf, 9, 0, SOCF_LE },
   5909     { AUTO_ADJUSTf, 1, 10, 0 },
   5910     { EN_1588f, 1, 9, 0 }
   5911 };
   5912 
   5913 #endif
   5914 #if defined(BCM_88470_B0)
   5915 soc_field_info_t soc_UMAC_TIMESTAMP_ADJUST_BCM88470_B0r_fields[] = {
   5916     { ADJUSTf, 9, 0, SOCF_LE },
   5917     { AUTO_ADJUSTf, 1, 10, 0 },
   5918     { EN_1588f, 1, 9, 0 }
   5919 };
   5920 
   5921 #endif
   5922 #if defined(BCM_88675_B0)
   5923 soc_field_info_t soc_UMAC_TIMESTAMP_ADJUST_BCM88675_B0r_fields[] = {
   5924     { ADJUSTf, 9, 0, SOCF_LE },
   5925     { AUTO_ADJUSTf, 1, 10, 0 },
   5926     { EN_1588f, 1, 9, 0 }
   5927 };
   5928 
   5929 #endif
   5930 #if defined(BCM_88680_A0)
   5931 soc_field_info_t soc_UMAC_TIMESTAMP_ADJUST_BCM88680_A0r_fields[] = {
   5932     { ADJUSTf, 9, 0, SOCF_LE },
   5933     { AUTO_ADJUSTf, 1, 10, 0 },
   5934     { EN_1588f, 1, 9, 0 }
   5935 };
   5936 
   5937 #endif
   5938 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   5939 soc_field_info_t soc_UMAN_EP_FLSH_WAIT_CNTRr_fields[] = {
   5940     { UMAN_EP_FLSH_WAIT_CNTRf, 12, 0, SOCF_LE }
   5941 };
   5942 
   5943 #endif
   5944 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   5945 soc_field_info_t soc_UMAN_IP_FLSH_WAIT_CNTRr_fields[] = {
   5946     { UMAN_IP_FLSH_WAIT_CNTRf, 12, 0, SOCF_LE }
   5947 };
   5948 
   5949 #endif
   5950 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   5951 soc_field_info_t soc_UMAN_LINKUP_DLY_CNTRr_fields[] = {
   5952     { UMAN_LINKUP_DLY_CNTRf, 18, 0, SOCF_LE|SOCF_RES }
   5953 };
   5954 
   5955 #endif
   5956 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   5957     defined(BCM_56450_A0)
   5958 soc_field_info_t soc_UNIMAC0_COMMAND_CONFIGr_fields[] = {
   5959     { CNTL_FRM_ENAf, 1, 23, 0 },
   5960     { CRC_FWDf, 1, 6, 0 },
   5961     { ENA_EXT_CONFIGf, 1, 22, SOCF_RES },
   5962     { EN_INTERNAL_TX_CRSf, 1, 21, 0 },
   5963     { ETH_SPEEDf, 2, 2, SOCF_LE },
   5964     { FCS_CORRUPT_URUN_ENf, 1, 14, 0 },
   5965     { HD_ENAf, 1, 10, 0 },
   5966     { IGNORE_TX_PAUSEf, 1, 28, 0 },
   5967     { LINE_LOOPBACKf, 1, 25, 0 },
   5968     { LOOP_ENAf, 1, 15, 0 },
   5969     { MAC_LOOP_CONf, 1, 16, 0 },
   5970     { NO_LGTH_CHECKf, 1, 24, 0 },
   5971     { OOB_EFC_ENf, 1, 29, 0 },
   5972     { OVERFLOW_ENf, 1, 12, 0 },
   5973     { PAD_ENf, 1, 5, 0 },
   5974     { PAUSE_FWDf, 1, 7, 0 },
   5975     { PAUSE_IGNOREf, 1, 8, 0 },
   5976     { PRBL_ENAf, 1, 27, 0 },
   5977     { PROMIS_ENf, 1, 4, 0 },
   5978     { RUNT_FILTER_DISf, 1, 30, 0 },
   5979     { RX_ENAf, 1, 1, 0 },
   5980     { RX_ERR_DISCf, 1, 26, 0 },
   5981     { RX_LOW_LATENCY_ENf, 1, 11, 0 },
   5982     { SW_OVERRIDE_RXf, 1, 18, 0 },
   5983     { SW_OVERRIDE_TXf, 1, 17, 0 },
   5984     { SW_RESETf, 1, 13, SOCF_RES },
   5985     { TX_ADDR_INSf, 1, 9, 0 },
   5986     { TX_ENAf, 1, 0, 0 }
   5987 };
   5988 
   5989 #endif
   5990 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5991     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   5992     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   5993     defined(BCM_56260_B0)
   5994 soc_field_info_t soc_UNIMAC0_COMMAND_CONFIG_BCM53400_A0r_fields[] = {
   5995     { CNTL_FRM_ENAf, 1, 23, 0 },
   5996     { CRC_FWDf, 1, 6, 0 },
   5997     { ENA_EXT_CONFIGf, 1, 22, SOCF_RES },
   5998     { EN_INTERNAL_TX_CRSf, 1, 21, 0 },
   5999     { ETH_SPEEDf, 2, 2, SOCF_LE },
   6000     { FCS_CORRUPT_URUN_ENf, 1, 14, 0 },
   6001     { FD_TX_URUN_FIX_ENf, 1, 27, 0 },
   6002     { HD_ENAf, 1, 10, 0 },
   6003     { IGNORE_TX_PAUSEf, 1, 28, 0 },
   6004     { LINE_LOOPBACKf, 1, 25, 0 },
   6005     { LOOP_ENAf, 1, 15, 0 },
   6006     { MAC_LOOP_CONf, 1, 16, 0 },
   6007     { NO_LGTH_CHECKf, 1, 24, 0 },
   6008     { OOB_EFC_ENf, 1, 29, 0 },
   6009     { OVERFLOW_ENf, 1, 12, 0 },
   6010     { PAD_ENf, 1, 5, 0 },
   6011     { PAUSE_FWDf, 1, 7, 0 },
   6012     { PAUSE_IGNOREf, 1, 8, 0 },
   6013     { PROMIS_ENf, 1, 4, 0 },
   6014     { RUNT_FILTER_DISf, 1, 30, 0 },
   6015     { RX_ENAf, 1, 1, 0 },
   6016     { RX_ERR_DISCf, 1, 26, 0 },
   6017     { RX_LOW_LATENCY_ENf, 1, 11, 0 },
   6018     { SW_OVERRIDE_RXf, 1, 18, 0 },
   6019     { SW_OVERRIDE_TXf, 1, 17, 0 },
   6020     { SW_RESETf, 1, 13, SOCF_RES },
   6021     { TX_ADDR_INSf, 1, 9, 0 },
   6022     { TX_ENAf, 1, 0, 0 }
   6023 };
   6024 
   6025 #endif
   6026 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6027 soc_field_info_t soc_UNIMAC0_COMMAND_CONFIG_BCM56450_B0r_fields[] = {
   6028     { CNTL_FRM_ENAf, 1, 23, 0 },
   6029     { CRC_FWDf, 1, 6, 0 },
   6030     { ENA_EXT_CONFIGf, 1, 22, SOCF_RES },
   6031     { EN_INTERNAL_TX_CRSf, 1, 21, 0 },
   6032     { ETH_SPEEDf, 2, 2, SOCF_LE },
   6033     { FCS_CORRUPT_URUN_ENf, 1, 14, 0 },
   6034     { HD_ENAf, 1, 10, 0 },
   6035     { IGNORE_TX_PAUSEf, 1, 28, 0 },
   6036     { LINE_LOOPBACKf, 1, 25, 0 },
   6037     { LOOP_ENAf, 1, 15, 0 },
   6038     { MAC_LOOP_CONf, 1, 16, 0 },
   6039     { NO_LGTH_CHECKf, 1, 24, 0 },
   6040     { OOB_EFC_ENf, 1, 29, 0 },
   6041     { OVERFLOW_ENf, 1, 12, 0 },
   6042     { PAD_ENf, 1, 5, 0 },
   6043     { PAUSE_FWDf, 1, 7, 0 },
   6044     { PAUSE_IGNOREf, 1, 8, 0 },
   6045     { PRBL_ENAf, 1, 27, SOCF_RES },
   6046     { PROMIS_ENf, 1, 4, 0 },
   6047     { RUNT_FILTER_DISf, 1, 30, 0 },
   6048     { RX_ENAf, 1, 1, 0 },
   6049     { RX_ERR_DISCf, 1, 26, 0 },
   6050     { RX_LOW_LATENCY_ENf, 1, 11, 0 },
   6051     { SW_OVERRIDE_RXf, 1, 18, 0 },
   6052     { SW_OVERRIDE_TXf, 1, 17, 0 },
   6053     { SW_RESETf, 1, 13, SOCF_RES },
   6054     { TX_ADDR_INSf, 1, 9, 0 },
   6055     { TX_ENAf, 1, 0, 0 }
   6056 };
   6057 
   6058 #endif
   6059 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6060     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6061     defined(BCM_56450_B1)
   6062 soc_field_info_t soc_UNIMAC0_FLUSH_CONTROLr_fields[] = {
   6063     { FLUSHf, 1, 0, SOCF_RES }
   6064 };
   6065 
   6066 #endif
   6067 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6068     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6069     defined(BCM_56450_B1)
   6070 soc_field_info_t soc_UNIMAC0_FRM_LENGTHr_fields[] = {
   6071     { MAXFRf, 14, 0, SOCF_LE }
   6072 };
   6073 
   6074 #endif
   6075 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6076     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6077     defined(BCM_56450_B1)
   6078 soc_field_info_t soc_UNIMAC0_GMII_EEE_DELAY_ENTRY_TIMERr_fields[] = {
   6079     { GMII_EEE_LPI_TIMERf, 32, 0, SOCF_LE }
   6080 };
   6081 
   6082 #endif
   6083 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6084     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6085     defined(BCM_56450_B1)
   6086 soc_field_info_t soc_UNIMAC0_GMII_EEE_WAKE_TIMERr_fields[] = {
   6087     { GMII_EEE_WAKE_TIMERf, 16, 0, SOCF_LE }
   6088 };
   6089 
   6090 #endif
   6091 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6092     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6093     defined(BCM_56450_B1)
   6094 soc_field_info_t soc_UNIMAC0_IPG_HD_BKP_CNTLr_fields[] = {
   6095     { HD_FC_BKOFF_OKf, 1, 1, 0 },
   6096     { HD_FC_ENAf, 1, 0, 0 },
   6097     { IPG_CONFIG_RXf, 5, 2, SOCF_LE|SOCF_RES }
   6098 };
   6099 
   6100 #endif
   6101 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6102     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6103     defined(BCM_56450_B1)
   6104 soc_field_info_t soc_UNIMAC0_MAC_0r_fields[] = {
   6105     { MAC_ADDR0f, 32, 0, SOCF_LE }
   6106 };
   6107 
   6108 #endif
   6109 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6110     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6111     defined(BCM_56450_B1)
   6112 soc_field_info_t soc_UNIMAC0_MAC_1r_fields[] = {
   6113     { MAC_ADDR1f, 16, 0, SOCF_LE }
   6114 };
   6115 
   6116 #endif
   6117 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6118     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6119     defined(BCM_56450_B1)
   6120 soc_field_info_t soc_UNIMAC0_MAC_MODEr_fields[] = {
   6121     { LINK_STATUSf, 1, 5, SOCF_RO },
   6122     { MAC_DUPLEXf, 1, 2, SOCF_RO },
   6123     { MAC_RX_PAUSEf, 1, 3, SOCF_RO },
   6124     { MAC_SPEEDf, 2, 0, SOCF_LE|SOCF_RO },
   6125     { MAC_TX_PAUSEf, 1, 4, SOCF_RO }
   6126 };
   6127 
   6128 #endif
   6129 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6130     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6131 soc_field_info_t soc_UNIMAC0_MAC_PFC_CTRLr_fields[] = {
   6132     { FORCE_PFC_XONf, 1, 2, SOCF_RES },
   6133     { PFC_RX_ENBLf, 1, 1, 0 },
   6134     { PFC_STATS_ENf, 1, 5, 0 },
   6135     { PFC_TX_ENBLf, 1, 0, 0 },
   6136     { RX_PASS_PFC_FRMf, 1, 4, 0 }
   6137 };
   6138 
   6139 #endif
   6140 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
   6141     defined(BCM_53570_B0) || defined(BCM_56160_A0) || \
   6142     defined(BCM_56370_A0)
   6143 soc_field_info_t soc_UNIMAC0_MAC_PFC_CTRL_BCM56160_A0r_fields[] = {
   6144     { FORCE_PFC_XONf, 1, 2, SOCF_RES },
   6145     { PFC_RX_ENBLf, 1, 1, 0 },
   6146     { PFC_STATS_ENf, 1, 5, 0 },
   6147     { PFC_TX_ENBLf, 1, 0, 0 },
   6148     { RX_PASS_PFC_FRMf, 1, 4, 0 }
   6149 };
   6150 
   6151 #endif
   6152 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6153     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6154 soc_field_info_t soc_UNIMAC0_MAC_PFC_DA_0r_fields[] = {
   6155     { PFC_MACDA_0f, 32, 0, SOCF_LE }
   6156 };
   6157 
   6158 #endif
   6159 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6160     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6161 soc_field_info_t soc_UNIMAC0_MAC_PFC_DA_1r_fields[] = {
   6162     { PFC_MACDA_1f, 16, 0, SOCF_LE }
   6163 };
   6164 
   6165 #endif
   6166 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6167     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6168 soc_field_info_t soc_UNIMAC0_MAC_PFC_REFRESH_CTRLr_fields[] = {
   6169     { PFC_REFRESH_ENf, 1, 0, SOCF_RES },
   6170     { PFC_REFRESH_TIMERf, 16, 16, SOCF_LE|SOCF_RES }
   6171 };
   6172 
   6173 #endif
   6174 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6175     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6176     defined(BCM_56450_B1)
   6177 soc_field_info_t soc_UNIMAC0_MII_EEE_DELAY_ENTRY_TIMERr_fields[] = {
   6178     { MII_EEE_LPI_TIMERf, 32, 0, SOCF_LE }
   6179 };
   6180 
   6181 #endif
   6182 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6183     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6184     defined(BCM_56450_B1)
   6185 soc_field_info_t soc_UNIMAC0_MII_EEE_WAKE_TIMERr_fields[] = {
   6186     { MII_EEE_WAKE_TIMERf, 16, 0, SOCF_LE }
   6187 };
   6188 
   6189 #endif
   6190 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6191     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6192     defined(BCM_56450_B1)
   6193 soc_field_info_t soc_UNIMAC0_PAUSE_CONTROLr_fields[] = {
   6194     { ENABLEf, 1, 17, 0 },
   6195     { VALUEf, 17, 0, SOCF_LE }
   6196 };
   6197 
   6198 #endif
   6199 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6200     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6201     defined(BCM_56450_B1)
   6202 soc_field_info_t soc_UNIMAC0_PAUSE_QUANTr_fields[] = {
   6203     { STAD2f, 16, 0, SOCF_LE }
   6204 };
   6205 
   6206 #endif
   6207 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6208     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6209     defined(BCM_56450_B1)
   6210 soc_field_info_t soc_UNIMAC0_PFC_XOFF_TIMERr_fields[] = {
   6211     { PFC_XOFF_TIMERf, 16, 0, SOCF_LE }
   6212 };
   6213 
   6214 #endif
   6215 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6216     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6217     defined(BCM_56450_B1)
   6218 soc_field_info_t soc_UNIMAC0_RXFIFO_STATr_fields[] = {
   6219     { RXFIFO_OVERRUNf, 1, 1, SOCF_RO|SOCF_RES },
   6220     { RXFIFO_UNDERRUNf, 1, 0, SOCF_RO|SOCF_RES }
   6221 };
   6222 
   6223 #endif
   6224 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6225     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6226     defined(BCM_56450_B1)
   6227 soc_field_info_t soc_UNIMAC0_RX_PAUSE_QUANTA_SCALEr_fields[] = {
   6228     { SCALE_CONTROLf, 1, 16, 0 },
   6229     { SCALE_FIXf, 1, 17, 0 },
   6230     { SCALE_VALUEf, 16, 0, SOCF_LE }
   6231 };
   6232 
   6233 #endif
   6234 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6235     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6236     defined(BCM_56450_B1)
   6237 soc_field_info_t soc_UNIMAC0_TAG_0r_fields[] = {
   6238     { CONFIG_OUTER_TPID_ENABLEf, 1, 16, 0 },
   6239     { FRM_TAG_0f, 16, 0, SOCF_LE }
   6240 };
   6241 
   6242 #endif
   6243 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6244     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6245     defined(BCM_56450_B1)
   6246 soc_field_info_t soc_UNIMAC0_TAG_1r_fields[] = {
   6247     { CONFIG_INNER_TPID_ENABLEf, 1, 16, 0 },
   6248     { FRM_TAG_1f, 16, 0, SOCF_LE }
   6249 };
   6250 
   6251 #endif
   6252 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6253     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6254     defined(BCM_56450_B1)
   6255 soc_field_info_t soc_UNIMAC0_TS_STATUS_CNTRLr_fields[] = {
   6256     { TX_TS_FIFO_EMPTYf, 1, 1, SOCF_RO },
   6257     { TX_TS_FIFO_FULLf, 1, 0, SOCF_RO },
   6258     { WORD_AVAILf, 3, 2, SOCF_LE|SOCF_RO }
   6259 };
   6260 
   6261 #endif
   6262 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6263     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6264     defined(BCM_56450_B1)
   6265 soc_field_info_t soc_UNIMAC0_TXFIFO_STATr_fields[] = {
   6266     { TXFIFO_OVERRUNf, 1, 1, SOCF_RO|SOCF_RES },
   6267     { TXFIFO_UNDERRUNf, 1, 0, SOCF_RO|SOCF_RES }
   6268 };
   6269 
   6270 #endif
   6271 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6272     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6273     defined(BCM_56450_B1)
   6274 soc_field_info_t soc_UNIMAC0_TX_IPG_LENGTHr_fields[] = {
   6275     { TX_IPG_LENGTHf, 7, 0, SOCF_LE }
   6276 };
   6277 
   6278 #endif
   6279 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6280     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6281     defined(BCM_56450_B1)
   6282 soc_field_info_t soc_UNIMAC0_TX_PREAMBLEr_fields[] = {
   6283     { TX_PREAMBLEf, 3, 0, SOCF_LE }
   6284 };
   6285 
   6286 #endif
   6287 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6288     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6289     defined(BCM_56450_B1)
   6290 soc_field_info_t soc_UNIMAC0_TX_TS_DATAr_fields[] = {
   6291     { TX_TS_DATAf, 32, 0, SOCF_LE|SOCF_RO }
   6292 };
   6293 
   6294 #endif
   6295 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6296     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6297     defined(BCM_56450_B1)
   6298 soc_field_info_t soc_UNIMAC0_TX_TS_SEQ_IDr_fields[] = {
   6299     { TSTS_SEQ_IDf, 16, 0, SOCF_LE|SOCF_RO },
   6300     { TSTS_VALIDf, 1, 16, SOCF_RO }
   6301 };
   6302 
   6303 #endif
   6304 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6305     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6306     defined(BCM_56450_B1)
   6307 soc_field_info_t soc_UNIMAC0_UMAC_EEE_CTRLr_fields[] = {
   6308     { DIS_EEE_10Mf, 1, 6, 0 },
   6309     { EEE_ENf, 1, 3, 0 },
   6310     { EEE_TXCLK_DISf, 1, 5, 0 },
   6311     { LP_IDLE_PREDICTION_MODEf, 1, 7, 0 },
   6312     { RX_FIFO_CHECKf, 1, 4, 0 }
   6313 };
   6314 
   6315 #endif
   6316 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6317     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6318     defined(BCM_56450_B1)
   6319 soc_field_info_t soc_UNIMAC0_UMAC_EEE_REF_COUNTr_fields[] = {
   6320     { EEE_REF_COUNTf, 16, 0, SOCF_LE }
   6321 };
   6322 
   6323 #endif
   6324 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6325     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6326     defined(BCM_56450_B1)
   6327 soc_field_info_t soc_UNIMAC0_UMAC_REV_IDr_fields[] = {
   6328     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   6329     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   6330     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   6331 };
   6332 
   6333 #endif
   6334 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6335     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6336     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6337     defined(BCM_56260_B0)
   6338 soc_field_info_t soc_UNIMAC0_UMAC_REV_ID_BCM53400_A0r_fields[] = {
   6339     { PATCHf, 8, 0, SOCF_LE|SOCF_RO },
   6340     { REVISION_ID_MAJORf, 8, 16, SOCF_LE|SOCF_RO },
   6341     { REVISION_ID_MINORf, 8, 8, SOCF_LE|SOCF_RO }
   6342 };
   6343 
   6344 #endif
   6345 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6346     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6347     defined(BCM_56450_B1)
   6348 soc_field_info_t soc_UNIMAC0_UMAC_RX_PKT_DROP_STATUSr_fields[] = {
   6349     { RX_IPG_INVALf, 1, 0, 0 }
   6350 };
   6351 
   6352 #endif
   6353 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6354     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6355     defined(BCM_56450_B1)
   6356 soc_field_info_t soc_UNIMAC0_UMAC_SYMMETRIC_IDLE_THRESHOLDr_fields[] = {
   6357     { THRESHOLD_VALUEf, 16, 0, SOCF_LE }
   6358 };
   6359 
   6360 #endif
   6361 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6362 soc_field_info_t soc_UNIMAC_PFC_CTRLr_fields[] = {
   6363     { FORCE_PFC_XONf, 1, 2, 0 },
   6364     { PFC_EIGHT_CLASSf, 1, 3, 0 },
   6365     { PFC_RX_ENBLf, 1, 1, 0 },
   6366     { PFC_STATS_ENf, 1, 5, 0 },
   6367     { PFC_TX_ENBLf, 1, 0, 0 },
   6368     { RX_PASS_PFC_FRMf, 1, 4, 0 }
   6369 };
   6370 
   6371 #endif
   6372 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   6373     defined(BCM_56840_A0) || defined(BCM_56840_B0) || \
   6374     defined(BCM_88732_A0)
   6375 soc_field_info_t soc_UNIMAC_PFC_CTRL_BCM56840_A0r_fields[] = {
   6376     { FORCE_PFC_XONf, 1, 2, SOCF_RES },
   6377     { PFC_RX_ENBLf, 1, 1, 0 },
   6378     { PFC_STATS_ENf, 1, 5, 0 },
   6379     { PFC_TX_ENBLf, 1, 0, 0 },
   6380     { RX_PASS_PFC_FRMf, 1, 4, 0 }
   6381 };
   6382 
   6383 #endif
   6384 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   6385     defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6386 soc_field_info_t soc_UNKNOWN_HGI_BITMAPr_fields[] = {
   6387     { BITMAPf, 25, 0, SOCF_LE }
   6388 };
   6389 
   6390 #endif
   6391 #if defined(BCM_56860_A0)
   6392 soc_field_info_t soc_UPMEP_TX_SOBMH_HDR_0_64r_fields[] = {
   6393     { SOBMH_HEADER_BYTE_0_7f, 64, 0, SOCF_LE }
   6394 };
   6395 
   6396 #endif
   6397 #if defined(BCM_56860_A0)
   6398 soc_field_info_t soc_UPMEP_TX_SOBMH_HDR_1_64r_fields[] = {
   6399     { SOBMH_HEADER_BYTE_8_15f, 64, 0, SOCF_LE }
   6400 };
   6401 
   6402 #endif
   6403 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6404     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6405 soc_field_info_t soc_USB2D_DEVCONFIGr_fields[] = {
   6406     { CSR_PRGf, 1, 17, 0 },
   6407     { DDRf, 1, 19, SOCF_RO },
   6408     { DIRf, 1, 6, SOCF_RO },
   6409     { FS_TIMEOUT_CALIBf, 3, 10, SOCF_LE },
   6410     { HALT_STATUSf, 1, 16, 0 },
   6411     { HS_TIMEOUT_CALIBf, 3, 13, SOCF_LE },
   6412     { LPM_AUTOf, 1, 20, 0 },
   6413     { LPM_ENf, 1, 21, 0 },
   6414     { PHY_ERROR_DETECTf, 1, 9, 0 },
   6415     { PIf, 1, 5, 0 },
   6416     { RWKPf, 1, 2, 0 },
   6417     { SET_DESCf, 1, 18, 0 },
   6418     { SPf, 1, 3, 0 },
   6419     { SPDf, 2, 0, SOCF_LE },
   6420     { SSf, 1, 4, 0 },
   6421     { STATUSf, 1, 7, 0 },
   6422     { STATUS_1f, 1, 8, 0 }
   6423 };
   6424 
   6425 #endif
   6426 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6427     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6428     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6429     defined(BCM_56260_B0)
   6430 soc_field_info_t soc_USB2D_DEVCONFIG_BCM53400_A0r_fields[] = {
   6431     { CSR_PRGf, 1, 17, 0 },
   6432     { DDRf, 1, 19, SOCF_RO },
   6433     { DIRf, 1, 6, SOCF_RO },
   6434     { FS_TIMEOUT_CALIBf, 3, 10, SOCF_LE },
   6435     { HALT_STATUSf, 1, 16, 0 },
   6436     { HS_TIMEOUT_CALIBf, 3, 13, SOCF_LE },
   6437     { LPM_AUTOf, 1, 20, 0 },
   6438     { LPM_ENf, 1, 21, 0 },
   6439     { PHY_ERROR_DETECTf, 1, 9, 0 },
   6440     { PIf, 1, 5, 0 },
   6441     { RWKPf, 1, 2, 0 },
   6442     { SET_DESCf, 1, 18, 0 },
   6443     { SPf, 1, 3, 0 },
   6444     { SPDf, 2, 0, SOCF_LE },
   6445     { SSf, 1, 4, 0 },
   6446     { STATUSf, 1, 7, 0 },
   6447     { STATUS_1f, 1, 8, 0 }
   6448 };
   6449 
   6450 #endif
   6451 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6452     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6453 soc_field_info_t soc_USB2D_DEVCTRLr_fields[] = {
   6454     { BEf, 1, 5, 0 },
   6455     { BFf, 1, 6, 0 },
   6456     { BRENf, 1, 8, 0 },
   6457     { BRLENf, 8, 16, SOCF_LE },
   6458     { CSR_DONEf, 1, 13, 0 },
   6459     { DEVNAKf, 1, 12, 0 },
   6460     { DUf, 1, 4, 0 },
   6461     { MODEf, 1, 9, 0 },
   6462     { RDEf, 1, 2, 0 },
   6463     { RESf, 1, 0, 0 },
   6464     { SCALEf, 1, 11, 0 },
   6465     { SDf, 1, 10, 0 },
   6466     { SRX_FLUSHf, 1, 14, 0 },
   6467     { TDEf, 1, 3, 0 },
   6468     { THEf, 1, 7, 0 },
   6469     { THLENf, 8, 24, SOCF_LE }
   6470 };
   6471 
   6472 #endif
   6473 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6474     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6475     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6476     defined(BCM_56260_B0)
   6477 soc_field_info_t soc_USB2D_DEVCTRL_BCM53400_A0r_fields[] = {
   6478     { BEf, 1, 5, 0 },
   6479     { BFf, 1, 6, 0 },
   6480     { BRENf, 1, 8, 0 },
   6481     { BRLENf, 8, 16, SOCF_LE },
   6482     { CSR_DONEf, 1, 13, 0 },
   6483     { DEVNAKf, 1, 12, 0 },
   6484     { DUf, 1, 4, 0 },
   6485     { MODEf, 1, 9, 0 },
   6486     { RDEf, 1, 2, 0 },
   6487     { RESf, 1, 0, 0 },
   6488     { SCALEf, 1, 11, 0 },
   6489     { SDf, 1, 10, 0 },
   6490     { SRX_FLUSHf, 1, 14, 0 },
   6491     { TDEf, 1, 3, 0 },
   6492     { THEf, 1, 7, 0 },
   6493     { THLENf, 8, 24, SOCF_LE }
   6494 };
   6495 
   6496 #endif
   6497 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6498     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6499 soc_field_info_t soc_USB2D_DEVINTRr_fields[] = {
   6500     { EARLY_SLEEPf, 1, 10, SOCF_W1TC },
   6501     { ENUM_DONEf, 1, 6, SOCF_W1TC },
   6502     { ESf, 1, 2, SOCF_W1TC },
   6503     { LPM_TKNf, 1, 8, SOCF_W1TC },
   6504     { RMTWKP_STATE_INTf, 1, 7, SOCF_W1TC },
   6505     { SCf, 1, 0, SOCF_W1TC },
   6506     { SIf, 1, 1, SOCF_W1TC },
   6507     { SLEEPf, 1, 9, SOCF_W1TC },
   6508     { SOFf, 1, 5, SOCF_W1TC },
   6509     { URf, 1, 3, SOCF_W1TC },
   6510     { USf, 1, 4, SOCF_W1TC }
   6511 };
   6512 
   6513 #endif
   6514 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6515     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6516 soc_field_info_t soc_USB2D_DEVINTRMASKr_fields[] = {
   6517     { EARLY_SLEEPf, 1, 10, 0 },
   6518     { LPM_TKNf, 1, 8, 0 },
   6519     { MASKf, 8, 0, SOCF_LE },
   6520     { SLEEPf, 1, 9, 0 }
   6521 };
   6522 
   6523 #endif
   6524 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6525     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6526     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6527     defined(BCM_56260_B0)
   6528 soc_field_info_t soc_USB2D_DEVINTRMASK_BCM53400_A0r_fields[] = {
   6529     { EARLY_SLEEPf, 1, 10, 0 },
   6530     { LPM_TKNf, 1, 8, 0 },
   6531     { MASKf, 8, 0, SOCF_LE },
   6532     { SLEEPf, 1, 9, 0 }
   6533 };
   6534 
   6535 #endif
   6536 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6537     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6538     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6539     defined(BCM_56260_B0)
   6540 soc_field_info_t soc_USB2D_DEVINTR_BCM53400_A0r_fields[] = {
   6541     { EARLY_SLEEPf, 1, 10, SOCF_W1TC },
   6542     { ENUM_DONEf, 1, 6, SOCF_W1TC },
   6543     { ESf, 1, 2, SOCF_W1TC },
   6544     { LPM_TKNf, 1, 8, SOCF_W1TC },
   6545     { RMTWKP_STATE_INTf, 1, 7, SOCF_W1TC },
   6546     { SCf, 1, 0, SOCF_W1TC },
   6547     { SIf, 1, 1, SOCF_W1TC },
   6548     { SLEEPf, 1, 9, SOCF_W1TC },
   6549     { SOFf, 1, 5, SOCF_W1TC },
   6550     { URf, 1, 3, SOCF_W1TC },
   6551     { USf, 1, 4, SOCF_W1TC }
   6552 };
   6553 
   6554 #endif
   6555 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6556     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6557 soc_field_info_t soc_USB2D_DEVSTATUSr_fields[] = {
   6558     { ALTf, 4, 8, SOCF_LE|SOCF_RO },
   6559     { CFGf, 4, 0, SOCF_LE|SOCF_RO },
   6560     { ENUM_SPDf, 2, 13, SOCF_LE|SOCF_RO },
   6561     { INTFf, 4, 4, SOCF_LE|SOCF_RO },
   6562     { PHY_ERRORf, 1, 16, SOCF_RO },
   6563     { RMTWKP_STATEf, 1, 17, SOCF_RO },
   6564     { RXFIFO_EMPTYf, 1, 15, SOCF_RO },
   6565     { SUSPf, 1, 12, SOCF_RO },
   6566     { TSf, 14, 18, SOCF_LE|SOCF_RO }
   6567 };
   6568 
   6569 #endif
   6570 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6571     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6572     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6573     defined(BCM_56260_B0)
   6574 soc_field_info_t soc_USB2D_DEVSTATUS_BCM53400_A0r_fields[] = {
   6575     { ALTf, 4, 8, SOCF_LE|SOCF_RO },
   6576     { CFGf, 4, 0, SOCF_LE|SOCF_RO },
   6577     { ENUM_SPDf, 2, 13, SOCF_LE|SOCF_RO },
   6578     { INTFf, 4, 4, SOCF_LE|SOCF_RO },
   6579     { PHY_ERRORf, 1, 16, SOCF_RO },
   6580     { RMTWKP_STATEf, 1, 17, SOCF_RO },
   6581     { RXFIFO_EMPTYf, 1, 15, SOCF_RO },
   6582     { SUSPf, 1, 12, SOCF_RO },
   6583     { TSf, 14, 18, SOCF_LE|SOCF_RO }
   6584 };
   6585 
   6586 #endif
   6587 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6588     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6589 soc_field_info_t soc_USB2D_ENDPNTINTRr_fields[] = {
   6590     { IN_EPf, 16, 0, SOCF_LE|SOCF_W1TC },
   6591     { OUT_EPf, 16, 16, SOCF_LE|SOCF_W1TC }
   6592 };
   6593 
   6594 #endif
   6595 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6596     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6597 soc_field_info_t soc_USB2D_ENDPNTINTRMASKr_fields[] = {
   6598     { IN_EP_MASKf, 10, 0, SOCF_LE },
   6599     { OUT_EP_MASKf, 10, 16, SOCF_LE }
   6600 };
   6601 
   6602 #endif
   6603 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6604     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6605     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6606     defined(BCM_56260_B0)
   6607 soc_field_info_t soc_USB2D_ENDPNTINTRMASK_BCM53400_A0r_fields[] = {
   6608     { IN_EP_MASKf, 10, 0, SOCF_LE },
   6609     { OUT_EP_MASKf, 10, 16, SOCF_LE }
   6610 };
   6611 
   6612 #endif
   6613 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6614     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6615     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6616     defined(BCM_56260_B0)
   6617 soc_field_info_t soc_USB2D_ENDPNTINTR_BCM53400_A0r_fields[] = {
   6618     { IN_EPf, 16, 0, SOCF_LE|SOCF_W1TC },
   6619     { OUT_EPf, 16, 16, SOCF_LE|SOCF_W1TC }
   6620 };
   6621 
   6622 #endif
   6623 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6624     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6625 soc_field_info_t soc_USB2D_ENDPNT_IN_BUFFER_0r_fields[] = {
   6626     { BUFF_SIZEf, 16, 0, SOCF_LE|SOCF_RO },
   6627     { ISO_IN_PIDf, 2, 16, SOCF_LE }
   6628 };
   6629 
   6630 #endif
   6631 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6632     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6633     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6634     defined(BCM_56260_B0)
   6635 soc_field_info_t soc_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r_fields[] = {
   6636     { BUFF_SIZEf, 16, 0, SOCF_LE|SOCF_RO },
   6637     { ISO_IN_PIDf, 2, 16, SOCF_LE }
   6638 };
   6639 
   6640 #endif
   6641 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6642     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6643 soc_field_info_t soc_USB2D_ENDPNT_IN_CTRL_0r_fields[] = {
   6644     { CLOSE_DESCf, 1, 11, SOCF_RO },
   6645     { CNAKf, 1, 8, SOCF_WO },
   6646     { ETf, 2, 4, SOCF_LE },
   6647     { Ff, 1, 1, 0 },
   6648     { MRX_FLUSHf, 1, 12, SOCF_RO },
   6649     { NAKf, 1, 6, SOCF_RO },
   6650     { Pf, 1, 3, 0 },
   6651     { RRDYf, 1, 9, SOCF_RO },
   6652     { Sf, 1, 0, 0 },
   6653     { SEND_NULLf, 1, 10, 0 },
   6654     { SNf, 1, 2, SOCF_RO },
   6655     { SNAKf, 1, 7, SOCF_WO }
   6656 };
   6657 
   6658 #endif
   6659 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6660     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6661     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6662     defined(BCM_56260_B0)
   6663 soc_field_info_t soc_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r_fields[] = {
   6664     { CLOSE_DESCf, 1, 11, SOCF_RO },
   6665     { CNAKf, 1, 8, SOCF_WO },
   6666     { ETf, 2, 4, SOCF_LE },
   6667     { Ff, 1, 1, 0 },
   6668     { MRX_FLUSHf, 1, 12, SOCF_RO },
   6669     { NAKf, 1, 6, SOCF_RO },
   6670     { Pf, 1, 3, 0 },
   6671     { RRDYf, 1, 9, SOCF_RO },
   6672     { Sf, 1, 0, 0 },
   6673     { SEND_NULLf, 1, 10, 0 },
   6674     { SNf, 1, 2, SOCF_RO },
   6675     { SNAKf, 1, 7, SOCF_WO }
   6676 };
   6677 
   6678 #endif
   6679 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6680     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6681 soc_field_info_t soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields[] = {
   6682     { DESPTRf, 32, 0, SOCF_LE }
   6683 };
   6684 
   6685 #endif
   6686 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6687     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6688     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6689     defined(BCM_56260_B0)
   6690 soc_field_info_t soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields[] = {
   6691     { DESPTRf, 32, 0, SOCF_LE }
   6692 };
   6693 
   6694 #endif
   6695 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6696     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6697 soc_field_info_t soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0r_fields[] = {
   6698     { MAX_PKT_SIZEf, 16, 0, SOCF_LE }
   6699 };
   6700 
   6701 #endif
   6702 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6703     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6704     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6705     defined(BCM_56260_B0)
   6706 soc_field_info_t soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r_fields[] = {
   6707     { MAX_PKT_SIZEf, 16, 0, SOCF_LE }
   6708 };
   6709 
   6710 #endif
   6711 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6712     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6713 soc_field_info_t soc_USB2D_ENDPNT_IN_STATUS_0r_fields[] = {
   6714     { BNAf, 1, 7, SOCF_W1TC },
   6715     { CDC_CLEARf, 1, 28, SOCF_W1TC },
   6716     { HEf, 1, 9, SOCF_W1TC },
   6717     { INf, 1, 6, SOCF_W1TC },
   6718     { ISO_IN_DONEf, 1, 23, 0 },
   6719     { MRXFIFO_EMPTYf, 1, 8, SOCF_RO },
   6720     { OUTf, 2, 4, SOCF_LE|SOCF_W1TC },
   6721     { RCSf, 1, 25, SOCF_W1TC },
   6722     { RSSf, 1, 26, SOCF_W1TC },
   6723     { RX_PKT_SIZEf, 12, 11, SOCF_LE },
   6724     { TDCf, 1, 10, SOCF_W1TC },
   6725     { TXEMPTYf, 1, 24, SOCF_W1TC },
   6726     { XFERDONE_TXEMPTYf, 1, 27, SOCF_W1TC }
   6727 };
   6728 
   6729 #endif
   6730 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6731     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6732     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6733     defined(BCM_56260_B0)
   6734 soc_field_info_t soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields[] = {
   6735     { BNAf, 1, 7, SOCF_W1TC },
   6736     { CDC_CLEARf, 1, 28, SOCF_W1TC },
   6737     { HEf, 1, 9, SOCF_W1TC },
   6738     { INf, 1, 6, SOCF_W1TC },
   6739     { ISO_IN_DONEf, 1, 23, 0 },
   6740     { MRXFIFO_EMPTYf, 1, 8, SOCF_RO },
   6741     { OUTf, 2, 4, SOCF_LE|SOCF_W1TC },
   6742     { RCSf, 1, 25, SOCF_W1TC },
   6743     { RSSf, 1, 26, SOCF_W1TC },
   6744     { RX_PKT_SIZEf, 12, 11, SOCF_LE },
   6745     { TDCf, 1, 10, SOCF_W1TC },
   6746     { TXEMPTYf, 1, 24, SOCF_W1TC },
   6747     { XFERDONE_TXEMPTYf, 1, 27, SOCF_W1TC }
   6748 };
   6749 
   6750 #endif
   6751 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6752     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6753 soc_field_info_t soc_USB2D_ENDPNT_OUT_BUFSIZE_0r_fields[] = {
   6754     { BUFF_SIZEf, 16, 16, SOCF_LE|SOCF_RO },
   6755     { MAX_PKT_SIZEf, 16, 0, SOCF_LE }
   6756 };
   6757 
   6758 #endif
   6759 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6760     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6761     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6762     defined(BCM_56260_B0)
   6763 soc_field_info_t soc_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r_fields[] = {
   6764     { BUFF_SIZEf, 16, 16, SOCF_LE|SOCF_RO },
   6765     { MAX_PKT_SIZEf, 16, 0, SOCF_LE }
   6766 };
   6767 
   6768 #endif
   6769 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6770     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6771 soc_field_info_t soc_USB2D_ENDPNT_OUT_CTRL_0r_fields[] = {
   6772     { CLOSE_DESCf, 1, 11, 0 },
   6773     { CNAKf, 1, 8, SOCF_WO },
   6774     { ETf, 2, 4, SOCF_LE },
   6775     { Ff, 1, 1, SOCF_RO },
   6776     { MRX_FLUSHf, 1, 12, SOCF_RO },
   6777     { NAKf, 1, 6, SOCF_RO },
   6778     { Pf, 1, 3, SOCF_RO },
   6779     { RRDYf, 1, 9, SOCF_RO },
   6780     { Sf, 1, 0, 0 },
   6781     { SEND_NULLf, 1, 10, 0 },
   6782     { SNf, 1, 2, 0 },
   6783     { SNAKf, 1, 7, SOCF_WO }
   6784 };
   6785 
   6786 #endif
   6787 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6788     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6789     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6790     defined(BCM_56260_B0)
   6791 soc_field_info_t soc_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r_fields[] = {
   6792     { CLOSE_DESCf, 1, 11, 0 },
   6793     { CNAKf, 1, 8, SOCF_WO },
   6794     { ETf, 2, 4, SOCF_LE },
   6795     { Ff, 1, 1, SOCF_RO },
   6796     { MRX_FLUSHf, 1, 12, SOCF_RO },
   6797     { NAKf, 1, 6, SOCF_RO },
   6798     { Pf, 1, 3, SOCF_RO },
   6799     { RRDYf, 1, 9, SOCF_RO },
   6800     { Sf, 1, 0, 0 },
   6801     { SEND_NULLf, 1, 10, 0 },
   6802     { SNf, 1, 2, 0 },
   6803     { SNAKf, 1, 7, SOCF_WO }
   6804 };
   6805 
   6806 #endif
   6807 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6808     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6809 soc_field_info_t soc_USB2D_ENDPNT_OUT_SETUPBUF_0r_fields[] = {
   6810     { SUBPTRf, 32, 0, SOCF_LE }
   6811 };
   6812 
   6813 #endif
   6814 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6815     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6816     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6817     defined(BCM_56260_B0)
   6818 soc_field_info_t soc_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r_fields[] = {
   6819     { SUBPTRf, 32, 0, SOCF_LE }
   6820 };
   6821 
   6822 #endif
   6823 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6824     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6825 soc_field_info_t soc_USB2D_IDM_IDM_IO_CONTROL_DIRECTr_fields[] = {
   6826     { ARCACHEf, 4, 6, SOCF_LE },
   6827     { ASYNC_RESUME_DISABLE_If, 1, 17, 0 },
   6828     { AWCACHEf, 4, 2, SOCF_LE },
   6829     { CLK_ENABLEf, 1, 0, 0 },
   6830     { OVERRIDE_AHBS_HSELf, 1, 28, 0 },
   6831     { OVERRIDE_AHBS_HSEL_CSRf, 1, 29, 0 },
   6832     { OVERRIDE_AHBS_HSEL_FIFOSf, 1, 30, 0 },
   6833     { OVERRIDE_HREADY_TO_SLAVEf, 1, 31, 0 },
   6834     { SS_CDC_ISO_SHORT_DIS_If, 1, 16, 0 },
   6835     { SS_CLEAR_NAK_NEMPTY_EN_If, 1, 24, 0 },
   6836     { SS_CLOSE_DESC_ENA_If, 1, 20, 0 },
   6837     { SS_DIS_ISO_OUT_NAK_EN_If, 1, 25, 0 },
   6838     { SS_SEND_NULL_ENA_If, 1, 19, 0 },
   6839     { SS_SETCLR_RMTWKP_ENA_If, 1, 18, 0 },
   6840     { SS_SET_CLR_STALL_ENA_If, 1, 22, 0 },
   6841     { SS_SET_OPMODE_POR_If, 1, 23, 0 },
   6842     { SS_SET_STALL_NEMPTY_EN_If, 1, 26, 0 },
   6843     { SS_SNAK_BIT_ENH_EN_If, 1, 21, 0 }
   6844 };
   6845 
   6846 #endif
   6847 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6848     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6849     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6850     defined(BCM_56260_B0)
   6851 soc_field_info_t soc_USB2D_IDM_IDM_IO_CONTROL_DIRECT_BCM53400_A0r_fields[] = {
   6852     { ARCACHEf, 4, 6, SOCF_LE },
   6853     { ASYNC_RESUME_DISABLE_If, 1, 17, 0 },
   6854     { AWCACHEf, 4, 2, SOCF_LE },
   6855     { BYPASS_CTf, 1, 14, 0 },
   6856     { CLK_ENABLEf, 1, 0, 0 },
   6857     { CTf, 1, 15, 0 },
   6858     { OVERRIDE_AHBS_HSELf, 1, 28, 0 },
   6859     { OVERRIDE_AHBS_HSEL_CSRf, 1, 29, 0 },
   6860     { OVERRIDE_AHBS_HSEL_FIFOSf, 1, 30, 0 },
   6861     { OVERRIDE_HREADY_TO_SLAVEf, 1, 31, 0 },
   6862     { SS_CDC_ISO_SHORT_DIS_If, 1, 16, 0 },
   6863     { SS_CLEAR_NAK_NEMPTY_EN_If, 1, 24, 0 },
   6864     { SS_CLOSE_DESC_ENA_If, 1, 20, 0 },
   6865     { SS_DIS_ISO_OUT_NAK_EN_If, 1, 25, 0 },
   6866     { SS_SEND_NULL_ENA_If, 1, 19, 0 },
   6867     { SS_SETCLR_RMTWKP_ENA_If, 1, 18, 0 },
   6868     { SS_SET_CLR_STALL_ENA_If, 1, 22, 0 },
   6869     { SS_SET_OPMODE_POR_If, 1, 23, 0 },
   6870     { SS_SET_STALL_NEMPTY_EN_If, 1, 26, 0 },
   6871     { SS_SNAK_BIT_ENH_EN_If, 1, 21, 0 }
   6872 };
   6873 
   6874 #endif
   6875 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6876     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6877 soc_field_info_t soc_USB2D_LPMCTRLSTATUSr_fields[] = {
   6878     { HIRD_THRESHOLDf, 5, 25, SOCF_LE },
   6879     { LPM_BLINK_STATEf, 4, 4, SOCF_LE|SOCF_RO },
   6880     { LPM_BREMOTEWAKEf, 1, 12, SOCF_RO },
   6881     { LPM_ENDPOINTf, 4, 0, SOCF_LE|SOCF_RO },
   6882     { LPM_HIRDf, 4, 8, SOCF_LE|SOCF_RO },
   6883     { LPM_HSK_SENTf, 2, 13, SOCF_LE|SOCF_RO },
   6884     { LPM_L1SUSPEND_STATUSf, 1, 16, SOCF_RO },
   6885     { LPM_RESPf, 2, 30, SOCF_LE },
   6886     { LPM_SLEEP_STATUSf, 1, 15, SOCF_RO },
   6887     { NYET_CONTROLf, 1, 24, 0 }
   6888 };
   6889 
   6890 #endif
   6891 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6892     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6893     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6894     defined(BCM_56260_B0)
   6895 soc_field_info_t soc_USB2D_LPMCTRLSTATUS_BCM53400_A0r_fields[] = {
   6896     { HIRD_THRESHOLDf, 5, 25, SOCF_LE },
   6897     { LPM_BLINK_STATEf, 4, 4, SOCF_LE|SOCF_RO },
   6898     { LPM_BREMOTEWAKEf, 1, 12, SOCF_RO },
   6899     { LPM_ENDPOINTf, 4, 0, SOCF_LE|SOCF_RO },
   6900     { LPM_HIRDf, 4, 8, SOCF_LE|SOCF_RO },
   6901     { LPM_HSK_SENTf, 2, 13, SOCF_LE|SOCF_RO },
   6902     { LPM_L1SUSPEND_STATUSf, 1, 16, SOCF_RO },
   6903     { LPM_RESPf, 2, 30, SOCF_LE },
   6904     { LPM_SLEEP_STATUSf, 1, 15, SOCF_RO },
   6905     { NYET_CONTROLf, 1, 24, 0 }
   6906 };
   6907 
   6908 #endif
   6909 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6910     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6911 soc_field_info_t soc_USB2D_RECPACKFRAMNO_0r_fields[] = {
   6912     { FRAME_NUMBERf, 16, 0, SOCF_LE|SOCF_RO },
   6913     { ISO_OUT_PIDf, 2, 16, SOCF_LE|SOCF_RO }
   6914 };
   6915 
   6916 #endif
   6917 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6918     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6919     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6920     defined(BCM_56260_B0)
   6921 soc_field_info_t soc_USB2D_RECPACKFRAMNO_0_BCM53400_A0r_fields[] = {
   6922     { FRAME_NUMBERf, 16, 0, SOCF_LE|SOCF_RO },
   6923     { ISO_OUT_PIDf, 2, 16, SOCF_LE|SOCF_RO }
   6924 };
   6925 
   6926 #endif
   6927 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6928     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6929 soc_field_info_t soc_USB2D_RELEASE_NUMBERr_fields[] = {
   6930     { RELEASE_NUMBERf, 32, 0, SOCF_LE|SOCF_RO }
   6931 };
   6932 
   6933 #endif
   6934 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6935     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6936     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6937     defined(BCM_56260_B0)
   6938 soc_field_info_t soc_USB2D_RELEASE_NUMBER_BCM53400_A0r_fields[] = {
   6939     { RELEASE_NUMBERf, 32, 0, SOCF_LE|SOCF_RO }
   6940 };
   6941 
   6942 #endif
   6943 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6944     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6945 soc_field_info_t soc_USB2D_UDC20_ENDPOINT0r_fields[] = {
   6946     { ASWf, 4, 15, SOCF_LE },
   6947     { CNWf, 4, 7, SOCF_LE },
   6948     { EDf, 1, 4, 0 },
   6949     { ETf, 2, 5, SOCF_LE },
   6950     { INWf, 4, 11, SOCF_LE },
   6951     { LENf, 4, 0, SOCF_LE },
   6952     { MPSf, 11, 19, SOCF_LE }
   6953 };
   6954 
   6955 #endif
   6956 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6957     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6958     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6959     defined(BCM_56260_B0)
   6960 soc_field_info_t soc_USB2D_UDC20_ENDPOINT0_BCM53400_A0r_fields[] = {
   6961     { ASWf, 4, 15, SOCF_LE },
   6962     { CNWf, 4, 7, SOCF_LE },
   6963     { EDf, 1, 4, 0 },
   6964     { ETf, 2, 5, SOCF_LE },
   6965     { INWf, 4, 11, SOCF_LE },
   6966     { LENf, 4, 0, SOCF_LE },
   6967     { MPSf, 11, 19, SOCF_LE }
   6968 };
   6969 
   6970 #endif
   6971 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   6972     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   6973 soc_field_info_t soc_USB2_IDM_IDM_IO_CONTROL_DIRECTr_fields[] = {
   6974     { APP_START_CLK_If, 1, 12, 0 },
   6975     { ARCACHEf, 4, 6, SOCF_LE },
   6976     { AWCACHEf, 4, 2, SOCF_LE },
   6977     { CLK_ENABLEf, 1, 0, 0 },
   6978     { SUSPEND_OVERRIDE_0f, 1, 13, 0 },
   6979     { SUSPEND_OVERRIDE_1f, 1, 14, 0 }
   6980 };
   6981 
   6982 #endif
   6983 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6984     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6985     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6986     defined(BCM_56260_B0)
   6987 soc_field_info_t soc_USB2_IDM_IDM_IO_CONTROL_DIRECT_BCM53400_A0r_fields[] = {
   6988     { APP_START_CLK_If, 1, 12, 0 },
   6989     { ARCACHEf, 4, 6, SOCF_LE },
   6990     { ARUSERf, 5, 17, SOCF_LE },
   6991     { AWCACHEf, 4, 2, SOCF_LE },
   6992     { AWUSERf, 5, 22, SOCF_LE },
   6993     { BYPASS_CTf, 1, 29, 0 },
   6994     { CLK_ENABLEf, 1, 0, 0 },
   6995     { CTf, 1, 28, 0 },
   6996     { SUSPEND_OVERRIDE_0f, 1, 13, 0 },
   6997     { SUSPEND_OVERRIDE_1f, 1, 14, 0 },
   6998     { SUSPEND_OVERRIDE_2f, 1, 15, 0 }
   6999 };
   7000 
   7001 #endif
   7002 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7003     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7004 soc_field_info_t soc_USB2_IDM_IDM_IO_STATUSr_fields[] = {
   7005     { RESERVEDf, 32, 0, SOCF_LE|SOCF_RO|SOCF_RES }
   7006 };
   7007 
   7008 #endif
   7009 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7010     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7011     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7012     defined(BCM_56260_B0)
   7013 soc_field_info_t soc_USB2_IDM_IDM_IO_STATUS_BCM53400_A0r_fields[] = {
   7014     { RESERVEDf, 32, 0, SOCF_LE|SOCF_RO|SOCF_RES }
   7015 };
   7016 
   7017 #endif
   7018 #if defined(BCM_56370_A0)
   7019 soc_field_info_t soc_USBD_BDC_AIUDMAr_fields[] = {
   7020     { RESERVEDf, 16, 0, SOCF_LE|SOCF_RO|SOCF_RES },
   7021     { RTDf, 2, 18, SOCF_LE },
   7022     { RTFf, 2, 16, SOCF_LE },
   7023     { WEDf, 2, 24, SOCF_LE },
   7024     { WRDf, 2, 26, SOCF_LE }
   7025 };
   7026 
   7027 #endif
   7028 #if defined(BCM_56370_A0)
   7029 soc_field_info_t soc_USBD_BDC_AIUIEPS0r_fields[] = {
   7030     { BNAf, 1, 31, 0 },
   7031     { CHNf, 4, 8, SOCF_LE },
   7032     { EPGf, 2, 14, SOCF_LE },
   7033     { LEDf, 2, 27, SOCF_LE },
   7034     { LRDf, 2, 29, SOCF_LE },
   7035     { RCFDf, 2, 0, SOCF_LE },
   7036     { RCFMf, 3, 2, SOCF_LE },
   7037     { RCFNf, 3, 5, SOCF_LE },
   7038     { RESERVEDf, 2, 12, SOCF_LE|SOCF_RO|SOCF_RES }
   7039 };
   7040 
   7041 #endif
   7042 #if defined(BCM_56370_A0)
   7043 soc_field_info_t soc_USBD_BDC_AXILPMr_fields[] = {
   7044     { ENBf, 1, 31, 0 },
   7045     { ITTf, 3, 0, SOCF_LE },
   7046     { RESERVEDf, 28, 3, SOCF_LE|SOCF_RO|SOCF_RES }
   7047 };
   7048 
   7049 #endif
   7050 #if defined(BCM_56370_A0)
   7051 soc_field_info_t soc_USBD_BDC_AXIQOSr_fields[] = {
   7052     { RQOS0f, 4, 0, SOCF_LE },
   7053     { RQOS1f, 4, 4, SOCF_LE },
   7054     { RQOS2f, 4, 8, SOCF_LE },
   7055     { RQOS3f, 4, 12, SOCF_LE },
   7056     { WQOS0f, 4, 16, SOCF_LE },
   7057     { WQOS1f, 4, 20, SOCF_LE },
   7058     { WQOS2f, 4, 24, SOCF_LE },
   7059     { WQOS3f, 4, 28, SOCF_LE }
   7060 };
   7061 
   7062 #endif
   7063 #if defined(BCM_56370_A0)
   7064 soc_field_info_t soc_USBD_BDC_AXIRDAr_fields[] = {
   7065     { RESERVEDf, 7, 9, SOCF_LE|SOCF_RO|SOCF_RES },
   7066     { RFPCf, 1, 27, 0 },
   7067     { RSAf, 9, 0, SOCF_LE },
   7068     { RTSf, 4, 28, SOCF_LE },
   7069     { RUAf, 9, 16, SOCF_LE }
   7070 };
   7071 
   7072 #endif
   7073 #if defined(BCM_56370_A0)
   7074 soc_field_info_t soc_USBD_BDC_AXIWRAr_fields[] = {
   7075     { RESERVEDf, 7, 9, SOCF_LE|SOCF_RO|SOCF_RES },
   7076     { WFPCf, 1, 27, 0 },
   7077     { WSAf, 9, 0, SOCF_LE },
   7078     { WTSf, 4, 28, SOCF_LE },
   7079     { WUAf, 9, 16, SOCF_LE }
   7080 };
   7081 
   7082 #endif
   7083 #if defined(BCM_56370_A0)
   7084 soc_field_info_t soc_USBD_BDC_BDCCAP0r_fields[] = {
   7085     { RESERVEDf, 8, 0, SOCF_LE|SOCF_RO|SOCF_RES },
   7086     { U1Lf, 8, 8, SOCF_LE|SOCF_RO },
   7087     { U2Lf, 16, 16, SOCF_LE|SOCF_RO }
   7088 };
   7089 
   7090 #endif
   7091 #if defined(BCM_56370_A0)
   7092 soc_field_info_t soc_USBD_BDC_BDCCAP1r_fields[] = {
   7093     { ALCf, 1, 8, SOCF_RO },
   7094     { BIAf, 1, 1, SOCF_RO },
   7095     { FWKf, 1, 3, SOCF_RO },
   7096     { HLCf, 1, 7, SOCF_RO },
   7097     { ILAf, 3, 4, SOCF_LE|SOCF_RO },
   7098     { L1Lf, 8, 24, SOCF_LE|SOCF_RO },
   7099     { LTMf, 1, 2, SOCF_RO },
   7100     { P64f, 1, 0, SOCF_RO },
   7101     { RESERVEDf, 15, 9, SOCF_LE|SOCF_RO|SOCF_RES }
   7102 };
   7103 
   7104 #endif
   7105 #if defined(BCM_56370_A0)
   7106 soc_field_info_t soc_USBD_BDC_BDCCFG0r_fields[] = {
   7107     { ITSf, 5, 11, SOCF_LE|SOCF_RO },
   7108     { MAJf, 8, 24, SOCF_LE|SOCF_RO },
   7109     { MINf, 8, 16, SOCF_LE|SOCF_RO },
   7110     { PGSf, 3, 8, SOCF_LE|SOCF_RO },
   7111     { RESERVEDf, 5, 3, SOCF_LE|SOCF_RO|SOCF_RES },
   7112     { SPBf, 3, 0, SOCF_LE|SOCF_RO }
   7113 };
   7114 
   7115 #endif
   7116 #if defined(BCM_56370_A0)
   7117 soc_field_info_t soc_USBD_BDC_BDCCFG1r_fields[] = {
   7118     { MPSIf, 4, 0, SOCF_LE|SOCF_RO },
   7119     { RESERVEDf, 27, 5, SOCF_LE|SOCF_RO|SOCF_RES },
   7120     { SSIf, 1, 4, SOCF_RO }
   7121 };
   7122 
   7123 #endif
   7124 #if defined(BCM_56370_A0)
   7125 soc_field_info_t soc_USBD_BDC_BDCSCr_fields[] = {
   7126     { CEPf, 1, 16, 0 },
   7127     { CERf, 1, 18, 0 },
   7128     { CEWf, 1, 17, 0 },
   7129     { CNRf, 1, 23, SOCF_RO },
   7130     { COPf, 3, 29, SOCF_LE },
   7131     { COSf, 1, 28, 0 },
   7132     { GIEf, 1, 1, 0 },
   7133     { GIPf, 1, 0, SOCF_RO },
   7134     { MUMf, 1, 2, 0 },
   7135     { RESERVEDf, 4, 3, SOCF_LE|SOCF_RO|SOCF_RES },
   7136     { SRBEL1f, 1, 12, 0 },
   7137     { SRBESSf, 1, 13, 0 },
   7138     { SRBHRLf, 1, 10, 0 },
   7139     { SRBHRSf, 1, 11, 0 },
   7140     { SRBRL1f, 1, 8, 0 },
   7141     { SRBRSSf, 1, 9, 0 },
   7142     { SRBSIBf, 1, 14, 0 },
   7143     { SRMMCWf, 1, 7, 0 },
   7144     { STSf, 3, 20, SOCF_LE|SOCF_RO }
   7145 };
   7146 
   7147 #endif
   7148 #if defined(BCM_56370_A0)
   7149 soc_field_info_t soc_USBD_BDC_BIUSPCr_fields[] = {
   7150     { MAJf, 4, 28, SOCF_LE|SOCF_RO },
   7151     { MINf, 4, 24, SOCF_LE|SOCF_RO },
   7152     { RESERVEDf, 15, 5, SOCF_LE|SOCF_RO|SOCF_RES },
   7153     { RLSf, 4, 20, SOCF_LE|SOCF_RO },
   7154     { SPIf, 3, 2, SOCF_LE|SOCF_RO },
   7155     { TYPf, 2, 0, SOCF_LE|SOCF_RO }
   7156 };
   7157 
   7158 #endif
   7159 #if defined(BCM_56370_A0)
   7160 soc_field_info_t soc_USBD_BDC_CMDPAR0r_fields[] = {
   7161     { PARf, 32, 0, SOCF_LE }
   7162 };
   7163 
   7164 #endif
   7165 #if defined(BCM_56370_A0)
   7166 soc_field_info_t soc_USBD_BDC_CMDSCr_fields[] = {
   7167     { CIDf, 4, 28, SOCF_LE },
   7168     { CMDf, 4, 0, SOCF_LE },
   7169     { CSAf, 2, 15, SOCF_LE },
   7170     { CSTf, 4, 6, SOCF_LE },
   7171     { CWSf, 1, 5, 0 },
   7172     { EPNf, 5, 10, SOCF_LE },
   7173     { RESERVEDf, 1, 4, SOCF_RO|SOCF_RES },
   7174     { SRDf, 1, 27, 0 },
   7175     { SRRf, 5, 20, SOCF_LE },
   7176     { SUBf, 3, 17, SOCF_LE }
   7177 };
   7178 
   7179 #endif
   7180 #if defined(BCM_56370_A0)
   7181 soc_field_info_t soc_USBD_BDC_CSRSPCr_fields[] = {
   7182     { MAJf, 4, 28, SOCF_LE|SOCF_RO },
   7183     { MINf, 4, 24, SOCF_LE|SOCF_RO },
   7184     { RESERVEDf, 18, 2, SOCF_LE|SOCF_RO|SOCF_RES },
   7185     { RLSf, 4, 20, SOCF_LE|SOCF_RO },
   7186     { TYPf, 2, 0, SOCF_LE|SOCF_RO }
   7187 };
   7188 
   7189 #endif
   7190 #if defined(BCM_56370_A0)
   7191 soc_field_info_t soc_USBD_BDC_DVCNPHr_fields[] = {
   7192     { NPHf, 32, 0, SOCF_LE|SOCF_RO }
   7193 };
   7194 
   7195 #endif
   7196 #if defined(BCM_56370_A0)
   7197 soc_field_info_t soc_USBD_BDC_DVCNPLr_fields[] = {
   7198     { NPLf, 32, 0, SOCF_LE|SOCF_RO }
   7199 };
   7200 
   7201 #endif
   7202 #if defined(BCM_56370_A0)
   7203 soc_field_info_t soc_USBD_BDC_DVCSAr_fields[] = {
   7204     { DVSf, 5, 27, SOCF_LE },
   7205     { RESERVEDf, 7, 20, SOCF_LE|SOCF_RO|SOCF_RES },
   7206     { RSTf, 20, 0, SOCF_LE }
   7207 };
   7208 
   7209 #endif
   7210 #if defined(BCM_56370_A0)
   7211 soc_field_info_t soc_USBD_BDC_DVCSBr_fields[] = {
   7212     { DAf, 7, 0, SOCF_LE },
   7213     { PSPf, 4, 8, SOCF_LE },
   7214     { RESERVEDf, 1, 7, SOCF_RO|SOCF_RES }
   7215 };
   7216 
   7217 #endif
   7218 #if defined(BCM_56370_A0)
   7219 soc_field_info_t soc_USBD_BDC_DVCSCr_fields[] = {
   7220     { OPQf, 32, 0, SOCF_LE }
   7221 };
   7222 
   7223 #endif
   7224 #if defined(BCM_56370_A0)
   7225 soc_field_info_t soc_USBD_BDC_DVCSTPr_fields[] = {
   7226     { ACFf, 4, 24, SOCF_LE },
   7227     { BPDf, 1, 1, SOCF_RO },
   7228     { NDRf, 1, 0, SOCF_RO },
   7229     { RESERVEDf, 22, 2, SOCF_LE|SOCF_RO|SOCF_RES },
   7230     { SPDf, 3, 29, SOCF_LE|SOCF_RO }
   7231 };
   7232 
   7233 #endif
   7234 #if defined(BCM_56370_A0)
   7235 soc_field_info_t soc_USBD_BDC_ECHAIUr_fields[] = {
   7236     { BDFSf, 3, 20, SOCF_LE },
   7237     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   7238     { DMAf, 2, 30, SOCF_LE },
   7239     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   7240     { RESERVEDf, 7, 23, SOCF_LE|SOCF_RO|SOCF_RES },
   7241     { WPFf, 4, 16, SOCF_LE|SOCF_RO }
   7242 };
   7243 
   7244 #endif
   7245 #if defined(BCM_56370_A0)
   7246 soc_field_info_t soc_USBD_BDC_ECHBIUr_fields[] = {
   7247     { AALf, 1, 19, SOCF_RO },
   7248     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   7249     { CLKf, 11, 21, SOCF_LE|SOCF_RO },
   7250     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   7251     { RESERVEDf, 1, 20, SOCF_RO|SOCF_RES },
   7252     { WIDf, 3, 16, SOCF_LE|SOCF_RO }
   7253 };
   7254 
   7255 #endif
   7256 #if defined(BCM_56370_A0)
   7257 soc_field_info_t soc_USBD_BDC_ECHCSRr_fields[] = {
   7258     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   7259     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   7260     { RESERVEDf, 13, 19, SOCF_LE|SOCF_RO|SOCF_RES },
   7261     { WIDf, 3, 16, SOCF_LE|SOCF_RO }
   7262 };
   7263 
   7264 #endif
   7265 #if defined(BCM_56370_A0)
   7266 soc_field_info_t soc_USBD_BDC_ECHDVCr_fields[] = {
   7267     { ACFf, 5, 23, SOCF_LE },
   7268     { ACSf, 1, 22, 0 },
   7269     { CCCf, 1, 28, 0 },
   7270     { CIDf, 8, 0, SOCF_LE },
   7271     { CLKf, 2, 20, SOCF_LE },
   7272     { DEPSf, 1, 18, 0 },
   7273     { IRAf, 1, 19, 0 },
   7274     { NCPf, 8, 8, SOCF_LE },
   7275     { RESERVEDf, 1, 17, SOCF_RO|SOCF_RES },
   7276     { SPDf, 3, 29, SOCF_LE },
   7277     { TEDAf, 1, 16, 0 }
   7278 };
   7279 
   7280 #endif
   7281 #if defined(BCM_56370_A0)
   7282 soc_field_info_t soc_USBD_BDC_ECHFSCr_fields[] = {
   7283     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   7284     { FSIf, 2, 30, SOCF_LE|SOCF_RO },
   7285     { FSICH0f, 2, 28, SOCF_LE|SOCF_RO },
   7286     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   7287     { RESERVEDf, 4, 24, SOCF_LE|SOCF_RO|SOCF_RES },
   7288     { RRMBf, 4, 16, SOCF_LE|SOCF_RO },
   7289     { WRMBf, 4, 20, SOCF_LE|SOCF_RO }
   7290 };
   7291 
   7292 #endif
   7293 #if defined(BCM_56370_A0)
   7294 soc_field_info_t soc_USBD_BDC_ECHIRAr_fields[] = {
   7295     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   7296     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   7297     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   7298 };
   7299 
   7300 #endif
   7301 #if defined(BCM_56370_A0)
   7302 soc_field_info_t soc_USBD_BDC_ECHLNKr_fields[] = {
   7303     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   7304     { HSTf, 1, 16, SOCF_RO },
   7305     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   7306     { RESERVEDf, 15, 17, SOCF_LE|SOCF_RO|SOCF_RES }
   7307 };
   7308 
   7309 #endif
   7310 #if defined(BCM_56370_A0)
   7311 soc_field_info_t soc_USBD_BDC_ECHPHYr_fields[] = {
   7312     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   7313     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   7314     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   7315 };
   7316 
   7317 #endif
   7318 #if defined(BCM_56370_A0)
   7319 soc_field_info_t soc_USBD_BDC_ECHPRTr_fields[] = {
   7320     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   7321     { HSTf, 1, 16, SOCF_RO },
   7322     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   7323     { RESERVEDf, 15, 17, SOCF_LE|SOCF_RO|SOCF_RES }
   7324 };
   7325 
   7326 #endif
   7327 #if defined(BCM_56370_A0)
   7328 soc_field_info_t soc_USBD_BDC_ECHRBVr_fields[] = {
   7329     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   7330     { MAJf, 4, 28, SOCF_LE|SOCF_RO },
   7331     { MINf, 4, 24, SOCF_LE|SOCF_RO },
   7332     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   7333     { RLSf, 8, 16, SOCF_LE|SOCF_RO }
   7334 };
   7335 
   7336 #endif
   7337 #if defined(BCM_56370_A0)
   7338 soc_field_info_t soc_USBD_BDC_ECHRSVr_fields[] = {
   7339     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   7340     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   7341     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   7342 };
   7343 
   7344 #endif
   7345 #if defined(BCM_56370_A0)
   7346 soc_field_info_t soc_USBD_BDC_EPS0r_fields[] = {
   7347     { BPLf, 28, 4, SOCF_LE },
   7348     { RESERVEDf, 4, 0, SOCF_LE|SOCF_RO|SOCF_RES }
   7349 };
   7350 
   7351 #endif
   7352 #if defined(BCM_56370_A0)
   7353 soc_field_info_t soc_USBD_BDC_EPS1r_fields[] = {
   7354     { BPHf, 32, 0, SOCF_LE }
   7355 };
   7356 
   7357 #endif
   7358 #if defined(BCM_56370_A0)
   7359 soc_field_info_t soc_USBD_BDC_EPS2r_fields[] = {
   7360     { MBSf, 4, 6, SOCF_LE },
   7361     { MPSf, 11, 10, SOCF_LE },
   7362     { MULf, 2, 4, SOCF_LE },
   7363     { PSIf, 4, 28, SOCF_LE },
   7364     { RESERVEDf, 1, 21, SOCF_RO|SOCF_RES },
   7365     { SIf, 4, 0, SOCF_LE },
   7366     { SSIf, 4, 24, SOCF_LE },
   7367     { TYPf, 2, 22, SOCF_LE }
   7368 };
   7369 
   7370 #endif
   7371 #if defined(BCM_56370_A0)
   7372 soc_field_info_t soc_USBD_BDC_EPS3r_fields[] = {
   7373     { EPNf, 5, 16, SOCF_LE },
   7374     { EPSf, 5, 27, SOCF_LE },
   7375     { RESERVEDf, 6, 21, SOCF_LE|SOCF_RO|SOCF_RES },
   7376     { SIDf, 16, 0, SOCF_LE }
   7377 };
   7378 
   7379 #endif
   7380 #if defined(BCM_56370_A0)
   7381 soc_field_info_t soc_USBD_BDC_EXCPBAr_fields[] = {
   7382     { ECBAf, 10, 2, SOCF_LE|SOCF_RO },
   7383     { RESERVEDf, 2, 0, SOCF_LE|SOCF_RO|SOCF_RES }
   7384 };
   7385 
   7386 #endif
   7387 #if defined(BCM_56370_A0)
   7388 soc_field_info_t soc_USBD_BDC_FSCHICr_fields[] = {
   7389     { BSIZf, 6, 0, SOCF_LE|SOCF_RO },
   7390     { FSIZf, 6, 18, SOCF_LE|SOCF_RO },
   7391     { NCSf, 4, 28, SOCF_LE|SOCF_RO },
   7392     { PSIZf, 6, 12, SOCF_LE|SOCF_RO },
   7393     { RESERVEDf, 4, 24, SOCF_LE|SOCF_RO|SOCF_RES },
   7394     { RSIZf, 6, 6, SOCF_LE|SOCF_RO }
   7395 };
   7396 
   7397 #endif
   7398 #if defined(BCM_56370_A0)
   7399 soc_field_info_t soc_USBD_BDC_FSCHOCr_fields[] = {
   7400     { BSIZf, 6, 0, SOCF_LE|SOCF_RO },
   7401     { NCSf, 4, 28, SOCF_LE|SOCF_RO },
   7402     { RESERVEDf, 22, 6, SOCF_LE|SOCF_RO|SOCF_RES }
   7403 };
   7404 
   7405 #endif
   7406 #if defined(BCM_56370_A0)
   7407 soc_field_info_t soc_USBD_BDC_FSCIBDC0r_fields[] = {
   7408     { BOFFf, 10, 6, SOCF_LE },
   7409     { BSIZf, 6, 0, SOCF_LE },
   7410     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   7411 };
   7412 
   7413 #endif
   7414 #if defined(BCM_56370_A0)
   7415 soc_field_info_t soc_USBD_BDC_FSCICH0r_fields[] = {
   7416     { FOFFf, 10, 6, SOCF_LE },
   7417     { FSIZf, 6, 0, SOCF_LE },
   7418     { ROFFf, 10, 22, SOCF_LE },
   7419     { RSIZf, 6, 16, SOCF_LE }
   7420 };
   7421 
   7422 #endif
   7423 #if defined(BCM_56370_A0)
   7424 soc_field_info_t soc_USBD_BDC_FSCICHX0r_fields[] = {
   7425     { POFFf, 10, 6, SOCF_LE },
   7426     { PSIZf, 6, 0, SOCF_LE },
   7427     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   7428 };
   7429 
   7430 #endif
   7431 #if defined(BCM_56370_A0)
   7432 soc_field_info_t soc_USBD_BDC_FSCOUTr_fields[] = {
   7433     { FSIZf, 8, 18, SOCF_LE|SOCF_RO },
   7434     { PSIZf, 6, 12, SOCF_LE|SOCF_RO },
   7435     { RESERVEDf, 12, 0, SOCF_LE|SOCF_RO|SOCF_RES }
   7436 };
   7437 
   7438 #endif
   7439 #if defined(BCM_56370_A0)
   7440 soc_field_info_t soc_USBD_BDC_INTCLS0r_fields[] = {
   7441     { ICCf, 16, 16, SOCF_LE|SOCF_RO },
   7442     { ICIf, 16, 0, SOCF_LE }
   7443 };
   7444 
   7445 #endif
   7446 #if defined(BCM_56370_A0)
   7447 soc_field_info_t soc_USBD_BDC_IRAADRr_fields[] = {
   7448     { ADRf, 22, 2, SOCF_LE },
   7449     { MODf, 1, 0, 0 },
   7450     { RESERVEDf, 1, 1, SOCF_RO|SOCF_RES }
   7451 };
   7452 
   7453 #endif
   7454 #if defined(BCM_56370_A0)
   7455 soc_field_info_t soc_USBD_BDC_IRADATr_fields[] = {
   7456     { DATf, 32, 0, SOCF_LE }
   7457 };
   7458 
   7459 #endif
   7460 #if defined(BCM_56370_A0)
   7461 soc_field_info_t soc_USBD_BDC_LNKHSCr_fields[] = {
   7462     { ASMf, 2, 4, SOCF_LE },
   7463     { CMDf, 2, 2, SOCF_LE|SOCF_WO },
   7464     { RESERVEDf, 1, 1, SOCF_RO|SOCF_RES },
   7465     { RSLf, 2, 6, SOCF_LE },
   7466     { STBf, 1, 0, SOCF_WO },
   7467     { TMRf, 16, 16, SOCF_LE }
   7468 };
   7469 
   7470 #endif
   7471 #if defined(BCM_56370_A0)
   7472 soc_field_info_t soc_USBD_BDC_LNKHSRr_fields[] = {
   7473     { RDLYf, 8, 24, SOCF_LE|SOCF_RO },
   7474     { RDPPf, 8, 8, SOCF_LE|SOCF_RO },
   7475     { TDPPf, 8, 16, SOCF_LE|SOCF_RO },
   7476     { TRTYf, 8, 0, SOCF_LE|SOCF_RO }
   7477 };
   7478 
   7479 #endif
   7480 #if defined(BCM_56370_A0)
   7481 soc_field_info_t soc_USBD_BDC_MFNUMr_fields[] = {
   7482     { MFCf, 14, 0, SOCF_LE },
   7483     { RESERVEDf, 17, 14, SOCF_LE|SOCF_RO|SOCF_RES },
   7484     { VLDf, 1, 31, 0 }
   7485 };
   7486 
   7487 #endif
   7488 #if defined(BCM_56370_A0)
   7489 soc_field_info_t soc_USBD_BDC_OSC0r_fields[] = {
   7490     { LENf, 24, 0, SOCF_LE|SOCF_RO },
   7491     { LMDf, 2, 24, SOCF_LE|SOCF_RO },
   7492     { RESERVEDf, 6, 26, SOCF_LE|SOCF_RO|SOCF_RES }
   7493 };
   7494 
   7495 #endif
   7496 #if defined(BCM_56370_A0)
   7497 soc_field_info_t soc_USBD_BDC_PHYSSPr_fields[] = {
   7498     { DRSf, 1, 11, SOCF_RO },
   7499     { GEARf, 2, 12, SOCF_LE|SOCF_RO },
   7500     { MAJf, 4, 28, SOCF_LE|SOCF_RO },
   7501     { MINf, 4, 24, SOCF_LE|SOCF_RO },
   7502     { NLSf, 2, 9, SOCF_LE|SOCF_RO },
   7503     { RESERVEDf, 3, 0, SOCF_LE|SOCF_RO|SOCF_RES },
   7504     { RLSf, 4, 20, SOCF_LE|SOCF_RO },
   7505     { SSIf, 3, 16, SOCF_LE|SOCF_RO },
   7506     { U2Of, 1, 3, SOCF_RO }
   7507 };
   7508 
   7509 #endif
   7510 #if defined(BCM_56370_A0)
   7511 soc_field_info_t soc_USBD_BDC_PHYU2Pr_fields[] = {
   7512     { L1Of, 1, 3, SOCF_RO },
   7513     { LPMf, 1, 4, SOCF_RO },
   7514     { MAJf, 4, 28, SOCF_LE|SOCF_RO },
   7515     { MINf, 4, 24, SOCF_LE|SOCF_RO },
   7516     { RESERVEDf, 3, 0, SOCF_LE|SOCF_RO|SOCF_RES },
   7517     { RLSf, 4, 20, SOCF_LE|SOCF_RO },
   7518     { U2If, 3, 16, SOCF_LE|SOCF_RO }
   7519 };
   7520 
   7521 #endif
   7522 #if defined(BCM_56370_A0)
   7523 soc_field_info_t soc_USBD_BDC_RBVMGNr_fields[] = {
   7524     { MGNf, 32, 0, SOCF_LE|SOCF_RO }
   7525 };
   7526 
   7527 #endif
   7528 #if defined(BCM_56370_A0)
   7529 soc_field_info_t soc_USBD_BDC_RBVPDTr_fields[] = {
   7530     { PDTf, 16, 0, SOCF_LE|SOCF_RO },
   7531     { VDRf, 16, 16, SOCF_LE|SOCF_RO }
   7532 };
   7533 
   7534 #endif
   7535 #if defined(BCM_56370_A0)
   7536 soc_field_info_t soc_USBD_BDC_SPBBAHr_fields[] = {
   7537     { BAHf, 32, 0, SOCF_LE }
   7538 };
   7539 
   7540 #endif
   7541 #if defined(BCM_56370_A0)
   7542 soc_field_info_t soc_USBD_BDC_SPBBALr_fields[] = {
   7543     { BALf, 30, 2, SOCF_LE },
   7544     { RESERVEDf, 2, 0, SOCF_LE|SOCF_RO|SOCF_RES }
   7545 };
   7546 
   7547 #endif
   7548 #if defined(BCM_56370_A0)
   7549 soc_field_info_t soc_USBD_BDC_SRRBAL0r_fields[] = {
   7550     { BALf, 28, 4, SOCF_LE },
   7551     { SIZf, 3, 0, SOCF_LE },
   7552     { SWSf, 1, 3, 0 }
   7553 };
   7554 
   7555 #endif
   7556 #if defined(BCM_56370_A0)
   7557 soc_field_info_t soc_USBD_BDC_SRRINT0r_fields[] = {
   7558     { DQPf, 8, 16, SOCF_LE },
   7559     { EQPf, 8, 24, SOCF_LE|SOCF_RO },
   7560     { IEf, 1, 1, 0 },
   7561     { IPf, 1, 0, 0 },
   7562     { ISRf, 1, 2, 0 },
   7563     { RESERVEDf, 11, 5, SOCF_LE|SOCF_RO|SOCF_RES },
   7564     { RSTf, 1, 3, 0 },
   7565     { RWSf, 1, 4, 0 }
   7566 };
   7567 
   7568 #endif
   7569 #if defined(BCM_56370_A0)
   7570 soc_field_info_t soc_USBD_BDC_USPPM2r_fields[] = {
   7571     { HIRDf, 4, 8, SOCF_LE|SOCF_RO },
   7572     { HIRDSf, 4, 4, SOCF_LE|SOCF_RO },
   7573     { HIRDTf, 4, 12, SOCF_LE },
   7574     { HLEf, 1, 16, 0 },
   7575     { L1Rf, 8, 20, SOCF_LE },
   7576     { L1Sf, 3, 0, SOCF_LE|SOCF_RO },
   7577     { PTCf, 4, 28, SOCF_LE },
   7578     { RESERVEDf, 1, 3, SOCF_RO|SOCF_RES }
   7579 };
   7580 
   7581 #endif
   7582 #if defined(BCM_56370_A0)
   7583 soc_field_info_t soc_USBD_BDC_USPPMSr_fields[] = {
   7584     { FLAf, 1, 16, 0 },
   7585     { RESERVEDf, 10, 19, SOCF_LE|SOCF_RO|SOCF_RES },
   7586     { U1Ef, 1, 30, 0 },
   7587     { U1Tf, 8, 0, SOCF_LE },
   7588     { U2Af, 1, 29, 0 },
   7589     { U2Ef, 1, 31, 0 },
   7590     { U2Tf, 8, 8, SOCF_LE },
   7591     { W1Sf, 1, 17, 0 },
   7592     { W2Sf, 1, 18, 0 }
   7593 };
   7594 
   7595 #endif
   7596 #if defined(BCM_56370_A0)
   7597 soc_field_info_t soc_USBD_BDC_USPSCr_fields[] = {
   7598     { CECf, 1, 28, 0 },
   7599     { PCCf, 1, 27, 0 },
   7600     { PCEf, 1, 29, 0 },
   7601     { PCSf, 1, 23, SOCF_RO },
   7602     { PRCf, 1, 30, 0 },
   7603     { PRSf, 1, 24, SOCF_RO },
   7604     { PSCf, 1, 26, 0 },
   7605     { PSPf, 3, 20, SOCF_LE|SOCF_RO },
   7606     { PSTf, 4, 0, SOCF_LE },
   7607     { RESERVEDf, 2, 5, SOCF_LE|SOCF_RO|SOCF_RES },
   7608     { SCNf, 1, 8, 0 },
   7609     { SDCf, 1, 7, 0 },
   7610     { SWSf, 1, 4, 0 },
   7611     { VBCf, 1, 31, 0 },
   7612     { VBSf, 1, 25, SOCF_RO }
   7613 };
   7614 
   7615 #endif
   7616 #if defined(BCM_56370_A0)
   7617 soc_field_info_t soc_USBD_BDC_USPTDSr_fields[] = {
   7618     { BECf, 1, 15, 0 },
   7619     { BEC0f, 8, 16, SOCF_LE|SOCF_RO },
   7620     { BEC1f, 8, 24, SOCF_LE|SOCF_RO },
   7621     { BTCf, 4, 0, SOCF_LE|SOCF_WO },
   7622     { BTSf, 1, 4, 0 },
   7623     { LMCf, 1, 13, 0 },
   7624     { LMDf, 2, 5, SOCF_LE },
   7625     { LMSf, 1, 7, 0 },
   7626     { RESERVEDf, 3, 10, SOCF_LE|SOCF_RO|SOCF_RES },
   7627     { SMCf, 1, 14, 0 },
   7628     { SMDf, 1, 8, 0 },
   7629     { SMSf, 1, 9, 0 }
   7630 };
   7631 
   7632 #endif
   7633 #if defined(BCM_56370_A0)
   7634 soc_field_info_t soc_USBD_BDC_XSFNTFr_fields[] = {
   7635     { EPNf, 5, 0, SOCF_LE|SOCF_WO },
   7636     { RESERVEDf, 11, 5, SOCF_LE|SOCF_RO|SOCF_RES },
   7637     { SIDf, 16, 16, SOCF_LE|SOCF_WO }
   7638 };
   7639 
   7640 #endif
   7641 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7642     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7643 soc_field_info_t soc_USBH_ASYNCLISTADDRr_fields[] = {
   7644     { LINK_POINTER_LOW_LPLf, 27, 5, SOCF_LE }
   7645 };
   7646 
   7647 #endif
   7648 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7649     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7650     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7651     defined(BCM_56260_B0)
   7652 soc_field_info_t soc_USBH_ASYNCLISTADDR_BCM53400_A0r_fields[] = {
   7653     { LINK_POINTER_LOW_LPLf, 27, 5, SOCF_LE }
   7654 };
   7655 
   7656 #endif
   7657 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7658     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7659 soc_field_info_t soc_USBH_CONFIGFLAGr_fields[] = {
   7660     { CONFIGURE_FLAG_CFf, 1, 0, 0 }
   7661 };
   7662 
   7663 #endif
   7664 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7665     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7666     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7667     defined(BCM_56260_B0)
   7668 soc_field_info_t soc_USBH_CONFIGFLAG_BCM53400_A0r_fields[] = {
   7669     { CONFIGURE_FLAG_CFf, 1, 0, 0 }
   7670 };
   7671 
   7672 #endif
   7673 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7674     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7675 soc_field_info_t soc_USBH_CTRLDSSEGMENTr_fields[] = {
   7676     { CTRLDSSEGMENTf, 32, 0, SOCF_LE }
   7677 };
   7678 
   7679 #endif
   7680 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7681     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7682     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7683     defined(BCM_56260_B0)
   7684 soc_field_info_t soc_USBH_CTRLDSSEGMENT_BCM53400_A0r_fields[] = {
   7685     { CTRLDSSEGMENTf, 32, 0, SOCF_LE }
   7686 };
   7687 
   7688 #endif
   7689 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7690     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7691     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7692     defined(BCM_56260_B0)
   7693 soc_field_info_t soc_USBH_EHCI_INCRX_STRAPr_fields[] = {
   7694     { SS_ENA_INCR16_If, 1, 0, 0 },
   7695     { SS_ENA_INCR4_If, 1, 2, 0 },
   7696     { SS_ENA_INCR8_If, 1, 1, 0 },
   7697     { SS_ENA_INCRX_ALIGNf, 1, 3, 0 }
   7698 };
   7699 
   7700 #endif
   7701 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7702     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7703     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7704     defined(BCM_56260_B0)
   7705 soc_field_info_t soc_USBH_EHCI_LPSMC_STATEr_fields[] = {
   7706     { LPSMC_STSf, 4, 0, SOCF_LE|SOCF_RO }
   7707 };
   7708 
   7709 #endif
   7710 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7711     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7712 soc_field_info_t soc_USBH_EHCI_STATUSr_fields[] = {
   7713     { USB_STATUSf, 6, 0, SOCF_LE|SOCF_RO }
   7714 };
   7715 
   7716 #endif
   7717 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7718     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7719     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7720     defined(BCM_56260_B0)
   7721 soc_field_info_t soc_USBH_EHCI_STATUS_BCM53400_A0r_fields[] = {
   7722     { USB_STATUSf, 6, 0, SOCF_LE|SOCF_RO }
   7723 };
   7724 
   7725 #endif
   7726 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7727     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7728     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7729     defined(BCM_56260_B0)
   7730 soc_field_info_t soc_USBH_EHCI_XFERr_fields[] = {
   7731     { EHCI_XRERf, 12, 0, SOCF_LE|SOCF_RO }
   7732 };
   7733 
   7734 #endif
   7735 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7736     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7737 soc_field_info_t soc_USBH_FRAME_LENADJr_fields[] = {
   7738     { FRAMELEN_ADJf, 6, 0, SOCF_LE }
   7739 };
   7740 
   7741 #endif
   7742 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7743     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7744     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7745     defined(BCM_56260_B0)
   7746 soc_field_info_t soc_USBH_FRAME_LENADJ_BCM53400_A0r_fields[] = {
   7747     { FRAMELEN_ADJf, 6, 0, SOCF_LE }
   7748 };
   7749 
   7750 #endif
   7751 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7752     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7753 soc_field_info_t soc_USBH_FRINDEXr_fields[] = {
   7754     { FRAME_INDEXf, 14, 0, SOCF_LE }
   7755 };
   7756 
   7757 #endif
   7758 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7759     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7760     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7761     defined(BCM_56260_B0)
   7762 soc_field_info_t soc_USBH_FRINDEX_BCM53400_A0r_fields[] = {
   7763     { FRAME_INDEXf, 14, 0, SOCF_LE }
   7764 };
   7765 
   7766 #endif
   7767 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7768     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7769 soc_field_info_t soc_USBH_GPIO_OEr_fields[] = {
   7770     { GPIO_OEf, 8, 0, SOCF_LE|SOCF_RO }
   7771 };
   7772 
   7773 #endif
   7774 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7775     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7776     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7777     defined(BCM_56260_B0)
   7778 soc_field_info_t soc_USBH_GPIO_OE_BCM53400_A0r_fields[] = {
   7779     { GPIO_OEf, 8, 0, SOCF_LE|SOCF_RO }
   7780 };
   7781 
   7782 #endif
   7783 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7784     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7785 soc_field_info_t soc_USBH_GPIO_SELr_fields[] = {
   7786     { GPIO_SELf, 32, 0, SOCF_LE }
   7787 };
   7788 
   7789 #endif
   7790 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7791     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7792     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7793     defined(BCM_56260_B0)
   7794 soc_field_info_t soc_USBH_GPIO_SEL_BCM53400_A0r_fields[] = {
   7795     { GPIO_SELf, 32, 0, SOCF_LE }
   7796 };
   7797 
   7798 #endif
   7799 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7800     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7801 soc_field_info_t soc_USBH_HCBULKCURRENTEDr_fields[] = {
   7802     { BCEDf, 28, 4, SOCF_LE }
   7803 };
   7804 
   7805 #endif
   7806 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7807     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7808     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7809     defined(BCM_56260_B0)
   7810 soc_field_info_t soc_USBH_HCBULKCURRENTED_BCM53400_A0r_fields[] = {
   7811     { BCEDf, 28, 4, SOCF_LE }
   7812 };
   7813 
   7814 #endif
   7815 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7816     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7817 soc_field_info_t soc_USBH_HCBULKHEADEDr_fields[] = {
   7818     { BHEDf, 28, 4, SOCF_LE }
   7819 };
   7820 
   7821 #endif
   7822 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7823     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7824     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7825     defined(BCM_56260_B0)
   7826 soc_field_info_t soc_USBH_HCBULKHEADED_BCM53400_A0r_fields[] = {
   7827     { BHEDf, 28, 4, SOCF_LE }
   7828 };
   7829 
   7830 #endif
   7831 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7832     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7833 soc_field_info_t soc_USBH_HCCAPBASEr_fields[] = {
   7834     { CAPLENGTHf, 8, 0, SOCF_LE|SOCF_RO },
   7835     { HCIVERSIONf, 16, 16, SOCF_LE|SOCF_RO }
   7836 };
   7837 
   7838 #endif
   7839 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7840     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7841     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7842     defined(BCM_56260_B0)
   7843 soc_field_info_t soc_USBH_HCCAPBASE_BCM53400_A0r_fields[] = {
   7844     { CAPLENGTHf, 8, 0, SOCF_LE|SOCF_RO },
   7845     { HCIVERSIONf, 16, 16, SOCF_LE|SOCF_RO }
   7846 };
   7847 
   7848 #endif
   7849 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7850     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7851 soc_field_info_t soc_USBH_HCCOMMANDSTATUSr_fields[] = {
   7852     { BLFf, 1, 2, 0 },
   7853     { CLFf, 1, 1, 0 },
   7854     { HCRf, 1, 0, 0 },
   7855     { OCRf, 1, 3, 0 },
   7856     { SOCf, 2, 16, SOCF_LE|SOCF_RO }
   7857 };
   7858 
   7859 #endif
   7860 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7861     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7862     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7863     defined(BCM_56260_B0)
   7864 soc_field_info_t soc_USBH_HCCOMMANDSTATUS_BCM53400_A0r_fields[] = {
   7865     { BLFf, 1, 2, 0 },
   7866     { CLFf, 1, 1, 0 },
   7867     { HCRf, 1, 0, 0 },
   7868     { OCRf, 1, 3, 0 },
   7869     { SOCf, 2, 16, SOCF_LE|SOCF_RO }
   7870 };
   7871 
   7872 #endif
   7873 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7874     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7875 soc_field_info_t soc_USBH_HCCONTOLCURRENTEDr_fields[] = {
   7876     { CCEDf, 28, 4, SOCF_LE }
   7877 };
   7878 
   7879 #endif
   7880 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7881     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7882     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7883     defined(BCM_56260_B0)
   7884 soc_field_info_t soc_USBH_HCCONTOLCURRENTED_BCM53400_A0r_fields[] = {
   7885     { CCEDf, 28, 4, SOCF_LE }
   7886 };
   7887 
   7888 #endif
   7889 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7890     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7891 soc_field_info_t soc_USBH_HCCONTROLr_fields[] = {
   7892     { BLEf, 1, 5, 0 },
   7893     { CBSRf, 2, 0, SOCF_LE },
   7894     { CLEf, 1, 4, 0 },
   7895     { HCFSf, 2, 6, SOCF_LE },
   7896     { IEf, 1, 3, 0 },
   7897     { IRf, 1, 8, 0 },
   7898     { PLEf, 1, 2, 0 },
   7899     { RWCf, 1, 9, 0 },
   7900     { RWEf, 1, 10, 0 }
   7901 };
   7902 
   7903 #endif
   7904 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7905     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7906 soc_field_info_t soc_USBH_HCCONTROLHEADEDr_fields[] = {
   7907     { CHEDf, 28, 4, SOCF_LE }
   7908 };
   7909 
   7910 #endif
   7911 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7912     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7913     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7914     defined(BCM_56260_B0)
   7915 soc_field_info_t soc_USBH_HCCONTROLHEADED_BCM53400_A0r_fields[] = {
   7916     { CHEDf, 28, 4, SOCF_LE }
   7917 };
   7918 
   7919 #endif
   7920 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7921     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7922     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7923     defined(BCM_56260_B0)
   7924 soc_field_info_t soc_USBH_HCCONTROL_BCM53400_A0r_fields[] = {
   7925     { BLEf, 1, 5, 0 },
   7926     { CBSRf, 2, 0, SOCF_LE },
   7927     { CLEf, 1, 4, 0 },
   7928     { HCFSf, 2, 6, SOCF_LE },
   7929     { IEf, 1, 3, 0 },
   7930     { IRf, 1, 8, 0 },
   7931     { PLEf, 1, 2, 0 },
   7932     { RWCf, 1, 9, 0 },
   7933     { RWEf, 1, 10, 0 }
   7934 };
   7935 
   7936 #endif
   7937 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7938     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7939 soc_field_info_t soc_USBH_HCCPARAMSr_fields[] = {
   7940     { ASYNCHRONOUS_SCHEDULE_PARK_CAPABILITYf, 1, 2, SOCF_RO },
   7941     { BIT_64_ADDRESSING_CAPABILITY1f, 1, 0, SOCF_RO },
   7942     { EHCI_EXTENDED_CAPABILITIES_POINTER_EECPf, 8, 8, SOCF_LE|SOCF_RO },
   7943     { ISOCHRONOUS_SCHEDULING_THRESHOLDf, 4, 4, SOCF_LE|SOCF_RO },
   7944     { PROGRAMMABLE_FRAME_LIST_FLAGf, 1, 1, SOCF_RO }
   7945 };
   7946 
   7947 #endif
   7948 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7949     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7950     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7951     defined(BCM_56260_B0)
   7952 soc_field_info_t soc_USBH_HCCPARAMS_BCM53400_A0r_fields[] = {
   7953     { ASYNCHRONOUS_SCHEDULE_PARK_CAPABILITYf, 1, 2, SOCF_RO },
   7954     { BIT_64_ADDRESSING_CAPABILITY1f, 1, 0, SOCF_RO },
   7955     { EHCI_EXTENDED_CAPABILITIES_POINTER_EECPf, 8, 8, SOCF_LE|SOCF_RO },
   7956     { ISOCHRONOUS_SCHEDULING_THRESHOLDf, 4, 4, SOCF_LE|SOCF_RO },
   7957     { PROGRAMMABLE_FRAME_LIST_FLAGf, 1, 1, SOCF_RO }
   7958 };
   7959 
   7960 #endif
   7961 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7962     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7963 soc_field_info_t soc_USBH_HCDONEHEADr_fields[] = {
   7964     { DHf, 28, 4, SOCF_LE|SOCF_RO }
   7965 };
   7966 
   7967 #endif
   7968 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7969     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7970     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7971     defined(BCM_56260_B0)
   7972 soc_field_info_t soc_USBH_HCDONEHEAD_BCM53400_A0r_fields[] = {
   7973     { DHf, 28, 4, SOCF_LE|SOCF_RO }
   7974 };
   7975 
   7976 #endif
   7977 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7978     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7979 soc_field_info_t soc_USBH_HCFMINTERVALr_fields[] = {
   7980     { FIf, 14, 0, SOCF_LE },
   7981     { FITf, 1, 31, 0 },
   7982     { FSMPSf, 15, 16, SOCF_LE }
   7983 };
   7984 
   7985 #endif
   7986 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7987     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7988     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7989     defined(BCM_56260_B0)
   7990 soc_field_info_t soc_USBH_HCFMINTERVAL_BCM53400_A0r_fields[] = {
   7991     { FIf, 14, 0, SOCF_LE },
   7992     { FITf, 1, 31, 0 },
   7993     { FSMPSf, 15, 16, SOCF_LE }
   7994 };
   7995 
   7996 #endif
   7997 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   7998     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   7999 soc_field_info_t soc_USBH_HCFMNUMBERr_fields[] = {
   8000     { FNf, 16, 0, SOCF_LE }
   8001 };
   8002 
   8003 #endif
   8004 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8005     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8006     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8007     defined(BCM_56260_B0)
   8008 soc_field_info_t soc_USBH_HCFMNUMBER_BCM53400_A0r_fields[] = {
   8009     { FNf, 16, 0, SOCF_LE }
   8010 };
   8011 
   8012 #endif
   8013 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8014     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8015 soc_field_info_t soc_USBH_HCFMREMAININGr_fields[] = {
   8016     { FRf, 14, 0, SOCF_LE },
   8017     { FRTf, 1, 31, 0 }
   8018 };
   8019 
   8020 #endif
   8021 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8022     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8023     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8024     defined(BCM_56260_B0)
   8025 soc_field_info_t soc_USBH_HCFMREMAINING_BCM53400_A0r_fields[] = {
   8026     { FRf, 14, 0, SOCF_LE },
   8027     { FRTf, 1, 31, 0 }
   8028 };
   8029 
   8030 #endif
   8031 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8032     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8033 soc_field_info_t soc_USBH_HCHCCAr_fields[] = {
   8034     { HCCAf, 24, 8, SOCF_LE }
   8035 };
   8036 
   8037 #endif
   8038 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8039     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8040     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8041     defined(BCM_56260_B0)
   8042 soc_field_info_t soc_USBH_HCHCCA_BCM53400_A0r_fields[] = {
   8043     { HCCAf, 24, 8, SOCF_LE }
   8044 };
   8045 
   8046 #endif
   8047 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8048     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8049 soc_field_info_t soc_USBH_HCINTERRUPTDISABLEr_fields[] = {
   8050     { FNOf, 1, 5, 0 },
   8051     { MIEf, 1, 31, 0 },
   8052     { OCf, 1, 30, 0 },
   8053     { RDf, 1, 3, 0 },
   8054     { RHSCf, 1, 6, 0 },
   8055     { SFf, 1, 2, 0 },
   8056     { SOf, 1, 0, 0 },
   8057     { UEf, 1, 4, 0 },
   8058     { WDHf, 1, 1, 0 }
   8059 };
   8060 
   8061 #endif
   8062 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8063     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8064     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8065     defined(BCM_56260_B0)
   8066 soc_field_info_t soc_USBH_HCINTERRUPTDISABLE_BCM53400_A0r_fields[] = {
   8067     { FNOf, 1, 5, 0 },
   8068     { MIEf, 1, 31, 0 },
   8069     { OCf, 1, 30, 0 },
   8070     { RDf, 1, 3, 0 },
   8071     { RHSCf, 1, 6, 0 },
   8072     { SFf, 1, 2, 0 },
   8073     { SOf, 1, 0, 0 },
   8074     { UEf, 1, 4, 0 },
   8075     { WDHf, 1, 1, 0 }
   8076 };
   8077 
   8078 #endif
   8079 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8080     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8081 soc_field_info_t soc_USBH_HCINTERRUPTSTATUSr_fields[] = {
   8082     { FNOf, 1, 5, 0 },
   8083     { OCf, 1, 30, 0 },
   8084     { RDf, 1, 3, 0 },
   8085     { RHSCf, 1, 6, 0 },
   8086     { SFf, 1, 2, 0 },
   8087     { SOf, 1, 0, 0 },
   8088     { UEf, 1, 4, 0 },
   8089     { WDHf, 1, 1, 0 }
   8090 };
   8091 
   8092 #endif
   8093 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8094     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8095     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8096     defined(BCM_56260_B0)
   8097 soc_field_info_t soc_USBH_HCINTERRUPTSTATUS_BCM53400_A0r_fields[] = {
   8098     { FNOf, 1, 5, 0 },
   8099     { OCf, 1, 30, 0 },
   8100     { RDf, 1, 3, 0 },
   8101     { RHSCf, 1, 6, 0 },
   8102     { SFf, 1, 2, 0 },
   8103     { SOf, 1, 0, 0 },
   8104     { UEf, 1, 4, 0 },
   8105     { WDHf, 1, 1, 0 }
   8106 };
   8107 
   8108 #endif
   8109 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8110     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8111 soc_field_info_t soc_USBH_HCLSTHRESHOLDr_fields[] = {
   8112     { LSTf, 12, 0, SOCF_LE }
   8113 };
   8114 
   8115 #endif
   8116 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8117     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8118     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8119     defined(BCM_56260_B0)
   8120 soc_field_info_t soc_USBH_HCLSTHRESHOLD_BCM53400_A0r_fields[] = {
   8121     { LSTf, 12, 0, SOCF_LE }
   8122 };
   8123 
   8124 #endif
   8125 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8126     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8127 soc_field_info_t soc_USBH_HCPERIODCURRENTEDr_fields[] = {
   8128     { PCEDf, 28, 4, SOCF_LE|SOCF_RO }
   8129 };
   8130 
   8131 #endif
   8132 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8133     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8134     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8135     defined(BCM_56260_B0)
   8136 soc_field_info_t soc_USBH_HCPERIODCURRENTED_BCM53400_A0r_fields[] = {
   8137     { PCEDf, 28, 4, SOCF_LE|SOCF_RO }
   8138 };
   8139 
   8140 #endif
   8141 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8142     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8143 soc_field_info_t soc_USBH_HCPERIODICSTARTr_fields[] = {
   8144     { PSf, 14, 0, SOCF_LE }
   8145 };
   8146 
   8147 #endif
   8148 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8149     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8150     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8151     defined(BCM_56260_B0)
   8152 soc_field_info_t soc_USBH_HCPERIODICSTART_BCM53400_A0r_fields[] = {
   8153     { PSf, 14, 0, SOCF_LE }
   8154 };
   8155 
   8156 #endif
   8157 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8158     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8159 soc_field_info_t soc_USBH_HCREVISIONr_fields[] = {
   8160     { REVf, 8, 0, SOCF_LE|SOCF_RO }
   8161 };
   8162 
   8163 #endif
   8164 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8165     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8166     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8167     defined(BCM_56260_B0)
   8168 soc_field_info_t soc_USBH_HCREVISION_BCM53400_A0r_fields[] = {
   8169     { REVf, 8, 0, SOCF_LE|SOCF_RO }
   8170 };
   8171 
   8172 #endif
   8173 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8174     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8175 soc_field_info_t soc_USBH_HCRHDESCRIPTORAr_fields[] = {
   8176     { DTf, 1, 10, SOCF_RO },
   8177     { NDPf, 8, 0, SOCF_LE|SOCF_RO },
   8178     { NOCPf, 1, 12, 0 },
   8179     { NPSf, 1, 9, 0 },
   8180     { OCPMf, 1, 11, 0 },
   8181     { POTPGTf, 8, 24, SOCF_LE },
   8182     { PSMf, 1, 8, 0 }
   8183 };
   8184 
   8185 #endif
   8186 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8187     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8188     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8189     defined(BCM_56260_B0)
   8190 soc_field_info_t soc_USBH_HCRHDESCRIPTORA_BCM53400_A0r_fields[] = {
   8191     { DTf, 1, 10, SOCF_RO },
   8192     { NDPf, 8, 0, SOCF_LE|SOCF_RO },
   8193     { NOCPf, 1, 12, 0 },
   8194     { NPSf, 1, 9, 0 },
   8195     { OCPMf, 1, 11, 0 },
   8196     { POTPGTf, 8, 24, SOCF_LE },
   8197     { PSMf, 1, 8, 0 }
   8198 };
   8199 
   8200 #endif
   8201 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8202     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8203 soc_field_info_t soc_USBH_HCRHDESCRIPTORBr_fields[] = {
   8204     { DRf, 2, 1, SOCF_LE },
   8205     { PPCMf, 2, 17, SOCF_LE }
   8206 };
   8207 
   8208 #endif
   8209 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8210     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8211     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8212     defined(BCM_56260_B0)
   8213 soc_field_info_t soc_USBH_HCRHDESCRIPTORB_BCM53400_A0r_fields[] = {
   8214     { DRf, 2, 1, SOCF_LE },
   8215     { PPCMf, 2, 17, SOCF_LE }
   8216 };
   8217 
   8218 #endif
   8219 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8220     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8221 soc_field_info_t soc_USBH_HCRHPORT00r_fields[] = {
   8222     { CCSf, 1, 0, 0 },
   8223     { CSCf, 1, 16, 0 },
   8224     { LSDAf, 1, 9, 0 },
   8225     { OCICf, 1, 19, 0 },
   8226     { PESf, 1, 1, 0 },
   8227     { PESCf, 1, 17, 0 },
   8228     { POCIf, 1, 3, 0 },
   8229     { PPSf, 1, 8, 0 },
   8230     { PRSf, 1, 4, 0 },
   8231     { PRSCf, 1, 20, 0 },
   8232     { PSSf, 1, 2, 0 },
   8233     { PSSCf, 1, 18, 0 }
   8234 };
   8235 
   8236 #endif
   8237 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8238     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8239     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8240     defined(BCM_56260_B0)
   8241 soc_field_info_t soc_USBH_HCRHPORT00_BCM53400_A0r_fields[] = {
   8242     { CCSf, 1, 0, 0 },
   8243     { CSCf, 1, 16, 0 },
   8244     { LSDAf, 1, 9, 0 },
   8245     { OCICf, 1, 19, 0 },
   8246     { PESf, 1, 1, 0 },
   8247     { PESCf, 1, 17, 0 },
   8248     { POCIf, 1, 3, 0 },
   8249     { PPSf, 1, 8, 0 },
   8250     { PRSf, 1, 4, 0 },
   8251     { PRSCf, 1, 20, 0 },
   8252     { PSSf, 1, 2, 0 },
   8253     { PSSCf, 1, 18, 0 }
   8254 };
   8255 
   8256 #endif
   8257 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8258     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8259 soc_field_info_t soc_USBH_HCRHSTATUSr_fields[] = {
   8260     { CRWEf, 1, 31, 0 },
   8261     { DRWEf, 1, 15, 0 },
   8262     { LPSf, 1, 0, 0 },
   8263     { LPSCf, 1, 16, 0 },
   8264     { OCIf, 1, 1, SOCF_RO },
   8265     { OCICf, 1, 17, 0 }
   8266 };
   8267 
   8268 #endif
   8269 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8270     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8271     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8272     defined(BCM_56260_B0)
   8273 soc_field_info_t soc_USBH_HCRHSTATUS_BCM53400_A0r_fields[] = {
   8274     { CRWEf, 1, 31, 0 },
   8275     { DRWEf, 1, 15, 0 },
   8276     { LPSf, 1, 0, 0 },
   8277     { LPSCf, 1, 16, 0 },
   8278     { OCIf, 1, 1, SOCF_RO },
   8279     { OCICf, 1, 17, 0 }
   8280 };
   8281 
   8282 #endif
   8283 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8284     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8285 soc_field_info_t soc_USBH_HCSPARAMSr_fields[] = {
   8286     { DPNf, 4, 20, SOCF_LE|SOCF_RO },
   8287     { N_CCf, 4, 12, SOCF_LE|SOCF_RO },
   8288     { N_PCCf, 4, 8, SOCF_LE|SOCF_RO },
   8289     { N_PORTSf, 4, 0, SOCF_LE|SOCF_RO },
   8290     { PPCf, 1, 4, SOCF_RO },
   8291     { PRRf, 1, 7, SOCF_RO },
   8292     { P_INDICATORf, 1, 16, SOCF_RO }
   8293 };
   8294 
   8295 #endif
   8296 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8297     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8298     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8299     defined(BCM_56260_B0)
   8300 soc_field_info_t soc_USBH_HCSPARAMS_BCM53400_A0r_fields[] = {
   8301     { DPNf, 4, 20, SOCF_LE|SOCF_RO },
   8302     { N_CCf, 4, 12, SOCF_LE|SOCF_RO },
   8303     { N_PCCf, 4, 8, SOCF_LE|SOCF_RO },
   8304     { N_PORTSf, 4, 0, SOCF_LE|SOCF_RO },
   8305     { PPCf, 1, 4, SOCF_RO },
   8306     { PRRf, 1, 7, SOCF_RO },
   8307     { P_INDICATORf, 1, 16, SOCF_RO }
   8308 };
   8309 
   8310 #endif
   8311 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8312 soc_field_info_t soc_USBH_INSNREG00r_fields[] = {
   8313     { MICROFRAME_BASE_VALUEf, 14, 0, SOCF_LE }
   8314 };
   8315 
   8316 #endif
   8317 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8318 soc_field_info_t soc_USBH_INSNREG01r_fields[] = {
   8319     { IN_THRESHOLDf, 16, 0, SOCF_LE },
   8320     { OUT_THRESHOLDf, 16, 16, SOCF_LE }
   8321 };
   8322 
   8323 #endif
   8324 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8325 soc_field_info_t soc_USBH_INSNREG02r_fields[] = {
   8326     { PACKET_BUFFER_DEPTHf, 12, 0, SOCF_LE }
   8327 };
   8328 
   8329 #endif
   8330 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8331 soc_field_info_t soc_USBH_INSNREG03r_fields[] = {
   8332     { BRK_MEM_TXFERf, 1, 0, 0 },
   8333     { PERI_FRM_LIST_FETCHf, 1, 9, 0 },
   8334     { TIME_AVAILABLE_OFFSETf, 8, 1, SOCF_LE },
   8335     { TX_TX_TURNAROUND_ADDONf, 3, 10, SOCF_LE }
   8336 };
   8337 
   8338 #endif
   8339 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8340 soc_field_info_t soc_USBH_INSNREG04r_fields[] = {
   8341     { EN_AUTO_FEATUREf, 1, 5, 0 },
   8342     { EN_RW_HCCPARAMSf, 1, 0, 0 },
   8343     { EN_RW_HCCPARAMS_PARTf, 1, 1, 0 },
   8344     { NAK_RELOAD_FIX_ENf, 1, 4, 0 },
   8345     { REDUCE_PORT_ENUM_TIMEf, 1, 2, 0 },
   8346     { RESERVEDf, 1, 3, SOCF_RO|SOCF_RES }
   8347 };
   8348 
   8349 #endif
   8350 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8351 soc_field_info_t soc_USBH_INSNREG05r_fields[] = {
   8352     { RESERVEDf, 14, 18, SOCF_LE|SOCF_RO|SOCF_RES },
   8353     { VBUSYf, 1, 17, SOCF_RO },
   8354     { VCTRLf, 4, 8, SOCF_LE },
   8355     { VCTRLLOADMf, 1, 12, 0 },
   8356     { VPORTf, 4, 13, SOCF_LE },
   8357     { VSTSf, 8, 0, SOCF_LE|SOCF_RO }
   8358 };
   8359 
   8360 #endif
   8361 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8362 soc_field_info_t soc_USBH_INSNREG06r_fields[] = {
   8363     { AHB_ERR_CAPTUREf, 1, 31, 0 },
   8364     { HBURSTf, 3, 9, SOCF_LE|SOCF_RO },
   8365     { NO_COMPL_BEATSf, 4, 0, SOCF_LE|SOCF_RO },
   8366     { NO_EXP_BEATSf, 5, 4, SOCF_LE|SOCF_RO },
   8367     { RESERVEDf, 19, 12, SOCF_LE|SOCF_RO|SOCF_RES }
   8368 };
   8369 
   8370 #endif
   8371 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8372 soc_field_info_t soc_USBH_INSNREG07r_fields[] = {
   8373     { AHB_ERR_ADDRf, 32, 0, SOCF_LE|SOCF_RO }
   8374 };
   8375 
   8376 #endif
   8377 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8378 soc_field_info_t soc_USBH_INSNREG08r_fields[] = {
   8379     { HSIC_ENf, 32, 0, SOCF_LE }
   8380 };
   8381 
   8382 #endif
   8383 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8384     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8385     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8386     defined(BCM_56260_B0)
   8387 soc_field_info_t soc_USBH_INSNREG00_BCM53400_A0r_fields[] = {
   8388     { MICROFRAME_BASE_VALUEf, 14, 0, SOCF_LE }
   8389 };
   8390 
   8391 #endif
   8392 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8393     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8394     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8395     defined(BCM_56260_B0)
   8396 soc_field_info_t soc_USBH_INSNREG01_BCM53400_A0r_fields[] = {
   8397     { IN_THRESHOLDf, 16, 0, SOCF_LE },
   8398     { OUT_THRESHOLDf, 16, 16, SOCF_LE }
   8399 };
   8400 
   8401 #endif
   8402 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8403     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8404     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8405     defined(BCM_56260_B0)
   8406 soc_field_info_t soc_USBH_INSNREG02_BCM53400_A0r_fields[] = {
   8407     { PACKET_BUFFER_DEPTHf, 12, 0, SOCF_LE }
   8408 };
   8409 
   8410 #endif
   8411 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8412     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8413     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8414     defined(BCM_56260_B0)
   8415 soc_field_info_t soc_USBH_INSNREG03_BCM53400_A0r_fields[] = {
   8416     { BRK_MEM_TXFERf, 1, 0, 0 },
   8417     { EN_256_CLK_CHKf, 1, 14, 0 },
   8418     { EN_L1_SLEEP_ULPIf, 1, 15, 0 },
   8419     { IGN_LINEST_TESTSE0_NAKf, 1, 13, 0 },
   8420     { PERI_FRM_LIST_FETCHf, 1, 9, 0 },
   8421     { TIME_AVAILABLE_OFFSETf, 8, 1, SOCF_LE },
   8422     { TX_TX_TURNAROUND_ADDONf, 3, 10, SOCF_LE }
   8423 };
   8424 
   8425 #endif
   8426 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8427     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8428     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8429     defined(BCM_56260_B0)
   8430 soc_field_info_t soc_USBH_INSNREG04_BCM53400_A0r_fields[] = {
   8431     { DEBUGf, 3, 6, SOCF_LE },
   8432     { EN_AUTO_FEATUREf, 1, 5, 0 },
   8433     { EN_RW_HCCPARAMSf, 1, 0, 0 },
   8434     { EN_RW_HCCPARAMS_PARTf, 1, 1, 0 },
   8435     { NAK_RELOAD_FIX_ENf, 1, 4, 0 },
   8436     { REDUCE_PORT_ENUM_TIMEf, 1, 2, 0 },
   8437     { RESERVEDf, 1, 3, SOCF_RO|SOCF_RES }
   8438 };
   8439 
   8440 #endif
   8441 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8442     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8443     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8444     defined(BCM_56260_B0)
   8445 soc_field_info_t soc_USBH_INSNREG05_BCM53400_A0r_fields[] = {
   8446     { RESERVEDf, 14, 18, SOCF_LE|SOCF_RO|SOCF_RES },
   8447     { VBUSYf, 1, 17, SOCF_RO },
   8448     { VCTRLf, 4, 8, SOCF_LE },
   8449     { VCTRLLOADMf, 1, 12, 0 },
   8450     { VPORTf, 4, 13, SOCF_LE },
   8451     { VSTSf, 8, 0, SOCF_LE|SOCF_RO }
   8452 };
   8453 
   8454 #endif
   8455 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8456     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8457     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8458     defined(BCM_56260_B0)
   8459 soc_field_info_t soc_USBH_INSNREG06_BCM53400_A0r_fields[] = {
   8460     { AHB_ERR_CAPTUREf, 1, 31, 0 },
   8461     { HBURSTf, 3, 9, SOCF_LE|SOCF_RO },
   8462     { NO_COMPL_BEATSf, 4, 0, SOCF_LE|SOCF_RO },
   8463     { NO_EXP_BEATSf, 5, 4, SOCF_LE|SOCF_RO },
   8464     { RESERVEDf, 19, 12, SOCF_LE|SOCF_RO|SOCF_RES }
   8465 };
   8466 
   8467 #endif
   8468 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8469     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8470     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8471     defined(BCM_56260_B0)
   8472 soc_field_info_t soc_USBH_INSNREG07_BCM53400_A0r_fields[] = {
   8473     { AHB_ERR_ADDRf, 32, 0, SOCF_LE|SOCF_RO }
   8474 };
   8475 
   8476 #endif
   8477 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8478     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8479     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8480     defined(BCM_56260_B0)
   8481 soc_field_info_t soc_USBH_INSNREG08_BCM53400_A0r_fields[] = {
   8482     { HSIC_ENf, 32, 0, SOCF_LE }
   8483 };
   8484 
   8485 #endif
   8486 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8487     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8488     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8489     defined(BCM_56260_B0)
   8490 soc_field_info_t soc_USBH_INTR_CONTROLr_fields[] = {
   8491     { OHCI_RMTWKP_ENf, 1, 0, 0 },
   8492     { OHCI_SMI_ENf, 1, 1, 0 }
   8493 };
   8494 
   8495 #endif
   8496 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8497     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8498 soc_field_info_t soc_USBH_MDIO_CTRLr_fields[] = {
   8499     { MDIO_IDf, 5, 1, SOCF_LE },
   8500     { MDIO_MEM_SELf, 1, 0, 0 },
   8501     { MDIO_RD_STARTf, 1, 7, 0 },
   8502     { MDIO_REG_ADDRf, 5, 8, SOCF_LE },
   8503     { MDIO_WR_DATAf, 16, 13, SOCF_LE },
   8504     { MDIO_WR_STARTf, 1, 6, 0 }
   8505 };
   8506 
   8507 #endif
   8508 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8509     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8510 soc_field_info_t soc_USBH_MDIO_RDDATr_fields[] = {
   8511     { MDIOTOREGf, 16, 0, SOCF_LE|SOCF_RO },
   8512     { MDIO_RDATA_DONEf, 1, 31, SOCF_RO }
   8513 };
   8514 
   8515 #endif
   8516 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8517     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8518     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8519     defined(BCM_56260_B0)
   8520 soc_field_info_t soc_USBH_OHCI_CCS_STSr_fields[] = {
   8521     { SS_POWER_STATEf, 3, 0, SOCF_LE|SOCF_RO }
   8522 };
   8523 
   8524 #endif
   8525 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8526     defined(BCM_53570_A0) || defined(BCM_56160_A0) || \
   8527     defined(BCM_56260_A0) || defined(BCM_56260_B0)
   8528 soc_field_info_t soc_USBH_OHCI_EHCI_STRAPr_fields[] = {
   8529     { OHCI_APP_PORT_OVRCUR_POLARITYf, 1, 11, 0 },
   8530     { OHCI_CNT_SELf, 1, 10, 0 },
   8531     { SS_AUTOPPD_ON_OVERCUR_ENf, 1, 7, 0 },
   8532     { SS_NEXT_POWER_STATEf, 2, 2, SOCF_LE },
   8533     { SS_NXT_POWER_STATE_VALIDf, 1, 5, 0 },
   8534     { SS_POWER_STATEf, 2, 0, SOCF_LE },
   8535     { SS_POWER_STATE_VALIDf, 1, 4, 0 },
   8536     { SS_RESUME_UTMI_PLS_DISf, 1, 9, 0 },
   8537     { SS_SIMULATION_MODEf, 1, 6, 0 },
   8538     { SS_UTMI_BACKWARD_ENf, 1, 8, 0 }
   8539 };
   8540 
   8541 #endif
   8542 #if defined(BCM_53570_B0)
   8543 soc_field_info_t soc_USBH_OHCI_EHCI_STRAP_BCM53570_B0r_fields[] = {
   8544     { OHCI_APP_PORT_OVRCUR_POLARITYf, 1, 11, 0 },
   8545     { OHCI_CNT_SELf, 1, 10, 0 },
   8546     { OHCI_RCTL_KALIVE_SE0_SELf, 2, 12, SOCF_LE },
   8547     { SS_AUTOPPD_ON_OVERCUR_ENf, 1, 7, 0 },
   8548     { SS_NEXT_POWER_STATEf, 2, 2, SOCF_LE },
   8549     { SS_NXT_POWER_STATE_VALIDf, 1, 5, 0 },
   8550     { SS_POWER_STATEf, 2, 0, SOCF_LE },
   8551     { SS_POWER_STATE_VALIDf, 1, 4, 0 },
   8552     { SS_RESUME_UTMI_PLS_DISf, 1, 9, 0 },
   8553     { SS_SIMULATION_MODEf, 1, 6, 0 },
   8554     { SS_UTMI_BACKWARD_ENf, 1, 8, 0 }
   8555 };
   8556 
   8557 #endif
   8558 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8559     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8560     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8561     defined(BCM_56260_B0)
   8562 soc_field_info_t soc_USBH_OHCI_PWR_STSr_fields[] = {
   8563     { OHCI_PWR_STSf, 3, 0, SOCF_LE|SOCF_RO }
   8564 };
   8565 
   8566 #endif
   8567 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8568     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8569 soc_field_info_t soc_USBH_PERIODICLISTBASEr_fields[] = {
   8570     { BASE_ADDRESS_LOWf, 20, 12, SOCF_LE }
   8571 };
   8572 
   8573 #endif
   8574 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8575     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8576     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8577     defined(BCM_56260_B0)
   8578 soc_field_info_t soc_USBH_PERIODICLISTBASE_BCM53400_A0r_fields[] = {
   8579     { BASE_ADDRESS_LOWf, 20, 12, SOCF_LE }
   8580 };
   8581 
   8582 #endif
   8583 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8584     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8585 soc_field_info_t soc_USBH_PHY_CTRL_P0r_fields[] = {
   8586     { CORE_RESETf, 1, 8, 0 },
   8587     { PHY_HARD_RESETf, 1, 9, 0 },
   8588     { PHY_PLL_POWER_DOWNf, 2, 0, SOCF_LE },
   8589     { PHY_SOFT_RESETf, 2, 6, SOCF_LE },
   8590     { PHY_TEST_PORT_POWER_DOWNf, 2, 4, SOCF_LE },
   8591     { PHY_TEST_PORT_UTMI_POWER_DOWNf, 2, 2, SOCF_LE }
   8592 };
   8593 
   8594 #endif
   8595 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8596     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8597     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8598     defined(BCM_56260_B0)
   8599 soc_field_info_t soc_USBH_PHY_CTRL_P0_BCM53400_A0r_fields[] = {
   8600     { CORE_RESETf, 1, 8, 0 },
   8601     { PHY_HARD_RESETf, 1, 9, 0 },
   8602     { PHY_PLL_POWER_DOWNf, 2, 0, SOCF_LE },
   8603     { PHY_SOFT_RESETf, 2, 6, SOCF_LE },
   8604     { PHY_TEST_PORT_POWER_DOWNf, 2, 4, SOCF_LE },
   8605     { PHY_TEST_PORT_UTMI_POWER_DOWNf, 2, 2, SOCF_LE }
   8606 };
   8607 
   8608 #endif
   8609 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8610     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8611 soc_field_info_t soc_USBH_PORTSC_0r_fields[] = {
   8612     { CONNECT_STATUS_CHANGEf, 1, 1, 0 },
   8613     { CURRENT_CONNECT_STATUSf, 1, 0, SOCF_RO },
   8614     { FORCE_PORT_RESUMEf, 1, 6, 0 },
   8615     { LINE_STATUSf, 2, 10, SOCF_LE|SOCF_RO },
   8616     { OVER_CURRENT_ACTIVEf, 1, 4, SOCF_RO },
   8617     { OVER_CURRENT_CHANGEf, 1, 5, 0 },
   8618     { PORT_ENABLED_DISABLEDf, 1, 2, 0 },
   8619     { PORT_ENABLE_DISABLE_CHANGEf, 1, 3, 0 },
   8620     { PORT_INDICATOR_CONTROLf, 2, 14, SOCF_LE },
   8621     { PORT_OWNERf, 1, 13, 0 },
   8622     { PORT_POWER_PPf, 1, 12, 0 },
   8623     { PORT_RESETf, 1, 8, 0 },
   8624     { PORT_TEST_CONTROLf, 4, 16, SOCF_LE },
   8625     { SUSPENDf, 1, 7, 0 },
   8626     { WAKE_ON_CONNECT_ENABLE_WKCNNT_Ef, 1, 20, 0 },
   8627     { WAKE_ON_DISCONNECT_ENABLE_WKDSCNNT_Ef, 1, 21, 0 },
   8628     { WAKE_ON_OVER_CURRENT_ENABLE_WKOC_Ef, 1, 22, 0 }
   8629 };
   8630 
   8631 #endif
   8632 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8633     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8634     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8635     defined(BCM_56260_B0)
   8636 soc_field_info_t soc_USBH_PORTSC_0_BCM53400_A0r_fields[] = {
   8637     { CONNECT_STATUS_CHANGEf, 1, 1, 0 },
   8638     { CURRENT_CONNECT_STATUSf, 1, 0, SOCF_RO },
   8639     { FORCE_PORT_RESUMEf, 1, 6, 0 },
   8640     { LINE_STATUSf, 2, 10, SOCF_LE|SOCF_RO },
   8641     { OVER_CURRENT_ACTIVEf, 1, 4, SOCF_RO },
   8642     { OVER_CURRENT_CHANGEf, 1, 5, 0 },
   8643     { PORT_ENABLED_DISABLEDf, 1, 2, 0 },
   8644     { PORT_ENABLE_DISABLE_CHANGEf, 1, 3, 0 },
   8645     { PORT_INDICATOR_CONTROLf, 2, 14, SOCF_LE },
   8646     { PORT_OWNERf, 1, 13, 0 },
   8647     { PORT_POWER_PPf, 1, 12, 0 },
   8648     { PORT_RESETf, 1, 8, 0 },
   8649     { PORT_TEST_CONTROLf, 4, 16, SOCF_LE },
   8650     { SUSPENDf, 1, 7, 0 },
   8651     { WAKE_ON_CONNECT_ENABLE_WKCNNT_Ef, 1, 20, 0 },
   8652     { WAKE_ON_DISCONNECT_ENABLE_WKDSCNNT_Ef, 1, 21, 0 },
   8653     { WAKE_ON_OVER_CURRENT_ENABLE_WKOC_Ef, 1, 22, 0 }
   8654 };
   8655 
   8656 #endif
   8657 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8658     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8659 soc_field_info_t soc_USBH_SB_ADDRHIr_fields[] = {
   8660     { SBADDRHIf, 32, 0, SOCF_LE }
   8661 };
   8662 
   8663 #endif
   8664 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8665     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8666 soc_field_info_t soc_USBH_SHIM_CTRLr_fields[] = {
   8667     { OVERCURRENT_POLARITYf, 1, 10, 0 },
   8668     { PORT_POWER_POLARITYf, 1, 11, 0 },
   8669     { PREFETCH_BURST_SIZEf, 4, 0, SOCF_LE },
   8670     { SHIM_ERROR_INTERRUPT_ENABLEf, 1, 9, 0 },
   8671     { TIMEOUT_COUNTER_ENABLEf, 1, 8, 0 },
   8672     { WRITE_BURST_SIZEf, 4, 4, SOCF_LE }
   8673 };
   8674 
   8675 #endif
   8676 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8677     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8678     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8679     defined(BCM_56260_B0)
   8680 soc_field_info_t soc_USBH_SHIM_CTRL_BCM53400_A0r_fields[] = {
   8681     { OVERCURRENT_POLARITYf, 1, 10, 0 },
   8682     { PORT_POWER_POLARITYf, 1, 11, 0 },
   8683     { PREFETCH_BURST_SIZEf, 4, 0, SOCF_LE },
   8684     { SHIM_ERROR_INTERRUPT_ENABLEf, 1, 9, 0 },
   8685     { TIMEOUT_COUNTER_ENABLEf, 1, 8, 0 },
   8686     { WRITE_BURST_SIZEf, 4, 4, SOCF_LE }
   8687 };
   8688 
   8689 #endif
   8690 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8691     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8692 soc_field_info_t soc_USBH_SHIM_MASTER_STATUSr_fields[] = {
   8693     { MASTER_STATEf, 4, 3, SOCF_LE|SOCF_RO },
   8694     { RESERVEDf, 1, 2, SOCF_RES },
   8695     { RESP_ERRORf, 1, 0, 0 }
   8696 };
   8697 
   8698 #endif
   8699 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8700     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8701     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8702     defined(BCM_56260_B0)
   8703 soc_field_info_t soc_USBH_SHIM_MASTER_STATUS_BCM53400_A0r_fields[] = {
   8704     { MASTER_STATEf, 4, 3, SOCF_LE|SOCF_RO },
   8705     { RESERVEDf, 1, 2, SOCF_RES },
   8706     { RESP_ERRORf, 1, 0, 0 }
   8707 };
   8708 
   8709 #endif
   8710 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8711     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8712 soc_field_info_t soc_USBH_SHIM_SLAVE_STATUSr_fields[] = {
   8713     { EHCI_APB_ERRf, 1, 0, 0 },
   8714     { OHCI_APB_ERRf, 1, 1, 0 },
   8715     { SLAVE_STATEf, 4, 3, SOCF_LE|SOCF_RO },
   8716     { TIMEOUTf, 1, 2, 0 }
   8717 };
   8718 
   8719 #endif
   8720 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8721     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8722     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8723     defined(BCM_56260_B0)
   8724 soc_field_info_t soc_USBH_SHIM_SLAVE_STATUS_BCM53400_A0r_fields[] = {
   8725     { EHCI_APB_ERRf, 1, 0, 0 },
   8726     { OHCI_APB_ERRf, 1, 1, 0 },
   8727     { SLAVE_STATEf, 4, 3, SOCF_LE|SOCF_RO },
   8728     { TIMEOUTf, 1, 2, 0 }
   8729 };
   8730 
   8731 #endif
   8732 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8733     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8734 soc_field_info_t soc_USBH_TP_CTLr_fields[] = {
   8735     { TP_IN_I_7_0f, 8, 24, SOCF_LE|SOCF_RO },
   8736     { TP_MUX_SEL_If, 5, 0, SOCF_LE },
   8737     { TP_PHY_SEL_If, 4, 16, SOCF_LE|SOCF_RO },
   8738     { TP_PORT_SEL_If, 4, 8, SOCF_LE }
   8739 };
   8740 
   8741 #endif
   8742 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8743     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8744     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8745     defined(BCM_56260_B0)
   8746 soc_field_info_t soc_USBH_TP_CTL_BCM53400_A0r_fields[] = {
   8747     { TP_IN_I_7_0f, 8, 24, SOCF_LE|SOCF_RO },
   8748     { TP_MUX_SEL_If, 5, 0, SOCF_LE },
   8749     { TP_PHY_SEL_If, 4, 16, SOCF_LE|SOCF_RO },
   8750     { TP_PORT_SEL_If, 4, 8, SOCF_LE }
   8751 };
   8752 
   8753 #endif
   8754 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8755     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8756 soc_field_info_t soc_USBH_TP_OUTP0r_fields[] = {
   8757     { TP_OUTf, 32, 0, SOCF_LE|SOCF_RO }
   8758 };
   8759 
   8760 #endif
   8761 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8762     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8763     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8764     defined(BCM_56260_B0)
   8765 soc_field_info_t soc_USBH_TP_OUTP0_BCM53400_A0r_fields[] = {
   8766     { TP_OUTf, 32, 0, SOCF_LE|SOCF_RO }
   8767 };
   8768 
   8769 #endif
   8770 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8771     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8772     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8773     defined(BCM_56260_B0)
   8774 soc_field_info_t soc_USBH_USB2H_STDCELL_SRAM_PARAMr_fields[] = {
   8775     { SRAM_TMf, 6, 0, SOCF_LE }
   8776 };
   8777 
   8778 #endif
   8779 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8780     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8781 soc_field_info_t soc_USBH_USBCMDr_fields[] = {
   8782     { ASYNCHRONOUS_SCHEDULE_ENABLEf, 1, 5, 0 },
   8783     { ASYNCHRONOUS_SCHEDULE_PARK_MODE_COUNTf, 2, 8, SOCF_LE },
   8784     { ASYNCHRONOUS_SCHEDULE_PARK_MODE_ENABLEf, 1, 11, 0 },
   8785     { FRAME_LIST_SIZEf, 2, 2, SOCF_LE },
   8786     { HOST_CONTROLLER_RESET_HCRESETf, 1, 1, 0 },
   8787     { INTERRUPT_ON_ASYNC_ADVANCE_DOORBELLf, 1, 6, 0 },
   8788     { INTERRUPT_THRESHOLD_CONTROLf, 8, 16, SOCF_LE },
   8789     { LIGHT_HOST_CONTROLLER_RESETf, 1, 7, 0 },
   8790     { PERIODIC_SCHEDULE_ENABLEf, 1, 4, 0 },
   8791     { RUN_STOP_RSf, 1, 0, 0 }
   8792 };
   8793 
   8794 #endif
   8795 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8796     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8797     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8798     defined(BCM_56260_B0)
   8799 soc_field_info_t soc_USBH_USBCMD_BCM53400_A0r_fields[] = {
   8800     { ASYNCHRONOUS_SCHEDULE_ENABLEf, 1, 5, 0 },
   8801     { ASYNCHRONOUS_SCHEDULE_PARK_MODE_COUNTf, 2, 8, SOCF_LE },
   8802     { ASYNCHRONOUS_SCHEDULE_PARK_MODE_ENABLEf, 1, 11, 0 },
   8803     { FRAME_LIST_SIZEf, 2, 2, SOCF_LE },
   8804     { HOST_CONTROLLER_RESET_HCRESETf, 1, 1, 0 },
   8805     { INTERRUPT_ON_ASYNC_ADVANCE_DOORBELLf, 1, 6, 0 },
   8806     { INTERRUPT_THRESHOLD_CONTROLf, 8, 16, SOCF_LE },
   8807     { LIGHT_HOST_CONTROLLER_RESETf, 1, 7, 0 },
   8808     { PERIODIC_SCHEDULE_ENABLEf, 1, 4, 0 },
   8809     { RUN_STOP_RSf, 1, 0, 0 }
   8810 };
   8811 
   8812 #endif
   8813 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8814     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8815 soc_field_info_t soc_USBH_USBINTRr_fields[] = {
   8816     { FRAME_LIST_ROLLOVER_ENABLEf, 1, 3, 0 },
   8817     { HOST_SYSTEM_ERROR_ENABLEf, 1, 4, 0 },
   8818     { INTERRUPT_ON_ASYNC_ADVANCE_ENABLEf, 1, 5, 0 },
   8819     { PORT_CHANGE_INTERRUPT_ENABLEf, 1, 2, 0 },
   8820     { USB_ERROR_INTERRUPT_ENABLEf, 1, 1, 0 },
   8821     { USB_INTERRUPT_ENABLEf, 1, 0, 0 }
   8822 };
   8823 
   8824 #endif
   8825 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8826     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8827     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8828     defined(BCM_56260_B0)
   8829 soc_field_info_t soc_USBH_USBINTR_BCM53400_A0r_fields[] = {
   8830     { FRAME_LIST_ROLLOVER_ENABLEf, 1, 3, 0 },
   8831     { HOST_SYSTEM_ERROR_ENABLEf, 1, 4, 0 },
   8832     { INTERRUPT_ON_ASYNC_ADVANCE_ENABLEf, 1, 5, 0 },
   8833     { PORT_CHANGE_INTERRUPT_ENABLEf, 1, 2, 0 },
   8834     { USB_ERROR_INTERRUPT_ENABLEf, 1, 1, 0 },
   8835     { USB_INTERRUPT_ENABLEf, 1, 0, 0 }
   8836 };
   8837 
   8838 #endif
   8839 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8840     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8841 soc_field_info_t soc_USBH_USBSTSr_fields[] = {
   8842     { ASYNCHRONOUS_SCHEDULE_STATUSf, 1, 15, SOCF_RO },
   8843     { FRAME_LIST_ROLLOVERf, 1, 3, 0 },
   8844     { HCHALTEDf, 1, 12, SOCF_RO },
   8845     { HOST_SYSTEM_ERRORf, 1, 4, 0 },
   8846     { INTERRUPT_ON_ASYNC_ADVANCEf, 1, 5, 0 },
   8847     { PERIODIC_SCHEDULE_STATUSf, 1, 14, SOCF_RO },
   8848     { PORT_CHANGE_DETECTf, 1, 2, 0 },
   8849     { RECLAMATIONf, 1, 13, SOCF_RO },
   8850     { USB_ERROR_INTERRUPT_USBERRINTf, 1, 1, 0 },
   8851     { USB_INTERRUPT_USBINTf, 1, 0, 0 }
   8852 };
   8853 
   8854 #endif
   8855 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8856     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8857     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8858     defined(BCM_56260_B0)
   8859 soc_field_info_t soc_USBH_USBSTS_BCM53400_A0r_fields[] = {
   8860     { ASYNCHRONOUS_SCHEDULE_STATUSf, 1, 15, SOCF_RO },
   8861     { FRAME_LIST_ROLLOVERf, 1, 3, 0 },
   8862     { HCHALTEDf, 1, 12, SOCF_RO },
   8863     { HOST_SYSTEM_ERRORf, 1, 4, 0 },
   8864     { INTERRUPT_ON_ASYNC_ADVANCEf, 1, 5, 0 },
   8865     { PERIODIC_SCHEDULE_STATUSf, 1, 14, SOCF_RO },
   8866     { PORT_CHANGE_DETECTf, 1, 2, 0 },
   8867     { RECLAMATIONf, 1, 13, SOCF_RO },
   8868     { USB_ERROR_INTERRUPT_USBERRINTf, 1, 1, 0 },
   8869     { USB_INTERRUPT_USBINTf, 1, 0, 0 }
   8870 };
   8871 
   8872 #endif
   8873 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   8874     defined(BCM_56450_B0) || defined(BCM_56450_B1)
   8875 soc_field_info_t soc_USBH_UTMI_P0CTLr_fields[] = {
   8876     { AFE_NON_DRIVINGf, 1, 0, 0 },
   8877     { BC10_ACTIVE_DMPULLUPf, 1, 10, 0 },
   8878     { BC10_ACTIVE_DPPULLUPf, 1, 9, 0 },
   8879     { BC10_DMPULLDOWNf, 1, 5, 0 },
   8880     { BC10_DPPULLDOWNf, 1, 4, 0 },
   8881     { BC10_IDLE_DMPULLDOWNf, 1, 7, 0 },
   8882     { BC10_IDLE_DPPULLDOWNf, 1, 6, 0 },
   8883     { DFE_LOOPBACKf, 1, 11, 0 },
   8884     { PHY_DISCONNETf, 1, 8, 0 },
   8885     { PHY_MODEf, 2, 2, SOCF_LE },
   8886     { RX_SYNC_DETECT_LENGTHf, 3, 12, SOCF_LE },
   8887     { SOFT_RESETBf, 1, 1, 0 }
   8888 };
   8889 
   8890 #endif
   8891 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8892     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8893     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8894     defined(BCM_56260_B0)
   8895 soc_field_info_t soc_USBH_UTMI_P0CTL_BCM53400_A0r_fields[] = {
   8896     { AFE_NON_DRIVINGf, 1, 0, 0 },
   8897     { BC10_ACTIVE_DMPULLUPf, 1, 10, 0 },
   8898     { BC10_DMPULLDOWNf, 1, 5, 0 },
   8899     { BC10_DPPULLDOWNf, 1, 4, 0 },
   8900     { BC10_IDLE_DMPULLDOWNf, 1, 7, 0 },
   8901     { BC10_IDLE_DPPULLDOWNf, 1, 6, 0 },
   8902     { CDR_CLK_POLf, 1, 9, 0 },
   8903     { DFE_POWERUP_FSMf, 1, 11, 0 },
   8904     { PHY_MODEf, 2, 2, SOCF_LE },
   8905     { REF_CLK_DIVIDERf, 1, 8, 0 },
   8906     { RX_SYNC_DETECT_LENGTHf, 3, 12, SOCF_LE },
   8907     { SOFT_RESETBf, 1, 1, 0 }
   8908 };
   8909 
   8910 #endif
   8911 #if defined(BCM_56370_A0)
   8912 soc_field_info_t soc_USBH_XHC_AIUCFGr_fields[] = {
   8913     { EPCf, 3, 24, SOCF_LE },
   8914     { EPSf, 3, 12, SOCF_LE },
   8915     { HIDf, 1, 15, 0 },
   8916     { ISOf, 3, 28, SOCF_LE },
   8917     { MELADJf, 6, 0, SOCF_LE },
   8918     { NTQf, 3, 16, SOCF_LE },
   8919     { PEP2f, 3, 6, SOCF_LE },
   8920     { PTQf, 3, 20, SOCF_LE },
   8921     { RESERVEDf, 3, 9, SOCF_LE|SOCF_RO|SOCF_RES }
   8922 };
   8923 
   8924 #endif
   8925 #if defined(BCM_56370_A0)
   8926 soc_field_info_t soc_USBH_XHC_AIUDMAr_fields[] = {
   8927     { RCMf, 2, 20, SOCF_LE },
   8928     { RESERVEDf, 16, 0, SOCF_LE|SOCF_RO|SOCF_RES },
   8929     { RTDf, 2, 18, SOCF_LE },
   8930     { RTEf, 2, 22, SOCF_LE },
   8931     { RTFf, 2, 16, SOCF_LE },
   8932     { WCMf, 2, 28, SOCF_LE },
   8933     { WEDf, 2, 24, SOCF_LE },
   8934     { WMIf, 2, 30, SOCF_LE },
   8935     { WRDf, 2, 26, SOCF_LE }
   8936 };
   8937 
   8938 #endif
   8939 #if defined(BCM_56370_A0)
   8940 soc_field_info_t soc_USBH_XHC_AIUFLAr_fields[] = {
   8941     { ACLKf, 9, 23, SOCF_LE },
   8942     { FLADJf, 6, 0, SOCF_LE },
   8943     { MFLVf, 16, 7, SOCF_LE },
   8944     { NFCf, 1, 6, SOCF_RO }
   8945 };
   8946 
   8947 #endif
   8948 #if defined(BCM_56370_A0)
   8949 soc_field_info_t soc_USBH_XHC_AXILPMr_fields[] = {
   8950     { ENBf, 1, 31, 0 },
   8951     { ITTf, 3, 0, SOCF_LE },
   8952     { RESERVEDf, 28, 3, SOCF_LE|SOCF_RO|SOCF_RES }
   8953 };
   8954 
   8955 #endif
   8956 #if defined(BCM_56370_A0)
   8957 soc_field_info_t soc_USBH_XHC_AXIRDAr_fields[] = {
   8958     { RESERVEDf, 7, 9, SOCF_LE|SOCF_RO|SOCF_RES },
   8959     { RFPCf, 1, 27, 0 },
   8960     { RSAf, 9, 0, SOCF_LE },
   8961     { RTSf, 4, 28, SOCF_LE },
   8962     { RUAf, 9, 16, SOCF_LE }
   8963 };
   8964 
   8965 #endif
   8966 #if defined(BCM_56370_A0)
   8967 soc_field_info_t soc_USBH_XHC_AXIWRAr_fields[] = {
   8968     { BYPf, 1, 9, 0 },
   8969     { RESERVEDf, 6, 10, SOCF_LE|SOCF_RO|SOCF_RES },
   8970     { WSAf, 9, 0, SOCF_LE },
   8971     { WTSf, 4, 28, SOCF_LE },
   8972     { WUAf, 9, 16, SOCF_LE }
   8973 };
   8974 
   8975 #endif
   8976 #if defined(BCM_56370_A0)
   8977 soc_field_info_t soc_USBH_XHC_BIUSPCr_fields[] = {
   8978     { MAJf, 4, 28, SOCF_LE|SOCF_RO },
   8979     { MINf, 4, 24, SOCF_LE|SOCF_RO },
   8980     { RESERVEDf, 16, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   8981     { RLSf, 4, 20, SOCF_LE|SOCF_RO },
   8982     { SPIf, 2, 2, SOCF_LE|SOCF_RO },
   8983     { TYPf, 2, 0, SOCF_LE|SOCF_RO }
   8984 };
   8985 
   8986 #endif
   8987 #if defined(BCM_56370_A0)
   8988 soc_field_info_t soc_USBH_XHC_CONFIGr_fields[] = {
   8989     { CIEf, 1, 9, 0 },
   8990     { MSEf, 8, 0, SOCF_LE },
   8991     { RESERVEDf, 22, 10, SOCF_LE|SOCF_RO|SOCF_RES },
   8992     { U3Ef, 1, 8, 0 }
   8993 };
   8994 
   8995 #endif
   8996 #if defined(BCM_56370_A0)
   8997 soc_field_info_t soc_USBH_XHC_CPARAMS1r_fields[] = {
   8998     { AC64f, 1, 0, SOCF_RO },
   8999     { BNCf, 1, 1, SOCF_RO },
   9000     { CFCf, 1, 11, SOCF_RO },
   9001     { CSZf, 1, 2, SOCF_RO },
   9002     { LRCf, 1, 5, SOCF_RO },
   9003     { LTCf, 1, 6, SOCF_RO },
   9004     { MPSAf, 4, 12, SOCF_LE|SOCF_RO },
   9005     { NSSf, 1, 7, SOCF_RO },
   9006     { PAEf, 1, 8, SOCF_RO },
   9007     { PINDf, 1, 4, SOCF_RO },
   9008     { PPCf, 1, 3, SOCF_RO },
   9009     { SECf, 1, 10, SOCF_RO },
   9010     { SPCf, 1, 9, SOCF_RO },
   9011     { XECPf, 16, 16, SOCF_LE|SOCF_RO }
   9012 };
   9013 
   9014 #endif
   9015 #if defined(BCM_56370_A0)
   9016 soc_field_info_t soc_USBH_XHC_CPARAMS2r_fields[] = {
   9017     { CICf, 1, 5, SOCF_RO },
   9018     { CMCf, 1, 1, SOCF_RO },
   9019     { CTCf, 1, 3, SOCF_RO },
   9020     { FSCf, 1, 2, SOCF_RO },
   9021     { LECf, 1, 4, SOCF_RO },
   9022     { RESERVEDf, 26, 6, SOCF_LE|SOCF_RO|SOCF_RES },
   9023     { U3Cf, 1, 0, SOCF_RO }
   9024 };
   9025 
   9026 #endif
   9027 #if defined(BCM_56370_A0)
   9028 soc_field_info_t soc_USBH_XHC_CPLIVERr_fields[] = {
   9029     { CPLf, 8, 0, SOCF_LE|SOCF_RO },
   9030     { IVHf, 8, 24, SOCF_LE|SOCF_RO },
   9031     { IVLf, 8, 16, SOCF_LE|SOCF_RO },
   9032     { RESERVEDf, 8, 8, SOCF_LE|SOCF_RO|SOCF_RES }
   9033 };
   9034 
   9035 #endif
   9036 #if defined(BCM_56370_A0)
   9037 soc_field_info_t soc_USBH_XHC_CRCRHr_fields[] = {
   9038     { CRPHf, 32, 0, SOCF_LE }
   9039 };
   9040 
   9041 #endif
   9042 #if defined(BCM_56370_A0)
   9043 soc_field_info_t soc_USBH_XHC_CRCRLr_fields[] = {
   9044     { CAf, 1, 2, 0 },
   9045     { CRPLf, 26, 6, SOCF_LE },
   9046     { CRRf, 1, 3, SOCF_RO },
   9047     { CSf, 1, 1, 0 },
   9048     { RCSf, 1, 0, 0 },
   9049     { RESERVEDf, 2, 4, SOCF_LE|SOCF_RO|SOCF_RES }
   9050 };
   9051 
   9052 #endif
   9053 #if defined(BCM_56370_A0)
   9054 soc_field_info_t soc_USBH_XHC_CSRSPCr_fields[] = {
   9055     { ASPf, 1, 2, SOCF_RO },
   9056     { MAJf, 4, 28, SOCF_LE|SOCF_RO },
   9057     { MINf, 4, 24, SOCF_LE|SOCF_RO },
   9058     { RESERVEDf, 17, 3, SOCF_LE|SOCF_RO|SOCF_RES },
   9059     { RLSf, 4, 20, SOCF_LE|SOCF_RO },
   9060     { TYPf, 2, 0, SOCF_LE|SOCF_RO }
   9061 };
   9062 
   9063 #endif
   9064 #if defined(BCM_56370_A0)
   9065 soc_field_info_t soc_USBH_XHC_CTTMTS0r_fields[] = {
   9066     { DCMf, 1, 31, SOCF_RO },
   9067     { RESERVEDf, 21, 10, SOCF_LE|SOCF_RO|SOCF_RES },
   9068     { SLAf, 10, 0, SOCF_LE|SOCF_RO }
   9069 };
   9070 
   9071 #endif
   9072 #if defined(BCM_56370_A0)
   9073 soc_field_info_t soc_USBH_XHC_CTTMTS1r_fields[] = {
   9074     { RESERVEDf, 6, 10, SOCF_LE|SOCF_RO|SOCF_RES },
   9075     { RXFf, 10, 0, SOCF_LE|SOCF_RO },
   9076     { TXFf, 10, 16, SOCF_LE|SOCF_RO }
   9077 };
   9078 
   9079 #endif
   9080 #if defined(BCM_56370_A0)
   9081 soc_field_info_t soc_USBH_XHC_DBLCMDr_fields[] = {
   9082     { RESERVEDf, 8, 8, SOCF_LE|SOCF_RO|SOCF_RES },
   9083     { SIDf, 16, 16, SOCF_LE },
   9084     { TGTf, 8, 0, SOCF_LE }
   9085 };
   9086 
   9087 #endif
   9088 #if defined(BCM_56370_A0)
   9089 soc_field_info_t soc_USBH_XHC_DBOFFr_fields[] = {
   9090     { DBOf, 14, 2, SOCF_LE|SOCF_RO },
   9091     { RESERVEDf, 2, 0, SOCF_LE|SOCF_RO|SOCF_RES }
   9092 };
   9093 
   9094 #endif
   9095 #if defined(BCM_56370_A0)
   9096 soc_field_info_t soc_USBH_XHC_DCBAAPHr_fields[] = {
   9097     { DCAHf, 32, 0, SOCF_LE }
   9098 };
   9099 
   9100 #endif
   9101 #if defined(BCM_56370_A0)
   9102 soc_field_info_t soc_USBH_XHC_DCBAAPLr_fields[] = {
   9103     { DCALf, 26, 6, SOCF_LE },
   9104     { RESERVEDf, 6, 0, SOCF_LE|SOCF_RO|SOCF_RES }
   9105 };
   9106 
   9107 #endif
   9108 #if defined(BCM_56370_A0)
   9109 soc_field_info_t soc_USBH_XHC_DNCTRLr_fields[] = {
   9110     { DNEf, 16, 0, SOCF_LE },
   9111     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   9112 };
   9113 
   9114 #endif
   9115 #if defined(BCM_56370_A0)
   9116 soc_field_info_t soc_USBH_XHC_ECHAIUr_fields[] = {
   9117     { CHMf, 2, 24, SOCF_LE },
   9118     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9119     { DMAf, 2, 30, SOCF_LE },
   9120     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9121     { RDPf, 1, 22, 0 },
   9122     { RESERVEDf, 1, 21, SOCF_RO|SOCF_RES },
   9123     { RTYf, 1, 20, 0 },
   9124     { SCHf, 3, 26, SOCF_LE },
   9125     { TDPf, 1, 23, 0 },
   9126     { WPFf, 4, 16, SOCF_LE|SOCF_RO }
   9127 };
   9128 
   9129 #endif
   9130 #if defined(BCM_56370_A0)
   9131 soc_field_info_t soc_USBH_XHC_ECHBIUr_fields[] = {
   9132     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9133     { CLKf, 11, 21, SOCF_LE|SOCF_RO },
   9134     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9135     { RESERVEDf, 2, 19, SOCF_LE|SOCF_RO|SOCF_RES },
   9136     { WIDf, 3, 16, SOCF_LE|SOCF_RO }
   9137 };
   9138 
   9139 #endif
   9140 #if defined(BCM_56370_A0)
   9141 soc_field_info_t soc_USBH_XHC_ECHCSRr_fields[] = {
   9142     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9143     { CLKf, 11, 21, SOCF_LE|SOCF_RO },
   9144     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9145     { RESERVEDf, 2, 19, SOCF_LE|SOCF_RO|SOCF_RES },
   9146     { WIDf, 3, 16, SOCF_LE|SOCF_RO }
   9147 };
   9148 
   9149 #endif
   9150 #if defined(BCM_56370_A0)
   9151 soc_field_info_t soc_USBH_XHC_ECHCTTr_fields[] = {
   9152     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9153     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9154     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   9155 };
   9156 
   9157 #endif
   9158 #if defined(BCM_56370_A0)
   9159 soc_field_info_t soc_USBH_XHC_ECHDBGr_fields[] = {
   9160     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9161     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9162     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   9163 };
   9164 
   9165 #endif
   9166 #if defined(BCM_56370_A0)
   9167 soc_field_info_t soc_USBH_XHC_ECHFSCr_fields[] = {
   9168     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9169     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9170     { RESERVEDf, 8, 24, SOCF_LE|SOCF_RO|SOCF_RES },
   9171     { RRMBf, 4, 16, SOCF_LE|SOCF_RO },
   9172     { WRMBf, 4, 20, SOCF_LE|SOCF_RO }
   9173 };
   9174 
   9175 #endif
   9176 #if defined(BCM_56370_A0)
   9177 soc_field_info_t soc_USBH_XHC_ECHHSTr_fields[] = {
   9178     { AUXf, 6, 24, SOCF_LE|SOCF_RO },
   9179     { CCCf, 1, 31, 0 },
   9180     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9181     { FSWf, 1, 16, SOCF_RO },
   9182     { IRAf, 1, 20, SOCF_RO },
   9183     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9184     { PMEf, 1, 30, SOCF_RO },
   9185     { RESERVEDf, 1, 18, SOCF_RO|SOCF_RES },
   9186     { TEDAf, 1, 17, SOCF_RO },
   9187     { ULSf, 1, 19, SOCF_RO }
   9188 };
   9189 
   9190 #endif
   9191 #if defined(BCM_56370_A0)
   9192 soc_field_info_t soc_USBH_XHC_ECHIOVr_fields[] = {
   9193     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9194     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9195     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   9196 };
   9197 
   9198 #endif
   9199 #if defined(BCM_56370_A0)
   9200 soc_field_info_t soc_USBH_XHC_ECHMSIr_fields[] = {
   9201     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9202     { MA64f, 1, 23, SOCF_RO },
   9203     { MMCf, 3, 20, SOCF_LE|SOCF_RO },
   9204     { MMEf, 3, 17, SOCF_LE|SOCF_RO },
   9205     { MSIEf, 1, 16, SOCF_RO },
   9206     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9207     { PVMCf, 1, 24, SOCF_RO },
   9208     { RESERVEDf, 7, 25, SOCF_LE|SOCF_RO|SOCF_RES }
   9209 };
   9210 
   9211 #endif
   9212 #if defined(BCM_56370_A0)
   9213 soc_field_info_t soc_USBH_XHC_ECHPMGr_fields[] = {
   9214     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9215     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9216     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   9217 };
   9218 
   9219 #endif
   9220 #if defined(BCM_56370_A0)
   9221 soc_field_info_t soc_USBH_XHC_ECHPRTr_fields[] = {
   9222     { CIDf, 8, 0, SOCF_LE },
   9223     { HSTf, 1, 16, 0 },
   9224     { MFTf, 8, 17, SOCF_LE },
   9225     { NCPf, 8, 8, SOCF_LE },
   9226     { RDPf, 1, 30, 0 },
   9227     { RESERVEDf, 5, 25, SOCF_LE|SOCF_RO|SOCF_RES },
   9228     { TDPf, 1, 31, 0 }
   9229 };
   9230 
   9231 #endif
   9232 #if defined(BCM_56370_A0)
   9233 soc_field_info_t soc_USBH_XHC_ECHRBVr_fields[] = {
   9234     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9235     { MAJf, 4, 28, SOCF_LE|SOCF_RO },
   9236     { MINf, 4, 24, SOCF_LE|SOCF_RO },
   9237     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9238     { RLSf, 8, 16, SOCF_LE|SOCF_RO }
   9239 };
   9240 
   9241 #endif
   9242 #if defined(BCM_56370_A0)
   9243 soc_field_info_t soc_USBH_XHC_ECHRH2r_fields[] = {
   9244     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9245     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9246     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   9247 };
   9248 
   9249 #endif
   9250 #if defined(BCM_56370_A0)
   9251 soc_field_info_t soc_USBH_XHC_ECHRHSr_fields[] = {
   9252     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9253     { DNRf, 4, 16, SOCF_LE|SOCF_RO },
   9254     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9255     { RESERVEDf, 2, 22, SOCF_LE|SOCF_RO|SOCF_RES },
   9256     { RPNf, 2, 20, SOCF_LE|SOCF_RO },
   9257     { RPOf, 7, 24, SOCF_LE|SOCF_RO }
   9258 };
   9259 
   9260 #endif
   9261 #if defined(BCM_56370_A0)
   9262 soc_field_info_t soc_USBH_XHC_ECHRSV2r_fields[] = {
   9263     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9264     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9265     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   9266 };
   9267 
   9268 #endif
   9269 #if defined(BCM_56370_A0)
   9270 soc_field_info_t soc_USBH_XHC_ECHRSVOr_fields[] = {
   9271     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9272     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9273     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   9274 };
   9275 
   9276 #endif
   9277 #if defined(BCM_56370_A0)
   9278 soc_field_info_t soc_USBH_XHC_ECHSPT2r_fields[] = {
   9279     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9280     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9281     { RMAJf, 8, 24, SOCF_LE|SOCF_RO },
   9282     { RMINf, 8, 16, SOCF_LE|SOCF_RO }
   9283 };
   9284 
   9285 #endif
   9286 #if defined(BCM_56370_A0)
   9287 soc_field_info_t soc_USBH_XHC_ECHSPT3r_fields[] = {
   9288     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9289     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9290     { RMAJf, 8, 24, SOCF_LE|SOCF_RO },
   9291     { RMINf, 8, 16, SOCF_LE|SOCF_RO }
   9292 };
   9293 
   9294 #endif
   9295 #if defined(BCM_56370_A0)
   9296 soc_field_info_t soc_USBH_XHC_ECHSSPr_fields[] = {
   9297     { CIDf, 8, 0, SOCF_LE|SOCF_RO },
   9298     { NCPf, 8, 8, SOCF_LE|SOCF_RO },
   9299     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   9300 };
   9301 
   9302 #endif
   9303 #if defined(BCM_56370_A0)
   9304 soc_field_info_t soc_USBH_XHC_ERDPH0r_fields[] = {
   9305     { DPHf, 32, 0, SOCF_LE }
   9306 };
   9307 
   9308 #endif
   9309 #if defined(BCM_56370_A0)
   9310 soc_field_info_t soc_USBH_XHC_ERDPL0r_fields[] = {
   9311     { DESIf, 3, 0, SOCF_LE },
   9312     { DPLf, 28, 4, SOCF_LE },
   9313     { EHBf, 1, 3, 0 }
   9314 };
   9315 
   9316 #endif
   9317 #if defined(BCM_56370_A0)
   9318 soc_field_info_t soc_USBH_XHC_ERSTBAL0r_fields[] = {
   9319     { BALf, 28, 4, SOCF_LE },
   9320     { RESERVEDf, 4, 0, SOCF_LE|SOCF_RO|SOCF_RES }
   9321 };
   9322 
   9323 #endif
   9324 #if defined(BCM_56370_A0)
   9325 soc_field_info_t soc_USBH_XHC_ERSTSZ0r_fields[] = {
   9326     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES },
   9327     { TSZf, 16, 0, SOCF_LE }
   9328 };
   9329 
   9330 #endif
   9331 #if defined(BCM_56370_A0)
   9332 soc_field_info_t soc_USBH_XHC_HSTDBGr_fields[] = {
   9333     { ETEf, 1, 31, 0 },
   9334     { INPf, 8, 0, SOCF_LE|SOCF_RO },
   9335     { OUTPf, 8, 8, SOCF_LE|SOCF_RO },
   9336     { RESERVEDf, 15, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   9337 };
   9338 
   9339 #endif
   9340 #if defined(BCM_56370_A0)
   9341 soc_field_info_t soc_USBH_XHC_HSTNPLr_fields[] = {
   9342     { NPLf, 23, 9, SOCF_LE|SOCF_RO },
   9343     { RESERVEDf, 9, 0, SOCF_LE|SOCF_RO|SOCF_RES }
   9344 };
   9345 
   9346 #endif
   9347 #if defined(BCM_56370_A0)
   9348 soc_field_info_t soc_USBH_XHC_IMAN0r_fields[] = {
   9349     { IEf, 1, 1, 0 },
   9350     { IPf, 1, 0, 0 },
   9351     { RESERVEDf, 30, 2, SOCF_LE|SOCF_RO|SOCF_RES }
   9352 };
   9353 
   9354 #endif
   9355 #if defined(BCM_56370_A0)
   9356 soc_field_info_t soc_USBH_XHC_IMOD0r_fields[] = {
   9357     { IMODCf, 16, 16, SOCF_LE|SOCF_RO },
   9358     { IMODIf, 16, 0, SOCF_LE }
   9359 };
   9360 
   9361 #endif
   9362 #if defined(BCM_56370_A0)
   9363 soc_field_info_t soc_USBH_XHC_IRAADRr_fields[] = {
   9364     { ADRf, 22, 2, SOCF_LE|SOCF_WO },
   9365     { MODf, 1, 0, SOCF_WO },
   9366     { RESERVEDf, 1, 1, SOCF_RO|SOCF_RES }
   9367 };
   9368 
   9369 #endif
   9370 #if defined(BCM_56370_A0)
   9371 soc_field_info_t soc_USBH_XHC_MFINDEXr_fields[] = {
   9372     { MFIf, 14, 0, SOCF_LE },
   9373     { RESERVEDf, 18, 14, SOCF_LE|SOCF_RO|SOCF_RES }
   9374 };
   9375 
   9376 #endif
   9377 #if defined(BCM_56370_A0)
   9378 soc_field_info_t soc_USBH_XHC_PAGESIZEr_fields[] = {
   9379     { PSf, 16, 0, SOCF_LE|SOCF_RO },
   9380     { RESERVEDf, 16, 16, SOCF_LE|SOCF_RO|SOCF_RES }
   9381 };
   9382 
   9383 #endif
   9384 #if defined(BCM_56370_A0)
   9385 soc_field_info_t soc_USBH_XHC_PNSTR2r_fields[] = {
   9386     { STRf, 32, 0, SOCF_LE|SOCF_RO }
   9387 };
   9388 
   9389 #endif
   9390 #if defined(BCM_56370_A0)
   9391 soc_field_info_t soc_USBH_XHC_PORTPM1r_fields[] = {
   9392     { FLAf, 1, 16, 0 },
   9393     { RESERVEDf, 15, 17, SOCF_LE|SOCF_RO|SOCF_RES },
   9394     { U1Tf, 8, 0, SOCF_LE },
   9395     { U2Tf, 8, 8, SOCF_LE }
   9396 };
   9397 
   9398 #endif
   9399 #if defined(BCM_56370_A0)
   9400 soc_field_info_t soc_USBH_XHC_PORTSC1r_fields[] = {
   9401     { CASf, 1, 24, 0 },
   9402     { CCSf, 1, 0, SOCF_RO },
   9403     { CECf, 1, 23, 0 },
   9404     { CSCf, 1, 17, 0 },
   9405     { DNRf, 1, 30, 0 },
   9406     { LWSf, 1, 16, 0 },
   9407     { OCAf, 1, 3, 0 },
   9408     { OCCf, 1, 20, 0 },
   9409     { PECf, 1, 18, 0 },
   9410     { PEDf, 1, 1, 0 },
   9411     { PICf, 2, 14, SOCF_LE },
   9412     { PLCf, 1, 22, 0 },
   9413     { PLSf, 4, 5, SOCF_LE },
   9414     { PPf, 1, 9, 0 },
   9415     { PRf, 1, 4, 0 },
   9416     { PRCf, 1, 21, 0 },
   9417     { PSf, 4, 10, SOCF_LE|SOCF_RO },
   9418     { RESERVEDf, 1, 2, SOCF_RO|SOCF_RES },
   9419     { WCEf, 1, 25, 0 },
   9420     { WDEf, 1, 26, 0 },
   9421     { WOEf, 1, 27, 0 },
   9422     { WPRf, 1, 31, 0 },
   9423     { WRCf, 1, 19, 0 }
   9424 };
   9425 
   9426 #endif
   9427 #if defined(BCM_56370_A0)
   9428 soc_field_info_t soc_USBH_XHC_PSUM2r_fields[] = {
   9429     { BLCf, 1, 20, SOCF_RO },
   9430     { CPCf, 8, 8, SOCF_LE|SOCF_RO },
   9431     { CPOf, 8, 0, SOCF_LE|SOCF_RO },
   9432     { HLCf, 1, 19, SOCF_RO },
   9433     { HSOf, 1, 17, SOCF_RO },
   9434     { IHIf, 1, 18, SOCF_RO },
   9435     { MHDf, 3, 25, SOCF_LE|SOCF_RO },
   9436     { PSICf, 4, 28, SOCF_LE|SOCF_RO },
   9437     { RESERVEDf, 1, 16, SOCF_RO|SOCF_RES }
   9438 };
   9439 
   9440 #endif
   9441 #if defined(BCM_56370_A0)
   9442 soc_field_info_t soc_USBH_XHC_PTSLTYP2r_fields[] = {
   9443     { PSTf, 5, 0, SOCF_LE|SOCF_RO },
   9444     { RESERVEDf, 27, 5, SOCF_LE|SOCF_RO|SOCF_RES }
   9445 };
   9446 
   9447 #endif
   9448 #if defined(BCM_56370_A0)
   9449 soc_field_info_t soc_USBH_XHC_RTOFFr_fields[] = {
   9450     { RESERVEDf, 5, 0, SOCF_LE|SOCF_RO|SOCF_RES },
   9451     { RTOf, 11, 5, SOCF_LE|SOCF_RO }
   9452 };
   9453 
   9454 #endif
   9455 #if defined(BCM_56370_A0)
   9456 soc_field_info_t soc_USBH_XHC_SPARAMS1r_fields[] = {
   9457     { MITSf, 11, 8, SOCF_LE|SOCF_RO },
   9458     { MSLSf, 8, 0, SOCF_LE|SOCF_RO },
   9459     { NPTSf, 8, 24, SOCF_LE|SOCF_RO },
   9460     { RESERVEDf, 5, 19, SOCF_LE|SOCF_RO|SOCF_RES }
   9461 };
   9462 
   9463 #endif
   9464 #if defined(BCM_56370_A0)
   9465 soc_field_info_t soc_USBH_XHC_SPARAMS2r_fields[] = {
   9466     { ISTf, 4, 0, SOCF_LE|SOCF_RO },
   9467     { MERSTf, 4, 4, SOCF_LE|SOCF_RO },
   9468     { MSPBSHf, 5, 21, SOCF_LE|SOCF_RO },
   9469     { MSPBSLf, 5, 27, SOCF_LE|SOCF_RO },
   9470     { RESERVEDf, 13, 8, SOCF_LE|SOCF_RO|SOCF_RES },
   9471     { SPRf, 1, 26, SOCF_RO }
   9472 };
   9473 
   9474 #endif
   9475 #if defined(BCM_56370_A0)
   9476 soc_field_info_t soc_USBH_XHC_SPARAMS3r_fields[] = {
   9477     { RESERVEDf, 8, 8, SOCF_LE|SOCF_RO|SOCF_RES },
   9478     { U1Lf, 8, 0, SOCF_LE|SOCF_RO },
   9479     { U2Lf, 16, 16, SOCF_LE|SOCF_RO }
   9480 };
   9481 
   9482 #endif
   9483 #if defined(BCM_56370_A0)
   9484 soc_field_info_t soc_USBH_XHC_USBCMDr_fields[] = {
   9485     { CMEf, 1, 13, 0 },
   9486     { CRSf, 1, 9, 0 },
   9487     { CSSf, 1, 8, 0 },
   9488     { EU3Sf, 1, 11, 0 },
   9489     { EWEf, 1, 10, 0 },
   9490     { HSEEf, 1, 3, 0 },
   9491     { INTEf, 1, 2, 0 },
   9492     { LRSTf, 1, 7, 0 },
   9493     { RESERVEDf, 3, 4, SOCF_LE|SOCF_RO|SOCF_RES },
   9494     { RSf, 1, 0, 0 },
   9495     { RSTf, 1, 1, 0 },
   9496     { SPEf, 1, 12, 0 }
   9497 };
   9498 
   9499 #endif
   9500 #if defined(BCM_56370_A0)
   9501 soc_field_info_t soc_USBH_XHC_USBSTSr_fields[] = {
   9502     { CEf, 1, 12, SOCF_RO },
   9503     { CHf, 1, 0, SOCF_RO },
   9504     { CNRf, 1, 11, SOCF_RO },
   9505     { EINTf, 1, 3, 0 },
   9506     { HSEf, 1, 2, 0 },
   9507     { PCDf, 1, 4, 0 },
   9508     { RESERVEDf, 1, 1, SOCF_RO|SOCF_RES },
   9509     { RSSf, 1, 9, SOCF_RO },
   9510     { SREf, 1, 10, 0 },
   9511     { SSSf, 1, 8, SOCF_RO }
   9512 };
   9513 
   9514 #endif
   9515 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   9516     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9517 soc_field_info_t soc_USER_OTP_BONDOPTION_127_96_REGr_fields[] = {
   9518     { BONDOPTION_VALUEf, 32, 0, SOCF_LE|SOCF_RO }
   9519 };
   9520 
   9521 #endif
   9522 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   9523     defined(BCM_56870_A0)
   9524 soc_field_info_t soc_UAT_EXTRACTION_CTRL_ID_PROFILEm_fields[] = {
   9525     { EXTRACTION_CTRL_ID_ACTIONf, 16, 0, SOCF_LE | SOCF_GLOBAL },
   9526     { INHERITANCE_GROUPf, 2, 16, SOCF_LE | SOCF_GLOBAL }
   9527 };
   9528 #endif
   9529 
   9530 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   9531 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_CAMm_fields[] = {
   9532     { FIELD_1_DATAf, 32, 1, SOCF_LE | SOCF_GLOBAL },
   9533     { FIELD_1_MASKf, 32, 65, SOCF_LE | SOCF_GLOBAL },
   9534     { FIELD_2_DATAf, 32, 33, SOCF_LE | SOCF_GLOBAL },
   9535     { FIELD_2_MASKf, 32, 97, SOCF_LE | SOCF_GLOBAL },
   9536     { KEYf, 64, 1, SOCF_LE | SOCF_GLOBAL },
   9537     { MASKf, 64, 65, SOCF_LE | SOCF_GLOBAL },
   9538     { VALIDf, 1, 0, 0 | SOCF_GLOBAL }
   9539 };
   9540 #endif
   9541 
   9542 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   9543     defined(BCM_56270_A0)
   9544 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_CAM_BCM56260_A0m_fields[] = {
   9545     { FIELD_1_DATAf, 32, 1, SOCF_LE | SOCF_GLOBAL },
   9546     { FIELD_1_MASKf, 32, 65, SOCF_LE | SOCF_GLOBAL },
   9547     { FIELD_2_DATAf, 32, 33, SOCF_LE | SOCF_GLOBAL },
   9548     { FIELD_2_MASKf, 32, 97, SOCF_LE | SOCF_GLOBAL },
   9549     { KEYf, 64, 1, SOCF_LE | SOCF_GLOBAL },
   9550     { MASKf, 64, 65, SOCF_LE | SOCF_GLOBAL },
   9551     { UDF0_DATAf, 32, 1, SOCF_LE | SOCF_GLOBAL },
   9552     { UDF0_MASKf, 32, 65, SOCF_LE | SOCF_GLOBAL },
   9553     { UDF1_DATAf, 32, 33, SOCF_LE | SOCF_GLOBAL },
   9554     { UDF1_MASKf, 32, 97, SOCF_LE | SOCF_GLOBAL },
   9555     { VALIDf, 1, 0, 0 | SOCF_GLOBAL }
   9556 };
   9557 #endif
   9558 
   9559 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   9560     defined(BCM_56450_B1)
   9561 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_CAM_BCM56450_A0m_fields[] = {
   9562     { FIELD_1_DATAf, 32, 1, SOCF_LE | SOCF_GLOBAL },
   9563     { FIELD_1_MASKf, 32, 65, SOCF_LE | SOCF_GLOBAL },
   9564     { FIELD_2_DATAf, 32, 33, SOCF_LE | SOCF_GLOBAL },
   9565     { FIELD_2_MASKf, 32, 97, SOCF_LE | SOCF_GLOBAL },
   9566     { KEYf, 64, 1, SOCF_LE | SOCF_GLOBAL },
   9567     { MASKf, 64, 65, SOCF_LE | SOCF_GLOBAL },
   9568     { UDF0_DATAf, 32, 1, SOCF_LE | SOCF_GLOBAL },
   9569     { UDF0_MASKf, 32, 65, SOCF_LE | SOCF_GLOBAL },
   9570     { UDF1_DATAf, 32, 33, SOCF_LE | SOCF_GLOBAL },
   9571     { UDF1_MASKf, 32, 97, SOCF_LE | SOCF_GLOBAL },
   9572     { VALIDf, 1, 0, 0 | SOCF_GLOBAL }
   9573 };
   9574 #endif
   9575 
   9576 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   9577     defined(BCM_56670_A0) || defined(BCM_56670_B0) || \
   9578     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   9579     defined(BCM_56970_A0)
   9580 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_CAM_BCM56960_A0m_fields[] = {
   9581     { FIELD_1_DATAf, 32, 1, SOCF_LE | SOCF_GLOBAL },
   9582     { FIELD_1_MASKf, 32, 65, SOCF_LE | SOCF_GLOBAL },
   9583     { FIELD_2_DATAf, 32, 33, SOCF_LE | SOCF_GLOBAL },
   9584     { FIELD_2_MASKf, 32, 97, SOCF_LE | SOCF_GLOBAL },
   9585     { KEYf, 64, 1, SOCF_LE | SOCF_GLOBAL },
   9586     { MASKf, 64, 65, SOCF_LE | SOCF_GLOBAL },
   9587     { VALIDf, 1, 0, 0 | SOCF_GLOBAL }
   9588 };
   9589 #endif
   9590 
   9591 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9592 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_CAM_BCM56980_A0m_fields[] = {
   9593     { FIELD_1_DATAf, 32, 1, SOCF_LE | SOCF_GLOBAL },
   9594     { FIELD_1_MASKf, 32, 65, SOCF_LE | SOCF_GLOBAL },
   9595     { FIELD_2_DATAf, 32, 33, SOCF_LE | SOCF_GLOBAL },
   9596     { FIELD_2_MASKf, 32, 97, SOCF_LE | SOCF_GLOBAL },
   9597     { KEYf, 64, 1, SOCF_LE | SOCF_GLOBAL },
   9598     { MASKf, 64, 65, SOCF_LE | SOCF_GLOBAL },
   9599     { VALIDf, 1, 0, 0 | SOCF_GLOBAL }
   9600 };
   9601 #endif
   9602 
   9603 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   9604 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_RAMm_fields[] = {
   9605     { FIELD_1_MASKf, 16, 4, SOCF_LE | SOCF_GLOBAL },
   9606     { FIELD_1_OFFSETf, 4, 0, SOCF_LE | SOCF_GLOBAL },
   9607     { FIELD_2_MASKf, 16, 24, SOCF_LE | SOCF_GLOBAL },
   9608     { FIELD_2_OFFSETf, 4, 20, SOCF_LE | SOCF_GLOBAL }
   9609 };
   9610 #endif
   9611 
   9612 #if defined(BCM_56970_A0)
   9613 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_RAM_1m_fields[] = {
   9614     { FIELD_10_MASKf, 16, 144, SOCF_LE | SOCF_GLOBAL },
   9615     { FIELD_11_MASKf, 16, 160, SOCF_LE | SOCF_GLOBAL },
   9616     { FIELD_12_MASKf, 16, 176, SOCF_LE | SOCF_GLOBAL },
   9617     { FIELD_13_MASKf, 16, 192, SOCF_LE | SOCF_GLOBAL },
   9618     { FIELD_1_MASKf, 16, 0, SOCF_LE | SOCF_GLOBAL },
   9619     { FIELD_2_MASKf, 16, 16, SOCF_LE | SOCF_GLOBAL },
   9620     { FIELD_3_MASKf, 16, 32, SOCF_LE | SOCF_GLOBAL },
   9621     { FIELD_4_MASKf, 16, 48, SOCF_LE | SOCF_GLOBAL },
   9622     { FIELD_5_MASKf, 16, 64, SOCF_LE | SOCF_GLOBAL },
   9623     { FIELD_6_MASKf, 16, 80, SOCF_LE | SOCF_GLOBAL },
   9624     { FIELD_7_MASKf, 16, 96, SOCF_LE | SOCF_GLOBAL },
   9625     { FIELD_8_MASKf, 16, 112, SOCF_LE | SOCF_GLOBAL },
   9626     { FIELD_9_MASKf, 16, 128, SOCF_LE | SOCF_GLOBAL }
   9627 };
   9628 #endif
   9629 
   9630 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9631 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_RAM_1_BCM56980_A0m_fields[] = {
   9632     { FIELD_10_MASKf, 16, 144, SOCF_LE | SOCF_GLOBAL },
   9633     { FIELD_11_MASKf, 16, 160, SOCF_LE | SOCF_GLOBAL },
   9634     { FIELD_12_MASKf, 16, 176, SOCF_LE | SOCF_GLOBAL },
   9635     { FIELD_13_MASKf, 16, 192, SOCF_LE | SOCF_GLOBAL },
   9636     { FIELD_1_MASKf, 16, 0, SOCF_LE | SOCF_GLOBAL },
   9637     { FIELD_2_MASKf, 16, 16, SOCF_LE | SOCF_GLOBAL },
   9638     { FIELD_3_MASKf, 16, 32, SOCF_LE | SOCF_GLOBAL },
   9639     { FIELD_4_MASKf, 16, 48, SOCF_LE | SOCF_GLOBAL },
   9640     { FIELD_5_MASKf, 16, 64, SOCF_LE | SOCF_GLOBAL },
   9641     { FIELD_6_MASKf, 16, 80, SOCF_LE | SOCF_GLOBAL },
   9642     { FIELD_7_MASKf, 16, 96, SOCF_LE | SOCF_GLOBAL },
   9643     { FIELD_8_MASKf, 16, 112, SOCF_LE | SOCF_GLOBAL },
   9644     { FIELD_9_MASKf, 16, 128, SOCF_LE | SOCF_GLOBAL }
   9645 };
   9646 #endif
   9647 
   9648 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   9649     defined(BCM_56270_A0)
   9650 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_RAM_BCM56260_A0m_fields[] = {
   9651     { FIELD_1_MASKf, 16, 4, SOCF_LE | SOCF_GLOBAL },
   9652     { FIELD_1_OFFSETf, 4, 0, SOCF_LE | SOCF_GLOBAL },
   9653     { FIELD_2_MASKf, 16, 24, SOCF_LE | SOCF_GLOBAL },
   9654     { FIELD_2_OFFSETf, 4, 20, SOCF_LE | SOCF_GLOBAL },
   9655     { MASK0f, 16, 4, SOCF_LE | SOCF_GLOBAL },
   9656     { MASK1f, 16, 24, SOCF_LE | SOCF_GLOBAL },
   9657     { OFFSET0f, 4, 0, SOCF_LE | SOCF_GLOBAL },
   9658     { OFFSET1f, 4, 20, SOCF_LE | SOCF_GLOBAL }
   9659 };
   9660 #endif
   9661 
   9662 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   9663     defined(BCM_56450_B1)
   9664 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_RAM_BCM56450_A0m_fields[] = {
   9665     { FIELD_1_MASKf, 16, 4, SOCF_LE | SOCF_GLOBAL },
   9666     { FIELD_1_OFFSETf, 4, 0, SOCF_LE | SOCF_GLOBAL },
   9667     { FIELD_2_MASKf, 16, 24, SOCF_LE | SOCF_GLOBAL },
   9668     { FIELD_2_OFFSETf, 4, 20, SOCF_LE | SOCF_GLOBAL },
   9669     { MASK0f, 16, 4, SOCF_LE | SOCF_GLOBAL },
   9670     { MASK1f, 16, 24, SOCF_LE | SOCF_GLOBAL },
   9671     { OFFSET0f, 4, 0, SOCF_LE | SOCF_GLOBAL },
   9672     { OFFSET1f, 4, 20, SOCF_LE | SOCF_GLOBAL }
   9673 };
   9674 #endif
   9675 
   9676 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   9677     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9678 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_RAM_BCM56560_A0m_fields[] = {
   9679     { FIELD_1_MASKf, 16, 4, SOCF_LE | SOCF_GLOBAL },
   9680     { FIELD_1_OFFSETf, 4, 0, SOCF_LE | SOCF_GLOBAL },
   9681     { FIELD_2_MASKf, 16, 24, SOCF_LE | SOCF_GLOBAL },
   9682     { FIELD_2_OFFSETf, 4, 20, SOCF_LE | SOCF_GLOBAL }
   9683 };
   9684 #endif
   9685 
   9686 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9687 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_RAM_BCM56960_A0m_fields[] = {
   9688     { FIELD_1_MASKf, 16, 5, SOCF_LE | SOCF_GLOBAL },
   9689     { FIELD_1_OFFSETf, 4, 1, SOCF_LE | SOCF_GLOBAL },
   9690     { FIELD_1_TYPEf, 1, 0, 0 | SOCF_GLOBAL },
   9691     { FIELD_2_MASKf, 16, 26, SOCF_LE | SOCF_GLOBAL },
   9692     { FIELD_2_OFFSETf, 4, 22, SOCF_LE | SOCF_GLOBAL },
   9693     { FIELD_2_TYPEf, 1, 21, 0 | SOCF_GLOBAL },
   9694     { UDF_CHUNK_ID_1f, 3, 1, SOCF_LE | SOCF_GLOBAL },
   9695     { UDF_CHUNK_ID_2f, 3, 22, SOCF_LE | SOCF_GLOBAL },
   9696     { UDF_SEL_1f, 1, 4, 0 | SOCF_GLOBAL },
   9697     { UDF_SEL_2f, 1, 25, 0 | SOCF_GLOBAL }
   9698 };
   9699 #endif
   9700 
   9701 #if defined(BCM_56970_A0)
   9702 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_RAM_BCM56970_A0m_fields[] = {
   9703     { FIELD_10_TYPEf, 1, 45, 0 | SOCF_GLOBAL },
   9704     { FIELD_11_TYPEf, 1, 50, 0 | SOCF_GLOBAL },
   9705     { FIELD_12_TYPEf, 1, 55, 0 | SOCF_GLOBAL },
   9706     { FIELD_13_TYPEf, 1, 60, 0 | SOCF_GLOBAL },
   9707     { FIELD_1_OFFSETf, 4, 1, SOCF_LE | SOCF_GLOBAL },
   9708     { FIELD_1_TYPEf, 1, 0, 0 | SOCF_GLOBAL },
   9709     { FIELD_2_OFFSETf, 4, 6, SOCF_LE | SOCF_GLOBAL },
   9710     { FIELD_2_TYPEf, 1, 5, 0 | SOCF_GLOBAL },
   9711     { FIELD_3_TYPEf, 1, 10, 0 | SOCF_GLOBAL },
   9712     { FIELD_4_TYPEf, 1, 15, 0 | SOCF_GLOBAL },
   9713     { FIELD_5_TYPEf, 1, 20, 0 | SOCF_GLOBAL },
   9714     { FIELD_6_TYPEf, 1, 25, 0 | SOCF_GLOBAL },
   9715     { FIELD_7_TYPEf, 1, 30, 0 | SOCF_GLOBAL },
   9716     { FIELD_8_TYPEf, 1, 35, 0 | SOCF_GLOBAL },
   9717     { FIELD_9_TYPEf, 1, 40, 0 | SOCF_GLOBAL },
   9718     { UDF_CHUNK_ID_1f, 3, 1, SOCF_LE | SOCF_GLOBAL },
   9719     { UDF_CHUNK_ID_10f, 3, 46, SOCF_LE | SOCF_GLOBAL },
   9720     { UDF_CHUNK_ID_11f, 3, 51, SOCF_LE | SOCF_GLOBAL },
   9721     { UDF_CHUNK_ID_12f, 3, 56, SOCF_LE | SOCF_GLOBAL },
   9722     { UDF_CHUNK_ID_13f, 3, 61, SOCF_LE | SOCF_GLOBAL },
   9723     { UDF_CHUNK_ID_2f, 3, 6, SOCF_LE | SOCF_GLOBAL },
   9724     { UDF_CHUNK_ID_3f, 3, 11, SOCF_LE | SOCF_GLOBAL },
   9725     { UDF_CHUNK_ID_4f, 3, 16, SOCF_LE | SOCF_GLOBAL },
   9726     { UDF_CHUNK_ID_5f, 3, 21, SOCF_LE | SOCF_GLOBAL },
   9727     { UDF_CHUNK_ID_6f, 3, 26, SOCF_LE | SOCF_GLOBAL },
   9728     { UDF_CHUNK_ID_7f, 3, 31, SOCF_LE | SOCF_GLOBAL },
   9729     { UDF_CHUNK_ID_8f, 3, 36, SOCF_LE | SOCF_GLOBAL },
   9730     { UDF_CHUNK_ID_9f, 3, 41, SOCF_LE | SOCF_GLOBAL },
   9731     { UDF_SEL_1f, 1, 4, 0 | SOCF_GLOBAL },
   9732     { UDF_SEL_10f, 1, 49, 0 | SOCF_GLOBAL },
   9733     { UDF_SEL_11f, 1, 54, 0 | SOCF_GLOBAL },
   9734     { UDF_SEL_12f, 1, 59, 0 | SOCF_GLOBAL },
   9735     { UDF_SEL_13f, 1, 64, 0 | SOCF_GLOBAL },
   9736     { UDF_SEL_2f, 1, 9, 0 | SOCF_GLOBAL },
   9737     { UDF_SEL_3f, 1, 14, 0 | SOCF_GLOBAL },
   9738     { UDF_SEL_4f, 1, 19, 0 | SOCF_GLOBAL },
   9739     { UDF_SEL_5f, 1, 24, 0 | SOCF_GLOBAL },
   9740     { UDF_SEL_6f, 1, 29, 0 | SOCF_GLOBAL },
   9741     { UDF_SEL_7f, 1, 34, 0 | SOCF_GLOBAL },
   9742     { UDF_SEL_8f, 1, 39, 0 | SOCF_GLOBAL },
   9743     { UDF_SEL_9f, 1, 44, 0 | SOCF_GLOBAL }
   9744 };
   9745 #endif
   9746 
   9747 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9748 soc_field_info_t soc_UDF_CONDITIONAL_CHECK_TABLE_RAM_BCM56980_A0m_fields[] = {
   9749     { FIELD_10_TYPEf, 1, 45, 0 | SOCF_GLOBAL },
   9750     { FIELD_11_TYPEf, 1, 50, 0 | SOCF_GLOBAL },
   9751     { FIELD_12_TYPEf, 1, 55, 0 | SOCF_GLOBAL },
   9752     { FIELD_13_TYPEf, 1, 60, 0 | SOCF_GLOBAL },
   9753     { FIELD_1_OFFSETf, 4, 1, SOCF_LE | SOCF_GLOBAL },
   9754     { FIELD_1_TYPEf, 1, 0, 0 | SOCF_GLOBAL },
   9755     { FIELD_2_OFFSETf, 4, 6, SOCF_LE | SOCF_GLOBAL },
   9756     { FIELD_2_TYPEf, 1, 5, 0 | SOCF_GLOBAL },
   9757     { FIELD_3_TYPEf, 1, 10, 0 | SOCF_GLOBAL },
   9758     { FIELD_4_TYPEf, 1, 15, 0 | SOCF_GLOBAL },
   9759     { FIELD_5_TYPEf, 1, 20, 0 | SOCF_GLOBAL },
   9760     { FIELD_6_TYPEf, 1, 25, 0 | SOCF_GLOBAL },
   9761     { FIELD_7_TYPEf, 1, 30, 0 | SOCF_GLOBAL },
   9762     { FIELD_8_TYPEf, 1, 35, 0 | SOCF_GLOBAL },
   9763     { FIELD_9_TYPEf, 1, 40, 0 | SOCF_GLOBAL },
   9764     { UDF_CHUNK_ID_1f, 3, 1, SOCF_LE | SOCF_GLOBAL },
   9765     { UDF_CHUNK_ID_10f, 3, 46, SOCF_LE | SOCF_GLOBAL },
   9766     { UDF_CHUNK_ID_11f, 3, 51, SOCF_LE | SOCF_GLOBAL },
   9767     { UDF_CHUNK_ID_12f, 3, 56, SOCF_LE | SOCF_GLOBAL },
   9768     { UDF_CHUNK_ID_13f, 3, 61, SOCF_LE | SOCF_GLOBAL },
   9769     { UDF_CHUNK_ID_2f, 3, 6, SOCF_LE | SOCF_GLOBAL },
   9770     { UDF_CHUNK_ID_3f, 3, 11, SOCF_LE | SOCF_GLOBAL },
   9771     { UDF_CHUNK_ID_4f, 3, 16, SOCF_LE | SOCF_GLOBAL },
   9772     { UDF_CHUNK_ID_5f, 3, 21, SOCF_LE | SOCF_GLOBAL },
   9773     { UDF_CHUNK_ID_6f, 3, 26, SOCF_LE | SOCF_GLOBAL },
   9774     { UDF_CHUNK_ID_7f, 3, 31, SOCF_LE | SOCF_GLOBAL },
   9775     { UDF_CHUNK_ID_8f, 3, 36, SOCF_LE | SOCF_GLOBAL },
   9776     { UDF_CHUNK_ID_9f, 3, 41, SOCF_LE | SOCF_GLOBAL },
   9777     { UDF_SEL_1f, 1, 4, 0 | SOCF_GLOBAL },
   9778     { UDF_SEL_10f, 1, 49, 0 | SOCF_GLOBAL },
   9779     { UDF_SEL_11f, 1, 54, 0 | SOCF_GLOBAL },
   9780     { UDF_SEL_12f, 1, 59, 0 | SOCF_GLOBAL },
   9781     { UDF_SEL_13f, 1, 64, 0 | SOCF_GLOBAL },
   9782     { UDF_SEL_2f, 1, 9, 0 | SOCF_GLOBAL },
   9783     { UDF_SEL_3f, 1, 14, 0 | SOCF_GLOBAL },
   9784     { UDF_SEL_4f, 1, 19, 0 | SOCF_GLOBAL },
   9785     { UDF_SEL_5f, 1, 24, 0 | SOCF_GLOBAL },
   9786     { UDF_SEL_6f, 1, 29, 0 | SOCF_GLOBAL },
   9787     { UDF_SEL_7f, 1, 34, 0 | SOCF_GLOBAL },
   9788     { UDF_SEL_8f, 1, 39, 0 | SOCF_GLOBAL },
   9789     { UDF_SEL_9f, 1, 44, 0 | SOCF_GLOBAL }
   9790 };
   9791 #endif
   9792 
   9793 #if defined(BCM_88732_A0)
   9794 soc_field_info_t soc_UDF_OFFSETm_fields[] = {
   9795     { BASE_OFFSET0f, 4, 4, SOCF_LE | SOCF_GLOBAL },
   9796     { BASE_OFFSET1f, 4, 12, SOCF_LE | SOCF_GLOBAL },
   9797     { BASE_OFFSET2f, 4, 20, SOCF_LE | SOCF_GLOBAL },
   9798     { BASE_OFFSET3f, 4, 28, SOCF_LE | SOCF_GLOBAL },
   9799     { BASE_OFFSET4f, 4, 36, SOCF_LE | SOCF_GLOBAL },
   9800     { BASE_OFFSET5f, 4, 44, SOCF_LE | SOCF_GLOBAL },
   9801     { BASE_OFFSET6f, 4, 52, SOCF_LE | SOCF_GLOBAL },
   9802     { BASE_OFFSET7f, 4, 60, SOCF_LE | SOCF_GLOBAL },
   9803     { ECCf, 7, 76, SOCF_LE | SOCF_GLOBAL },
   9804     { ECCPf, 8, 76, SOCF_LE | SOCF_GLOBAL },
   9805     { OFFSET_VALUE0f, 4, 0, SOCF_LE | SOCF_GLOBAL },
   9806     { OFFSET_VALUE1f, 4, 8, SOCF_LE | SOCF_GLOBAL },
   9807     { OFFSET_VALUE2f, 4, 16, SOCF_LE | SOCF_GLOBAL },
   9808     { OFFSET_VALUE3f, 4, 24, SOCF_LE | SOCF_GLOBAL },
   9809     { OFFSET_VALUE4f, 4, 32, SOCF_LE | SOCF_GLOBAL },
   9810     { OFFSET_VALUE5f, 4, 40, SOCF_LE | SOCF_GLOBAL },
   9811     { OFFSET_VALUE6f, 4, 48, SOCF_LE | SOCF_GLOBAL },
   9812     { OFFSET_VALUE7f, 4, 56, SOCF_LE | SOCF_GLOBAL },
   9813     { PARITYf, 1, 83, 0 | SOCF_GLOBAL },
   9814     { PORT_FIELD_SEL_INDEX0f, 6, 64, SOCF_LE | SOCF_GLOBAL },
   9815     { PORT_FIELD_SEL_INDEX1f, 6, 70, SOCF_LE | SOCF_GLOBAL }
   9816 };
   9817 #endif
   9818 
   9819 #if defined(BCM_88732_A0)
   9820 soc_field_info_t soc_UFLOW_Am_fields[] = {
   9821     { AGED_INDICATORf, 1, 14, 0 | SOCF_GLOBAL },
   9822     { DEST_PORT_OFFSETf, 4, 0, SOCF_LE | SOCF_GLOBAL },
   9823     { ECCf, 5, 16, SOCF_LE | SOCF_GLOBAL },
   9824     { ECCPf, 6, 16, SOCF_LE | SOCF_GLOBAL },
   9825     { PARITYf, 1, 21, 0 | SOCF_GLOBAL },
   9826     { PHASEf, 1, 15, 0 | SOCF_GLOBAL },
   9827     { TIMERf, 10, 4, SOCF_LE | SOCF_GLOBAL }
   9828 };
   9829 #endif
   9830 
   9831 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   9832     defined(BCM_56870_A0)
   9833 soc_field_info_t soc_UFT_EXTRACTION_CTRL_ID_PROFILEm_fields[] = {
   9834     { EXTRACTION_CTRL_ID_ACTIONf, 16, 0, SOCF_LE | SOCF_GLOBAL }
   9835 };
   9836 #endif
   9837 
   9838 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
   9839 soc_field_info_t soc_UFT_SHARED_BANKS_CONTROLm_fields[] = {
   9840     { ALPM_ADDRESS_SWIZZLE_MODEf, 1, 30, 0 | SOCF_GLOBAL },
   9841     { ALPM_MODEf, 1, 29, 0 | SOCF_GLOBAL },
   9842     { B0_HASH_OFFSETf, 6, 31, SOCF_LE | SOCF_GLOBAL },
   9843     { B1_HASH_OFFSETf, 6, 37, SOCF_LE | SOCF_GLOBAL },
   9844     { B2_HASH_OFFSETf, 6, 43, SOCF_LE | SOCF_GLOBAL },
   9845     { B3_HASH_OFFSETf, 6, 49, SOCF_LE | SOCF_GLOBAL },
   9846     { B4_HASH_OFFSETf, 6, 55, SOCF_LE | SOCF_GLOBAL },
   9847     { B5_HASH_OFFSETf, 6, 61, SOCF_LE | SOCF_GLOBAL },
   9848     { B6_HASH_OFFSETf, 6, 67, SOCF_LE | SOCF_GLOBAL },
   9849     { B7_HASH_OFFSETf, 6, 73, SOCF_LE | SOCF_GLOBAL },
   9850     { BANK_BYPASS_LPf, 8, 0, SOCF_LE | SOCF_GLOBAL },
   9851     { BANK_DISABLE_LPf, 8, 8, SOCF_LE | SOCF_GLOBAL },
   9852     { BANK_XOR_3WR_ENf, 8, 16, SOCF_LE | SOCF_GLOBAL },
   9853     { DISABLE_XOR_WRITEf, 1, 28, 0 | SOCF_GLOBAL },
   9854     { FORCE_XOR_GENf, 1, 27, 0 | SOCF_GLOBAL },
   9855     { LANE0_BYPASS_LPf, 1, 24, 0 | SOCF_GLOBAL },
   9856     { LANE1_BYPASS_LPf, 1, 25, 0 | SOCF_GLOBAL },
   9857     { LANE2_BYPASS_LPf, 1, 26, 0 | SOCF_GLOBAL }
   9858 };
   9859 #endif
   9860 
   9861 #if defined(BCM_56370_A0)
   9862 soc_field_info_t soc_UFT_SHARED_BANKS_CONTROL_BCM56370_A0m_fields[] = {
   9863     { ALPM_ADDRESS_SWIZZLE_MODEf, 1, 30, 0 | SOCF_GLOBAL },
   9864     { ALPM_MODEf, 1, 29, 0 | SOCF_GLOBAL },
   9865     { B0_HASH_OFFSETf, 6, 31, SOCF_LE | SOCF_GLOBAL },
   9866     { B1_HASH_OFFSETf, 6, 37, SOCF_LE | SOCF_GLOBAL },
   9867     { B2_HASH_OFFSETf, 6, 43, SOCF_LE | SOCF_GLOBAL },
   9868     { B3_HASH_OFFSETf, 6, 49, SOCF_LE | SOCF_GLOBAL },
   9869     { B4_HASH_OFFSETf, 6, 55, SOCF_LE | SOCF_GLOBAL },
   9870     { B5_HASH_OFFSETf, 6, 61, SOCF_LE | SOCF_GLOBAL },
   9871     { BANK_BYPASS_LPf, 8, 0, SOCF_LE | SOCF_GLOBAL },
   9872     { BANK_DISABLE_LPf, 8, 8, SOCF_LE | SOCF_GLOBAL },
   9873     { BANK_XOR_3WR_ENf, 8, 16, SOCF_LE | SOCF_GLOBAL },
   9874     { DISABLE_XOR_WRITEf, 1, 28, 0 | SOCF_GLOBAL },
   9875     { FORCE_XOR_GENf, 1, 27, 0 | SOCF_GLOBAL },
   9876     { LANE0_BYPASS_LPf, 1, 24, 0 | SOCF_GLOBAL },
   9877     { LANE1_BYPASS_LPf, 1, 25, 0 | SOCF_GLOBAL },
   9878     { LANE2_BYPASS_LPf, 1, 26, 0 | SOCF_GLOBAL }
   9879 };
   9880 #endif
   9881 
   9882 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9883 soc_field_info_t soc_UFT_SHARED_BANKS_CONTROL_BCM56980_A0m_fields[] = {
   9884     { B0_HASH_OFFSETf, 6, 2, SOCF_LE | SOCF_GLOBAL },
   9885     { B1_HASH_OFFSETf, 6, 8, SOCF_LE | SOCF_GLOBAL },
   9886     { B2_HASH_OFFSETf, 6, 14, SOCF_LE | SOCF_GLOBAL },
   9887     { B3_HASH_OFFSETf, 6, 20, SOCF_LE | SOCF_GLOBAL },
   9888     { B4_HASH_OFFSETf, 6, 26, SOCF_LE | SOCF_GLOBAL },
   9889     { B5_HASH_OFFSETf, 6, 32, SOCF_LE | SOCF_GLOBAL },
   9890     { B6_HASH_OFFSETf, 6, 38, SOCF_LE | SOCF_GLOBAL },
   9891     { B7_HASH_OFFSETf, 6, 44, SOCF_LE | SOCF_GLOBAL },
   9892     { DISABLE_XOR_WRITEf, 1, 1, 0 | SOCF_GLOBAL },
   9893     { FORCE_XOR_GENf, 1, 0, 0 | SOCF_GLOBAL }
   9894 };
   9895 #endif
   9896 
   9897 #if defined(BCM_88690_A0)
   9898 soc_field_info_t soc_UM_TABLEm_fields[] = {
   9899     { UM_DATAf, 49, 0, SOCF_LE | SOCF_GLOBAL }
   9900 };
   9901 #endif
   9902 
   9903 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9904 soc_field_info_t soc_UM_TABLE_BCM56980_A0m_fields[] = {
   9905     { CM_CONTROLf, 8, 40, SOCF_LE | SOCF_GLOBAL },
   9906     { CM_PADf, 8, 24, SOCF_LE | SOCF_GLOBAL },
   9907     { RSVDf, 1, 48, SOCF_RES | SOCF_GLOBAL },
   9908     { UMf, 24, 0, SOCF_LE | SOCF_GLOBAL },
   9909     { UM_DATAf, 49, 0, SOCF_LE | SOCF_GLOBAL },
   9910     { UM_PADf, 8, 32, SOCF_LE | SOCF_GLOBAL }
   9911 };
   9912 #endif
   9913 
   9914 #if defined(BCM_88690_B0)
   9915 soc_field_info_t soc_UM_TABLE_BCM88690_B0m_fields[] = {
   9916     { UM_DATAf, 49, 0, SOCF_LE | SOCF_GLOBAL }
   9917 };
   9918 #endif
   9919 
   9920 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   9921     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   9922 soc_field_info_t soc_UDF_BASE_OFFSET_ENCODINGfmt_fields[] = {
   9923     { BASE_OFFSETf, 3, 0, SOCF_LE }
   9924 };
   9925 #endif
   9926 
   9927 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
   9928     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
   9929     defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   9930     defined(BCM_56860_A0)
   9931 soc_field_info_t soc_UDF_BASE_OFFSET_ENCODING_BCM56640_A0fmt_fields[] = {
   9932     { BASE_OFFSETf, 3, 0, SOCF_LE }
   9933 };
   9934 #endif
   9935 
   9936 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   9937     defined(BCM_56270_A0) || defined(BCM_56370_A0) || \
   9938     defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   9939     defined(BCM_56670_A0) || defined(BCM_56670_B0) || \
   9940     defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9941     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   9942     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   9943     defined(BCM_56980_B0)
   9944 soc_field_info_t soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields[] = {
   9945     { BASE_OFFSETf, 3, 0, SOCF_LE }
   9946 };
   9947 #endif
   9948 
   9949 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9950     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   9951     defined(BCM_56970_A0)
   9952 soc_field_info_t soc_UDF_TCAM_KEYfmt_fields[] = {
   9953     { CNTAG_PRESENTf, 1, 63, 0 },
   9954     { ETAG_PACKETf, 1, 70, 0 },
   9955     { FC_HDR_ENCODE_1f, 3, 67, SOCF_LE },
   9956     { FC_HDR_ENCODE_2f, 3, 64, SOCF_LE },
   9957     { HIGIGf, 1, 48, 0 },
   9958     { INNER_IP_TYPEf, 3, 0, SOCF_LE },
   9959     { L2_ETHER_TYPEf, 16, 30, SOCF_LE },
   9960     { L2_TAG_STATUSf, 2, 46, SOCF_LE },
   9961     { L2_TYPEf, 2, 49, SOCF_LE },
   9962     { L3_FIELDSf, 24, 6, SOCF_LE },
   9963     { LOOPBACK_PKT_TYPEf, 3, 51, SOCF_LE },
   9964     { OUTER_IP_TYPEf, 3, 3, SOCF_LE },
   9965     { RESERVEDf, 9, 71, SOCF_LE|SOCF_RES },
   9966     { SOURCE_PORT_NUMBERf, 8, 54, SOCF_LE },
   9967     { VNTAG_PRESENTf, 1, 62, 0 }
   9968 };
   9969 #endif
   9970 
   9971 #if defined(BCM_56370_A0)
   9972 soc_field_info_t soc_UDF_TCAM_KEY_BCM56370_A0fmt_fields[] = {
   9973     { CNTAG_PRESENTf, 1, 63, 0 },
   9974     { ETAG_PACKETf, 1, 70, 0 },
   9975     { FC_HDR_ENCODE_1f, 3, 67, SOCF_LE },
   9976     { FC_HDR_ENCODE_2f, 3, 64, SOCF_LE },
   9977     { HIGIGf, 1, 48, 0 },
   9978     { INNER_IP_TYPEf, 3, 0, SOCF_LE },
   9979     { L2_ETHER_TYPEf, 16, 30, SOCF_LE },
   9980     { L2_TAG_STATUSf, 2, 46, SOCF_LE },
   9981     { L2_TYPEf, 2, 49, SOCF_LE },
   9982     { L3_FIELDSf, 24, 6, SOCF_LE },
   9983     { LOOPBACK_PKT_TYPEf, 3, 51, SOCF_LE },
   9984     { OUTER_IP_TYPEf, 3, 3, SOCF_LE },
   9985     { RESERVEDf, 9, 71, SOCF_LE|SOCF_RES },
   9986     { RESERVED_SOURCE_PORT_NUMBERf, 1, 133, SOCF_RES },
   9987     { SOURCE_PORT_NUMBERf, 79, 54, SOCF_LE },
   9988     { VNTAG_PRESENTf, 1, 62, 0 }
   9989 };
   9990 #endif
   9991 
   9992 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9993 soc_field_info_t soc_UDF_TCAM_KEY_BCM56980_A0fmt_fields[] = {
   9994     { INNER_IP_TYPEf, 3, 0, SOCF_LE },
   9995     { INT_PKTf, 1, 3, 0 },
   9996     { L2_ETHER_TYPEf, 16, 4, SOCF_LE },
   9997     { L2_TAG_STATUSf, 1, 20, 0 },
   9998     { L2_TYPEf, 2, 21, SOCF_LE },
   9999     { L3_FIELDSf, 24, 23, SOCF_LE },
  10000     { L4_DST_PORTf, 16, 47, SOCF_LE },
  10001     { LOOPBACK_PKT_TYPEf, 2, 63, SOCF_LE },
  10002     { MODULE_HDR_PRESENTf, 1, 65, 0 },
  10003     { OPAQUE_TAG_TYPEf, 2, 66, SOCF_LE },
  10004     { OUTER_IP_TYPEf, 3, 68, SOCF_LE },
  10005     { RESERVEDf, 1, 71, SOCF_RES },
  10006     { SOURCE_PORT_NUMBERf, 8, 72, SOCF_LE }
  10007 };
  10008 #endif
  10009 
  10010 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  10011     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10012     defined(BCM_56450_B1) || defined(BCM_56640_A0) || \
  10013     defined(BCM_56850_A0) || defined(BCM_56860_A0)
  10014 soc_field_info_t soc_UDP_HDRfmt_fields[] = {
  10015     { CHECKSUMf, 16, 48, SOCF_LE },
  10016     { DST_PORTf, 16, 16, SOCF_LE },
  10017     { LENGTHf, 16, 32, SOCF_LE },
  10018     { SRC_PORTf, 16, 0, SOCF_LE }
  10019 };
  10020 #endif
  10021 
  10022 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  10023     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  10024     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  10025     defined(BCM_56260_B0) || defined(BCM_56270_A0) || \
  10026     defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  10027     defined(BCM_56670_A0) || defined(BCM_56670_B0) || \
  10028     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  10029     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  10030     defined(BCM_56980_B0)
  10031 soc_field_info_t soc_UDP_HDR_BCM53400_A0fmt_fields[] = {
  10032     { CHECKSUMf, 16, 48, SOCF_LE },
  10033     { DST_PORTf, 16, 16, SOCF_LE },
  10034     { LENGTHf, 16, 32, SOCF_LE },
  10035     { SRC_PORTf, 16, 0, SOCF_LE }
  10036 };
  10037 #endif
  10038 
  10039 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  10040     defined(BCM_56870_A0)
  10041 soc_field_info_t soc_UDP_HDR_BCM56870_A0fmt_fields[] = {
  10042     { CHECKSUMf, 16, 0, SOCF_LE },
  10043     { DST_PORTf, 16, 32, SOCF_LE },
  10044     { LENGTHf, 16, 16, SOCF_LE },
  10045     { SRC_PORTf, 16, 48, SOCF_LE }
  10046 };
  10047 #endif
  10048