openbcm

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allregs_x.i (2056072B)

      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_x.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
     16     defined(BCM_56504_B0) || defined(BCM_56514_A0)
     17     { /* SOC_REG_INT_XBOD_OVRFLWr */
     18         soc_block_list[0],
     19         soc_genreg,
     20         1,
     21         0,
     22         0x80020,
     23         SOC_REG_FLAG_RO,
     24         0,
     25         1,
     26         soc_GE0_GBOD_OVRFLWr_fields,
     27         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     28         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
     29         -1,
     30         -1,
     31     },
     32 #endif /* chips */
     33 
     34 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
     35     defined(BCM_56334_B0)
     36     { /* SOC_REG_INT_XBOD_OVRFLW_BCM56334_A0r */
     37         soc_block_list[14],
     38         soc_portreg,
     39         1,
     40         0,
     41         0x823,
     42         SOC_REG_FLAG_RO,
     43         0,
     44         1,
     45         soc_GE0_GBOD_OVRFLWr_fields,
     46         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     47         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
     48         -1,
     49         -1,
     50     },
     51 #endif /* chips */
     52 
     53 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
     54     defined(BCM_56680_A0) || defined(BCM_56680_B0)
     55     { /* SOC_REG_INT_XBOD_OVRFLW_BCM56624_A0r */
     56         soc_block_list[204],
     57         soc_portreg,
     58         1,
     59         0,
     60         0x823,
     61         SOC_REG_FLAG_RO,
     62         0,
     63         1,
     64         soc_GE0_GBOD_OVRFLWr_fields,
     65         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     66         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
     67         -1,
     68         -1,
     69     },
     70 #endif /* chips */
     71 
     72 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
     73     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
     74     defined(BCM_56685_A0) || defined(BCM_56685_B0)
     75     { /* SOC_REG_INT_XBOD_OVRFLW_BCM56634_A0r */
     76         soc_block_list[208],
     77         soc_portreg,
     78         1,
     79         0,
     80         0x823,
     81         SOC_REG_FLAG_RO,
     82         0,
     83         1,
     84         soc_GE0_GBOD_OVRFLWr_fields,
     85         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     86         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
     87         -1,
     88         -1,
     89     },
     90 #endif /* chips */
     91 
     92 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
     93     defined(BCM_56820_A0)
     94     { /* SOC_REG_INT_XBOD_OVRFLW_BCM56800_A0r */
     95         soc_block_list[9],
     96         soc_portreg,
     97         1,
     98         0,
     99         0x823,
    100         SOC_REG_FLAG_RO,
    101         0,
    102         1,
    103         soc_GE0_GBOD_OVRFLWr_fields,
    104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    105         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    106         -1,
    107         -1,
    108     },
    109 #endif /* chips */
    110 
    111 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    112     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    113     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    114     { /* SOC_REG_INT_XCON_CCM_DEFECT_STATUSr */
    115         soc_block_list[5],
    116         soc_genreg,
    117         1,
    118         0,
    119         0xa080016,
    120         0,
    121         0,
    122         3,
    123         soc_ERROR_CCM_DEFECT_STATUSr_fields,
    124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    125         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
    126         -1,
    127         -1,
    128     },
    129 #endif /* chips */
    130 
    131 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
    132     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
    133     defined(BCM_56160_A0)
    134     { /* SOC_REG_INT_XCON_CCM_DEFECT_STATUS_BCM53400_A0r */
    135         soc_block_list[5],
    136         soc_genreg,
    137         1,
    138         0,
    139         0x32000400,
    140         0,
    141         0,
    142         3,
    143         soc_ERROR_CCM_DEFECT_STATUS_BCM53400_A0r_fields,
    144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    145         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    146         -1,
    147         -1,
    148     },
    149 #endif /* chips */
    150 
    151 #if defined(BCM_56150_A0)
    152     { /* SOC_REG_INT_XCON_CCM_DEFECT_STATUS_BCM56150_A0r */
    153         soc_block_list[5],
    154         soc_genreg,
    155         1,
    156         0,
    157         0x36000400,
    158         0,
    159         0,
    160         3,
    161         soc_ERROR_CCM_DEFECT_STATUS_BCM56150_A0r_fields,
    162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    163         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    164         -1,
    165         -1,
    166     },
    167 #endif /* chips */
    168 
    169 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
    170     defined(BCM_56270_A0)
    171     { /* SOC_REG_INT_XCON_CCM_DEFECT_STATUS_BCM56260_A0r */
    172         soc_block_list[5],
    173         soc_genreg,
    174         1,
    175         0,
    176         0x2e000e00,
    177         0,
    178         0,
    179         3,
    180         soc_ERROR_CCM_DEFECT_STATUS_BCM56260_A0r_fields,
    181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    182         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    183         -1,
    184         -1,
    185     },
    186 #endif /* chips */
    187 
    188 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
    189     { /* SOC_REG_INT_XCON_CCM_DEFECT_STATUS_BCM56334_A0r */
    190         soc_block_list[5],
    191         soc_genreg,
    192         1,
    193         0,
    194         0xd080016,
    195         0,
    196         0,
    197         4,
    198         soc_XCON_CCM_DEFECT_STATUSr_fields,
    199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    200         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    201         -1,
    202         -1,
    203     },
    204 #endif /* chips */
    205 
    206 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    207     { /* SOC_REG_INT_XCON_CCM_DEFECT_STATUS_BCM56440_A0r */
    208         soc_block_list[5],
    209         soc_genreg,
    210         1,
    211         0,
    212         0xb08060e,
    213         0,
    214         0,
    215         3,
    216         soc_ERROR_CCM_DEFECT_STATUS_BCM56440_A0r_fields,
    217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    218         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    219         -1,
    220         -1,
    221     },
    222 #endif /* chips */
    223 
    224 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    225     defined(BCM_56450_B1)
    226     { /* SOC_REG_INT_XCON_CCM_DEFECT_STATUS_BCM56450_A0r */
    227         soc_block_list[5],
    228         soc_genreg,
    229         1,
    230         0,
    231         0x2e000e00,
    232         0,
    233         0,
    234         3,
    235         soc_ERROR_CCM_DEFECT_STATUS_BCM56640_A0r_fields,
    236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    237         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
    238         -1,
    239         -1,
    240     },
    241 #endif /* chips */
    242 
    243 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    244     { /* SOC_REG_INT_XCON_CCM_DEFECT_STATUS_BCM56640_A0r */
    245         soc_block_list[5],
    246         soc_genreg,
    247         1,
    248         0,
    249         0x2a000800,
    250         0,
    251         0,
    252         3,
    253         soc_ERROR_CCM_DEFECT_STATUS_BCM56640_A0r_fields,
    254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    255         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
    256         -1,
    257         -1,
    258     },
    259 #endif /* chips */
    260 
    261 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    262     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    263     { /* SOC_REG_INT_XGPORT_EXTRA_XGXS_NEWCTL_REGr */
    264         soc_block_list[11],
    265         soc_genreg,
    266         1,
    267         0,
    268         0x80d05,
    269         0,
    270         0,
    271         1,
    272         soc_XGPORT_EXTRA_XGXS_NEWCTL_REGr_fields,
    273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    274         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    275         -1,
    276         -1,
    277     },
    278 #endif /* chips */
    279 
    280 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    281     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    282     { /* SOC_REG_INT_XGPORT_EXTRA_XGXS_NEWSTATUS0_REGr */
    283         soc_block_list[11],
    284         soc_genreg,
    285         1,
    286         0,
    287         0x80d0a,
    288         SOC_REG_FLAG_RO,
    289         0,
    290         8,
    291         soc_XGPORT_EXTRA_XGXS_NEWSTATUS0_REGr_fields,
    292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    293         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    294         -1,
    295         -1,
    296     },
    297 #endif /* chips */
    298 
    299 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    300     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    301     { /* SOC_REG_INT_XGPORT_EXTRA_XGXS_NEWSTATUS1_REGr */
    302         soc_block_list[11],
    303         soc_genreg,
    304         1,
    305         0,
    306         0x80d0b,
    307         SOC_REG_FLAG_RO,
    308         0,
    309         8,
    310         soc_XGPORT_EXTRA_XGXS_NEWSTATUS1_REGr_fields,
    311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    312         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    313         -1,
    314         -1,
    315     },
    316 #endif /* chips */
    317 
    318 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    319     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    320     { /* SOC_REG_INT_XGPORT_EXTRA_XGXS_NEWSTATUS2_REGr */
    321         soc_block_list[11],
    322         soc_genreg,
    323         1,
    324         0,
    325         0x80d0c,
    326         SOC_REG_FLAG_RO,
    327         0,
    328         8,
    329         soc_XGPORT_EXTRA_XGXS_NEWSTATUS2_REGr_fields,
    330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    331         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    332         -1,
    333         -1,
    334     },
    335 #endif /* chips */
    336 
    337 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    338     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    339     { /* SOC_REG_INT_XGPORT_EXTRA_XGXS_NEWSTATUS3_REGr */
    340         soc_block_list[11],
    341         soc_genreg,
    342         1,
    343         0,
    344         0x80d0d,
    345         SOC_REG_FLAG_RO,
    346         0,
    347         2,
    348         soc_XGPORT_EXTRA_XGXS_NEWSTATUS3_REGr_fields,
    349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    350         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    351         -1,
    352         -1,
    353     },
    354 #endif /* chips */
    355 
    356 #if defined(BCM_56624_A0) || defined(BCM_56680_A0)
    357     { /* SOC_REG_INT_XGPORT_MODE_REGr */
    358         soc_block_list[11],
    359         soc_genreg,
    360         1,
    361         0,
    362         0x80d00,
    363         0,
    364         0,
    365         1,
    366         soc_XGPORT_MODE_REGr_fields,
    367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    368         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    369         -1,
    370         -1,
    371     },
    372 #endif /* chips */
    373 
    374 #if defined(BCM_56624_B0) || defined(BCM_56680_B0)
    375     { /* SOC_REG_INT_XGPORT_MODE_REG_BCM56624_B0r */
    376         soc_block_list[11],
    377         soc_genreg,
    378         1,
    379         0,
    380         0x80d00,
    381         0,
    382         0,
    383         1,
    384         soc_XGPORT_MODE_REG_BCM56624_B0r_fields,
    385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    386         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    387         -1,
    388         -1,
    389     },
    390 #endif /* chips */
    391 
    392 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    393     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    394     { /* SOC_REG_INT_XGPORT_SERDES_CTLr */
    395         soc_block_list[11],
    396         soc_genreg,
    397         1,
    398         0,
    399         0x80d03,
    400         0,
    401         0,
    402         1,
    403         soc_XGPORT_SERDES_CTLr_fields,
    404         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
    405         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
    406         -1,
    407         -1,
    408     },
    409 #endif /* chips */
    410 
    411 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    412     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    413     { /* SOC_REG_INT_XGPORT_XGXS_CTRLr */
    414         soc_block_list[11],
    415         soc_genreg,
    416         1,
    417         0,
    418         0x80d01,
    419         0,
    420         0,
    421         11,
    422         soc_MAC_XGXS_CTRL_BCM56800_A0r_fields,
    423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    424         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    425         -1,
    426         -1,
    427     },
    428 #endif /* chips */
    429 
    430 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    431     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    432     { /* SOC_REG_INT_XGPORT_XGXS_NEWCTL_REGr */
    433         soc_block_list[11],
    434         soc_genreg,
    435         1,
    436         0,
    437         0x80d04,
    438         0,
    439         0,
    440         1,
    441         soc_XGPORT_EXTRA_XGXS_NEWCTL_REGr_fields,
    442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    443         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    444         -1,
    445         -1,
    446     },
    447 #endif /* chips */
    448 
    449 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    450     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    451     { /* SOC_REG_INT_XGPORT_XGXS_NEWSTATUS0_REGr */
    452         soc_block_list[11],
    453         soc_genreg,
    454         1,
    455         0,
    456         0x80d06,
    457         SOC_REG_FLAG_RO,
    458         0,
    459         8,
    460         soc_XGPORT_EXTRA_XGXS_NEWSTATUS0_REGr_fields,
    461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    462         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    463         -1,
    464         -1,
    465     },
    466 #endif /* chips */
    467 
    468 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    469     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    470     { /* SOC_REG_INT_XGPORT_XGXS_NEWSTATUS1_REGr */
    471         soc_block_list[11],
    472         soc_genreg,
    473         1,
    474         0,
    475         0x80d07,
    476         SOC_REG_FLAG_RO,
    477         0,
    478         8,
    479         soc_XGPORT_EXTRA_XGXS_NEWSTATUS1_REGr_fields,
    480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    481         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    482         -1,
    483         -1,
    484     },
    485 #endif /* chips */
    486 
    487 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    488     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    489     { /* SOC_REG_INT_XGPORT_XGXS_NEWSTATUS2_REGr */
    490         soc_block_list[11],
    491         soc_genreg,
    492         1,
    493         0,
    494         0x80d08,
    495         SOC_REG_FLAG_RO,
    496         0,
    497         8,
    498         soc_XGPORT_EXTRA_XGXS_NEWSTATUS2_REGr_fields,
    499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    500         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    501         -1,
    502         -1,
    503     },
    504 #endif /* chips */
    505 
    506 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    507     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    508     { /* SOC_REG_INT_XGPORT_XGXS_NEWSTATUS3_REGr */
    509         soc_block_list[11],
    510         soc_genreg,
    511         1,
    512         0,
    513         0x80d09,
    514         SOC_REG_FLAG_RO,
    515         0,
    516         2,
    517         soc_XGPORT_EXTRA_XGXS_NEWSTATUS3_REGr_fields,
    518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    519         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    520         -1,
    521         -1,
    522     },
    523 #endif /* chips */
    524 
    525 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    526     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    527     { /* SOC_REG_INT_XGPORT_XGXS_STATr */
    528         soc_block_list[11],
    529         soc_genreg,
    530         1,
    531         0,
    532         0x80d02,
    533         SOC_REG_FLAG_RO,
    534         0,
    535         22,
    536         soc_MAC_XGXS_STAT_BCM56800_A0r_fields,
    537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    539         -1,
    540         -1,
    541     },
    542 #endif /* chips */
    543 
    544 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
    545     defined(BCM_56504_B0) || defined(BCM_56514_A0)
    546     { /* SOC_REG_INT_XHOL_D0r */
    547         soc_block_list[0],
    548         soc_genreg,
    549         1,
    550         0,
    551         0x8000e,
    552         0,
    553         0,
    554         1,
    555         soc_XHOL_D0r_fields,
    556         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    557         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    558         -1,
    559         -1,
    560     },
    561 #endif /* chips */
    562 
    563 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
    564     defined(BCM_56504_B0) || defined(BCM_56514_A0)
    565     { /* SOC_REG_INT_XHOL_D1r */
    566         soc_block_list[0],
    567         soc_genreg,
    568         1,
    569         0,
    570         0x8000f,
    571         0,
    572         0,
    573         1,
    574         soc_XHOL_D1r_fields,
    575         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
    576         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    577         -1,
    578         -1,
    579     },
    580 #endif /* chips */
    581 
    582 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
    583     defined(BCM_56504_B0) || defined(BCM_56514_A0)
    584     { /* SOC_REG_INT_XHOL_D2r */
    585         soc_block_list[0],
    586         soc_genreg,
    587         1,
    588         0,
    589         0x80010,
    590         0,
    591         0,
    592         1,
    593         soc_XHOL_D2r_fields,
    594         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
    595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    596         -1,
    597         -1,
    598     },
    599 #endif /* chips */
    600 
    601 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
    602     defined(BCM_56504_B0) || defined(BCM_56514_A0)
    603     { /* SOC_REG_INT_XHOL_D3r */
    604         soc_block_list[0],
    605         soc_genreg,
    606         1,
    607         0,
    608         0x80011,
    609         0,
    610         0,
    611         1,
    612         soc_XHOL_D3r_fields,
    613         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
    614         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    615         -1,
    616         -1,
    617     },
    618 #endif /* chips */
    619 
    620 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
    621     defined(BCM_56334_B0)
    622     { /* SOC_REG_INT_XHOL_D0_BCM56334_A0r */
    623         soc_block_list[14],
    624         soc_portreg,
    625         1,
    626         0,
    627         0x810,
    628         0,
    629         0,
    630         1,
    631         soc_XHOL_D0r_fields,
    632         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    633         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    634         -1,
    635         -1,
    636     },
    637 #endif /* chips */
    638 
    639 #if defined(BCM_56340_A0)
    640     { /* SOC_REG_INT_XHOL_D0_BCM56340_A0r */
    641         soc_block_list[214],
    642         soc_portreg,
    643         1,
    644         0,
    645         0x23000,
    646         0,
    647         0,
    648         1,
    649         soc_XHOL_D0_BCM56640_A0r_fields,
    650         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    651         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    652         -1,
    653         -1,
    654     },
    655 #endif /* chips */
    656 
    657 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    658     { /* SOC_REG_INT_XHOL_D0_BCM56440_A0r */
    659         soc_block_list[83],
    660         soc_genreg,
    661         1,
    662         0,
    663         0x80229,
    664         0,
    665         0,
    666         1,
    667         soc_XHOL_D0r_fields,
    668         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    670         -1,
    671         -1,
    672     },
    673 #endif /* chips */
    674 
    675 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    676     defined(BCM_56450_B1)
    677     { /* SOC_REG_INT_XHOL_D0_BCM56450_A0r */
    678         soc_block_list[83],
    679         soc_genreg,
    680         1,
    681         0,
    682         0x2022900,
    683         0,
    684         0,
    685         1,
    686         soc_XHOL_D0_BCM56640_A0r_fields,
    687         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    689         -1,
    690         -1,
    691     },
    692 #endif /* chips */
    693 
    694 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    695     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    696     { /* SOC_REG_INT_XHOL_D0_BCM56624_A0r */
    697         soc_block_list[204],
    698         soc_portreg,
    699         1,
    700         0,
    701         0x810,
    702         0,
    703         0,
    704         1,
    705         soc_XHOL_D0r_fields,
    706         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    708         -1,
    709         -1,
    710     },
    711 #endif /* chips */
    712 
    713 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    714     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    715     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    716     { /* SOC_REG_INT_XHOL_D0_BCM56634_A0r */
    717         soc_block_list[208],
    718         soc_portreg,
    719         1,
    720         0,
    721         0x810,
    722         0,
    723         0,
    724         1,
    725         soc_XHOL_D0r_fields,
    726         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    727         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    728         -1,
    729         -1,
    730     },
    731 #endif /* chips */
    732 
    733 #if defined(BCM_56640_A0)
    734     { /* SOC_REG_INT_XHOL_D0_BCM56640_A0r */
    735         soc_block_list[212],
    736         soc_portreg,
    737         1,
    738         0,
    739         0x23000,
    740         0,
    741         0,
    742         1,
    743         soc_XHOL_D0_BCM56640_A0r_fields,
    744         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    745         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    746         -1,
    747         -1,
    748     },
    749 #endif /* chips */
    750 
    751 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
    752     defined(BCM_56820_A0)
    753     { /* SOC_REG_INT_XHOL_D0_BCM56800_A0r */
    754         soc_block_list[9],
    755         soc_portreg,
    756         1,
    757         0,
    758         0x810,
    759         0,
    760         0,
    761         1,
    762         soc_XHOL_D0r_fields,
    763         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    764         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    765         -1,
    766         -1,
    767     },
    768 #endif /* chips */
    769 
    770 #if defined(BCM_56840_A0)
    771     { /* SOC_REG_INT_XHOL_D0_BCM56840_A0r */
    772         soc_block_list[16],
    773         soc_genreg,
    774         1,
    775         0,
    776         0x80233,
    777         0,
    778         0,
    779         1,
    780         soc_XHOL_D0r_fields,
    781         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    782         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    783         -1,
    784         -1,
    785     },
    786 #endif /* chips */
    787 
    788 #if defined(BCM_56840_B0)
    789     { /* SOC_REG_INT_XHOL_D0_BCM56840_B0r */
    790         soc_block_list[16],
    791         soc_genreg,
    792         1,
    793         0,
    794         0x80233,
    795         0,
    796         0,
    797         1,
    798         soc_XHOL_D0r_fields,
    799         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    800         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    801         -1,
    802         -1,
    803     },
    804 #endif /* chips */
    805 
    806 #if defined(BCM_88732_A0)
    807     { /* SOC_REG_INT_XHOL_D0_BCM88732_A0r */
    808         soc_block_list[16],
    809         soc_genreg,
    810         1,
    811         0,
    812         0x80233,
    813         0,
    814         0,
    815         1,
    816         soc_XHOL_D0r_fields,
    817         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
    818         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    819         -1,
    820         -1,
    821     },
    822 #endif /* chips */
    823 
    824 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
    825     defined(BCM_56334_B0)
    826     { /* SOC_REG_INT_XHOL_D1_BCM56334_A0r */
    827         soc_block_list[14],
    828         soc_portreg,
    829         1,
    830         0,
    831         0x811,
    832         0,
    833         0,
    834         1,
    835         soc_XHOL_D1r_fields,
    836         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
    837         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    838         -1,
    839         -1,
    840     },
    841 #endif /* chips */
    842 
    843 #if defined(BCM_56340_A0)
    844     { /* SOC_REG_INT_XHOL_D1_BCM56340_A0r */
    845         soc_block_list[214],
    846         soc_portreg,
    847         1,
    848         0,
    849         0x23100,
    850         0,
    851         0,
    852         1,
    853         soc_XHOL_D1_BCM56640_A0r_fields,
    854         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
    855         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    856         -1,
    857         -1,
    858     },
    859 #endif /* chips */
    860 
    861 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    862     { /* SOC_REG_INT_XHOL_D1_BCM56440_A0r */
    863         soc_block_list[83],
    864         soc_genreg,
    865         1,
    866         0,
    867         0x8022a,
    868         0,
    869         0,
    870         1,
    871         soc_XHOL_D1r_fields,
    872         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
    873         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    874         -1,
    875         -1,
    876     },
    877 #endif /* chips */
    878 
    879 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    880     defined(BCM_56450_B1)
    881     { /* SOC_REG_INT_XHOL_D1_BCM56450_A0r */
    882         soc_block_list[83],
    883         soc_genreg,
    884         1,
    885         0,
    886         0x2022a00,
    887         0,
    888         0,
    889         1,
    890         soc_XHOL_D1_BCM56640_A0r_fields,
    891         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
    892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    893         -1,
    894         -1,
    895     },
    896 #endif /* chips */
    897 
    898 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    899     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    900     { /* SOC_REG_INT_XHOL_D1_BCM56624_A0r */
    901         soc_block_list[204],
    902         soc_portreg,
    903         1,
    904         0,
    905         0x811,
    906         0,
    907         0,
    908         1,
    909         soc_XHOL_D1r_fields,
    910         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
    911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    912         -1,
    913         -1,
    914     },
    915 #endif /* chips */
    916 
    917 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    918     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    919     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    920     { /* SOC_REG_INT_XHOL_D1_BCM56634_A0r */
    921         soc_block_list[208],
    922         soc_portreg,
    923         1,
    924         0,
    925         0x811,
    926         0,
    927         0,
    928         1,
    929         soc_XHOL_D1r_fields,
    930         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
    931         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    932         -1,
    933         -1,
    934     },
    935 #endif /* chips */
    936 
    937 #if defined(BCM_56640_A0)
    938     { /* SOC_REG_INT_XHOL_D1_BCM56640_A0r */
    939         soc_block_list[212],
    940         soc_portreg,
    941         1,
    942         0,
    943         0x23100,
    944         0,
    945         0,
    946         1,
    947         soc_XHOL_D1_BCM56640_A0r_fields,
    948         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
    949         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    950         -1,
    951         -1,
    952     },
    953 #endif /* chips */
    954 
    955 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
    956     defined(BCM_56820_A0)
    957     { /* SOC_REG_INT_XHOL_D1_BCM56800_A0r */
    958         soc_block_list[9],
    959         soc_portreg,
    960         1,
    961         0,
    962         0x811,
    963         0,
    964         0,
    965         1,
    966         soc_XHOL_D1r_fields,
    967         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
    968         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    969         -1,
    970         -1,
    971     },
    972 #endif /* chips */
    973 
    974 #if defined(BCM_56840_A0)
    975     { /* SOC_REG_INT_XHOL_D1_BCM56840_A0r */
    976         soc_block_list[16],
    977         soc_genreg,
    978         1,
    979         0,
    980         0x80234,
    981         0,
    982         0,
    983         1,
    984         soc_XHOL_D1r_fields,
    985         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
    986         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    987         -1,
    988         -1,
    989     },
    990 #endif /* chips */
    991 
    992 #if defined(BCM_56840_B0)
    993     { /* SOC_REG_INT_XHOL_D1_BCM56840_B0r */
    994         soc_block_list[16],
    995         soc_genreg,
    996         1,
    997         0,
    998         0x80234,
    999         0,
   1000         0,
   1001         1,
   1002         soc_XHOL_D1r_fields,
   1003         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
   1004         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1005         -1,
   1006         -1,
   1007     },
   1008 #endif /* chips */
   1009 
   1010 #if defined(BCM_88732_A0)
   1011     { /* SOC_REG_INT_XHOL_D1_BCM88732_A0r */
   1012         soc_block_list[16],
   1013         soc_genreg,
   1014         1,
   1015         0,
   1016         0x80234,
   1017         0,
   1018         0,
   1019         1,
   1020         soc_XHOL_D1r_fields,
   1021         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
   1022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1023         -1,
   1024         -1,
   1025     },
   1026 #endif /* chips */
   1027 
   1028 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   1029     defined(BCM_56334_B0)
   1030     { /* SOC_REG_INT_XHOL_D2_BCM56334_A0r */
   1031         soc_block_list[14],
   1032         soc_portreg,
   1033         1,
   1034         0,
   1035         0x812,
   1036         0,
   1037         0,
   1038         1,
   1039         soc_XHOL_D2r_fields,
   1040         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   1041         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1042         -1,
   1043         -1,
   1044     },
   1045 #endif /* chips */
   1046 
   1047 #if defined(BCM_56340_A0)
   1048     { /* SOC_REG_INT_XHOL_D2_BCM56340_A0r */
   1049         soc_block_list[214],
   1050         soc_portreg,
   1051         1,
   1052         0,
   1053         0x23200,
   1054         0,
   1055         0,
   1056         1,
   1057         soc_XHOL_D2_BCM56640_A0r_fields,
   1058         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   1059         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1060         -1,
   1061         -1,
   1062     },
   1063 #endif /* chips */
   1064 
   1065 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1066     { /* SOC_REG_INT_XHOL_D2_BCM56440_A0r */
   1067         soc_block_list[83],
   1068         soc_genreg,
   1069         1,
   1070         0,
   1071         0x8022b,
   1072         0,
   1073         0,
   1074         1,
   1075         soc_XHOL_D2r_fields,
   1076         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   1077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1078         -1,
   1079         -1,
   1080     },
   1081 #endif /* chips */
   1082 
   1083 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1084     defined(BCM_56450_B1)
   1085     { /* SOC_REG_INT_XHOL_D2_BCM56450_A0r */
   1086         soc_block_list[83],
   1087         soc_genreg,
   1088         1,
   1089         0,
   1090         0x2022b00,
   1091         0,
   1092         0,
   1093         1,
   1094         soc_XHOL_D2_BCM56640_A0r_fields,
   1095         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   1096         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1097         -1,
   1098         -1,
   1099     },
   1100 #endif /* chips */
   1101 
   1102 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   1103     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   1104     { /* SOC_REG_INT_XHOL_D2_BCM56624_A0r */
   1105         soc_block_list[204],
   1106         soc_portreg,
   1107         1,
   1108         0,
   1109         0x812,
   1110         0,
   1111         0,
   1112         1,
   1113         soc_XHOL_D2r_fields,
   1114         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   1115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1116         -1,
   1117         -1,
   1118     },
   1119 #endif /* chips */
   1120 
   1121 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   1122     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   1123     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   1124     { /* SOC_REG_INT_XHOL_D2_BCM56634_A0r */
   1125         soc_block_list[208],
   1126         soc_portreg,
   1127         1,
   1128         0,
   1129         0x812,
   1130         0,
   1131         0,
   1132         1,
   1133         soc_XHOL_D2r_fields,
   1134         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   1135         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1136         -1,
   1137         -1,
   1138     },
   1139 #endif /* chips */
   1140 
   1141 #if defined(BCM_56640_A0)
   1142     { /* SOC_REG_INT_XHOL_D2_BCM56640_A0r */
   1143         soc_block_list[212],
   1144         soc_portreg,
   1145         1,
   1146         0,
   1147         0x23200,
   1148         0,
   1149         0,
   1150         1,
   1151         soc_XHOL_D2_BCM56640_A0r_fields,
   1152         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   1153         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1154         -1,
   1155         -1,
   1156     },
   1157 #endif /* chips */
   1158 
   1159 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   1160     defined(BCM_56820_A0)
   1161     { /* SOC_REG_INT_XHOL_D2_BCM56800_A0r */
   1162         soc_block_list[9],
   1163         soc_portreg,
   1164         1,
   1165         0,
   1166         0x812,
   1167         0,
   1168         0,
   1169         1,
   1170         soc_XHOL_D2r_fields,
   1171         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   1172         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1173         -1,
   1174         -1,
   1175     },
   1176 #endif /* chips */
   1177 
   1178 #if defined(BCM_56840_A0)
   1179     { /* SOC_REG_INT_XHOL_D2_BCM56840_A0r */
   1180         soc_block_list[16],
   1181         soc_genreg,
   1182         1,
   1183         0,
   1184         0x80235,
   1185         0,
   1186         0,
   1187         1,
   1188         soc_XHOL_D2r_fields,
   1189         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   1190         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1191         -1,
   1192         -1,
   1193     },
   1194 #endif /* chips */
   1195 
   1196 #if defined(BCM_56840_B0)
   1197     { /* SOC_REG_INT_XHOL_D2_BCM56840_B0r */
   1198         soc_block_list[16],
   1199         soc_genreg,
   1200         1,
   1201         0,
   1202         0x80235,
   1203         0,
   1204         0,
   1205         1,
   1206         soc_XHOL_D2r_fields,
   1207         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   1208         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1209         -1,
   1210         -1,
   1211     },
   1212 #endif /* chips */
   1213 
   1214 #if defined(BCM_88732_A0)
   1215     { /* SOC_REG_INT_XHOL_D2_BCM88732_A0r */
   1216         soc_block_list[16],
   1217         soc_genreg,
   1218         1,
   1219         0,
   1220         0x80235,
   1221         0,
   1222         0,
   1223         1,
   1224         soc_XHOL_D2r_fields,
   1225         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   1226         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1227         -1,
   1228         -1,
   1229     },
   1230 #endif /* chips */
   1231 
   1232 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   1233     defined(BCM_56334_B0)
   1234     { /* SOC_REG_INT_XHOL_D3_BCM56334_A0r */
   1235         soc_block_list[14],
   1236         soc_portreg,
   1237         1,
   1238         0,
   1239         0x813,
   1240         0,
   1241         0,
   1242         1,
   1243         soc_XHOL_D3r_fields,
   1244         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   1245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1246         -1,
   1247         -1,
   1248     },
   1249 #endif /* chips */
   1250 
   1251 #if defined(BCM_56340_A0)
   1252     { /* SOC_REG_INT_XHOL_D3_BCM56340_A0r */
   1253         soc_block_list[214],
   1254         soc_portreg,
   1255         1,
   1256         0,
   1257         0x23300,
   1258         0,
   1259         0,
   1260         1,
   1261         soc_XHOL_D3_BCM56640_A0r_fields,
   1262         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   1263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1264         -1,
   1265         -1,
   1266     },
   1267 #endif /* chips */
   1268 
   1269 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1270     { /* SOC_REG_INT_XHOL_D3_BCM56440_A0r */
   1271         soc_block_list[83],
   1272         soc_genreg,
   1273         1,
   1274         0,
   1275         0x8022c,
   1276         0,
   1277         0,
   1278         1,
   1279         soc_XHOL_D3r_fields,
   1280         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   1281         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1282         -1,
   1283         -1,
   1284     },
   1285 #endif /* chips */
   1286 
   1287 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1288     defined(BCM_56450_B1)
   1289     { /* SOC_REG_INT_XHOL_D3_BCM56450_A0r */
   1290         soc_block_list[83],
   1291         soc_genreg,
   1292         1,
   1293         0,
   1294         0x2022c00,
   1295         0,
   1296         0,
   1297         1,
   1298         soc_XHOL_D3_BCM56640_A0r_fields,
   1299         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   1300         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1301         -1,
   1302         -1,
   1303     },
   1304 #endif /* chips */
   1305 
   1306 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   1307     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   1308     { /* SOC_REG_INT_XHOL_D3_BCM56624_A0r */
   1309         soc_block_list[204],
   1310         soc_portreg,
   1311         1,
   1312         0,
   1313         0x813,
   1314         0,
   1315         0,
   1316         1,
   1317         soc_XHOL_D3r_fields,
   1318         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   1319         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1320         -1,
   1321         -1,
   1322     },
   1323 #endif /* chips */
   1324 
   1325 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   1326     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   1327     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   1328     { /* SOC_REG_INT_XHOL_D3_BCM56634_A0r */
   1329         soc_block_list[208],
   1330         soc_portreg,
   1331         1,
   1332         0,
   1333         0x813,
   1334         0,
   1335         0,
   1336         1,
   1337         soc_XHOL_D3r_fields,
   1338         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   1339         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1340         -1,
   1341         -1,
   1342     },
   1343 #endif /* chips */
   1344 
   1345 #if defined(BCM_56640_A0)
   1346     { /* SOC_REG_INT_XHOL_D3_BCM56640_A0r */
   1347         soc_block_list[212],
   1348         soc_portreg,
   1349         1,
   1350         0,
   1351         0x23300,
   1352         0,
   1353         0,
   1354         1,
   1355         soc_XHOL_D3_BCM56640_A0r_fields,
   1356         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   1357         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1358         -1,
   1359         -1,
   1360     },
   1361 #endif /* chips */
   1362 
   1363 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   1364     defined(BCM_56820_A0)
   1365     { /* SOC_REG_INT_XHOL_D3_BCM56800_A0r */
   1366         soc_block_list[9],
   1367         soc_portreg,
   1368         1,
   1369         0,
   1370         0x813,
   1371         0,
   1372         0,
   1373         1,
   1374         soc_XHOL_D3r_fields,
   1375         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   1376         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1377         -1,
   1378         -1,
   1379     },
   1380 #endif /* chips */
   1381 
   1382 #if defined(BCM_56840_A0)
   1383     { /* SOC_REG_INT_XHOL_D3_BCM56840_A0r */
   1384         soc_block_list[16],
   1385         soc_genreg,
   1386         1,
   1387         0,
   1388         0x80236,
   1389         0,
   1390         0,
   1391         1,
   1392         soc_XHOL_D3r_fields,
   1393         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   1394         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1395         -1,
   1396         -1,
   1397     },
   1398 #endif /* chips */
   1399 
   1400 #if defined(BCM_56840_B0)
   1401     { /* SOC_REG_INT_XHOL_D3_BCM56840_B0r */
   1402         soc_block_list[16],
   1403         soc_genreg,
   1404         1,
   1405         0,
   1406         0x80236,
   1407         0,
   1408         0,
   1409         1,
   1410         soc_XHOL_D3r_fields,
   1411         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   1412         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1413         -1,
   1414         -1,
   1415     },
   1416 #endif /* chips */
   1417 
   1418 #if defined(BCM_88732_A0)
   1419     { /* SOC_REG_INT_XHOL_D3_BCM88732_A0r */
   1420         soc_block_list[16],
   1421         soc_genreg,
   1422         1,
   1423         0,
   1424         0x80236,
   1425         0,
   1426         0,
   1427         1,
   1428         soc_XHOL_D3r_fields,
   1429         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   1430         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1431         -1,
   1432         -1,
   1433     },
   1434 #endif /* chips */
   1435 
   1436 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   1437     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   1438     { /* SOC_REG_INT_XHOL_MH0r */
   1439         soc_block_list[0],
   1440         soc_genreg,
   1441         1,
   1442         0,
   1443         0x8000b,
   1444         0,
   1445         0,
   1446         1,
   1447         soc_XHOL_MH0r_fields,
   1448         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1449         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1450         -1,
   1451         -1,
   1452     },
   1453 #endif /* chips */
   1454 
   1455 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   1456     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   1457     { /* SOC_REG_INT_XHOL_MH1r */
   1458         soc_block_list[0],
   1459         soc_genreg,
   1460         1,
   1461         0,
   1462         0x8000c,
   1463         0,
   1464         0,
   1465         1,
   1466         soc_XHOL_MH1r_fields,
   1467         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1469         -1,
   1470         -1,
   1471     },
   1472 #endif /* chips */
   1473 
   1474 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   1475     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   1476     { /* SOC_REG_INT_XHOL_MH2r */
   1477         soc_block_list[0],
   1478         soc_genreg,
   1479         1,
   1480         0,
   1481         0x8000d,
   1482         0,
   1483         0,
   1484         1,
   1485         soc_XHOL_MH2r_fields,
   1486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1487         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1488         -1,
   1489         -1,
   1490     },
   1491 #endif /* chips */
   1492 
   1493 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   1494     defined(BCM_56820_A0)
   1495     { /* SOC_REG_INT_XHOL_MH3r */
   1496         soc_block_list[9],
   1497         soc_portreg,
   1498         1,
   1499         0,
   1500         0x80f,
   1501         0,
   1502         0,
   1503         1,
   1504         soc_XHOL_MH3r_fields,
   1505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1506         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1507         -1,
   1508         -1,
   1509     },
   1510 #endif /* chips */
   1511 
   1512 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   1513     defined(BCM_56334_B0)
   1514     { /* SOC_REG_INT_XHOL_MH0_BCM56334_A0r */
   1515         soc_block_list[14],
   1516         soc_portreg,
   1517         1,
   1518         0,
   1519         0x80c,
   1520         0,
   1521         0,
   1522         1,
   1523         soc_XHOL_MH0r_fields,
   1524         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1526         -1,
   1527         -1,
   1528     },
   1529 #endif /* chips */
   1530 
   1531 #if defined(BCM_56340_A0)
   1532     { /* SOC_REG_INT_XHOL_MH0_BCM56340_A0r */
   1533         soc_block_list[214],
   1534         soc_portreg,
   1535         1,
   1536         0,
   1537         0x22c00,
   1538         0,
   1539         0,
   1540         1,
   1541         soc_XHOL_MH0_BCM56640_A0r_fields,
   1542         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1544         -1,
   1545         -1,
   1546     },
   1547 #endif /* chips */
   1548 
   1549 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1550     { /* SOC_REG_INT_XHOL_MH0_BCM56440_A0r */
   1551         soc_block_list[83],
   1552         soc_genreg,
   1553         1,
   1554         0,
   1555         0x80225,
   1556         0,
   1557         0,
   1558         1,
   1559         soc_XHOL_MH0r_fields,
   1560         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1561         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1562         -1,
   1563         -1,
   1564     },
   1565 #endif /* chips */
   1566 
   1567 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1568     defined(BCM_56450_B1)
   1569     { /* SOC_REG_INT_XHOL_MH0_BCM56450_A0r */
   1570         soc_block_list[83],
   1571         soc_genreg,
   1572         1,
   1573         0,
   1574         0x2022500,
   1575         0,
   1576         0,
   1577         1,
   1578         soc_XHOL_MH0_BCM56640_A0r_fields,
   1579         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1580         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1581         -1,
   1582         -1,
   1583     },
   1584 #endif /* chips */
   1585 
   1586 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   1587     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   1588     { /* SOC_REG_INT_XHOL_MH0_BCM56624_A0r */
   1589         soc_block_list[204],
   1590         soc_portreg,
   1591         1,
   1592         0,
   1593         0x80c,
   1594         0,
   1595         0,
   1596         1,
   1597         soc_XHOL_MH0r_fields,
   1598         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1599         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1600         -1,
   1601         -1,
   1602     },
   1603 #endif /* chips */
   1604 
   1605 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   1606     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   1607     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   1608     { /* SOC_REG_INT_XHOL_MH0_BCM56634_A0r */
   1609         soc_block_list[208],
   1610         soc_portreg,
   1611         1,
   1612         0,
   1613         0x80c,
   1614         0,
   1615         0,
   1616         1,
   1617         soc_XHOL_MH0r_fields,
   1618         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1619         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1620         -1,
   1621         -1,
   1622     },
   1623 #endif /* chips */
   1624 
   1625 #if defined(BCM_56640_A0)
   1626     { /* SOC_REG_INT_XHOL_MH0_BCM56640_A0r */
   1627         soc_block_list[212],
   1628         soc_portreg,
   1629         1,
   1630         0,
   1631         0x22c00,
   1632         0,
   1633         0,
   1634         1,
   1635         soc_XHOL_MH0_BCM56640_A0r_fields,
   1636         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1637         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1638         -1,
   1639         -1,
   1640     },
   1641 #endif /* chips */
   1642 
   1643 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   1644     defined(BCM_56820_A0)
   1645     { /* SOC_REG_INT_XHOL_MH0_BCM56800_A0r */
   1646         soc_block_list[9],
   1647         soc_portreg,
   1648         1,
   1649         0,
   1650         0x80c,
   1651         0,
   1652         0,
   1653         1,
   1654         soc_XHOL_MH0r_fields,
   1655         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1656         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1657         -1,
   1658         -1,
   1659     },
   1660 #endif /* chips */
   1661 
   1662 #if defined(BCM_56840_A0)
   1663     { /* SOC_REG_INT_XHOL_MH0_BCM56840_A0r */
   1664         soc_block_list[16],
   1665         soc_genreg,
   1666         1,
   1667         0,
   1668         0x8022f,
   1669         0,
   1670         0,
   1671         1,
   1672         soc_XHOL_MH0r_fields,
   1673         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1674         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1675         -1,
   1676         -1,
   1677     },
   1678 #endif /* chips */
   1679 
   1680 #if defined(BCM_56840_B0)
   1681     { /* SOC_REG_INT_XHOL_MH0_BCM56840_B0r */
   1682         soc_block_list[16],
   1683         soc_genreg,
   1684         1,
   1685         0,
   1686         0x8022f,
   1687         0,
   1688         0,
   1689         1,
   1690         soc_XHOL_MH0r_fields,
   1691         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1692         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1693         -1,
   1694         -1,
   1695     },
   1696 #endif /* chips */
   1697 
   1698 #if defined(BCM_88732_A0)
   1699     { /* SOC_REG_INT_XHOL_MH0_BCM88732_A0r */
   1700         soc_block_list[16],
   1701         soc_genreg,
   1702         1,
   1703         0,
   1704         0x8022f,
   1705         0,
   1706         0,
   1707         1,
   1708         soc_XHOL_MH0r_fields,
   1709         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   1710         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1711         -1,
   1712         -1,
   1713     },
   1714 #endif /* chips */
   1715 
   1716 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   1717     defined(BCM_56334_B0)
   1718     { /* SOC_REG_INT_XHOL_MH1_BCM56334_A0r */
   1719         soc_block_list[14],
   1720         soc_portreg,
   1721         1,
   1722         0,
   1723         0x80d,
   1724         0,
   1725         0,
   1726         1,
   1727         soc_XHOL_MH1r_fields,
   1728         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1729         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1730         -1,
   1731         -1,
   1732     },
   1733 #endif /* chips */
   1734 
   1735 #if defined(BCM_56340_A0)
   1736     { /* SOC_REG_INT_XHOL_MH1_BCM56340_A0r */
   1737         soc_block_list[214],
   1738         soc_portreg,
   1739         1,
   1740         0,
   1741         0x22d00,
   1742         0,
   1743         0,
   1744         1,
   1745         soc_XHOL_MH1_BCM56640_A0r_fields,
   1746         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1747         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1748         -1,
   1749         -1,
   1750     },
   1751 #endif /* chips */
   1752 
   1753 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1754     { /* SOC_REG_INT_XHOL_MH1_BCM56440_A0r */
   1755         soc_block_list[83],
   1756         soc_genreg,
   1757         1,
   1758         0,
   1759         0x80226,
   1760         0,
   1761         0,
   1762         1,
   1763         soc_XHOL_MH1r_fields,
   1764         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1765         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1766         -1,
   1767         -1,
   1768     },
   1769 #endif /* chips */
   1770 
   1771 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1772     defined(BCM_56450_B1)
   1773     { /* SOC_REG_INT_XHOL_MH1_BCM56450_A0r */
   1774         soc_block_list[83],
   1775         soc_genreg,
   1776         1,
   1777         0,
   1778         0x2022600,
   1779         0,
   1780         0,
   1781         1,
   1782         soc_XHOL_MH1_BCM56640_A0r_fields,
   1783         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1784         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1785         -1,
   1786         -1,
   1787     },
   1788 #endif /* chips */
   1789 
   1790 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   1791     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   1792     { /* SOC_REG_INT_XHOL_MH1_BCM56624_A0r */
   1793         soc_block_list[204],
   1794         soc_portreg,
   1795         1,
   1796         0,
   1797         0x80d,
   1798         0,
   1799         0,
   1800         1,
   1801         soc_XHOL_MH1r_fields,
   1802         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1803         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1804         -1,
   1805         -1,
   1806     },
   1807 #endif /* chips */
   1808 
   1809 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   1810     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   1811     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   1812     { /* SOC_REG_INT_XHOL_MH1_BCM56634_A0r */
   1813         soc_block_list[208],
   1814         soc_portreg,
   1815         1,
   1816         0,
   1817         0x80d,
   1818         0,
   1819         0,
   1820         1,
   1821         soc_XHOL_MH1r_fields,
   1822         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1823         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1824         -1,
   1825         -1,
   1826     },
   1827 #endif /* chips */
   1828 
   1829 #if defined(BCM_56640_A0)
   1830     { /* SOC_REG_INT_XHOL_MH1_BCM56640_A0r */
   1831         soc_block_list[212],
   1832         soc_portreg,
   1833         1,
   1834         0,
   1835         0x22d00,
   1836         0,
   1837         0,
   1838         1,
   1839         soc_XHOL_MH1_BCM56640_A0r_fields,
   1840         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1842         -1,
   1843         -1,
   1844     },
   1845 #endif /* chips */
   1846 
   1847 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   1848     defined(BCM_56820_A0)
   1849     { /* SOC_REG_INT_XHOL_MH1_BCM56800_A0r */
   1850         soc_block_list[9],
   1851         soc_portreg,
   1852         1,
   1853         0,
   1854         0x80d,
   1855         0,
   1856         0,
   1857         1,
   1858         soc_XHOL_MH1r_fields,
   1859         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1860         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1861         -1,
   1862         -1,
   1863     },
   1864 #endif /* chips */
   1865 
   1866 #if defined(BCM_56840_A0)
   1867     { /* SOC_REG_INT_XHOL_MH1_BCM56840_A0r */
   1868         soc_block_list[16],
   1869         soc_genreg,
   1870         1,
   1871         0,
   1872         0x80230,
   1873         0,
   1874         0,
   1875         1,
   1876         soc_XHOL_MH1r_fields,
   1877         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1878         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1879         -1,
   1880         -1,
   1881     },
   1882 #endif /* chips */
   1883 
   1884 #if defined(BCM_56840_B0)
   1885     { /* SOC_REG_INT_XHOL_MH1_BCM56840_B0r */
   1886         soc_block_list[16],
   1887         soc_genreg,
   1888         1,
   1889         0,
   1890         0x80230,
   1891         0,
   1892         0,
   1893         1,
   1894         soc_XHOL_MH1r_fields,
   1895         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1896         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1897         -1,
   1898         -1,
   1899     },
   1900 #endif /* chips */
   1901 
   1902 #if defined(BCM_88732_A0)
   1903     { /* SOC_REG_INT_XHOL_MH1_BCM88732_A0r */
   1904         soc_block_list[16],
   1905         soc_genreg,
   1906         1,
   1907         0,
   1908         0x80230,
   1909         0,
   1910         0,
   1911         1,
   1912         soc_XHOL_MH1r_fields,
   1913         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   1914         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1915         -1,
   1916         -1,
   1917     },
   1918 #endif /* chips */
   1919 
   1920 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   1921     defined(BCM_56334_B0)
   1922     { /* SOC_REG_INT_XHOL_MH2_BCM56334_A0r */
   1923         soc_block_list[14],
   1924         soc_portreg,
   1925         1,
   1926         0,
   1927         0x80e,
   1928         0,
   1929         0,
   1930         1,
   1931         soc_XHOL_MH2r_fields,
   1932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1933         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1934         -1,
   1935         -1,
   1936     },
   1937 #endif /* chips */
   1938 
   1939 #if defined(BCM_56340_A0)
   1940     { /* SOC_REG_INT_XHOL_MH2_BCM56340_A0r */
   1941         soc_block_list[214],
   1942         soc_portreg,
   1943         1,
   1944         0,
   1945         0x22e00,
   1946         0,
   1947         0,
   1948         1,
   1949         soc_XHOL_MH2_BCM56640_A0r_fields,
   1950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1952         -1,
   1953         -1,
   1954     },
   1955 #endif /* chips */
   1956 
   1957 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1958     { /* SOC_REG_INT_XHOL_MH2_BCM56440_A0r */
   1959         soc_block_list[83],
   1960         soc_genreg,
   1961         1,
   1962         0,
   1963         0x80227,
   1964         0,
   1965         0,
   1966         1,
   1967         soc_XHOL_MH2r_fields,
   1968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1969         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1970         -1,
   1971         -1,
   1972     },
   1973 #endif /* chips */
   1974 
   1975 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1976     defined(BCM_56450_B1)
   1977     { /* SOC_REG_INT_XHOL_MH2_BCM56450_A0r */
   1978         soc_block_list[83],
   1979         soc_genreg,
   1980         1,
   1981         0,
   1982         0x2022700,
   1983         0,
   1984         0,
   1985         1,
   1986         soc_XHOL_MH2_BCM56640_A0r_fields,
   1987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1988         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1989         -1,
   1990         -1,
   1991     },
   1992 #endif /* chips */
   1993 
   1994 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   1995     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   1996     { /* SOC_REG_INT_XHOL_MH2_BCM56624_A0r */
   1997         soc_block_list[204],
   1998         soc_portreg,
   1999         1,
   2000         0,
   2001         0x80e,
   2002         0,
   2003         0,
   2004         1,
   2005         soc_XHOL_MH2r_fields,
   2006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2007         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2008         -1,
   2009         -1,
   2010     },
   2011 #endif /* chips */
   2012 
   2013 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2014     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2015     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2016     { /* SOC_REG_INT_XHOL_MH2_BCM56634_A0r */
   2017         soc_block_list[208],
   2018         soc_portreg,
   2019         1,
   2020         0,
   2021         0x80e,
   2022         0,
   2023         0,
   2024         1,
   2025         soc_XHOL_MH2r_fields,
   2026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2028         -1,
   2029         -1,
   2030     },
   2031 #endif /* chips */
   2032 
   2033 #if defined(BCM_56640_A0)
   2034     { /* SOC_REG_INT_XHOL_MH2_BCM56640_A0r */
   2035         soc_block_list[212],
   2036         soc_portreg,
   2037         1,
   2038         0,
   2039         0x22e00,
   2040         0,
   2041         0,
   2042         1,
   2043         soc_XHOL_MH2_BCM56640_A0r_fields,
   2044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2045         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2046         -1,
   2047         -1,
   2048     },
   2049 #endif /* chips */
   2050 
   2051 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   2052     defined(BCM_56820_A0)
   2053     { /* SOC_REG_INT_XHOL_MH2_BCM56800_A0r */
   2054         soc_block_list[9],
   2055         soc_portreg,
   2056         1,
   2057         0,
   2058         0x80e,
   2059         0,
   2060         0,
   2061         1,
   2062         soc_XHOL_MH2r_fields,
   2063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2064         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2065         -1,
   2066         -1,
   2067     },
   2068 #endif /* chips */
   2069 
   2070 #if defined(BCM_56840_A0)
   2071     { /* SOC_REG_INT_XHOL_MH2_BCM56840_A0r */
   2072         soc_block_list[16],
   2073         soc_genreg,
   2074         1,
   2075         0,
   2076         0x80231,
   2077         0,
   2078         0,
   2079         1,
   2080         soc_XHOL_MH2r_fields,
   2081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2082         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2083         -1,
   2084         -1,
   2085     },
   2086 #endif /* chips */
   2087 
   2088 #if defined(BCM_56840_B0)
   2089     { /* SOC_REG_INT_XHOL_MH2_BCM56840_B0r */
   2090         soc_block_list[16],
   2091         soc_genreg,
   2092         1,
   2093         0,
   2094         0x80231,
   2095         0,
   2096         0,
   2097         1,
   2098         soc_XHOL_MH2r_fields,
   2099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2100         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2101         -1,
   2102         -1,
   2103     },
   2104 #endif /* chips */
   2105 
   2106 #if defined(BCM_88732_A0)
   2107     { /* SOC_REG_INT_XHOL_MH2_BCM88732_A0r */
   2108         soc_block_list[16],
   2109         soc_genreg,
   2110         1,
   2111         0,
   2112         0x80231,
   2113         0,
   2114         0,
   2115         1,
   2116         soc_XHOL_MH2r_fields,
   2117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2118         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2119         -1,
   2120         -1,
   2121     },
   2122 #endif /* chips */
   2123 
   2124 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   2125     defined(BCM_56334_B0)
   2126     { /* SOC_REG_INT_XHOL_MH3_BCM56334_A0r */
   2127         soc_block_list[14],
   2128         soc_portreg,
   2129         1,
   2130         0,
   2131         0x80f,
   2132         0,
   2133         0,
   2134         1,
   2135         soc_XHOL_MH3r_fields,
   2136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2138         -1,
   2139         -1,
   2140     },
   2141 #endif /* chips */
   2142 
   2143 #if defined(BCM_56340_A0)
   2144     { /* SOC_REG_INT_XHOL_MH3_BCM56340_A0r */
   2145         soc_block_list[214],
   2146         soc_portreg,
   2147         1,
   2148         0,
   2149         0x22f00,
   2150         0,
   2151         0,
   2152         1,
   2153         soc_XHOL_MH3_BCM56640_A0r_fields,
   2154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2156         -1,
   2157         -1,
   2158     },
   2159 #endif /* chips */
   2160 
   2161 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2162     { /* SOC_REG_INT_XHOL_MH3_BCM56440_A0r */
   2163         soc_block_list[83],
   2164         soc_genreg,
   2165         1,
   2166         0,
   2167         0x80228,
   2168         0,
   2169         0,
   2170         1,
   2171         soc_XHOL_MH3r_fields,
   2172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2173         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2174         -1,
   2175         -1,
   2176     },
   2177 #endif /* chips */
   2178 
   2179 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2180     defined(BCM_56450_B1)
   2181     { /* SOC_REG_INT_XHOL_MH3_BCM56450_A0r */
   2182         soc_block_list[83],
   2183         soc_genreg,
   2184         1,
   2185         0,
   2186         0x2022800,
   2187         0,
   2188         0,
   2189         1,
   2190         soc_XHOL_MH3_BCM56640_A0r_fields,
   2191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2192         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2193         -1,
   2194         -1,
   2195     },
   2196 #endif /* chips */
   2197 
   2198 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   2199     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   2200     { /* SOC_REG_INT_XHOL_MH3_BCM56624_A0r */
   2201         soc_block_list[204],
   2202         soc_portreg,
   2203         1,
   2204         0,
   2205         0x80f,
   2206         0,
   2207         0,
   2208         1,
   2209         soc_XHOL_MH3r_fields,
   2210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2211         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2212         -1,
   2213         -1,
   2214     },
   2215 #endif /* chips */
   2216 
   2217 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2218     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2219     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2220     { /* SOC_REG_INT_XHOL_MH3_BCM56634_A0r */
   2221         soc_block_list[208],
   2222         soc_portreg,
   2223         1,
   2224         0,
   2225         0x80f,
   2226         0,
   2227         0,
   2228         1,
   2229         soc_XHOL_MH3r_fields,
   2230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2231         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2232         -1,
   2233         -1,
   2234     },
   2235 #endif /* chips */
   2236 
   2237 #if defined(BCM_56640_A0)
   2238     { /* SOC_REG_INT_XHOL_MH3_BCM56640_A0r */
   2239         soc_block_list[212],
   2240         soc_portreg,
   2241         1,
   2242         0,
   2243         0x22f00,
   2244         0,
   2245         0,
   2246         1,
   2247         soc_XHOL_MH3_BCM56640_A0r_fields,
   2248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2249         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2250         -1,
   2251         -1,
   2252     },
   2253 #endif /* chips */
   2254 
   2255 #if defined(BCM_56840_A0)
   2256     { /* SOC_REG_INT_XHOL_MH3_BCM56840_A0r */
   2257         soc_block_list[16],
   2258         soc_genreg,
   2259         1,
   2260         0,
   2261         0x80232,
   2262         0,
   2263         0,
   2264         1,
   2265         soc_XHOL_MH3r_fields,
   2266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2267         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2268         -1,
   2269         -1,
   2270     },
   2271 #endif /* chips */
   2272 
   2273 #if defined(BCM_56840_B0)
   2274     { /* SOC_REG_INT_XHOL_MH3_BCM56840_B0r */
   2275         soc_block_list[16],
   2276         soc_genreg,
   2277         1,
   2278         0,
   2279         0x80232,
   2280         0,
   2281         0,
   2282         1,
   2283         soc_XHOL_MH3r_fields,
   2284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2285         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2286         -1,
   2287         -1,
   2288     },
   2289 #endif /* chips */
   2290 
   2291 #if defined(BCM_88732_A0)
   2292     { /* SOC_REG_INT_XHOL_MH3_BCM88732_A0r */
   2293         soc_block_list[16],
   2294         soc_genreg,
   2295         1,
   2296         0,
   2297         0x80232,
   2298         0,
   2299         0,
   2300         1,
   2301         soc_XHOL_MH3r_fields,
   2302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2303         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2304         -1,
   2305         -1,
   2306     },
   2307 #endif /* chips */
   2308 
   2309 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2310     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2311     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2312     { /* SOC_REG_INT_XHOL_RX_MH_DATA0r */
   2313         soc_block_list[9],
   2314         soc_genreg,
   2315         1,
   2316         0,
   2317         0x80d0b,
   2318         0,
   2319         0,
   2320         1,
   2321         soc_XHOL_RX_MH_DATA0r_fields,
   2322         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   2323         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2324         -1,
   2325         -1,
   2326     },
   2327 #endif /* chips */
   2328 
   2329 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2330     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2331     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2332     { /* SOC_REG_INT_XHOL_RX_MH_DATA1r */
   2333         soc_block_list[9],
   2334         soc_genreg,
   2335         1,
   2336         0,
   2337         0x80d0c,
   2338         0,
   2339         0,
   2340         1,
   2341         soc_XHOL_RX_MH_DATA1r_fields,
   2342         SOC_RESET_VAL_DEC(0x20000000, 0x00000000)
   2343         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2344         -1,
   2345         -1,
   2346     },
   2347 #endif /* chips */
   2348 
   2349 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2350     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2351     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2352     { /* SOC_REG_INT_XHOL_RX_MH_DATA2r */
   2353         soc_block_list[9],
   2354         soc_genreg,
   2355         1,
   2356         0,
   2357         0x80d0d,
   2358         0,
   2359         0,
   2360         1,
   2361         soc_XHOL_RX_MH_DATA2r_fields,
   2362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2363         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2364         -1,
   2365         -1,
   2366     },
   2367 #endif /* chips */
   2368 
   2369 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2370     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2371     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2372     { /* SOC_REG_INT_XHOL_RX_MH_DATA3r */
   2373         soc_block_list[9],
   2374         soc_genreg,
   2375         1,
   2376         0,
   2377         0x80d0e,
   2378         0,
   2379         0,
   2380         1,
   2381         soc_XHOL_RX_MH_DATA3r_fields,
   2382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2383         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2384         -1,
   2385         -1,
   2386     },
   2387 #endif /* chips */
   2388 
   2389 #if defined(BCM_56340_A0)
   2390     { /* SOC_REG_INT_XHOL_RX_MH_DATA0_BCM56340_A0r */
   2391         soc_block_list[214],
   2392         soc_portreg,
   2393         1,
   2394         0,
   2395         0x23400,
   2396         0,
   2397         0,
   2398         1,
   2399         soc_XHOL_RX_MH_DATA0_BCM56640_A0r_fields,
   2400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2401         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2402         -1,
   2403         -1,
   2404     },
   2405 #endif /* chips */
   2406 
   2407 #if defined(BCM_56640_A0)
   2408     { /* SOC_REG_INT_XHOL_RX_MH_DATA0_BCM56640_A0r */
   2409         soc_block_list[212],
   2410         soc_portreg,
   2411         1,
   2412         0,
   2413         0x23400,
   2414         0,
   2415         0,
   2416         1,
   2417         soc_XHOL_RX_MH_DATA0_BCM56640_A0r_fields,
   2418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2419         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2420         -1,
   2421         -1,
   2422     },
   2423 #endif /* chips */
   2424 
   2425 #if defined(BCM_56340_A0)
   2426     { /* SOC_REG_INT_XHOL_RX_MH_DATA1_BCM56340_A0r */
   2427         soc_block_list[214],
   2428         soc_portreg,
   2429         1,
   2430         0,
   2431         0x23500,
   2432         0,
   2433         0,
   2434         1,
   2435         soc_XHOL_RX_MH_DATA1_BCM56640_A0r_fields,
   2436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2437         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2438         -1,
   2439         -1,
   2440     },
   2441 #endif /* chips */
   2442 
   2443 #if defined(BCM_56640_A0)
   2444     { /* SOC_REG_INT_XHOL_RX_MH_DATA1_BCM56640_A0r */
   2445         soc_block_list[212],
   2446         soc_portreg,
   2447         1,
   2448         0,
   2449         0x23500,
   2450         0,
   2451         0,
   2452         1,
   2453         soc_XHOL_RX_MH_DATA1_BCM56640_A0r_fields,
   2454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2455         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2456         -1,
   2457         -1,
   2458     },
   2459 #endif /* chips */
   2460 
   2461 #if defined(BCM_56340_A0)
   2462     { /* SOC_REG_INT_XHOL_RX_MH_DATA2_BCM56340_A0r */
   2463         soc_block_list[214],
   2464         soc_portreg,
   2465         1,
   2466         0,
   2467         0x23600,
   2468         0,
   2469         0,
   2470         1,
   2471         soc_XHOL_RX_MH_DATA2_BCM56640_A0r_fields,
   2472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2473         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2474         -1,
   2475         -1,
   2476     },
   2477 #endif /* chips */
   2478 
   2479 #if defined(BCM_56640_A0)
   2480     { /* SOC_REG_INT_XHOL_RX_MH_DATA2_BCM56640_A0r */
   2481         soc_block_list[212],
   2482         soc_portreg,
   2483         1,
   2484         0,
   2485         0x23600,
   2486         0,
   2487         0,
   2488         1,
   2489         soc_XHOL_RX_MH_DATA2_BCM56640_A0r_fields,
   2490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2491         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2492         -1,
   2493         -1,
   2494     },
   2495 #endif /* chips */
   2496 
   2497 #if defined(BCM_56340_A0)
   2498     { /* SOC_REG_INT_XHOL_RX_MH_DATA3_BCM56340_A0r */
   2499         soc_block_list[214],
   2500         soc_portreg,
   2501         1,
   2502         0,
   2503         0x23700,
   2504         0,
   2505         0,
   2506         1,
   2507         soc_XHOL_RX_MH_DATA3_BCM56640_A0r_fields,
   2508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2509         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2510         -1,
   2511         -1,
   2512     },
   2513 #endif /* chips */
   2514 
   2515 #if defined(BCM_56640_A0)
   2516     { /* SOC_REG_INT_XHOL_RX_MH_DATA3_BCM56640_A0r */
   2517         soc_block_list[212],
   2518         soc_portreg,
   2519         1,
   2520         0,
   2521         0x23700,
   2522         0,
   2523         0,
   2524         1,
   2525         soc_XHOL_RX_MH_DATA3_BCM56640_A0r_fields,
   2526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2527         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2528         -1,
   2529         -1,
   2530     },
   2531 #endif /* chips */
   2532 
   2533 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2534     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2535     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2536     { /* SOC_REG_INT_XHOL_RX_MH_MASK0r */
   2537         soc_block_list[9],
   2538         soc_genreg,
   2539         1,
   2540         0,
   2541         0x80d0f,
   2542         0,
   2543         0,
   2544         1,
   2545         soc_XHOL_RX_MH_MASK0r_fields,
   2546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2547         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2548         -1,
   2549         -1,
   2550     },
   2551 #endif /* chips */
   2552 
   2553 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2554     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2555     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2556     { /* SOC_REG_INT_XHOL_RX_MH_MASK1r */
   2557         soc_block_list[9],
   2558         soc_genreg,
   2559         1,
   2560         0,
   2561         0x80d10,
   2562         0,
   2563         0,
   2564         1,
   2565         soc_XHOL_RX_MH_MASK1r_fields,
   2566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2567         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2568         -1,
   2569         -1,
   2570     },
   2571 #endif /* chips */
   2572 
   2573 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2574     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2575     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2576     { /* SOC_REG_INT_XHOL_RX_MH_MASK2r */
   2577         soc_block_list[9],
   2578         soc_genreg,
   2579         1,
   2580         0,
   2581         0x80d11,
   2582         0,
   2583         0,
   2584         1,
   2585         soc_XHOL_RX_MH_MASK2r_fields,
   2586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2587         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2588         -1,
   2589         -1,
   2590     },
   2591 #endif /* chips */
   2592 
   2593 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2594     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2595     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2596     { /* SOC_REG_INT_XHOL_RX_MH_MASK3r */
   2597         soc_block_list[9],
   2598         soc_genreg,
   2599         1,
   2600         0,
   2601         0x80d12,
   2602         0,
   2603         0,
   2604         1,
   2605         soc_XHOL_RX_MH_MASK3r_fields,
   2606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2607         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2608         -1,
   2609         -1,
   2610     },
   2611 #endif /* chips */
   2612 
   2613 #if defined(BCM_56340_A0)
   2614     { /* SOC_REG_INT_XHOL_RX_MH_MASK0_BCM56340_A0r */
   2615         soc_block_list[214],
   2616         soc_portreg,
   2617         1,
   2618         0,
   2619         0x23800,
   2620         0,
   2621         0,
   2622         1,
   2623         soc_XHOL_RX_MH_MASK0_BCM56640_A0r_fields,
   2624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2625         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2626         -1,
   2627         -1,
   2628     },
   2629 #endif /* chips */
   2630 
   2631 #if defined(BCM_56640_A0)
   2632     { /* SOC_REG_INT_XHOL_RX_MH_MASK0_BCM56640_A0r */
   2633         soc_block_list[212],
   2634         soc_portreg,
   2635         1,
   2636         0,
   2637         0x23800,
   2638         0,
   2639         0,
   2640         1,
   2641         soc_XHOL_RX_MH_MASK0_BCM56640_A0r_fields,
   2642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2643         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2644         -1,
   2645         -1,
   2646     },
   2647 #endif /* chips */
   2648 
   2649 #if defined(BCM_56340_A0)
   2650     { /* SOC_REG_INT_XHOL_RX_MH_MASK1_BCM56340_A0r */
   2651         soc_block_list[214],
   2652         soc_portreg,
   2653         1,
   2654         0,
   2655         0x23900,
   2656         0,
   2657         0,
   2658         1,
   2659         soc_XHOL_RX_MH_MASK1_BCM56640_A0r_fields,
   2660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2661         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2662         -1,
   2663         -1,
   2664     },
   2665 #endif /* chips */
   2666 
   2667 #if defined(BCM_56640_A0)
   2668     { /* SOC_REG_INT_XHOL_RX_MH_MASK1_BCM56640_A0r */
   2669         soc_block_list[212],
   2670         soc_portreg,
   2671         1,
   2672         0,
   2673         0x23900,
   2674         0,
   2675         0,
   2676         1,
   2677         soc_XHOL_RX_MH_MASK1_BCM56640_A0r_fields,
   2678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2679         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2680         -1,
   2681         -1,
   2682     },
   2683 #endif /* chips */
   2684 
   2685 #if defined(BCM_56340_A0)
   2686     { /* SOC_REG_INT_XHOL_RX_MH_MASK2_BCM56340_A0r */
   2687         soc_block_list[214],
   2688         soc_portreg,
   2689         1,
   2690         0,
   2691         0x23a00,
   2692         0,
   2693         0,
   2694         1,
   2695         soc_XHOL_RX_MH_MASK2_BCM56640_A0r_fields,
   2696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2697         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2698         -1,
   2699         -1,
   2700     },
   2701 #endif /* chips */
   2702 
   2703 #if defined(BCM_56640_A0)
   2704     { /* SOC_REG_INT_XHOL_RX_MH_MASK2_BCM56640_A0r */
   2705         soc_block_list[212],
   2706         soc_portreg,
   2707         1,
   2708         0,
   2709         0x23a00,
   2710         0,
   2711         0,
   2712         1,
   2713         soc_XHOL_RX_MH_MASK2_BCM56640_A0r_fields,
   2714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2715         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2716         -1,
   2717         -1,
   2718     },
   2719 #endif /* chips */
   2720 
   2721 #if defined(BCM_56340_A0)
   2722     { /* SOC_REG_INT_XHOL_RX_MH_MASK3_BCM56340_A0r */
   2723         soc_block_list[214],
   2724         soc_portreg,
   2725         1,
   2726         0,
   2727         0x23b00,
   2728         0,
   2729         0,
   2730         1,
   2731         soc_XHOL_RX_MH_MASK3_BCM56640_A0r_fields,
   2732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2733         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2734         -1,
   2735         -1,
   2736     },
   2737 #endif /* chips */
   2738 
   2739 #if defined(BCM_56640_A0)
   2740     { /* SOC_REG_INT_XHOL_RX_MH_MASK3_BCM56640_A0r */
   2741         soc_block_list[212],
   2742         soc_portreg,
   2743         1,
   2744         0,
   2745         0x23b00,
   2746         0,
   2747         0,
   2748         1,
   2749         soc_XHOL_RX_MH_MASK3_BCM56640_A0r_fields,
   2750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2751         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2752         -1,
   2753         -1,
   2754     },
   2755 #endif /* chips */
   2756 
   2757 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2758     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2759     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2760     { /* SOC_REG_INT_XHOL_RX_PKT_DATA0r */
   2761         soc_block_list[9],
   2762         soc_genreg,
   2763         1,
   2764         0,
   2765         0x80d13,
   2766         0,
   2767         0,
   2768         1,
   2769         soc_XHOL_RX_PKT_DATA0r_fields,
   2770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2771         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2772         -1,
   2773         -1,
   2774     },
   2775 #endif /* chips */
   2776 
   2777 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2778     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2779     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2780     { /* SOC_REG_INT_XHOL_RX_PKT_DATA1r */
   2781         soc_block_list[9],
   2782         soc_genreg,
   2783         1,
   2784         0,
   2785         0x80d14,
   2786         0,
   2787         0,
   2788         1,
   2789         soc_XHOL_RX_PKT_DATA1r_fields,
   2790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2791         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2792         -1,
   2793         -1,
   2794     },
   2795 #endif /* chips */
   2796 
   2797 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2798     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2799     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2800     { /* SOC_REG_INT_XHOL_RX_PKT_DATA2r */
   2801         soc_block_list[9],
   2802         soc_genreg,
   2803         1,
   2804         0,
   2805         0x80d15,
   2806         0,
   2807         0,
   2808         1,
   2809         soc_XHOL_RX_PKT_DATA2r_fields,
   2810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2811         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2812         -1,
   2813         -1,
   2814     },
   2815 #endif /* chips */
   2816 
   2817 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2818     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2819     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2820     { /* SOC_REG_INT_XHOL_RX_PKT_DATA3r */
   2821         soc_block_list[9],
   2822         soc_genreg,
   2823         1,
   2824         0,
   2825         0x80d16,
   2826         0,
   2827         0,
   2828         1,
   2829         soc_XHOL_RX_PKT_DATA3r_fields,
   2830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2831         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2832         -1,
   2833         -1,
   2834     },
   2835 #endif /* chips */
   2836 
   2837 #if defined(BCM_56340_A0)
   2838     { /* SOC_REG_INT_XHOL_RX_PKT_DATA0_BCM56340_A0r */
   2839         soc_block_list[214],
   2840         soc_portreg,
   2841         1,
   2842         0,
   2843         0x23c00,
   2844         0,
   2845         0,
   2846         1,
   2847         soc_XHOL_RX_PKT_DATA0_BCM56640_A0r_fields,
   2848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2849         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2850         -1,
   2851         -1,
   2852     },
   2853 #endif /* chips */
   2854 
   2855 #if defined(BCM_56640_A0)
   2856     { /* SOC_REG_INT_XHOL_RX_PKT_DATA0_BCM56640_A0r */
   2857         soc_block_list[212],
   2858         soc_portreg,
   2859         1,
   2860         0,
   2861         0x23c00,
   2862         0,
   2863         0,
   2864         1,
   2865         soc_XHOL_RX_PKT_DATA0_BCM56640_A0r_fields,
   2866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2867         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2868         -1,
   2869         -1,
   2870     },
   2871 #endif /* chips */
   2872 
   2873 #if defined(BCM_56340_A0)
   2874     { /* SOC_REG_INT_XHOL_RX_PKT_DATA1_BCM56340_A0r */
   2875         soc_block_list[214],
   2876         soc_portreg,
   2877         1,
   2878         0,
   2879         0x23d00,
   2880         0,
   2881         0,
   2882         1,
   2883         soc_XHOL_RX_PKT_DATA1_BCM56640_A0r_fields,
   2884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2885         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2886         -1,
   2887         -1,
   2888     },
   2889 #endif /* chips */
   2890 
   2891 #if defined(BCM_56640_A0)
   2892     { /* SOC_REG_INT_XHOL_RX_PKT_DATA1_BCM56640_A0r */
   2893         soc_block_list[212],
   2894         soc_portreg,
   2895         1,
   2896         0,
   2897         0x23d00,
   2898         0,
   2899         0,
   2900         1,
   2901         soc_XHOL_RX_PKT_DATA1_BCM56640_A0r_fields,
   2902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2904         -1,
   2905         -1,
   2906     },
   2907 #endif /* chips */
   2908 
   2909 #if defined(BCM_56340_A0)
   2910     { /* SOC_REG_INT_XHOL_RX_PKT_DATA2_BCM56340_A0r */
   2911         soc_block_list[214],
   2912         soc_portreg,
   2913         1,
   2914         0,
   2915         0x23e00,
   2916         0,
   2917         0,
   2918         1,
   2919         soc_XHOL_RX_PKT_DATA2_BCM56640_A0r_fields,
   2920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2922         -1,
   2923         -1,
   2924     },
   2925 #endif /* chips */
   2926 
   2927 #if defined(BCM_56640_A0)
   2928     { /* SOC_REG_INT_XHOL_RX_PKT_DATA2_BCM56640_A0r */
   2929         soc_block_list[212],
   2930         soc_portreg,
   2931         1,
   2932         0,
   2933         0x23e00,
   2934         0,
   2935         0,
   2936         1,
   2937         soc_XHOL_RX_PKT_DATA2_BCM56640_A0r_fields,
   2938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2939         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2940         -1,
   2941         -1,
   2942     },
   2943 #endif /* chips */
   2944 
   2945 #if defined(BCM_56340_A0)
   2946     { /* SOC_REG_INT_XHOL_RX_PKT_DATA3_BCM56340_A0r */
   2947         soc_block_list[214],
   2948         soc_portreg,
   2949         1,
   2950         0,
   2951         0x23f00,
   2952         0,
   2953         0,
   2954         1,
   2955         soc_XHOL_RX_PKT_DATA3_BCM56640_A0r_fields,
   2956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2957         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2958         -1,
   2959         -1,
   2960     },
   2961 #endif /* chips */
   2962 
   2963 #if defined(BCM_56640_A0)
   2964     { /* SOC_REG_INT_XHOL_RX_PKT_DATA3_BCM56640_A0r */
   2965         soc_block_list[212],
   2966         soc_portreg,
   2967         1,
   2968         0,
   2969         0x23f00,
   2970         0,
   2971         0,
   2972         1,
   2973         soc_XHOL_RX_PKT_DATA3_BCM56640_A0r_fields,
   2974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2975         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2976         -1,
   2977         -1,
   2978     },
   2979 #endif /* chips */
   2980 
   2981 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2982     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2983     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2984     { /* SOC_REG_INT_XHOL_RX_PKT_MASK0r */
   2985         soc_block_list[9],
   2986         soc_genreg,
   2987         1,
   2988         0,
   2989         0x80d17,
   2990         0,
   2991         0,
   2992         1,
   2993         soc_XHOL_RX_PKT_MASK0r_fields,
   2994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2995         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2996         -1,
   2997         -1,
   2998     },
   2999 #endif /* chips */
   3000 
   3001 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   3002     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   3003     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   3004     { /* SOC_REG_INT_XHOL_RX_PKT_MASK1r */
   3005         soc_block_list[9],
   3006         soc_genreg,
   3007         1,
   3008         0,
   3009         0x80d18,
   3010         0,
   3011         0,
   3012         1,
   3013         soc_XHOL_RX_PKT_MASK1r_fields,
   3014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3016         -1,
   3017         -1,
   3018     },
   3019 #endif /* chips */
   3020 
   3021 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   3022     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   3023     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   3024     { /* SOC_REG_INT_XHOL_RX_PKT_MASK2r */
   3025         soc_block_list[9],
   3026         soc_genreg,
   3027         1,
   3028         0,
   3029         0x80d19,
   3030         0,
   3031         0,
   3032         1,
   3033         soc_XHOL_RX_PKT_MASK2r_fields,
   3034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3035         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3036         -1,
   3037         -1,
   3038     },
   3039 #endif /* chips */
   3040 
   3041 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   3042     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   3043     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   3044     { /* SOC_REG_INT_XHOL_RX_PKT_MASK3r */
   3045         soc_block_list[9],
   3046         soc_genreg,
   3047         1,
   3048         0,
   3049         0x80d1a,
   3050         0,
   3051         0,
   3052         1,
   3053         soc_XHOL_RX_PKT_MASK3r_fields,
   3054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3055         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3056         -1,
   3057         -1,
   3058     },
   3059 #endif /* chips */
   3060 
   3061 #if defined(BCM_56340_A0)
   3062     { /* SOC_REG_INT_XHOL_RX_PKT_MASK0_BCM56340_A0r */
   3063         soc_block_list[214],
   3064         soc_portreg,
   3065         1,
   3066         0,
   3067         0x24000,
   3068         0,
   3069         0,
   3070         1,
   3071         soc_XHOL_RX_PKT_MASK0_BCM56640_A0r_fields,
   3072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3073         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3074         -1,
   3075         -1,
   3076     },
   3077 #endif /* chips */
   3078 
   3079 #if defined(BCM_56640_A0)
   3080     { /* SOC_REG_INT_XHOL_RX_PKT_MASK0_BCM56640_A0r */
   3081         soc_block_list[212],
   3082         soc_portreg,
   3083         1,
   3084         0,
   3085         0x24000,
   3086         0,
   3087         0,
   3088         1,
   3089         soc_XHOL_RX_PKT_MASK0_BCM56640_A0r_fields,
   3090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3091         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3092         -1,
   3093         -1,
   3094     },
   3095 #endif /* chips */
   3096 
   3097 #if defined(BCM_56340_A0)
   3098     { /* SOC_REG_INT_XHOL_RX_PKT_MASK1_BCM56340_A0r */
   3099         soc_block_list[214],
   3100         soc_portreg,
   3101         1,
   3102         0,
   3103         0x24100,
   3104         0,
   3105         0,
   3106         1,
   3107         soc_XHOL_RX_PKT_MASK1_BCM56640_A0r_fields,
   3108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3110         -1,
   3111         -1,
   3112     },
   3113 #endif /* chips */
   3114 
   3115 #if defined(BCM_56640_A0)
   3116     { /* SOC_REG_INT_XHOL_RX_PKT_MASK1_BCM56640_A0r */
   3117         soc_block_list[212],
   3118         soc_portreg,
   3119         1,
   3120         0,
   3121         0x24100,
   3122         0,
   3123         0,
   3124         1,
   3125         soc_XHOL_RX_PKT_MASK1_BCM56640_A0r_fields,
   3126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3127         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3128         -1,
   3129         -1,
   3130     },
   3131 #endif /* chips */
   3132 
   3133 #if defined(BCM_56340_A0)
   3134     { /* SOC_REG_INT_XHOL_RX_PKT_MASK2_BCM56340_A0r */
   3135         soc_block_list[214],
   3136         soc_portreg,
   3137         1,
   3138         0,
   3139         0x24200,
   3140         0,
   3141         0,
   3142         1,
   3143         soc_XHOL_RX_PKT_MASK2_BCM56640_A0r_fields,
   3144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3145         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3146         -1,
   3147         -1,
   3148     },
   3149 #endif /* chips */
   3150 
   3151 #if defined(BCM_56640_A0)
   3152     { /* SOC_REG_INT_XHOL_RX_PKT_MASK2_BCM56640_A0r */
   3153         soc_block_list[212],
   3154         soc_portreg,
   3155         1,
   3156         0,
   3157         0x24200,
   3158         0,
   3159         0,
   3160         1,
   3161         soc_XHOL_RX_PKT_MASK2_BCM56640_A0r_fields,
   3162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3163         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3164         -1,
   3165         -1,
   3166     },
   3167 #endif /* chips */
   3168 
   3169 #if defined(BCM_56340_A0)
   3170     { /* SOC_REG_INT_XHOL_RX_PKT_MASK3_BCM56340_A0r */
   3171         soc_block_list[214],
   3172         soc_portreg,
   3173         1,
   3174         0,
   3175         0x24300,
   3176         0,
   3177         0,
   3178         1,
   3179         soc_XHOL_RX_PKT_MASK3_BCM56640_A0r_fields,
   3180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3182         -1,
   3183         -1,
   3184     },
   3185 #endif /* chips */
   3186 
   3187 #if defined(BCM_56640_A0)
   3188     { /* SOC_REG_INT_XHOL_RX_PKT_MASK3_BCM56640_A0r */
   3189         soc_block_list[212],
   3190         soc_portreg,
   3191         1,
   3192         0,
   3193         0x24300,
   3194         0,
   3195         0,
   3196         1,
   3197         soc_XHOL_RX_PKT_MASK3_BCM56640_A0r_fields,
   3198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3200         -1,
   3201         -1,
   3202     },
   3203 #endif /* chips */
   3204 
   3205 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   3206     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   3207     { /* SOC_REG_INT_XIBP_D0r */
   3208         soc_block_list[0],
   3209         soc_genreg,
   3210         1,
   3211         0,
   3212         0x80015,
   3213         0,
   3214         0,
   3215         1,
   3216         soc_XHOL_D0r_fields,
   3217         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3218         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3219         -1,
   3220         -1,
   3221     },
   3222 #endif /* chips */
   3223 
   3224 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   3225     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   3226     { /* SOC_REG_INT_XIBP_D1r */
   3227         soc_block_list[0],
   3228         soc_genreg,
   3229         1,
   3230         0,
   3231         0x80016,
   3232         0,
   3233         0,
   3234         1,
   3235         soc_XHOL_D1r_fields,
   3236         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
   3237         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3238         -1,
   3239         -1,
   3240     },
   3241 #endif /* chips */
   3242 
   3243 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   3244     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   3245     { /* SOC_REG_INT_XIBP_D2r */
   3246         soc_block_list[0],
   3247         soc_genreg,
   3248         1,
   3249         0,
   3250         0x80017,
   3251         0,
   3252         0,
   3253         1,
   3254         soc_XHOL_D2r_fields,
   3255         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   3256         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3257         -1,
   3258         -1,
   3259     },
   3260 #endif /* chips */
   3261 
   3262 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   3263     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   3264     { /* SOC_REG_INT_XIBP_D3r */
   3265         soc_block_list[0],
   3266         soc_genreg,
   3267         1,
   3268         0,
   3269         0x80018,
   3270         0,
   3271         0,
   3272         1,
   3273         soc_XHOL_D3r_fields,
   3274         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   3275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3276         -1,
   3277         -1,
   3278     },
   3279 #endif /* chips */
   3280 
   3281 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   3282     defined(BCM_56334_B0)
   3283     { /* SOC_REG_INT_XIBP_D0_BCM56334_A0r */
   3284         soc_block_list[14],
   3285         soc_portreg,
   3286         1,
   3287         0,
   3288         0x818,
   3289         0,
   3290         0,
   3291         1,
   3292         soc_XHOL_D0r_fields,
   3293         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3294         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3295         -1,
   3296         -1,
   3297     },
   3298 #endif /* chips */
   3299 
   3300 #if defined(BCM_56340_A0)
   3301     { /* SOC_REG_INT_XIBP_D0_BCM56340_A0r */
   3302         soc_block_list[214],
   3303         soc_portreg,
   3304         1,
   3305         0,
   3306         0x22700,
   3307         0,
   3308         0,
   3309         1,
   3310         soc_XHOL_D0_BCM56640_A0r_fields,
   3311         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3312         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3313         -1,
   3314         -1,
   3315     },
   3316 #endif /* chips */
   3317 
   3318 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3319     { /* SOC_REG_INT_XIBP_D0_BCM56440_A0r */
   3320         soc_block_list[83],
   3321         soc_genreg,
   3322         1,
   3323         0,
   3324         0x80231,
   3325         0,
   3326         0,
   3327         1,
   3328         soc_XHOL_D0r_fields,
   3329         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3330         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3331         -1,
   3332         -1,
   3333     },
   3334 #endif /* chips */
   3335 
   3336 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3337     defined(BCM_56450_B1)
   3338     { /* SOC_REG_INT_XIBP_D0_BCM56450_A0r */
   3339         soc_block_list[83],
   3340         soc_genreg,
   3341         1,
   3342         0,
   3343         0x2023100,
   3344         0,
   3345         0,
   3346         1,
   3347         soc_XHOL_D0_BCM56640_A0r_fields,
   3348         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3349         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3350         -1,
   3351         -1,
   3352     },
   3353 #endif /* chips */
   3354 
   3355 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   3356     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   3357     { /* SOC_REG_INT_XIBP_D0_BCM56624_A0r */
   3358         soc_block_list[204],
   3359         soc_portreg,
   3360         1,
   3361         0,
   3362         0x818,
   3363         0,
   3364         0,
   3365         1,
   3366         soc_XHOL_D0r_fields,
   3367         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3368         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3369         -1,
   3370         -1,
   3371     },
   3372 #endif /* chips */
   3373 
   3374 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   3375     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   3376     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   3377     { /* SOC_REG_INT_XIBP_D0_BCM56634_A0r */
   3378         soc_block_list[208],
   3379         soc_portreg,
   3380         1,
   3381         0,
   3382         0x818,
   3383         0,
   3384         0,
   3385         1,
   3386         soc_XHOL_D0r_fields,
   3387         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3388         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3389         -1,
   3390         -1,
   3391     },
   3392 #endif /* chips */
   3393 
   3394 #if defined(BCM_56640_A0)
   3395     { /* SOC_REG_INT_XIBP_D0_BCM56640_A0r */
   3396         soc_block_list[212],
   3397         soc_portreg,
   3398         1,
   3399         0,
   3400         0x22700,
   3401         0,
   3402         0,
   3403         1,
   3404         soc_XHOL_D0_BCM56640_A0r_fields,
   3405         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3406         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3407         -1,
   3408         -1,
   3409     },
   3410 #endif /* chips */
   3411 
   3412 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   3413     defined(BCM_56820_A0)
   3414     { /* SOC_REG_INT_XIBP_D0_BCM56800_A0r */
   3415         soc_block_list[9],
   3416         soc_portreg,
   3417         1,
   3418         0,
   3419         0x818,
   3420         0,
   3421         0,
   3422         1,
   3423         soc_XHOL_D0r_fields,
   3424         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3425         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3426         -1,
   3427         -1,
   3428     },
   3429 #endif /* chips */
   3430 
   3431 #if defined(BCM_56840_A0)
   3432     { /* SOC_REG_INT_XIBP_D0_BCM56840_A0r */
   3433         soc_block_list[16],
   3434         soc_portreg,
   3435         1,
   3436         0,
   3437         0x210,
   3438         0,
   3439         0,
   3440         1,
   3441         soc_XIBP_D0r_fields,
   3442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3443         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3444         -1,
   3445         -1,
   3446     },
   3447 #endif /* chips */
   3448 
   3449 #if defined(BCM_56840_B0)
   3450     { /* SOC_REG_INT_XIBP_D0_BCM56840_B0r */
   3451         soc_block_list[16],
   3452         soc_portreg,
   3453         1,
   3454         0,
   3455         0x210,
   3456         0,
   3457         0,
   3458         1,
   3459         soc_XIBP_D0r_fields,
   3460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3461         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3462         -1,
   3463         -1,
   3464     },
   3465 #endif /* chips */
   3466 
   3467 #if defined(BCM_88732_A0)
   3468     { /* SOC_REG_INT_XIBP_D0_BCM88732_A0r */
   3469         soc_block_list[16],
   3470         soc_portreg,
   3471         1,
   3472         0,
   3473         0x210,
   3474         0,
   3475         0,
   3476         1,
   3477         soc_XIBP_D0r_fields,
   3478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3479         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3480         -1,
   3481         -1,
   3482     },
   3483 #endif /* chips */
   3484 
   3485 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   3486     defined(BCM_56334_B0)
   3487     { /* SOC_REG_INT_XIBP_D1_BCM56334_A0r */
   3488         soc_block_list[14],
   3489         soc_portreg,
   3490         1,
   3491         0,
   3492         0x819,
   3493         0,
   3494         0,
   3495         1,
   3496         soc_XHOL_D1r_fields,
   3497         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
   3498         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3499         -1,
   3500         -1,
   3501     },
   3502 #endif /* chips */
   3503 
   3504 #if defined(BCM_56340_A0)
   3505     { /* SOC_REG_INT_XIBP_D1_BCM56340_A0r */
   3506         soc_block_list[214],
   3507         soc_portreg,
   3508         1,
   3509         0,
   3510         0x22800,
   3511         0,
   3512         0,
   3513         1,
   3514         soc_XHOL_D1_BCM56640_A0r_fields,
   3515         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
   3516         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3517         -1,
   3518         -1,
   3519     },
   3520 #endif /* chips */
   3521 
   3522 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3523     { /* SOC_REG_INT_XIBP_D1_BCM56440_A0r */
   3524         soc_block_list[83],
   3525         soc_genreg,
   3526         1,
   3527         0,
   3528         0x80232,
   3529         0,
   3530         0,
   3531         1,
   3532         soc_XHOL_D1r_fields,
   3533         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
   3534         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3535         -1,
   3536         -1,
   3537     },
   3538 #endif /* chips */
   3539 
   3540 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3541     defined(BCM_56450_B1)
   3542     { /* SOC_REG_INT_XIBP_D1_BCM56450_A0r */
   3543         soc_block_list[83],
   3544         soc_genreg,
   3545         1,
   3546         0,
   3547         0x2023200,
   3548         0,
   3549         0,
   3550         1,
   3551         soc_XHOL_D1_BCM56640_A0r_fields,
   3552         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
   3553         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3554         -1,
   3555         -1,
   3556     },
   3557 #endif /* chips */
   3558 
   3559 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   3560     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   3561     { /* SOC_REG_INT_XIBP_D1_BCM56624_A0r */
   3562         soc_block_list[204],
   3563         soc_portreg,
   3564         1,
   3565         0,
   3566         0x819,
   3567         0,
   3568         0,
   3569         1,
   3570         soc_XHOL_D1r_fields,
   3571         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
   3572         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3573         -1,
   3574         -1,
   3575     },
   3576 #endif /* chips */
   3577 
   3578 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   3579     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   3580     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   3581     { /* SOC_REG_INT_XIBP_D1_BCM56634_A0r */
   3582         soc_block_list[208],
   3583         soc_portreg,
   3584         1,
   3585         0,
   3586         0x819,
   3587         0,
   3588         0,
   3589         1,
   3590         soc_XHOL_D1r_fields,
   3591         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
   3592         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3593         -1,
   3594         -1,
   3595     },
   3596 #endif /* chips */
   3597 
   3598 #if defined(BCM_56640_A0)
   3599     { /* SOC_REG_INT_XIBP_D1_BCM56640_A0r */
   3600         soc_block_list[212],
   3601         soc_portreg,
   3602         1,
   3603         0,
   3604         0x22800,
   3605         0,
   3606         0,
   3607         1,
   3608         soc_XHOL_D1_BCM56640_A0r_fields,
   3609         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
   3610         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3611         -1,
   3612         -1,
   3613     },
   3614 #endif /* chips */
   3615 
   3616 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   3617     defined(BCM_56820_A0)
   3618     { /* SOC_REG_INT_XIBP_D1_BCM56800_A0r */
   3619         soc_block_list[9],
   3620         soc_portreg,
   3621         1,
   3622         0,
   3623         0x819,
   3624         0,
   3625         0,
   3626         1,
   3627         soc_XHOL_D1r_fields,
   3628         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
   3629         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3630         -1,
   3631         -1,
   3632     },
   3633 #endif /* chips */
   3634 
   3635 #if defined(BCM_56840_A0)
   3636     { /* SOC_REG_INT_XIBP_D1_BCM56840_A0r */
   3637         soc_block_list[16],
   3638         soc_portreg,
   3639         1,
   3640         0,
   3641         0x211,
   3642         0,
   3643         0,
   3644         1,
   3645         soc_XIBP_D1r_fields,
   3646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3647         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3648         -1,
   3649         -1,
   3650     },
   3651 #endif /* chips */
   3652 
   3653 #if defined(BCM_56840_B0)
   3654     { /* SOC_REG_INT_XIBP_D1_BCM56840_B0r */
   3655         soc_block_list[16],
   3656         soc_portreg,
   3657         1,
   3658         0,
   3659         0x211,
   3660         0,
   3661         0,
   3662         1,
   3663         soc_XIBP_D1r_fields,
   3664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3665         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3666         -1,
   3667         -1,
   3668     },
   3669 #endif /* chips */
   3670 
   3671 #if defined(BCM_88732_A0)
   3672     { /* SOC_REG_INT_XIBP_D1_BCM88732_A0r */
   3673         soc_block_list[16],
   3674         soc_portreg,
   3675         1,
   3676         0,
   3677         0x211,
   3678         0,
   3679         0,
   3680         1,
   3681         soc_XIBP_D1r_fields,
   3682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3683         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3684         -1,
   3685         -1,
   3686     },
   3687 #endif /* chips */
   3688 
   3689 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   3690     defined(BCM_56334_B0)
   3691     { /* SOC_REG_INT_XIBP_D2_BCM56334_A0r */
   3692         soc_block_list[14],
   3693         soc_portreg,
   3694         1,
   3695         0,
   3696         0x81a,
   3697         0,
   3698         0,
   3699         1,
   3700         soc_XHOL_D2r_fields,
   3701         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   3702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3703         -1,
   3704         -1,
   3705     },
   3706 #endif /* chips */
   3707 
   3708 #if defined(BCM_56340_A0)
   3709     { /* SOC_REG_INT_XIBP_D2_BCM56340_A0r */
   3710         soc_block_list[214],
   3711         soc_portreg,
   3712         1,
   3713         0,
   3714         0x22900,
   3715         0,
   3716         0,
   3717         1,
   3718         soc_XHOL_D2_BCM56640_A0r_fields,
   3719         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   3720         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3721         -1,
   3722         -1,
   3723     },
   3724 #endif /* chips */
   3725 
   3726 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3727     { /* SOC_REG_INT_XIBP_D2_BCM56440_A0r */
   3728         soc_block_list[83],
   3729         soc_genreg,
   3730         1,
   3731         0,
   3732         0x80233,
   3733         0,
   3734         0,
   3735         1,
   3736         soc_XHOL_D2r_fields,
   3737         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   3738         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3739         -1,
   3740         -1,
   3741     },
   3742 #endif /* chips */
   3743 
   3744 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3745     defined(BCM_56450_B1)
   3746     { /* SOC_REG_INT_XIBP_D2_BCM56450_A0r */
   3747         soc_block_list[83],
   3748         soc_genreg,
   3749         1,
   3750         0,
   3751         0x2023300,
   3752         0,
   3753         0,
   3754         1,
   3755         soc_XHOL_D2_BCM56640_A0r_fields,
   3756         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   3757         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3758         -1,
   3759         -1,
   3760     },
   3761 #endif /* chips */
   3762 
   3763 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   3764     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   3765     { /* SOC_REG_INT_XIBP_D2_BCM56624_A0r */
   3766         soc_block_list[204],
   3767         soc_portreg,
   3768         1,
   3769         0,
   3770         0x81a,
   3771         0,
   3772         0,
   3773         1,
   3774         soc_XHOL_D2r_fields,
   3775         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   3776         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3777         -1,
   3778         -1,
   3779     },
   3780 #endif /* chips */
   3781 
   3782 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   3783     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   3784     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   3785     { /* SOC_REG_INT_XIBP_D2_BCM56634_A0r */
   3786         soc_block_list[208],
   3787         soc_portreg,
   3788         1,
   3789         0,
   3790         0x81a,
   3791         0,
   3792         0,
   3793         1,
   3794         soc_XHOL_D2r_fields,
   3795         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   3796         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3797         -1,
   3798         -1,
   3799     },
   3800 #endif /* chips */
   3801 
   3802 #if defined(BCM_56640_A0)
   3803     { /* SOC_REG_INT_XIBP_D2_BCM56640_A0r */
   3804         soc_block_list[212],
   3805         soc_portreg,
   3806         1,
   3807         0,
   3808         0x22900,
   3809         0,
   3810         0,
   3811         1,
   3812         soc_XHOL_D2_BCM56640_A0r_fields,
   3813         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   3814         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3815         -1,
   3816         -1,
   3817     },
   3818 #endif /* chips */
   3819 
   3820 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   3821     defined(BCM_56820_A0)
   3822     { /* SOC_REG_INT_XIBP_D2_BCM56800_A0r */
   3823         soc_block_list[9],
   3824         soc_portreg,
   3825         1,
   3826         0,
   3827         0x81a,
   3828         0,
   3829         0,
   3830         1,
   3831         soc_XHOL_D2r_fields,
   3832         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   3833         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3834         -1,
   3835         -1,
   3836     },
   3837 #endif /* chips */
   3838 
   3839 #if defined(BCM_56840_A0)
   3840     { /* SOC_REG_INT_XIBP_D2_BCM56840_A0r */
   3841         soc_block_list[16],
   3842         soc_portreg,
   3843         1,
   3844         0,
   3845         0x212,
   3846         0,
   3847         0,
   3848         1,
   3849         soc_XIBP_D2r_fields,
   3850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3851         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3852         -1,
   3853         -1,
   3854     },
   3855 #endif /* chips */
   3856 
   3857 #if defined(BCM_56840_B0)
   3858     { /* SOC_REG_INT_XIBP_D2_BCM56840_B0r */
   3859         soc_block_list[16],
   3860         soc_portreg,
   3861         1,
   3862         0,
   3863         0x212,
   3864         0,
   3865         0,
   3866         1,
   3867         soc_XIBP_D2r_fields,
   3868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3869         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3870         -1,
   3871         -1,
   3872     },
   3873 #endif /* chips */
   3874 
   3875 #if defined(BCM_88732_A0)
   3876     { /* SOC_REG_INT_XIBP_D2_BCM88732_A0r */
   3877         soc_block_list[16],
   3878         soc_portreg,
   3879         1,
   3880         0,
   3881         0x212,
   3882         0,
   3883         0,
   3884         1,
   3885         soc_XIBP_D2r_fields,
   3886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3887         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3888         -1,
   3889         -1,
   3890     },
   3891 #endif /* chips */
   3892 
   3893 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   3894     defined(BCM_56334_B0)
   3895     { /* SOC_REG_INT_XIBP_D3_BCM56334_A0r */
   3896         soc_block_list[14],
   3897         soc_portreg,
   3898         1,
   3899         0,
   3900         0x81b,
   3901         0,
   3902         0,
   3903         1,
   3904         soc_XHOL_D3r_fields,
   3905         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   3906         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3907         -1,
   3908         -1,
   3909     },
   3910 #endif /* chips */
   3911 
   3912 #if defined(BCM_56340_A0)
   3913     { /* SOC_REG_INT_XIBP_D3_BCM56340_A0r */
   3914         soc_block_list[214],
   3915         soc_portreg,
   3916         1,
   3917         0,
   3918         0x22a00,
   3919         0,
   3920         0,
   3921         1,
   3922         soc_XHOL_D3_BCM56640_A0r_fields,
   3923         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   3924         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3925         -1,
   3926         -1,
   3927     },
   3928 #endif /* chips */
   3929 
   3930 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3931     { /* SOC_REG_INT_XIBP_D3_BCM56440_A0r */
   3932         soc_block_list[83],
   3933         soc_genreg,
   3934         1,
   3935         0,
   3936         0x80234,
   3937         0,
   3938         0,
   3939         1,
   3940         soc_XHOL_D3r_fields,
   3941         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   3942         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3943         -1,
   3944         -1,
   3945     },
   3946 #endif /* chips */
   3947 
   3948 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3949     defined(BCM_56450_B1)
   3950     { /* SOC_REG_INT_XIBP_D3_BCM56450_A0r */
   3951         soc_block_list[83],
   3952         soc_genreg,
   3953         1,
   3954         0,
   3955         0x2023400,
   3956         0,
   3957         0,
   3958         1,
   3959         soc_XHOL_D3_BCM56640_A0r_fields,
   3960         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   3961         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3962         -1,
   3963         -1,
   3964     },
   3965 #endif /* chips */
   3966 
   3967 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   3968     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   3969     { /* SOC_REG_INT_XIBP_D3_BCM56624_A0r */
   3970         soc_block_list[204],
   3971         soc_portreg,
   3972         1,
   3973         0,
   3974         0x81b,
   3975         0,
   3976         0,
   3977         1,
   3978         soc_XHOL_D3r_fields,
   3979         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   3980         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3981         -1,
   3982         -1,
   3983     },
   3984 #endif /* chips */
   3985 
   3986 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   3987     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   3988     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   3989     { /* SOC_REG_INT_XIBP_D3_BCM56634_A0r */
   3990         soc_block_list[208],
   3991         soc_portreg,
   3992         1,
   3993         0,
   3994         0x81b,
   3995         0,
   3996         0,
   3997         1,
   3998         soc_XHOL_D3r_fields,
   3999         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   4000         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4001         -1,
   4002         -1,
   4003     },
   4004 #endif /* chips */
   4005 
   4006 #if defined(BCM_56640_A0)
   4007     { /* SOC_REG_INT_XIBP_D3_BCM56640_A0r */
   4008         soc_block_list[212],
   4009         soc_portreg,
   4010         1,
   4011         0,
   4012         0x22a00,
   4013         0,
   4014         0,
   4015         1,
   4016         soc_XHOL_D3_BCM56640_A0r_fields,
   4017         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   4018         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4019         -1,
   4020         -1,
   4021     },
   4022 #endif /* chips */
   4023 
   4024 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   4025     defined(BCM_56820_A0)
   4026     { /* SOC_REG_INT_XIBP_D3_BCM56800_A0r */
   4027         soc_block_list[9],
   4028         soc_portreg,
   4029         1,
   4030         0,
   4031         0x81b,
   4032         0,
   4033         0,
   4034         1,
   4035         soc_XHOL_D3r_fields,
   4036         SOC_RESET_VAL_DEC(0x70000000, 0x00000000)
   4037         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4038         -1,
   4039         -1,
   4040     },
   4041 #endif /* chips */
   4042 
   4043 #if defined(BCM_56840_A0)
   4044     { /* SOC_REG_INT_XIBP_D3_BCM56840_A0r */
   4045         soc_block_list[16],
   4046         soc_portreg,
   4047         1,
   4048         0,
   4049         0x213,
   4050         0,
   4051         0,
   4052         1,
   4053         soc_XIBP_D3r_fields,
   4054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4055         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4056         -1,
   4057         -1,
   4058     },
   4059 #endif /* chips */
   4060 
   4061 #if defined(BCM_56840_B0)
   4062     { /* SOC_REG_INT_XIBP_D3_BCM56840_B0r */
   4063         soc_block_list[16],
   4064         soc_portreg,
   4065         1,
   4066         0,
   4067         0x213,
   4068         0,
   4069         0,
   4070         1,
   4071         soc_XIBP_D3r_fields,
   4072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4073         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4074         -1,
   4075         -1,
   4076     },
   4077 #endif /* chips */
   4078 
   4079 #if defined(BCM_88732_A0)
   4080     { /* SOC_REG_INT_XIBP_D3_BCM88732_A0r */
   4081         soc_block_list[16],
   4082         soc_portreg,
   4083         1,
   4084         0,
   4085         0x213,
   4086         0,
   4087         0,
   4088         1,
   4089         soc_XIBP_D3r_fields,
   4090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4091         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4092         -1,
   4093         -1,
   4094     },
   4095 #endif /* chips */
   4096 
   4097 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   4098     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   4099     { /* SOC_REG_INT_XIBP_MH0r */
   4100         soc_block_list[0],
   4101         soc_genreg,
   4102         1,
   4103         0,
   4104         0x80012,
   4105         0,
   4106         0,
   4107         1,
   4108         soc_XHOL_MH0r_fields,
   4109         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   4110         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4111         -1,
   4112         -1,
   4113     },
   4114 #endif /* chips */
   4115 
   4116 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   4117     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   4118     { /* SOC_REG_INT_XIBP_MH1r */
   4119         soc_block_list[0],
   4120         soc_genreg,
   4121         1,
   4122         0,
   4123         0x80013,
   4124         0,
   4125         0,
   4126         1,
   4127         soc_XIBP_MH1r_fields,
   4128         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4129         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4130         -1,
   4131         -1,
   4132     },
   4133 #endif /* chips */
   4134 
   4135 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   4136     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   4137     { /* SOC_REG_INT_XIBP_MH2r */
   4138         soc_block_list[0],
   4139         soc_genreg,
   4140         1,
   4141         0,
   4142         0x80014,
   4143         0,
   4144         0,
   4145         1,
   4146         soc_XHOL_MH2r_fields,
   4147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4148         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4149         -1,
   4150         -1,
   4151     },
   4152 #endif /* chips */
   4153 
   4154 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   4155     defined(BCM_56820_A0)
   4156     { /* SOC_REG_INT_XIBP_MH3r */
   4157         soc_block_list[9],
   4158         soc_portreg,
   4159         1,
   4160         0,
   4161         0x817,
   4162         0,
   4163         0,
   4164         1,
   4165         soc_XHOL_MH3r_fields,
   4166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4168         -1,
   4169         -1,
   4170     },
   4171 #endif /* chips */
   4172 
   4173 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   4174     defined(BCM_56334_B0)
   4175     { /* SOC_REG_INT_XIBP_MH0_BCM56334_A0r */
   4176         soc_block_list[14],
   4177         soc_portreg,
   4178         1,
   4179         0,
   4180         0x814,
   4181         0,
   4182         0,
   4183         1,
   4184         soc_XHOL_MH0r_fields,
   4185         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   4186         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4187         -1,
   4188         -1,
   4189     },
   4190 #endif /* chips */
   4191 
   4192 #if defined(BCM_56340_A0)
   4193     { /* SOC_REG_INT_XIBP_MH0_BCM56340_A0r */
   4194         soc_block_list[214],
   4195         soc_portreg,
   4196         1,
   4197         0,
   4198         0x22300,
   4199         0,
   4200         0,
   4201         1,
   4202         soc_XHOL_MH0_BCM56640_A0r_fields,
   4203         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   4204         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4205         -1,
   4206         -1,
   4207     },
   4208 #endif /* chips */
   4209 
   4210 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4211     { /* SOC_REG_INT_XIBP_MH0_BCM56440_A0r */
   4212         soc_block_list[83],
   4213         soc_genreg,
   4214         1,
   4215         0,
   4216         0x8022d,
   4217         0,
   4218         0,
   4219         1,
   4220         soc_XHOL_MH0r_fields,
   4221         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   4222         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4223         -1,
   4224         -1,
   4225     },
   4226 #endif /* chips */
   4227 
   4228 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4229     defined(BCM_56450_B1)
   4230     { /* SOC_REG_INT_XIBP_MH0_BCM56450_A0r */
   4231         soc_block_list[83],
   4232         soc_genreg,
   4233         1,
   4234         0,
   4235         0x2022d00,
   4236         0,
   4237         0,
   4238         1,
   4239         soc_XHOL_MH0_BCM56640_A0r_fields,
   4240         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   4241         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4242         -1,
   4243         -1,
   4244     },
   4245 #endif /* chips */
   4246 
   4247 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   4248     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   4249     { /* SOC_REG_INT_XIBP_MH0_BCM56624_A0r */
   4250         soc_block_list[204],
   4251         soc_portreg,
   4252         1,
   4253         0,
   4254         0x814,
   4255         0,
   4256         0,
   4257         1,
   4258         soc_XHOL_MH0r_fields,
   4259         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   4260         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4261         -1,
   4262         -1,
   4263     },
   4264 #endif /* chips */
   4265 
   4266 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   4267     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   4268     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   4269     { /* SOC_REG_INT_XIBP_MH0_BCM56634_A0r */
   4270         soc_block_list[208],
   4271         soc_portreg,
   4272         1,
   4273         0,
   4274         0x814,
   4275         0,
   4276         0,
   4277         1,
   4278         soc_XHOL_MH0r_fields,
   4279         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   4280         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4281         -1,
   4282         -1,
   4283     },
   4284 #endif /* chips */
   4285 
   4286 #if defined(BCM_56640_A0)
   4287     { /* SOC_REG_INT_XIBP_MH0_BCM56640_A0r */
   4288         soc_block_list[212],
   4289         soc_portreg,
   4290         1,
   4291         0,
   4292         0x22300,
   4293         0,
   4294         0,
   4295         1,
   4296         soc_XHOL_MH0_BCM56640_A0r_fields,
   4297         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   4298         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4299         -1,
   4300         -1,
   4301     },
   4302 #endif /* chips */
   4303 
   4304 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   4305     defined(BCM_56820_A0)
   4306     { /* SOC_REG_INT_XIBP_MH0_BCM56800_A0r */
   4307         soc_block_list[9],
   4308         soc_portreg,
   4309         1,
   4310         0,
   4311         0x814,
   4312         0,
   4313         0,
   4314         1,
   4315         soc_XHOL_MH0r_fields,
   4316         SOC_RESET_VAL_DEC(0xfb800ffe, 0x00000000)
   4317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4318         -1,
   4319         -1,
   4320     },
   4321 #endif /* chips */
   4322 
   4323 #if defined(BCM_56840_A0)
   4324     { /* SOC_REG_INT_XIBP_MH0_BCM56840_A0r */
   4325         soc_block_list[16],
   4326         soc_portreg,
   4327         1,
   4328         0,
   4329         0x20c,
   4330         0,
   4331         0,
   4332         1,
   4333         soc_XIBP_MH0r_fields,
   4334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4335         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4336         -1,
   4337         -1,
   4338     },
   4339 #endif /* chips */
   4340 
   4341 #if defined(BCM_56840_B0)
   4342     { /* SOC_REG_INT_XIBP_MH0_BCM56840_B0r */
   4343         soc_block_list[16],
   4344         soc_portreg,
   4345         1,
   4346         0,
   4347         0x20c,
   4348         0,
   4349         0,
   4350         1,
   4351         soc_XIBP_MH0r_fields,
   4352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4353         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4354         -1,
   4355         -1,
   4356     },
   4357 #endif /* chips */
   4358 
   4359 #if defined(BCM_88732_A0)
   4360     { /* SOC_REG_INT_XIBP_MH0_BCM88732_A0r */
   4361         soc_block_list[16],
   4362         soc_portreg,
   4363         1,
   4364         0,
   4365         0x20c,
   4366         0,
   4367         0,
   4368         1,
   4369         soc_XIBP_MH0r_fields,
   4370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4372         -1,
   4373         -1,
   4374     },
   4375 #endif /* chips */
   4376 
   4377 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   4378     defined(BCM_56334_B0)
   4379     { /* SOC_REG_INT_XIBP_MH1_BCM56334_A0r */
   4380         soc_block_list[14],
   4381         soc_portreg,
   4382         1,
   4383         0,
   4384         0x815,
   4385         0,
   4386         0,
   4387         1,
   4388         soc_XIBP_MH1r_fields,
   4389         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4390         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4391         -1,
   4392         -1,
   4393     },
   4394 #endif /* chips */
   4395 
   4396 #if defined(BCM_56340_A0)
   4397     { /* SOC_REG_INT_XIBP_MH1_BCM56340_A0r */
   4398         soc_block_list[214],
   4399         soc_portreg,
   4400         1,
   4401         0,
   4402         0x22400,
   4403         0,
   4404         0,
   4405         1,
   4406         soc_XIBP_MH1_BCM56640_A0r_fields,
   4407         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4408         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4409         -1,
   4410         -1,
   4411     },
   4412 #endif /* chips */
   4413 
   4414 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4415     { /* SOC_REG_INT_XIBP_MH1_BCM56440_A0r */
   4416         soc_block_list[83],
   4417         soc_genreg,
   4418         1,
   4419         0,
   4420         0x8022e,
   4421         0,
   4422         0,
   4423         1,
   4424         soc_XIBP_MH1r_fields,
   4425         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4426         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4427         -1,
   4428         -1,
   4429     },
   4430 #endif /* chips */
   4431 
   4432 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4433     defined(BCM_56450_B1)
   4434     { /* SOC_REG_INT_XIBP_MH1_BCM56450_A0r */
   4435         soc_block_list[83],
   4436         soc_genreg,
   4437         1,
   4438         0,
   4439         0x2022e00,
   4440         0,
   4441         0,
   4442         1,
   4443         soc_XIBP_MH1_BCM56640_A0r_fields,
   4444         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4446         -1,
   4447         -1,
   4448     },
   4449 #endif /* chips */
   4450 
   4451 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   4452     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   4453     { /* SOC_REG_INT_XIBP_MH1_BCM56624_A0r */
   4454         soc_block_list[204],
   4455         soc_portreg,
   4456         1,
   4457         0,
   4458         0x815,
   4459         0,
   4460         0,
   4461         1,
   4462         soc_XIBP_MH1r_fields,
   4463         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4464         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4465         -1,
   4466         -1,
   4467     },
   4468 #endif /* chips */
   4469 
   4470 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   4471     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   4472     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   4473     { /* SOC_REG_INT_XIBP_MH1_BCM56634_A0r */
   4474         soc_block_list[208],
   4475         soc_portreg,
   4476         1,
   4477         0,
   4478         0x815,
   4479         0,
   4480         0,
   4481         1,
   4482         soc_XIBP_MH1r_fields,
   4483         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4484         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4485         -1,
   4486         -1,
   4487     },
   4488 #endif /* chips */
   4489 
   4490 #if defined(BCM_56640_A0)
   4491     { /* SOC_REG_INT_XIBP_MH1_BCM56640_A0r */
   4492         soc_block_list[212],
   4493         soc_portreg,
   4494         1,
   4495         0,
   4496         0x22400,
   4497         0,
   4498         0,
   4499         1,
   4500         soc_XIBP_MH1_BCM56640_A0r_fields,
   4501         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4502         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4503         -1,
   4504         -1,
   4505     },
   4506 #endif /* chips */
   4507 
   4508 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   4509     defined(BCM_56820_A0)
   4510     { /* SOC_REG_INT_XIBP_MH1_BCM56800_A0r */
   4511         soc_block_list[9],
   4512         soc_portreg,
   4513         1,
   4514         0,
   4515         0x815,
   4516         0,
   4517         0,
   4518         1,
   4519         soc_XIBP_MH1r_fields,
   4520         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4521         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4522         -1,
   4523         -1,
   4524     },
   4525 #endif /* chips */
   4526 
   4527 #if defined(BCM_56840_A0)
   4528     { /* SOC_REG_INT_XIBP_MH1_BCM56840_A0r */
   4529         soc_block_list[16],
   4530         soc_portreg,
   4531         1,
   4532         0,
   4533         0x20d,
   4534         0,
   4535         0,
   4536         1,
   4537         soc_XIBP_MH1_BCM56840_A0r_fields,
   4538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4540         -1,
   4541         -1,
   4542     },
   4543 #endif /* chips */
   4544 
   4545 #if defined(BCM_56840_B0)
   4546     { /* SOC_REG_INT_XIBP_MH1_BCM56840_B0r */
   4547         soc_block_list[16],
   4548         soc_portreg,
   4549         1,
   4550         0,
   4551         0x20d,
   4552         0,
   4553         0,
   4554         1,
   4555         soc_XIBP_MH1_BCM56840_A0r_fields,
   4556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4558         -1,
   4559         -1,
   4560     },
   4561 #endif /* chips */
   4562 
   4563 #if defined(BCM_88732_A0)
   4564     { /* SOC_REG_INT_XIBP_MH1_BCM88732_A0r */
   4565         soc_block_list[16],
   4566         soc_portreg,
   4567         1,
   4568         0,
   4569         0x20d,
   4570         0,
   4571         0,
   4572         1,
   4573         soc_XIBP_MH1_BCM56840_A0r_fields,
   4574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4575         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4576         -1,
   4577         -1,
   4578     },
   4579 #endif /* chips */
   4580 
   4581 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   4582     defined(BCM_56334_B0)
   4583     { /* SOC_REG_INT_XIBP_MH2_BCM56334_A0r */
   4584         soc_block_list[14],
   4585         soc_portreg,
   4586         1,
   4587         0,
   4588         0x816,
   4589         0,
   4590         0,
   4591         1,
   4592         soc_XHOL_MH2r_fields,
   4593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4594         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4595         -1,
   4596         -1,
   4597     },
   4598 #endif /* chips */
   4599 
   4600 #if defined(BCM_56340_A0)
   4601     { /* SOC_REG_INT_XIBP_MH2_BCM56340_A0r */
   4602         soc_block_list[214],
   4603         soc_portreg,
   4604         1,
   4605         0,
   4606         0x22500,
   4607         0,
   4608         0,
   4609         1,
   4610         soc_XHOL_MH2_BCM56640_A0r_fields,
   4611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4612         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4613         -1,
   4614         -1,
   4615     },
   4616 #endif /* chips */
   4617 
   4618 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4619     { /* SOC_REG_INT_XIBP_MH2_BCM56440_A0r */
   4620         soc_block_list[83],
   4621         soc_genreg,
   4622         1,
   4623         0,
   4624         0x8022f,
   4625         0,
   4626         0,
   4627         1,
   4628         soc_XHOL_MH2r_fields,
   4629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4630         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4631         -1,
   4632         -1,
   4633     },
   4634 #endif /* chips */
   4635 
   4636 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4637     defined(BCM_56450_B1)
   4638     { /* SOC_REG_INT_XIBP_MH2_BCM56450_A0r */
   4639         soc_block_list[83],
   4640         soc_genreg,
   4641         1,
   4642         0,
   4643         0x2022f00,
   4644         0,
   4645         0,
   4646         1,
   4647         soc_XHOL_MH2_BCM56640_A0r_fields,
   4648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4649         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4650         -1,
   4651         -1,
   4652     },
   4653 #endif /* chips */
   4654 
   4655 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   4656     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   4657     { /* SOC_REG_INT_XIBP_MH2_BCM56624_A0r */
   4658         soc_block_list[204],
   4659         soc_portreg,
   4660         1,
   4661         0,
   4662         0x816,
   4663         0,
   4664         0,
   4665         1,
   4666         soc_XHOL_MH2r_fields,
   4667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4668         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4669         -1,
   4670         -1,
   4671     },
   4672 #endif /* chips */
   4673 
   4674 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   4675     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   4676     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   4677     { /* SOC_REG_INT_XIBP_MH2_BCM56634_A0r */
   4678         soc_block_list[208],
   4679         soc_portreg,
   4680         1,
   4681         0,
   4682         0x816,
   4683         0,
   4684         0,
   4685         1,
   4686         soc_XHOL_MH2r_fields,
   4687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4689         -1,
   4690         -1,
   4691     },
   4692 #endif /* chips */
   4693 
   4694 #if defined(BCM_56640_A0)
   4695     { /* SOC_REG_INT_XIBP_MH2_BCM56640_A0r */
   4696         soc_block_list[212],
   4697         soc_portreg,
   4698         1,
   4699         0,
   4700         0x22500,
   4701         0,
   4702         0,
   4703         1,
   4704         soc_XHOL_MH2_BCM56640_A0r_fields,
   4705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4706         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4707         -1,
   4708         -1,
   4709     },
   4710 #endif /* chips */
   4711 
   4712 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   4713     defined(BCM_56820_A0)
   4714     { /* SOC_REG_INT_XIBP_MH2_BCM56800_A0r */
   4715         soc_block_list[9],
   4716         soc_portreg,
   4717         1,
   4718         0,
   4719         0x816,
   4720         0,
   4721         0,
   4722         1,
   4723         soc_XHOL_MH2r_fields,
   4724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4726         -1,
   4727         -1,
   4728     },
   4729 #endif /* chips */
   4730 
   4731 #if defined(BCM_56840_A0)
   4732     { /* SOC_REG_INT_XIBP_MH2_BCM56840_A0r */
   4733         soc_block_list[16],
   4734         soc_portreg,
   4735         1,
   4736         0,
   4737         0x20e,
   4738         0,
   4739         0,
   4740         1,
   4741         soc_XIBP_MH2r_fields,
   4742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4743         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4744         -1,
   4745         -1,
   4746     },
   4747 #endif /* chips */
   4748 
   4749 #if defined(BCM_56840_B0)
   4750     { /* SOC_REG_INT_XIBP_MH2_BCM56840_B0r */
   4751         soc_block_list[16],
   4752         soc_portreg,
   4753         1,
   4754         0,
   4755         0x20e,
   4756         0,
   4757         0,
   4758         1,
   4759         soc_XIBP_MH2r_fields,
   4760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4762         -1,
   4763         -1,
   4764     },
   4765 #endif /* chips */
   4766 
   4767 #if defined(BCM_88732_A0)
   4768     { /* SOC_REG_INT_XIBP_MH2_BCM88732_A0r */
   4769         soc_block_list[16],
   4770         soc_portreg,
   4771         1,
   4772         0,
   4773         0x20e,
   4774         0,
   4775         0,
   4776         1,
   4777         soc_XIBP_MH2r_fields,
   4778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4779         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4780         -1,
   4781         -1,
   4782     },
   4783 #endif /* chips */
   4784 
   4785 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   4786     defined(BCM_56334_B0)
   4787     { /* SOC_REG_INT_XIBP_MH3_BCM56334_A0r */
   4788         soc_block_list[14],
   4789         soc_portreg,
   4790         1,
   4791         0,
   4792         0x817,
   4793         0,
   4794         0,
   4795         1,
   4796         soc_XHOL_MH3r_fields,
   4797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4798         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4799         -1,
   4800         -1,
   4801     },
   4802 #endif /* chips */
   4803 
   4804 #if defined(BCM_56340_A0)
   4805     { /* SOC_REG_INT_XIBP_MH3_BCM56340_A0r */
   4806         soc_block_list[214],
   4807         soc_portreg,
   4808         1,
   4809         0,
   4810         0x22600,
   4811         0,
   4812         0,
   4813         1,
   4814         soc_XHOL_MH3_BCM56640_A0r_fields,
   4815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4816         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4817         -1,
   4818         -1,
   4819     },
   4820 #endif /* chips */
   4821 
   4822 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4823     { /* SOC_REG_INT_XIBP_MH3_BCM56440_A0r */
   4824         soc_block_list[83],
   4825         soc_genreg,
   4826         1,
   4827         0,
   4828         0x80230,
   4829         0,
   4830         0,
   4831         1,
   4832         soc_XHOL_MH3r_fields,
   4833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4834         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4835         -1,
   4836         -1,
   4837     },
   4838 #endif /* chips */
   4839 
   4840 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4841     defined(BCM_56450_B1)
   4842     { /* SOC_REG_INT_XIBP_MH3_BCM56450_A0r */
   4843         soc_block_list[83],
   4844         soc_genreg,
   4845         1,
   4846         0,
   4847         0x2023000,
   4848         0,
   4849         0,
   4850         1,
   4851         soc_XHOL_MH3_BCM56640_A0r_fields,
   4852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4853         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4854         -1,
   4855         -1,
   4856     },
   4857 #endif /* chips */
   4858 
   4859 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   4860     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   4861     { /* SOC_REG_INT_XIBP_MH3_BCM56624_A0r */
   4862         soc_block_list[204],
   4863         soc_portreg,
   4864         1,
   4865         0,
   4866         0x817,
   4867         0,
   4868         0,
   4869         1,
   4870         soc_XHOL_MH3r_fields,
   4871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4872         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4873         -1,
   4874         -1,
   4875     },
   4876 #endif /* chips */
   4877 
   4878 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   4879     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   4880     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   4881     { /* SOC_REG_INT_XIBP_MH3_BCM56634_A0r */
   4882         soc_block_list[208],
   4883         soc_portreg,
   4884         1,
   4885         0,
   4886         0x817,
   4887         0,
   4888         0,
   4889         1,
   4890         soc_XHOL_MH3r_fields,
   4891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4893         -1,
   4894         -1,
   4895     },
   4896 #endif /* chips */
   4897 
   4898 #if defined(BCM_56640_A0)
   4899     { /* SOC_REG_INT_XIBP_MH3_BCM56640_A0r */
   4900         soc_block_list[212],
   4901         soc_portreg,
   4902         1,
   4903         0,
   4904         0x22600,
   4905         0,
   4906         0,
   4907         1,
   4908         soc_XHOL_MH3_BCM56640_A0r_fields,
   4909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4910         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4911         -1,
   4912         -1,
   4913     },
   4914 #endif /* chips */
   4915 
   4916 #if defined(BCM_56840_A0)
   4917     { /* SOC_REG_INT_XIBP_MH3_BCM56840_A0r */
   4918         soc_block_list[16],
   4919         soc_portreg,
   4920         1,
   4921         0,
   4922         0x20f,
   4923         0,
   4924         0,
   4925         1,
   4926         soc_XIBP_MH3r_fields,
   4927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4928         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4929         -1,
   4930         -1,
   4931     },
   4932 #endif /* chips */
   4933 
   4934 #if defined(BCM_56840_B0)
   4935     { /* SOC_REG_INT_XIBP_MH3_BCM56840_B0r */
   4936         soc_block_list[16],
   4937         soc_portreg,
   4938         1,
   4939         0,
   4940         0x20f,
   4941         0,
   4942         0,
   4943         1,
   4944         soc_XIBP_MH3r_fields,
   4945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4946         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4947         -1,
   4948         -1,
   4949     },
   4950 #endif /* chips */
   4951 
   4952 #if defined(BCM_88732_A0)
   4953     { /* SOC_REG_INT_XIBP_MH3_BCM88732_A0r */
   4954         soc_block_list[16],
   4955         soc_portreg,
   4956         1,
   4957         0,
   4958         0x20f,
   4959         0,
   4960         0,
   4961         1,
   4962         soc_XIBP_MH3r_fields,
   4963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4964         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4965         -1,
   4966         -1,
   4967     },
   4968 #endif /* chips */
   4969 
   4970 #if defined(BCM_56560_A0)
   4971     { /* SOC_REG_INT_XLMAC_B0_CLEAR_ECC_STATUSr */
   4972         soc_block_list[128],
   4973         soc_portreg,
   4974         1,
   4975         0,
   4976         0x63400,
   4977         SOC_REG_FLAG_64_BITS,
   4978         0,
   4979         4,
   4980         soc_XLMAC_B0_CLEAR_ECC_STATUSr_fields,
   4981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4982         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4983         -1,
   4984         -1,
   4985     },
   4986 #endif /* chips */
   4987 
   4988 #if defined(BCM_56560_A0)
   4989     { /* SOC_REG_INT_XLMAC_B0_CLEAR_FIFO_STATUSr */
   4990         soc_block_list[128],
   4991         soc_portreg,
   4992         1,
   4993         0,
   4994         0x61800,
   4995         SOC_REG_FLAG_64_BITS,
   4996         0,
   4997         8,
   4998         soc_CLMAC_CLEAR_FIFO_STATUSr_fields,
   4999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5000         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   5001         -1,
   5002         -1,
   5003     },
   5004 #endif /* chips */
   5005 
   5006 #if defined(BCM_56560_A0)
   5007     { /* SOC_REG_INT_XLMAC_B0_CLEAR_RX_LSS_STATUSr */
   5008         soc_block_list[128],
   5009         soc_portreg,
   5010         1,
   5011         0,
   5012         0x60c00,
   5013         SOC_REG_FLAG_64_BITS,
   5014         0,
   5015         3,
   5016         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   5017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5018         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5019         -1,
   5020         -1,
   5021     },
   5022 #endif /* chips */
   5023 
   5024 #if defined(BCM_56560_A0)
   5025     { /* SOC_REG_INT_XLMAC_B0_CTRLr */
   5026         soc_block_list[128],
   5027         soc_portreg,
   5028         1,
   5029         0,
   5030         0x60000,
   5031         SOC_REG_FLAG_64_BITS,
   5032         0,
   5033         15,
   5034         soc_XLMAC_B0_CTRLr_fields,
   5035         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   5036         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   5037         -1,
   5038         -1,
   5039     },
   5040 #endif /* chips */
   5041 
   5042 #if defined(BCM_56560_A0)
   5043     { /* SOC_REG_INT_XLMAC_B0_E2ECC_DATA_HDR_0r */
   5044         soc_block_list[128],
   5045         soc_portreg,
   5046         1,
   5047         0,
   5048         0x62600,
   5049         SOC_REG_FLAG_64_BITS,
   5050         0,
   5051         3,
   5052         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   5053         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   5054         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5055         -1,
   5056         -1,
   5057     },
   5058 #endif /* chips */
   5059 
   5060 #if defined(BCM_56560_A0)
   5061     { /* SOC_REG_INT_XLMAC_B0_E2ECC_DATA_HDR_1r */
   5062         soc_block_list[128],
   5063         soc_portreg,
   5064         1,
   5065         0,
   5066         0x62700,
   5067         SOC_REG_FLAG_64_BITS,
   5068         0,
   5069         3,
   5070         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   5071         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   5072         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5073         -1,
   5074         -1,
   5075     },
   5076 #endif /* chips */
   5077 
   5078 #if defined(BCM_56560_A0)
   5079     { /* SOC_REG_INT_XLMAC_B0_E2ECC_MODULE_HDR_0r */
   5080         soc_block_list[128],
   5081         soc_portreg,
   5082         1,
   5083         0,
   5084         0x62400,
   5085         SOC_REG_FLAG_64_BITS,
   5086         0,
   5087         3,
   5088         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   5089         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   5090         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5091         -1,
   5092         -1,
   5093     },
   5094 #endif /* chips */
   5095 
   5096 #if defined(BCM_56560_A0)
   5097     { /* SOC_REG_INT_XLMAC_B0_E2ECC_MODULE_HDR_1r */
   5098         soc_block_list[128],
   5099         soc_portreg,
   5100         1,
   5101         0,
   5102         0x62500,
   5103         SOC_REG_FLAG_64_BITS,
   5104         0,
   5105         3,
   5106         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   5107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5108         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5109         -1,
   5110         -1,
   5111     },
   5112 #endif /* chips */
   5113 
   5114 #if defined(BCM_56560_A0)
   5115     { /* SOC_REG_INT_XLMAC_B0_E2EFC_DATA_HDR_0r */
   5116         soc_block_list[128],
   5117         soc_portreg,
   5118         1,
   5119         0,
   5120         0x62a00,
   5121         SOC_REG_FLAG_64_BITS,
   5122         0,
   5123         3,
   5124         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   5125         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   5126         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5127         -1,
   5128         -1,
   5129     },
   5130 #endif /* chips */
   5131 
   5132 #if defined(BCM_56560_A0)
   5133     { /* SOC_REG_INT_XLMAC_B0_E2EFC_DATA_HDR_1r */
   5134         soc_block_list[128],
   5135         soc_portreg,
   5136         1,
   5137         0,
   5138         0x62b00,
   5139         SOC_REG_FLAG_64_BITS,
   5140         0,
   5141         3,
   5142         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   5143         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   5144         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5145         -1,
   5146         -1,
   5147     },
   5148 #endif /* chips */
   5149 
   5150 #if defined(BCM_56560_A0)
   5151     { /* SOC_REG_INT_XLMAC_B0_E2EFC_MODULE_HDR_0r */
   5152         soc_block_list[128],
   5153         soc_portreg,
   5154         1,
   5155         0,
   5156         0x62800,
   5157         SOC_REG_FLAG_64_BITS,
   5158         0,
   5159         3,
   5160         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
   5161         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
   5162         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5163         -1,
   5164         -1,
   5165     },
   5166 #endif /* chips */
   5167 
   5168 #if defined(BCM_56560_A0)
   5169     { /* SOC_REG_INT_XLMAC_B0_E2EFC_MODULE_HDR_1r */
   5170         soc_block_list[128],
   5171         soc_portreg,
   5172         1,
   5173         0,
   5174         0x62900,
   5175         SOC_REG_FLAG_64_BITS,
   5176         0,
   5177         3,
   5178         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
   5179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5180         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5181         -1,
   5182         -1,
   5183     },
   5184 #endif /* chips */
   5185 
   5186 #if defined(BCM_56560_A0)
   5187     { /* SOC_REG_INT_XLMAC_B0_E2E_CTRLr */
   5188         soc_block_list[128],
   5189         soc_portreg,
   5190         1,
   5191         0,
   5192         0x62300,
   5193         SOC_REG_FLAG_64_BITS,
   5194         0,
   5195         5,
   5196         soc_CLMAC_E2E_CTRLr_fields,
   5197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5198         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   5199         -1,
   5200         -1,
   5201     },
   5202 #endif /* chips */
   5203 
   5204 #if defined(BCM_56560_A0)
   5205     { /* SOC_REG_INT_XLMAC_B0_ECC_CTRLr */
   5206         soc_block_list[128],
   5207         soc_portreg,
   5208         1,
   5209         0,
   5210         0x62f00,
   5211         SOC_REG_FLAG_64_BITS,
   5212         0,
   5213         2,
   5214         soc_XLMAC_ECC_CTRLr_fields,
   5215         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   5216         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5217         -1,
   5218         -1,
   5219     },
   5220 #endif /* chips */
   5221 
   5222 #if defined(BCM_56560_A0)
   5223     { /* SOC_REG_INT_XLMAC_B0_ECC_FORCE_DOUBLE_BIT_ERRr */
   5224         soc_block_list[128],
   5225         soc_portreg,
   5226         1,
   5227         0,
   5228         0x63000,
   5229         SOC_REG_FLAG_64_BITS,
   5230         0,
   5231         2,
   5232         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
   5233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5234         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5235         -1,
   5236         -1,
   5237     },
   5238 #endif /* chips */
   5239 
   5240 #if defined(BCM_56560_A0)
   5241     { /* SOC_REG_INT_XLMAC_B0_ECC_FORCE_SINGLE_BIT_ERRr */
   5242         soc_block_list[128],
   5243         soc_portreg,
   5244         1,
   5245         0,
   5246         0x63100,
   5247         SOC_REG_FLAG_64_BITS,
   5248         0,
   5249         2,
   5250         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
   5251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5252         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5253         -1,
   5254         -1,
   5255     },
   5256 #endif /* chips */
   5257 
   5258 #if defined(BCM_56560_A0)
   5259     { /* SOC_REG_INT_XLMAC_B0_EEE_1_SEC_LINK_STATUS_TIMERr */
   5260         soc_block_list[128],
   5261         soc_portreg,
   5262         1,
   5263         0,
   5264         0x61c00,
   5265         SOC_REG_FLAG_64_BITS,
   5266         0,
   5267         1,
   5268         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
   5269         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
   5270         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   5271         -1,
   5272         -1,
   5273     },
   5274 #endif /* chips */
   5275 
   5276 #if defined(BCM_56560_A0)
   5277     { /* SOC_REG_INT_XLMAC_B0_EEE_CTRLr */
   5278         soc_block_list[128],
   5279         soc_portreg,
   5280         1,
   5281         0,
   5282         0x61a00,
   5283         SOC_REG_FLAG_64_BITS,
   5284         0,
   5285         2,
   5286         soc_CLMAC_EEE_CTRLr_fields,
   5287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5288         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5289         -1,
   5290         -1,
   5291     },
   5292 #endif /* chips */
   5293 
   5294 #if defined(BCM_56560_A0)
   5295     { /* SOC_REG_INT_XLMAC_B0_EEE_TIMERSr */
   5296         soc_block_list[128],
   5297         soc_portreg,
   5298         1,
   5299         0,
   5300         0x61b00,
   5301         SOC_REG_FLAG_64_BITS,
   5302         0,
   5303         5,
   5304         soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields,
   5305         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
   5306         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5307         -1,
   5308         -1,
   5309     },
   5310 #endif /* chips */
   5311 
   5312 #if defined(BCM_56560_A0)
   5313     { /* SOC_REG_INT_XLMAC_B0_FIFO_STATUSr */
   5314         soc_block_list[128],
   5315         soc_portreg,
   5316         1,
   5317         0,
   5318         0x61700,
   5319         SOC_REG_FLAG_64_BITS |
   5320                           SOC_REG_FLAG_RO,
   5321         0,
   5322         9,
   5323         soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields,
   5324         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
   5325         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   5326         -1,
   5327         -1,
   5328     },
   5329 #endif /* chips */
   5330 
   5331 #if defined(BCM_56560_A0)
   5332     { /* SOC_REG_INT_XLMAC_B0_GMII_EEE_CTRLr */
   5333         soc_block_list[128],
   5334         soc_portreg,
   5335         1,
   5336         0,
   5337         0x61f00,
   5338         SOC_REG_FLAG_64_BITS,
   5339         0,
   5340         2,
   5341         soc_CLMAC_GMII_EEE_CTRLr_fields,
   5342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5343         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   5344         -1,
   5345         -1,
   5346     },
   5347 #endif /* chips */
   5348 
   5349 #if defined(BCM_56560_A0)
   5350     { /* SOC_REG_INT_XLMAC_B0_HIGIG_HDR_0r */
   5351         soc_block_list[128],
   5352         soc_portreg,
   5353         1,
   5354         0,
   5355         0x61d00,
   5356         SOC_REG_FLAG_64_BITS,
   5357         0,
   5358         3,
   5359         soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields,
   5360         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
   5361         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5362         -1,
   5363         -1,
   5364     },
   5365 #endif /* chips */
   5366 
   5367 #if defined(BCM_56560_A0)
   5368     { /* SOC_REG_INT_XLMAC_B0_HIGIG_HDR_1r */
   5369         soc_block_list[128],
   5370         soc_portreg,
   5371         1,
   5372         0,
   5373         0x61e00,
   5374         SOC_REG_FLAG_64_BITS,
   5375         0,
   5376         3,
   5377         soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields,
   5378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5379         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5380         -1,
   5381         -1,
   5382     },
   5383 #endif /* chips */
   5384 
   5385 #if defined(BCM_56560_A0)
   5386     { /* SOC_REG_INT_XLMAC_B0_LAG_FAILOVER_STATUSr */
   5387         soc_block_list[128],
   5388         soc_portreg,
   5389         1,
   5390         0,
   5391         0x61900,
   5392         SOC_REG_FLAG_64_BITS |
   5393                           SOC_REG_FLAG_RO,
   5394         0,
   5395         2,
   5396         soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields,
   5397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5398         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5399         -1,
   5400         -1,
   5401     },
   5402 #endif /* chips */
   5403 
   5404 #if defined(BCM_56560_A0)
   5405     { /* SOC_REG_INT_XLMAC_B0_LLFC_CTRLr */
   5406         soc_block_list[128],
   5407         soc_portreg,
   5408         1,
   5409         0,
   5410         0x61200,
   5411         SOC_REG_FLAG_64_BITS,
   5412         0,
   5413         7,
   5414         soc_CLMAC_LLFC_CTRLr_fields,
   5415         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
   5416         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   5417         -1,
   5418         -1,
   5419     },
   5420 #endif /* chips */
   5421 
   5422 #if defined(BCM_56560_A0)
   5423     { /* SOC_REG_INT_XLMAC_B0_MEM_CTRLr */
   5424         soc_block_list[128],
   5425         soc_portreg,
   5426         1,
   5427         0,
   5428         0x62e00,
   5429         SOC_REG_FLAG_64_BITS,
   5430         0,
   5431         2,
   5432         soc_XLMAC_MEM_CTRLr_fields,
   5433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5434         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   5435         -1,
   5436         -1,
   5437     },
   5438 #endif /* chips */
   5439 
   5440 #if defined(BCM_56560_A0)
   5441     { /* SOC_REG_INT_XLMAC_B0_MODEr */
   5442         soc_block_list[128],
   5443         soc_portreg,
   5444         1,
   5445         0,
   5446         0x60100,
   5447         SOC_REG_FLAG_64_BITS,
   5448         0,
   5449         3,
   5450         soc_CLMAC_MODEr_fields,
   5451         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   5452         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   5453         -1,
   5454         -1,
   5455     },
   5456 #endif /* chips */
   5457 
   5458 #if defined(BCM_56560_A0)
   5459     { /* SOC_REG_INT_XLMAC_B0_PAUSE_CTRLr */
   5460         soc_block_list[128],
   5461         soc_portreg,
   5462         1,
   5463         0,
   5464         0x60d00,
   5465         SOC_REG_FLAG_64_BITS,
   5466         0,
   5467         9,
   5468         soc_XLMAC_B0_PAUSE_CTRLr_fields,
   5469         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
   5470         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
   5471         -1,
   5472         -1,
   5473     },
   5474 #endif /* chips */
   5475 
   5476 #if defined(BCM_56560_A0)
   5477     { /* SOC_REG_INT_XLMAC_B0_PFC_CTRLr */
   5478         soc_block_list[128],
   5479         soc_portreg,
   5480         1,
   5481         0,
   5482         0x60e00,
   5483         SOC_REG_FLAG_64_BITS,
   5484         0,
   5485         8,
   5486         soc_CLMAC_PFC_CTRLr_fields,
   5487         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
   5488         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
   5489         -1,
   5490         -1,
   5491     },
   5492 #endif /* chips */
   5493 
   5494 #if defined(BCM_56560_A0)
   5495     { /* SOC_REG_INT_XLMAC_B0_PFC_DAr */
   5496         soc_block_list[128],
   5497         soc_portreg,
   5498         1,
   5499         0,
   5500         0x61100,
   5501         SOC_REG_FLAG_64_BITS,
   5502         0,
   5503         3,
   5504         soc_XLMAC_PFC_DA_BCM53400_A0r_fields,
   5505         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
   5506         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   5507         -1,
   5508         -1,
   5509     },
   5510 #endif /* chips */
   5511 
   5512 #if defined(BCM_56560_A0)
   5513     { /* SOC_REG_INT_XLMAC_B0_PFC_OPCODEr */
   5514         soc_block_list[128],
   5515         soc_portreg,
   5516         1,
   5517         0,
   5518         0x61000,
   5519         SOC_REG_FLAG_64_BITS,
   5520         0,
   5521         1,
   5522         soc_CLMAC_PFC_OPCODEr_fields,
   5523         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
   5524         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5525         -1,
   5526         -1,
   5527     },
   5528 #endif /* chips */
   5529 
   5530 #if defined(BCM_56560_A0)
   5531     { /* SOC_REG_INT_XLMAC_B0_PFC_TYPEr */
   5532         soc_block_list[128],
   5533         soc_portreg,
   5534         1,
   5535         0,
   5536         0x60f00,
   5537         SOC_REG_FLAG_64_BITS,
   5538         0,
   5539         1,
   5540         soc_CLMAC_PFC_TYPEr_fields,
   5541         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
   5542         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5543         -1,
   5544         -1,
   5545     },
   5546 #endif /* chips */
   5547 
   5548 #if defined(BCM_56560_A0)
   5549     { /* SOC_REG_INT_XLMAC_B0_RX_CDC_ECC_STATUSr */
   5550         soc_block_list[128],
   5551         soc_portreg,
   5552         1,
   5553         0,
   5554         0x63200,
   5555         SOC_REG_FLAG_64_BITS |
   5556                           SOC_REG_FLAG_RO,
   5557         0,
   5558         2,
   5559         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
   5560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5561         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5562         -1,
   5563         -1,
   5564     },
   5565 #endif /* chips */
   5566 
   5567 #if defined(BCM_56560_A0)
   5568     { /* SOC_REG_INT_XLMAC_B0_RX_CTRLr */
   5569         soc_block_list[128],
   5570         soc_portreg,
   5571         1,
   5572         0,
   5573         0x60600,
   5574         SOC_REG_FLAG_64_BITS,
   5575         0,
   5576         7,
   5577         soc_XLMAC_B0_RX_CTRLr_fields,
   5578         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
   5579         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   5580         -1,
   5581         -1,
   5582     },
   5583 #endif /* chips */
   5584 
   5585 #if defined(BCM_56560_A0)
   5586     { /* SOC_REG_INT_XLMAC_B0_RX_LLFC_MSG_FIELDSr */
   5587         soc_block_list[128],
   5588         soc_portreg,
   5589         1,
   5590         0,
   5591         0x61400,
   5592         SOC_REG_FLAG_64_BITS,
   5593         0,
   5594         4,
   5595         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
   5596         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
   5597         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   5598         -1,
   5599         -1,
   5600     },
   5601 #endif /* chips */
   5602 
   5603 #if defined(BCM_56560_A0)
   5604     { /* SOC_REG_INT_XLMAC_B0_RX_LSS_CTRLr */
   5605         soc_block_list[128],
   5606         soc_portreg,
   5607         1,
   5608         0,
   5609         0x60a00,
   5610         SOC_REG_FLAG_64_BITS,
   5611         0,
   5612         8,
   5613         soc_CLMAC_RX_LSS_CTRLr_fields,
   5614         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   5615         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   5616         -1,
   5617         -1,
   5618     },
   5619 #endif /* chips */
   5620 
   5621 #if defined(BCM_56560_A0)
   5622     { /* SOC_REG_INT_XLMAC_B0_RX_LSS_STATUSr */
   5623         soc_block_list[128],
   5624         soc_portreg,
   5625         1,
   5626         0,
   5627         0x60b00,
   5628         SOC_REG_FLAG_64_BITS |
   5629                           SOC_REG_FLAG_RO,
   5630         0,
   5631         3,
   5632         soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields,
   5633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5634         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5635         -1,
   5636         -1,
   5637     },
   5638 #endif /* chips */
   5639 
   5640 #if defined(BCM_56560_A0)
   5641     { /* SOC_REG_INT_XLMAC_B0_RX_MAC_SAr */
   5642         soc_block_list[128],
   5643         soc_portreg,
   5644         1,
   5645         0,
   5646         0x60700,
   5647         SOC_REG_FLAG_64_BITS,
   5648         0,
   5649         3,
   5650         soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields,
   5651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5652         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   5653         -1,
   5654         -1,
   5655     },
   5656 #endif /* chips */
   5657 
   5658 #if defined(BCM_56560_A0)
   5659     { /* SOC_REG_INT_XLMAC_B0_RX_MAX_SIZEr */
   5660         soc_block_list[128],
   5661         soc_portreg,
   5662         1,
   5663         0,
   5664         0x60800,
   5665         SOC_REG_FLAG_64_BITS,
   5666         0,
   5667         1,
   5668         soc_CLMAC_RX_MAX_SIZEr_fields,
   5669         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
   5670         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   5671         -1,
   5672         -1,
   5673     },
   5674 #endif /* chips */
   5675 
   5676 #if defined(BCM_56560_A0)
   5677     { /* SOC_REG_INT_XLMAC_B0_RX_VLAN_TAGr */
   5678         soc_block_list[128],
   5679         soc_portreg,
   5680         1,
   5681         0,
   5682         0x60900,
   5683         SOC_REG_FLAG_64_BITS,
   5684         0,
   5685         4,
   5686         soc_CLMAC_RX_VLAN_TAGr_fields,
   5687         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
   5688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
   5689         -1,
   5690         -1,
   5691     },
   5692 #endif /* chips */
   5693 
   5694 #if defined(BCM_56560_A0)
   5695     { /* SOC_REG_INT_XLMAC_B0_SPARE0r */
   5696         soc_block_list[128],
   5697         soc_portreg,
   5698         1,
   5699         0,
   5700         0x60200,
   5701         SOC_REG_FLAG_64_BITS,
   5702         0,
   5703         1,
   5704         soc_CLPORT_SPARE0_REGr_fields,
   5705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5706         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5707         -1,
   5708         -1,
   5709     },
   5710 #endif /* chips */
   5711 
   5712 #if defined(BCM_56560_A0)
   5713     { /* SOC_REG_INT_XLMAC_B0_SPARE1r */
   5714         soc_block_list[128],
   5715         soc_portreg,
   5716         1,
   5717         0,
   5718         0x60300,
   5719         SOC_REG_FLAG_64_BITS,
   5720         0,
   5721         1,
   5722         soc_CLMAC_SPARE1r_fields,
   5723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5724         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5725         -1,
   5726         -1,
   5727     },
   5728 #endif /* chips */
   5729 
   5730 #if defined(BCM_56560_A0)
   5731     { /* SOC_REG_INT_XLMAC_B0_TIMESTAMP_ADJUSTr */
   5732         soc_block_list[128],
   5733         soc_portreg,
   5734         1,
   5735         0,
   5736         0x62000,
   5737         SOC_REG_FLAG_64_BITS,
   5738         0,
   5739         3,
   5740         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
   5741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5742         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5743         -1,
   5744         -1,
   5745     },
   5746 #endif /* chips */
   5747 
   5748 #if defined(BCM_56560_A0)
   5749     { /* SOC_REG_INT_XLMAC_B0_TIMESTAMP_BYTE_ADJUSTr */
   5750         soc_block_list[128],
   5751         soc_portreg,
   5752         1,
   5753         0,
   5754         0x62100,
   5755         SOC_REG_FLAG_64_BITS,
   5756         0,
   5757         4,
   5758         soc_XLMAC_B0_TIMESTAMP_BYTE_ADJUSTr_fields,
   5759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5760         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
   5761         -1,
   5762         -1,
   5763     },
   5764 #endif /* chips */
   5765 
   5766 #if defined(BCM_56560_A0)
   5767     { /* SOC_REG_INT_XLMAC_B0_TXFIFO_CELL_CNTr */
   5768         soc_block_list[128],
   5769         soc_portreg,
   5770         1,
   5771         0,
   5772         0x62c00,
   5773         SOC_REG_FLAG_64_BITS |
   5774                           SOC_REG_FLAG_RO,
   5775         0,
   5776         1,
   5777         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
   5778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5779         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   5780         -1,
   5781         -1,
   5782     },
   5783 #endif /* chips */
   5784 
   5785 #if defined(BCM_56560_A0)
   5786     { /* SOC_REG_INT_XLMAC_B0_TXFIFO_CELL_REQ_CNTr */
   5787         soc_block_list[128],
   5788         soc_portreg,
   5789         1,
   5790         0,
   5791         0x62d00,
   5792         SOC_REG_FLAG_64_BITS |
   5793                           SOC_REG_FLAG_RO,
   5794         0,
   5795         1,
   5796         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
   5797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5798         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   5799         -1,
   5800         -1,
   5801     },
   5802 #endif /* chips */
   5803 
   5804 #if defined(BCM_56560_A0)
   5805     { /* SOC_REG_INT_XLMAC_B0_TX_CDC_ECC_STATUSr */
   5806         soc_block_list[128],
   5807         soc_portreg,
   5808         1,
   5809         0,
   5810         0x63300,
   5811         SOC_REG_FLAG_64_BITS |
   5812                           SOC_REG_FLAG_RO,
   5813         0,
   5814         2,
   5815         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
   5816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5817         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5818         -1,
   5819         -1,
   5820     },
   5821 #endif /* chips */
   5822 
   5823 #if defined(BCM_56560_A0)
   5824     { /* SOC_REG_INT_XLMAC_B0_TX_CRC_CORRUPT_CTRLr */
   5825         soc_block_list[128],
   5826         soc_portreg,
   5827         1,
   5828         0,
   5829         0x62200,
   5830         SOC_REG_FLAG_64_BITS,
   5831         0,
   5832         6,
   5833         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
   5834         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   5835         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
   5836         -1,
   5837         -1,
   5838     },
   5839 #endif /* chips */
   5840 
   5841 #if defined(BCM_56560_A0)
   5842     { /* SOC_REG_INT_XLMAC_B0_TX_CTRLr */
   5843         soc_block_list[128],
   5844         soc_portreg,
   5845         1,
   5846         0,
   5847         0x60400,
   5848         SOC_REG_FLAG_64_BITS,
   5849         0,
   5850         13,
   5851         soc_XLMAC_TX_CTRL_BCM53400_A0r_fields,
   5852         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
   5853         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
   5854         -1,
   5855         -1,
   5856     },
   5857 #endif /* chips */
   5858 
   5859 #if defined(BCM_56560_A0)
   5860     { /* SOC_REG_INT_XLMAC_B0_TX_LLFC_MSG_FIELDSr */
   5861         soc_block_list[128],
   5862         soc_portreg,
   5863         1,
   5864         0,
   5865         0x61300,
   5866         SOC_REG_FLAG_64_BITS,
   5867         0,
   5868         3,
   5869         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
   5870         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
   5871         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   5872         -1,
   5873         -1,
   5874     },
   5875 #endif /* chips */
   5876 
   5877 #if defined(BCM_56560_A0)
   5878     { /* SOC_REG_INT_XLMAC_B0_TX_MAC_SAr */
   5879         soc_block_list[128],
   5880         soc_portreg,
   5881         1,
   5882         0,
   5883         0x60500,
   5884         SOC_REG_FLAG_64_BITS,
   5885         0,
   5886         3,
   5887         soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields,
   5888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5889         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   5890         -1,
   5891         -1,
   5892     },
   5893 #endif /* chips */
   5894 
   5895 #if defined(BCM_56560_A0)
   5896     { /* SOC_REG_INT_XLMAC_B0_TX_TIMESTAMP_FIFO_DATAr */
   5897         soc_block_list[128],
   5898         soc_portreg,
   5899         1,
   5900         0,
   5901         0x61500,
   5902         SOC_REG_FLAG_64_BITS |
   5903                           SOC_REG_FLAG_RO,
   5904         0,
   5905         3,
   5906         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields,
   5907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5908         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
   5909         -1,
   5910         -1,
   5911     },
   5912 #endif /* chips */
   5913 
   5914 #if defined(BCM_56560_A0)
   5915     { /* SOC_REG_INT_XLMAC_B0_TX_TIMESTAMP_FIFO_STATUSr */
   5916         soc_block_list[128],
   5917         soc_portreg,
   5918         1,
   5919         0,
   5920         0x61600,
   5921         SOC_REG_FLAG_64_BITS |
   5922                           SOC_REG_FLAG_RO,
   5923         0,
   5924         1,
   5925         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields,
   5926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5927         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5928         -1,
   5929         -1,
   5930     },
   5931 #endif /* chips */
   5932 
   5933 #if defined(BCM_56560_A0)
   5934     { /* SOC_REG_INT_XLMAC_B0_VERSION_IDr */
   5935         soc_block_list[128],
   5936         soc_portreg,
   5937         1,
   5938         0,
   5939         0x63500,
   5940         SOC_REG_FLAG_64_BITS |
   5941                           SOC_REG_FLAG_RO,
   5942         0,
   5943         1,
   5944         soc_XLMAC_B0_VERSION_IDr_fields,
   5945         SOC_RESET_VAL_DEC(0x0000a037, 0x00000000)
   5946         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5947         -1,
   5948         -1,
   5949     },
   5950 #endif /* chips */
   5951 
   5952 #if defined(BCM_2801PM_A0)
   5953     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUSr */
   5954         soc_block_list[56],
   5955         soc_portreg,
   5956         1,
   5957         0,
   5958         0x63300,
   5959         SOC_REG_FLAG_RO |
   5960                           SOC_REG_FLAG_SIGNAL,
   5961         0,
   5962         4,
   5963         soc_XLMAC_CLEAR_ECC_STATUSr_fields,
   5964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5965         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5966         -1,
   5967         -1,
   5968     },
   5969 #endif /* chips */
   5970 
   5971 #if defined(BCM_53400_A0)
   5972     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM53400_A0r */
   5973         soc_block_list[16],
   5974         soc_portreg,
   5975         1,
   5976         0,
   5977         0x63300,
   5978         SOC_REG_FLAG_64_BITS |
   5979                           SOC_REG_FLAG_RO,
   5980         0,
   5981         4,
   5982         soc_XLMAC_CLEAR_ECC_STATUSr_fields,
   5983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5984         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5985         -1,
   5986         -1,
   5987     },
   5988 #endif /* chips */
   5989 
   5990 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5991     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM53570_A0r */
   5992         soc_block_list[16],
   5993         soc_portreg,
   5994         1,
   5995         0,
   5996         0x63400,
   5997         SOC_REG_FLAG_64_BITS,
   5998         0,
   5999         4,
   6000         soc_XLMAC_B0_CLEAR_ECC_STATUSr_fields,
   6001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6002         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6003         -1,
   6004         -1,
   6005     },
   6006 #endif /* chips */
   6007 
   6008 #if defined(BCM_56160_A0)
   6009     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM56160_A0r */
   6010         soc_block_list[16],
   6011         soc_portreg,
   6012         1,
   6013         0,
   6014         0x63400,
   6015         SOC_REG_FLAG_64_BITS,
   6016         0,
   6017         4,
   6018         soc_XLMAC_B0_CLEAR_ECC_STATUSr_fields,
   6019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6020         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6021         -1,
   6022         -1,
   6023     },
   6024 #endif /* chips */
   6025 
   6026 #if defined(BCM_56260_A0)
   6027     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM56260_A0r */
   6028         soc_block_list[220],
   6029         soc_portreg,
   6030         1,
   6031         0,
   6032         0x63300,
   6033         SOC_REG_FLAG_64_BITS |
   6034                           SOC_REG_FLAG_RO,
   6035         0,
   6036         4,
   6037         soc_XLMAC_CLEAR_ECC_STATUSr_fields,
   6038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6039         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6040         -1,
   6041         -1,
   6042     },
   6043 #endif /* chips */
   6044 
   6045 #if defined(BCM_56260_B0)
   6046     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM56260_B0r */
   6047         soc_block_list[220],
   6048         soc_portreg,
   6049         1,
   6050         0,
   6051         0x63400,
   6052         SOC_REG_FLAG_64_BITS,
   6053         0,
   6054         4,
   6055         soc_XLMAC_B0_CLEAR_ECC_STATUSr_fields,
   6056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6057         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6058         -1,
   6059         -1,
   6060     },
   6061 #endif /* chips */
   6062 
   6063 #if defined(BCM_56270_A0)
   6064     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM56270_A0r */
   6065         soc_block_list[220],
   6066         soc_portreg,
   6067         1,
   6068         0,
   6069         0x63400,
   6070         SOC_REG_FLAG_64_BITS,
   6071         0,
   6072         4,
   6073         soc_XLMAC_B0_CLEAR_ECC_STATUSr_fields,
   6074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6075         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6076         -1,
   6077         -1,
   6078     },
   6079 #endif /* chips */
   6080 
   6081 #if defined(BCM_56370_A0)
   6082     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM56370_A0r */
   6083         soc_block_list[16],
   6084         soc_portreg,
   6085         1,
   6086         0,
   6087         0x63400,
   6088         SOC_REG_FLAG_64_BITS,
   6089         0,
   6090         4,
   6091         soc_XLMAC_B0_CLEAR_ECC_STATUSr_fields,
   6092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6093         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6094         -1,
   6095         -1,
   6096         3,
   6097     },
   6098 #endif /* chips */
   6099 
   6100 #if defined(BCM_56560_A0)
   6101     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM56560_A0r */
   6102         soc_block_list[16],
   6103         soc_portreg,
   6104         1,
   6105         0,
   6106         0x63300,
   6107         SOC_REG_FLAG_64_BITS |
   6108                           SOC_REG_FLAG_RO,
   6109         0,
   6110         4,
   6111         soc_XLMAC_CLEAR_ECC_STATUSr_fields,
   6112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6113         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6114         -1,
   6115         -1,
   6116     },
   6117 #endif /* chips */
   6118 
   6119 #if defined(BCM_56560_B0)
   6120     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM56560_B0r */
   6121         soc_block_list[16],
   6122         soc_portreg,
   6123         1,
   6124         0,
   6125         0x63400,
   6126         SOC_REG_FLAG_64_BITS,
   6127         0,
   6128         4,
   6129         soc_XLMAC_B0_CLEAR_ECC_STATUSr_fields,
   6130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6131         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6132         -1,
   6133         -1,
   6134     },
   6135 #endif /* chips */
   6136 
   6137 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   6138     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM56670_A0r */
   6139         soc_block_list[16],
   6140         soc_portreg,
   6141         1,
   6142         0,
   6143         0x63400,
   6144         SOC_REG_FLAG_64_BITS,
   6145         0,
   6146         4,
   6147         soc_XLMAC_B0_CLEAR_ECC_STATUSr_fields,
   6148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6149         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6150         -1,
   6151         -1,
   6152     },
   6153 #endif /* chips */
   6154 
   6155 #if defined(BCM_56860_A0)
   6156     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM56860_A0r */
   6157         soc_block_list[16],
   6158         soc_portreg,
   6159         1,
   6160         0,
   6161         0x63400,
   6162         SOC_REG_FLAG_64_BITS,
   6163         0,
   6164         4,
   6165         soc_XLMAC_CLEAR_ECC_STATUS_BCM56860_A0r_fields,
   6166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6167         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6168         -1,
   6169         -1,
   6170     },
   6171 #endif /* chips */
   6172 
   6173 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6174     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM56960_A0r */
   6175         soc_block_list[16],
   6176         soc_portreg,
   6177         1,
   6178         0,
   6179         0x63300,
   6180         SOC_REG_FLAG_64_BITS |
   6181                           SOC_REG_FLAG_RO,
   6182         0,
   6183         4,
   6184         soc_XLMAC_CLEAR_ECC_STATUSr_fields,
   6185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6186         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6187         -1,
   6188         -1,
   6189         3,
   6190     },
   6191 #endif /* chips */
   6192 
   6193 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6194     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   6195     defined(BCM_56980_B0)
   6196     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM56970_A0r */
   6197         soc_block_list[16],
   6198         soc_portreg,
   6199         1,
   6200         0,
   6201         0x63400,
   6202         SOC_REG_FLAG_64_BITS,
   6203         0,
   6204         4,
   6205         soc_XLMAC_B0_CLEAR_ECC_STATUSr_fields,
   6206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6207         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6208         -1,
   6209         -1,
   6210         3,
   6211     },
   6212 #endif /* chips */
   6213 
   6214 #if defined(BCM_88270_A0)
   6215     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM88270_A0r */
   6216         soc_block_list[221],
   6217         soc_portreg,
   6218         1,
   6219         0,
   6220         0x63400,
   6221         SOC_REG_FLAG_64_BITS |
   6222                           SOC_REG_FLAG_RO |
   6223                           SOC_REG_FLAG_SIGNAL,
   6224         0,
   6225         4,
   6226         soc_XLMAC_CLEAR_ECC_STATUS_BCM88270_A0r_fields,
   6227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6228         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6229         -1,
   6230         -1,
   6231     },
   6232 #endif /* chips */
   6233 
   6234 #if defined(BCM_88375_A0)
   6235     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM88375_A0r */
   6236         soc_block_list[56],
   6237         soc_portreg,
   6238         1,
   6239         0,
   6240         0x63300,
   6241         SOC_REG_FLAG_64_BITS |
   6242                           SOC_REG_FLAG_RO |
   6243                           SOC_REG_FLAG_SIGNAL,
   6244         0,
   6245         4,
   6246         soc_XLMAC_CLEAR_ECC_STATUS_BCM88375_A0r_fields,
   6247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6248         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6249         -1,
   6250         -1,
   6251     },
   6252 #endif /* chips */
   6253 
   6254 #if defined(BCM_88375_B0)
   6255     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM88375_B0r */
   6256         soc_block_list[56],
   6257         soc_portreg,
   6258         1,
   6259         0,
   6260         0x63400,
   6261         SOC_REG_FLAG_64_BITS,
   6262         0,
   6263         4,
   6264         soc_XLMAC_CLEAR_ECC_STATUS_BCM88375_B0r_fields,
   6265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6266         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6267         -1,
   6268         -1,
   6269     },
   6270 #endif /* chips */
   6271 
   6272 #if defined(BCM_88470_A0)
   6273     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM88470_A0r */
   6274         soc_block_list[56],
   6275         soc_portreg,
   6276         1,
   6277         0,
   6278         0x63300,
   6279         SOC_REG_FLAG_64_BITS |
   6280                           SOC_REG_FLAG_RO |
   6281                           SOC_REG_FLAG_SIGNAL,
   6282         0,
   6283         4,
   6284         soc_XLMAC_CLEAR_ECC_STATUS_BCM88470_A0r_fields,
   6285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6286         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6287         -1,
   6288         -1,
   6289     },
   6290 #endif /* chips */
   6291 
   6292 #if defined(BCM_88470_B0)
   6293     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM88470_B0r */
   6294         soc_block_list[56],
   6295         soc_portreg,
   6296         1,
   6297         0,
   6298         0x63400,
   6299         SOC_REG_FLAG_64_BITS,
   6300         0,
   6301         4,
   6302         soc_XLMAC_CLEAR_ECC_STATUS_BCM88470_B0r_fields,
   6303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6304         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6305         -1,
   6306         -1,
   6307     },
   6308 #endif /* chips */
   6309 
   6310 #if defined(BCM_88675_A0)
   6311     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM88675_A0r */
   6312         soc_block_list[56],
   6313         soc_portreg,
   6314         1,
   6315         0,
   6316         0x63300,
   6317         SOC_REG_FLAG_64_BITS |
   6318                           SOC_REG_FLAG_RO |
   6319                           SOC_REG_FLAG_SIGNAL,
   6320         0,
   6321         4,
   6322         soc_XLMAC_CLEAR_ECC_STATUS_BCM88675_A0r_fields,
   6323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6324         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6325         -1,
   6326         -1,
   6327     },
   6328 #endif /* chips */
   6329 
   6330 #if defined(BCM_88675_B0)
   6331     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM88675_B0r */
   6332         soc_block_list[56],
   6333         soc_portreg,
   6334         1,
   6335         0,
   6336         0x63400,
   6337         SOC_REG_FLAG_64_BITS,
   6338         0,
   6339         4,
   6340         soc_XLMAC_CLEAR_ECC_STATUS_BCM88675_B0r_fields,
   6341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6342         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6343         -1,
   6344         -1,
   6345     },
   6346 #endif /* chips */
   6347 
   6348 #if defined(BCM_88680_A0)
   6349     { /* SOC_REG_INT_XLMAC_CLEAR_ECC_STATUS_BCM88680_A0r */
   6350         soc_block_list[56],
   6351         soc_portreg,
   6352         1,
   6353         0,
   6354         0x63400,
   6355         SOC_REG_FLAG_64_BITS,
   6356         0,
   6357         4,
   6358         soc_XLMAC_CLEAR_ECC_STATUS_BCM88680_A0r_fields,
   6359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6360         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   6361         -1,
   6362         -1,
   6363     },
   6364 #endif /* chips */
   6365 
   6366 #if defined(BCM_2801PM_A0)
   6367     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUSr */
   6368         soc_block_list[56],
   6369         soc_portreg,
   6370         1,
   6371         0,
   6372         0x61800,
   6373         SOC_REG_FLAG_RO |
   6374                           SOC_REG_FLAG_SIGNAL,
   6375         0,
   6376         8,
   6377         soc_XLMAC_CLEAR_FIFO_STATUSr_fields,
   6378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6379         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6380         -1,
   6381         -1,
   6382     },
   6383 #endif /* chips */
   6384 
   6385 #if defined(BCM_53400_A0)
   6386     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM53400_A0r */
   6387         soc_block_list[16],
   6388         soc_portreg,
   6389         1,
   6390         0,
   6391         0x61800,
   6392         SOC_REG_FLAG_64_BITS |
   6393                           SOC_REG_FLAG_RO,
   6394         0,
   6395         8,
   6396         soc_XLMAC_CLEAR_FIFO_STATUSr_fields,
   6397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6398         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6399         -1,
   6400         -1,
   6401     },
   6402 #endif /* chips */
   6403 
   6404 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   6405     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM53570_A0r */
   6406         soc_block_list[16],
   6407         soc_portreg,
   6408         1,
   6409         0,
   6410         0x61700,
   6411         SOC_REG_FLAG_64_BITS,
   6412         0,
   6413         8,
   6414         soc_CLMAC_CLEAR_FIFO_STATUSr_fields,
   6415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6416         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6417         -1,
   6418         -1,
   6419     },
   6420 #endif /* chips */
   6421 
   6422 #if defined(BCM_56150_A0)
   6423     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56150_A0r */
   6424         soc_block_list[16],
   6425         soc_portreg,
   6426         1,
   6427         0,
   6428         0x61800,
   6429         SOC_REG_FLAG_64_BITS |
   6430                           SOC_REG_FLAG_RO,
   6431         0,
   6432         7,
   6433         soc_XLMAC_CLEAR_FIFO_STATUS_BCM56850_A0r_fields,
   6434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6435         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   6436         -1,
   6437         -1,
   6438     },
   6439 #endif /* chips */
   6440 
   6441 #if defined(BCM_56160_A0)
   6442     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56160_A0r */
   6443         soc_block_list[16],
   6444         soc_portreg,
   6445         1,
   6446         0,
   6447         0x61800,
   6448         SOC_REG_FLAG_64_BITS,
   6449         0,
   6450         8,
   6451         soc_CLMAC_CLEAR_FIFO_STATUSr_fields,
   6452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6453         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6454         -1,
   6455         -1,
   6456     },
   6457 #endif /* chips */
   6458 
   6459 #if defined(BCM_56260_A0)
   6460     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56260_A0r */
   6461         soc_block_list[220],
   6462         soc_portreg,
   6463         1,
   6464         0,
   6465         0x61800,
   6466         SOC_REG_FLAG_64_BITS |
   6467                           SOC_REG_FLAG_RO,
   6468         0,
   6469         8,
   6470         soc_XLMAC_CLEAR_FIFO_STATUSr_fields,
   6471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6472         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6473         -1,
   6474         -1,
   6475     },
   6476 #endif /* chips */
   6477 
   6478 #if defined(BCM_56260_B0)
   6479     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56260_B0r */
   6480         soc_block_list[220],
   6481         soc_portreg,
   6482         1,
   6483         0,
   6484         0x61800,
   6485         SOC_REG_FLAG_64_BITS,
   6486         0,
   6487         8,
   6488         soc_CLMAC_CLEAR_FIFO_STATUSr_fields,
   6489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6490         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6491         -1,
   6492         -1,
   6493     },
   6494 #endif /* chips */
   6495 
   6496 #if defined(BCM_56270_A0)
   6497     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56270_A0r */
   6498         soc_block_list[220],
   6499         soc_portreg,
   6500         1,
   6501         0,
   6502         0x61800,
   6503         SOC_REG_FLAG_64_BITS,
   6504         0,
   6505         8,
   6506         soc_CLMAC_CLEAR_FIFO_STATUSr_fields,
   6507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6508         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6509         -1,
   6510         -1,
   6511     },
   6512 #endif /* chips */
   6513 
   6514 #if defined(BCM_56370_A0)
   6515     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56370_A0r */
   6516         soc_block_list[16],
   6517         soc_portreg,
   6518         1,
   6519         0,
   6520         0x61800,
   6521         SOC_REG_FLAG_64_BITS,
   6522         0,
   6523         8,
   6524         soc_CLMAC_CLEAR_FIFO_STATUSr_fields,
   6525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6526         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6527         -1,
   6528         -1,
   6529         3,
   6530     },
   6531 #endif /* chips */
   6532 
   6533 #if defined(BCM_56560_A0)
   6534     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56560_A0r */
   6535         soc_block_list[16],
   6536         soc_portreg,
   6537         1,
   6538         0,
   6539         0x61800,
   6540         SOC_REG_FLAG_64_BITS |
   6541                           SOC_REG_FLAG_RO,
   6542         0,
   6543         8,
   6544         soc_XLMAC_CLEAR_FIFO_STATUSr_fields,
   6545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6546         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6547         -1,
   6548         -1,
   6549     },
   6550 #endif /* chips */
   6551 
   6552 #if defined(BCM_56560_B0)
   6553     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56560_B0r */
   6554         soc_block_list[16],
   6555         soc_portreg,
   6556         1,
   6557         0,
   6558         0x61800,
   6559         SOC_REG_FLAG_64_BITS,
   6560         0,
   6561         8,
   6562         soc_CLMAC_CLEAR_FIFO_STATUSr_fields,
   6563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6564         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6565         -1,
   6566         -1,
   6567     },
   6568 #endif /* chips */
   6569 
   6570 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   6571     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56670_A0r */
   6572         soc_block_list[16],
   6573         soc_portreg,
   6574         1,
   6575         0,
   6576         0x61700,
   6577         SOC_REG_FLAG_64_BITS,
   6578         0,
   6579         8,
   6580         soc_CLMAC_CLEAR_FIFO_STATUSr_fields,
   6581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6582         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6583         -1,
   6584         -1,
   6585     },
   6586 #endif /* chips */
   6587 
   6588 #if defined(BCM_56850_A0)
   6589     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56850_A0r */
   6590         soc_block_list[16],
   6591         soc_portreg,
   6592         1,
   6593         0,
   6594         0x61800,
   6595         SOC_REG_FLAG_64_BITS |
   6596                           SOC_REG_FLAG_RO,
   6597         0,
   6598         7,
   6599         soc_XLMAC_CLEAR_FIFO_STATUS_BCM56850_A0r_fields,
   6600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6601         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   6602         -1,
   6603         -1,
   6604     },
   6605 #endif /* chips */
   6606 
   6607 #if defined(BCM_56860_A0)
   6608     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56860_A0r */
   6609         soc_block_list[16],
   6610         soc_portreg,
   6611         1,
   6612         0,
   6613         0x61800,
   6614         SOC_REG_FLAG_64_BITS,
   6615         0,
   6616         8,
   6617         soc_CLMAC_CLEAR_FIFO_STATUS_BCM56860_A0r_fields,
   6618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6619         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6620         -1,
   6621         -1,
   6622     },
   6623 #endif /* chips */
   6624 
   6625 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6626     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56960_A0r */
   6627         soc_block_list[16],
   6628         soc_portreg,
   6629         1,
   6630         0,
   6631         0x61800,
   6632         SOC_REG_FLAG_64_BITS |
   6633                           SOC_REG_FLAG_RO,
   6634         0,
   6635         8,
   6636         soc_XLMAC_CLEAR_FIFO_STATUSr_fields,
   6637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6638         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6639         -1,
   6640         -1,
   6641         3,
   6642     },
   6643 #endif /* chips */
   6644 
   6645 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6646     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   6647     defined(BCM_56980_B0)
   6648     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM56970_A0r */
   6649         soc_block_list[16],
   6650         soc_portreg,
   6651         1,
   6652         0,
   6653         0x61800,
   6654         SOC_REG_FLAG_64_BITS,
   6655         0,
   6656         8,
   6657         soc_CLMAC_CLEAR_FIFO_STATUSr_fields,
   6658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6659         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6660         -1,
   6661         -1,
   6662         3,
   6663     },
   6664 #endif /* chips */
   6665 
   6666 #if defined(BCM_88270_A0)
   6667     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM88270_A0r */
   6668         soc_block_list[221],
   6669         soc_portreg,
   6670         1,
   6671         0,
   6672         0x61800,
   6673         SOC_REG_FLAG_64_BITS,
   6674         0,
   6675         8,
   6676         soc_XLMAC_CLEAR_FIFO_STATUS_BCM88270_A0r_fields,
   6677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6678         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6679         -1,
   6680         -1,
   6681     },
   6682 #endif /* chips */
   6683 
   6684 #if defined(BCM_88375_A0)
   6685     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM88375_A0r */
   6686         soc_block_list[56],
   6687         soc_portreg,
   6688         1,
   6689         0,
   6690         0x61800,
   6691         SOC_REG_FLAG_64_BITS |
   6692                           SOC_REG_FLAG_RO |
   6693                           SOC_REG_FLAG_SIGNAL,
   6694         0,
   6695         8,
   6696         soc_XLMAC_CLEAR_FIFO_STATUS_BCM88375_A0r_fields,
   6697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6698         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6699         -1,
   6700         -1,
   6701     },
   6702 #endif /* chips */
   6703 
   6704 #if defined(BCM_88375_B0)
   6705     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM88375_B0r */
   6706         soc_block_list[56],
   6707         soc_portreg,
   6708         1,
   6709         0,
   6710         0x61800,
   6711         SOC_REG_FLAG_64_BITS,
   6712         0,
   6713         8,
   6714         soc_XLMAC_CLEAR_FIFO_STATUS_BCM88375_B0r_fields,
   6715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6716         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6717         -1,
   6718         -1,
   6719     },
   6720 #endif /* chips */
   6721 
   6722 #if defined(BCM_88470_A0)
   6723     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM88470_A0r */
   6724         soc_block_list[56],
   6725         soc_portreg,
   6726         1,
   6727         0,
   6728         0x61800,
   6729         SOC_REG_FLAG_64_BITS |
   6730                           SOC_REG_FLAG_RO |
   6731                           SOC_REG_FLAG_SIGNAL,
   6732         0,
   6733         8,
   6734         soc_XLMAC_CLEAR_FIFO_STATUS_BCM88470_A0r_fields,
   6735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6736         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6737         -1,
   6738         -1,
   6739     },
   6740 #endif /* chips */
   6741 
   6742 #if defined(BCM_88470_B0)
   6743     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM88470_B0r */
   6744         soc_block_list[56],
   6745         soc_portreg,
   6746         1,
   6747         0,
   6748         0x61800,
   6749         SOC_REG_FLAG_64_BITS,
   6750         0,
   6751         8,
   6752         soc_XLMAC_CLEAR_FIFO_STATUS_BCM88470_B0r_fields,
   6753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6754         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6755         -1,
   6756         -1,
   6757     },
   6758 #endif /* chips */
   6759 
   6760 #if defined(BCM_88675_A0)
   6761     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM88675_A0r */
   6762         soc_block_list[56],
   6763         soc_portreg,
   6764         1,
   6765         0,
   6766         0x61800,
   6767         SOC_REG_FLAG_64_BITS |
   6768                           SOC_REG_FLAG_RO |
   6769                           SOC_REG_FLAG_SIGNAL,
   6770         0,
   6771         8,
   6772         soc_XLMAC_CLEAR_FIFO_STATUS_BCM88675_A0r_fields,
   6773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6774         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6775         -1,
   6776         -1,
   6777     },
   6778 #endif /* chips */
   6779 
   6780 #if defined(BCM_88675_B0)
   6781     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM88675_B0r */
   6782         soc_block_list[56],
   6783         soc_portreg,
   6784         1,
   6785         0,
   6786         0x61800,
   6787         SOC_REG_FLAG_64_BITS,
   6788         0,
   6789         8,
   6790         soc_XLMAC_CLEAR_FIFO_STATUS_BCM88675_B0r_fields,
   6791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6792         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6793         -1,
   6794         -1,
   6795     },
   6796 #endif /* chips */
   6797 
   6798 #if defined(BCM_88680_A0)
   6799     { /* SOC_REG_INT_XLMAC_CLEAR_FIFO_STATUS_BCM88680_A0r */
   6800         soc_block_list[56],
   6801         soc_portreg,
   6802         1,
   6803         0,
   6804         0x61800,
   6805         SOC_REG_FLAG_64_BITS,
   6806         0,
   6807         8,
   6808         soc_XLMAC_CLEAR_FIFO_STATUS_BCM88680_A0r_fields,
   6809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6810         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6811         -1,
   6812         -1,
   6813     },
   6814 #endif /* chips */
   6815 
   6816 #if defined(BCM_2801PM_A0)
   6817     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUSr */
   6818         soc_block_list[56],
   6819         soc_portreg,
   6820         1,
   6821         0,
   6822         0x60c00,
   6823         0,
   6824         0,
   6825         3,
   6826         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   6827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6828         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6829         -1,
   6830         -1,
   6831     },
   6832 #endif /* chips */
   6833 
   6834 #if defined(BCM_53400_A0)
   6835     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM53400_A0r */
   6836         soc_block_list[16],
   6837         soc_portreg,
   6838         1,
   6839         0,
   6840         0x60c00,
   6841         SOC_REG_FLAG_64_BITS,
   6842         0,
   6843         3,
   6844         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   6845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6846         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6847         -1,
   6848         -1,
   6849     },
   6850 #endif /* chips */
   6851 
   6852 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   6853     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM53570_A0r */
   6854         soc_block_list[16],
   6855         soc_portreg,
   6856         1,
   6857         0,
   6858         0x60b00,
   6859         SOC_REG_FLAG_64_BITS,
   6860         0,
   6861         3,
   6862         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   6863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6864         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6865         -1,
   6866         -1,
   6867     },
   6868 #endif /* chips */
   6869 
   6870 #if defined(BCM_56150_A0)
   6871     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM56150_A0r */
   6872         soc_block_list[16],
   6873         soc_portreg,
   6874         1,
   6875         0,
   6876         0x60c00,
   6877         SOC_REG_FLAG_64_BITS,
   6878         0,
   6879         3,
   6880         soc_XMAC_CLEAR_RX_LSS_STATUS_BCM56640_A0r_fields,
   6881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6882         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6883         -1,
   6884         -1,
   6885     },
   6886 #endif /* chips */
   6887 
   6888 #if defined(BCM_56160_A0)
   6889     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM56160_A0r */
   6890         soc_block_list[16],
   6891         soc_portreg,
   6892         1,
   6893         0,
   6894         0x60c00,
   6895         SOC_REG_FLAG_64_BITS,
   6896         0,
   6897         3,
   6898         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   6899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6900         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6901         -1,
   6902         -1,
   6903     },
   6904 #endif /* chips */
   6905 
   6906 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   6907     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM56260_A0r */
   6908         soc_block_list[220],
   6909         soc_portreg,
   6910         1,
   6911         0,
   6912         0x60c00,
   6913         SOC_REG_FLAG_64_BITS,
   6914         0,
   6915         3,
   6916         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   6917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6918         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6919         -1,
   6920         -1,
   6921     },
   6922 #endif /* chips */
   6923 
   6924 #if defined(BCM_56270_A0)
   6925     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM56270_A0r */
   6926         soc_block_list[220],
   6927         soc_portreg,
   6928         1,
   6929         0,
   6930         0x60c00,
   6931         SOC_REG_FLAG_64_BITS,
   6932         0,
   6933         3,
   6934         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   6935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6936         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6937         -1,
   6938         -1,
   6939     },
   6940 #endif /* chips */
   6941 
   6942 #if defined(BCM_56370_A0)
   6943     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM56370_A0r */
   6944         soc_block_list[16],
   6945         soc_portreg,
   6946         1,
   6947         0,
   6948         0x60c00,
   6949         SOC_REG_FLAG_64_BITS,
   6950         0,
   6951         3,
   6952         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   6953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6954         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6955         -1,
   6956         -1,
   6957         3,
   6958     },
   6959 #endif /* chips */
   6960 
   6961 #if defined(BCM_56560_A0)
   6962     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM56560_A0r */
   6963         soc_block_list[16],
   6964         soc_portreg,
   6965         1,
   6966         0,
   6967         0x60c00,
   6968         SOC_REG_FLAG_64_BITS,
   6969         0,
   6970         3,
   6971         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   6972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6973         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6974         -1,
   6975         -1,
   6976     },
   6977 #endif /* chips */
   6978 
   6979 #if defined(BCM_56560_B0)
   6980     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM56560_B0r */
   6981         soc_block_list[16],
   6982         soc_portreg,
   6983         1,
   6984         0,
   6985         0x60c00,
   6986         SOC_REG_FLAG_64_BITS,
   6987         0,
   6988         3,
   6989         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   6990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6991         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   6992         -1,
   6993         -1,
   6994     },
   6995 #endif /* chips */
   6996 
   6997 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   6998     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM56670_A0r */
   6999         soc_block_list[16],
   7000         soc_portreg,
   7001         1,
   7002         0,
   7003         0x60b00,
   7004         SOC_REG_FLAG_64_BITS,
   7005         0,
   7006         3,
   7007         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   7008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7009         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7010         -1,
   7011         -1,
   7012     },
   7013 #endif /* chips */
   7014 
   7015 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   7016     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM56850_A0r */
   7017         soc_block_list[16],
   7018         soc_portreg,
   7019         1,
   7020         0,
   7021         0x60c00,
   7022         SOC_REG_FLAG_64_BITS,
   7023         0,
   7024         3,
   7025         soc_XMAC_CLEAR_RX_LSS_STATUS_BCM56640_A0r_fields,
   7026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7027         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7028         -1,
   7029         -1,
   7030     },
   7031 #endif /* chips */
   7032 
   7033 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7034     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   7035     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   7036     defined(BCM_56980_B0)
   7037     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM56960_A0r */
   7038         soc_block_list[16],
   7039         soc_portreg,
   7040         1,
   7041         0,
   7042         0x60c00,
   7043         SOC_REG_FLAG_64_BITS,
   7044         0,
   7045         3,
   7046         soc_CLMAC_CLEAR_RX_LSS_STATUSr_fields,
   7047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7048         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7049         -1,
   7050         -1,
   7051         3,
   7052     },
   7053 #endif /* chips */
   7054 
   7055 #if defined(BCM_88270_A0)
   7056     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM88270_A0r */
   7057         soc_block_list[221],
   7058         soc_portreg,
   7059         1,
   7060         0,
   7061         0x60c00,
   7062         SOC_REG_FLAG_64_BITS,
   7063         0,
   7064         3,
   7065         soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88270_A0r_fields,
   7066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7067         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7068         -1,
   7069         -1,
   7070     },
   7071 #endif /* chips */
   7072 
   7073 #if defined(BCM_88375_A0)
   7074     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM88375_A0r */
   7075         soc_block_list[56],
   7076         soc_portreg,
   7077         1,
   7078         0,
   7079         0x60c00,
   7080         SOC_REG_FLAG_64_BITS,
   7081         0,
   7082         3,
   7083         soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88375_A0r_fields,
   7084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7085         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7086         -1,
   7087         -1,
   7088     },
   7089 #endif /* chips */
   7090 
   7091 #if defined(BCM_88375_B0)
   7092     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM88375_B0r */
   7093         soc_block_list[56],
   7094         soc_portreg,
   7095         1,
   7096         0,
   7097         0x60c00,
   7098         SOC_REG_FLAG_64_BITS,
   7099         0,
   7100         3,
   7101         soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88375_B0r_fields,
   7102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7103         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7104         -1,
   7105         -1,
   7106     },
   7107 #endif /* chips */
   7108 
   7109 #if defined(BCM_88470_A0)
   7110     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM88470_A0r */
   7111         soc_block_list[56],
   7112         soc_portreg,
   7113         1,
   7114         0,
   7115         0x60c00,
   7116         SOC_REG_FLAG_64_BITS,
   7117         0,
   7118         3,
   7119         soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88470_A0r_fields,
   7120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7121         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7122         -1,
   7123         -1,
   7124     },
   7125 #endif /* chips */
   7126 
   7127 #if defined(BCM_88470_B0)
   7128     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM88470_B0r */
   7129         soc_block_list[56],
   7130         soc_portreg,
   7131         1,
   7132         0,
   7133         0x60c00,
   7134         SOC_REG_FLAG_64_BITS,
   7135         0,
   7136         3,
   7137         soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88470_B0r_fields,
   7138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7139         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7140         -1,
   7141         -1,
   7142     },
   7143 #endif /* chips */
   7144 
   7145 #if defined(BCM_88675_A0)
   7146     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM88675_A0r */
   7147         soc_block_list[56],
   7148         soc_portreg,
   7149         1,
   7150         0,
   7151         0x60c00,
   7152         SOC_REG_FLAG_64_BITS,
   7153         0,
   7154         3,
   7155         soc_XLMAC_CLEAR_RX_LSS_STATUSr_fields,
   7156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7157         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7158         -1,
   7159         -1,
   7160     },
   7161 #endif /* chips */
   7162 
   7163 #if defined(BCM_88675_B0)
   7164     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM88675_B0r */
   7165         soc_block_list[56],
   7166         soc_portreg,
   7167         1,
   7168         0,
   7169         0x60c00,
   7170         SOC_REG_FLAG_64_BITS,
   7171         0,
   7172         3,
   7173         soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88675_B0r_fields,
   7174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7175         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7176         -1,
   7177         -1,
   7178     },
   7179 #endif /* chips */
   7180 
   7181 #if defined(BCM_88680_A0)
   7182     { /* SOC_REG_INT_XLMAC_CLEAR_RX_LSS_STATUS_BCM88680_A0r */
   7183         soc_block_list[56],
   7184         soc_portreg,
   7185         1,
   7186         0,
   7187         0x60c00,
   7188         SOC_REG_FLAG_64_BITS,
   7189         0,
   7190         3,
   7191         soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88680_A0r_fields,
   7192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7193         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7194         -1,
   7195         -1,
   7196     },
   7197 #endif /* chips */
   7198 
   7199 #if defined(BCM_2801PM_A0)
   7200     { /* SOC_REG_INT_XLMAC_CTRLr */
   7201         soc_block_list[56],
   7202         soc_portreg,
   7203         1,
   7204         0,
   7205         0x60000,
   7206         0,
   7207         0,
   7208         15,
   7209         soc_XLMAC_CTRLr_fields,
   7210         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7211         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7212         -1,
   7213         -1,
   7214     },
   7215 #endif /* chips */
   7216 
   7217 #if defined(BCM_53400_A0)
   7218     { /* SOC_REG_INT_XLMAC_CTRL_BCM53400_A0r */
   7219         soc_block_list[16],
   7220         soc_portreg,
   7221         1,
   7222         0,
   7223         0x60000,
   7224         SOC_REG_FLAG_64_BITS,
   7225         0,
   7226         15,
   7227         soc_XLMAC_CTRL_BCM53400_A0r_fields,
   7228         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7229         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7230         -1,
   7231         -1,
   7232     },
   7233 #endif /* chips */
   7234 
   7235 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   7236     { /* SOC_REG_INT_XLMAC_CTRL_BCM53570_A0r */
   7237         soc_block_list[16],
   7238         soc_portreg,
   7239         1,
   7240         0,
   7241         0x60100,
   7242         SOC_REG_FLAG_64_BITS,
   7243         0,
   7244         15,
   7245         soc_XLMAC_B0_CTRLr_fields,
   7246         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7247         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7248         -1,
   7249         -1,
   7250     },
   7251 #endif /* chips */
   7252 
   7253 #if defined(BCM_56150_A0)
   7254     { /* SOC_REG_INT_XLMAC_CTRL_BCM56150_A0r */
   7255         soc_block_list[16],
   7256         soc_portreg,
   7257         1,
   7258         0,
   7259         0x60000,
   7260         SOC_REG_FLAG_64_BITS,
   7261         0,
   7262         15,
   7263         soc_XLMAC_CTRL_BCM56850_A0r_fields,
   7264         SOC_RESET_VAL_DEC(0x00001040, 0x00000000)
   7265         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7266         -1,
   7267         -1,
   7268     },
   7269 #endif /* chips */
   7270 
   7271 #if defined(BCM_56160_A0)
   7272     { /* SOC_REG_INT_XLMAC_CTRL_BCM56160_A0r */
   7273         soc_block_list[16],
   7274         soc_portreg,
   7275         1,
   7276         0,
   7277         0x60000,
   7278         SOC_REG_FLAG_64_BITS,
   7279         0,
   7280         15,
   7281         soc_XLMAC_B0_CTRLr_fields,
   7282         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7283         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7284         -1,
   7285         -1,
   7286     },
   7287 #endif /* chips */
   7288 
   7289 #if defined(BCM_56260_A0)
   7290     { /* SOC_REG_INT_XLMAC_CTRL_BCM56260_A0r */
   7291         soc_block_list[220],
   7292         soc_portreg,
   7293         1,
   7294         0,
   7295         0x60000,
   7296         SOC_REG_FLAG_64_BITS,
   7297         0,
   7298         15,
   7299         soc_XLMAC_CTRL_BCM53400_A0r_fields,
   7300         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7301         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7302         -1,
   7303         -1,
   7304     },
   7305 #endif /* chips */
   7306 
   7307 #if defined(BCM_56260_B0)
   7308     { /* SOC_REG_INT_XLMAC_CTRL_BCM56260_B0r */
   7309         soc_block_list[220],
   7310         soc_portreg,
   7311         1,
   7312         0,
   7313         0x60000,
   7314         SOC_REG_FLAG_64_BITS,
   7315         0,
   7316         15,
   7317         soc_XLMAC_B0_CTRLr_fields,
   7318         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7319         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7320         -1,
   7321         -1,
   7322     },
   7323 #endif /* chips */
   7324 
   7325 #if defined(BCM_56270_A0)
   7326     { /* SOC_REG_INT_XLMAC_CTRL_BCM56270_A0r */
   7327         soc_block_list[220],
   7328         soc_portreg,
   7329         1,
   7330         0,
   7331         0x60000,
   7332         SOC_REG_FLAG_64_BITS,
   7333         0,
   7334         15,
   7335         soc_XLMAC_B0_CTRLr_fields,
   7336         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7337         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7338         -1,
   7339         -1,
   7340     },
   7341 #endif /* chips */
   7342 
   7343 #if defined(BCM_56370_A0)
   7344     { /* SOC_REG_INT_XLMAC_CTRL_BCM56370_A0r */
   7345         soc_block_list[16],
   7346         soc_portreg,
   7347         1,
   7348         0,
   7349         0x60000,
   7350         SOC_REG_FLAG_64_BITS,
   7351         0,
   7352         15,
   7353         soc_XLMAC_B0_CTRLr_fields,
   7354         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7355         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7356         -1,
   7357         -1,
   7358         3,
   7359     },
   7360 #endif /* chips */
   7361 
   7362 #if defined(BCM_56560_A0)
   7363     { /* SOC_REG_INT_XLMAC_CTRL_BCM56560_A0r */
   7364         soc_block_list[16],
   7365         soc_portreg,
   7366         1,
   7367         0,
   7368         0x60000,
   7369         SOC_REG_FLAG_64_BITS,
   7370         0,
   7371         15,
   7372         soc_XLMAC_CTRL_BCM53400_A0r_fields,
   7373         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7374         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7375         -1,
   7376         -1,
   7377     },
   7378 #endif /* chips */
   7379 
   7380 #if defined(BCM_56560_B0)
   7381     { /* SOC_REG_INT_XLMAC_CTRL_BCM56560_B0r */
   7382         soc_block_list[16],
   7383         soc_portreg,
   7384         1,
   7385         0,
   7386         0x60000,
   7387         SOC_REG_FLAG_64_BITS,
   7388         0,
   7389         15,
   7390         soc_XLMAC_B0_CTRLr_fields,
   7391         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7392         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7393         -1,
   7394         -1,
   7395     },
   7396 #endif /* chips */
   7397 
   7398 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   7399     { /* SOC_REG_INT_XLMAC_CTRL_BCM56670_A0r */
   7400         soc_block_list[16],
   7401         soc_portreg,
   7402         1,
   7403         0,
   7404         0x60100,
   7405         SOC_REG_FLAG_64_BITS,
   7406         0,
   7407         15,
   7408         soc_XLMAC_B0_CTRLr_fields,
   7409         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7410         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7411         -1,
   7412         -1,
   7413     },
   7414 #endif /* chips */
   7415 
   7416 #if defined(BCM_56850_A0)
   7417     { /* SOC_REG_INT_XLMAC_CTRL_BCM56850_A0r */
   7418         soc_block_list[16],
   7419         soc_portreg,
   7420         1,
   7421         0,
   7422         0x60000,
   7423         SOC_REG_FLAG_64_BITS,
   7424         0,
   7425         15,
   7426         soc_XLMAC_CTRL_BCM56850_A0r_fields,
   7427         SOC_RESET_VAL_DEC(0x00001040, 0x00000000)
   7428         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7429         -1,
   7430         -1,
   7431     },
   7432 #endif /* chips */
   7433 
   7434 #if defined(BCM_56860_A0)
   7435     { /* SOC_REG_INT_XLMAC_CTRL_BCM56860_A0r */
   7436         soc_block_list[16],
   7437         soc_portreg,
   7438         1,
   7439         0,
   7440         0x60000,
   7441         SOC_REG_FLAG_64_BITS,
   7442         0,
   7443         15,
   7444         soc_XLMAC_CTRL_BCM56860_A0r_fields,
   7445         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7446         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7447         -1,
   7448         -1,
   7449     },
   7450 #endif /* chips */
   7451 
   7452 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7453     { /* SOC_REG_INT_XLMAC_CTRL_BCM56960_A0r */
   7454         soc_block_list[16],
   7455         soc_portreg,
   7456         1,
   7457         0,
   7458         0x60000,
   7459         SOC_REG_FLAG_64_BITS,
   7460         0,
   7461         15,
   7462         soc_XLMAC_CTRL_BCM53400_A0r_fields,
   7463         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7464         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7465         -1,
   7466         -1,
   7467         3,
   7468     },
   7469 #endif /* chips */
   7470 
   7471 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7472     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   7473     defined(BCM_56980_B0)
   7474     { /* SOC_REG_INT_XLMAC_CTRL_BCM56970_A0r */
   7475         soc_block_list[16],
   7476         soc_portreg,
   7477         1,
   7478         0,
   7479         0x60000,
   7480         SOC_REG_FLAG_64_BITS,
   7481         0,
   7482         15,
   7483         soc_XLMAC_B0_CTRLr_fields,
   7484         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7485         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7486         -1,
   7487         -1,
   7488         3,
   7489     },
   7490 #endif /* chips */
   7491 
   7492 #if defined(BCM_88270_A0)
   7493     { /* SOC_REG_INT_XLMAC_CTRL_BCM88270_A0r */
   7494         soc_block_list[221],
   7495         soc_portreg,
   7496         1,
   7497         0,
   7498         0x60000,
   7499         SOC_REG_FLAG_64_BITS,
   7500         0,
   7501         15,
   7502         soc_XLMAC_CTRL_BCM88270_A0r_fields,
   7503         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7504         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7505         -1,
   7506         -1,
   7507     },
   7508 #endif /* chips */
   7509 
   7510 #if defined(BCM_88375_A0)
   7511     { /* SOC_REG_INT_XLMAC_CTRL_BCM88375_A0r */
   7512         soc_block_list[56],
   7513         soc_portreg,
   7514         1,
   7515         0,
   7516         0x60000,
   7517         SOC_REG_FLAG_64_BITS,
   7518         0,
   7519         15,
   7520         soc_XLMAC_CTRL_BCM88375_A0r_fields,
   7521         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7522         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7523         -1,
   7524         -1,
   7525     },
   7526 #endif /* chips */
   7527 
   7528 #if defined(BCM_88375_B0)
   7529     { /* SOC_REG_INT_XLMAC_CTRL_BCM88375_B0r */
   7530         soc_block_list[56],
   7531         soc_portreg,
   7532         1,
   7533         0,
   7534         0x60000,
   7535         SOC_REG_FLAG_64_BITS,
   7536         0,
   7537         15,
   7538         soc_XLMAC_CTRL_BCM88375_B0r_fields,
   7539         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7540         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7541         -1,
   7542         -1,
   7543     },
   7544 #endif /* chips */
   7545 
   7546 #if defined(BCM_88470_A0)
   7547     { /* SOC_REG_INT_XLMAC_CTRL_BCM88470_A0r */
   7548         soc_block_list[56],
   7549         soc_portreg,
   7550         1,
   7551         0,
   7552         0x60000,
   7553         SOC_REG_FLAG_64_BITS,
   7554         0,
   7555         15,
   7556         soc_XLMAC_CTRL_BCM88470_A0r_fields,
   7557         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7558         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7559         -1,
   7560         -1,
   7561     },
   7562 #endif /* chips */
   7563 
   7564 #if defined(BCM_88470_B0)
   7565     { /* SOC_REG_INT_XLMAC_CTRL_BCM88470_B0r */
   7566         soc_block_list[56],
   7567         soc_portreg,
   7568         1,
   7569         0,
   7570         0x60000,
   7571         SOC_REG_FLAG_64_BITS,
   7572         0,
   7573         15,
   7574         soc_XLMAC_CTRL_BCM88470_B0r_fields,
   7575         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7576         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7577         -1,
   7578         -1,
   7579     },
   7580 #endif /* chips */
   7581 
   7582 #if defined(BCM_88675_A0)
   7583     { /* SOC_REG_INT_XLMAC_CTRL_BCM88675_A0r */
   7584         soc_block_list[56],
   7585         soc_portreg,
   7586         1,
   7587         0,
   7588         0x60000,
   7589         SOC_REG_FLAG_64_BITS,
   7590         0,
   7591         15,
   7592         soc_XLMAC_CTRL_BCM88675_A0r_fields,
   7593         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7594         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7595         -1,
   7596         -1,
   7597     },
   7598 #endif /* chips */
   7599 
   7600 #if defined(BCM_88675_B0)
   7601     { /* SOC_REG_INT_XLMAC_CTRL_BCM88675_B0r */
   7602         soc_block_list[56],
   7603         soc_portreg,
   7604         1,
   7605         0,
   7606         0x60000,
   7607         SOC_REG_FLAG_64_BITS,
   7608         0,
   7609         15,
   7610         soc_XLMAC_CTRL_BCM88675_B0r_fields,
   7611         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7612         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7613         -1,
   7614         -1,
   7615     },
   7616 #endif /* chips */
   7617 
   7618 #if defined(BCM_88680_A0)
   7619     { /* SOC_REG_INT_XLMAC_CTRL_BCM88680_A0r */
   7620         soc_block_list[56],
   7621         soc_portreg,
   7622         1,
   7623         0,
   7624         0x60000,
   7625         SOC_REG_FLAG_64_BITS,
   7626         0,
   7627         15,
   7628         soc_XLMAC_CTRL_BCM88680_A0r_fields,
   7629         SOC_RESET_VAL_DEC(0x00005040, 0x00000000)
   7630         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   7631         -1,
   7632         -1,
   7633     },
   7634 #endif /* chips */
   7635 
   7636 #if defined(BCM_2801PM_A0)
   7637     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0r */
   7638         soc_block_list[56],
   7639         soc_portreg,
   7640         1,
   7641         0,
   7642         0x62500,
   7643         SOC_REG_FLAG_64_BITS,
   7644         0,
   7645         1,
   7646         soc_CLMAC_E2ECC_DATA_HDR_0r_fields,
   7647         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7648         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7649         -1,
   7650         -1,
   7651     },
   7652 #endif /* chips */
   7653 
   7654 #if defined(BCM_2801PM_A0)
   7655     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1r */
   7656         soc_block_list[56],
   7657         soc_portreg,
   7658         1,
   7659         0,
   7660         0x62600,
   7661         SOC_REG_FLAG_64_BITS,
   7662         0,
   7663         1,
   7664         soc_CLMAC_E2ECC_DATA_HDR_1r_fields,
   7665         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   7666         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7667         -1,
   7668         -1,
   7669     },
   7670 #endif /* chips */
   7671 
   7672 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
   7673     defined(BCM_56670_B0)
   7674     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r */
   7675         soc_block_list[16],
   7676         soc_portreg,
   7677         1,
   7678         0,
   7679         0x62500,
   7680         SOC_REG_FLAG_64_BITS,
   7681         0,
   7682         3,
   7683         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   7684         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7685         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7686         -1,
   7687         -1,
   7688     },
   7689 #endif /* chips */
   7690 
   7691 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   7692     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM53570_A0r */
   7693         soc_block_list[16],
   7694         soc_portreg,
   7695         1,
   7696         0,
   7697         0x62500,
   7698         SOC_REG_FLAG_64_BITS,
   7699         0,
   7700         3,
   7701         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   7702         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7703         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7704         -1,
   7705         -1,
   7706     },
   7707 #endif /* chips */
   7708 
   7709 #if defined(BCM_56150_A0)
   7710     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56150_A0r */
   7711         soc_block_list[16],
   7712         soc_portreg,
   7713         1,
   7714         0,
   7715         0x62500,
   7716         SOC_REG_FLAG_64_BITS,
   7717         0,
   7718         3,
   7719         soc_XLMAC_E2ECC_DATA_HDR_0_BCM56850_A0r_fields,
   7720         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7721         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7722         -1,
   7723         -1,
   7724     },
   7725 #endif /* chips */
   7726 
   7727 #if defined(BCM_56160_A0)
   7728     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56160_A0r */
   7729         soc_block_list[16],
   7730         soc_portreg,
   7731         1,
   7732         0,
   7733         0x62600,
   7734         SOC_REG_FLAG_64_BITS,
   7735         0,
   7736         3,
   7737         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   7738         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7739         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7740         -1,
   7741         -1,
   7742     },
   7743 #endif /* chips */
   7744 
   7745 #if defined(BCM_56260_A0)
   7746     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56260_A0r */
   7747         soc_block_list[220],
   7748         soc_portreg,
   7749         1,
   7750         0,
   7751         0x62500,
   7752         SOC_REG_FLAG_64_BITS,
   7753         0,
   7754         3,
   7755         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   7756         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7757         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7758         -1,
   7759         -1,
   7760     },
   7761 #endif /* chips */
   7762 
   7763 #if defined(BCM_56260_B0)
   7764     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56260_B0r */
   7765         soc_block_list[220],
   7766         soc_portreg,
   7767         1,
   7768         0,
   7769         0x62600,
   7770         SOC_REG_FLAG_64_BITS,
   7771         0,
   7772         3,
   7773         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   7774         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7775         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7776         -1,
   7777         -1,
   7778     },
   7779 #endif /* chips */
   7780 
   7781 #if defined(BCM_56270_A0)
   7782     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56270_A0r */
   7783         soc_block_list[220],
   7784         soc_portreg,
   7785         1,
   7786         0,
   7787         0x62600,
   7788         SOC_REG_FLAG_64_BITS,
   7789         0,
   7790         3,
   7791         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   7792         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7793         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7794         -1,
   7795         -1,
   7796     },
   7797 #endif /* chips */
   7798 
   7799 #if defined(BCM_56370_A0)
   7800     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56370_A0r */
   7801         soc_block_list[16],
   7802         soc_portreg,
   7803         1,
   7804         0,
   7805         0x62600,
   7806         SOC_REG_FLAG_64_BITS,
   7807         0,
   7808         3,
   7809         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   7810         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7811         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7812         -1,
   7813         -1,
   7814         3,
   7815     },
   7816 #endif /* chips */
   7817 
   7818 #if defined(BCM_56560_A0)
   7819     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56560_A0r */
   7820         soc_block_list[16],
   7821         soc_portreg,
   7822         1,
   7823         0,
   7824         0x62500,
   7825         SOC_REG_FLAG_64_BITS,
   7826         0,
   7827         3,
   7828         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   7829         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7830         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7831         -1,
   7832         -1,
   7833     },
   7834 #endif /* chips */
   7835 
   7836 #if defined(BCM_56560_B0)
   7837     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56560_B0r */
   7838         soc_block_list[16],
   7839         soc_portreg,
   7840         1,
   7841         0,
   7842         0x62600,
   7843         SOC_REG_FLAG_64_BITS,
   7844         0,
   7845         3,
   7846         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   7847         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7848         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7849         -1,
   7850         -1,
   7851     },
   7852 #endif /* chips */
   7853 
   7854 #if defined(BCM_56850_A0)
   7855     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56850_A0r */
   7856         soc_block_list[16],
   7857         soc_portreg,
   7858         1,
   7859         0,
   7860         0x62500,
   7861         SOC_REG_FLAG_64_BITS,
   7862         0,
   7863         3,
   7864         soc_XLMAC_E2ECC_DATA_HDR_0_BCM56850_A0r_fields,
   7865         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7866         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7867         -1,
   7868         -1,
   7869     },
   7870 #endif /* chips */
   7871 
   7872 #if defined(BCM_56860_A0)
   7873     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56860_A0r */
   7874         soc_block_list[16],
   7875         soc_portreg,
   7876         1,
   7877         0,
   7878         0x62600,
   7879         SOC_REG_FLAG_64_BITS,
   7880         0,
   7881         3,
   7882         soc_XLMAC_E2ECC_DATA_HDR_0_BCM56850_A0r_fields,
   7883         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7884         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7885         -1,
   7886         -1,
   7887     },
   7888 #endif /* chips */
   7889 
   7890 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7891     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56960_A0r */
   7892         soc_block_list[16],
   7893         soc_portreg,
   7894         1,
   7895         0,
   7896         0x62500,
   7897         SOC_REG_FLAG_64_BITS,
   7898         0,
   7899         3,
   7900         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   7901         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7902         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7903         -1,
   7904         -1,
   7905         3,
   7906     },
   7907 #endif /* chips */
   7908 
   7909 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7910     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   7911     defined(BCM_56980_B0)
   7912     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM56970_A0r */
   7913         soc_block_list[16],
   7914         soc_portreg,
   7915         1,
   7916         0,
   7917         0x62600,
   7918         SOC_REG_FLAG_64_BITS,
   7919         0,
   7920         3,
   7921         soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields,
   7922         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7923         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7924         -1,
   7925         -1,
   7926         3,
   7927     },
   7928 #endif /* chips */
   7929 
   7930 #if defined(BCM_88270_A0)
   7931     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM88270_A0r */
   7932         soc_block_list[221],
   7933         soc_portreg,
   7934         1,
   7935         0,
   7936         0x62600,
   7937         SOC_REG_FLAG_64_BITS,
   7938         0,
   7939         1,
   7940         soc_XLMAC_E2ECC_DATA_HDR_0_BCM88270_A0r_fields,
   7941         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7942         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7943         -1,
   7944         -1,
   7945     },
   7946 #endif /* chips */
   7947 
   7948 #if defined(BCM_88375_A0)
   7949     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM88375_A0r */
   7950         soc_block_list[56],
   7951         soc_portreg,
   7952         1,
   7953         0,
   7954         0x62500,
   7955         SOC_REG_FLAG_64_BITS,
   7956         0,
   7957         1,
   7958         soc_XLMAC_E2ECC_DATA_HDR_0_BCM88375_A0r_fields,
   7959         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7960         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7961         -1,
   7962         -1,
   7963     },
   7964 #endif /* chips */
   7965 
   7966 #if defined(BCM_88375_B0)
   7967     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM88375_B0r */
   7968         soc_block_list[56],
   7969         soc_portreg,
   7970         1,
   7971         0,
   7972         0x62600,
   7973         SOC_REG_FLAG_64_BITS,
   7974         0,
   7975         1,
   7976         soc_XLMAC_E2ECC_DATA_HDR_0_BCM88375_B0r_fields,
   7977         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7978         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7979         -1,
   7980         -1,
   7981     },
   7982 #endif /* chips */
   7983 
   7984 #if defined(BCM_88470_A0)
   7985     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM88470_A0r */
   7986         soc_block_list[56],
   7987         soc_portreg,
   7988         1,
   7989         0,
   7990         0x62500,
   7991         SOC_REG_FLAG_64_BITS,
   7992         0,
   7993         1,
   7994         soc_XLMAC_E2ECC_DATA_HDR_0_BCM88470_A0r_fields,
   7995         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   7996         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7997         -1,
   7998         -1,
   7999     },
   8000 #endif /* chips */
   8001 
   8002 #if defined(BCM_88470_B0)
   8003     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM88470_B0r */
   8004         soc_block_list[56],
   8005         soc_portreg,
   8006         1,
   8007         0,
   8008         0x62600,
   8009         SOC_REG_FLAG_64_BITS,
   8010         0,
   8011         1,
   8012         soc_XLMAC_E2ECC_DATA_HDR_0_BCM88470_B0r_fields,
   8013         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   8014         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8015         -1,
   8016         -1,
   8017     },
   8018 #endif /* chips */
   8019 
   8020 #if defined(BCM_88675_A0)
   8021     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM88675_A0r */
   8022         soc_block_list[56],
   8023         soc_portreg,
   8024         1,
   8025         0,
   8026         0x62500,
   8027         SOC_REG_FLAG_64_BITS,
   8028         0,
   8029         1,
   8030         soc_XLMAC_E2ECC_DATA_HDR_0r_fields,
   8031         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   8032         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8033         -1,
   8034         -1,
   8035     },
   8036 #endif /* chips */
   8037 
   8038 #if defined(BCM_88675_B0)
   8039     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM88675_B0r */
   8040         soc_block_list[56],
   8041         soc_portreg,
   8042         1,
   8043         0,
   8044         0x62600,
   8045         SOC_REG_FLAG_64_BITS,
   8046         0,
   8047         1,
   8048         soc_XLMAC_E2ECC_DATA_HDR_0_BCM88675_B0r_fields,
   8049         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   8050         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8051         -1,
   8052         -1,
   8053     },
   8054 #endif /* chips */
   8055 
   8056 #if defined(BCM_88680_A0)
   8057     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_0_BCM88680_A0r */
   8058         soc_block_list[56],
   8059         soc_portreg,
   8060         1,
   8061         0,
   8062         0x62600,
   8063         SOC_REG_FLAG_64_BITS,
   8064         0,
   8065         1,
   8066         soc_XLMAC_E2ECC_DATA_HDR_0_BCM88680_A0r_fields,
   8067         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   8068         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8069         -1,
   8070         -1,
   8071     },
   8072 #endif /* chips */
   8073 
   8074 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
   8075     defined(BCM_56670_B0)
   8076     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r */
   8077         soc_block_list[16],
   8078         soc_portreg,
   8079         1,
   8080         0,
   8081         0x62600,
   8082         SOC_REG_FLAG_64_BITS,
   8083         0,
   8084         3,
   8085         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   8086         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8087         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8088         -1,
   8089         -1,
   8090     },
   8091 #endif /* chips */
   8092 
   8093 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8094     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM53570_A0r */
   8095         soc_block_list[16],
   8096         soc_portreg,
   8097         1,
   8098         0,
   8099         0x62600,
   8100         SOC_REG_FLAG_64_BITS,
   8101         0,
   8102         3,
   8103         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   8104         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8105         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8106         -1,
   8107         -1,
   8108     },
   8109 #endif /* chips */
   8110 
   8111 #if defined(BCM_56150_A0)
   8112     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56150_A0r */
   8113         soc_block_list[16],
   8114         soc_portreg,
   8115         1,
   8116         0,
   8117         0x62600,
   8118         SOC_REG_FLAG_64_BITS,
   8119         0,
   8120         3,
   8121         soc_XLMAC_E2ECC_DATA_HDR_1_BCM56850_A0r_fields,
   8122         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8123         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8124         -1,
   8125         -1,
   8126     },
   8127 #endif /* chips */
   8128 
   8129 #if defined(BCM_56160_A0)
   8130     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56160_A0r */
   8131         soc_block_list[16],
   8132         soc_portreg,
   8133         1,
   8134         0,
   8135         0x62700,
   8136         SOC_REG_FLAG_64_BITS,
   8137         0,
   8138         3,
   8139         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   8140         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8141         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8142         -1,
   8143         -1,
   8144     },
   8145 #endif /* chips */
   8146 
   8147 #if defined(BCM_56260_A0)
   8148     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56260_A0r */
   8149         soc_block_list[220],
   8150         soc_portreg,
   8151         1,
   8152         0,
   8153         0x62600,
   8154         SOC_REG_FLAG_64_BITS,
   8155         0,
   8156         3,
   8157         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   8158         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8159         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8160         -1,
   8161         -1,
   8162     },
   8163 #endif /* chips */
   8164 
   8165 #if defined(BCM_56260_B0)
   8166     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56260_B0r */
   8167         soc_block_list[220],
   8168         soc_portreg,
   8169         1,
   8170         0,
   8171         0x62700,
   8172         SOC_REG_FLAG_64_BITS,
   8173         0,
   8174         3,
   8175         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   8176         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8177         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8178         -1,
   8179         -1,
   8180     },
   8181 #endif /* chips */
   8182 
   8183 #if defined(BCM_56270_A0)
   8184     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56270_A0r */
   8185         soc_block_list[220],
   8186         soc_portreg,
   8187         1,
   8188         0,
   8189         0x62700,
   8190         SOC_REG_FLAG_64_BITS,
   8191         0,
   8192         3,
   8193         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   8194         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8195         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8196         -1,
   8197         -1,
   8198     },
   8199 #endif /* chips */
   8200 
   8201 #if defined(BCM_56370_A0)
   8202     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56370_A0r */
   8203         soc_block_list[16],
   8204         soc_portreg,
   8205         1,
   8206         0,
   8207         0x62700,
   8208         SOC_REG_FLAG_64_BITS,
   8209         0,
   8210         3,
   8211         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   8212         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8213         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8214         -1,
   8215         -1,
   8216         3,
   8217     },
   8218 #endif /* chips */
   8219 
   8220 #if defined(BCM_56560_A0)
   8221     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56560_A0r */
   8222         soc_block_list[16],
   8223         soc_portreg,
   8224         1,
   8225         0,
   8226         0x62600,
   8227         SOC_REG_FLAG_64_BITS,
   8228         0,
   8229         3,
   8230         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   8231         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8232         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8233         -1,
   8234         -1,
   8235     },
   8236 #endif /* chips */
   8237 
   8238 #if defined(BCM_56560_B0)
   8239     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56560_B0r */
   8240         soc_block_list[16],
   8241         soc_portreg,
   8242         1,
   8243         0,
   8244         0x62700,
   8245         SOC_REG_FLAG_64_BITS,
   8246         0,
   8247         3,
   8248         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   8249         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8250         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8251         -1,
   8252         -1,
   8253     },
   8254 #endif /* chips */
   8255 
   8256 #if defined(BCM_56850_A0)
   8257     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56850_A0r */
   8258         soc_block_list[16],
   8259         soc_portreg,
   8260         1,
   8261         0,
   8262         0x62600,
   8263         SOC_REG_FLAG_64_BITS,
   8264         0,
   8265         3,
   8266         soc_XLMAC_E2ECC_DATA_HDR_1_BCM56850_A0r_fields,
   8267         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8268         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8269         -1,
   8270         -1,
   8271     },
   8272 #endif /* chips */
   8273 
   8274 #if defined(BCM_56860_A0)
   8275     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56860_A0r */
   8276         soc_block_list[16],
   8277         soc_portreg,
   8278         1,
   8279         0,
   8280         0x62700,
   8281         SOC_REG_FLAG_64_BITS,
   8282         0,
   8283         3,
   8284         soc_XLMAC_E2ECC_DATA_HDR_1_BCM56850_A0r_fields,
   8285         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8286         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8287         -1,
   8288         -1,
   8289     },
   8290 #endif /* chips */
   8291 
   8292 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   8293     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56960_A0r */
   8294         soc_block_list[16],
   8295         soc_portreg,
   8296         1,
   8297         0,
   8298         0x62600,
   8299         SOC_REG_FLAG_64_BITS,
   8300         0,
   8301         3,
   8302         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   8303         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8304         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8305         -1,
   8306         -1,
   8307         3,
   8308     },
   8309 #endif /* chips */
   8310 
   8311 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8312     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   8313     defined(BCM_56980_B0)
   8314     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM56970_A0r */
   8315         soc_block_list[16],
   8316         soc_portreg,
   8317         1,
   8318         0,
   8319         0x62700,
   8320         SOC_REG_FLAG_64_BITS,
   8321         0,
   8322         3,
   8323         soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields,
   8324         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8325         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8326         -1,
   8327         -1,
   8328         3,
   8329     },
   8330 #endif /* chips */
   8331 
   8332 #if defined(BCM_88270_A0)
   8333     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM88270_A0r */
   8334         soc_block_list[221],
   8335         soc_portreg,
   8336         1,
   8337         0,
   8338         0x62700,
   8339         SOC_REG_FLAG_64_BITS,
   8340         0,
   8341         1,
   8342         soc_XLMAC_E2ECC_DATA_HDR_1_BCM88270_A0r_fields,
   8343         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8344         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8345         -1,
   8346         -1,
   8347     },
   8348 #endif /* chips */
   8349 
   8350 #if defined(BCM_88375_A0)
   8351     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM88375_A0r */
   8352         soc_block_list[56],
   8353         soc_portreg,
   8354         1,
   8355         0,
   8356         0x62600,
   8357         SOC_REG_FLAG_64_BITS,
   8358         0,
   8359         1,
   8360         soc_XLMAC_E2ECC_DATA_HDR_1_BCM88375_A0r_fields,
   8361         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8362         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8363         -1,
   8364         -1,
   8365     },
   8366 #endif /* chips */
   8367 
   8368 #if defined(BCM_88375_B0)
   8369     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM88375_B0r */
   8370         soc_block_list[56],
   8371         soc_portreg,
   8372         1,
   8373         0,
   8374         0x62700,
   8375         SOC_REG_FLAG_64_BITS,
   8376         0,
   8377         1,
   8378         soc_XLMAC_E2ECC_DATA_HDR_1_BCM88375_B0r_fields,
   8379         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8380         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8381         -1,
   8382         -1,
   8383     },
   8384 #endif /* chips */
   8385 
   8386 #if defined(BCM_88470_A0)
   8387     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM88470_A0r */
   8388         soc_block_list[56],
   8389         soc_portreg,
   8390         1,
   8391         0,
   8392         0x62600,
   8393         SOC_REG_FLAG_64_BITS,
   8394         0,
   8395         1,
   8396         soc_XLMAC_E2ECC_DATA_HDR_1_BCM88470_A0r_fields,
   8397         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8398         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8399         -1,
   8400         -1,
   8401     },
   8402 #endif /* chips */
   8403 
   8404 #if defined(BCM_88470_B0)
   8405     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM88470_B0r */
   8406         soc_block_list[56],
   8407         soc_portreg,
   8408         1,
   8409         0,
   8410         0x62700,
   8411         SOC_REG_FLAG_64_BITS,
   8412         0,
   8413         1,
   8414         soc_XLMAC_E2ECC_DATA_HDR_1_BCM88470_B0r_fields,
   8415         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8416         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8417         -1,
   8418         -1,
   8419     },
   8420 #endif /* chips */
   8421 
   8422 #if defined(BCM_88675_A0)
   8423     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM88675_A0r */
   8424         soc_block_list[56],
   8425         soc_portreg,
   8426         1,
   8427         0,
   8428         0x62600,
   8429         SOC_REG_FLAG_64_BITS,
   8430         0,
   8431         1,
   8432         soc_XLMAC_E2ECC_DATA_HDR_1r_fields,
   8433         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8434         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8435         -1,
   8436         -1,
   8437     },
   8438 #endif /* chips */
   8439 
   8440 #if defined(BCM_88675_B0)
   8441     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM88675_B0r */
   8442         soc_block_list[56],
   8443         soc_portreg,
   8444         1,
   8445         0,
   8446         0x62700,
   8447         SOC_REG_FLAG_64_BITS,
   8448         0,
   8449         1,
   8450         soc_XLMAC_E2ECC_DATA_HDR_1_BCM88675_B0r_fields,
   8451         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8452         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8453         -1,
   8454         -1,
   8455     },
   8456 #endif /* chips */
   8457 
   8458 #if defined(BCM_88680_A0)
   8459     { /* SOC_REG_INT_XLMAC_E2ECC_DATA_HDR_1_BCM88680_A0r */
   8460         soc_block_list[56],
   8461         soc_portreg,
   8462         1,
   8463         0,
   8464         0x62700,
   8465         SOC_REG_FLAG_64_BITS,
   8466         0,
   8467         1,
   8468         soc_XLMAC_E2ECC_DATA_HDR_1_BCM88680_A0r_fields,
   8469         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   8470         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8471         -1,
   8472         -1,
   8473     },
   8474 #endif /* chips */
   8475 
   8476 #if defined(BCM_2801PM_A0)
   8477     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0r */
   8478         soc_block_list[56],
   8479         soc_portreg,
   8480         1,
   8481         0,
   8482         0x62300,
   8483         SOC_REG_FLAG_64_BITS,
   8484         0,
   8485         1,
   8486         soc_CLMAC_E2ECC_MODULE_HDR_0r_fields,
   8487         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8488         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8489         -1,
   8490         -1,
   8491     },
   8492 #endif /* chips */
   8493 
   8494 #if defined(BCM_2801PM_A0)
   8495     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1r */
   8496         soc_block_list[56],
   8497         soc_portreg,
   8498         1,
   8499         0,
   8500         0x62400,
   8501         SOC_REG_FLAG_64_BITS,
   8502         0,
   8503         1,
   8504         soc_CLMAC_E2ECC_MODULE_HDR_1r_fields,
   8505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8506         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8507         -1,
   8508         -1,
   8509     },
   8510 #endif /* chips */
   8511 
   8512 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
   8513     defined(BCM_56670_B0)
   8514     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r */
   8515         soc_block_list[16],
   8516         soc_portreg,
   8517         1,
   8518         0,
   8519         0x62300,
   8520         SOC_REG_FLAG_64_BITS,
   8521         0,
   8522         3,
   8523         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   8524         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8525         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8526         -1,
   8527         -1,
   8528     },
   8529 #endif /* chips */
   8530 
   8531 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8532     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM53570_A0r */
   8533         soc_block_list[16],
   8534         soc_portreg,
   8535         1,
   8536         0,
   8537         0x62300,
   8538         SOC_REG_FLAG_64_BITS,
   8539         0,
   8540         3,
   8541         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   8542         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8543         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8544         -1,
   8545         -1,
   8546     },
   8547 #endif /* chips */
   8548 
   8549 #if defined(BCM_56150_A0)
   8550     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56150_A0r */
   8551         soc_block_list[16],
   8552         soc_portreg,
   8553         1,
   8554         0,
   8555         0x62300,
   8556         SOC_REG_FLAG_64_BITS,
   8557         0,
   8558         3,
   8559         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM56850_A0r_fields,
   8560         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8561         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8562         -1,
   8563         -1,
   8564     },
   8565 #endif /* chips */
   8566 
   8567 #if defined(BCM_56160_A0)
   8568     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56160_A0r */
   8569         soc_block_list[16],
   8570         soc_portreg,
   8571         1,
   8572         0,
   8573         0x62400,
   8574         SOC_REG_FLAG_64_BITS,
   8575         0,
   8576         3,
   8577         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   8578         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8579         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8580         -1,
   8581         -1,
   8582     },
   8583 #endif /* chips */
   8584 
   8585 #if defined(BCM_56260_A0)
   8586     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56260_A0r */
   8587         soc_block_list[220],
   8588         soc_portreg,
   8589         1,
   8590         0,
   8591         0x62300,
   8592         SOC_REG_FLAG_64_BITS,
   8593         0,
   8594         3,
   8595         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   8596         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8597         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8598         -1,
   8599         -1,
   8600     },
   8601 #endif /* chips */
   8602 
   8603 #if defined(BCM_56260_B0)
   8604     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56260_B0r */
   8605         soc_block_list[220],
   8606         soc_portreg,
   8607         1,
   8608         0,
   8609         0x62400,
   8610         SOC_REG_FLAG_64_BITS,
   8611         0,
   8612         3,
   8613         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   8614         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8615         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8616         -1,
   8617         -1,
   8618     },
   8619 #endif /* chips */
   8620 
   8621 #if defined(BCM_56270_A0)
   8622     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56270_A0r */
   8623         soc_block_list[220],
   8624         soc_portreg,
   8625         1,
   8626         0,
   8627         0x62400,
   8628         SOC_REG_FLAG_64_BITS,
   8629         0,
   8630         3,
   8631         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   8632         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8633         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8634         -1,
   8635         -1,
   8636     },
   8637 #endif /* chips */
   8638 
   8639 #if defined(BCM_56370_A0)
   8640     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56370_A0r */
   8641         soc_block_list[16],
   8642         soc_portreg,
   8643         1,
   8644         0,
   8645         0x62400,
   8646         SOC_REG_FLAG_64_BITS,
   8647         0,
   8648         3,
   8649         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   8650         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8651         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8652         -1,
   8653         -1,
   8654         3,
   8655     },
   8656 #endif /* chips */
   8657 
   8658 #if defined(BCM_56560_A0)
   8659     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56560_A0r */
   8660         soc_block_list[16],
   8661         soc_portreg,
   8662         1,
   8663         0,
   8664         0x62300,
   8665         SOC_REG_FLAG_64_BITS,
   8666         0,
   8667         3,
   8668         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   8669         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8670         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8671         -1,
   8672         -1,
   8673     },
   8674 #endif /* chips */
   8675 
   8676 #if defined(BCM_56560_B0)
   8677     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56560_B0r */
   8678         soc_block_list[16],
   8679         soc_portreg,
   8680         1,
   8681         0,
   8682         0x62400,
   8683         SOC_REG_FLAG_64_BITS,
   8684         0,
   8685         3,
   8686         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   8687         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8688         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8689         -1,
   8690         -1,
   8691     },
   8692 #endif /* chips */
   8693 
   8694 #if defined(BCM_56850_A0)
   8695     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56850_A0r */
   8696         soc_block_list[16],
   8697         soc_portreg,
   8698         1,
   8699         0,
   8700         0x62300,
   8701         SOC_REG_FLAG_64_BITS,
   8702         0,
   8703         3,
   8704         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM56850_A0r_fields,
   8705         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8706         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8707         -1,
   8708         -1,
   8709     },
   8710 #endif /* chips */
   8711 
   8712 #if defined(BCM_56860_A0)
   8713     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56860_A0r */
   8714         soc_block_list[16],
   8715         soc_portreg,
   8716         1,
   8717         0,
   8718         0x62400,
   8719         SOC_REG_FLAG_64_BITS,
   8720         0,
   8721         3,
   8722         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM56850_A0r_fields,
   8723         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8724         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8725         -1,
   8726         -1,
   8727     },
   8728 #endif /* chips */
   8729 
   8730 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   8731     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56960_A0r */
   8732         soc_block_list[16],
   8733         soc_portreg,
   8734         1,
   8735         0,
   8736         0x62300,
   8737         SOC_REG_FLAG_64_BITS,
   8738         0,
   8739         3,
   8740         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   8741         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8742         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8743         -1,
   8744         -1,
   8745         3,
   8746     },
   8747 #endif /* chips */
   8748 
   8749 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8750     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   8751     defined(BCM_56980_B0)
   8752     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM56970_A0r */
   8753         soc_block_list[16],
   8754         soc_portreg,
   8755         1,
   8756         0,
   8757         0x62400,
   8758         SOC_REG_FLAG_64_BITS,
   8759         0,
   8760         3,
   8761         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields,
   8762         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8763         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8764         -1,
   8765         -1,
   8766         3,
   8767     },
   8768 #endif /* chips */
   8769 
   8770 #if defined(BCM_88270_A0)
   8771     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM88270_A0r */
   8772         soc_block_list[221],
   8773         soc_portreg,
   8774         1,
   8775         0,
   8776         0x62400,
   8777         SOC_REG_FLAG_64_BITS,
   8778         0,
   8779         1,
   8780         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88270_A0r_fields,
   8781         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8782         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8783         -1,
   8784         -1,
   8785     },
   8786 #endif /* chips */
   8787 
   8788 #if defined(BCM_88375_A0)
   8789     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM88375_A0r */
   8790         soc_block_list[56],
   8791         soc_portreg,
   8792         1,
   8793         0,
   8794         0x62300,
   8795         SOC_REG_FLAG_64_BITS,
   8796         0,
   8797         1,
   8798         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88375_A0r_fields,
   8799         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8800         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8801         -1,
   8802         -1,
   8803     },
   8804 #endif /* chips */
   8805 
   8806 #if defined(BCM_88375_B0)
   8807     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM88375_B0r */
   8808         soc_block_list[56],
   8809         soc_portreg,
   8810         1,
   8811         0,
   8812         0x62400,
   8813         SOC_REG_FLAG_64_BITS,
   8814         0,
   8815         1,
   8816         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88375_B0r_fields,
   8817         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8818         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8819         -1,
   8820         -1,
   8821     },
   8822 #endif /* chips */
   8823 
   8824 #if defined(BCM_88470_A0)
   8825     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM88470_A0r */
   8826         soc_block_list[56],
   8827         soc_portreg,
   8828         1,
   8829         0,
   8830         0x62300,
   8831         SOC_REG_FLAG_64_BITS,
   8832         0,
   8833         1,
   8834         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88470_A0r_fields,
   8835         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8836         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8837         -1,
   8838         -1,
   8839     },
   8840 #endif /* chips */
   8841 
   8842 #if defined(BCM_88470_B0)
   8843     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM88470_B0r */
   8844         soc_block_list[56],
   8845         soc_portreg,
   8846         1,
   8847         0,
   8848         0x62400,
   8849         SOC_REG_FLAG_64_BITS,
   8850         0,
   8851         1,
   8852         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88470_B0r_fields,
   8853         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8854         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8855         -1,
   8856         -1,
   8857     },
   8858 #endif /* chips */
   8859 
   8860 #if defined(BCM_88675_A0)
   8861     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM88675_A0r */
   8862         soc_block_list[56],
   8863         soc_portreg,
   8864         1,
   8865         0,
   8866         0x62300,
   8867         SOC_REG_FLAG_64_BITS,
   8868         0,
   8869         1,
   8870         soc_XLMAC_E2ECC_MODULE_HDR_0r_fields,
   8871         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8872         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8873         -1,
   8874         -1,
   8875     },
   8876 #endif /* chips */
   8877 
   8878 #if defined(BCM_88675_B0)
   8879     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM88675_B0r */
   8880         soc_block_list[56],
   8881         soc_portreg,
   8882         1,
   8883         0,
   8884         0x62400,
   8885         SOC_REG_FLAG_64_BITS,
   8886         0,
   8887         1,
   8888         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88675_B0r_fields,
   8889         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8890         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8891         -1,
   8892         -1,
   8893     },
   8894 #endif /* chips */
   8895 
   8896 #if defined(BCM_88680_A0)
   8897     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_0_BCM88680_A0r */
   8898         soc_block_list[56],
   8899         soc_portreg,
   8900         1,
   8901         0,
   8902         0x62400,
   8903         SOC_REG_FLAG_64_BITS,
   8904         0,
   8905         1,
   8906         soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88680_A0r_fields,
   8907         SOC_RESET_VAL_DEC(0x20000000, 0xfb800ffe)
   8908         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8909         -1,
   8910         -1,
   8911     },
   8912 #endif /* chips */
   8913 
   8914 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
   8915     defined(BCM_56670_B0)
   8916     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r */
   8917         soc_block_list[16],
   8918         soc_portreg,
   8919         1,
   8920         0,
   8921         0x62400,
   8922         SOC_REG_FLAG_64_BITS,
   8923         0,
   8924         3,
   8925         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   8926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8927         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8928         -1,
   8929         -1,
   8930     },
   8931 #endif /* chips */
   8932 
   8933 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8934     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM53570_A0r */
   8935         soc_block_list[16],
   8936         soc_portreg,
   8937         1,
   8938         0,
   8939         0x62400,
   8940         SOC_REG_FLAG_64_BITS,
   8941         0,
   8942         3,
   8943         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   8944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8945         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8946         -1,
   8947         -1,
   8948     },
   8949 #endif /* chips */
   8950 
   8951 #if defined(BCM_56150_A0)
   8952     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56150_A0r */
   8953         soc_block_list[16],
   8954         soc_portreg,
   8955         1,
   8956         0,
   8957         0x62400,
   8958         SOC_REG_FLAG_64_BITS,
   8959         0,
   8960         3,
   8961         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM56850_A0r_fields,
   8962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8963         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8964         -1,
   8965         -1,
   8966     },
   8967 #endif /* chips */
   8968 
   8969 #if defined(BCM_56160_A0)
   8970     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56160_A0r */
   8971         soc_block_list[16],
   8972         soc_portreg,
   8973         1,
   8974         0,
   8975         0x62500,
   8976         SOC_REG_FLAG_64_BITS,
   8977         0,
   8978         3,
   8979         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   8980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8981         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   8982         -1,
   8983         -1,
   8984     },
   8985 #endif /* chips */
   8986 
   8987 #if defined(BCM_56260_A0)
   8988     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56260_A0r */
   8989         soc_block_list[220],
   8990         soc_portreg,
   8991         1,
   8992         0,
   8993         0x62400,
   8994         SOC_REG_FLAG_64_BITS,
   8995         0,
   8996         3,
   8997         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   8998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8999         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9000         -1,
   9001         -1,
   9002     },
   9003 #endif /* chips */
   9004 
   9005 #if defined(BCM_56260_B0)
   9006     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56260_B0r */
   9007         soc_block_list[220],
   9008         soc_portreg,
   9009         1,
   9010         0,
   9011         0x62500,
   9012         SOC_REG_FLAG_64_BITS,
   9013         0,
   9014         3,
   9015         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   9016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9017         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9018         -1,
   9019         -1,
   9020     },
   9021 #endif /* chips */
   9022 
   9023 #if defined(BCM_56270_A0)
   9024     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56270_A0r */
   9025         soc_block_list[220],
   9026         soc_portreg,
   9027         1,
   9028         0,
   9029         0x62500,
   9030         SOC_REG_FLAG_64_BITS,
   9031         0,
   9032         3,
   9033         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   9034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9035         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9036         -1,
   9037         -1,
   9038     },
   9039 #endif /* chips */
   9040 
   9041 #if defined(BCM_56370_A0)
   9042     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56370_A0r */
   9043         soc_block_list[16],
   9044         soc_portreg,
   9045         1,
   9046         0,
   9047         0x62500,
   9048         SOC_REG_FLAG_64_BITS,
   9049         0,
   9050         3,
   9051         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   9052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9053         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9054         -1,
   9055         -1,
   9056         3,
   9057     },
   9058 #endif /* chips */
   9059 
   9060 #if defined(BCM_56560_A0)
   9061     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56560_A0r */
   9062         soc_block_list[16],
   9063         soc_portreg,
   9064         1,
   9065         0,
   9066         0x62400,
   9067         SOC_REG_FLAG_64_BITS,
   9068         0,
   9069         3,
   9070         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   9071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9072         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9073         -1,
   9074         -1,
   9075     },
   9076 #endif /* chips */
   9077 
   9078 #if defined(BCM_56560_B0)
   9079     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56560_B0r */
   9080         soc_block_list[16],
   9081         soc_portreg,
   9082         1,
   9083         0,
   9084         0x62500,
   9085         SOC_REG_FLAG_64_BITS,
   9086         0,
   9087         3,
   9088         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   9089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9090         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9091         -1,
   9092         -1,
   9093     },
   9094 #endif /* chips */
   9095 
   9096 #if defined(BCM_56850_A0)
   9097     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56850_A0r */
   9098         soc_block_list[16],
   9099         soc_portreg,
   9100         1,
   9101         0,
   9102         0x62400,
   9103         SOC_REG_FLAG_64_BITS,
   9104         0,
   9105         3,
   9106         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM56850_A0r_fields,
   9107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9108         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9109         -1,
   9110         -1,
   9111     },
   9112 #endif /* chips */
   9113 
   9114 #if defined(BCM_56860_A0)
   9115     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56860_A0r */
   9116         soc_block_list[16],
   9117         soc_portreg,
   9118         1,
   9119         0,
   9120         0x62500,
   9121         SOC_REG_FLAG_64_BITS,
   9122         0,
   9123         3,
   9124         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM56850_A0r_fields,
   9125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9126         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9127         -1,
   9128         -1,
   9129     },
   9130 #endif /* chips */
   9131 
   9132 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9133     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56960_A0r */
   9134         soc_block_list[16],
   9135         soc_portreg,
   9136         1,
   9137         0,
   9138         0x62400,
   9139         SOC_REG_FLAG_64_BITS,
   9140         0,
   9141         3,
   9142         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   9143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9144         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9145         -1,
   9146         -1,
   9147         3,
   9148     },
   9149 #endif /* chips */
   9150 
   9151 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9152     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   9153     defined(BCM_56980_B0)
   9154     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM56970_A0r */
   9155         soc_block_list[16],
   9156         soc_portreg,
   9157         1,
   9158         0,
   9159         0x62500,
   9160         SOC_REG_FLAG_64_BITS,
   9161         0,
   9162         3,
   9163         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields,
   9164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9165         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9166         -1,
   9167         -1,
   9168         3,
   9169     },
   9170 #endif /* chips */
   9171 
   9172 #if defined(BCM_88270_A0)
   9173     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM88270_A0r */
   9174         soc_block_list[221],
   9175         soc_portreg,
   9176         1,
   9177         0,
   9178         0x62500,
   9179         SOC_REG_FLAG_64_BITS,
   9180         0,
   9181         1,
   9182         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88270_A0r_fields,
   9183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9184         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9185         -1,
   9186         -1,
   9187     },
   9188 #endif /* chips */
   9189 
   9190 #if defined(BCM_88375_A0)
   9191     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM88375_A0r */
   9192         soc_block_list[56],
   9193         soc_portreg,
   9194         1,
   9195         0,
   9196         0x62400,
   9197         SOC_REG_FLAG_64_BITS,
   9198         0,
   9199         1,
   9200         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88375_A0r_fields,
   9201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9202         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9203         -1,
   9204         -1,
   9205     },
   9206 #endif /* chips */
   9207 
   9208 #if defined(BCM_88375_B0)
   9209     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM88375_B0r */
   9210         soc_block_list[56],
   9211         soc_portreg,
   9212         1,
   9213         0,
   9214         0x62500,
   9215         SOC_REG_FLAG_64_BITS,
   9216         0,
   9217         1,
   9218         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88375_B0r_fields,
   9219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9220         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9221         -1,
   9222         -1,
   9223     },
   9224 #endif /* chips */
   9225 
   9226 #if defined(BCM_88470_A0)
   9227     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM88470_A0r */
   9228         soc_block_list[56],
   9229         soc_portreg,
   9230         1,
   9231         0,
   9232         0x62400,
   9233         SOC_REG_FLAG_64_BITS,
   9234         0,
   9235         1,
   9236         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88470_A0r_fields,
   9237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9238         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9239         -1,
   9240         -1,
   9241     },
   9242 #endif /* chips */
   9243 
   9244 #if defined(BCM_88470_B0)
   9245     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM88470_B0r */
   9246         soc_block_list[56],
   9247         soc_portreg,
   9248         1,
   9249         0,
   9250         0x62500,
   9251         SOC_REG_FLAG_64_BITS,
   9252         0,
   9253         1,
   9254         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88470_B0r_fields,
   9255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9256         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9257         -1,
   9258         -1,
   9259     },
   9260 #endif /* chips */
   9261 
   9262 #if defined(BCM_88675_A0)
   9263     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM88675_A0r */
   9264         soc_block_list[56],
   9265         soc_portreg,
   9266         1,
   9267         0,
   9268         0x62400,
   9269         SOC_REG_FLAG_64_BITS,
   9270         0,
   9271         1,
   9272         soc_XLMAC_E2ECC_MODULE_HDR_1r_fields,
   9273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9274         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9275         -1,
   9276         -1,
   9277     },
   9278 #endif /* chips */
   9279 
   9280 #if defined(BCM_88675_B0)
   9281     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM88675_B0r */
   9282         soc_block_list[56],
   9283         soc_portreg,
   9284         1,
   9285         0,
   9286         0x62500,
   9287         SOC_REG_FLAG_64_BITS,
   9288         0,
   9289         1,
   9290         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88675_B0r_fields,
   9291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9292         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9293         -1,
   9294         -1,
   9295     },
   9296 #endif /* chips */
   9297 
   9298 #if defined(BCM_88680_A0)
   9299     { /* SOC_REG_INT_XLMAC_E2ECC_MODULE_HDR_1_BCM88680_A0r */
   9300         soc_block_list[56],
   9301         soc_portreg,
   9302         1,
   9303         0,
   9304         0x62500,
   9305         SOC_REG_FLAG_64_BITS,
   9306         0,
   9307         1,
   9308         soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88680_A0r_fields,
   9309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9310         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9311         -1,
   9312         -1,
   9313     },
   9314 #endif /* chips */
   9315 
   9316 #if defined(BCM_2801PM_A0)
   9317     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0r */
   9318         soc_block_list[56],
   9319         soc_portreg,
   9320         1,
   9321         0,
   9322         0x62900,
   9323         SOC_REG_FLAG_64_BITS,
   9324         0,
   9325         1,
   9326         soc_CLMAC_E2EFC_DATA_HDR_0r_fields,
   9327         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9328         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9329         -1,
   9330         -1,
   9331     },
   9332 #endif /* chips */
   9333 
   9334 #if defined(BCM_2801PM_A0)
   9335     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1r */
   9336         soc_block_list[56],
   9337         soc_portreg,
   9338         1,
   9339         0,
   9340         0x62a00,
   9341         SOC_REG_FLAG_64_BITS,
   9342         0,
   9343         1,
   9344         soc_CLMAC_E2EFC_DATA_HDR_1r_fields,
   9345         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9346         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9347         -1,
   9348         -1,
   9349     },
   9350 #endif /* chips */
   9351 
   9352 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
   9353     defined(BCM_56670_B0)
   9354     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r */
   9355         soc_block_list[16],
   9356         soc_portreg,
   9357         1,
   9358         0,
   9359         0x62900,
   9360         SOC_REG_FLAG_64_BITS,
   9361         0,
   9362         3,
   9363         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   9364         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9365         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9366         -1,
   9367         -1,
   9368     },
   9369 #endif /* chips */
   9370 
   9371 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   9372     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM53570_A0r */
   9373         soc_block_list[16],
   9374         soc_portreg,
   9375         1,
   9376         0,
   9377         0x62900,
   9378         SOC_REG_FLAG_64_BITS,
   9379         0,
   9380         3,
   9381         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   9382         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9383         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9384         -1,
   9385         -1,
   9386     },
   9387 #endif /* chips */
   9388 
   9389 #if defined(BCM_56150_A0)
   9390     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM56150_A0r */
   9391         soc_block_list[16],
   9392         soc_portreg,
   9393         1,
   9394         0,
   9395         0x62900,
   9396         SOC_REG_FLAG_64_BITS,
   9397         0,
   9398         3,
   9399         soc_XLMAC_E2EFC_DATA_HDR_0_BCM56150_A0r_fields,
   9400         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9401         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9402         -1,
   9403         -1,
   9404     },
   9405 #endif /* chips */
   9406 
   9407 #if defined(BCM_56160_A0)
   9408     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM56160_A0r */
   9409         soc_block_list[16],
   9410         soc_portreg,
   9411         1,
   9412         0,
   9413         0x62a00,
   9414         SOC_REG_FLAG_64_BITS,
   9415         0,
   9416         3,
   9417         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   9418         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9419         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9420         -1,
   9421         -1,
   9422     },
   9423 #endif /* chips */
   9424 
   9425 #if defined(BCM_56260_A0)
   9426     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM56260_A0r */
   9427         soc_block_list[220],
   9428         soc_portreg,
   9429         1,
   9430         0,
   9431         0x62900,
   9432         SOC_REG_FLAG_64_BITS,
   9433         0,
   9434         3,
   9435         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   9436         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9437         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9438         -1,
   9439         -1,
   9440     },
   9441 #endif /* chips */
   9442 
   9443 #if defined(BCM_56260_B0)
   9444     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM56260_B0r */
   9445         soc_block_list[220],
   9446         soc_portreg,
   9447         1,
   9448         0,
   9449         0x62a00,
   9450         SOC_REG_FLAG_64_BITS,
   9451         0,
   9452         3,
   9453         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   9454         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9455         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9456         -1,
   9457         -1,
   9458     },
   9459 #endif /* chips */
   9460 
   9461 #if defined(BCM_56270_A0)
   9462     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM56270_A0r */
   9463         soc_block_list[220],
   9464         soc_portreg,
   9465         1,
   9466         0,
   9467         0x62a00,
   9468         SOC_REG_FLAG_64_BITS,
   9469         0,
   9470         3,
   9471         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   9472         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9473         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9474         -1,
   9475         -1,
   9476     },
   9477 #endif /* chips */
   9478 
   9479 #if defined(BCM_56370_A0)
   9480     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM56370_A0r */
   9481         soc_block_list[16],
   9482         soc_portreg,
   9483         1,
   9484         0,
   9485         0x62a00,
   9486         SOC_REG_FLAG_64_BITS,
   9487         0,
   9488         3,
   9489         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   9490         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9491         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9492         -1,
   9493         -1,
   9494         3,
   9495     },
   9496 #endif /* chips */
   9497 
   9498 #if defined(BCM_56560_A0)
   9499     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM56560_A0r */
   9500         soc_block_list[16],
   9501         soc_portreg,
   9502         1,
   9503         0,
   9504         0x62900,
   9505         SOC_REG_FLAG_64_BITS,
   9506         0,
   9507         3,
   9508         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   9509         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9510         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9511         -1,
   9512         -1,
   9513     },
   9514 #endif /* chips */
   9515 
   9516 #if defined(BCM_56560_B0)
   9517     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM56560_B0r */
   9518         soc_block_list[16],
   9519         soc_portreg,
   9520         1,
   9521         0,
   9522         0x62a00,
   9523         SOC_REG_FLAG_64_BITS,
   9524         0,
   9525         3,
   9526         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   9527         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9528         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9529         -1,
   9530         -1,
   9531     },
   9532 #endif /* chips */
   9533 
   9534 #if defined(BCM_56860_A0)
   9535     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM56860_A0r */
   9536         soc_block_list[16],
   9537         soc_portreg,
   9538         1,
   9539         0,
   9540         0x62a00,
   9541         SOC_REG_FLAG_64_BITS,
   9542         0,
   9543         3,
   9544         soc_XLMAC_E2EFC_DATA_HDR_0_BCM56150_A0r_fields,
   9545         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9546         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9547         -1,
   9548         -1,
   9549     },
   9550 #endif /* chips */
   9551 
   9552 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9553     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM56960_A0r */
   9554         soc_block_list[16],
   9555         soc_portreg,
   9556         1,
   9557         0,
   9558         0x62900,
   9559         SOC_REG_FLAG_64_BITS,
   9560         0,
   9561         3,
   9562         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   9563         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9564         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9565         -1,
   9566         -1,
   9567         3,
   9568     },
   9569 #endif /* chips */
   9570 
   9571 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9572     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   9573     defined(BCM_56980_B0)
   9574     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM56970_A0r */
   9575         soc_block_list[16],
   9576         soc_portreg,
   9577         1,
   9578         0,
   9579         0x62a00,
   9580         SOC_REG_FLAG_64_BITS,
   9581         0,
   9582         3,
   9583         soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields,
   9584         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9585         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9586         -1,
   9587         -1,
   9588         3,
   9589     },
   9590 #endif /* chips */
   9591 
   9592 #if defined(BCM_88270_A0)
   9593     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM88270_A0r */
   9594         soc_block_list[221],
   9595         soc_portreg,
   9596         1,
   9597         0,
   9598         0x62a00,
   9599         SOC_REG_FLAG_64_BITS,
   9600         0,
   9601         1,
   9602         soc_XLMAC_E2EFC_DATA_HDR_0_BCM88270_A0r_fields,
   9603         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9604         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9605         -1,
   9606         -1,
   9607     },
   9608 #endif /* chips */
   9609 
   9610 #if defined(BCM_88375_A0)
   9611     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM88375_A0r */
   9612         soc_block_list[56],
   9613         soc_portreg,
   9614         1,
   9615         0,
   9616         0x62900,
   9617         SOC_REG_FLAG_64_BITS,
   9618         0,
   9619         1,
   9620         soc_XLMAC_E2EFC_DATA_HDR_0_BCM88375_A0r_fields,
   9621         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9622         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9623         -1,
   9624         -1,
   9625     },
   9626 #endif /* chips */
   9627 
   9628 #if defined(BCM_88375_B0)
   9629     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM88375_B0r */
   9630         soc_block_list[56],
   9631         soc_portreg,
   9632         1,
   9633         0,
   9634         0x62a00,
   9635         SOC_REG_FLAG_64_BITS,
   9636         0,
   9637         1,
   9638         soc_XLMAC_E2EFC_DATA_HDR_0_BCM88375_B0r_fields,
   9639         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9640         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9641         -1,
   9642         -1,
   9643     },
   9644 #endif /* chips */
   9645 
   9646 #if defined(BCM_88470_A0)
   9647     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM88470_A0r */
   9648         soc_block_list[56],
   9649         soc_portreg,
   9650         1,
   9651         0,
   9652         0x62900,
   9653         SOC_REG_FLAG_64_BITS,
   9654         0,
   9655         1,
   9656         soc_XLMAC_E2EFC_DATA_HDR_0_BCM88470_A0r_fields,
   9657         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9658         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9659         -1,
   9660         -1,
   9661     },
   9662 #endif /* chips */
   9663 
   9664 #if defined(BCM_88470_B0)
   9665     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM88470_B0r */
   9666         soc_block_list[56],
   9667         soc_portreg,
   9668         1,
   9669         0,
   9670         0x62a00,
   9671         SOC_REG_FLAG_64_BITS,
   9672         0,
   9673         1,
   9674         soc_XLMAC_E2EFC_DATA_HDR_0_BCM88470_B0r_fields,
   9675         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9676         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9677         -1,
   9678         -1,
   9679     },
   9680 #endif /* chips */
   9681 
   9682 #if defined(BCM_88675_A0)
   9683     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM88675_A0r */
   9684         soc_block_list[56],
   9685         soc_portreg,
   9686         1,
   9687         0,
   9688         0x62900,
   9689         SOC_REG_FLAG_64_BITS,
   9690         0,
   9691         1,
   9692         soc_XLMAC_E2EFC_DATA_HDR_0r_fields,
   9693         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9694         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9695         -1,
   9696         -1,
   9697     },
   9698 #endif /* chips */
   9699 
   9700 #if defined(BCM_88675_B0)
   9701     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM88675_B0r */
   9702         soc_block_list[56],
   9703         soc_portreg,
   9704         1,
   9705         0,
   9706         0x62a00,
   9707         SOC_REG_FLAG_64_BITS,
   9708         0,
   9709         1,
   9710         soc_XLMAC_E2EFC_DATA_HDR_0_BCM88675_B0r_fields,
   9711         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9712         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9713         -1,
   9714         -1,
   9715     },
   9716 #endif /* chips */
   9717 
   9718 #if defined(BCM_88680_A0)
   9719     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_0_BCM88680_A0r */
   9720         soc_block_list[56],
   9721         soc_portreg,
   9722         1,
   9723         0,
   9724         0x62a00,
   9725         SOC_REG_FLAG_64_BITS,
   9726         0,
   9727         1,
   9728         soc_XLMAC_E2EFC_DATA_HDR_0_BCM88680_A0r_fields,
   9729         SOC_RESET_VAL_DEC(0xffff0000, 0xffffffff)
   9730         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9731         -1,
   9732         -1,
   9733     },
   9734 #endif /* chips */
   9735 
   9736 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
   9737     defined(BCM_56670_B0)
   9738     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r */
   9739         soc_block_list[16],
   9740         soc_portreg,
   9741         1,
   9742         0,
   9743         0x62a00,
   9744         SOC_REG_FLAG_64_BITS,
   9745         0,
   9746         3,
   9747         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   9748         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9749         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9750         -1,
   9751         -1,
   9752     },
   9753 #endif /* chips */
   9754 
   9755 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   9756     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM53570_A0r */
   9757         soc_block_list[16],
   9758         soc_portreg,
   9759         1,
   9760         0,
   9761         0x62a00,
   9762         SOC_REG_FLAG_64_BITS,
   9763         0,
   9764         3,
   9765         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   9766         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9767         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9768         -1,
   9769         -1,
   9770     },
   9771 #endif /* chips */
   9772 
   9773 #if defined(BCM_56150_A0)
   9774     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM56150_A0r */
   9775         soc_block_list[16],
   9776         soc_portreg,
   9777         1,
   9778         0,
   9779         0x62a00,
   9780         SOC_REG_FLAG_64_BITS,
   9781         0,
   9782         3,
   9783         soc_XLMAC_E2EFC_DATA_HDR_1_BCM56150_A0r_fields,
   9784         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9785         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9786         -1,
   9787         -1,
   9788     },
   9789 #endif /* chips */
   9790 
   9791 #if defined(BCM_56160_A0)
   9792     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM56160_A0r */
   9793         soc_block_list[16],
   9794         soc_portreg,
   9795         1,
   9796         0,
   9797         0x62b00,
   9798         SOC_REG_FLAG_64_BITS,
   9799         0,
   9800         3,
   9801         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   9802         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9803         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9804         -1,
   9805         -1,
   9806     },
   9807 #endif /* chips */
   9808 
   9809 #if defined(BCM_56260_A0)
   9810     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM56260_A0r */
   9811         soc_block_list[220],
   9812         soc_portreg,
   9813         1,
   9814         0,
   9815         0x62a00,
   9816         SOC_REG_FLAG_64_BITS,
   9817         0,
   9818         3,
   9819         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   9820         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9821         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9822         -1,
   9823         -1,
   9824     },
   9825 #endif /* chips */
   9826 
   9827 #if defined(BCM_56260_B0)
   9828     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM56260_B0r */
   9829         soc_block_list[220],
   9830         soc_portreg,
   9831         1,
   9832         0,
   9833         0x62b00,
   9834         SOC_REG_FLAG_64_BITS,
   9835         0,
   9836         3,
   9837         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   9838         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9839         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9840         -1,
   9841         -1,
   9842     },
   9843 #endif /* chips */
   9844 
   9845 #if defined(BCM_56270_A0)
   9846     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM56270_A0r */
   9847         soc_block_list[220],
   9848         soc_portreg,
   9849         1,
   9850         0,
   9851         0x62b00,
   9852         SOC_REG_FLAG_64_BITS,
   9853         0,
   9854         3,
   9855         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   9856         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9857         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9858         -1,
   9859         -1,
   9860     },
   9861 #endif /* chips */
   9862 
   9863 #if defined(BCM_56370_A0)
   9864     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM56370_A0r */
   9865         soc_block_list[16],
   9866         soc_portreg,
   9867         1,
   9868         0,
   9869         0x62b00,
   9870         SOC_REG_FLAG_64_BITS,
   9871         0,
   9872         3,
   9873         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   9874         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9875         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9876         -1,
   9877         -1,
   9878         3,
   9879     },
   9880 #endif /* chips */
   9881 
   9882 #if defined(BCM_56560_A0)
   9883     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM56560_A0r */
   9884         soc_block_list[16],
   9885         soc_portreg,
   9886         1,
   9887         0,
   9888         0x62a00,
   9889         SOC_REG_FLAG_64_BITS,
   9890         0,
   9891         3,
   9892         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   9893         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9894         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9895         -1,
   9896         -1,
   9897     },
   9898 #endif /* chips */
   9899 
   9900 #if defined(BCM_56560_B0)
   9901     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM56560_B0r */
   9902         soc_block_list[16],
   9903         soc_portreg,
   9904         1,
   9905         0,
   9906         0x62b00,
   9907         SOC_REG_FLAG_64_BITS,
   9908         0,
   9909         3,
   9910         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   9911         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9912         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9913         -1,
   9914         -1,
   9915     },
   9916 #endif /* chips */
   9917 
   9918 #if defined(BCM_56860_A0)
   9919     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM56860_A0r */
   9920         soc_block_list[16],
   9921         soc_portreg,
   9922         1,
   9923         0,
   9924         0x62b00,
   9925         SOC_REG_FLAG_64_BITS,
   9926         0,
   9927         3,
   9928         soc_XLMAC_E2EFC_DATA_HDR_1_BCM56150_A0r_fields,
   9929         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9930         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9931         -1,
   9932         -1,
   9933     },
   9934 #endif /* chips */
   9935 
   9936 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9937     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM56960_A0r */
   9938         soc_block_list[16],
   9939         soc_portreg,
   9940         1,
   9941         0,
   9942         0x62a00,
   9943         SOC_REG_FLAG_64_BITS,
   9944         0,
   9945         3,
   9946         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   9947         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9948         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9949         -1,
   9950         -1,
   9951         3,
   9952     },
   9953 #endif /* chips */
   9954 
   9955 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9956     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   9957     defined(BCM_56980_B0)
   9958     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM56970_A0r */
   9959         soc_block_list[16],
   9960         soc_portreg,
   9961         1,
   9962         0,
   9963         0x62b00,
   9964         SOC_REG_FLAG_64_BITS,
   9965         0,
   9966         3,
   9967         soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields,
   9968         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9969         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9970         -1,
   9971         -1,
   9972         3,
   9973     },
   9974 #endif /* chips */
   9975 
   9976 #if defined(BCM_88270_A0)
   9977     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM88270_A0r */
   9978         soc_block_list[221],
   9979         soc_portreg,
   9980         1,
   9981         0,
   9982         0x62b00,
   9983         SOC_REG_FLAG_64_BITS,
   9984         0,
   9985         1,
   9986         soc_XLMAC_E2EFC_DATA_HDR_1_BCM88270_A0r_fields,
   9987         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
   9988         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9989         -1,
   9990         -1,
   9991     },
   9992 #endif /* chips */
   9993 
   9994 #if defined(BCM_88375_A0)
   9995     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM88375_A0r */
   9996         soc_block_list[56],
   9997         soc_portreg,
   9998         1,
   9999         0,
  10000         0x62a00,
  10001         SOC_REG_FLAG_64_BITS,
  10002         0,
  10003         1,
  10004         soc_XLMAC_E2EFC_DATA_HDR_1_BCM88375_A0r_fields,
  10005         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
  10006         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10007         -1,
  10008         -1,
  10009     },
  10010 #endif /* chips */
  10011 
  10012 #if defined(BCM_88375_B0)
  10013     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM88375_B0r */
  10014         soc_block_list[56],
  10015         soc_portreg,
  10016         1,
  10017         0,
  10018         0x62b00,
  10019         SOC_REG_FLAG_64_BITS,
  10020         0,
  10021         1,
  10022         soc_XLMAC_E2EFC_DATA_HDR_1_BCM88375_B0r_fields,
  10023         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
  10024         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10025         -1,
  10026         -1,
  10027     },
  10028 #endif /* chips */
  10029 
  10030 #if defined(BCM_88470_A0)
  10031     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM88470_A0r */
  10032         soc_block_list[56],
  10033         soc_portreg,
  10034         1,
  10035         0,
  10036         0x62a00,
  10037         SOC_REG_FLAG_64_BITS,
  10038         0,
  10039         1,
  10040         soc_XLMAC_E2EFC_DATA_HDR_1_BCM88470_A0r_fields,
  10041         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
  10042         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10043         -1,
  10044         -1,
  10045     },
  10046 #endif /* chips */
  10047 
  10048 #if defined(BCM_88470_B0)
  10049     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM88470_B0r */
  10050         soc_block_list[56],
  10051         soc_portreg,
  10052         1,
  10053         0,
  10054         0x62b00,
  10055         SOC_REG_FLAG_64_BITS,
  10056         0,
  10057         1,
  10058         soc_XLMAC_E2EFC_DATA_HDR_1_BCM88470_B0r_fields,
  10059         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
  10060         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10061         -1,
  10062         -1,
  10063     },
  10064 #endif /* chips */
  10065 
  10066 #if defined(BCM_88675_A0)
  10067     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM88675_A0r */
  10068         soc_block_list[56],
  10069         soc_portreg,
  10070         1,
  10071         0,
  10072         0x62a00,
  10073         SOC_REG_FLAG_64_BITS,
  10074         0,
  10075         1,
  10076         soc_XLMAC_E2EFC_DATA_HDR_1r_fields,
  10077         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
  10078         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10079         -1,
  10080         -1,
  10081     },
  10082 #endif /* chips */
  10083 
  10084 #if defined(BCM_88675_B0)
  10085     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM88675_B0r */
  10086         soc_block_list[56],
  10087         soc_portreg,
  10088         1,
  10089         0,
  10090         0x62b00,
  10091         SOC_REG_FLAG_64_BITS,
  10092         0,
  10093         1,
  10094         soc_XLMAC_E2EFC_DATA_HDR_1_BCM88675_B0r_fields,
  10095         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
  10096         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10097         -1,
  10098         -1,
  10099     },
  10100 #endif /* chips */
  10101 
  10102 #if defined(BCM_88680_A0)
  10103     { /* SOC_REG_INT_XLMAC_E2EFC_DATA_HDR_1_BCM88680_A0r */
  10104         soc_block_list[56],
  10105         soc_portreg,
  10106         1,
  10107         0,
  10108         0x62b00,
  10109         SOC_REG_FLAG_64_BITS,
  10110         0,
  10111         1,
  10112         soc_XLMAC_E2EFC_DATA_HDR_1_BCM88680_A0r_fields,
  10113         SOC_RESET_VAL_DEC(0x70000000, 0x00000001)
  10114         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10115         -1,
  10116         -1,
  10117     },
  10118 #endif /* chips */
  10119 
  10120 #if defined(BCM_2801PM_A0)
  10121     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0r */
  10122         soc_block_list[56],
  10123         soc_portreg,
  10124         1,
  10125         0,
  10126         0x62700,
  10127         SOC_REG_FLAG_64_BITS,
  10128         0,
  10129         1,
  10130         soc_CLMAC_E2EFC_MODULE_HDR_0r_fields,
  10131         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10132         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10133         -1,
  10134         -1,
  10135     },
  10136 #endif /* chips */
  10137 
  10138 #if defined(BCM_2801PM_A0)
  10139     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1r */
  10140         soc_block_list[56],
  10141         soc_portreg,
  10142         1,
  10143         0,
  10144         0x62800,
  10145         SOC_REG_FLAG_64_BITS,
  10146         0,
  10147         1,
  10148         soc_CLMAC_E2EFC_MODULE_HDR_1r_fields,
  10149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10150         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10151         -1,
  10152         -1,
  10153     },
  10154 #endif /* chips */
  10155 
  10156 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  10157     defined(BCM_56670_B0)
  10158     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r */
  10159         soc_block_list[16],
  10160         soc_portreg,
  10161         1,
  10162         0,
  10163         0x62700,
  10164         SOC_REG_FLAG_64_BITS,
  10165         0,
  10166         3,
  10167         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
  10168         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10169         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10170         -1,
  10171         -1,
  10172     },
  10173 #endif /* chips */
  10174 
  10175 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  10176     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM53570_A0r */
  10177         soc_block_list[16],
  10178         soc_portreg,
  10179         1,
  10180         0,
  10181         0x62700,
  10182         SOC_REG_FLAG_64_BITS,
  10183         0,
  10184         3,
  10185         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
  10186         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10187         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10188         -1,
  10189         -1,
  10190     },
  10191 #endif /* chips */
  10192 
  10193 #if defined(BCM_56150_A0)
  10194     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM56150_A0r */
  10195         soc_block_list[16],
  10196         soc_portreg,
  10197         1,
  10198         0,
  10199         0x62700,
  10200         SOC_REG_FLAG_64_BITS,
  10201         0,
  10202         3,
  10203         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM56150_A0r_fields,
  10204         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10205         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10206         -1,
  10207         -1,
  10208     },
  10209 #endif /* chips */
  10210 
  10211 #if defined(BCM_56160_A0)
  10212     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM56160_A0r */
  10213         soc_block_list[16],
  10214         soc_portreg,
  10215         1,
  10216         0,
  10217         0x62800,
  10218         SOC_REG_FLAG_64_BITS,
  10219         0,
  10220         3,
  10221         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
  10222         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10223         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10224         -1,
  10225         -1,
  10226     },
  10227 #endif /* chips */
  10228 
  10229 #if defined(BCM_56260_A0)
  10230     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM56260_A0r */
  10231         soc_block_list[220],
  10232         soc_portreg,
  10233         1,
  10234         0,
  10235         0x62700,
  10236         SOC_REG_FLAG_64_BITS,
  10237         0,
  10238         3,
  10239         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
  10240         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10241         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10242         -1,
  10243         -1,
  10244     },
  10245 #endif /* chips */
  10246 
  10247 #if defined(BCM_56260_B0)
  10248     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM56260_B0r */
  10249         soc_block_list[220],
  10250         soc_portreg,
  10251         1,
  10252         0,
  10253         0x62800,
  10254         SOC_REG_FLAG_64_BITS,
  10255         0,
  10256         3,
  10257         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
  10258         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10259         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10260         -1,
  10261         -1,
  10262     },
  10263 #endif /* chips */
  10264 
  10265 #if defined(BCM_56270_A0)
  10266     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM56270_A0r */
  10267         soc_block_list[220],
  10268         soc_portreg,
  10269         1,
  10270         0,
  10271         0x62800,
  10272         SOC_REG_FLAG_64_BITS,
  10273         0,
  10274         3,
  10275         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
  10276         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10277         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10278         -1,
  10279         -1,
  10280     },
  10281 #endif /* chips */
  10282 
  10283 #if defined(BCM_56370_A0)
  10284     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM56370_A0r */
  10285         soc_block_list[16],
  10286         soc_portreg,
  10287         1,
  10288         0,
  10289         0x62800,
  10290         SOC_REG_FLAG_64_BITS,
  10291         0,
  10292         3,
  10293         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
  10294         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10295         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10296         -1,
  10297         -1,
  10298         3,
  10299     },
  10300 #endif /* chips */
  10301 
  10302 #if defined(BCM_56560_A0)
  10303     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM56560_A0r */
  10304         soc_block_list[16],
  10305         soc_portreg,
  10306         1,
  10307         0,
  10308         0x62700,
  10309         SOC_REG_FLAG_64_BITS,
  10310         0,
  10311         3,
  10312         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
  10313         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10314         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10315         -1,
  10316         -1,
  10317     },
  10318 #endif /* chips */
  10319 
  10320 #if defined(BCM_56560_B0)
  10321     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM56560_B0r */
  10322         soc_block_list[16],
  10323         soc_portreg,
  10324         1,
  10325         0,
  10326         0x62800,
  10327         SOC_REG_FLAG_64_BITS,
  10328         0,
  10329         3,
  10330         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
  10331         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10332         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10333         -1,
  10334         -1,
  10335     },
  10336 #endif /* chips */
  10337 
  10338 #if defined(BCM_56860_A0)
  10339     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM56860_A0r */
  10340         soc_block_list[16],
  10341         soc_portreg,
  10342         1,
  10343         0,
  10344         0x62800,
  10345         SOC_REG_FLAG_64_BITS,
  10346         0,
  10347         3,
  10348         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM56150_A0r_fields,
  10349         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10350         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10351         -1,
  10352         -1,
  10353     },
  10354 #endif /* chips */
  10355 
  10356 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10357     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM56960_A0r */
  10358         soc_block_list[16],
  10359         soc_portreg,
  10360         1,
  10361         0,
  10362         0x62700,
  10363         SOC_REG_FLAG_64_BITS,
  10364         0,
  10365         3,
  10366         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
  10367         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10368         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10369         -1,
  10370         -1,
  10371         3,
  10372     },
  10373 #endif /* chips */
  10374 
  10375 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10376     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  10377     defined(BCM_56980_B0)
  10378     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM56970_A0r */
  10379         soc_block_list[16],
  10380         soc_portreg,
  10381         1,
  10382         0,
  10383         0x62800,
  10384         SOC_REG_FLAG_64_BITS,
  10385         0,
  10386         3,
  10387         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields,
  10388         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10389         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10390         -1,
  10391         -1,
  10392         3,
  10393     },
  10394 #endif /* chips */
  10395 
  10396 #if defined(BCM_88270_A0)
  10397     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM88270_A0r */
  10398         soc_block_list[221],
  10399         soc_portreg,
  10400         1,
  10401         0,
  10402         0x62800,
  10403         SOC_REG_FLAG_64_BITS,
  10404         0,
  10405         1,
  10406         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88270_A0r_fields,
  10407         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10408         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10409         -1,
  10410         -1,
  10411     },
  10412 #endif /* chips */
  10413 
  10414 #if defined(BCM_88375_A0)
  10415     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM88375_A0r */
  10416         soc_block_list[56],
  10417         soc_portreg,
  10418         1,
  10419         0,
  10420         0x62700,
  10421         SOC_REG_FLAG_64_BITS,
  10422         0,
  10423         1,
  10424         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88375_A0r_fields,
  10425         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10426         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10427         -1,
  10428         -1,
  10429     },
  10430 #endif /* chips */
  10431 
  10432 #if defined(BCM_88375_B0)
  10433     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM88375_B0r */
  10434         soc_block_list[56],
  10435         soc_portreg,
  10436         1,
  10437         0,
  10438         0x62800,
  10439         SOC_REG_FLAG_64_BITS,
  10440         0,
  10441         1,
  10442         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88375_B0r_fields,
  10443         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10444         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10445         -1,
  10446         -1,
  10447     },
  10448 #endif /* chips */
  10449 
  10450 #if defined(BCM_88470_A0)
  10451     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM88470_A0r */
  10452         soc_block_list[56],
  10453         soc_portreg,
  10454         1,
  10455         0,
  10456         0x62700,
  10457         SOC_REG_FLAG_64_BITS,
  10458         0,
  10459         1,
  10460         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88470_A0r_fields,
  10461         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10462         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10463         -1,
  10464         -1,
  10465     },
  10466 #endif /* chips */
  10467 
  10468 #if defined(BCM_88470_B0)
  10469     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM88470_B0r */
  10470         soc_block_list[56],
  10471         soc_portreg,
  10472         1,
  10473         0,
  10474         0x62800,
  10475         SOC_REG_FLAG_64_BITS,
  10476         0,
  10477         1,
  10478         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88470_B0r_fields,
  10479         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10480         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10481         -1,
  10482         -1,
  10483     },
  10484 #endif /* chips */
  10485 
  10486 #if defined(BCM_88675_A0)
  10487     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM88675_A0r */
  10488         soc_block_list[56],
  10489         soc_portreg,
  10490         1,
  10491         0,
  10492         0x62700,
  10493         SOC_REG_FLAG_64_BITS,
  10494         0,
  10495         1,
  10496         soc_XLMAC_E2EFC_MODULE_HDR_0r_fields,
  10497         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10498         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10499         -1,
  10500         -1,
  10501     },
  10502 #endif /* chips */
  10503 
  10504 #if defined(BCM_88675_B0)
  10505     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM88675_B0r */
  10506         soc_block_list[56],
  10507         soc_portreg,
  10508         1,
  10509         0,
  10510         0x62800,
  10511         SOC_REG_FLAG_64_BITS,
  10512         0,
  10513         1,
  10514         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88675_B0r_fields,
  10515         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10516         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10517         -1,
  10518         -1,
  10519     },
  10520 #endif /* chips */
  10521 
  10522 #if defined(BCM_88680_A0)
  10523     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_0_BCM88680_A0r */
  10524         soc_block_list[56],
  10525         soc_portreg,
  10526         1,
  10527         0,
  10528         0x62800,
  10529         SOC_REG_FLAG_64_BITS,
  10530         0,
  10531         1,
  10532         soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88680_A0r_fields,
  10533         SOC_RESET_VAL_DEC(0x10000000, 0xfb800ffe)
  10534         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10535         -1,
  10536         -1,
  10537     },
  10538 #endif /* chips */
  10539 
  10540 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  10541     defined(BCM_56670_B0)
  10542     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r */
  10543         soc_block_list[16],
  10544         soc_portreg,
  10545         1,
  10546         0,
  10547         0x62800,
  10548         SOC_REG_FLAG_64_BITS,
  10549         0,
  10550         3,
  10551         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
  10552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10553         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10554         -1,
  10555         -1,
  10556     },
  10557 #endif /* chips */
  10558 
  10559 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  10560     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM53570_A0r */
  10561         soc_block_list[16],
  10562         soc_portreg,
  10563         1,
  10564         0,
  10565         0x62800,
  10566         SOC_REG_FLAG_64_BITS,
  10567         0,
  10568         3,
  10569         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
  10570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10571         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10572         -1,
  10573         -1,
  10574     },
  10575 #endif /* chips */
  10576 
  10577 #if defined(BCM_56150_A0)
  10578     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM56150_A0r */
  10579         soc_block_list[16],
  10580         soc_portreg,
  10581         1,
  10582         0,
  10583         0x62800,
  10584         SOC_REG_FLAG_64_BITS,
  10585         0,
  10586         3,
  10587         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM56150_A0r_fields,
  10588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10589         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10590         -1,
  10591         -1,
  10592     },
  10593 #endif /* chips */
  10594 
  10595 #if defined(BCM_56160_A0)
  10596     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM56160_A0r */
  10597         soc_block_list[16],
  10598         soc_portreg,
  10599         1,
  10600         0,
  10601         0x62900,
  10602         SOC_REG_FLAG_64_BITS,
  10603         0,
  10604         3,
  10605         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
  10606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10607         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10608         -1,
  10609         -1,
  10610     },
  10611 #endif /* chips */
  10612 
  10613 #if defined(BCM_56260_A0)
  10614     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM56260_A0r */
  10615         soc_block_list[220],
  10616         soc_portreg,
  10617         1,
  10618         0,
  10619         0x62800,
  10620         SOC_REG_FLAG_64_BITS,
  10621         0,
  10622         3,
  10623         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
  10624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10625         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10626         -1,
  10627         -1,
  10628     },
  10629 #endif /* chips */
  10630 
  10631 #if defined(BCM_56260_B0)
  10632     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM56260_B0r */
  10633         soc_block_list[220],
  10634         soc_portreg,
  10635         1,
  10636         0,
  10637         0x62900,
  10638         SOC_REG_FLAG_64_BITS,
  10639         0,
  10640         3,
  10641         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
  10642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10643         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10644         -1,
  10645         -1,
  10646     },
  10647 #endif /* chips */
  10648 
  10649 #if defined(BCM_56270_A0)
  10650     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM56270_A0r */
  10651         soc_block_list[220],
  10652         soc_portreg,
  10653         1,
  10654         0,
  10655         0x62900,
  10656         SOC_REG_FLAG_64_BITS,
  10657         0,
  10658         3,
  10659         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
  10660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10661         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10662         -1,
  10663         -1,
  10664     },
  10665 #endif /* chips */
  10666 
  10667 #if defined(BCM_56370_A0)
  10668     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM56370_A0r */
  10669         soc_block_list[16],
  10670         soc_portreg,
  10671         1,
  10672         0,
  10673         0x62900,
  10674         SOC_REG_FLAG_64_BITS,
  10675         0,
  10676         3,
  10677         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
  10678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10679         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10680         -1,
  10681         -1,
  10682         3,
  10683     },
  10684 #endif /* chips */
  10685 
  10686 #if defined(BCM_56560_A0)
  10687     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM56560_A0r */
  10688         soc_block_list[16],
  10689         soc_portreg,
  10690         1,
  10691         0,
  10692         0x62800,
  10693         SOC_REG_FLAG_64_BITS,
  10694         0,
  10695         3,
  10696         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
  10697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10698         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10699         -1,
  10700         -1,
  10701     },
  10702 #endif /* chips */
  10703 
  10704 #if defined(BCM_56560_B0)
  10705     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM56560_B0r */
  10706         soc_block_list[16],
  10707         soc_portreg,
  10708         1,
  10709         0,
  10710         0x62900,
  10711         SOC_REG_FLAG_64_BITS,
  10712         0,
  10713         3,
  10714         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
  10715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10716         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10717         -1,
  10718         -1,
  10719     },
  10720 #endif /* chips */
  10721 
  10722 #if defined(BCM_56860_A0)
  10723     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM56860_A0r */
  10724         soc_block_list[16],
  10725         soc_portreg,
  10726         1,
  10727         0,
  10728         0x62900,
  10729         SOC_REG_FLAG_64_BITS,
  10730         0,
  10731         3,
  10732         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM56150_A0r_fields,
  10733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10734         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10735         -1,
  10736         -1,
  10737     },
  10738 #endif /* chips */
  10739 
  10740 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  10741     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM56960_A0r */
  10742         soc_block_list[16],
  10743         soc_portreg,
  10744         1,
  10745         0,
  10746         0x62800,
  10747         SOC_REG_FLAG_64_BITS,
  10748         0,
  10749         3,
  10750         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
  10751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10752         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10753         -1,
  10754         -1,
  10755         3,
  10756     },
  10757 #endif /* chips */
  10758 
  10759 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10760     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  10761     defined(BCM_56980_B0)
  10762     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM56970_A0r */
  10763         soc_block_list[16],
  10764         soc_portreg,
  10765         1,
  10766         0,
  10767         0x62900,
  10768         SOC_REG_FLAG_64_BITS,
  10769         0,
  10770         3,
  10771         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields,
  10772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10773         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10774         -1,
  10775         -1,
  10776         3,
  10777     },
  10778 #endif /* chips */
  10779 
  10780 #if defined(BCM_88270_A0)
  10781     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM88270_A0r */
  10782         soc_block_list[221],
  10783         soc_portreg,
  10784         1,
  10785         0,
  10786         0x62900,
  10787         SOC_REG_FLAG_64_BITS,
  10788         0,
  10789         1,
  10790         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88270_A0r_fields,
  10791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10792         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10793         -1,
  10794         -1,
  10795     },
  10796 #endif /* chips */
  10797 
  10798 #if defined(BCM_88375_A0)
  10799     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM88375_A0r */
  10800         soc_block_list[56],
  10801         soc_portreg,
  10802         1,
  10803         0,
  10804         0x62800,
  10805         SOC_REG_FLAG_64_BITS,
  10806         0,
  10807         1,
  10808         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88375_A0r_fields,
  10809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10810         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10811         -1,
  10812         -1,
  10813     },
  10814 #endif /* chips */
  10815 
  10816 #if defined(BCM_88375_B0)
  10817     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM88375_B0r */
  10818         soc_block_list[56],
  10819         soc_portreg,
  10820         1,
  10821         0,
  10822         0x62900,
  10823         SOC_REG_FLAG_64_BITS,
  10824         0,
  10825         1,
  10826         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88375_B0r_fields,
  10827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10828         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10829         -1,
  10830         -1,
  10831     },
  10832 #endif /* chips */
  10833 
  10834 #if defined(BCM_88470_A0)
  10835     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM88470_A0r */
  10836         soc_block_list[56],
  10837         soc_portreg,
  10838         1,
  10839         0,
  10840         0x62800,
  10841         SOC_REG_FLAG_64_BITS,
  10842         0,
  10843         1,
  10844         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88470_A0r_fields,
  10845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10846         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10847         -1,
  10848         -1,
  10849     },
  10850 #endif /* chips */
  10851 
  10852 #if defined(BCM_88470_B0)
  10853     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM88470_B0r */
  10854         soc_block_list[56],
  10855         soc_portreg,
  10856         1,
  10857         0,
  10858         0x62900,
  10859         SOC_REG_FLAG_64_BITS,
  10860         0,
  10861         1,
  10862         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88470_B0r_fields,
  10863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10864         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10865         -1,
  10866         -1,
  10867     },
  10868 #endif /* chips */
  10869 
  10870 #if defined(BCM_88675_A0)
  10871     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM88675_A0r */
  10872         soc_block_list[56],
  10873         soc_portreg,
  10874         1,
  10875         0,
  10876         0x62800,
  10877         SOC_REG_FLAG_64_BITS,
  10878         0,
  10879         1,
  10880         soc_XLMAC_E2EFC_MODULE_HDR_1r_fields,
  10881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10882         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10883         -1,
  10884         -1,
  10885     },
  10886 #endif /* chips */
  10887 
  10888 #if defined(BCM_88675_B0)
  10889     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM88675_B0r */
  10890         soc_block_list[56],
  10891         soc_portreg,
  10892         1,
  10893         0,
  10894         0x62900,
  10895         SOC_REG_FLAG_64_BITS,
  10896         0,
  10897         1,
  10898         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88675_B0r_fields,
  10899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10900         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10901         -1,
  10902         -1,
  10903     },
  10904 #endif /* chips */
  10905 
  10906 #if defined(BCM_88680_A0)
  10907     { /* SOC_REG_INT_XLMAC_E2EFC_MODULE_HDR_1_BCM88680_A0r */
  10908         soc_block_list[56],
  10909         soc_portreg,
  10910         1,
  10911         0,
  10912         0x62900,
  10913         SOC_REG_FLAG_64_BITS,
  10914         0,
  10915         1,
  10916         soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88680_A0r_fields,
  10917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10918         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  10919         -1,
  10920         -1,
  10921     },
  10922 #endif /* chips */
  10923 
  10924 #if defined(BCM_2801PM_A0)
  10925     { /* SOC_REG_INT_XLMAC_E2E_CTRLr */
  10926         soc_block_list[56],
  10927         soc_portreg,
  10928         1,
  10929         0,
  10930         0x62200,
  10931         0,
  10932         0,
  10933         5,
  10934         soc_CLMAC_E2E_CTRLr_fields,
  10935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10936         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10937         -1,
  10938         -1,
  10939     },
  10940 #endif /* chips */
  10941 
  10942 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  10943     defined(BCM_56670_B0)
  10944     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM53400_A0r */
  10945         soc_block_list[16],
  10946         soc_portreg,
  10947         1,
  10948         0,
  10949         0x62200,
  10950         SOC_REG_FLAG_64_BITS,
  10951         0,
  10952         5,
  10953         soc_CLMAC_E2E_CTRLr_fields,
  10954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10955         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10956         -1,
  10957         -1,
  10958     },
  10959 #endif /* chips */
  10960 
  10961 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  10962     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM53570_A0r */
  10963         soc_block_list[16],
  10964         soc_portreg,
  10965         1,
  10966         0,
  10967         0x62200,
  10968         SOC_REG_FLAG_64_BITS,
  10969         0,
  10970         5,
  10971         soc_CLMAC_E2E_CTRLr_fields,
  10972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10973         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10974         -1,
  10975         -1,
  10976     },
  10977 #endif /* chips */
  10978 
  10979 #if defined(BCM_56150_A0)
  10980     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56150_A0r */
  10981         soc_block_list[16],
  10982         soc_portreg,
  10983         1,
  10984         0,
  10985         0x62200,
  10986         SOC_REG_FLAG_64_BITS,
  10987         0,
  10988         3,
  10989         soc_XLMAC_E2E_CTRL_BCM56850_A0r_fields,
  10990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10991         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  10992         -1,
  10993         -1,
  10994     },
  10995 #endif /* chips */
  10996 
  10997 #if defined(BCM_56160_A0)
  10998     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56160_A0r */
  10999         soc_block_list[16],
  11000         soc_portreg,
  11001         1,
  11002         0,
  11003         0x62300,
  11004         SOC_REG_FLAG_64_BITS,
  11005         0,
  11006         5,
  11007         soc_CLMAC_E2E_CTRLr_fields,
  11008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11009         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11010         -1,
  11011         -1,
  11012     },
  11013 #endif /* chips */
  11014 
  11015 #if defined(BCM_56260_A0)
  11016     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56260_A0r */
  11017         soc_block_list[220],
  11018         soc_portreg,
  11019         1,
  11020         0,
  11021         0x62200,
  11022         SOC_REG_FLAG_64_BITS,
  11023         0,
  11024         5,
  11025         soc_CLMAC_E2E_CTRLr_fields,
  11026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11027         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11028         -1,
  11029         -1,
  11030     },
  11031 #endif /* chips */
  11032 
  11033 #if defined(BCM_56260_B0)
  11034     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56260_B0r */
  11035         soc_block_list[220],
  11036         soc_portreg,
  11037         1,
  11038         0,
  11039         0x62300,
  11040         SOC_REG_FLAG_64_BITS,
  11041         0,
  11042         5,
  11043         soc_CLMAC_E2E_CTRLr_fields,
  11044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11045         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11046         -1,
  11047         -1,
  11048     },
  11049 #endif /* chips */
  11050 
  11051 #if defined(BCM_56270_A0)
  11052     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56270_A0r */
  11053         soc_block_list[220],
  11054         soc_portreg,
  11055         1,
  11056         0,
  11057         0x62300,
  11058         SOC_REG_FLAG_64_BITS,
  11059         0,
  11060         5,
  11061         soc_CLMAC_E2E_CTRLr_fields,
  11062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11063         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11064         -1,
  11065         -1,
  11066     },
  11067 #endif /* chips */
  11068 
  11069 #if defined(BCM_56370_A0)
  11070     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56370_A0r */
  11071         soc_block_list[16],
  11072         soc_portreg,
  11073         1,
  11074         0,
  11075         0x62300,
  11076         SOC_REG_FLAG_64_BITS,
  11077         0,
  11078         5,
  11079         soc_CLMAC_E2E_CTRLr_fields,
  11080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11081         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11082         -1,
  11083         -1,
  11084         3,
  11085     },
  11086 #endif /* chips */
  11087 
  11088 #if defined(BCM_56560_A0)
  11089     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56560_A0r */
  11090         soc_block_list[16],
  11091         soc_portreg,
  11092         1,
  11093         0,
  11094         0x62200,
  11095         SOC_REG_FLAG_64_BITS,
  11096         0,
  11097         5,
  11098         soc_CLMAC_E2E_CTRLr_fields,
  11099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11100         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11101         -1,
  11102         -1,
  11103     },
  11104 #endif /* chips */
  11105 
  11106 #if defined(BCM_56560_B0)
  11107     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56560_B0r */
  11108         soc_block_list[16],
  11109         soc_portreg,
  11110         1,
  11111         0,
  11112         0x62300,
  11113         SOC_REG_FLAG_64_BITS,
  11114         0,
  11115         5,
  11116         soc_CLMAC_E2E_CTRLr_fields,
  11117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11118         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11119         -1,
  11120         -1,
  11121     },
  11122 #endif /* chips */
  11123 
  11124 #if defined(BCM_56850_A0)
  11125     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56850_A0r */
  11126         soc_block_list[16],
  11127         soc_portreg,
  11128         1,
  11129         0,
  11130         0x62200,
  11131         SOC_REG_FLAG_64_BITS,
  11132         0,
  11133         3,
  11134         soc_XLMAC_E2E_CTRL_BCM56850_A0r_fields,
  11135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11136         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  11137         -1,
  11138         -1,
  11139     },
  11140 #endif /* chips */
  11141 
  11142 #if defined(BCM_56860_A0)
  11143     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56860_A0r */
  11144         soc_block_list[16],
  11145         soc_portreg,
  11146         1,
  11147         0,
  11148         0x62300,
  11149         SOC_REG_FLAG_64_BITS,
  11150         0,
  11151         5,
  11152         soc_CLMAC_E2E_CTRL_BCM56860_A0r_fields,
  11153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11154         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11155         -1,
  11156         -1,
  11157     },
  11158 #endif /* chips */
  11159 
  11160 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11161     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56960_A0r */
  11162         soc_block_list[16],
  11163         soc_portreg,
  11164         1,
  11165         0,
  11166         0x62200,
  11167         SOC_REG_FLAG_64_BITS,
  11168         0,
  11169         5,
  11170         soc_CLMAC_E2E_CTRLr_fields,
  11171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11172         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11173         -1,
  11174         -1,
  11175         3,
  11176     },
  11177 #endif /* chips */
  11178 
  11179 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11180     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  11181     defined(BCM_56980_B0)
  11182     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM56970_A0r */
  11183         soc_block_list[16],
  11184         soc_portreg,
  11185         1,
  11186         0,
  11187         0x62300,
  11188         SOC_REG_FLAG_64_BITS,
  11189         0,
  11190         5,
  11191         soc_CLMAC_E2E_CTRLr_fields,
  11192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11193         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11194         -1,
  11195         -1,
  11196         3,
  11197     },
  11198 #endif /* chips */
  11199 
  11200 #if defined(BCM_88270_A0)
  11201     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM88270_A0r */
  11202         soc_block_list[221],
  11203         soc_portreg,
  11204         1,
  11205         0,
  11206         0x62300,
  11207         SOC_REG_FLAG_64_BITS,
  11208         0,
  11209         5,
  11210         soc_XLMAC_E2E_CTRL_BCM88270_A0r_fields,
  11211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11212         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11213         -1,
  11214         -1,
  11215     },
  11216 #endif /* chips */
  11217 
  11218 #if defined(BCM_88375_A0)
  11219     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM88375_A0r */
  11220         soc_block_list[56],
  11221         soc_portreg,
  11222         1,
  11223         0,
  11224         0x62200,
  11225         SOC_REG_FLAG_64_BITS,
  11226         0,
  11227         5,
  11228         soc_XLMAC_E2E_CTRL_BCM88375_A0r_fields,
  11229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11230         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11231         -1,
  11232         -1,
  11233     },
  11234 #endif /* chips */
  11235 
  11236 #if defined(BCM_88375_B0)
  11237     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM88375_B0r */
  11238         soc_block_list[56],
  11239         soc_portreg,
  11240         1,
  11241         0,
  11242         0x62300,
  11243         SOC_REG_FLAG_64_BITS,
  11244         0,
  11245         5,
  11246         soc_XLMAC_E2E_CTRL_BCM88375_B0r_fields,
  11247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11248         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11249         -1,
  11250         -1,
  11251     },
  11252 #endif /* chips */
  11253 
  11254 #if defined(BCM_88470_A0)
  11255     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM88470_A0r */
  11256         soc_block_list[56],
  11257         soc_portreg,
  11258         1,
  11259         0,
  11260         0x62200,
  11261         SOC_REG_FLAG_64_BITS,
  11262         0,
  11263         5,
  11264         soc_XLMAC_E2E_CTRL_BCM88470_A0r_fields,
  11265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11266         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11267         -1,
  11268         -1,
  11269     },
  11270 #endif /* chips */
  11271 
  11272 #if defined(BCM_88470_B0)
  11273     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM88470_B0r */
  11274         soc_block_list[56],
  11275         soc_portreg,
  11276         1,
  11277         0,
  11278         0x62300,
  11279         SOC_REG_FLAG_64_BITS,
  11280         0,
  11281         5,
  11282         soc_XLMAC_E2E_CTRL_BCM88470_B0r_fields,
  11283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11284         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11285         -1,
  11286         -1,
  11287     },
  11288 #endif /* chips */
  11289 
  11290 #if defined(BCM_88675_A0)
  11291     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM88675_A0r */
  11292         soc_block_list[56],
  11293         soc_portreg,
  11294         1,
  11295         0,
  11296         0x62200,
  11297         SOC_REG_FLAG_64_BITS,
  11298         0,
  11299         5,
  11300         soc_XLMAC_E2E_CTRLr_fields,
  11301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11302         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11303         -1,
  11304         -1,
  11305     },
  11306 #endif /* chips */
  11307 
  11308 #if defined(BCM_88675_B0)
  11309     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM88675_B0r */
  11310         soc_block_list[56],
  11311         soc_portreg,
  11312         1,
  11313         0,
  11314         0x62300,
  11315         SOC_REG_FLAG_64_BITS,
  11316         0,
  11317         5,
  11318         soc_XLMAC_E2E_CTRL_BCM88675_B0r_fields,
  11319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11320         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11321         -1,
  11322         -1,
  11323     },
  11324 #endif /* chips */
  11325 
  11326 #if defined(BCM_88680_A0)
  11327     { /* SOC_REG_INT_XLMAC_E2E_CTRL_BCM88680_A0r */
  11328         soc_block_list[56],
  11329         soc_portreg,
  11330         1,
  11331         0,
  11332         0x62300,
  11333         SOC_REG_FLAG_64_BITS,
  11334         0,
  11335         5,
  11336         soc_XLMAC_E2E_CTRL_BCM88680_A0r_fields,
  11337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11338         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  11339         -1,
  11340         -1,
  11341     },
  11342 #endif /* chips */
  11343 
  11344 #if defined(BCM_2801PM_A0)
  11345     { /* SOC_REG_INT_XLMAC_ECC_CTRLr */
  11346         soc_block_list[56],
  11347         soc_portreg,
  11348         1,
  11349         0,
  11350         0x62e00,
  11351         0,
  11352         0,
  11353         2,
  11354         soc_XLMAC_ECC_CTRLr_fields,
  11355         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11356         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11357         -1,
  11358         -1,
  11359     },
  11360 #endif /* chips */
  11361 
  11362 #if defined(BCM_53400_A0)
  11363     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM53400_A0r */
  11364         soc_block_list[16],
  11365         soc_portreg,
  11366         1,
  11367         0,
  11368         0x62e00,
  11369         SOC_REG_FLAG_64_BITS,
  11370         0,
  11371         2,
  11372         soc_XLMAC_ECC_CTRLr_fields,
  11373         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11374         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11375         -1,
  11376         -1,
  11377     },
  11378 #endif /* chips */
  11379 
  11380 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  11381     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM53570_A0r */
  11382         soc_block_list[16],
  11383         soc_portreg,
  11384         1,
  11385         0,
  11386         0x62f00,
  11387         SOC_REG_FLAG_64_BITS,
  11388         0,
  11389         2,
  11390         soc_XLMAC_ECC_CTRLr_fields,
  11391         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11392         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11393         -1,
  11394         -1,
  11395     },
  11396 #endif /* chips */
  11397 
  11398 #if defined(BCM_56160_A0)
  11399     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM56160_A0r */
  11400         soc_block_list[16],
  11401         soc_portreg,
  11402         1,
  11403         0,
  11404         0x62f00,
  11405         SOC_REG_FLAG_64_BITS,
  11406         0,
  11407         2,
  11408         soc_XLMAC_ECC_CTRLr_fields,
  11409         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11410         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11411         -1,
  11412         -1,
  11413     },
  11414 #endif /* chips */
  11415 
  11416 #if defined(BCM_56260_A0)
  11417     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM56260_A0r */
  11418         soc_block_list[220],
  11419         soc_portreg,
  11420         1,
  11421         0,
  11422         0x62e00,
  11423         SOC_REG_FLAG_64_BITS,
  11424         0,
  11425         2,
  11426         soc_XLMAC_ECC_CTRLr_fields,
  11427         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11428         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11429         -1,
  11430         -1,
  11431     },
  11432 #endif /* chips */
  11433 
  11434 #if defined(BCM_56260_B0)
  11435     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM56260_B0r */
  11436         soc_block_list[220],
  11437         soc_portreg,
  11438         1,
  11439         0,
  11440         0x62f00,
  11441         SOC_REG_FLAG_64_BITS,
  11442         0,
  11443         2,
  11444         soc_XLMAC_ECC_CTRLr_fields,
  11445         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11446         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11447         -1,
  11448         -1,
  11449     },
  11450 #endif /* chips */
  11451 
  11452 #if defined(BCM_56270_A0)
  11453     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM56270_A0r */
  11454         soc_block_list[220],
  11455         soc_portreg,
  11456         1,
  11457         0,
  11458         0x62f00,
  11459         SOC_REG_FLAG_64_BITS,
  11460         0,
  11461         2,
  11462         soc_XLMAC_ECC_CTRLr_fields,
  11463         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11464         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11465         -1,
  11466         -1,
  11467     },
  11468 #endif /* chips */
  11469 
  11470 #if defined(BCM_56370_A0)
  11471     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM56370_A0r */
  11472         soc_block_list[16],
  11473         soc_portreg,
  11474         1,
  11475         0,
  11476         0x62f00,
  11477         SOC_REG_FLAG_64_BITS,
  11478         0,
  11479         2,
  11480         soc_XLMAC_ECC_CTRLr_fields,
  11481         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11482         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11483         -1,
  11484         -1,
  11485         3,
  11486     },
  11487 #endif /* chips */
  11488 
  11489 #if defined(BCM_56560_A0)
  11490     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM56560_A0r */
  11491         soc_block_list[16],
  11492         soc_portreg,
  11493         1,
  11494         0,
  11495         0x62e00,
  11496         SOC_REG_FLAG_64_BITS,
  11497         0,
  11498         2,
  11499         soc_XLMAC_ECC_CTRLr_fields,
  11500         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11501         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11502         -1,
  11503         -1,
  11504     },
  11505 #endif /* chips */
  11506 
  11507 #if defined(BCM_56560_B0)
  11508     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM56560_B0r */
  11509         soc_block_list[16],
  11510         soc_portreg,
  11511         1,
  11512         0,
  11513         0x62f00,
  11514         SOC_REG_FLAG_64_BITS,
  11515         0,
  11516         2,
  11517         soc_XLMAC_ECC_CTRLr_fields,
  11518         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11519         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11520         -1,
  11521         -1,
  11522     },
  11523 #endif /* chips */
  11524 
  11525 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  11526     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM56670_A0r */
  11527         soc_block_list[16],
  11528         soc_portreg,
  11529         1,
  11530         0,
  11531         0x62f00,
  11532         SOC_REG_FLAG_64_BITS,
  11533         0,
  11534         2,
  11535         soc_XLMAC_ECC_CTRLr_fields,
  11536         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11537         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11538         -1,
  11539         -1,
  11540     },
  11541 #endif /* chips */
  11542 
  11543 #if defined(BCM_56860_A0)
  11544     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM56860_A0r */
  11545         soc_block_list[16],
  11546         soc_portreg,
  11547         1,
  11548         0,
  11549         0x62f00,
  11550         SOC_REG_FLAG_64_BITS,
  11551         0,
  11552         2,
  11553         soc_XLMAC_ECC_CTRL_BCM56860_A0r_fields,
  11554         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11555         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11556         -1,
  11557         -1,
  11558     },
  11559 #endif /* chips */
  11560 
  11561 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11562     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM56960_A0r */
  11563         soc_block_list[16],
  11564         soc_portreg,
  11565         1,
  11566         0,
  11567         0x62e00,
  11568         SOC_REG_FLAG_64_BITS,
  11569         0,
  11570         2,
  11571         soc_XLMAC_ECC_CTRLr_fields,
  11572         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11573         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11574         -1,
  11575         -1,
  11576         3,
  11577     },
  11578 #endif /* chips */
  11579 
  11580 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11581     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  11582     defined(BCM_56980_B0)
  11583     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM56970_A0r */
  11584         soc_block_list[16],
  11585         soc_portreg,
  11586         1,
  11587         0,
  11588         0x62f00,
  11589         SOC_REG_FLAG_64_BITS,
  11590         0,
  11591         2,
  11592         soc_XLMAC_ECC_CTRLr_fields,
  11593         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11594         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11595         -1,
  11596         -1,
  11597         3,
  11598     },
  11599 #endif /* chips */
  11600 
  11601 #if defined(BCM_88270_A0)
  11602     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM88270_A0r */
  11603         soc_block_list[221],
  11604         soc_portreg,
  11605         1,
  11606         0,
  11607         0x62f00,
  11608         SOC_REG_FLAG_64_BITS,
  11609         0,
  11610         2,
  11611         soc_XLMAC_ECC_CTRL_BCM88270_A0r_fields,
  11612         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11613         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11614         -1,
  11615         -1,
  11616     },
  11617 #endif /* chips */
  11618 
  11619 #if defined(BCM_88375_A0)
  11620     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM88375_A0r */
  11621         soc_block_list[56],
  11622         soc_portreg,
  11623         1,
  11624         0,
  11625         0x62e00,
  11626         SOC_REG_FLAG_64_BITS,
  11627         0,
  11628         2,
  11629         soc_XLMAC_ECC_CTRL_BCM88375_A0r_fields,
  11630         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11631         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11632         -1,
  11633         -1,
  11634     },
  11635 #endif /* chips */
  11636 
  11637 #if defined(BCM_88375_B0)
  11638     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM88375_B0r */
  11639         soc_block_list[56],
  11640         soc_portreg,
  11641         1,
  11642         0,
  11643         0x62f00,
  11644         SOC_REG_FLAG_64_BITS,
  11645         0,
  11646         2,
  11647         soc_XLMAC_ECC_CTRL_BCM88375_B0r_fields,
  11648         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11649         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11650         -1,
  11651         -1,
  11652     },
  11653 #endif /* chips */
  11654 
  11655 #if defined(BCM_88470_A0)
  11656     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM88470_A0r */
  11657         soc_block_list[56],
  11658         soc_portreg,
  11659         1,
  11660         0,
  11661         0x62e00,
  11662         SOC_REG_FLAG_64_BITS,
  11663         0,
  11664         2,
  11665         soc_XLMAC_ECC_CTRL_BCM88470_A0r_fields,
  11666         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11667         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11668         -1,
  11669         -1,
  11670     },
  11671 #endif /* chips */
  11672 
  11673 #if defined(BCM_88470_B0)
  11674     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM88470_B0r */
  11675         soc_block_list[56],
  11676         soc_portreg,
  11677         1,
  11678         0,
  11679         0x62f00,
  11680         SOC_REG_FLAG_64_BITS,
  11681         0,
  11682         2,
  11683         soc_XLMAC_ECC_CTRL_BCM88470_B0r_fields,
  11684         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11685         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11686         -1,
  11687         -1,
  11688     },
  11689 #endif /* chips */
  11690 
  11691 #if defined(BCM_88675_A0)
  11692     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM88675_A0r */
  11693         soc_block_list[56],
  11694         soc_portreg,
  11695         1,
  11696         0,
  11697         0x62e00,
  11698         SOC_REG_FLAG_64_BITS,
  11699         0,
  11700         2,
  11701         soc_XLMAC_ECC_CTRL_BCM88675_A0r_fields,
  11702         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11703         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11704         -1,
  11705         -1,
  11706     },
  11707 #endif /* chips */
  11708 
  11709 #if defined(BCM_88675_B0)
  11710     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM88675_B0r */
  11711         soc_block_list[56],
  11712         soc_portreg,
  11713         1,
  11714         0,
  11715         0x62f00,
  11716         SOC_REG_FLAG_64_BITS,
  11717         0,
  11718         2,
  11719         soc_XLMAC_ECC_CTRL_BCM88675_B0r_fields,
  11720         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11721         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11722         -1,
  11723         -1,
  11724     },
  11725 #endif /* chips */
  11726 
  11727 #if defined(BCM_88680_A0)
  11728     { /* SOC_REG_INT_XLMAC_ECC_CTRL_BCM88680_A0r */
  11729         soc_block_list[56],
  11730         soc_portreg,
  11731         1,
  11732         0,
  11733         0x62f00,
  11734         SOC_REG_FLAG_64_BITS,
  11735         0,
  11736         2,
  11737         soc_XLMAC_ECC_CTRL_BCM88680_A0r_fields,
  11738         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  11739         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11740         -1,
  11741         -1,
  11742     },
  11743 #endif /* chips */
  11744 
  11745 #if defined(BCM_2801PM_A0)
  11746     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr */
  11747         soc_block_list[56],
  11748         soc_portreg,
  11749         1,
  11750         0,
  11751         0x62f00,
  11752         0,
  11753         0,
  11754         2,
  11755         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11757         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11758         -1,
  11759         -1,
  11760     },
  11761 #endif /* chips */
  11762 
  11763 #if defined(BCM_53400_A0)
  11764     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM53400_A0r */
  11765         soc_block_list[16],
  11766         soc_portreg,
  11767         1,
  11768         0,
  11769         0x62f00,
  11770         SOC_REG_FLAG_64_BITS,
  11771         0,
  11772         2,
  11773         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11775         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11776         -1,
  11777         -1,
  11778     },
  11779 #endif /* chips */
  11780 
  11781 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  11782     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM53570_A0r */
  11783         soc_block_list[16],
  11784         soc_portreg,
  11785         1,
  11786         0,
  11787         0x63000,
  11788         SOC_REG_FLAG_64_BITS,
  11789         0,
  11790         2,
  11791         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11793         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11794         -1,
  11795         -1,
  11796     },
  11797 #endif /* chips */
  11798 
  11799 #if defined(BCM_56160_A0)
  11800     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56160_A0r */
  11801         soc_block_list[16],
  11802         soc_portreg,
  11803         1,
  11804         0,
  11805         0x63000,
  11806         SOC_REG_FLAG_64_BITS,
  11807         0,
  11808         2,
  11809         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11811         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11812         -1,
  11813         -1,
  11814     },
  11815 #endif /* chips */
  11816 
  11817 #if defined(BCM_56260_A0)
  11818     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56260_A0r */
  11819         soc_block_list[220],
  11820         soc_portreg,
  11821         1,
  11822         0,
  11823         0x62f00,
  11824         SOC_REG_FLAG_64_BITS,
  11825         0,
  11826         2,
  11827         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11829         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11830         -1,
  11831         -1,
  11832     },
  11833 #endif /* chips */
  11834 
  11835 #if defined(BCM_56260_B0)
  11836     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56260_B0r */
  11837         soc_block_list[220],
  11838         soc_portreg,
  11839         1,
  11840         0,
  11841         0x63000,
  11842         SOC_REG_FLAG_64_BITS,
  11843         0,
  11844         2,
  11845         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11847         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11848         -1,
  11849         -1,
  11850     },
  11851 #endif /* chips */
  11852 
  11853 #if defined(BCM_56270_A0)
  11854     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56270_A0r */
  11855         soc_block_list[220],
  11856         soc_portreg,
  11857         1,
  11858         0,
  11859         0x63000,
  11860         SOC_REG_FLAG_64_BITS,
  11861         0,
  11862         2,
  11863         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11865         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11866         -1,
  11867         -1,
  11868     },
  11869 #endif /* chips */
  11870 
  11871 #if defined(BCM_56370_A0)
  11872     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56370_A0r */
  11873         soc_block_list[16],
  11874         soc_portreg,
  11875         1,
  11876         0,
  11877         0x63000,
  11878         SOC_REG_FLAG_64_BITS,
  11879         0,
  11880         2,
  11881         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11883         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11884         -1,
  11885         -1,
  11886         3,
  11887     },
  11888 #endif /* chips */
  11889 
  11890 #if defined(BCM_56560_A0)
  11891     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56560_A0r */
  11892         soc_block_list[16],
  11893         soc_portreg,
  11894         1,
  11895         0,
  11896         0x62f00,
  11897         SOC_REG_FLAG_64_BITS,
  11898         0,
  11899         2,
  11900         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11902         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11903         -1,
  11904         -1,
  11905     },
  11906 #endif /* chips */
  11907 
  11908 #if defined(BCM_56560_B0)
  11909     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56560_B0r */
  11910         soc_block_list[16],
  11911         soc_portreg,
  11912         1,
  11913         0,
  11914         0x63000,
  11915         SOC_REG_FLAG_64_BITS,
  11916         0,
  11917         2,
  11918         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11920         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11921         -1,
  11922         -1,
  11923     },
  11924 #endif /* chips */
  11925 
  11926 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  11927     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56670_A0r */
  11928         soc_block_list[16],
  11929         soc_portreg,
  11930         1,
  11931         0,
  11932         0x63000,
  11933         SOC_REG_FLAG_64_BITS,
  11934         0,
  11935         2,
  11936         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11938         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11939         -1,
  11940         -1,
  11941     },
  11942 #endif /* chips */
  11943 
  11944 #if defined(BCM_56860_A0)
  11945     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56860_A0r */
  11946         soc_block_list[16],
  11947         soc_portreg,
  11948         1,
  11949         0,
  11950         0x63000,
  11951         SOC_REG_FLAG_64_BITS,
  11952         0,
  11953         2,
  11954         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56860_A0r_fields,
  11955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11956         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11957         -1,
  11958         -1,
  11959     },
  11960 #endif /* chips */
  11961 
  11962 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11963     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56960_A0r */
  11964         soc_block_list[16],
  11965         soc_portreg,
  11966         1,
  11967         0,
  11968         0x62f00,
  11969         SOC_REG_FLAG_64_BITS,
  11970         0,
  11971         2,
  11972         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11974         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11975         -1,
  11976         -1,
  11977         3,
  11978     },
  11979 #endif /* chips */
  11980 
  11981 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11982     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  11983     defined(BCM_56980_B0)
  11984     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56970_A0r */
  11985         soc_block_list[16],
  11986         soc_portreg,
  11987         1,
  11988         0,
  11989         0x63000,
  11990         SOC_REG_FLAG_64_BITS,
  11991         0,
  11992         2,
  11993         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields,
  11994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11995         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11996         -1,
  11997         -1,
  11998         3,
  11999     },
  12000 #endif /* chips */
  12001 
  12002 #if defined(BCM_88270_A0)
  12003     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88270_A0r */
  12004         soc_block_list[221],
  12005         soc_portreg,
  12006         1,
  12007         0,
  12008         0x63000,
  12009         SOC_REG_FLAG_64_BITS,
  12010         0,
  12011         2,
  12012         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88270_A0r_fields,
  12013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12014         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12015         -1,
  12016         -1,
  12017     },
  12018 #endif /* chips */
  12019 
  12020 #if defined(BCM_88375_A0)
  12021     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88375_A0r */
  12022         soc_block_list[56],
  12023         soc_portreg,
  12024         1,
  12025         0,
  12026         0x62f00,
  12027         SOC_REG_FLAG_64_BITS,
  12028         0,
  12029         2,
  12030         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88375_A0r_fields,
  12031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12032         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12033         -1,
  12034         -1,
  12035     },
  12036 #endif /* chips */
  12037 
  12038 #if defined(BCM_88375_B0)
  12039     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88375_B0r */
  12040         soc_block_list[56],
  12041         soc_portreg,
  12042         1,
  12043         0,
  12044         0x63000,
  12045         SOC_REG_FLAG_64_BITS,
  12046         0,
  12047         2,
  12048         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88375_B0r_fields,
  12049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12050         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12051         -1,
  12052         -1,
  12053     },
  12054 #endif /* chips */
  12055 
  12056 #if defined(BCM_88470_A0)
  12057     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88470_A0r */
  12058         soc_block_list[56],
  12059         soc_portreg,
  12060         1,
  12061         0,
  12062         0x62f00,
  12063         SOC_REG_FLAG_64_BITS,
  12064         0,
  12065         2,
  12066         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88470_A0r_fields,
  12067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12068         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12069         -1,
  12070         -1,
  12071     },
  12072 #endif /* chips */
  12073 
  12074 #if defined(BCM_88470_B0)
  12075     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88470_B0r */
  12076         soc_block_list[56],
  12077         soc_portreg,
  12078         1,
  12079         0,
  12080         0x63000,
  12081         SOC_REG_FLAG_64_BITS,
  12082         0,
  12083         2,
  12084         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88470_B0r_fields,
  12085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12086         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12087         -1,
  12088         -1,
  12089     },
  12090 #endif /* chips */
  12091 
  12092 #if defined(BCM_88675_A0)
  12093     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88675_A0r */
  12094         soc_block_list[56],
  12095         soc_portreg,
  12096         1,
  12097         0,
  12098         0x62f00,
  12099         SOC_REG_FLAG_64_BITS,
  12100         0,
  12101         2,
  12102         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88675_A0r_fields,
  12103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12104         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12105         -1,
  12106         -1,
  12107     },
  12108 #endif /* chips */
  12109 
  12110 #if defined(BCM_88675_B0)
  12111     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88675_B0r */
  12112         soc_block_list[56],
  12113         soc_portreg,
  12114         1,
  12115         0,
  12116         0x63000,
  12117         SOC_REG_FLAG_64_BITS,
  12118         0,
  12119         2,
  12120         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88675_B0r_fields,
  12121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12122         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12123         -1,
  12124         -1,
  12125     },
  12126 #endif /* chips */
  12127 
  12128 #if defined(BCM_88680_A0)
  12129     { /* SOC_REG_INT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88680_A0r */
  12130         soc_block_list[56],
  12131         soc_portreg,
  12132         1,
  12133         0,
  12134         0x63000,
  12135         SOC_REG_FLAG_64_BITS,
  12136         0,
  12137         2,
  12138         soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88680_A0r_fields,
  12139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12140         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12141         -1,
  12142         -1,
  12143     },
  12144 #endif /* chips */
  12145 
  12146 #if defined(BCM_2801PM_A0)
  12147     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr */
  12148         soc_block_list[56],
  12149         soc_portreg,
  12150         1,
  12151         0,
  12152         0x63000,
  12153         0,
  12154         0,
  12155         2,
  12156         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12158         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12159         -1,
  12160         -1,
  12161     },
  12162 #endif /* chips */
  12163 
  12164 #if defined(BCM_53400_A0)
  12165     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM53400_A0r */
  12166         soc_block_list[16],
  12167         soc_portreg,
  12168         1,
  12169         0,
  12170         0x63000,
  12171         SOC_REG_FLAG_64_BITS,
  12172         0,
  12173         2,
  12174         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12176         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12177         -1,
  12178         -1,
  12179     },
  12180 #endif /* chips */
  12181 
  12182 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  12183     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM53570_A0r */
  12184         soc_block_list[16],
  12185         soc_portreg,
  12186         1,
  12187         0,
  12188         0x63100,
  12189         SOC_REG_FLAG_64_BITS,
  12190         0,
  12191         2,
  12192         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12194         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12195         -1,
  12196         -1,
  12197     },
  12198 #endif /* chips */
  12199 
  12200 #if defined(BCM_56160_A0)
  12201     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56160_A0r */
  12202         soc_block_list[16],
  12203         soc_portreg,
  12204         1,
  12205         0,
  12206         0x63100,
  12207         SOC_REG_FLAG_64_BITS,
  12208         0,
  12209         2,
  12210         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12212         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12213         -1,
  12214         -1,
  12215     },
  12216 #endif /* chips */
  12217 
  12218 #if defined(BCM_56260_A0)
  12219     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56260_A0r */
  12220         soc_block_list[220],
  12221         soc_portreg,
  12222         1,
  12223         0,
  12224         0x63000,
  12225         SOC_REG_FLAG_64_BITS,
  12226         0,
  12227         2,
  12228         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12230         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12231         -1,
  12232         -1,
  12233     },
  12234 #endif /* chips */
  12235 
  12236 #if defined(BCM_56260_B0)
  12237     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56260_B0r */
  12238         soc_block_list[220],
  12239         soc_portreg,
  12240         1,
  12241         0,
  12242         0x63100,
  12243         SOC_REG_FLAG_64_BITS,
  12244         0,
  12245         2,
  12246         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12248         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12249         -1,
  12250         -1,
  12251     },
  12252 #endif /* chips */
  12253 
  12254 #if defined(BCM_56270_A0)
  12255     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56270_A0r */
  12256         soc_block_list[220],
  12257         soc_portreg,
  12258         1,
  12259         0,
  12260         0x63100,
  12261         SOC_REG_FLAG_64_BITS,
  12262         0,
  12263         2,
  12264         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12266         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12267         -1,
  12268         -1,
  12269     },
  12270 #endif /* chips */
  12271 
  12272 #if defined(BCM_56370_A0)
  12273     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56370_A0r */
  12274         soc_block_list[16],
  12275         soc_portreg,
  12276         1,
  12277         0,
  12278         0x63100,
  12279         SOC_REG_FLAG_64_BITS,
  12280         0,
  12281         2,
  12282         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12284         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12285         -1,
  12286         -1,
  12287         3,
  12288     },
  12289 #endif /* chips */
  12290 
  12291 #if defined(BCM_56560_A0)
  12292     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56560_A0r */
  12293         soc_block_list[16],
  12294         soc_portreg,
  12295         1,
  12296         0,
  12297         0x63000,
  12298         SOC_REG_FLAG_64_BITS,
  12299         0,
  12300         2,
  12301         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12303         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12304         -1,
  12305         -1,
  12306     },
  12307 #endif /* chips */
  12308 
  12309 #if defined(BCM_56560_B0)
  12310     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56560_B0r */
  12311         soc_block_list[16],
  12312         soc_portreg,
  12313         1,
  12314         0,
  12315         0x63100,
  12316         SOC_REG_FLAG_64_BITS,
  12317         0,
  12318         2,
  12319         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12321         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12322         -1,
  12323         -1,
  12324     },
  12325 #endif /* chips */
  12326 
  12327 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  12328     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56670_A0r */
  12329         soc_block_list[16],
  12330         soc_portreg,
  12331         1,
  12332         0,
  12333         0x63100,
  12334         SOC_REG_FLAG_64_BITS,
  12335         0,
  12336         2,
  12337         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12339         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12340         -1,
  12341         -1,
  12342     },
  12343 #endif /* chips */
  12344 
  12345 #if defined(BCM_56860_A0)
  12346     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56860_A0r */
  12347         soc_block_list[16],
  12348         soc_portreg,
  12349         1,
  12350         0,
  12351         0x63100,
  12352         SOC_REG_FLAG_64_BITS,
  12353         0,
  12354         2,
  12355         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56860_A0r_fields,
  12356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12357         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12358         -1,
  12359         -1,
  12360     },
  12361 #endif /* chips */
  12362 
  12363 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12364     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56960_A0r */
  12365         soc_block_list[16],
  12366         soc_portreg,
  12367         1,
  12368         0,
  12369         0x63000,
  12370         SOC_REG_FLAG_64_BITS,
  12371         0,
  12372         2,
  12373         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12375         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12376         -1,
  12377         -1,
  12378         3,
  12379     },
  12380 #endif /* chips */
  12381 
  12382 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12383     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  12384     defined(BCM_56980_B0)
  12385     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56970_A0r */
  12386         soc_block_list[16],
  12387         soc_portreg,
  12388         1,
  12389         0,
  12390         0x63100,
  12391         SOC_REG_FLAG_64_BITS,
  12392         0,
  12393         2,
  12394         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields,
  12395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12396         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12397         -1,
  12398         -1,
  12399         3,
  12400     },
  12401 #endif /* chips */
  12402 
  12403 #if defined(BCM_88270_A0)
  12404     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88270_A0r */
  12405         soc_block_list[221],
  12406         soc_portreg,
  12407         1,
  12408         0,
  12409         0x63100,
  12410         SOC_REG_FLAG_64_BITS,
  12411         0,
  12412         2,
  12413         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88270_A0r_fields,
  12414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12415         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12416         -1,
  12417         -1,
  12418     },
  12419 #endif /* chips */
  12420 
  12421 #if defined(BCM_88375_A0)
  12422     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88375_A0r */
  12423         soc_block_list[56],
  12424         soc_portreg,
  12425         1,
  12426         0,
  12427         0x63000,
  12428         SOC_REG_FLAG_64_BITS,
  12429         0,
  12430         2,
  12431         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88375_A0r_fields,
  12432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12433         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12434         -1,
  12435         -1,
  12436     },
  12437 #endif /* chips */
  12438 
  12439 #if defined(BCM_88375_B0)
  12440     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88375_B0r */
  12441         soc_block_list[56],
  12442         soc_portreg,
  12443         1,
  12444         0,
  12445         0x63100,
  12446         SOC_REG_FLAG_64_BITS,
  12447         0,
  12448         2,
  12449         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88375_B0r_fields,
  12450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12451         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12452         -1,
  12453         -1,
  12454     },
  12455 #endif /* chips */
  12456 
  12457 #if defined(BCM_88470_A0)
  12458     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88470_A0r */
  12459         soc_block_list[56],
  12460         soc_portreg,
  12461         1,
  12462         0,
  12463         0x63000,
  12464         SOC_REG_FLAG_64_BITS,
  12465         0,
  12466         2,
  12467         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88470_A0r_fields,
  12468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12469         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12470         -1,
  12471         -1,
  12472     },
  12473 #endif /* chips */
  12474 
  12475 #if defined(BCM_88470_B0)
  12476     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88470_B0r */
  12477         soc_block_list[56],
  12478         soc_portreg,
  12479         1,
  12480         0,
  12481         0x63100,
  12482         SOC_REG_FLAG_64_BITS,
  12483         0,
  12484         2,
  12485         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88470_B0r_fields,
  12486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12487         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12488         -1,
  12489         -1,
  12490     },
  12491 #endif /* chips */
  12492 
  12493 #if defined(BCM_88675_A0)
  12494     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88675_A0r */
  12495         soc_block_list[56],
  12496         soc_portreg,
  12497         1,
  12498         0,
  12499         0x63000,
  12500         SOC_REG_FLAG_64_BITS,
  12501         0,
  12502         2,
  12503         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88675_A0r_fields,
  12504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12505         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12506         -1,
  12507         -1,
  12508     },
  12509 #endif /* chips */
  12510 
  12511 #if defined(BCM_88675_B0)
  12512     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88675_B0r */
  12513         soc_block_list[56],
  12514         soc_portreg,
  12515         1,
  12516         0,
  12517         0x63100,
  12518         SOC_REG_FLAG_64_BITS,
  12519         0,
  12520         2,
  12521         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88675_B0r_fields,
  12522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12523         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12524         -1,
  12525         -1,
  12526     },
  12527 #endif /* chips */
  12528 
  12529 #if defined(BCM_88680_A0)
  12530     { /* SOC_REG_INT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88680_A0r */
  12531         soc_block_list[56],
  12532         soc_portreg,
  12533         1,
  12534         0,
  12535         0x63100,
  12536         SOC_REG_FLAG_64_BITS,
  12537         0,
  12538         2,
  12539         soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88680_A0r_fields,
  12540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12541         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12542         -1,
  12543         -1,
  12544     },
  12545 #endif /* chips */
  12546 
  12547 #if defined(BCM_2801PM_A0)
  12548     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMERr */
  12549         soc_block_list[56],
  12550         soc_portreg,
  12551         1,
  12552         0,
  12553         0x61c00,
  12554         0,
  12555         0,
  12556         1,
  12557         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12558         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12559         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12560         -1,
  12561         -1,
  12562     },
  12563 #endif /* chips */
  12564 
  12565 #if defined(BCM_53400_A0)
  12566     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM53400_A0r */
  12567         soc_block_list[16],
  12568         soc_portreg,
  12569         1,
  12570         0,
  12571         0x61c00,
  12572         SOC_REG_FLAG_64_BITS,
  12573         0,
  12574         1,
  12575         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12576         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12577         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12578         -1,
  12579         -1,
  12580     },
  12581 #endif /* chips */
  12582 
  12583 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  12584     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM53570_A0r */
  12585         soc_block_list[16],
  12586         soc_portreg,
  12587         1,
  12588         0,
  12589         0x61b00,
  12590         SOC_REG_FLAG_64_BITS,
  12591         0,
  12592         1,
  12593         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12594         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12595         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12596         -1,
  12597         -1,
  12598     },
  12599 #endif /* chips */
  12600 
  12601 #if defined(BCM_56150_A0)
  12602     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56150_A0r */
  12603         soc_block_list[16],
  12604         soc_portreg,
  12605         1,
  12606         0,
  12607         0x61c00,
  12608         SOC_REG_FLAG_64_BITS,
  12609         0,
  12610         1,
  12611         soc_CMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12612         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12613         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12614         -1,
  12615         -1,
  12616     },
  12617 #endif /* chips */
  12618 
  12619 #if defined(BCM_56160_A0)
  12620     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56160_A0r */
  12621         soc_block_list[16],
  12622         soc_portreg,
  12623         1,
  12624         0,
  12625         0x61c00,
  12626         SOC_REG_FLAG_64_BITS,
  12627         0,
  12628         1,
  12629         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12630         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12631         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12632         -1,
  12633         -1,
  12634     },
  12635 #endif /* chips */
  12636 
  12637 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12638     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56260_A0r */
  12639         soc_block_list[220],
  12640         soc_portreg,
  12641         1,
  12642         0,
  12643         0x61c00,
  12644         SOC_REG_FLAG_64_BITS,
  12645         0,
  12646         1,
  12647         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12648         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12649         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12650         -1,
  12651         -1,
  12652     },
  12653 #endif /* chips */
  12654 
  12655 #if defined(BCM_56270_A0)
  12656     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56270_A0r */
  12657         soc_block_list[220],
  12658         soc_portreg,
  12659         1,
  12660         0,
  12661         0x61c00,
  12662         SOC_REG_FLAG_64_BITS,
  12663         0,
  12664         1,
  12665         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12666         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12667         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12668         -1,
  12669         -1,
  12670     },
  12671 #endif /* chips */
  12672 
  12673 #if defined(BCM_56370_A0)
  12674     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56370_A0r */
  12675         soc_block_list[16],
  12676         soc_portreg,
  12677         1,
  12678         0,
  12679         0x61c00,
  12680         SOC_REG_FLAG_64_BITS,
  12681         0,
  12682         1,
  12683         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12684         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12685         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12686         -1,
  12687         -1,
  12688         3,
  12689     },
  12690 #endif /* chips */
  12691 
  12692 #if defined(BCM_56560_A0)
  12693     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56560_A0r */
  12694         soc_block_list[16],
  12695         soc_portreg,
  12696         1,
  12697         0,
  12698         0x61c00,
  12699         SOC_REG_FLAG_64_BITS,
  12700         0,
  12701         1,
  12702         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12703         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12704         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12705         -1,
  12706         -1,
  12707     },
  12708 #endif /* chips */
  12709 
  12710 #if defined(BCM_56560_B0)
  12711     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56560_B0r */
  12712         soc_block_list[16],
  12713         soc_portreg,
  12714         1,
  12715         0,
  12716         0x61c00,
  12717         SOC_REG_FLAG_64_BITS,
  12718         0,
  12719         1,
  12720         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12721         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12722         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12723         -1,
  12724         -1,
  12725     },
  12726 #endif /* chips */
  12727 
  12728 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  12729     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56670_A0r */
  12730         soc_block_list[16],
  12731         soc_portreg,
  12732         1,
  12733         0,
  12734         0x61b00,
  12735         SOC_REG_FLAG_64_BITS,
  12736         0,
  12737         1,
  12738         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12739         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12740         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12741         -1,
  12742         -1,
  12743     },
  12744 #endif /* chips */
  12745 
  12746 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  12747     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56850_A0r */
  12748         soc_block_list[16],
  12749         soc_portreg,
  12750         1,
  12751         0,
  12752         0x61c00,
  12753         SOC_REG_FLAG_64_BITS,
  12754         0,
  12755         1,
  12756         soc_CMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12757         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12758         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12759         -1,
  12760         -1,
  12761     },
  12762 #endif /* chips */
  12763 
  12764 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12765     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  12766     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  12767     defined(BCM_56980_B0)
  12768     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56960_A0r */
  12769         soc_block_list[16],
  12770         soc_portreg,
  12771         1,
  12772         0,
  12773         0x61c00,
  12774         SOC_REG_FLAG_64_BITS,
  12775         0,
  12776         1,
  12777         soc_CLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12778         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12779         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12780         -1,
  12781         -1,
  12782         3,
  12783     },
  12784 #endif /* chips */
  12785 
  12786 #if defined(BCM_88270_A0)
  12787     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88270_A0r */
  12788         soc_block_list[221],
  12789         soc_portreg,
  12790         1,
  12791         0,
  12792         0x61c00,
  12793         SOC_REG_FLAG_64_BITS,
  12794         0,
  12795         1,
  12796         soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88270_A0r_fields,
  12797         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12798         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12799         -1,
  12800         -1,
  12801     },
  12802 #endif /* chips */
  12803 
  12804 #if defined(BCM_88375_A0)
  12805     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88375_A0r */
  12806         soc_block_list[56],
  12807         soc_portreg,
  12808         1,
  12809         0,
  12810         0x61c00,
  12811         SOC_REG_FLAG_64_BITS,
  12812         0,
  12813         1,
  12814         soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88375_A0r_fields,
  12815         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12816         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12817         -1,
  12818         -1,
  12819     },
  12820 #endif /* chips */
  12821 
  12822 #if defined(BCM_88375_B0)
  12823     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88375_B0r */
  12824         soc_block_list[56],
  12825         soc_portreg,
  12826         1,
  12827         0,
  12828         0x61c00,
  12829         SOC_REG_FLAG_64_BITS,
  12830         0,
  12831         1,
  12832         soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88375_B0r_fields,
  12833         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12834         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12835         -1,
  12836         -1,
  12837     },
  12838 #endif /* chips */
  12839 
  12840 #if defined(BCM_88470_A0)
  12841     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88470_A0r */
  12842         soc_block_list[56],
  12843         soc_portreg,
  12844         1,
  12845         0,
  12846         0x61c00,
  12847         SOC_REG_FLAG_64_BITS,
  12848         0,
  12849         1,
  12850         soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88470_A0r_fields,
  12851         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12852         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12853         -1,
  12854         -1,
  12855     },
  12856 #endif /* chips */
  12857 
  12858 #if defined(BCM_88470_B0)
  12859     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88470_B0r */
  12860         soc_block_list[56],
  12861         soc_portreg,
  12862         1,
  12863         0,
  12864         0x61c00,
  12865         SOC_REG_FLAG_64_BITS,
  12866         0,
  12867         1,
  12868         soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88470_B0r_fields,
  12869         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12870         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12871         -1,
  12872         -1,
  12873     },
  12874 #endif /* chips */
  12875 
  12876 #if defined(BCM_88675_A0)
  12877     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88675_A0r */
  12878         soc_block_list[56],
  12879         soc_portreg,
  12880         1,
  12881         0,
  12882         0x61c00,
  12883         SOC_REG_FLAG_64_BITS,
  12884         0,
  12885         1,
  12886         soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  12887         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12888         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12889         -1,
  12890         -1,
  12891     },
  12892 #endif /* chips */
  12893 
  12894 #if defined(BCM_88675_B0)
  12895     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88675_B0r */
  12896         soc_block_list[56],
  12897         soc_portreg,
  12898         1,
  12899         0,
  12900         0x61c00,
  12901         SOC_REG_FLAG_64_BITS,
  12902         0,
  12903         1,
  12904         soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88675_B0r_fields,
  12905         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12906         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12907         -1,
  12908         -1,
  12909     },
  12910 #endif /* chips */
  12911 
  12912 #if defined(BCM_88680_A0)
  12913     { /* SOC_REG_INT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88680_A0r */
  12914         soc_block_list[56],
  12915         soc_portreg,
  12916         1,
  12917         0,
  12918         0x61c00,
  12919         SOC_REG_FLAG_64_BITS,
  12920         0,
  12921         1,
  12922         soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88680_A0r_fields,
  12923         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  12924         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12925         -1,
  12926         -1,
  12927     },
  12928 #endif /* chips */
  12929 
  12930 #if defined(BCM_2801PM_A0)
  12931     { /* SOC_REG_INT_XLMAC_EEE_CTRLr */
  12932         soc_block_list[56],
  12933         soc_portreg,
  12934         1,
  12935         0,
  12936         0x61a00,
  12937         0,
  12938         0,
  12939         2,
  12940         soc_CLMAC_EEE_CTRLr_fields,
  12941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12942         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12943         -1,
  12944         -1,
  12945     },
  12946 #endif /* chips */
  12947 
  12948 #if defined(BCM_53400_A0)
  12949     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM53400_A0r */
  12950         soc_block_list[16],
  12951         soc_portreg,
  12952         1,
  12953         0,
  12954         0x61a00,
  12955         SOC_REG_FLAG_64_BITS,
  12956         0,
  12957         2,
  12958         soc_CLMAC_EEE_CTRLr_fields,
  12959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12960         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12961         -1,
  12962         -1,
  12963     },
  12964 #endif /* chips */
  12965 
  12966 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  12967     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM53570_A0r */
  12968         soc_block_list[16],
  12969         soc_portreg,
  12970         1,
  12971         0,
  12972         0x61900,
  12973         SOC_REG_FLAG_64_BITS,
  12974         0,
  12975         2,
  12976         soc_CLMAC_EEE_CTRLr_fields,
  12977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12978         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12979         -1,
  12980         -1,
  12981     },
  12982 #endif /* chips */
  12983 
  12984 #if defined(BCM_56150_A0)
  12985     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM56150_A0r */
  12986         soc_block_list[16],
  12987         soc_portreg,
  12988         1,
  12989         0,
  12990         0x61a00,
  12991         SOC_REG_FLAG_64_BITS,
  12992         0,
  12993         2,
  12994         soc_XLMAC_EEE_CTRL_BCM56850_A0r_fields,
  12995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12996         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12997         -1,
  12998         -1,
  12999     },
  13000 #endif /* chips */
  13001 
  13002 #if defined(BCM_56160_A0)
  13003     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM56160_A0r */
  13004         soc_block_list[16],
  13005         soc_portreg,
  13006         1,
  13007         0,
  13008         0x61a00,
  13009         SOC_REG_FLAG_64_BITS,
  13010         0,
  13011         2,
  13012         soc_CLMAC_EEE_CTRLr_fields,
  13013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13014         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13015         -1,
  13016         -1,
  13017     },
  13018 #endif /* chips */
  13019 
  13020 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13021     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM56260_A0r */
  13022         soc_block_list[220],
  13023         soc_portreg,
  13024         1,
  13025         0,
  13026         0x61a00,
  13027         SOC_REG_FLAG_64_BITS,
  13028         0,
  13029         2,
  13030         soc_CLMAC_EEE_CTRLr_fields,
  13031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13032         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13033         -1,
  13034         -1,
  13035     },
  13036 #endif /* chips */
  13037 
  13038 #if defined(BCM_56270_A0)
  13039     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM56270_A0r */
  13040         soc_block_list[220],
  13041         soc_portreg,
  13042         1,
  13043         0,
  13044         0x61a00,
  13045         SOC_REG_FLAG_64_BITS,
  13046         0,
  13047         2,
  13048         soc_CLMAC_EEE_CTRLr_fields,
  13049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13050         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13051         -1,
  13052         -1,
  13053     },
  13054 #endif /* chips */
  13055 
  13056 #if defined(BCM_56370_A0)
  13057     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM56370_A0r */
  13058         soc_block_list[16],
  13059         soc_portreg,
  13060         1,
  13061         0,
  13062         0x61a00,
  13063         SOC_REG_FLAG_64_BITS,
  13064         0,
  13065         2,
  13066         soc_CLMAC_EEE_CTRLr_fields,
  13067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13068         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13069         -1,
  13070         -1,
  13071         3,
  13072     },
  13073 #endif /* chips */
  13074 
  13075 #if defined(BCM_56560_A0)
  13076     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM56560_A0r */
  13077         soc_block_list[16],
  13078         soc_portreg,
  13079         1,
  13080         0,
  13081         0x61a00,
  13082         SOC_REG_FLAG_64_BITS,
  13083         0,
  13084         2,
  13085         soc_CLMAC_EEE_CTRLr_fields,
  13086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13087         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13088         -1,
  13089         -1,
  13090     },
  13091 #endif /* chips */
  13092 
  13093 #if defined(BCM_56560_B0)
  13094     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM56560_B0r */
  13095         soc_block_list[16],
  13096         soc_portreg,
  13097         1,
  13098         0,
  13099         0x61a00,
  13100         SOC_REG_FLAG_64_BITS,
  13101         0,
  13102         2,
  13103         soc_CLMAC_EEE_CTRLr_fields,
  13104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13105         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13106         -1,
  13107         -1,
  13108     },
  13109 #endif /* chips */
  13110 
  13111 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13112     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM56670_A0r */
  13113         soc_block_list[16],
  13114         soc_portreg,
  13115         1,
  13116         0,
  13117         0x61900,
  13118         SOC_REG_FLAG_64_BITS,
  13119         0,
  13120         2,
  13121         soc_CLMAC_EEE_CTRLr_fields,
  13122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13123         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13124         -1,
  13125         -1,
  13126     },
  13127 #endif /* chips */
  13128 
  13129 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  13130     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM56850_A0r */
  13131         soc_block_list[16],
  13132         soc_portreg,
  13133         1,
  13134         0,
  13135         0x61a00,
  13136         SOC_REG_FLAG_64_BITS,
  13137         0,
  13138         2,
  13139         soc_XLMAC_EEE_CTRL_BCM56850_A0r_fields,
  13140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13141         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13142         -1,
  13143         -1,
  13144     },
  13145 #endif /* chips */
  13146 
  13147 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13148     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  13149     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  13150     defined(BCM_56980_B0)
  13151     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM56960_A0r */
  13152         soc_block_list[16],
  13153         soc_portreg,
  13154         1,
  13155         0,
  13156         0x61a00,
  13157         SOC_REG_FLAG_64_BITS,
  13158         0,
  13159         2,
  13160         soc_CLMAC_EEE_CTRLr_fields,
  13161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13162         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13163         -1,
  13164         -1,
  13165         3,
  13166     },
  13167 #endif /* chips */
  13168 
  13169 #if defined(BCM_88270_A0)
  13170     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM88270_A0r */
  13171         soc_block_list[221],
  13172         soc_portreg,
  13173         1,
  13174         0,
  13175         0x61a00,
  13176         SOC_REG_FLAG_64_BITS,
  13177         0,
  13178         2,
  13179         soc_XLMAC_EEE_CTRL_BCM88270_A0r_fields,
  13180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13181         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13182         -1,
  13183         -1,
  13184     },
  13185 #endif /* chips */
  13186 
  13187 #if defined(BCM_88375_A0)
  13188     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM88375_A0r */
  13189         soc_block_list[56],
  13190         soc_portreg,
  13191         1,
  13192         0,
  13193         0x61a00,
  13194         SOC_REG_FLAG_64_BITS,
  13195         0,
  13196         2,
  13197         soc_XLMAC_EEE_CTRL_BCM88375_A0r_fields,
  13198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13199         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13200         -1,
  13201         -1,
  13202     },
  13203 #endif /* chips */
  13204 
  13205 #if defined(BCM_88375_B0)
  13206     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM88375_B0r */
  13207         soc_block_list[56],
  13208         soc_portreg,
  13209         1,
  13210         0,
  13211         0x61a00,
  13212         SOC_REG_FLAG_64_BITS,
  13213         0,
  13214         2,
  13215         soc_XLMAC_EEE_CTRL_BCM88375_B0r_fields,
  13216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13217         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13218         -1,
  13219         -1,
  13220     },
  13221 #endif /* chips */
  13222 
  13223 #if defined(BCM_88470_A0)
  13224     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM88470_A0r */
  13225         soc_block_list[56],
  13226         soc_portreg,
  13227         1,
  13228         0,
  13229         0x61a00,
  13230         SOC_REG_FLAG_64_BITS,
  13231         0,
  13232         2,
  13233         soc_XLMAC_EEE_CTRL_BCM88470_A0r_fields,
  13234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13235         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13236         -1,
  13237         -1,
  13238     },
  13239 #endif /* chips */
  13240 
  13241 #if defined(BCM_88470_B0)
  13242     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM88470_B0r */
  13243         soc_block_list[56],
  13244         soc_portreg,
  13245         1,
  13246         0,
  13247         0x61a00,
  13248         SOC_REG_FLAG_64_BITS,
  13249         0,
  13250         2,
  13251         soc_XLMAC_EEE_CTRL_BCM88470_B0r_fields,
  13252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13253         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13254         -1,
  13255         -1,
  13256     },
  13257 #endif /* chips */
  13258 
  13259 #if defined(BCM_88675_A0)
  13260     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM88675_A0r */
  13261         soc_block_list[56],
  13262         soc_portreg,
  13263         1,
  13264         0,
  13265         0x61a00,
  13266         SOC_REG_FLAG_64_BITS,
  13267         0,
  13268         2,
  13269         soc_XLMAC_EEE_CTRLr_fields,
  13270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13271         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13272         -1,
  13273         -1,
  13274     },
  13275 #endif /* chips */
  13276 
  13277 #if defined(BCM_88675_B0)
  13278     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM88675_B0r */
  13279         soc_block_list[56],
  13280         soc_portreg,
  13281         1,
  13282         0,
  13283         0x61a00,
  13284         SOC_REG_FLAG_64_BITS,
  13285         0,
  13286         2,
  13287         soc_XLMAC_EEE_CTRL_BCM88675_B0r_fields,
  13288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13289         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13290         -1,
  13291         -1,
  13292     },
  13293 #endif /* chips */
  13294 
  13295 #if defined(BCM_88680_A0)
  13296     { /* SOC_REG_INT_XLMAC_EEE_CTRL_BCM88680_A0r */
  13297         soc_block_list[56],
  13298         soc_portreg,
  13299         1,
  13300         0,
  13301         0x61a00,
  13302         SOC_REG_FLAG_64_BITS,
  13303         0,
  13304         2,
  13305         soc_XLMAC_EEE_CTRL_BCM88680_A0r_fields,
  13306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13307         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13308         -1,
  13309         -1,
  13310     },
  13311 #endif /* chips */
  13312 
  13313 #if defined(BCM_2801PM_A0)
  13314     { /* SOC_REG_INT_XLMAC_EEE_TIMERSr */
  13315         soc_block_list[56],
  13316         soc_portreg,
  13317         1,
  13318         0,
  13319         0x61b00,
  13320         SOC_REG_FLAG_64_BITS,
  13321         0,
  13322         3,
  13323         soc_CLMAC_EEE_TIMERSr_fields,
  13324         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13325         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13326         -1,
  13327         -1,
  13328     },
  13329 #endif /* chips */
  13330 
  13331 #if defined(BCM_53400_A0)
  13332     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM53400_A0r */
  13333         soc_block_list[16],
  13334         soc_portreg,
  13335         1,
  13336         0,
  13337         0x61b00,
  13338         SOC_REG_FLAG_64_BITS,
  13339         0,
  13340         5,
  13341         soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields,
  13342         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13343         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13344         -1,
  13345         -1,
  13346     },
  13347 #endif /* chips */
  13348 
  13349 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  13350     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM53570_A0r */
  13351         soc_block_list[16],
  13352         soc_portreg,
  13353         1,
  13354         0,
  13355         0x61a00,
  13356         SOC_REG_FLAG_64_BITS,
  13357         0,
  13358         5,
  13359         soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields,
  13360         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13361         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13362         -1,
  13363         -1,
  13364     },
  13365 #endif /* chips */
  13366 
  13367 #if defined(BCM_56150_A0)
  13368     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM56150_A0r */
  13369         soc_block_list[16],
  13370         soc_portreg,
  13371         1,
  13372         0,
  13373         0x61b00,
  13374         SOC_REG_FLAG_64_BITS,
  13375         0,
  13376         5,
  13377         soc_XLMAC_EEE_TIMERS_BCM56850_A0r_fields,
  13378         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13379         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13380         -1,
  13381         -1,
  13382     },
  13383 #endif /* chips */
  13384 
  13385 #if defined(BCM_56160_A0)
  13386     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM56160_A0r */
  13387         soc_block_list[16],
  13388         soc_portreg,
  13389         1,
  13390         0,
  13391         0x61b00,
  13392         SOC_REG_FLAG_64_BITS,
  13393         0,
  13394         5,
  13395         soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields,
  13396         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13397         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13398         -1,
  13399         -1,
  13400     },
  13401 #endif /* chips */
  13402 
  13403 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13404     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM56260_A0r */
  13405         soc_block_list[220],
  13406         soc_portreg,
  13407         1,
  13408         0,
  13409         0x61b00,
  13410         SOC_REG_FLAG_64_BITS,
  13411         0,
  13412         5,
  13413         soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields,
  13414         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13415         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13416         -1,
  13417         -1,
  13418     },
  13419 #endif /* chips */
  13420 
  13421 #if defined(BCM_56270_A0)
  13422     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM56270_A0r */
  13423         soc_block_list[220],
  13424         soc_portreg,
  13425         1,
  13426         0,
  13427         0x61b00,
  13428         SOC_REG_FLAG_64_BITS,
  13429         0,
  13430         5,
  13431         soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields,
  13432         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13433         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13434         -1,
  13435         -1,
  13436     },
  13437 #endif /* chips */
  13438 
  13439 #if defined(BCM_56370_A0)
  13440     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM56370_A0r */
  13441         soc_block_list[16],
  13442         soc_portreg,
  13443         1,
  13444         0,
  13445         0x61b00,
  13446         SOC_REG_FLAG_64_BITS,
  13447         0,
  13448         5,
  13449         soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields,
  13450         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13451         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13452         -1,
  13453         -1,
  13454         3,
  13455     },
  13456 #endif /* chips */
  13457 
  13458 #if defined(BCM_56560_A0)
  13459     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM56560_A0r */
  13460         soc_block_list[16],
  13461         soc_portreg,
  13462         1,
  13463         0,
  13464         0x61b00,
  13465         SOC_REG_FLAG_64_BITS,
  13466         0,
  13467         5,
  13468         soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields,
  13469         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13470         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13471         -1,
  13472         -1,
  13473     },
  13474 #endif /* chips */
  13475 
  13476 #if defined(BCM_56560_B0)
  13477     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM56560_B0r */
  13478         soc_block_list[16],
  13479         soc_portreg,
  13480         1,
  13481         0,
  13482         0x61b00,
  13483         SOC_REG_FLAG_64_BITS,
  13484         0,
  13485         5,
  13486         soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields,
  13487         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13488         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13489         -1,
  13490         -1,
  13491     },
  13492 #endif /* chips */
  13493 
  13494 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13495     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM56670_A0r */
  13496         soc_block_list[16],
  13497         soc_portreg,
  13498         1,
  13499         0,
  13500         0x61a00,
  13501         SOC_REG_FLAG_64_BITS,
  13502         0,
  13503         5,
  13504         soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields,
  13505         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13506         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13507         -1,
  13508         -1,
  13509     },
  13510 #endif /* chips */
  13511 
  13512 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  13513     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM56850_A0r */
  13514         soc_block_list[16],
  13515         soc_portreg,
  13516         1,
  13517         0,
  13518         0x61b00,
  13519         SOC_REG_FLAG_64_BITS,
  13520         0,
  13521         5,
  13522         soc_XLMAC_EEE_TIMERS_BCM56850_A0r_fields,
  13523         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13524         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13525         -1,
  13526         -1,
  13527     },
  13528 #endif /* chips */
  13529 
  13530 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13531     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  13532     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  13533     defined(BCM_56980_B0)
  13534     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM56960_A0r */
  13535         soc_block_list[16],
  13536         soc_portreg,
  13537         1,
  13538         0,
  13539         0x61b00,
  13540         SOC_REG_FLAG_64_BITS,
  13541         0,
  13542         5,
  13543         soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields,
  13544         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13545         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13546         -1,
  13547         -1,
  13548         3,
  13549     },
  13550 #endif /* chips */
  13551 
  13552 #if defined(BCM_88270_A0)
  13553     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM88270_A0r */
  13554         soc_block_list[221],
  13555         soc_portreg,
  13556         1,
  13557         0,
  13558         0x61b00,
  13559         SOC_REG_FLAG_64_BITS,
  13560         0,
  13561         3,
  13562         soc_XLMAC_EEE_TIMERS_BCM88270_A0r_fields,
  13563         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13564         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13565         -1,
  13566         -1,
  13567     },
  13568 #endif /* chips */
  13569 
  13570 #if defined(BCM_88375_A0)
  13571     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM88375_A0r */
  13572         soc_block_list[56],
  13573         soc_portreg,
  13574         1,
  13575         0,
  13576         0x61b00,
  13577         SOC_REG_FLAG_64_BITS,
  13578         0,
  13579         3,
  13580         soc_XLMAC_EEE_TIMERS_BCM88375_A0r_fields,
  13581         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13582         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13583         -1,
  13584         -1,
  13585     },
  13586 #endif /* chips */
  13587 
  13588 #if defined(BCM_88375_B0)
  13589     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM88375_B0r */
  13590         soc_block_list[56],
  13591         soc_portreg,
  13592         1,
  13593         0,
  13594         0x61b00,
  13595         SOC_REG_FLAG_64_BITS,
  13596         0,
  13597         3,
  13598         soc_XLMAC_EEE_TIMERS_BCM88375_B0r_fields,
  13599         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13600         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13601         -1,
  13602         -1,
  13603     },
  13604 #endif /* chips */
  13605 
  13606 #if defined(BCM_88470_A0)
  13607     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM88470_A0r */
  13608         soc_block_list[56],
  13609         soc_portreg,
  13610         1,
  13611         0,
  13612         0x61b00,
  13613         SOC_REG_FLAG_64_BITS,
  13614         0,
  13615         3,
  13616         soc_XLMAC_EEE_TIMERS_BCM88470_A0r_fields,
  13617         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13618         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13619         -1,
  13620         -1,
  13621     },
  13622 #endif /* chips */
  13623 
  13624 #if defined(BCM_88470_B0)
  13625     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM88470_B0r */
  13626         soc_block_list[56],
  13627         soc_portreg,
  13628         1,
  13629         0,
  13630         0x61b00,
  13631         SOC_REG_FLAG_64_BITS,
  13632         0,
  13633         3,
  13634         soc_XLMAC_EEE_TIMERS_BCM88470_B0r_fields,
  13635         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13636         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13637         -1,
  13638         -1,
  13639     },
  13640 #endif /* chips */
  13641 
  13642 #if defined(BCM_88675_A0)
  13643     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM88675_A0r */
  13644         soc_block_list[56],
  13645         soc_portreg,
  13646         1,
  13647         0,
  13648         0x61b00,
  13649         SOC_REG_FLAG_64_BITS,
  13650         0,
  13651         3,
  13652         soc_XLMAC_EEE_TIMERSr_fields,
  13653         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13654         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13655         -1,
  13656         -1,
  13657     },
  13658 #endif /* chips */
  13659 
  13660 #if defined(BCM_88675_B0)
  13661     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM88675_B0r */
  13662         soc_block_list[56],
  13663         soc_portreg,
  13664         1,
  13665         0,
  13666         0x61b00,
  13667         SOC_REG_FLAG_64_BITS,
  13668         0,
  13669         3,
  13670         soc_XLMAC_EEE_TIMERS_BCM88675_B0r_fields,
  13671         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13672         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13673         -1,
  13674         -1,
  13675     },
  13676 #endif /* chips */
  13677 
  13678 #if defined(BCM_88680_A0)
  13679     { /* SOC_REG_INT_XLMAC_EEE_TIMERS_BCM88680_A0r */
  13680         soc_block_list[56],
  13681         soc_portreg,
  13682         1,
  13683         0,
  13684         0x61b00,
  13685         SOC_REG_FLAG_64_BITS,
  13686         0,
  13687         3,
  13688         soc_XLMAC_EEE_TIMERS_BCM88680_A0r_fields,
  13689         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  13690         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  13691         -1,
  13692         -1,
  13693     },
  13694 #endif /* chips */
  13695 
  13696 #if defined(BCM_2801PM_A0)
  13697     { /* SOC_REG_INT_XLMAC_FIFO_STATUSr */
  13698         soc_block_list[56],
  13699         soc_portreg,
  13700         1,
  13701         0,
  13702         0x61700,
  13703         SOC_REG_FLAG_RO |
  13704                           SOC_REG_FLAG_SIGNAL,
  13705         0,
  13706         9,
  13707         soc_CLMAC_FIFO_STATUSr_fields,
  13708         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13709         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13710         -1,
  13711         -1,
  13712     },
  13713 #endif /* chips */
  13714 
  13715 #if defined(BCM_53400_A0)
  13716     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM53400_A0r */
  13717         soc_block_list[16],
  13718         soc_portreg,
  13719         1,
  13720         0,
  13721         0x61700,
  13722         SOC_REG_FLAG_64_BITS |
  13723                           SOC_REG_FLAG_RO,
  13724         0,
  13725         9,
  13726         soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields,
  13727         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13728         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13729         -1,
  13730         -1,
  13731     },
  13732 #endif /* chips */
  13733 
  13734 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  13735     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM53570_A0r */
  13736         soc_block_list[16],
  13737         soc_portreg,
  13738         1,
  13739         0,
  13740         0x61600,
  13741         SOC_REG_FLAG_64_BITS |
  13742                           SOC_REG_FLAG_RO,
  13743         0,
  13744         9,
  13745         soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields,
  13746         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13747         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13748         -1,
  13749         -1,
  13750     },
  13751 #endif /* chips */
  13752 
  13753 #if defined(BCM_56150_A0)
  13754     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM56150_A0r */
  13755         soc_block_list[16],
  13756         soc_portreg,
  13757         1,
  13758         0,
  13759         0x61700,
  13760         SOC_REG_FLAG_64_BITS |
  13761                           SOC_REG_FLAG_RO,
  13762         0,
  13763         8,
  13764         soc_XLMAC_FIFO_STATUS_BCM56850_A0r_fields,
  13765         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13766         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13767         -1,
  13768         -1,
  13769     },
  13770 #endif /* chips */
  13771 
  13772 #if defined(BCM_56160_A0)
  13773     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM56160_A0r */
  13774         soc_block_list[16],
  13775         soc_portreg,
  13776         1,
  13777         0,
  13778         0x61700,
  13779         SOC_REG_FLAG_64_BITS |
  13780                           SOC_REG_FLAG_RO,
  13781         0,
  13782         9,
  13783         soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields,
  13784         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13785         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13786         -1,
  13787         -1,
  13788     },
  13789 #endif /* chips */
  13790 
  13791 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  13792     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM56260_A0r */
  13793         soc_block_list[220],
  13794         soc_portreg,
  13795         1,
  13796         0,
  13797         0x61700,
  13798         SOC_REG_FLAG_64_BITS |
  13799                           SOC_REG_FLAG_RO,
  13800         0,
  13801         9,
  13802         soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields,
  13803         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13804         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13805         -1,
  13806         -1,
  13807     },
  13808 #endif /* chips */
  13809 
  13810 #if defined(BCM_56270_A0)
  13811     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM56270_A0r */
  13812         soc_block_list[220],
  13813         soc_portreg,
  13814         1,
  13815         0,
  13816         0x61700,
  13817         SOC_REG_FLAG_64_BITS |
  13818                           SOC_REG_FLAG_RO,
  13819         0,
  13820         9,
  13821         soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields,
  13822         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13823         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13824         -1,
  13825         -1,
  13826     },
  13827 #endif /* chips */
  13828 
  13829 #if defined(BCM_56370_A0)
  13830     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM56370_A0r */
  13831         soc_block_list[16],
  13832         soc_portreg,
  13833         1,
  13834         0,
  13835         0x61700,
  13836         SOC_REG_FLAG_64_BITS |
  13837                           SOC_REG_FLAG_RO,
  13838         0,
  13839         9,
  13840         soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields,
  13841         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13842         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13843         -1,
  13844         -1,
  13845         3,
  13846     },
  13847 #endif /* chips */
  13848 
  13849 #if defined(BCM_56560_A0)
  13850     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM56560_A0r */
  13851         soc_block_list[16],
  13852         soc_portreg,
  13853         1,
  13854         0,
  13855         0x61700,
  13856         SOC_REG_FLAG_64_BITS |
  13857                           SOC_REG_FLAG_RO,
  13858         0,
  13859         9,
  13860         soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields,
  13861         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13862         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13863         -1,
  13864         -1,
  13865     },
  13866 #endif /* chips */
  13867 
  13868 #if defined(BCM_56560_B0)
  13869     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM56560_B0r */
  13870         soc_block_list[16],
  13871         soc_portreg,
  13872         1,
  13873         0,
  13874         0x61700,
  13875         SOC_REG_FLAG_64_BITS |
  13876                           SOC_REG_FLAG_RO,
  13877         0,
  13878         9,
  13879         soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields,
  13880         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13881         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13882         -1,
  13883         -1,
  13884     },
  13885 #endif /* chips */
  13886 
  13887 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13888     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM56670_A0r */
  13889         soc_block_list[16],
  13890         soc_portreg,
  13891         1,
  13892         0,
  13893         0x61600,
  13894         SOC_REG_FLAG_64_BITS |
  13895                           SOC_REG_FLAG_RO,
  13896         0,
  13897         9,
  13898         soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields,
  13899         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13900         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13901         -1,
  13902         -1,
  13903     },
  13904 #endif /* chips */
  13905 
  13906 #if defined(BCM_56850_A0)
  13907     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM56850_A0r */
  13908         soc_block_list[16],
  13909         soc_portreg,
  13910         1,
  13911         0,
  13912         0x61700,
  13913         SOC_REG_FLAG_64_BITS |
  13914                           SOC_REG_FLAG_RO,
  13915         0,
  13916         8,
  13917         soc_XLMAC_FIFO_STATUS_BCM56850_A0r_fields,
  13918         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13919         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13920         -1,
  13921         -1,
  13922     },
  13923 #endif /* chips */
  13924 
  13925 #if defined(BCM_56860_A0)
  13926     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM56860_A0r */
  13927         soc_block_list[16],
  13928         soc_portreg,
  13929         1,
  13930         0,
  13931         0x61700,
  13932         SOC_REG_FLAG_64_BITS |
  13933                           SOC_REG_FLAG_RO,
  13934         0,
  13935         9,
  13936         soc_CLMAC_FIFO_STATUS_BCM56860_A0r_fields,
  13937         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13938         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13939         -1,
  13940         -1,
  13941     },
  13942 #endif /* chips */
  13943 
  13944 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13945     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  13946     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  13947     defined(BCM_56980_B0)
  13948     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM56960_A0r */
  13949         soc_block_list[16],
  13950         soc_portreg,
  13951         1,
  13952         0,
  13953         0x61700,
  13954         SOC_REG_FLAG_64_BITS |
  13955                           SOC_REG_FLAG_RO,
  13956         0,
  13957         9,
  13958         soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields,
  13959         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13960         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13961         -1,
  13962         -1,
  13963         3,
  13964     },
  13965 #endif /* chips */
  13966 
  13967 #if defined(BCM_88270_A0)
  13968     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM88270_A0r */
  13969         soc_block_list[221],
  13970         soc_portreg,
  13971         1,
  13972         0,
  13973         0x61700,
  13974         SOC_REG_FLAG_64_BITS |
  13975                           SOC_REG_FLAG_RO |
  13976                           SOC_REG_FLAG_SIGNAL,
  13977         0,
  13978         9,
  13979         soc_XLMAC_FIFO_STATUS_BCM88270_A0r_fields,
  13980         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13981         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13982         -1,
  13983         -1,
  13984     },
  13985 #endif /* chips */
  13986 
  13987 #if defined(BCM_88375_A0)
  13988     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM88375_A0r */
  13989         soc_block_list[56],
  13990         soc_portreg,
  13991         1,
  13992         0,
  13993         0x61700,
  13994         SOC_REG_FLAG_64_BITS |
  13995                           SOC_REG_FLAG_RO |
  13996                           SOC_REG_FLAG_SIGNAL,
  13997         0,
  13998         9,
  13999         soc_XLMAC_FIFO_STATUS_BCM88375_A0r_fields,
  14000         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  14001         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  14002         -1,
  14003         -1,
  14004     },
  14005 #endif /* chips */
  14006 
  14007 #if defined(BCM_88375_B0)
  14008     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM88375_B0r */
  14009         soc_block_list[56],
  14010         soc_portreg,
  14011         1,
  14012         0,
  14013         0x61700,
  14014         SOC_REG_FLAG_64_BITS |
  14015                           SOC_REG_FLAG_RO |
  14016                           SOC_REG_FLAG_SIGNAL,
  14017         0,
  14018         9,
  14019         soc_XLMAC_FIFO_STATUS_BCM88375_B0r_fields,
  14020         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  14021         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  14022         -1,
  14023         -1,
  14024     },
  14025 #endif /* chips */
  14026 
  14027 #if defined(BCM_88470_A0)
  14028     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM88470_A0r */
  14029         soc_block_list[56],
  14030         soc_portreg,
  14031         1,
  14032         0,
  14033         0x61700,
  14034         SOC_REG_FLAG_64_BITS |
  14035                           SOC_REG_FLAG_RO |
  14036                           SOC_REG_FLAG_SIGNAL,
  14037         0,
  14038         9,
  14039         soc_XLMAC_FIFO_STATUS_BCM88470_A0r_fields,
  14040         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  14041         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  14042         -1,
  14043         -1,
  14044     },
  14045 #endif /* chips */
  14046 
  14047 #if defined(BCM_88470_B0)
  14048     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM88470_B0r */
  14049         soc_block_list[56],
  14050         soc_portreg,
  14051         1,
  14052         0,
  14053         0x61700,
  14054         SOC_REG_FLAG_64_BITS |
  14055                           SOC_REG_FLAG_RO |
  14056                           SOC_REG_FLAG_SIGNAL,
  14057         0,
  14058         9,
  14059         soc_XLMAC_FIFO_STATUS_BCM88470_B0r_fields,
  14060         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  14061         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  14062         -1,
  14063         -1,
  14064     },
  14065 #endif /* chips */
  14066 
  14067 #if defined(BCM_88675_A0)
  14068     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM88675_A0r */
  14069         soc_block_list[56],
  14070         soc_portreg,
  14071         1,
  14072         0,
  14073         0x61700,
  14074         SOC_REG_FLAG_64_BITS |
  14075                           SOC_REG_FLAG_RO |
  14076                           SOC_REG_FLAG_SIGNAL,
  14077         0,
  14078         9,
  14079         soc_XLMAC_FIFO_STATUSr_fields,
  14080         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  14081         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  14082         -1,
  14083         -1,
  14084     },
  14085 #endif /* chips */
  14086 
  14087 #if defined(BCM_88675_B0)
  14088     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM88675_B0r */
  14089         soc_block_list[56],
  14090         soc_portreg,
  14091         1,
  14092         0,
  14093         0x61700,
  14094         SOC_REG_FLAG_64_BITS |
  14095                           SOC_REG_FLAG_RO |
  14096                           SOC_REG_FLAG_SIGNAL,
  14097         0,
  14098         9,
  14099         soc_XLMAC_FIFO_STATUS_BCM88675_B0r_fields,
  14100         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  14101         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  14102         -1,
  14103         -1,
  14104     },
  14105 #endif /* chips */
  14106 
  14107 #if defined(BCM_88680_A0)
  14108     { /* SOC_REG_INT_XLMAC_FIFO_STATUS_BCM88680_A0r */
  14109         soc_block_list[56],
  14110         soc_portreg,
  14111         1,
  14112         0,
  14113         0x61700,
  14114         SOC_REG_FLAG_64_BITS |
  14115                           SOC_REG_FLAG_RO |
  14116                           SOC_REG_FLAG_SIGNAL,
  14117         0,
  14118         9,
  14119         soc_XLMAC_FIFO_STATUS_BCM88680_A0r_fields,
  14120         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  14121         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  14122         -1,
  14123         -1,
  14124     },
  14125 #endif /* chips */
  14126 
  14127 #if defined(BCM_2801PM_A0)
  14128     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRLr */
  14129         soc_block_list[56],
  14130         soc_portreg,
  14131         1,
  14132         0,
  14133         0x61f00,
  14134         0,
  14135         0,
  14136         2,
  14137         soc_CLMAC_GMII_EEE_CTRLr_fields,
  14138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14139         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14140         -1,
  14141         -1,
  14142     },
  14143 #endif /* chips */
  14144 
  14145 #if defined(BCM_53400_A0)
  14146     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM53400_A0r */
  14147         soc_block_list[16],
  14148         soc_portreg,
  14149         1,
  14150         0,
  14151         0x61f00,
  14152         SOC_REG_FLAG_64_BITS,
  14153         0,
  14154         2,
  14155         soc_CLMAC_GMII_EEE_CTRLr_fields,
  14156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14157         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14158         -1,
  14159         -1,
  14160     },
  14161 #endif /* chips */
  14162 
  14163 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  14164     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM53570_A0r */
  14165         soc_block_list[16],
  14166         soc_portreg,
  14167         1,
  14168         0,
  14169         0x61e00,
  14170         SOC_REG_FLAG_64_BITS,
  14171         0,
  14172         2,
  14173         soc_CLMAC_GMII_EEE_CTRLr_fields,
  14174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14175         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14176         -1,
  14177         -1,
  14178     },
  14179 #endif /* chips */
  14180 
  14181 #if defined(BCM_56150_A0)
  14182     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM56150_A0r */
  14183         soc_block_list[16],
  14184         soc_portreg,
  14185         1,
  14186         0,
  14187         0x61f00,
  14188         SOC_REG_FLAG_64_BITS,
  14189         0,
  14190         2,
  14191         soc_XLMAC_GMII_EEE_CTRL_BCM56850_A0r_fields,
  14192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14193         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14194         -1,
  14195         -1,
  14196     },
  14197 #endif /* chips */
  14198 
  14199 #if defined(BCM_56160_A0)
  14200     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM56160_A0r */
  14201         soc_block_list[16],
  14202         soc_portreg,
  14203         1,
  14204         0,
  14205         0x61f00,
  14206         SOC_REG_FLAG_64_BITS,
  14207         0,
  14208         2,
  14209         soc_CLMAC_GMII_EEE_CTRLr_fields,
  14210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14211         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14212         -1,
  14213         -1,
  14214     },
  14215 #endif /* chips */
  14216 
  14217 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  14218     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM56260_A0r */
  14219         soc_block_list[220],
  14220         soc_portreg,
  14221         1,
  14222         0,
  14223         0x61f00,
  14224         SOC_REG_FLAG_64_BITS,
  14225         0,
  14226         2,
  14227         soc_CLMAC_GMII_EEE_CTRLr_fields,
  14228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14229         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14230         -1,
  14231         -1,
  14232     },
  14233 #endif /* chips */
  14234 
  14235 #if defined(BCM_56270_A0)
  14236     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM56270_A0r */
  14237         soc_block_list[220],
  14238         soc_portreg,
  14239         1,
  14240         0,
  14241         0x61f00,
  14242         SOC_REG_FLAG_64_BITS,
  14243         0,
  14244         2,
  14245         soc_CLMAC_GMII_EEE_CTRLr_fields,
  14246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14247         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14248         -1,
  14249         -1,
  14250     },
  14251 #endif /* chips */
  14252 
  14253 #if defined(BCM_56370_A0)
  14254     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM56370_A0r */
  14255         soc_block_list[16],
  14256         soc_portreg,
  14257         1,
  14258         0,
  14259         0x61f00,
  14260         SOC_REG_FLAG_64_BITS,
  14261         0,
  14262         2,
  14263         soc_CLMAC_GMII_EEE_CTRLr_fields,
  14264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14265         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14266         -1,
  14267         -1,
  14268         3,
  14269     },
  14270 #endif /* chips */
  14271 
  14272 #if defined(BCM_56560_A0)
  14273     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM56560_A0r */
  14274         soc_block_list[16],
  14275         soc_portreg,
  14276         1,
  14277         0,
  14278         0x61f00,
  14279         SOC_REG_FLAG_64_BITS,
  14280         0,
  14281         2,
  14282         soc_CLMAC_GMII_EEE_CTRLr_fields,
  14283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14284         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14285         -1,
  14286         -1,
  14287     },
  14288 #endif /* chips */
  14289 
  14290 #if defined(BCM_56560_B0)
  14291     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM56560_B0r */
  14292         soc_block_list[16],
  14293         soc_portreg,
  14294         1,
  14295         0,
  14296         0x61f00,
  14297         SOC_REG_FLAG_64_BITS,
  14298         0,
  14299         2,
  14300         soc_CLMAC_GMII_EEE_CTRLr_fields,
  14301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14302         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14303         -1,
  14304         -1,
  14305     },
  14306 #endif /* chips */
  14307 
  14308 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14309     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM56670_A0r */
  14310         soc_block_list[16],
  14311         soc_portreg,
  14312         1,
  14313         0,
  14314         0x61e00,
  14315         SOC_REG_FLAG_64_BITS,
  14316         0,
  14317         2,
  14318         soc_CLMAC_GMII_EEE_CTRLr_fields,
  14319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14320         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14321         -1,
  14322         -1,
  14323     },
  14324 #endif /* chips */
  14325 
  14326 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  14327     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM56850_A0r */
  14328         soc_block_list[16],
  14329         soc_portreg,
  14330         1,
  14331         0,
  14332         0x61f00,
  14333         SOC_REG_FLAG_64_BITS,
  14334         0,
  14335         2,
  14336         soc_XLMAC_GMII_EEE_CTRL_BCM56850_A0r_fields,
  14337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14338         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14339         -1,
  14340         -1,
  14341     },
  14342 #endif /* chips */
  14343 
  14344 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14345     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  14346     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  14347     defined(BCM_56980_B0)
  14348     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM56960_A0r */
  14349         soc_block_list[16],
  14350         soc_portreg,
  14351         1,
  14352         0,
  14353         0x61f00,
  14354         SOC_REG_FLAG_64_BITS,
  14355         0,
  14356         2,
  14357         soc_CLMAC_GMII_EEE_CTRLr_fields,
  14358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14359         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14360         -1,
  14361         -1,
  14362         3,
  14363     },
  14364 #endif /* chips */
  14365 
  14366 #if defined(BCM_88270_A0)
  14367     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM88270_A0r */
  14368         soc_block_list[221],
  14369         soc_portreg,
  14370         1,
  14371         0,
  14372         0x61f00,
  14373         SOC_REG_FLAG_64_BITS,
  14374         0,
  14375         2,
  14376         soc_XLMAC_GMII_EEE_CTRL_BCM88270_A0r_fields,
  14377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14378         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14379         -1,
  14380         -1,
  14381     },
  14382 #endif /* chips */
  14383 
  14384 #if defined(BCM_88375_A0)
  14385     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM88375_A0r */
  14386         soc_block_list[56],
  14387         soc_portreg,
  14388         1,
  14389         0,
  14390         0x61f00,
  14391         SOC_REG_FLAG_64_BITS,
  14392         0,
  14393         2,
  14394         soc_XLMAC_GMII_EEE_CTRL_BCM88375_A0r_fields,
  14395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14396         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14397         -1,
  14398         -1,
  14399     },
  14400 #endif /* chips */
  14401 
  14402 #if defined(BCM_88375_B0)
  14403     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM88375_B0r */
  14404         soc_block_list[56],
  14405         soc_portreg,
  14406         1,
  14407         0,
  14408         0x61f00,
  14409         SOC_REG_FLAG_64_BITS,
  14410         0,
  14411         2,
  14412         soc_XLMAC_GMII_EEE_CTRL_BCM88375_B0r_fields,
  14413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14414         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14415         -1,
  14416         -1,
  14417     },
  14418 #endif /* chips */
  14419 
  14420 #if defined(BCM_88470_A0)
  14421     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM88470_A0r */
  14422         soc_block_list[56],
  14423         soc_portreg,
  14424         1,
  14425         0,
  14426         0x61f00,
  14427         SOC_REG_FLAG_64_BITS,
  14428         0,
  14429         2,
  14430         soc_XLMAC_GMII_EEE_CTRL_BCM88470_A0r_fields,
  14431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14432         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14433         -1,
  14434         -1,
  14435     },
  14436 #endif /* chips */
  14437 
  14438 #if defined(BCM_88470_B0)
  14439     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM88470_B0r */
  14440         soc_block_list[56],
  14441         soc_portreg,
  14442         1,
  14443         0,
  14444         0x61f00,
  14445         SOC_REG_FLAG_64_BITS,
  14446         0,
  14447         2,
  14448         soc_XLMAC_GMII_EEE_CTRL_BCM88470_B0r_fields,
  14449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14450         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14451         -1,
  14452         -1,
  14453     },
  14454 #endif /* chips */
  14455 
  14456 #if defined(BCM_88675_A0)
  14457     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM88675_A0r */
  14458         soc_block_list[56],
  14459         soc_portreg,
  14460         1,
  14461         0,
  14462         0x61f00,
  14463         SOC_REG_FLAG_64_BITS,
  14464         0,
  14465         2,
  14466         soc_XLMAC_GMII_EEE_CTRLr_fields,
  14467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14468         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14469         -1,
  14470         -1,
  14471     },
  14472 #endif /* chips */
  14473 
  14474 #if defined(BCM_88675_B0)
  14475     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM88675_B0r */
  14476         soc_block_list[56],
  14477         soc_portreg,
  14478         1,
  14479         0,
  14480         0x61f00,
  14481         SOC_REG_FLAG_64_BITS,
  14482         0,
  14483         2,
  14484         soc_XLMAC_GMII_EEE_CTRL_BCM88675_B0r_fields,
  14485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14486         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14487         -1,
  14488         -1,
  14489     },
  14490 #endif /* chips */
  14491 
  14492 #if defined(BCM_88680_A0)
  14493     { /* SOC_REG_INT_XLMAC_GMII_EEE_CTRL_BCM88680_A0r */
  14494         soc_block_list[56],
  14495         soc_portreg,
  14496         1,
  14497         0,
  14498         0x61f00,
  14499         SOC_REG_FLAG_64_BITS,
  14500         0,
  14501         2,
  14502         soc_XLMAC_GMII_EEE_CTRL_BCM88680_A0r_fields,
  14503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14504         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  14505         -1,
  14506         -1,
  14507     },
  14508 #endif /* chips */
  14509 
  14510 #if defined(BCM_2801PM_A0)
  14511     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0r */
  14512         soc_block_list[56],
  14513         soc_portreg,
  14514         1,
  14515         0,
  14516         0x61d00,
  14517         SOC_REG_FLAG_64_BITS,
  14518         0,
  14519         1,
  14520         soc_CLMAC_HIGIG_HDR_0r_fields,
  14521         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14522         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14523         -1,
  14524         -1,
  14525     },
  14526 #endif /* chips */
  14527 
  14528 #if defined(BCM_2801PM_A0)
  14529     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1r */
  14530         soc_block_list[56],
  14531         soc_portreg,
  14532         1,
  14533         0,
  14534         0x61e00,
  14535         SOC_REG_FLAG_64_BITS,
  14536         0,
  14537         1,
  14538         soc_CLMAC_HIGIG_HDR_1r_fields,
  14539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14540         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14541         -1,
  14542         -1,
  14543     },
  14544 #endif /* chips */
  14545 
  14546 #if defined(BCM_53400_A0)
  14547     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM53400_A0r */
  14548         soc_block_list[16],
  14549         soc_portreg,
  14550         1,
  14551         0,
  14552         0x61d00,
  14553         SOC_REG_FLAG_64_BITS,
  14554         0,
  14555         3,
  14556         soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields,
  14557         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14558         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14559         -1,
  14560         -1,
  14561     },
  14562 #endif /* chips */
  14563 
  14564 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  14565     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM53570_A0r */
  14566         soc_block_list[16],
  14567         soc_portreg,
  14568         1,
  14569         0,
  14570         0x61c00,
  14571         SOC_REG_FLAG_64_BITS,
  14572         0,
  14573         3,
  14574         soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields,
  14575         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14576         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14577         -1,
  14578         -1,
  14579     },
  14580 #endif /* chips */
  14581 
  14582 #if defined(BCM_56150_A0)
  14583     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM56150_A0r */
  14584         soc_block_list[16],
  14585         soc_portreg,
  14586         1,
  14587         0,
  14588         0x61d00,
  14589         SOC_REG_FLAG_64_BITS,
  14590         0,
  14591         3,
  14592         soc_XLMAC_HIGIG_HDR_0_BCM56850_A0r_fields,
  14593         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14594         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14595         -1,
  14596         -1,
  14597     },
  14598 #endif /* chips */
  14599 
  14600 #if defined(BCM_56160_A0)
  14601     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM56160_A0r */
  14602         soc_block_list[16],
  14603         soc_portreg,
  14604         1,
  14605         0,
  14606         0x61d00,
  14607         SOC_REG_FLAG_64_BITS,
  14608         0,
  14609         3,
  14610         soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields,
  14611         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14612         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14613         -1,
  14614         -1,
  14615     },
  14616 #endif /* chips */
  14617 
  14618 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  14619     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM56260_A0r */
  14620         soc_block_list[220],
  14621         soc_portreg,
  14622         1,
  14623         0,
  14624         0x61d00,
  14625         SOC_REG_FLAG_64_BITS,
  14626         0,
  14627         3,
  14628         soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields,
  14629         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14630         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14631         -1,
  14632         -1,
  14633     },
  14634 #endif /* chips */
  14635 
  14636 #if defined(BCM_56270_A0)
  14637     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM56270_A0r */
  14638         soc_block_list[220],
  14639         soc_portreg,
  14640         1,
  14641         0,
  14642         0x61d00,
  14643         SOC_REG_FLAG_64_BITS,
  14644         0,
  14645         3,
  14646         soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields,
  14647         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14648         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14649         -1,
  14650         -1,
  14651     },
  14652 #endif /* chips */
  14653 
  14654 #if defined(BCM_56370_A0)
  14655     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM56370_A0r */
  14656         soc_block_list[16],
  14657         soc_portreg,
  14658         1,
  14659         0,
  14660         0x61d00,
  14661         SOC_REG_FLAG_64_BITS,
  14662         0,
  14663         3,
  14664         soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields,
  14665         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14666         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14667         -1,
  14668         -1,
  14669         3,
  14670     },
  14671 #endif /* chips */
  14672 
  14673 #if defined(BCM_56560_A0)
  14674     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM56560_A0r */
  14675         soc_block_list[16],
  14676         soc_portreg,
  14677         1,
  14678         0,
  14679         0x61d00,
  14680         SOC_REG_FLAG_64_BITS,
  14681         0,
  14682         3,
  14683         soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields,
  14684         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14685         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14686         -1,
  14687         -1,
  14688     },
  14689 #endif /* chips */
  14690 
  14691 #if defined(BCM_56560_B0)
  14692     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM56560_B0r */
  14693         soc_block_list[16],
  14694         soc_portreg,
  14695         1,
  14696         0,
  14697         0x61d00,
  14698         SOC_REG_FLAG_64_BITS,
  14699         0,
  14700         3,
  14701         soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields,
  14702         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14703         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14704         -1,
  14705         -1,
  14706     },
  14707 #endif /* chips */
  14708 
  14709 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14710     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM56670_A0r */
  14711         soc_block_list[16],
  14712         soc_portreg,
  14713         1,
  14714         0,
  14715         0x61c00,
  14716         SOC_REG_FLAG_64_BITS,
  14717         0,
  14718         3,
  14719         soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields,
  14720         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14721         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14722         -1,
  14723         -1,
  14724     },
  14725 #endif /* chips */
  14726 
  14727 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  14728     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM56850_A0r */
  14729         soc_block_list[16],
  14730         soc_portreg,
  14731         1,
  14732         0,
  14733         0x61d00,
  14734         SOC_REG_FLAG_64_BITS,
  14735         0,
  14736         3,
  14737         soc_XLMAC_HIGIG_HDR_0_BCM56850_A0r_fields,
  14738         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14739         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14740         -1,
  14741         -1,
  14742     },
  14743 #endif /* chips */
  14744 
  14745 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14746     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  14747     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  14748     defined(BCM_56980_B0)
  14749     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM56960_A0r */
  14750         soc_block_list[16],
  14751         soc_portreg,
  14752         1,
  14753         0,
  14754         0x61d00,
  14755         SOC_REG_FLAG_64_BITS,
  14756         0,
  14757         3,
  14758         soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields,
  14759         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14760         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14761         -1,
  14762         -1,
  14763         3,
  14764     },
  14765 #endif /* chips */
  14766 
  14767 #if defined(BCM_88270_A0)
  14768     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM88270_A0r */
  14769         soc_block_list[221],
  14770         soc_portreg,
  14771         1,
  14772         0,
  14773         0x61d00,
  14774         SOC_REG_FLAG_64_BITS,
  14775         0,
  14776         1,
  14777         soc_XLMAC_HIGIG_HDR_0_BCM88270_A0r_fields,
  14778         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14779         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14780         -1,
  14781         -1,
  14782     },
  14783 #endif /* chips */
  14784 
  14785 #if defined(BCM_88375_A0)
  14786     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM88375_A0r */
  14787         soc_block_list[56],
  14788         soc_portreg,
  14789         1,
  14790         0,
  14791         0x61d00,
  14792         SOC_REG_FLAG_64_BITS,
  14793         0,
  14794         1,
  14795         soc_XLMAC_HIGIG_HDR_0_BCM88375_A0r_fields,
  14796         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14797         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14798         -1,
  14799         -1,
  14800     },
  14801 #endif /* chips */
  14802 
  14803 #if defined(BCM_88375_B0)
  14804     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM88375_B0r */
  14805         soc_block_list[56],
  14806         soc_portreg,
  14807         1,
  14808         0,
  14809         0x61d00,
  14810         SOC_REG_FLAG_64_BITS,
  14811         0,
  14812         1,
  14813         soc_XLMAC_HIGIG_HDR_0_BCM88375_B0r_fields,
  14814         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14815         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14816         -1,
  14817         -1,
  14818     },
  14819 #endif /* chips */
  14820 
  14821 #if defined(BCM_88470_A0)
  14822     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM88470_A0r */
  14823         soc_block_list[56],
  14824         soc_portreg,
  14825         1,
  14826         0,
  14827         0x61d00,
  14828         SOC_REG_FLAG_64_BITS,
  14829         0,
  14830         1,
  14831         soc_XLMAC_HIGIG_HDR_0_BCM88470_A0r_fields,
  14832         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14833         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14834         -1,
  14835         -1,
  14836     },
  14837 #endif /* chips */
  14838 
  14839 #if defined(BCM_88470_B0)
  14840     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM88470_B0r */
  14841         soc_block_list[56],
  14842         soc_portreg,
  14843         1,
  14844         0,
  14845         0x61d00,
  14846         SOC_REG_FLAG_64_BITS,
  14847         0,
  14848         1,
  14849         soc_XLMAC_HIGIG_HDR_0_BCM88470_B0r_fields,
  14850         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14851         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14852         -1,
  14853         -1,
  14854     },
  14855 #endif /* chips */
  14856 
  14857 #if defined(BCM_88675_A0)
  14858     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM88675_A0r */
  14859         soc_block_list[56],
  14860         soc_portreg,
  14861         1,
  14862         0,
  14863         0x61d00,
  14864         SOC_REG_FLAG_64_BITS,
  14865         0,
  14866         1,
  14867         soc_XLMAC_HIGIG_HDR_0r_fields,
  14868         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14869         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14870         -1,
  14871         -1,
  14872     },
  14873 #endif /* chips */
  14874 
  14875 #if defined(BCM_88675_B0)
  14876     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM88675_B0r */
  14877         soc_block_list[56],
  14878         soc_portreg,
  14879         1,
  14880         0,
  14881         0x61d00,
  14882         SOC_REG_FLAG_64_BITS,
  14883         0,
  14884         1,
  14885         soc_XLMAC_HIGIG_HDR_0_BCM88675_B0r_fields,
  14886         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14887         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14888         -1,
  14889         -1,
  14890     },
  14891 #endif /* chips */
  14892 
  14893 #if defined(BCM_88680_A0)
  14894     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_0_BCM88680_A0r */
  14895         soc_block_list[56],
  14896         soc_portreg,
  14897         1,
  14898         0,
  14899         0x61d00,
  14900         SOC_REG_FLAG_64_BITS,
  14901         0,
  14902         1,
  14903         soc_XLMAC_HIGIG_HDR_0_BCM88680_A0r_fields,
  14904         SOC_RESET_VAL_DEC(0x00000000, 0xfb800000)
  14905         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14906         -1,
  14907         -1,
  14908     },
  14909 #endif /* chips */
  14910 
  14911 #if defined(BCM_53400_A0)
  14912     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM53400_A0r */
  14913         soc_block_list[16],
  14914         soc_portreg,
  14915         1,
  14916         0,
  14917         0x61e00,
  14918         SOC_REG_FLAG_64_BITS,
  14919         0,
  14920         3,
  14921         soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields,
  14922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14923         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14924         -1,
  14925         -1,
  14926     },
  14927 #endif /* chips */
  14928 
  14929 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  14930     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM53570_A0r */
  14931         soc_block_list[16],
  14932         soc_portreg,
  14933         1,
  14934         0,
  14935         0x61d00,
  14936         SOC_REG_FLAG_64_BITS,
  14937         0,
  14938         3,
  14939         soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields,
  14940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14941         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14942         -1,
  14943         -1,
  14944     },
  14945 #endif /* chips */
  14946 
  14947 #if defined(BCM_56150_A0)
  14948     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM56150_A0r */
  14949         soc_block_list[16],
  14950         soc_portreg,
  14951         1,
  14952         0,
  14953         0x61e00,
  14954         SOC_REG_FLAG_64_BITS,
  14955         0,
  14956         3,
  14957         soc_XLMAC_HIGIG_HDR_1_BCM56850_A0r_fields,
  14958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14959         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14960         -1,
  14961         -1,
  14962     },
  14963 #endif /* chips */
  14964 
  14965 #if defined(BCM_56160_A0)
  14966     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM56160_A0r */
  14967         soc_block_list[16],
  14968         soc_portreg,
  14969         1,
  14970         0,
  14971         0x61e00,
  14972         SOC_REG_FLAG_64_BITS,
  14973         0,
  14974         3,
  14975         soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields,
  14976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14977         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14978         -1,
  14979         -1,
  14980     },
  14981 #endif /* chips */
  14982 
  14983 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  14984     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM56260_A0r */
  14985         soc_block_list[220],
  14986         soc_portreg,
  14987         1,
  14988         0,
  14989         0x61e00,
  14990         SOC_REG_FLAG_64_BITS,
  14991         0,
  14992         3,
  14993         soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields,
  14994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14995         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14996         -1,
  14997         -1,
  14998     },
  14999 #endif /* chips */
  15000 
  15001 #if defined(BCM_56270_A0)
  15002     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM56270_A0r */
  15003         soc_block_list[220],
  15004         soc_portreg,
  15005         1,
  15006         0,
  15007         0x61e00,
  15008         SOC_REG_FLAG_64_BITS,
  15009         0,
  15010         3,
  15011         soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields,
  15012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15013         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15014         -1,
  15015         -1,
  15016     },
  15017 #endif /* chips */
  15018 
  15019 #if defined(BCM_56370_A0)
  15020     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM56370_A0r */
  15021         soc_block_list[16],
  15022         soc_portreg,
  15023         1,
  15024         0,
  15025         0x61e00,
  15026         SOC_REG_FLAG_64_BITS,
  15027         0,
  15028         3,
  15029         soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields,
  15030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15031         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15032         -1,
  15033         -1,
  15034         3,
  15035     },
  15036 #endif /* chips */
  15037 
  15038 #if defined(BCM_56560_A0)
  15039     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM56560_A0r */
  15040         soc_block_list[16],
  15041         soc_portreg,
  15042         1,
  15043         0,
  15044         0x61e00,
  15045         SOC_REG_FLAG_64_BITS,
  15046         0,
  15047         3,
  15048         soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields,
  15049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15050         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15051         -1,
  15052         -1,
  15053     },
  15054 #endif /* chips */
  15055 
  15056 #if defined(BCM_56560_B0)
  15057     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM56560_B0r */
  15058         soc_block_list[16],
  15059         soc_portreg,
  15060         1,
  15061         0,
  15062         0x61e00,
  15063         SOC_REG_FLAG_64_BITS,
  15064         0,
  15065         3,
  15066         soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields,
  15067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15068         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15069         -1,
  15070         -1,
  15071     },
  15072 #endif /* chips */
  15073 
  15074 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  15075     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM56670_A0r */
  15076         soc_block_list[16],
  15077         soc_portreg,
  15078         1,
  15079         0,
  15080         0x61d00,
  15081         SOC_REG_FLAG_64_BITS,
  15082         0,
  15083         3,
  15084         soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields,
  15085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15086         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15087         -1,
  15088         -1,
  15089     },
  15090 #endif /* chips */
  15091 
  15092 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  15093     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM56850_A0r */
  15094         soc_block_list[16],
  15095         soc_portreg,
  15096         1,
  15097         0,
  15098         0x61e00,
  15099         SOC_REG_FLAG_64_BITS,
  15100         0,
  15101         3,
  15102         soc_XLMAC_HIGIG_HDR_1_BCM56850_A0r_fields,
  15103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15104         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15105         -1,
  15106         -1,
  15107     },
  15108 #endif /* chips */
  15109 
  15110 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15111     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  15112     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  15113     defined(BCM_56980_B0)
  15114     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM56960_A0r */
  15115         soc_block_list[16],
  15116         soc_portreg,
  15117         1,
  15118         0,
  15119         0x61e00,
  15120         SOC_REG_FLAG_64_BITS,
  15121         0,
  15122         3,
  15123         soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields,
  15124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15125         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15126         -1,
  15127         -1,
  15128         3,
  15129     },
  15130 #endif /* chips */
  15131 
  15132 #if defined(BCM_88270_A0)
  15133     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM88270_A0r */
  15134         soc_block_list[221],
  15135         soc_portreg,
  15136         1,
  15137         0,
  15138         0x61e00,
  15139         SOC_REG_FLAG_64_BITS,
  15140         0,
  15141         1,
  15142         soc_XLMAC_HIGIG_HDR_1_BCM88270_A0r_fields,
  15143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15144         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15145         -1,
  15146         -1,
  15147     },
  15148 #endif /* chips */
  15149 
  15150 #if defined(BCM_88375_A0)
  15151     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM88375_A0r */
  15152         soc_block_list[56],
  15153         soc_portreg,
  15154         1,
  15155         0,
  15156         0x61e00,
  15157         SOC_REG_FLAG_64_BITS,
  15158         0,
  15159         1,
  15160         soc_XLMAC_HIGIG_HDR_1_BCM88375_A0r_fields,
  15161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15162         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15163         -1,
  15164         -1,
  15165     },
  15166 #endif /* chips */
  15167 
  15168 #if defined(BCM_88375_B0)
  15169     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM88375_B0r */
  15170         soc_block_list[56],
  15171         soc_portreg,
  15172         1,
  15173         0,
  15174         0x61e00,
  15175         SOC_REG_FLAG_64_BITS,
  15176         0,
  15177         1,
  15178         soc_XLMAC_HIGIG_HDR_1_BCM88375_B0r_fields,
  15179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15180         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15181         -1,
  15182         -1,
  15183     },
  15184 #endif /* chips */
  15185 
  15186 #if defined(BCM_88470_A0)
  15187     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM88470_A0r */
  15188         soc_block_list[56],
  15189         soc_portreg,
  15190         1,
  15191         0,
  15192         0x61e00,
  15193         SOC_REG_FLAG_64_BITS,
  15194         0,
  15195         1,
  15196         soc_XLMAC_HIGIG_HDR_1_BCM88470_A0r_fields,
  15197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15198         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15199         -1,
  15200         -1,
  15201     },
  15202 #endif /* chips */
  15203 
  15204 #if defined(BCM_88470_B0)
  15205     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM88470_B0r */
  15206         soc_block_list[56],
  15207         soc_portreg,
  15208         1,
  15209         0,
  15210         0x61e00,
  15211         SOC_REG_FLAG_64_BITS,
  15212         0,
  15213         1,
  15214         soc_XLMAC_HIGIG_HDR_1_BCM88470_B0r_fields,
  15215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15216         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15217         -1,
  15218         -1,
  15219     },
  15220 #endif /* chips */
  15221 
  15222 #if defined(BCM_88675_A0)
  15223     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM88675_A0r */
  15224         soc_block_list[56],
  15225         soc_portreg,
  15226         1,
  15227         0,
  15228         0x61e00,
  15229         SOC_REG_FLAG_64_BITS,
  15230         0,
  15231         1,
  15232         soc_XLMAC_HIGIG_HDR_1r_fields,
  15233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15234         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15235         -1,
  15236         -1,
  15237     },
  15238 #endif /* chips */
  15239 
  15240 #if defined(BCM_88675_B0)
  15241     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM88675_B0r */
  15242         soc_block_list[56],
  15243         soc_portreg,
  15244         1,
  15245         0,
  15246         0x61e00,
  15247         SOC_REG_FLAG_64_BITS,
  15248         0,
  15249         1,
  15250         soc_XLMAC_HIGIG_HDR_1_BCM88675_B0r_fields,
  15251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15252         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15253         -1,
  15254         -1,
  15255     },
  15256 #endif /* chips */
  15257 
  15258 #if defined(BCM_88680_A0)
  15259     { /* SOC_REG_INT_XLMAC_HIGIG_HDR_1_BCM88680_A0r */
  15260         soc_block_list[56],
  15261         soc_portreg,
  15262         1,
  15263         0,
  15264         0x61e00,
  15265         SOC_REG_FLAG_64_BITS,
  15266         0,
  15267         1,
  15268         soc_XLMAC_HIGIG_HDR_1_BCM88680_A0r_fields,
  15269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15270         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  15271         -1,
  15272         -1,
  15273     },
  15274 #endif /* chips */
  15275 
  15276 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15277     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  15278     defined(BCM_56980_B0)
  15279     { /* SOC_REG_INT_XLMAC_INTR_ENABLEr */
  15280         soc_block_list[16],
  15281         soc_portreg,
  15282         1,
  15283         0,
  15284         0x63600,
  15285         SOC_REG_FLAG_64_BITS,
  15286         0,
  15287         14,
  15288         soc_XLMAC_INTR_ENABLEr_fields,
  15289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15290         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15291         -1,
  15292         -1,
  15293         3,
  15294     },
  15295 #endif /* chips */
  15296 
  15297 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  15298     { /* SOC_REG_INT_XLMAC_INTR_ENABLE_BCM53570_A0r */
  15299         soc_block_list[16],
  15300         soc_portreg,
  15301         1,
  15302         0,
  15303         0x63600,
  15304         SOC_REG_FLAG_64_BITS,
  15305         0,
  15306         18,
  15307         soc_XLMAC_INTR_ENABLE_BCM53570_A0r_fields,
  15308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15309         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  15310         -1,
  15311         -1,
  15312     },
  15313 #endif /* chips */
  15314 
  15315 #if defined(BCM_56370_A0)
  15316     { /* SOC_REG_INT_XLMAC_INTR_ENABLE_BCM56370_A0r */
  15317         soc_block_list[16],
  15318         soc_portreg,
  15319         1,
  15320         0,
  15321         0x63600,
  15322         SOC_REG_FLAG_64_BITS,
  15323         0,
  15324         14,
  15325         soc_XLMAC_INTR_ENABLEr_fields,
  15326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15327         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15328         -1,
  15329         -1,
  15330         3,
  15331     },
  15332 #endif /* chips */
  15333 
  15334 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  15335     { /* SOC_REG_INT_XLMAC_INTR_ENABLE_BCM56670_A0r */
  15336         soc_block_list[16],
  15337         soc_portreg,
  15338         1,
  15339         0,
  15340         0x63600,
  15341         SOC_REG_FLAG_64_BITS,
  15342         0,
  15343         18,
  15344         soc_XLMAC_INTR_ENABLE_BCM53570_A0r_fields,
  15345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15346         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  15347         -1,
  15348         -1,
  15349     },
  15350 #endif /* chips */
  15351 
  15352 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15353     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  15354     defined(BCM_56980_B0)
  15355     { /* SOC_REG_INT_XLMAC_INTR_STATUSr */
  15356         soc_block_list[16],
  15357         soc_portreg,
  15358         1,
  15359         0,
  15360         0x63500,
  15361         SOC_REG_FLAG_64_BITS |
  15362                           SOC_REG_FLAG_RO,
  15363         0,
  15364         14,
  15365         soc_XLMAC_INTR_STATUSr_fields,
  15366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15367         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15368         -1,
  15369         -1,
  15370         3,
  15371     },
  15372 #endif /* chips */
  15373 
  15374 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  15375     { /* SOC_REG_INT_XLMAC_INTR_STATUS_BCM53570_A0r */
  15376         soc_block_list[16],
  15377         soc_portreg,
  15378         1,
  15379         0,
  15380         0x63500,
  15381         SOC_REG_FLAG_64_BITS |
  15382                           SOC_REG_FLAG_RO,
  15383         0,
  15384         18,
  15385         soc_XLMAC_INTR_STATUS_BCM53570_A0r_fields,
  15386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15387         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  15388         -1,
  15389         -1,
  15390     },
  15391 #endif /* chips */
  15392 
  15393 #if defined(BCM_56370_A0)
  15394     { /* SOC_REG_INT_XLMAC_INTR_STATUS_BCM56370_A0r */
  15395         soc_block_list[16],
  15396         soc_portreg,
  15397         1,
  15398         0,
  15399         0x63500,
  15400         SOC_REG_FLAG_64_BITS |
  15401                           SOC_REG_FLAG_RO,
  15402         0,
  15403         14,
  15404         soc_XLMAC_INTR_STATUSr_fields,
  15405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15406         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15407         -1,
  15408         -1,
  15409         3,
  15410     },
  15411 #endif /* chips */
  15412 
  15413 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  15414     { /* SOC_REG_INT_XLMAC_INTR_STATUS_BCM56670_A0r */
  15415         soc_block_list[16],
  15416         soc_portreg,
  15417         1,
  15418         0,
  15419         0x63500,
  15420         SOC_REG_FLAG_64_BITS |
  15421                           SOC_REG_FLAG_RO,
  15422         0,
  15423         18,
  15424         soc_XLMAC_INTR_STATUS_BCM53570_A0r_fields,
  15425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15426         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  15427         -1,
  15428         -1,
  15429     },
  15430 #endif /* chips */
  15431 
  15432 #if defined(BCM_2801PM_A0)
  15433     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUSr */
  15434         soc_block_list[56],
  15435         soc_portreg,
  15436         1,
  15437         0,
  15438         0x61900,
  15439         SOC_REG_FLAG_RO,
  15440         0,
  15441         2,
  15442         soc_CLMAC_LAG_FAILOVER_STATUSr_fields,
  15443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15444         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15445         -1,
  15446         -1,
  15447     },
  15448 #endif /* chips */
  15449 
  15450 #if defined(BCM_53400_A0)
  15451     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r */
  15452         soc_block_list[16],
  15453         soc_portreg,
  15454         1,
  15455         0,
  15456         0x61900,
  15457         SOC_REG_FLAG_64_BITS |
  15458                           SOC_REG_FLAG_RO,
  15459         0,
  15460         2,
  15461         soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields,
  15462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15463         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15464         -1,
  15465         -1,
  15466     },
  15467 #endif /* chips */
  15468 
  15469 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  15470     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM53570_A0r */
  15471         soc_block_list[16],
  15472         soc_portreg,
  15473         1,
  15474         0,
  15475         0x61800,
  15476         SOC_REG_FLAG_64_BITS |
  15477                           SOC_REG_FLAG_RO,
  15478         0,
  15479         2,
  15480         soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields,
  15481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15482         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15483         -1,
  15484         -1,
  15485     },
  15486 #endif /* chips */
  15487 
  15488 #if defined(BCM_56150_A0)
  15489     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM56150_A0r */
  15490         soc_block_list[16],
  15491         soc_portreg,
  15492         1,
  15493         0,
  15494         0x61900,
  15495         SOC_REG_FLAG_64_BITS |
  15496                           SOC_REG_FLAG_RO,
  15497         0,
  15498         2,
  15499         soc_CMAC_LAG_FAILOVER_STATUSr_fields,
  15500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15501         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15502         -1,
  15503         -1,
  15504     },
  15505 #endif /* chips */
  15506 
  15507 #if defined(BCM_56160_A0)
  15508     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM56160_A0r */
  15509         soc_block_list[16],
  15510         soc_portreg,
  15511         1,
  15512         0,
  15513         0x61900,
  15514         SOC_REG_FLAG_64_BITS |
  15515                           SOC_REG_FLAG_RO,
  15516         0,
  15517         2,
  15518         soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields,
  15519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15520         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15521         -1,
  15522         -1,
  15523     },
  15524 #endif /* chips */
  15525 
  15526 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  15527     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM56260_A0r */
  15528         soc_block_list[220],
  15529         soc_portreg,
  15530         1,
  15531         0,
  15532         0x61900,
  15533         SOC_REG_FLAG_64_BITS |
  15534                           SOC_REG_FLAG_RO,
  15535         0,
  15536         2,
  15537         soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields,
  15538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15539         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15540         -1,
  15541         -1,
  15542     },
  15543 #endif /* chips */
  15544 
  15545 #if defined(BCM_56270_A0)
  15546     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM56270_A0r */
  15547         soc_block_list[220],
  15548         soc_portreg,
  15549         1,
  15550         0,
  15551         0x61900,
  15552         SOC_REG_FLAG_64_BITS |
  15553                           SOC_REG_FLAG_RO,
  15554         0,
  15555         2,
  15556         soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields,
  15557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15558         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15559         -1,
  15560         -1,
  15561     },
  15562 #endif /* chips */
  15563 
  15564 #if defined(BCM_56370_A0)
  15565     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM56370_A0r */
  15566         soc_block_list[16],
  15567         soc_portreg,
  15568         1,
  15569         0,
  15570         0x61900,
  15571         SOC_REG_FLAG_64_BITS |
  15572                           SOC_REG_FLAG_RO,
  15573         0,
  15574         2,
  15575         soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields,
  15576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15577         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15578         -1,
  15579         -1,
  15580         3,
  15581     },
  15582 #endif /* chips */
  15583 
  15584 #if defined(BCM_56560_A0)
  15585     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM56560_A0r */
  15586         soc_block_list[16],
  15587         soc_portreg,
  15588         1,
  15589         0,
  15590         0x61900,
  15591         SOC_REG_FLAG_64_BITS |
  15592                           SOC_REG_FLAG_RO,
  15593         0,
  15594         2,
  15595         soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields,
  15596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15597         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15598         -1,
  15599         -1,
  15600     },
  15601 #endif /* chips */
  15602 
  15603 #if defined(BCM_56560_B0)
  15604     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM56560_B0r */
  15605         soc_block_list[16],
  15606         soc_portreg,
  15607         1,
  15608         0,
  15609         0x61900,
  15610         SOC_REG_FLAG_64_BITS |
  15611                           SOC_REG_FLAG_RO,
  15612         0,
  15613         2,
  15614         soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields,
  15615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15616         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15617         -1,
  15618         -1,
  15619     },
  15620 #endif /* chips */
  15621 
  15622 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  15623     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM56670_A0r */
  15624         soc_block_list[16],
  15625         soc_portreg,
  15626         1,
  15627         0,
  15628         0x61800,
  15629         SOC_REG_FLAG_64_BITS |
  15630                           SOC_REG_FLAG_RO,
  15631         0,
  15632         2,
  15633         soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields,
  15634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15635         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15636         -1,
  15637         -1,
  15638     },
  15639 #endif /* chips */
  15640 
  15641 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  15642     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM56850_A0r */
  15643         soc_block_list[16],
  15644         soc_portreg,
  15645         1,
  15646         0,
  15647         0x61900,
  15648         SOC_REG_FLAG_64_BITS |
  15649                           SOC_REG_FLAG_RO,
  15650         0,
  15651         2,
  15652         soc_CMAC_LAG_FAILOVER_STATUSr_fields,
  15653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15654         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15655         -1,
  15656         -1,
  15657     },
  15658 #endif /* chips */
  15659 
  15660 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15661     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  15662     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  15663     defined(BCM_56980_B0)
  15664     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM56960_A0r */
  15665         soc_block_list[16],
  15666         soc_portreg,
  15667         1,
  15668         0,
  15669         0x61900,
  15670         SOC_REG_FLAG_64_BITS |
  15671                           SOC_REG_FLAG_RO,
  15672         0,
  15673         2,
  15674         soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields,
  15675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15676         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15677         -1,
  15678         -1,
  15679         3,
  15680     },
  15681 #endif /* chips */
  15682 
  15683 #if defined(BCM_88270_A0)
  15684     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM88270_A0r */
  15685         soc_block_list[221],
  15686         soc_portreg,
  15687         1,
  15688         0,
  15689         0x61900,
  15690         SOC_REG_FLAG_64_BITS |
  15691                           SOC_REG_FLAG_RO,
  15692         0,
  15693         2,
  15694         soc_XLMAC_LAG_FAILOVER_STATUS_BCM88270_A0r_fields,
  15695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15696         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15697         -1,
  15698         -1,
  15699     },
  15700 #endif /* chips */
  15701 
  15702 #if defined(BCM_88375_A0)
  15703     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM88375_A0r */
  15704         soc_block_list[56],
  15705         soc_portreg,
  15706         1,
  15707         0,
  15708         0x61900,
  15709         SOC_REG_FLAG_64_BITS |
  15710                           SOC_REG_FLAG_RO,
  15711         0,
  15712         2,
  15713         soc_XLMAC_LAG_FAILOVER_STATUS_BCM88375_A0r_fields,
  15714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15715         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15716         -1,
  15717         -1,
  15718     },
  15719 #endif /* chips */
  15720 
  15721 #if defined(BCM_88375_B0)
  15722     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM88375_B0r */
  15723         soc_block_list[56],
  15724         soc_portreg,
  15725         1,
  15726         0,
  15727         0x61900,
  15728         SOC_REG_FLAG_64_BITS |
  15729                           SOC_REG_FLAG_RO,
  15730         0,
  15731         2,
  15732         soc_XLMAC_LAG_FAILOVER_STATUS_BCM88375_B0r_fields,
  15733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15734         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15735         -1,
  15736         -1,
  15737     },
  15738 #endif /* chips */
  15739 
  15740 #if defined(BCM_88470_A0)
  15741     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM88470_A0r */
  15742         soc_block_list[56],
  15743         soc_portreg,
  15744         1,
  15745         0,
  15746         0x61900,
  15747         SOC_REG_FLAG_64_BITS |
  15748                           SOC_REG_FLAG_RO,
  15749         0,
  15750         2,
  15751         soc_XLMAC_LAG_FAILOVER_STATUS_BCM88470_A0r_fields,
  15752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15753         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15754         -1,
  15755         -1,
  15756     },
  15757 #endif /* chips */
  15758 
  15759 #if defined(BCM_88470_B0)
  15760     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM88470_B0r */
  15761         soc_block_list[56],
  15762         soc_portreg,
  15763         1,
  15764         0,
  15765         0x61900,
  15766         SOC_REG_FLAG_64_BITS |
  15767                           SOC_REG_FLAG_RO,
  15768         0,
  15769         2,
  15770         soc_XLMAC_LAG_FAILOVER_STATUS_BCM88470_B0r_fields,
  15771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15772         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15773         -1,
  15774         -1,
  15775     },
  15776 #endif /* chips */
  15777 
  15778 #if defined(BCM_88675_A0)
  15779     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM88675_A0r */
  15780         soc_block_list[56],
  15781         soc_portreg,
  15782         1,
  15783         0,
  15784         0x61900,
  15785         SOC_REG_FLAG_64_BITS |
  15786                           SOC_REG_FLAG_RO,
  15787         0,
  15788         2,
  15789         soc_XLMAC_LAG_FAILOVER_STATUSr_fields,
  15790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15791         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15792         -1,
  15793         -1,
  15794     },
  15795 #endif /* chips */
  15796 
  15797 #if defined(BCM_88675_B0)
  15798     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM88675_B0r */
  15799         soc_block_list[56],
  15800         soc_portreg,
  15801         1,
  15802         0,
  15803         0x61900,
  15804         SOC_REG_FLAG_64_BITS |
  15805                           SOC_REG_FLAG_RO,
  15806         0,
  15807         2,
  15808         soc_XLMAC_LAG_FAILOVER_STATUS_BCM88675_B0r_fields,
  15809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15810         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15811         -1,
  15812         -1,
  15813     },
  15814 #endif /* chips */
  15815 
  15816 #if defined(BCM_88680_A0)
  15817     { /* SOC_REG_INT_XLMAC_LAG_FAILOVER_STATUS_BCM88680_A0r */
  15818         soc_block_list[56],
  15819         soc_portreg,
  15820         1,
  15821         0,
  15822         0x61900,
  15823         SOC_REG_FLAG_64_BITS |
  15824                           SOC_REG_FLAG_RO,
  15825         0,
  15826         2,
  15827         soc_XLMAC_LAG_FAILOVER_STATUS_BCM88680_A0r_fields,
  15828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15829         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15830         -1,
  15831         -1,
  15832     },
  15833 #endif /* chips */
  15834 
  15835 #if defined(BCM_2801PM_A0)
  15836     { /* SOC_REG_INT_XLMAC_LLFC_CTRLr */
  15837         soc_block_list[56],
  15838         soc_portreg,
  15839         1,
  15840         0,
  15841         0x61200,
  15842         0,
  15843         0,
  15844         7,
  15845         soc_CLMAC_LLFC_CTRLr_fields,
  15846         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  15847         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15848         -1,
  15849         -1,
  15850     },
  15851 #endif /* chips */
  15852 
  15853 #if defined(BCM_53400_A0)
  15854     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM53400_A0r */
  15855         soc_block_list[16],
  15856         soc_portreg,
  15857         1,
  15858         0,
  15859         0x61200,
  15860         SOC_REG_FLAG_64_BITS,
  15861         0,
  15862         7,
  15863         soc_CLMAC_LLFC_CTRLr_fields,
  15864         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  15865         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15866         -1,
  15867         -1,
  15868     },
  15869 #endif /* chips */
  15870 
  15871 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  15872     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM53570_A0r */
  15873         soc_block_list[16],
  15874         soc_portreg,
  15875         1,
  15876         0,
  15877         0x61100,
  15878         SOC_REG_FLAG_64_BITS,
  15879         0,
  15880         7,
  15881         soc_CLMAC_LLFC_CTRLr_fields,
  15882         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  15883         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15884         -1,
  15885         -1,
  15886     },
  15887 #endif /* chips */
  15888 
  15889 #if defined(BCM_56150_A0)
  15890     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM56150_A0r */
  15891         soc_block_list[16],
  15892         soc_portreg,
  15893         1,
  15894         0,
  15895         0x61200,
  15896         SOC_REG_FLAG_64_BITS,
  15897         0,
  15898         7,
  15899         soc_CMAC_LLFC_CTRLr_fields,
  15900         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  15901         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15902         -1,
  15903         -1,
  15904     },
  15905 #endif /* chips */
  15906 
  15907 #if defined(BCM_56160_A0)
  15908     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM56160_A0r */
  15909         soc_block_list[16],
  15910         soc_portreg,
  15911         1,
  15912         0,
  15913         0x61200,
  15914         SOC_REG_FLAG_64_BITS,
  15915         0,
  15916         7,
  15917         soc_CLMAC_LLFC_CTRLr_fields,
  15918         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  15919         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15920         -1,
  15921         -1,
  15922     },
  15923 #endif /* chips */
  15924 
  15925 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  15926     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM56260_A0r */
  15927         soc_block_list[220],
  15928         soc_portreg,
  15929         1,
  15930         0,
  15931         0x61200,
  15932         SOC_REG_FLAG_64_BITS,
  15933         0,
  15934         7,
  15935         soc_CLMAC_LLFC_CTRLr_fields,
  15936         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  15937         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15938         -1,
  15939         -1,
  15940     },
  15941 #endif /* chips */
  15942 
  15943 #if defined(BCM_56270_A0)
  15944     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM56270_A0r */
  15945         soc_block_list[220],
  15946         soc_portreg,
  15947         1,
  15948         0,
  15949         0x61200,
  15950         SOC_REG_FLAG_64_BITS,
  15951         0,
  15952         7,
  15953         soc_CLMAC_LLFC_CTRLr_fields,
  15954         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  15955         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15956         -1,
  15957         -1,
  15958     },
  15959 #endif /* chips */
  15960 
  15961 #if defined(BCM_56370_A0)
  15962     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM56370_A0r */
  15963         soc_block_list[16],
  15964         soc_portreg,
  15965         1,
  15966         0,
  15967         0x61200,
  15968         SOC_REG_FLAG_64_BITS,
  15969         0,
  15970         7,
  15971         soc_CLMAC_LLFC_CTRLr_fields,
  15972         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  15973         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15974         -1,
  15975         -1,
  15976         3,
  15977     },
  15978 #endif /* chips */
  15979 
  15980 #if defined(BCM_56560_A0)
  15981     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM56560_A0r */
  15982         soc_block_list[16],
  15983         soc_portreg,
  15984         1,
  15985         0,
  15986         0x61200,
  15987         SOC_REG_FLAG_64_BITS,
  15988         0,
  15989         7,
  15990         soc_CLMAC_LLFC_CTRLr_fields,
  15991         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  15992         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  15993         -1,
  15994         -1,
  15995     },
  15996 #endif /* chips */
  15997 
  15998 #if defined(BCM_56560_B0)
  15999     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM56560_B0r */
  16000         soc_block_list[16],
  16001         soc_portreg,
  16002         1,
  16003         0,
  16004         0x61200,
  16005         SOC_REG_FLAG_64_BITS,
  16006         0,
  16007         7,
  16008         soc_CLMAC_LLFC_CTRLr_fields,
  16009         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16010         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16011         -1,
  16012         -1,
  16013     },
  16014 #endif /* chips */
  16015 
  16016 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  16017     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM56670_A0r */
  16018         soc_block_list[16],
  16019         soc_portreg,
  16020         1,
  16021         0,
  16022         0x61100,
  16023         SOC_REG_FLAG_64_BITS,
  16024         0,
  16025         7,
  16026         soc_CLMAC_LLFC_CTRLr_fields,
  16027         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16028         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16029         -1,
  16030         -1,
  16031     },
  16032 #endif /* chips */
  16033 
  16034 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  16035     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM56850_A0r */
  16036         soc_block_list[16],
  16037         soc_portreg,
  16038         1,
  16039         0,
  16040         0x61200,
  16041         SOC_REG_FLAG_64_BITS,
  16042         0,
  16043         7,
  16044         soc_CMAC_LLFC_CTRLr_fields,
  16045         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16046         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16047         -1,
  16048         -1,
  16049     },
  16050 #endif /* chips */
  16051 
  16052 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16053     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  16054     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  16055     defined(BCM_56980_B0)
  16056     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM56960_A0r */
  16057         soc_block_list[16],
  16058         soc_portreg,
  16059         1,
  16060         0,
  16061         0x61200,
  16062         SOC_REG_FLAG_64_BITS,
  16063         0,
  16064         7,
  16065         soc_CLMAC_LLFC_CTRLr_fields,
  16066         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16067         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16068         -1,
  16069         -1,
  16070         3,
  16071     },
  16072 #endif /* chips */
  16073 
  16074 #if defined(BCM_88270_A0)
  16075     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM88270_A0r */
  16076         soc_block_list[221],
  16077         soc_portreg,
  16078         1,
  16079         0,
  16080         0x61200,
  16081         SOC_REG_FLAG_64_BITS,
  16082         0,
  16083         7,
  16084         soc_XLMAC_LLFC_CTRL_BCM88270_A0r_fields,
  16085         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16086         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16087         -1,
  16088         -1,
  16089     },
  16090 #endif /* chips */
  16091 
  16092 #if defined(BCM_88375_A0)
  16093     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM88375_A0r */
  16094         soc_block_list[56],
  16095         soc_portreg,
  16096         1,
  16097         0,
  16098         0x61200,
  16099         SOC_REG_FLAG_64_BITS,
  16100         0,
  16101         7,
  16102         soc_XLMAC_LLFC_CTRL_BCM88375_A0r_fields,
  16103         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16104         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16105         -1,
  16106         -1,
  16107     },
  16108 #endif /* chips */
  16109 
  16110 #if defined(BCM_88375_B0)
  16111     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM88375_B0r */
  16112         soc_block_list[56],
  16113         soc_portreg,
  16114         1,
  16115         0,
  16116         0x61200,
  16117         SOC_REG_FLAG_64_BITS,
  16118         0,
  16119         7,
  16120         soc_XLMAC_LLFC_CTRL_BCM88375_B0r_fields,
  16121         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16122         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16123         -1,
  16124         -1,
  16125     },
  16126 #endif /* chips */
  16127 
  16128 #if defined(BCM_88470_A0)
  16129     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM88470_A0r */
  16130         soc_block_list[56],
  16131         soc_portreg,
  16132         1,
  16133         0,
  16134         0x61200,
  16135         SOC_REG_FLAG_64_BITS,
  16136         0,
  16137         7,
  16138         soc_XLMAC_LLFC_CTRL_BCM88470_A0r_fields,
  16139         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16140         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16141         -1,
  16142         -1,
  16143     },
  16144 #endif /* chips */
  16145 
  16146 #if defined(BCM_88470_B0)
  16147     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM88470_B0r */
  16148         soc_block_list[56],
  16149         soc_portreg,
  16150         1,
  16151         0,
  16152         0x61200,
  16153         SOC_REG_FLAG_64_BITS,
  16154         0,
  16155         7,
  16156         soc_XLMAC_LLFC_CTRL_BCM88470_B0r_fields,
  16157         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16158         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16159         -1,
  16160         -1,
  16161     },
  16162 #endif /* chips */
  16163 
  16164 #if defined(BCM_88675_A0)
  16165     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM88675_A0r */
  16166         soc_block_list[56],
  16167         soc_portreg,
  16168         1,
  16169         0,
  16170         0x61200,
  16171         SOC_REG_FLAG_64_BITS,
  16172         0,
  16173         7,
  16174         soc_XLMAC_LLFC_CTRLr_fields,
  16175         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16176         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16177         -1,
  16178         -1,
  16179     },
  16180 #endif /* chips */
  16181 
  16182 #if defined(BCM_88675_B0)
  16183     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM88675_B0r */
  16184         soc_block_list[56],
  16185         soc_portreg,
  16186         1,
  16187         0,
  16188         0x61200,
  16189         SOC_REG_FLAG_64_BITS,
  16190         0,
  16191         7,
  16192         soc_XLMAC_LLFC_CTRL_BCM88675_B0r_fields,
  16193         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16194         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16195         -1,
  16196         -1,
  16197     },
  16198 #endif /* chips */
  16199 
  16200 #if defined(BCM_88680_A0)
  16201     { /* SOC_REG_INT_XLMAC_LLFC_CTRL_BCM88680_A0r */
  16202         soc_block_list[56],
  16203         soc_portreg,
  16204         1,
  16205         0,
  16206         0x61200,
  16207         SOC_REG_FLAG_64_BITS,
  16208         0,
  16209         7,
  16210         soc_XLMAC_LLFC_CTRL_BCM88680_A0r_fields,
  16211         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  16212         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  16213         -1,
  16214         -1,
  16215     },
  16216 #endif /* chips */
  16217 
  16218 #if defined(BCM_56850_A0)
  16219     { /* SOC_REG_INT_XLMAC_MACSEC_CTRLr */
  16220         soc_block_list[16],
  16221         soc_portreg,
  16222         1,
  16223         0,
  16224         0x62100,
  16225         SOC_REG_FLAG_64_BITS,
  16226         0,
  16227         6,
  16228         soc_XLMAC_MACSEC_CTRLr_fields,
  16229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16230         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  16231         -1,
  16232         -1,
  16233     },
  16234 #endif /* chips */
  16235 
  16236 #if defined(BCM_56150_A0)
  16237     { /* SOC_REG_INT_XLMAC_MACSEC_CTRL_BCM56150_A0r */
  16238         soc_block_list[16],
  16239         soc_portreg,
  16240         1,
  16241         0,
  16242         0x62100,
  16243         SOC_REG_FLAG_64_BITS,
  16244         0,
  16245         6,
  16246         soc_XLMAC_MACSEC_CTRLr_fields,
  16247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16248         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  16249         -1,
  16250         -1,
  16251     },
  16252 #endif /* chips */
  16253 
  16254 #if defined(BCM_2801PM_A0)
  16255     { /* SOC_REG_INT_XLMAC_MEM_CTRLr */
  16256         soc_block_list[56],
  16257         soc_portreg,
  16258         1,
  16259         0,
  16260         0x62d00,
  16261         0,
  16262         0,
  16263         2,
  16264         soc_XLMAC_MEM_CTRLr_fields,
  16265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16266         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16267         -1,
  16268         -1,
  16269     },
  16270 #endif /* chips */
  16271 
  16272 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  16273     defined(BCM_56670_B0)
  16274     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM53400_A0r */
  16275         soc_block_list[16],
  16276         soc_portreg,
  16277         1,
  16278         0,
  16279         0x62d00,
  16280         SOC_REG_FLAG_64_BITS,
  16281         0,
  16282         2,
  16283         soc_XLMAC_MEM_CTRLr_fields,
  16284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16285         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16286         -1,
  16287         -1,
  16288     },
  16289 #endif /* chips */
  16290 
  16291 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16292     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM53570_A0r */
  16293         soc_block_list[16],
  16294         soc_portreg,
  16295         1,
  16296         0,
  16297         0x62d00,
  16298         SOC_REG_FLAG_64_BITS,
  16299         0,
  16300         2,
  16301         soc_XLMAC_MEM_CTRLr_fields,
  16302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16303         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16304         -1,
  16305         -1,
  16306     },
  16307 #endif /* chips */
  16308 
  16309 #if defined(BCM_56160_A0)
  16310     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM56160_A0r */
  16311         soc_block_list[16],
  16312         soc_portreg,
  16313         1,
  16314         0,
  16315         0x62e00,
  16316         SOC_REG_FLAG_64_BITS,
  16317         0,
  16318         2,
  16319         soc_XLMAC_MEM_CTRLr_fields,
  16320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16321         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16322         -1,
  16323         -1,
  16324     },
  16325 #endif /* chips */
  16326 
  16327 #if defined(BCM_56260_A0)
  16328     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM56260_A0r */
  16329         soc_block_list[220],
  16330         soc_portreg,
  16331         1,
  16332         0,
  16333         0x62d00,
  16334         SOC_REG_FLAG_64_BITS,
  16335         0,
  16336         2,
  16337         soc_XLMAC_MEM_CTRLr_fields,
  16338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16339         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16340         -1,
  16341         -1,
  16342     },
  16343 #endif /* chips */
  16344 
  16345 #if defined(BCM_56260_B0)
  16346     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM56260_B0r */
  16347         soc_block_list[220],
  16348         soc_portreg,
  16349         1,
  16350         0,
  16351         0x62e00,
  16352         SOC_REG_FLAG_64_BITS,
  16353         0,
  16354         2,
  16355         soc_XLMAC_MEM_CTRLr_fields,
  16356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16357         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16358         -1,
  16359         -1,
  16360     },
  16361 #endif /* chips */
  16362 
  16363 #if defined(BCM_56270_A0)
  16364     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM56270_A0r */
  16365         soc_block_list[220],
  16366         soc_portreg,
  16367         1,
  16368         0,
  16369         0x62e00,
  16370         SOC_REG_FLAG_64_BITS,
  16371         0,
  16372         2,
  16373         soc_XLMAC_MEM_CTRLr_fields,
  16374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16375         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16376         -1,
  16377         -1,
  16378     },
  16379 #endif /* chips */
  16380 
  16381 #if defined(BCM_56370_A0)
  16382     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM56370_A0r */
  16383         soc_block_list[16],
  16384         soc_portreg,
  16385         1,
  16386         0,
  16387         0x62e00,
  16388         SOC_REG_FLAG_64_BITS,
  16389         0,
  16390         2,
  16391         soc_XLMAC_MEM_CTRLr_fields,
  16392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16393         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16394         -1,
  16395         -1,
  16396         3,
  16397     },
  16398 #endif /* chips */
  16399 
  16400 #if defined(BCM_56560_A0)
  16401     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM56560_A0r */
  16402         soc_block_list[16],
  16403         soc_portreg,
  16404         1,
  16405         0,
  16406         0x62d00,
  16407         SOC_REG_FLAG_64_BITS,
  16408         0,
  16409         2,
  16410         soc_XLMAC_MEM_CTRLr_fields,
  16411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16412         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16413         -1,
  16414         -1,
  16415     },
  16416 #endif /* chips */
  16417 
  16418 #if defined(BCM_56560_B0)
  16419     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM56560_B0r */
  16420         soc_block_list[16],
  16421         soc_portreg,
  16422         1,
  16423         0,
  16424         0x62e00,
  16425         SOC_REG_FLAG_64_BITS,
  16426         0,
  16427         2,
  16428         soc_XLMAC_MEM_CTRLr_fields,
  16429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16430         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16431         -1,
  16432         -1,
  16433     },
  16434 #endif /* chips */
  16435 
  16436 #if defined(BCM_56860_A0)
  16437     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM56860_A0r */
  16438         soc_block_list[16],
  16439         soc_portreg,
  16440         1,
  16441         0,
  16442         0x62e00,
  16443         SOC_REG_FLAG_64_BITS,
  16444         0,
  16445         2,
  16446         soc_XLMAC_MEM_CTRL_BCM56860_A0r_fields,
  16447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16448         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16449         -1,
  16450         -1,
  16451     },
  16452 #endif /* chips */
  16453 
  16454 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  16455     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM56960_A0r */
  16456         soc_block_list[16],
  16457         soc_portreg,
  16458         1,
  16459         0,
  16460         0x62d00,
  16461         SOC_REG_FLAG_64_BITS,
  16462         0,
  16463         2,
  16464         soc_XLMAC_MEM_CTRLr_fields,
  16465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16466         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16467         -1,
  16468         -1,
  16469         3,
  16470     },
  16471 #endif /* chips */
  16472 
  16473 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16474     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  16475     defined(BCM_56980_B0)
  16476     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM56970_A0r */
  16477         soc_block_list[16],
  16478         soc_portreg,
  16479         1,
  16480         0,
  16481         0x62e00,
  16482         SOC_REG_FLAG_64_BITS,
  16483         0,
  16484         2,
  16485         soc_XLMAC_MEM_CTRLr_fields,
  16486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16487         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16488         -1,
  16489         -1,
  16490         3,
  16491     },
  16492 #endif /* chips */
  16493 
  16494 #if defined(BCM_88270_A0)
  16495     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM88270_A0r */
  16496         soc_block_list[221],
  16497         soc_portreg,
  16498         1,
  16499         0,
  16500         0x62e00,
  16501         SOC_REG_FLAG_64_BITS,
  16502         0,
  16503         2,
  16504         soc_XLMAC_MEM_CTRL_BCM88270_A0r_fields,
  16505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16506         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16507         -1,
  16508         -1,
  16509     },
  16510 #endif /* chips */
  16511 
  16512 #if defined(BCM_88375_A0)
  16513     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM88375_A0r */
  16514         soc_block_list[56],
  16515         soc_portreg,
  16516         1,
  16517         0,
  16518         0x62d00,
  16519         SOC_REG_FLAG_64_BITS,
  16520         0,
  16521         2,
  16522         soc_XLMAC_MEM_CTRL_BCM88375_A0r_fields,
  16523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16524         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16525         -1,
  16526         -1,
  16527     },
  16528 #endif /* chips */
  16529 
  16530 #if defined(BCM_88375_B0)
  16531     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM88375_B0r */
  16532         soc_block_list[56],
  16533         soc_portreg,
  16534         1,
  16535         0,
  16536         0x62e00,
  16537         SOC_REG_FLAG_64_BITS,
  16538         0,
  16539         2,
  16540         soc_XLMAC_MEM_CTRL_BCM88375_B0r_fields,
  16541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16542         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16543         -1,
  16544         -1,
  16545     },
  16546 #endif /* chips */
  16547 
  16548 #if defined(BCM_88470_A0)
  16549     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM88470_A0r */
  16550         soc_block_list[56],
  16551         soc_portreg,
  16552         1,
  16553         0,
  16554         0x62d00,
  16555         SOC_REG_FLAG_64_BITS,
  16556         0,
  16557         2,
  16558         soc_XLMAC_MEM_CTRL_BCM88470_A0r_fields,
  16559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16560         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16561         -1,
  16562         -1,
  16563     },
  16564 #endif /* chips */
  16565 
  16566 #if defined(BCM_88470_B0)
  16567     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM88470_B0r */
  16568         soc_block_list[56],
  16569         soc_portreg,
  16570         1,
  16571         0,
  16572         0x62e00,
  16573         SOC_REG_FLAG_64_BITS,
  16574         0,
  16575         2,
  16576         soc_XLMAC_MEM_CTRL_BCM88470_B0r_fields,
  16577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16578         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16579         -1,
  16580         -1,
  16581     },
  16582 #endif /* chips */
  16583 
  16584 #if defined(BCM_88675_A0)
  16585     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM88675_A0r */
  16586         soc_block_list[56],
  16587         soc_portreg,
  16588         1,
  16589         0,
  16590         0x62d00,
  16591         SOC_REG_FLAG_64_BITS,
  16592         0,
  16593         2,
  16594         soc_XLMAC_MEM_CTRL_BCM88675_A0r_fields,
  16595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16596         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16597         -1,
  16598         -1,
  16599     },
  16600 #endif /* chips */
  16601 
  16602 #if defined(BCM_88675_B0)
  16603     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM88675_B0r */
  16604         soc_block_list[56],
  16605         soc_portreg,
  16606         1,
  16607         0,
  16608         0x62e00,
  16609         SOC_REG_FLAG_64_BITS,
  16610         0,
  16611         2,
  16612         soc_XLMAC_MEM_CTRL_BCM88675_B0r_fields,
  16613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16614         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16615         -1,
  16616         -1,
  16617     },
  16618 #endif /* chips */
  16619 
  16620 #if defined(BCM_88680_A0)
  16621     { /* SOC_REG_INT_XLMAC_MEM_CTRL_BCM88680_A0r */
  16622         soc_block_list[56],
  16623         soc_portreg,
  16624         1,
  16625         0,
  16626         0x62e00,
  16627         SOC_REG_FLAG_64_BITS,
  16628         0,
  16629         2,
  16630         soc_XLMAC_MEM_CTRL_BCM88680_A0r_fields,
  16631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16632         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16633         -1,
  16634         -1,
  16635     },
  16636 #endif /* chips */
  16637 
  16638 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16639     { /* SOC_REG_INT_XLMAC_MERGE_CLEAR_STATUSr */
  16640         soc_block_list[16],
  16641         soc_portreg,
  16642         1,
  16643         0,
  16644         0x63f00,
  16645         SOC_REG_FLAG_64_BITS,
  16646         0,
  16647         2,
  16648         soc_XLMAC_MERGE_CLEAR_STATUSr_fields,
  16649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16650         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  16651         -1,
  16652         -1,
  16653     },
  16654 #endif /* chips */
  16655 
  16656 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  16657     { /* SOC_REG_INT_XLMAC_MERGE_CLEAR_STATUS_BCM56670_A0r */
  16658         soc_block_list[16],
  16659         soc_portreg,
  16660         1,
  16661         0,
  16662         0x63f00,
  16663         SOC_REG_FLAG_64_BITS,
  16664         0,
  16665         2,
  16666         soc_XLMAC_MERGE_CLEAR_STATUSr_fields,
  16667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16668         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  16669         -1,
  16670         -1,
  16671     },
  16672 #endif /* chips */
  16673 
  16674 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16675     { /* SOC_REG_INT_XLMAC_MERGE_CONFIGr */
  16676         soc_block_list[16],
  16677         soc_portreg,
  16678         1,
  16679         0,
  16680         0x63700,
  16681         SOC_REG_FLAG_64_BITS,
  16682         0,
  16683         8,
  16684         soc_MAC_MERGE_CONFIGr_fields,
  16685         SOC_RESET_VAL_DEC(0x00006848, 0x00000000)
  16686         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16687         -1,
  16688         -1,
  16689     },
  16690 #endif /* chips */
  16691 
  16692 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  16693     { /* SOC_REG_INT_XLMAC_MERGE_CONFIG_BCM56670_A0r */
  16694         soc_block_list[16],
  16695         soc_portreg,
  16696         1,
  16697         0,
  16698         0x63700,
  16699         SOC_REG_FLAG_64_BITS,
  16700         0,
  16701         8,
  16702         soc_MAC_MERGE_CONFIGr_fields,
  16703         SOC_RESET_VAL_DEC(0x00006848, 0x00000000)
  16704         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16705         -1,
  16706         -1,
  16707     },
  16708 #endif /* chips */
  16709 
  16710 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16711     { /* SOC_REG_INT_XLMAC_MERGE_CTRL_SECRET_CONFIGr */
  16712         soc_block_list[16],
  16713         soc_portreg,
  16714         1,
  16715         0,
  16716         0x63b00,
  16717         SOC_REG_FLAG_64_BITS,
  16718         0,
  16719         3,
  16720         soc_XLMAC_MERGE_CTRL_SECRET_CONFIGr_fields,
  16721         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  16722         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  16723         -1,
  16724         -1,
  16725     },
  16726 #endif /* chips */
  16727 
  16728 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  16729     { /* SOC_REG_INT_XLMAC_MERGE_CTRL_SECRET_CONFIG_BCM56670_A0r */
  16730         soc_block_list[16],
  16731         soc_portreg,
  16732         1,
  16733         0,
  16734         0x63b00,
  16735         SOC_REG_FLAG_64_BITS,
  16736         0,
  16737         3,
  16738         soc_XLMAC_MERGE_CTRL_SECRET_CONFIGr_fields,
  16739         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  16740         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  16741         -1,
  16742         -1,
  16743     },
  16744 #endif /* chips */
  16745 
  16746 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16747     { /* SOC_REG_INT_XLMAC_MERGE_FRG_CNT_CONFIGr */
  16748         soc_block_list[16],
  16749         soc_portreg,
  16750         1,
  16751         0,
  16752         0x63a00,
  16753         SOC_REG_FLAG_64_BITS,
  16754         0,
  16755         4,
  16756         soc_MAC_MERGE_FRG_CNT_CONFIGr_fields,
  16757         SOC_RESET_VAL_DEC(0xb37f4ce6, 0x00000000)
  16758         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16759         -1,
  16760         -1,
  16761     },
  16762 #endif /* chips */
  16763 
  16764 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  16765     { /* SOC_REG_INT_XLMAC_MERGE_FRG_CNT_CONFIG_BCM56670_A0r */
  16766         soc_block_list[16],
  16767         soc_portreg,
  16768         1,
  16769         0,
  16770         0x63a00,
  16771         SOC_REG_FLAG_64_BITS,
  16772         0,
  16773         4,
  16774         soc_MAC_MERGE_FRG_CNT_CONFIGr_fields,
  16775         SOC_RESET_VAL_DEC(0xb37f4ce6, 0x00000000)
  16776         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16777         -1,
  16778         -1,
  16779     },
  16780 #endif /* chips */
  16781 
  16782 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16783     { /* SOC_REG_INT_XLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIGr */
  16784         soc_block_list[16],
  16785         soc_portreg,
  16786         1,
  16787         0,
  16788         0x64000,
  16789         SOC_REG_FLAG_64_BITS,
  16790         0,
  16791         2,
  16792         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIGr_fields,
  16793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16794         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  16795         -1,
  16796         -1,
  16797     },
  16798 #endif /* chips */
  16799 
  16800 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  16801     { /* SOC_REG_INT_XLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG_BCM56670_A0r */
  16802         soc_block_list[16],
  16803         soc_portreg,
  16804         1,
  16805         0,
  16806         0x64000,
  16807         SOC_REG_FLAG_64_BITS,
  16808         0,
  16809         2,
  16810         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIGr_fields,
  16811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16812         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  16813         -1,
  16814         -1,
  16815     },
  16816 #endif /* chips */
  16817 
  16818 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16819     { /* SOC_REG_INT_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0r */
  16820         soc_block_list[16],
  16821         soc_portreg,
  16822         1,
  16823         0,
  16824         0x64100,
  16825         SOC_REG_FLAG_64_BITS |
  16826                           SOC_REG_FLAG_RO,
  16827         0,
  16828         2,
  16829         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0r_fields,
  16830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16831         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  16832         -1,
  16833         -1,
  16834     },
  16835 #endif /* chips */
  16836 
  16837 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16838     { /* SOC_REG_INT_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1r */
  16839         soc_block_list[16],
  16840         soc_portreg,
  16841         1,
  16842         0,
  16843         0x64200,
  16844         SOC_REG_FLAG_64_BITS |
  16845                           SOC_REG_FLAG_RO,
  16846         0,
  16847         2,
  16848         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1r_fields,
  16849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16850         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  16851         -1,
  16852         -1,
  16853     },
  16854 #endif /* chips */
  16855 
  16856 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16857     { /* SOC_REG_INT_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2r */
  16858         soc_block_list[16],
  16859         soc_portreg,
  16860         1,
  16861         0,
  16862         0x64300,
  16863         SOC_REG_FLAG_64_BITS |
  16864                           SOC_REG_FLAG_RO,
  16865         0,
  16866         2,
  16867         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2r_fields,
  16868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16869         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  16870         -1,
  16871         -1,
  16872     },
  16873 #endif /* chips */
  16874 
  16875 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  16876     { /* SOC_REG_INT_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0_BCM56670_A0r */
  16877         soc_block_list[16],
  16878         soc_portreg,
  16879         1,
  16880         0,
  16881         0x64100,
  16882         SOC_REG_FLAG_64_BITS |
  16883                           SOC_REG_FLAG_RO,
  16884         0,
  16885         2,
  16886         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0r_fields,
  16887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  16889         -1,
  16890         -1,
  16891     },
  16892 #endif /* chips */
  16893 
  16894 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  16895     { /* SOC_REG_INT_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1_BCM56670_A0r */
  16896         soc_block_list[16],
  16897         soc_portreg,
  16898         1,
  16899         0,
  16900         0x64200,
  16901         SOC_REG_FLAG_64_BITS |
  16902                           SOC_REG_FLAG_RO,
  16903         0,
  16904         2,
  16905         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1r_fields,
  16906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16907         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  16908         -1,
  16909         -1,
  16910     },
  16911 #endif /* chips */
  16912 
  16913 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  16914     { /* SOC_REG_INT_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2_BCM56670_A0r */
  16915         soc_block_list[16],
  16916         soc_portreg,
  16917         1,
  16918         0,
  16919         0x64300,
  16920         SOC_REG_FLAG_64_BITS |
  16921                           SOC_REG_FLAG_RO,
  16922         0,
  16923         2,
  16924         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2r_fields,
  16925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16926         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  16927         -1,
  16928         -1,
  16929     },
  16930 #endif /* chips */
  16931 
  16932 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16933     { /* SOC_REG_INT_XLMAC_MERGE_RX_TIMEOUT_CONFIGr */
  16934         soc_block_list[16],
  16935         soc_portreg,
  16936         1,
  16937         0,
  16938         0x63c00,
  16939         SOC_REG_FLAG_64_BITS,
  16940         0,
  16941         2,
  16942         soc_MAC_MERGE_RX_TIMEOUT_CONFIGr_fields,
  16943         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  16944         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  16945         -1,
  16946         -1,
  16947     },
  16948 #endif /* chips */
  16949 
  16950 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  16951     { /* SOC_REG_INT_XLMAC_MERGE_RX_TIMEOUT_CONFIG_BCM56670_A0r */
  16952         soc_block_list[16],
  16953         soc_portreg,
  16954         1,
  16955         0,
  16956         0x63c00,
  16957         SOC_REG_FLAG_64_BITS,
  16958         0,
  16959         2,
  16960         soc_MAC_MERGE_RX_TIMEOUT_CONFIGr_fields,
  16961         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  16962         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  16963         -1,
  16964         -1,
  16965     },
  16966 #endif /* chips */
  16967 
  16968 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16969     { /* SOC_REG_INT_XLMAC_MERGE_SMD_CONFIG_0r */
  16970         soc_block_list[16],
  16971         soc_portreg,
  16972         1,
  16973         0,
  16974         0x63800,
  16975         SOC_REG_FLAG_64_BITS,
  16976         0,
  16977         8,
  16978         soc_XLMAC_MERGE_SMD_CONFIG_0r_fields,
  16979         SOC_RESET_VAL_DEC(0xb37f4ce6, 0x2a9e5261)
  16980         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  16981         -1,
  16982         -1,
  16983     },
  16984 #endif /* chips */
  16985 
  16986 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  16987     { /* SOC_REG_INT_XLMAC_MERGE_SMD_CONFIG_1r */
  16988         soc_block_list[16],
  16989         soc_portreg,
  16990         1,
  16991         0,
  16992         0x63900,
  16993         SOC_REG_FLAG_64_BITS,
  16994         0,
  16995         2,
  16996         soc_MAC_MERGE_SMD_CONFIG_2r_fields,
  16997         SOC_RESET_VAL_DEC(0x00001907, 0x00000000)
  16998         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  16999         -1,
  17000         -1,
  17001     },
  17002 #endif /* chips */
  17003 
  17004 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17005     { /* SOC_REG_INT_XLMAC_MERGE_SMD_CONFIG_0_BCM56670_A0r */
  17006         soc_block_list[16],
  17007         soc_portreg,
  17008         1,
  17009         0,
  17010         0x63800,
  17011         SOC_REG_FLAG_64_BITS,
  17012         0,
  17013         8,
  17014         soc_XLMAC_MERGE_SMD_CONFIG_0r_fields,
  17015         SOC_RESET_VAL_DEC(0xb37f4ce6, 0x2a9e5261)
  17016         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  17017         -1,
  17018         -1,
  17019     },
  17020 #endif /* chips */
  17021 
  17022 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17023     { /* SOC_REG_INT_XLMAC_MERGE_SMD_CONFIG_1_BCM56670_A0r */
  17024         soc_block_list[16],
  17025         soc_portreg,
  17026         1,
  17027         0,
  17028         0x63900,
  17029         SOC_REG_FLAG_64_BITS,
  17030         0,
  17031         2,
  17032         soc_MAC_MERGE_SMD_CONFIG_2r_fields,
  17033         SOC_RESET_VAL_DEC(0x00001907, 0x00000000)
  17034         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  17035         -1,
  17036         -1,
  17037     },
  17038 #endif /* chips */
  17039 
  17040 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17041     { /* SOC_REG_INT_XLMAC_MERGE_STATUSr */
  17042         soc_block_list[16],
  17043         soc_portreg,
  17044         1,
  17045         0,
  17046         0x63e00,
  17047         SOC_REG_FLAG_64_BITS |
  17048                           SOC_REG_FLAG_RO,
  17049         0,
  17050         2,
  17051         soc_MAC_MERGE_STATUSr_fields,
  17052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17053         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  17054         -1,
  17055         -1,
  17056     },
  17057 #endif /* chips */
  17058 
  17059 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17060     { /* SOC_REG_INT_XLMAC_MERGE_STATUS_BCM56670_A0r */
  17061         soc_block_list[16],
  17062         soc_portreg,
  17063         1,
  17064         0,
  17065         0x63e00,
  17066         SOC_REG_FLAG_64_BITS |
  17067                           SOC_REG_FLAG_RO,
  17068         0,
  17069         2,
  17070         soc_MAC_MERGE_STATUSr_fields,
  17071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17072         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  17073         -1,
  17074         -1,
  17075     },
  17076 #endif /* chips */
  17077 
  17078 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17079     { /* SOC_REG_INT_XLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIGr */
  17080         soc_block_list[16],
  17081         soc_portreg,
  17082         1,
  17083         0,
  17084         0x64400,
  17085         SOC_REG_FLAG_64_BITS,
  17086         0,
  17087         2,
  17088         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIGr_fields,
  17089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17090         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  17091         -1,
  17092         -1,
  17093     },
  17094 #endif /* chips */
  17095 
  17096 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17097     { /* SOC_REG_INT_XLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG_BCM56670_A0r */
  17098         soc_block_list[16],
  17099         soc_portreg,
  17100         1,
  17101         0,
  17102         0x64400,
  17103         SOC_REG_FLAG_64_BITS,
  17104         0,
  17105         2,
  17106         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIGr_fields,
  17107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17108         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  17109         -1,
  17110         -1,
  17111     },
  17112 #endif /* chips */
  17113 
  17114 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17115     { /* SOC_REG_INT_XLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0r */
  17116         soc_block_list[16],
  17117         soc_portreg,
  17118         1,
  17119         0,
  17120         0x64500,
  17121         SOC_REG_FLAG_64_BITS |
  17122                           SOC_REG_FLAG_RO,
  17123         0,
  17124         2,
  17125         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0r_fields,
  17126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17127         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  17128         -1,
  17129         -1,
  17130     },
  17131 #endif /* chips */
  17132 
  17133 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17134     { /* SOC_REG_INT_XLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1r */
  17135         soc_block_list[16],
  17136         soc_portreg,
  17137         1,
  17138         0,
  17139         0x64600,
  17140         SOC_REG_FLAG_64_BITS |
  17141                           SOC_REG_FLAG_RO,
  17142         0,
  17143         2,
  17144         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1r_fields,
  17145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17146         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  17147         -1,
  17148         -1,
  17149     },
  17150 #endif /* chips */
  17151 
  17152 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17153     { /* SOC_REG_INT_XLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2r */
  17154         soc_block_list[16],
  17155         soc_portreg,
  17156         1,
  17157         0,
  17158         0x64700,
  17159         SOC_REG_FLAG_64_BITS |
  17160                           SOC_REG_FLAG_RO,
  17161         0,
  17162         2,
  17163         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2r_fields,
  17164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17165         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  17166         -1,
  17167         -1,
  17168     },
  17169 #endif /* chips */
  17170 
  17171 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17172     { /* SOC_REG_INT_XLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0_BCM56670_A0r */
  17173         soc_block_list[16],
  17174         soc_portreg,
  17175         1,
  17176         0,
  17177         0x64500,
  17178         SOC_REG_FLAG_64_BITS |
  17179                           SOC_REG_FLAG_RO,
  17180         0,
  17181         2,
  17182         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0r_fields,
  17183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17184         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  17185         -1,
  17186         -1,
  17187     },
  17188 #endif /* chips */
  17189 
  17190 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17191     { /* SOC_REG_INT_XLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1_BCM56670_A0r */
  17192         soc_block_list[16],
  17193         soc_portreg,
  17194         1,
  17195         0,
  17196         0x64600,
  17197         SOC_REG_FLAG_64_BITS |
  17198                           SOC_REG_FLAG_RO,
  17199         0,
  17200         2,
  17201         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1r_fields,
  17202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17203         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  17204         -1,
  17205         -1,
  17206     },
  17207 #endif /* chips */
  17208 
  17209 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17210     { /* SOC_REG_INT_XLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2_BCM56670_A0r */
  17211         soc_block_list[16],
  17212         soc_portreg,
  17213         1,
  17214         0,
  17215         0x64700,
  17216         SOC_REG_FLAG_64_BITS |
  17217                           SOC_REG_FLAG_RO,
  17218         0,
  17219         2,
  17220         soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2r_fields,
  17221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17222         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  17223         -1,
  17224         -1,
  17225     },
  17226 #endif /* chips */
  17227 
  17228 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17229     { /* SOC_REG_INT_XLMAC_MERGE_VERIFY_STATEr */
  17230         soc_block_list[16],
  17231         soc_portreg,
  17232         1,
  17233         0,
  17234         0x63d00,
  17235         SOC_REG_FLAG_64_BITS |
  17236                           SOC_REG_FLAG_RO,
  17237         0,
  17238         3,
  17239         soc_MAC_MERGE_VERIFY_STATEr_fields,
  17240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17241         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  17242         -1,
  17243         -1,
  17244     },
  17245 #endif /* chips */
  17246 
  17247 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17248     { /* SOC_REG_INT_XLMAC_MERGE_VERIFY_STATE_BCM56670_A0r */
  17249         soc_block_list[16],
  17250         soc_portreg,
  17251         1,
  17252         0,
  17253         0x63d00,
  17254         SOC_REG_FLAG_64_BITS |
  17255                           SOC_REG_FLAG_RO,
  17256         0,
  17257         3,
  17258         soc_MAC_MERGE_VERIFY_STATEr_fields,
  17259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17260         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  17261         -1,
  17262         -1,
  17263     },
  17264 #endif /* chips */
  17265 
  17266 #if defined(BCM_2801PM_A0)
  17267     { /* SOC_REG_INT_XLMAC_MODEr */
  17268         soc_block_list[56],
  17269         soc_portreg,
  17270         1,
  17271         0,
  17272         0x60100,
  17273         0,
  17274         0,
  17275         3,
  17276         soc_CLMAC_MODEr_fields,
  17277         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17278         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17279         -1,
  17280         -1,
  17281     },
  17282 #endif /* chips */
  17283 
  17284 #if defined(BCM_53400_A0)
  17285     { /* SOC_REG_INT_XLMAC_MODE_BCM53400_A0r */
  17286         soc_block_list[16],
  17287         soc_portreg,
  17288         1,
  17289         0,
  17290         0x60100,
  17291         SOC_REG_FLAG_64_BITS,
  17292         0,
  17293         3,
  17294         soc_CLMAC_MODEr_fields,
  17295         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17296         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17297         -1,
  17298         -1,
  17299     },
  17300 #endif /* chips */
  17301 
  17302 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17303     { /* SOC_REG_INT_XLMAC_MODE_BCM53570_A0r */
  17304         soc_block_list[16],
  17305         soc_portreg,
  17306         1,
  17307         0,
  17308         0x60200,
  17309         SOC_REG_FLAG_64_BITS,
  17310         0,
  17311         3,
  17312         soc_CLMAC_MODEr_fields,
  17313         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17314         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17315         -1,
  17316         -1,
  17317     },
  17318 #endif /* chips */
  17319 
  17320 #if defined(BCM_56150_A0)
  17321     { /* SOC_REG_INT_XLMAC_MODE_BCM56150_A0r */
  17322         soc_block_list[16],
  17323         soc_portreg,
  17324         1,
  17325         0,
  17326         0x60100,
  17327         SOC_REG_FLAG_64_BITS,
  17328         0,
  17329         3,
  17330         soc_CMAC_MODEr_fields,
  17331         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17332         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17333         -1,
  17334         -1,
  17335     },
  17336 #endif /* chips */
  17337 
  17338 #if defined(BCM_56160_A0)
  17339     { /* SOC_REG_INT_XLMAC_MODE_BCM56160_A0r */
  17340         soc_block_list[16],
  17341         soc_portreg,
  17342         1,
  17343         0,
  17344         0x60100,
  17345         SOC_REG_FLAG_64_BITS,
  17346         0,
  17347         3,
  17348         soc_CLMAC_MODEr_fields,
  17349         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17350         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17351         -1,
  17352         -1,
  17353     },
  17354 #endif /* chips */
  17355 
  17356 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  17357     { /* SOC_REG_INT_XLMAC_MODE_BCM56260_A0r */
  17358         soc_block_list[220],
  17359         soc_portreg,
  17360         1,
  17361         0,
  17362         0x60100,
  17363         SOC_REG_FLAG_64_BITS,
  17364         0,
  17365         3,
  17366         soc_CLMAC_MODEr_fields,
  17367         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17368         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17369         -1,
  17370         -1,
  17371     },
  17372 #endif /* chips */
  17373 
  17374 #if defined(BCM_56270_A0)
  17375     { /* SOC_REG_INT_XLMAC_MODE_BCM56270_A0r */
  17376         soc_block_list[220],
  17377         soc_portreg,
  17378         1,
  17379         0,
  17380         0x60100,
  17381         SOC_REG_FLAG_64_BITS,
  17382         0,
  17383         3,
  17384         soc_CLMAC_MODEr_fields,
  17385         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17386         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17387         -1,
  17388         -1,
  17389     },
  17390 #endif /* chips */
  17391 
  17392 #if defined(BCM_56370_A0)
  17393     { /* SOC_REG_INT_XLMAC_MODE_BCM56370_A0r */
  17394         soc_block_list[16],
  17395         soc_portreg,
  17396         1,
  17397         0,
  17398         0x60100,
  17399         SOC_REG_FLAG_64_BITS,
  17400         0,
  17401         3,
  17402         soc_CLMAC_MODEr_fields,
  17403         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17404         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17405         -1,
  17406         -1,
  17407         3,
  17408     },
  17409 #endif /* chips */
  17410 
  17411 #if defined(BCM_56560_A0)
  17412     { /* SOC_REG_INT_XLMAC_MODE_BCM56560_A0r */
  17413         soc_block_list[16],
  17414         soc_portreg,
  17415         1,
  17416         0,
  17417         0x60100,
  17418         SOC_REG_FLAG_64_BITS,
  17419         0,
  17420         3,
  17421         soc_CLMAC_MODEr_fields,
  17422         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17423         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17424         -1,
  17425         -1,
  17426     },
  17427 #endif /* chips */
  17428 
  17429 #if defined(BCM_56560_B0)
  17430     { /* SOC_REG_INT_XLMAC_MODE_BCM56560_B0r */
  17431         soc_block_list[16],
  17432         soc_portreg,
  17433         1,
  17434         0,
  17435         0x60100,
  17436         SOC_REG_FLAG_64_BITS,
  17437         0,
  17438         3,
  17439         soc_CLMAC_MODEr_fields,
  17440         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17441         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17442         -1,
  17443         -1,
  17444     },
  17445 #endif /* chips */
  17446 
  17447 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17448     { /* SOC_REG_INT_XLMAC_MODE_BCM56670_A0r */
  17449         soc_block_list[16],
  17450         soc_portreg,
  17451         1,
  17452         0,
  17453         0x60200,
  17454         SOC_REG_FLAG_64_BITS,
  17455         0,
  17456         3,
  17457         soc_CLMAC_MODEr_fields,
  17458         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17459         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17460         -1,
  17461         -1,
  17462     },
  17463 #endif /* chips */
  17464 
  17465 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  17466     { /* SOC_REG_INT_XLMAC_MODE_BCM56850_A0r */
  17467         soc_block_list[16],
  17468         soc_portreg,
  17469         1,
  17470         0,
  17471         0x60100,
  17472         SOC_REG_FLAG_64_BITS,
  17473         0,
  17474         3,
  17475         soc_CMAC_MODEr_fields,
  17476         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17477         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17478         -1,
  17479         -1,
  17480     },
  17481 #endif /* chips */
  17482 
  17483 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  17484     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  17485     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  17486     defined(BCM_56980_B0)
  17487     { /* SOC_REG_INT_XLMAC_MODE_BCM56960_A0r */
  17488         soc_block_list[16],
  17489         soc_portreg,
  17490         1,
  17491         0,
  17492         0x60100,
  17493         SOC_REG_FLAG_64_BITS,
  17494         0,
  17495         3,
  17496         soc_CLMAC_MODEr_fields,
  17497         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17498         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17499         -1,
  17500         -1,
  17501         3,
  17502     },
  17503 #endif /* chips */
  17504 
  17505 #if defined(BCM_88270_A0)
  17506     { /* SOC_REG_INT_XLMAC_MODE_BCM88270_A0r */
  17507         soc_block_list[221],
  17508         soc_portreg,
  17509         1,
  17510         0,
  17511         0x60100,
  17512         SOC_REG_FLAG_64_BITS,
  17513         0,
  17514         3,
  17515         soc_XLMAC_MODE_BCM88270_A0r_fields,
  17516         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17517         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17518         -1,
  17519         -1,
  17520     },
  17521 #endif /* chips */
  17522 
  17523 #if defined(BCM_88375_A0)
  17524     { /* SOC_REG_INT_XLMAC_MODE_BCM88375_A0r */
  17525         soc_block_list[56],
  17526         soc_portreg,
  17527         1,
  17528         0,
  17529         0x60100,
  17530         SOC_REG_FLAG_64_BITS,
  17531         0,
  17532         3,
  17533         soc_XLMAC_MODE_BCM88375_A0r_fields,
  17534         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17535         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17536         -1,
  17537         -1,
  17538     },
  17539 #endif /* chips */
  17540 
  17541 #if defined(BCM_88375_B0)
  17542     { /* SOC_REG_INT_XLMAC_MODE_BCM88375_B0r */
  17543         soc_block_list[56],
  17544         soc_portreg,
  17545         1,
  17546         0,
  17547         0x60100,
  17548         SOC_REG_FLAG_64_BITS,
  17549         0,
  17550         3,
  17551         soc_XLMAC_MODE_BCM88375_B0r_fields,
  17552         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17553         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17554         -1,
  17555         -1,
  17556     },
  17557 #endif /* chips */
  17558 
  17559 #if defined(BCM_88470_A0)
  17560     { /* SOC_REG_INT_XLMAC_MODE_BCM88470_A0r */
  17561         soc_block_list[56],
  17562         soc_portreg,
  17563         1,
  17564         0,
  17565         0x60100,
  17566         SOC_REG_FLAG_64_BITS,
  17567         0,
  17568         3,
  17569         soc_XLMAC_MODE_BCM88470_A0r_fields,
  17570         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17571         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17572         -1,
  17573         -1,
  17574     },
  17575 #endif /* chips */
  17576 
  17577 #if defined(BCM_88470_B0)
  17578     { /* SOC_REG_INT_XLMAC_MODE_BCM88470_B0r */
  17579         soc_block_list[56],
  17580         soc_portreg,
  17581         1,
  17582         0,
  17583         0x60100,
  17584         SOC_REG_FLAG_64_BITS,
  17585         0,
  17586         3,
  17587         soc_XLMAC_MODE_BCM88470_B0r_fields,
  17588         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17589         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17590         -1,
  17591         -1,
  17592     },
  17593 #endif /* chips */
  17594 
  17595 #if defined(BCM_88675_A0)
  17596     { /* SOC_REG_INT_XLMAC_MODE_BCM88675_A0r */
  17597         soc_block_list[56],
  17598         soc_portreg,
  17599         1,
  17600         0,
  17601         0x60100,
  17602         SOC_REG_FLAG_64_BITS,
  17603         0,
  17604         3,
  17605         soc_XLMAC_MODEr_fields,
  17606         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17607         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17608         -1,
  17609         -1,
  17610     },
  17611 #endif /* chips */
  17612 
  17613 #if defined(BCM_88675_B0)
  17614     { /* SOC_REG_INT_XLMAC_MODE_BCM88675_B0r */
  17615         soc_block_list[56],
  17616         soc_portreg,
  17617         1,
  17618         0,
  17619         0x60100,
  17620         SOC_REG_FLAG_64_BITS,
  17621         0,
  17622         3,
  17623         soc_XLMAC_MODE_BCM88675_B0r_fields,
  17624         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17625         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17626         -1,
  17627         -1,
  17628     },
  17629 #endif /* chips */
  17630 
  17631 #if defined(BCM_88680_A0)
  17632     { /* SOC_REG_INT_XLMAC_MODE_BCM88680_A0r */
  17633         soc_block_list[56],
  17634         soc_portreg,
  17635         1,
  17636         0,
  17637         0x60100,
  17638         SOC_REG_FLAG_64_BITS,
  17639         0,
  17640         3,
  17641         soc_XLMAC_MODE_BCM88680_A0r_fields,
  17642         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  17643         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17644         -1,
  17645         -1,
  17646     },
  17647 #endif /* chips */
  17648 
  17649 #if defined(BCM_2801PM_A0)
  17650     { /* SOC_REG_INT_XLMAC_PAUSE_CTRLr */
  17651         soc_block_list[56],
  17652         soc_portreg,
  17653         1,
  17654         0,
  17655         0x60d00,
  17656         SOC_REG_FLAG_64_BITS,
  17657         0,
  17658         7,
  17659         soc_CLMAC_PAUSE_CTRLr_fields,
  17660         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  17661         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17662         -1,
  17663         -1,
  17664     },
  17665 #endif /* chips */
  17666 
  17667 #if defined(BCM_53400_A0)
  17668     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM53400_A0r */
  17669         soc_block_list[16],
  17670         soc_portreg,
  17671         1,
  17672         0,
  17673         0x60d00,
  17674         SOC_REG_FLAG_64_BITS,
  17675         0,
  17676         9,
  17677         soc_XLMAC_PAUSE_CTRL_BCM53400_A0r_fields,
  17678         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  17679         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17680         -1,
  17681         -1,
  17682     },
  17683 #endif /* chips */
  17684 
  17685 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17686     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM53570_A0r */
  17687         soc_block_list[16],
  17688         soc_portreg,
  17689         1,
  17690         0,
  17691         0x60c00,
  17692         SOC_REG_FLAG_64_BITS,
  17693         0,
  17694         9,
  17695         soc_XLMAC_B0_PAUSE_CTRLr_fields,
  17696         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  17697         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17698         -1,
  17699         -1,
  17700     },
  17701 #endif /* chips */
  17702 
  17703 #if defined(BCM_56150_A0)
  17704     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56150_A0r */
  17705         soc_block_list[16],
  17706         soc_portreg,
  17707         1,
  17708         0,
  17709         0x60d00,
  17710         SOC_REG_FLAG_64_BITS,
  17711         0,
  17712         9,
  17713         soc_XLMAC_PAUSE_CTRL_BCM56850_A0r_fields,
  17714         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  17715         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17716         -1,
  17717         -1,
  17718     },
  17719 #endif /* chips */
  17720 
  17721 #if defined(BCM_56160_A0)
  17722     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56160_A0r */
  17723         soc_block_list[16],
  17724         soc_portreg,
  17725         1,
  17726         0,
  17727         0x60d00,
  17728         SOC_REG_FLAG_64_BITS,
  17729         0,
  17730         9,
  17731         soc_XLMAC_B0_PAUSE_CTRLr_fields,
  17732         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  17733         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17734         -1,
  17735         -1,
  17736     },
  17737 #endif /* chips */
  17738 
  17739 #if defined(BCM_56260_A0)
  17740     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56260_A0r */
  17741         soc_block_list[220],
  17742         soc_portreg,
  17743         1,
  17744         0,
  17745         0x60d00,
  17746         SOC_REG_FLAG_64_BITS,
  17747         0,
  17748         9,
  17749         soc_XLMAC_PAUSE_CTRL_BCM53400_A0r_fields,
  17750         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  17751         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17752         -1,
  17753         -1,
  17754     },
  17755 #endif /* chips */
  17756 
  17757 #if defined(BCM_56260_B0)
  17758     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56260_B0r */
  17759         soc_block_list[220],
  17760         soc_portreg,
  17761         1,
  17762         0,
  17763         0x60d00,
  17764         SOC_REG_FLAG_64_BITS,
  17765         0,
  17766         9,
  17767         soc_XLMAC_B0_PAUSE_CTRLr_fields,
  17768         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  17769         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17770         -1,
  17771         -1,
  17772     },
  17773 #endif /* chips */
  17774 
  17775 #if defined(BCM_56270_A0)
  17776     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56270_A0r */
  17777         soc_block_list[220],
  17778         soc_portreg,
  17779         1,
  17780         0,
  17781         0x60d00,
  17782         SOC_REG_FLAG_64_BITS,
  17783         0,
  17784         9,
  17785         soc_XLMAC_B0_PAUSE_CTRLr_fields,
  17786         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  17787         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17788         -1,
  17789         -1,
  17790     },
  17791 #endif /* chips */
  17792 
  17793 #if defined(BCM_56370_A0)
  17794     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56370_A0r */
  17795         soc_block_list[16],
  17796         soc_portreg,
  17797         1,
  17798         0,
  17799         0x60d00,
  17800         SOC_REG_FLAG_64_BITS,
  17801         0,
  17802         9,
  17803         soc_XLMAC_B0_PAUSE_CTRLr_fields,
  17804         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  17805         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17806         -1,
  17807         -1,
  17808         3,
  17809     },
  17810 #endif /* chips */
  17811 
  17812 #if defined(BCM_56560_A0)
  17813     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56560_A0r */
  17814         soc_block_list[16],
  17815         soc_portreg,
  17816         1,
  17817         0,
  17818         0x60d00,
  17819         SOC_REG_FLAG_64_BITS,
  17820         0,
  17821         9,
  17822         soc_XLMAC_PAUSE_CTRL_BCM53400_A0r_fields,
  17823         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  17824         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17825         -1,
  17826         -1,
  17827     },
  17828 #endif /* chips */
  17829 
  17830 #if defined(BCM_56560_B0)
  17831     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56560_B0r */
  17832         soc_block_list[16],
  17833         soc_portreg,
  17834         1,
  17835         0,
  17836         0x60d00,
  17837         SOC_REG_FLAG_64_BITS,
  17838         0,
  17839         9,
  17840         soc_XLMAC_B0_PAUSE_CTRLr_fields,
  17841         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  17842         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17843         -1,
  17844         -1,
  17845     },
  17846 #endif /* chips */
  17847 
  17848 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17849     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56670_A0r */
  17850         soc_block_list[16],
  17851         soc_portreg,
  17852         1,
  17853         0,
  17854         0x60c00,
  17855         SOC_REG_FLAG_64_BITS,
  17856         0,
  17857         9,
  17858         soc_XLMAC_B0_PAUSE_CTRLr_fields,
  17859         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  17860         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17861         -1,
  17862         -1,
  17863     },
  17864 #endif /* chips */
  17865 
  17866 #if defined(BCM_56850_A0)
  17867     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56850_A0r */
  17868         soc_block_list[16],
  17869         soc_portreg,
  17870         1,
  17871         0,
  17872         0x60d00,
  17873         SOC_REG_FLAG_64_BITS,
  17874         0,
  17875         9,
  17876         soc_XLMAC_PAUSE_CTRL_BCM56850_A0r_fields,
  17877         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  17878         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17879         -1,
  17880         -1,
  17881     },
  17882 #endif /* chips */
  17883 
  17884 #if defined(BCM_56860_A0)
  17885     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56860_A0r */
  17886         soc_block_list[16],
  17887         soc_portreg,
  17888         1,
  17889         0,
  17890         0x60d00,
  17891         SOC_REG_FLAG_64_BITS,
  17892         0,
  17893         9,
  17894         soc_XLMAC_PAUSE_CTRL_BCM56860_A0r_fields,
  17895         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  17896         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17897         -1,
  17898         -1,
  17899     },
  17900 #endif /* chips */
  17901 
  17902 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17903     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56960_A0r */
  17904         soc_block_list[16],
  17905         soc_portreg,
  17906         1,
  17907         0,
  17908         0x60d00,
  17909         SOC_REG_FLAG_64_BITS,
  17910         0,
  17911         9,
  17912         soc_XLMAC_PAUSE_CTRL_BCM53400_A0r_fields,
  17913         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  17914         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17915         -1,
  17916         -1,
  17917         3,
  17918     },
  17919 #endif /* chips */
  17920 
  17921 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  17922     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  17923     defined(BCM_56980_B0)
  17924     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM56970_A0r */
  17925         soc_block_list[16],
  17926         soc_portreg,
  17927         1,
  17928         0,
  17929         0x60d00,
  17930         SOC_REG_FLAG_64_BITS,
  17931         0,
  17932         9,
  17933         soc_XLMAC_B0_PAUSE_CTRLr_fields,
  17934         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  17935         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17936         -1,
  17937         -1,
  17938         3,
  17939     },
  17940 #endif /* chips */
  17941 
  17942 #if defined(BCM_88270_A0)
  17943     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM88270_A0r */
  17944         soc_block_list[221],
  17945         soc_portreg,
  17946         1,
  17947         0,
  17948         0x60d00,
  17949         SOC_REG_FLAG_64_BITS,
  17950         0,
  17951         7,
  17952         soc_XLMAC_PAUSE_CTRL_BCM88270_A0r_fields,
  17953         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  17954         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17955         -1,
  17956         -1,
  17957     },
  17958 #endif /* chips */
  17959 
  17960 #if defined(BCM_88375_A0)
  17961     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM88375_A0r */
  17962         soc_block_list[56],
  17963         soc_portreg,
  17964         1,
  17965         0,
  17966         0x60d00,
  17967         SOC_REG_FLAG_64_BITS,
  17968         0,
  17969         7,
  17970         soc_XLMAC_PAUSE_CTRL_BCM88375_A0r_fields,
  17971         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  17972         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17973         -1,
  17974         -1,
  17975     },
  17976 #endif /* chips */
  17977 
  17978 #if defined(BCM_88375_B0)
  17979     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM88375_B0r */
  17980         soc_block_list[56],
  17981         soc_portreg,
  17982         1,
  17983         0,
  17984         0x60d00,
  17985         SOC_REG_FLAG_64_BITS,
  17986         0,
  17987         7,
  17988         soc_XLMAC_PAUSE_CTRL_BCM88375_B0r_fields,
  17989         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  17990         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  17991         -1,
  17992         -1,
  17993     },
  17994 #endif /* chips */
  17995 
  17996 #if defined(BCM_88470_A0)
  17997     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM88470_A0r */
  17998         soc_block_list[56],
  17999         soc_portreg,
  18000         1,
  18001         0,
  18002         0x60d00,
  18003         SOC_REG_FLAG_64_BITS,
  18004         0,
  18005         7,
  18006         soc_XLMAC_PAUSE_CTRL_BCM88470_A0r_fields,
  18007         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  18008         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  18009         -1,
  18010         -1,
  18011     },
  18012 #endif /* chips */
  18013 
  18014 #if defined(BCM_88470_B0)
  18015     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM88470_B0r */
  18016         soc_block_list[56],
  18017         soc_portreg,
  18018         1,
  18019         0,
  18020         0x60d00,
  18021         SOC_REG_FLAG_64_BITS,
  18022         0,
  18023         7,
  18024         soc_XLMAC_PAUSE_CTRL_BCM88470_B0r_fields,
  18025         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  18026         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  18027         -1,
  18028         -1,
  18029     },
  18030 #endif /* chips */
  18031 
  18032 #if defined(BCM_88675_A0)
  18033     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM88675_A0r */
  18034         soc_block_list[56],
  18035         soc_portreg,
  18036         1,
  18037         0,
  18038         0x60d00,
  18039         SOC_REG_FLAG_64_BITS,
  18040         0,
  18041         7,
  18042         soc_XLMAC_PAUSE_CTRLr_fields,
  18043         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  18044         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  18045         -1,
  18046         -1,
  18047     },
  18048 #endif /* chips */
  18049 
  18050 #if defined(BCM_88675_B0)
  18051     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM88675_B0r */
  18052         soc_block_list[56],
  18053         soc_portreg,
  18054         1,
  18055         0,
  18056         0x60d00,
  18057         SOC_REG_FLAG_64_BITS,
  18058         0,
  18059         7,
  18060         soc_XLMAC_PAUSE_CTRL_BCM88675_B0r_fields,
  18061         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  18062         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  18063         -1,
  18064         -1,
  18065     },
  18066 #endif /* chips */
  18067 
  18068 #if defined(BCM_88680_A0)
  18069     { /* SOC_REG_INT_XLMAC_PAUSE_CTRL_BCM88680_A0r */
  18070         soc_block_list[56],
  18071         soc_portreg,
  18072         1,
  18073         0,
  18074         0x60d00,
  18075         SOC_REG_FLAG_64_BITS,
  18076         0,
  18077         7,
  18078         soc_XLMAC_PAUSE_CTRL_BCM88680_A0r_fields,
  18079         SOC_RESET_VAL_DEC(0xffe1c000, 0x0000001f)
  18080         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  18081         -1,
  18082         -1,
  18083     },
  18084 #endif /* chips */
  18085 
  18086 #if defined(BCM_2801PM_A0)
  18087     { /* SOC_REG_INT_XLMAC_PFC_CTRLr */
  18088         soc_block_list[56],
  18089         soc_portreg,
  18090         1,
  18091         0,
  18092         0x60e00,
  18093         SOC_REG_FLAG_64_BITS,
  18094         0,
  18095         8,
  18096         soc_CLMAC_PFC_CTRLr_fields,
  18097         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18098         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18099         -1,
  18100         -1,
  18101     },
  18102 #endif /* chips */
  18103 
  18104 #if defined(BCM_53400_A0)
  18105     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM53400_A0r */
  18106         soc_block_list[16],
  18107         soc_portreg,
  18108         1,
  18109         0,
  18110         0x60e00,
  18111         SOC_REG_FLAG_64_BITS,
  18112         0,
  18113         8,
  18114         soc_CLMAC_PFC_CTRLr_fields,
  18115         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18116         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18117         -1,
  18118         -1,
  18119     },
  18120 #endif /* chips */
  18121 
  18122 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  18123     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM53570_A0r */
  18124         soc_block_list[16],
  18125         soc_portreg,
  18126         1,
  18127         0,
  18128         0x60d00,
  18129         SOC_REG_FLAG_64_BITS,
  18130         0,
  18131         10,
  18132         soc_CLG2MAC_PFC_CTRLr_fields,
  18133         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18134         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18135         -1,
  18136         -1,
  18137     },
  18138 #endif /* chips */
  18139 
  18140 #if defined(BCM_56150_A0)
  18141     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM56150_A0r */
  18142         soc_block_list[16],
  18143         soc_portreg,
  18144         1,
  18145         0,
  18146         0x60e00,
  18147         SOC_REG_FLAG_64_BITS,
  18148         0,
  18149         8,
  18150         soc_XLMAC_PFC_CTRL_BCM56850_A0r_fields,
  18151         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18152         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18153         -1,
  18154         -1,
  18155     },
  18156 #endif /* chips */
  18157 
  18158 #if defined(BCM_56160_A0)
  18159     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM56160_A0r */
  18160         soc_block_list[16],
  18161         soc_portreg,
  18162         1,
  18163         0,
  18164         0x60e00,
  18165         SOC_REG_FLAG_64_BITS,
  18166         0,
  18167         8,
  18168         soc_CLMAC_PFC_CTRLr_fields,
  18169         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18170         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18171         -1,
  18172         -1,
  18173     },
  18174 #endif /* chips */
  18175 
  18176 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  18177     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM56260_A0r */
  18178         soc_block_list[220],
  18179         soc_portreg,
  18180         1,
  18181         0,
  18182         0x60e00,
  18183         SOC_REG_FLAG_64_BITS,
  18184         0,
  18185         8,
  18186         soc_CLMAC_PFC_CTRLr_fields,
  18187         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18188         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18189         -1,
  18190         -1,
  18191     },
  18192 #endif /* chips */
  18193 
  18194 #if defined(BCM_56270_A0)
  18195     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM56270_A0r */
  18196         soc_block_list[220],
  18197         soc_portreg,
  18198         1,
  18199         0,
  18200         0x60e00,
  18201         SOC_REG_FLAG_64_BITS,
  18202         0,
  18203         8,
  18204         soc_CLMAC_PFC_CTRLr_fields,
  18205         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18206         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18207         -1,
  18208         -1,
  18209     },
  18210 #endif /* chips */
  18211 
  18212 #if defined(BCM_56370_A0)
  18213     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM56370_A0r */
  18214         soc_block_list[16],
  18215         soc_portreg,
  18216         1,
  18217         0,
  18218         0x60e00,
  18219         SOC_REG_FLAG_64_BITS,
  18220         0,
  18221         10,
  18222         soc_CLG2MAC_PFC_CTRLr_fields,
  18223         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18224         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18225         -1,
  18226         -1,
  18227         3,
  18228     },
  18229 #endif /* chips */
  18230 
  18231 #if defined(BCM_56560_A0)
  18232     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM56560_A0r */
  18233         soc_block_list[16],
  18234         soc_portreg,
  18235         1,
  18236         0,
  18237         0x60e00,
  18238         SOC_REG_FLAG_64_BITS,
  18239         0,
  18240         8,
  18241         soc_CLMAC_PFC_CTRLr_fields,
  18242         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18243         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18244         -1,
  18245         -1,
  18246     },
  18247 #endif /* chips */
  18248 
  18249 #if defined(BCM_56560_B0)
  18250     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM56560_B0r */
  18251         soc_block_list[16],
  18252         soc_portreg,
  18253         1,
  18254         0,
  18255         0x60e00,
  18256         SOC_REG_FLAG_64_BITS,
  18257         0,
  18258         8,
  18259         soc_CLMAC_PFC_CTRLr_fields,
  18260         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18261         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18262         -1,
  18263         -1,
  18264     },
  18265 #endif /* chips */
  18266 
  18267 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  18268     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM56670_A0r */
  18269         soc_block_list[16],
  18270         soc_portreg,
  18271         1,
  18272         0,
  18273         0x60d00,
  18274         SOC_REG_FLAG_64_BITS,
  18275         0,
  18276         10,
  18277         soc_CLG2MAC_PFC_CTRLr_fields,
  18278         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18279         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18280         -1,
  18281         -1,
  18282     },
  18283 #endif /* chips */
  18284 
  18285 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  18286     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM56850_A0r */
  18287         soc_block_list[16],
  18288         soc_portreg,
  18289         1,
  18290         0,
  18291         0x60e00,
  18292         SOC_REG_FLAG_64_BITS,
  18293         0,
  18294         8,
  18295         soc_XLMAC_PFC_CTRL_BCM56850_A0r_fields,
  18296         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18297         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18298         -1,
  18299         -1,
  18300     },
  18301 #endif /* chips */
  18302 
  18303 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18304     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM56960_A0r */
  18305         soc_block_list[16],
  18306         soc_portreg,
  18307         1,
  18308         0,
  18309         0x60e00,
  18310         SOC_REG_FLAG_64_BITS,
  18311         0,
  18312         8,
  18313         soc_CLMAC_PFC_CTRLr_fields,
  18314         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18315         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18316         -1,
  18317         -1,
  18318         3,
  18319     },
  18320 #endif /* chips */
  18321 
  18322 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  18323     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  18324     defined(BCM_56980_B0)
  18325     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM56970_A0r */
  18326         soc_block_list[16],
  18327         soc_portreg,
  18328         1,
  18329         0,
  18330         0x60e00,
  18331         SOC_REG_FLAG_64_BITS,
  18332         0,
  18333         10,
  18334         soc_CLG2MAC_PFC_CTRLr_fields,
  18335         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18336         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18337         -1,
  18338         -1,
  18339         3,
  18340     },
  18341 #endif /* chips */
  18342 
  18343 #if defined(BCM_88270_A0)
  18344     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM88270_A0r */
  18345         soc_block_list[221],
  18346         soc_portreg,
  18347         1,
  18348         0,
  18349         0x60e00,
  18350         SOC_REG_FLAG_64_BITS,
  18351         0,
  18352         8,
  18353         soc_XLMAC_PFC_CTRL_BCM88270_A0r_fields,
  18354         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18355         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18356         -1,
  18357         -1,
  18358     },
  18359 #endif /* chips */
  18360 
  18361 #if defined(BCM_88375_A0)
  18362     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM88375_A0r */
  18363         soc_block_list[56],
  18364         soc_portreg,
  18365         1,
  18366         0,
  18367         0x60e00,
  18368         SOC_REG_FLAG_64_BITS,
  18369         0,
  18370         8,
  18371         soc_XLMAC_PFC_CTRL_BCM88375_A0r_fields,
  18372         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18373         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18374         -1,
  18375         -1,
  18376     },
  18377 #endif /* chips */
  18378 
  18379 #if defined(BCM_88375_B0)
  18380     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM88375_B0r */
  18381         soc_block_list[56],
  18382         soc_portreg,
  18383         1,
  18384         0,
  18385         0x60e00,
  18386         SOC_REG_FLAG_64_BITS,
  18387         0,
  18388         8,
  18389         soc_XLMAC_PFC_CTRL_BCM88375_B0r_fields,
  18390         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18391         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18392         -1,
  18393         -1,
  18394     },
  18395 #endif /* chips */
  18396 
  18397 #if defined(BCM_88470_A0)
  18398     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM88470_A0r */
  18399         soc_block_list[56],
  18400         soc_portreg,
  18401         1,
  18402         0,
  18403         0x60e00,
  18404         SOC_REG_FLAG_64_BITS,
  18405         0,
  18406         8,
  18407         soc_XLMAC_PFC_CTRL_BCM88470_A0r_fields,
  18408         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18409         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18410         -1,
  18411         -1,
  18412     },
  18413 #endif /* chips */
  18414 
  18415 #if defined(BCM_88470_B0)
  18416     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM88470_B0r */
  18417         soc_block_list[56],
  18418         soc_portreg,
  18419         1,
  18420         0,
  18421         0x60e00,
  18422         SOC_REG_FLAG_64_BITS,
  18423         0,
  18424         8,
  18425         soc_XLMAC_PFC_CTRL_BCM88470_B0r_fields,
  18426         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18427         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18428         -1,
  18429         -1,
  18430     },
  18431 #endif /* chips */
  18432 
  18433 #if defined(BCM_88675_A0)
  18434     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM88675_A0r */
  18435         soc_block_list[56],
  18436         soc_portreg,
  18437         1,
  18438         0,
  18439         0x60e00,
  18440         SOC_REG_FLAG_64_BITS,
  18441         0,
  18442         8,
  18443         soc_XLMAC_PFC_CTRLr_fields,
  18444         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18445         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18446         -1,
  18447         -1,
  18448     },
  18449 #endif /* chips */
  18450 
  18451 #if defined(BCM_88675_B0)
  18452     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM88675_B0r */
  18453         soc_block_list[56],
  18454         soc_portreg,
  18455         1,
  18456         0,
  18457         0x60e00,
  18458         SOC_REG_FLAG_64_BITS,
  18459         0,
  18460         8,
  18461         soc_XLMAC_PFC_CTRL_BCM88675_B0r_fields,
  18462         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18463         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18464         -1,
  18465         -1,
  18466     },
  18467 #endif /* chips */
  18468 
  18469 #if defined(BCM_88680_A0)
  18470     { /* SOC_REG_INT_XLMAC_PFC_CTRL_BCM88680_A0r */
  18471         soc_block_list[56],
  18472         soc_portreg,
  18473         1,
  18474         0,
  18475         0x60e00,
  18476         SOC_REG_FLAG_64_BITS,
  18477         0,
  18478         8,
  18479         soc_XLMAC_PFC_CTRL_BCM88680_A0r_fields,
  18480         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  18481         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  18482         -1,
  18483         -1,
  18484     },
  18485 #endif /* chips */
  18486 
  18487 #if defined(BCM_2801PM_A0)
  18488     { /* SOC_REG_INT_XLMAC_PFC_DAr */
  18489         soc_block_list[56],
  18490         soc_portreg,
  18491         1,
  18492         0,
  18493         0x61100,
  18494         SOC_REG_FLAG_64_BITS,
  18495         0,
  18496         1,
  18497         soc_CLMAC_PFC_DAr_fields,
  18498         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18499         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18500         -1,
  18501         -1,
  18502     },
  18503 #endif /* chips */
  18504 
  18505 #if defined(BCM_53400_A0)
  18506     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM53400_A0r */
  18507         soc_block_list[16],
  18508         soc_portreg,
  18509         1,
  18510         0,
  18511         0x61100,
  18512         SOC_REG_FLAG_64_BITS,
  18513         0,
  18514         3,
  18515         soc_XLMAC_PFC_DA_BCM53400_A0r_fields,
  18516         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18517         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18518         -1,
  18519         -1,
  18520     },
  18521 #endif /* chips */
  18522 
  18523 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  18524     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM53570_A0r */
  18525         soc_block_list[16],
  18526         soc_portreg,
  18527         1,
  18528         0,
  18529         0x61000,
  18530         SOC_REG_FLAG_64_BITS,
  18531         0,
  18532         3,
  18533         soc_XLMAC_PFC_DA_BCM53400_A0r_fields,
  18534         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18535         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18536         -1,
  18537         -1,
  18538     },
  18539 #endif /* chips */
  18540 
  18541 #if defined(BCM_56150_A0)
  18542     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM56150_A0r */
  18543         soc_block_list[16],
  18544         soc_portreg,
  18545         1,
  18546         0,
  18547         0x61100,
  18548         SOC_REG_FLAG_64_BITS,
  18549         0,
  18550         3,
  18551         soc_CMAC_PFC_DAr_fields,
  18552         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18553         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18554         -1,
  18555         -1,
  18556     },
  18557 #endif /* chips */
  18558 
  18559 #if defined(BCM_56160_A0)
  18560     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM56160_A0r */
  18561         soc_block_list[16],
  18562         soc_portreg,
  18563         1,
  18564         0,
  18565         0x61100,
  18566         SOC_REG_FLAG_64_BITS,
  18567         0,
  18568         3,
  18569         soc_XLMAC_PFC_DA_BCM53400_A0r_fields,
  18570         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18571         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18572         -1,
  18573         -1,
  18574     },
  18575 #endif /* chips */
  18576 
  18577 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  18578     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM56260_A0r */
  18579         soc_block_list[220],
  18580         soc_portreg,
  18581         1,
  18582         0,
  18583         0x61100,
  18584         SOC_REG_FLAG_64_BITS,
  18585         0,
  18586         3,
  18587         soc_XLMAC_PFC_DA_BCM53400_A0r_fields,
  18588         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18589         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18590         -1,
  18591         -1,
  18592     },
  18593 #endif /* chips */
  18594 
  18595 #if defined(BCM_56270_A0)
  18596     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM56270_A0r */
  18597         soc_block_list[220],
  18598         soc_portreg,
  18599         1,
  18600         0,
  18601         0x61100,
  18602         SOC_REG_FLAG_64_BITS,
  18603         0,
  18604         3,
  18605         soc_XLMAC_PFC_DA_BCM53400_A0r_fields,
  18606         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18607         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18608         -1,
  18609         -1,
  18610     },
  18611 #endif /* chips */
  18612 
  18613 #if defined(BCM_56370_A0)
  18614     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM56370_A0r */
  18615         soc_block_list[16],
  18616         soc_portreg,
  18617         1,
  18618         0,
  18619         0x61100,
  18620         SOC_REG_FLAG_64_BITS,
  18621         0,
  18622         3,
  18623         soc_XLMAC_PFC_DA_BCM53400_A0r_fields,
  18624         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18625         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18626         -1,
  18627         -1,
  18628         3,
  18629     },
  18630 #endif /* chips */
  18631 
  18632 #if defined(BCM_56560_A0)
  18633     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM56560_A0r */
  18634         soc_block_list[16],
  18635         soc_portreg,
  18636         1,
  18637         0,
  18638         0x61100,
  18639         SOC_REG_FLAG_64_BITS,
  18640         0,
  18641         3,
  18642         soc_XLMAC_PFC_DA_BCM53400_A0r_fields,
  18643         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18644         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18645         -1,
  18646         -1,
  18647     },
  18648 #endif /* chips */
  18649 
  18650 #if defined(BCM_56560_B0)
  18651     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM56560_B0r */
  18652         soc_block_list[16],
  18653         soc_portreg,
  18654         1,
  18655         0,
  18656         0x61100,
  18657         SOC_REG_FLAG_64_BITS,
  18658         0,
  18659         3,
  18660         soc_XLMAC_PFC_DA_BCM53400_A0r_fields,
  18661         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18662         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18663         -1,
  18664         -1,
  18665     },
  18666 #endif /* chips */
  18667 
  18668 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  18669     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM56670_A0r */
  18670         soc_block_list[16],
  18671         soc_portreg,
  18672         1,
  18673         0,
  18674         0x61000,
  18675         SOC_REG_FLAG_64_BITS,
  18676         0,
  18677         3,
  18678         soc_XLMAC_PFC_DA_BCM53400_A0r_fields,
  18679         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18680         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18681         -1,
  18682         -1,
  18683     },
  18684 #endif /* chips */
  18685 
  18686 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  18687     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM56850_A0r */
  18688         soc_block_list[16],
  18689         soc_portreg,
  18690         1,
  18691         0,
  18692         0x61100,
  18693         SOC_REG_FLAG_64_BITS,
  18694         0,
  18695         3,
  18696         soc_CMAC_PFC_DAr_fields,
  18697         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18698         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18699         -1,
  18700         -1,
  18701     },
  18702 #endif /* chips */
  18703 
  18704 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  18705     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  18706     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  18707     defined(BCM_56980_B0)
  18708     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM56960_A0r */
  18709         soc_block_list[16],
  18710         soc_portreg,
  18711         1,
  18712         0,
  18713         0x61100,
  18714         SOC_REG_FLAG_64_BITS,
  18715         0,
  18716         3,
  18717         soc_XLMAC_PFC_DA_BCM53400_A0r_fields,
  18718         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18719         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18720         -1,
  18721         -1,
  18722         3,
  18723     },
  18724 #endif /* chips */
  18725 
  18726 #if defined(BCM_88270_A0)
  18727     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM88270_A0r */
  18728         soc_block_list[221],
  18729         soc_portreg,
  18730         1,
  18731         0,
  18732         0x61100,
  18733         SOC_REG_FLAG_64_BITS,
  18734         0,
  18735         1,
  18736         soc_XLMAC_PFC_DA_BCM88270_A0r_fields,
  18737         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18738         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18739         -1,
  18740         -1,
  18741     },
  18742 #endif /* chips */
  18743 
  18744 #if defined(BCM_88375_A0)
  18745     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM88375_A0r */
  18746         soc_block_list[56],
  18747         soc_portreg,
  18748         1,
  18749         0,
  18750         0x61100,
  18751         SOC_REG_FLAG_64_BITS,
  18752         0,
  18753         1,
  18754         soc_XLMAC_PFC_DA_BCM88375_A0r_fields,
  18755         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18756         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18757         -1,
  18758         -1,
  18759     },
  18760 #endif /* chips */
  18761 
  18762 #if defined(BCM_88375_B0)
  18763     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM88375_B0r */
  18764         soc_block_list[56],
  18765         soc_portreg,
  18766         1,
  18767         0,
  18768         0x61100,
  18769         SOC_REG_FLAG_64_BITS,
  18770         0,
  18771         1,
  18772         soc_XLMAC_PFC_DA_BCM88375_B0r_fields,
  18773         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18774         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18775         -1,
  18776         -1,
  18777     },
  18778 #endif /* chips */
  18779 
  18780 #if defined(BCM_88470_A0)
  18781     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM88470_A0r */
  18782         soc_block_list[56],
  18783         soc_portreg,
  18784         1,
  18785         0,
  18786         0x61100,
  18787         SOC_REG_FLAG_64_BITS,
  18788         0,
  18789         1,
  18790         soc_XLMAC_PFC_DA_BCM88470_A0r_fields,
  18791         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18792         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18793         -1,
  18794         -1,
  18795     },
  18796 #endif /* chips */
  18797 
  18798 #if defined(BCM_88470_B0)
  18799     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM88470_B0r */
  18800         soc_block_list[56],
  18801         soc_portreg,
  18802         1,
  18803         0,
  18804         0x61100,
  18805         SOC_REG_FLAG_64_BITS,
  18806         0,
  18807         1,
  18808         soc_XLMAC_PFC_DA_BCM88470_B0r_fields,
  18809         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18810         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18811         -1,
  18812         -1,
  18813     },
  18814 #endif /* chips */
  18815 
  18816 #if defined(BCM_88675_A0)
  18817     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM88675_A0r */
  18818         soc_block_list[56],
  18819         soc_portreg,
  18820         1,
  18821         0,
  18822         0x61100,
  18823         SOC_REG_FLAG_64_BITS,
  18824         0,
  18825         1,
  18826         soc_XLMAC_PFC_DAr_fields,
  18827         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18828         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18829         -1,
  18830         -1,
  18831     },
  18832 #endif /* chips */
  18833 
  18834 #if defined(BCM_88675_B0)
  18835     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM88675_B0r */
  18836         soc_block_list[56],
  18837         soc_portreg,
  18838         1,
  18839         0,
  18840         0x61100,
  18841         SOC_REG_FLAG_64_BITS,
  18842         0,
  18843         1,
  18844         soc_XLMAC_PFC_DA_BCM88675_B0r_fields,
  18845         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18846         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18847         -1,
  18848         -1,
  18849     },
  18850 #endif /* chips */
  18851 
  18852 #if defined(BCM_88680_A0)
  18853     { /* SOC_REG_INT_XLMAC_PFC_DA_BCM88680_A0r */
  18854         soc_block_list[56],
  18855         soc_portreg,
  18856         1,
  18857         0,
  18858         0x61100,
  18859         SOC_REG_FLAG_64_BITS,
  18860         0,
  18861         1,
  18862         soc_XLMAC_PFC_DA_BCM88680_A0r_fields,
  18863         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  18864         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  18865         -1,
  18866         -1,
  18867     },
  18868 #endif /* chips */
  18869 
  18870 #if defined(BCM_2801PM_A0)
  18871     { /* SOC_REG_INT_XLMAC_PFC_OPCODEr */
  18872         soc_block_list[56],
  18873         soc_portreg,
  18874         1,
  18875         0,
  18876         0x61000,
  18877         0,
  18878         0,
  18879         1,
  18880         soc_CLMAC_PFC_OPCODEr_fields,
  18881         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  18882         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  18883         -1,
  18884         -1,
  18885     },
  18886 #endif /* chips */
  18887 
  18888 #if defined(BCM_53400_A0)
  18889     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM53400_A0r */
  18890         soc_block_list[16],
  18891         soc_portreg,
  18892         1,
  18893         0,
  18894         0x61000,
  18895         SOC_REG_FLAG_64_BITS,
  18896         0,
  18897         1,
  18898         soc_CLMAC_PFC_OPCODEr_fields,
  18899         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  18900         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  18901         -1,
  18902         -1,
  18903     },
  18904 #endif /* chips */
  18905 
  18906 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  18907     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM53570_A0r */
  18908         soc_block_list[16],
  18909         soc_portreg,
  18910         1,
  18911         0,
  18912         0x60f00,
  18913         SOC_REG_FLAG_64_BITS,
  18914         0,
  18915         1,
  18916         soc_CLMAC_PFC_OPCODEr_fields,
  18917         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  18918         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  18919         -1,
  18920         -1,
  18921     },
  18922 #endif /* chips */
  18923 
  18924 #if defined(BCM_56150_A0)
  18925     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM56150_A0r */
  18926         soc_block_list[16],
  18927         soc_portreg,
  18928         1,
  18929         0,
  18930         0x61000,
  18931         SOC_REG_FLAG_64_BITS,
  18932         0,
  18933         1,
  18934         soc_CMAC_PFC_OPCODEr_fields,
  18935         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  18936         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  18937         -1,
  18938         -1,
  18939     },
  18940 #endif /* chips */
  18941 
  18942 #if defined(BCM_56160_A0)
  18943     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM56160_A0r */
  18944         soc_block_list[16],
  18945         soc_portreg,
  18946         1,
  18947         0,
  18948         0x61000,
  18949         SOC_REG_FLAG_64_BITS,
  18950         0,
  18951         1,
  18952         soc_CLMAC_PFC_OPCODEr_fields,
  18953         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  18954         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  18955         -1,
  18956         -1,
  18957     },
  18958 #endif /* chips */
  18959 
  18960 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  18961     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM56260_A0r */
  18962         soc_block_list[220],
  18963         soc_portreg,
  18964         1,
  18965         0,
  18966         0x61000,
  18967         SOC_REG_FLAG_64_BITS,
  18968         0,
  18969         1,
  18970         soc_CLMAC_PFC_OPCODEr_fields,
  18971         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  18972         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  18973         -1,
  18974         -1,
  18975     },
  18976 #endif /* chips */
  18977 
  18978 #if defined(BCM_56270_A0)
  18979     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM56270_A0r */
  18980         soc_block_list[220],
  18981         soc_portreg,
  18982         1,
  18983         0,
  18984         0x61000,
  18985         SOC_REG_FLAG_64_BITS,
  18986         0,
  18987         1,
  18988         soc_CLMAC_PFC_OPCODEr_fields,
  18989         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  18990         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  18991         -1,
  18992         -1,
  18993     },
  18994 #endif /* chips */
  18995 
  18996 #if defined(BCM_56370_A0)
  18997     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM56370_A0r */
  18998         soc_block_list[16],
  18999         soc_portreg,
  19000         1,
  19001         0,
  19002         0x61000,
  19003         SOC_REG_FLAG_64_BITS,
  19004         0,
  19005         1,
  19006         soc_CLMAC_PFC_OPCODEr_fields,
  19007         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19008         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19009         -1,
  19010         -1,
  19011         3,
  19012     },
  19013 #endif /* chips */
  19014 
  19015 #if defined(BCM_56560_A0)
  19016     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM56560_A0r */
  19017         soc_block_list[16],
  19018         soc_portreg,
  19019         1,
  19020         0,
  19021         0x61000,
  19022         SOC_REG_FLAG_64_BITS,
  19023         0,
  19024         1,
  19025         soc_CLMAC_PFC_OPCODEr_fields,
  19026         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19027         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19028         -1,
  19029         -1,
  19030     },
  19031 #endif /* chips */
  19032 
  19033 #if defined(BCM_56560_B0)
  19034     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM56560_B0r */
  19035         soc_block_list[16],
  19036         soc_portreg,
  19037         1,
  19038         0,
  19039         0x61000,
  19040         SOC_REG_FLAG_64_BITS,
  19041         0,
  19042         1,
  19043         soc_CLMAC_PFC_OPCODEr_fields,
  19044         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19045         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19046         -1,
  19047         -1,
  19048     },
  19049 #endif /* chips */
  19050 
  19051 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  19052     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM56670_A0r */
  19053         soc_block_list[16],
  19054         soc_portreg,
  19055         1,
  19056         0,
  19057         0x60f00,
  19058         SOC_REG_FLAG_64_BITS,
  19059         0,
  19060         1,
  19061         soc_CLMAC_PFC_OPCODEr_fields,
  19062         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19063         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19064         -1,
  19065         -1,
  19066     },
  19067 #endif /* chips */
  19068 
  19069 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  19070     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM56850_A0r */
  19071         soc_block_list[16],
  19072         soc_portreg,
  19073         1,
  19074         0,
  19075         0x61000,
  19076         SOC_REG_FLAG_64_BITS,
  19077         0,
  19078         1,
  19079         soc_CMAC_PFC_OPCODEr_fields,
  19080         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19081         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19082         -1,
  19083         -1,
  19084     },
  19085 #endif /* chips */
  19086 
  19087 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  19088     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  19089     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  19090     defined(BCM_56980_B0)
  19091     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM56960_A0r */
  19092         soc_block_list[16],
  19093         soc_portreg,
  19094         1,
  19095         0,
  19096         0x61000,
  19097         SOC_REG_FLAG_64_BITS,
  19098         0,
  19099         1,
  19100         soc_CLMAC_PFC_OPCODEr_fields,
  19101         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19102         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19103         -1,
  19104         -1,
  19105         3,
  19106     },
  19107 #endif /* chips */
  19108 
  19109 #if defined(BCM_88270_A0)
  19110     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM88270_A0r */
  19111         soc_block_list[221],
  19112         soc_portreg,
  19113         1,
  19114         0,
  19115         0x61000,
  19116         SOC_REG_FLAG_64_BITS,
  19117         0,
  19118         1,
  19119         soc_XLMAC_PFC_OPCODE_BCM88270_A0r_fields,
  19120         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19121         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19122         -1,
  19123         -1,
  19124     },
  19125 #endif /* chips */
  19126 
  19127 #if defined(BCM_88375_A0)
  19128     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM88375_A0r */
  19129         soc_block_list[56],
  19130         soc_portreg,
  19131         1,
  19132         0,
  19133         0x61000,
  19134         SOC_REG_FLAG_64_BITS,
  19135         0,
  19136         1,
  19137         soc_XLMAC_PFC_OPCODE_BCM88375_A0r_fields,
  19138         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19139         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19140         -1,
  19141         -1,
  19142     },
  19143 #endif /* chips */
  19144 
  19145 #if defined(BCM_88375_B0)
  19146     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM88375_B0r */
  19147         soc_block_list[56],
  19148         soc_portreg,
  19149         1,
  19150         0,
  19151         0x61000,
  19152         SOC_REG_FLAG_64_BITS,
  19153         0,
  19154         1,
  19155         soc_XLMAC_PFC_OPCODE_BCM88375_B0r_fields,
  19156         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19157         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19158         -1,
  19159         -1,
  19160     },
  19161 #endif /* chips */
  19162 
  19163 #if defined(BCM_88470_A0)
  19164     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM88470_A0r */
  19165         soc_block_list[56],
  19166         soc_portreg,
  19167         1,
  19168         0,
  19169         0x61000,
  19170         SOC_REG_FLAG_64_BITS,
  19171         0,
  19172         1,
  19173         soc_XLMAC_PFC_OPCODE_BCM88470_A0r_fields,
  19174         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19175         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19176         -1,
  19177         -1,
  19178     },
  19179 #endif /* chips */
  19180 
  19181 #if defined(BCM_88470_B0)
  19182     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM88470_B0r */
  19183         soc_block_list[56],
  19184         soc_portreg,
  19185         1,
  19186         0,
  19187         0x61000,
  19188         SOC_REG_FLAG_64_BITS,
  19189         0,
  19190         1,
  19191         soc_XLMAC_PFC_OPCODE_BCM88470_B0r_fields,
  19192         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19193         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19194         -1,
  19195         -1,
  19196     },
  19197 #endif /* chips */
  19198 
  19199 #if defined(BCM_88675_A0)
  19200     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM88675_A0r */
  19201         soc_block_list[56],
  19202         soc_portreg,
  19203         1,
  19204         0,
  19205         0x61000,
  19206         SOC_REG_FLAG_64_BITS,
  19207         0,
  19208         1,
  19209         soc_XLMAC_PFC_OPCODEr_fields,
  19210         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19211         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19212         -1,
  19213         -1,
  19214     },
  19215 #endif /* chips */
  19216 
  19217 #if defined(BCM_88675_B0)
  19218     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM88675_B0r */
  19219         soc_block_list[56],
  19220         soc_portreg,
  19221         1,
  19222         0,
  19223         0x61000,
  19224         SOC_REG_FLAG_64_BITS,
  19225         0,
  19226         1,
  19227         soc_XLMAC_PFC_OPCODE_BCM88675_B0r_fields,
  19228         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19229         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19230         -1,
  19231         -1,
  19232     },
  19233 #endif /* chips */
  19234 
  19235 #if defined(BCM_88680_A0)
  19236     { /* SOC_REG_INT_XLMAC_PFC_OPCODE_BCM88680_A0r */
  19237         soc_block_list[56],
  19238         soc_portreg,
  19239         1,
  19240         0,
  19241         0x61000,
  19242         SOC_REG_FLAG_64_BITS,
  19243         0,
  19244         1,
  19245         soc_XLMAC_PFC_OPCODE_BCM88680_A0r_fields,
  19246         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  19247         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19248         -1,
  19249         -1,
  19250     },
  19251 #endif /* chips */
  19252 
  19253 #if defined(BCM_2801PM_A0)
  19254     { /* SOC_REG_INT_XLMAC_PFC_TYPEr */
  19255         soc_block_list[56],
  19256         soc_portreg,
  19257         1,
  19258         0,
  19259         0x60f00,
  19260         0,
  19261         0,
  19262         1,
  19263         soc_CLMAC_PFC_TYPEr_fields,
  19264         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19265         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19266         -1,
  19267         -1,
  19268     },
  19269 #endif /* chips */
  19270 
  19271 #if defined(BCM_53400_A0)
  19272     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM53400_A0r */
  19273         soc_block_list[16],
  19274         soc_portreg,
  19275         1,
  19276         0,
  19277         0x60f00,
  19278         SOC_REG_FLAG_64_BITS,
  19279         0,
  19280         1,
  19281         soc_CLMAC_PFC_TYPEr_fields,
  19282         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19283         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19284         -1,
  19285         -1,
  19286     },
  19287 #endif /* chips */
  19288 
  19289 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  19290     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM53570_A0r */
  19291         soc_block_list[16],
  19292         soc_portreg,
  19293         1,
  19294         0,
  19295         0x60e00,
  19296         SOC_REG_FLAG_64_BITS,
  19297         0,
  19298         1,
  19299         soc_CLMAC_PFC_TYPEr_fields,
  19300         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19301         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19302         -1,
  19303         -1,
  19304     },
  19305 #endif /* chips */
  19306 
  19307 #if defined(BCM_56150_A0)
  19308     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM56150_A0r */
  19309         soc_block_list[16],
  19310         soc_portreg,
  19311         1,
  19312         0,
  19313         0x60f00,
  19314         SOC_REG_FLAG_64_BITS,
  19315         0,
  19316         1,
  19317         soc_CMAC_PFC_TYPEr_fields,
  19318         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19319         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19320         -1,
  19321         -1,
  19322     },
  19323 #endif /* chips */
  19324 
  19325 #if defined(BCM_56160_A0)
  19326     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM56160_A0r */
  19327         soc_block_list[16],
  19328         soc_portreg,
  19329         1,
  19330         0,
  19331         0x60f00,
  19332         SOC_REG_FLAG_64_BITS,
  19333         0,
  19334         1,
  19335         soc_CLMAC_PFC_TYPEr_fields,
  19336         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19337         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19338         -1,
  19339         -1,
  19340     },
  19341 #endif /* chips */
  19342 
  19343 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  19344     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM56260_A0r */
  19345         soc_block_list[220],
  19346         soc_portreg,
  19347         1,
  19348         0,
  19349         0x60f00,
  19350         SOC_REG_FLAG_64_BITS,
  19351         0,
  19352         1,
  19353         soc_CLMAC_PFC_TYPEr_fields,
  19354         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19355         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19356         -1,
  19357         -1,
  19358     },
  19359 #endif /* chips */
  19360 
  19361 #if defined(BCM_56270_A0)
  19362     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM56270_A0r */
  19363         soc_block_list[220],
  19364         soc_portreg,
  19365         1,
  19366         0,
  19367         0x60f00,
  19368         SOC_REG_FLAG_64_BITS,
  19369         0,
  19370         1,
  19371         soc_CLMAC_PFC_TYPEr_fields,
  19372         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19373         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19374         -1,
  19375         -1,
  19376     },
  19377 #endif /* chips */
  19378 
  19379 #if defined(BCM_56370_A0)
  19380     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM56370_A0r */
  19381         soc_block_list[16],
  19382         soc_portreg,
  19383         1,
  19384         0,
  19385         0x60f00,
  19386         SOC_REG_FLAG_64_BITS,
  19387         0,
  19388         1,
  19389         soc_CLMAC_PFC_TYPEr_fields,
  19390         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19391         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19392         -1,
  19393         -1,
  19394         3,
  19395     },
  19396 #endif /* chips */
  19397 
  19398 #if defined(BCM_56560_A0)
  19399     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM56560_A0r */
  19400         soc_block_list[16],
  19401         soc_portreg,
  19402         1,
  19403         0,
  19404         0x60f00,
  19405         SOC_REG_FLAG_64_BITS,
  19406         0,
  19407         1,
  19408         soc_CLMAC_PFC_TYPEr_fields,
  19409         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19410         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19411         -1,
  19412         -1,
  19413     },
  19414 #endif /* chips */
  19415 
  19416 #if defined(BCM_56560_B0)
  19417     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM56560_B0r */
  19418         soc_block_list[16],
  19419         soc_portreg,
  19420         1,
  19421         0,
  19422         0x60f00,
  19423         SOC_REG_FLAG_64_BITS,
  19424         0,
  19425         1,
  19426         soc_CLMAC_PFC_TYPEr_fields,
  19427         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19428         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19429         -1,
  19430         -1,
  19431     },
  19432 #endif /* chips */
  19433 
  19434 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  19435     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM56670_A0r */
  19436         soc_block_list[16],
  19437         soc_portreg,
  19438         1,
  19439         0,
  19440         0x60e00,
  19441         SOC_REG_FLAG_64_BITS,
  19442         0,
  19443         1,
  19444         soc_CLMAC_PFC_TYPEr_fields,
  19445         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19446         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19447         -1,
  19448         -1,
  19449     },
  19450 #endif /* chips */
  19451 
  19452 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  19453     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM56850_A0r */
  19454         soc_block_list[16],
  19455         soc_portreg,
  19456         1,
  19457         0,
  19458         0x60f00,
  19459         SOC_REG_FLAG_64_BITS,
  19460         0,
  19461         1,
  19462         soc_CMAC_PFC_TYPEr_fields,
  19463         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19464         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19465         -1,
  19466         -1,
  19467     },
  19468 #endif /* chips */
  19469 
  19470 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  19471     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  19472     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  19473     defined(BCM_56980_B0)
  19474     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM56960_A0r */
  19475         soc_block_list[16],
  19476         soc_portreg,
  19477         1,
  19478         0,
  19479         0x60f00,
  19480         SOC_REG_FLAG_64_BITS,
  19481         0,
  19482         1,
  19483         soc_CLMAC_PFC_TYPEr_fields,
  19484         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19485         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19486         -1,
  19487         -1,
  19488         3,
  19489     },
  19490 #endif /* chips */
  19491 
  19492 #if defined(BCM_88270_A0)
  19493     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM88270_A0r */
  19494         soc_block_list[221],
  19495         soc_portreg,
  19496         1,
  19497         0,
  19498         0x60f00,
  19499         SOC_REG_FLAG_64_BITS,
  19500         0,
  19501         1,
  19502         soc_XLMAC_PFC_TYPE_BCM88270_A0r_fields,
  19503         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19504         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19505         -1,
  19506         -1,
  19507     },
  19508 #endif /* chips */
  19509 
  19510 #if defined(BCM_88375_A0)
  19511     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM88375_A0r */
  19512         soc_block_list[56],
  19513         soc_portreg,
  19514         1,
  19515         0,
  19516         0x60f00,
  19517         SOC_REG_FLAG_64_BITS,
  19518         0,
  19519         1,
  19520         soc_XLMAC_PFC_TYPE_BCM88375_A0r_fields,
  19521         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19522         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19523         -1,
  19524         -1,
  19525     },
  19526 #endif /* chips */
  19527 
  19528 #if defined(BCM_88375_B0)
  19529     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM88375_B0r */
  19530         soc_block_list[56],
  19531         soc_portreg,
  19532         1,
  19533         0,
  19534         0x60f00,
  19535         SOC_REG_FLAG_64_BITS,
  19536         0,
  19537         1,
  19538         soc_XLMAC_PFC_TYPE_BCM88375_B0r_fields,
  19539         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19540         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19541         -1,
  19542         -1,
  19543     },
  19544 #endif /* chips */
  19545 
  19546 #if defined(BCM_88470_A0)
  19547     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM88470_A0r */
  19548         soc_block_list[56],
  19549         soc_portreg,
  19550         1,
  19551         0,
  19552         0x60f00,
  19553         SOC_REG_FLAG_64_BITS,
  19554         0,
  19555         1,
  19556         soc_XLMAC_PFC_TYPE_BCM88470_A0r_fields,
  19557         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19558         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19559         -1,
  19560         -1,
  19561     },
  19562 #endif /* chips */
  19563 
  19564 #if defined(BCM_88470_B0)
  19565     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM88470_B0r */
  19566         soc_block_list[56],
  19567         soc_portreg,
  19568         1,
  19569         0,
  19570         0x60f00,
  19571         SOC_REG_FLAG_64_BITS,
  19572         0,
  19573         1,
  19574         soc_XLMAC_PFC_TYPE_BCM88470_B0r_fields,
  19575         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19576         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19577         -1,
  19578         -1,
  19579     },
  19580 #endif /* chips */
  19581 
  19582 #if defined(BCM_88675_A0)
  19583     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM88675_A0r */
  19584         soc_block_list[56],
  19585         soc_portreg,
  19586         1,
  19587         0,
  19588         0x60f00,
  19589         SOC_REG_FLAG_64_BITS,
  19590         0,
  19591         1,
  19592         soc_XLMAC_PFC_TYPEr_fields,
  19593         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19594         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19595         -1,
  19596         -1,
  19597     },
  19598 #endif /* chips */
  19599 
  19600 #if defined(BCM_88675_B0)
  19601     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM88675_B0r */
  19602         soc_block_list[56],
  19603         soc_portreg,
  19604         1,
  19605         0,
  19606         0x60f00,
  19607         SOC_REG_FLAG_64_BITS,
  19608         0,
  19609         1,
  19610         soc_XLMAC_PFC_TYPE_BCM88675_B0r_fields,
  19611         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19612         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19613         -1,
  19614         -1,
  19615     },
  19616 #endif /* chips */
  19617 
  19618 #if defined(BCM_88680_A0)
  19619     { /* SOC_REG_INT_XLMAC_PFC_TYPE_BCM88680_A0r */
  19620         soc_block_list[56],
  19621         soc_portreg,
  19622         1,
  19623         0,
  19624         0x60f00,
  19625         SOC_REG_FLAG_64_BITS,
  19626         0,
  19627         1,
  19628         soc_XLMAC_PFC_TYPE_BCM88680_A0r_fields,
  19629         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  19630         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19631         -1,
  19632         -1,
  19633     },
  19634 #endif /* chips */
  19635 
  19636 #if defined(BCM_2801PM_A0)
  19637     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUSr */
  19638         soc_block_list[56],
  19639         soc_portreg,
  19640         1,
  19641         0,
  19642         0x63100,
  19643         SOC_REG_FLAG_RO |
  19644                           SOC_REG_FLAG_SIGNAL,
  19645         0,
  19646         2,
  19647         soc_CLMAC_RX_CDC_ECC_STATUSr_fields,
  19648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19649         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19650         -1,
  19651         -1,
  19652     },
  19653 #endif /* chips */
  19654 
  19655 #if defined(BCM_53400_A0)
  19656     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r */
  19657         soc_block_list[16],
  19658         soc_portreg,
  19659         1,
  19660         0,
  19661         0x63100,
  19662         SOC_REG_FLAG_64_BITS |
  19663                           SOC_REG_FLAG_RO,
  19664         0,
  19665         2,
  19666         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19668         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19669         -1,
  19670         -1,
  19671     },
  19672 #endif /* chips */
  19673 
  19674 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  19675     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM53570_A0r */
  19676         soc_block_list[16],
  19677         soc_portreg,
  19678         1,
  19679         0,
  19680         0x63200,
  19681         SOC_REG_FLAG_64_BITS |
  19682                           SOC_REG_FLAG_RO,
  19683         0,
  19684         2,
  19685         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19687         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19688         -1,
  19689         -1,
  19690     },
  19691 #endif /* chips */
  19692 
  19693 #if defined(BCM_56160_A0)
  19694     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM56160_A0r */
  19695         soc_block_list[16],
  19696         soc_portreg,
  19697         1,
  19698         0,
  19699         0x63200,
  19700         SOC_REG_FLAG_64_BITS |
  19701                           SOC_REG_FLAG_RO,
  19702         0,
  19703         2,
  19704         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19706         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19707         -1,
  19708         -1,
  19709     },
  19710 #endif /* chips */
  19711 
  19712 #if defined(BCM_56260_A0)
  19713     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM56260_A0r */
  19714         soc_block_list[220],
  19715         soc_portreg,
  19716         1,
  19717         0,
  19718         0x63100,
  19719         SOC_REG_FLAG_64_BITS |
  19720                           SOC_REG_FLAG_RO,
  19721         0,
  19722         2,
  19723         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19725         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19726         -1,
  19727         -1,
  19728     },
  19729 #endif /* chips */
  19730 
  19731 #if defined(BCM_56260_B0)
  19732     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM56260_B0r */
  19733         soc_block_list[220],
  19734         soc_portreg,
  19735         1,
  19736         0,
  19737         0x63200,
  19738         SOC_REG_FLAG_64_BITS |
  19739                           SOC_REG_FLAG_RO,
  19740         0,
  19741         2,
  19742         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19744         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19745         -1,
  19746         -1,
  19747     },
  19748 #endif /* chips */
  19749 
  19750 #if defined(BCM_56270_A0)
  19751     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM56270_A0r */
  19752         soc_block_list[220],
  19753         soc_portreg,
  19754         1,
  19755         0,
  19756         0x63200,
  19757         SOC_REG_FLAG_64_BITS |
  19758                           SOC_REG_FLAG_RO,
  19759         0,
  19760         2,
  19761         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19763         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19764         -1,
  19765         -1,
  19766     },
  19767 #endif /* chips */
  19768 
  19769 #if defined(BCM_56370_A0)
  19770     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM56370_A0r */
  19771         soc_block_list[16],
  19772         soc_portreg,
  19773         1,
  19774         0,
  19775         0x63200,
  19776         SOC_REG_FLAG_64_BITS |
  19777                           SOC_REG_FLAG_RO,
  19778         0,
  19779         2,
  19780         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19782         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19783         -1,
  19784         -1,
  19785         3,
  19786     },
  19787 #endif /* chips */
  19788 
  19789 #if defined(BCM_56560_A0)
  19790     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM56560_A0r */
  19791         soc_block_list[16],
  19792         soc_portreg,
  19793         1,
  19794         0,
  19795         0x63100,
  19796         SOC_REG_FLAG_64_BITS |
  19797                           SOC_REG_FLAG_RO,
  19798         0,
  19799         2,
  19800         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19802         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19803         -1,
  19804         -1,
  19805     },
  19806 #endif /* chips */
  19807 
  19808 #if defined(BCM_56560_B0)
  19809     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM56560_B0r */
  19810         soc_block_list[16],
  19811         soc_portreg,
  19812         1,
  19813         0,
  19814         0x63200,
  19815         SOC_REG_FLAG_64_BITS |
  19816                           SOC_REG_FLAG_RO,
  19817         0,
  19818         2,
  19819         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19821         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19822         -1,
  19823         -1,
  19824     },
  19825 #endif /* chips */
  19826 
  19827 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  19828     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM56670_A0r */
  19829         soc_block_list[16],
  19830         soc_portreg,
  19831         1,
  19832         0,
  19833         0x63200,
  19834         SOC_REG_FLAG_64_BITS |
  19835                           SOC_REG_FLAG_RO,
  19836         0,
  19837         2,
  19838         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19840         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19841         -1,
  19842         -1,
  19843     },
  19844 #endif /* chips */
  19845 
  19846 #if defined(BCM_56860_A0)
  19847     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM56860_A0r */
  19848         soc_block_list[16],
  19849         soc_portreg,
  19850         1,
  19851         0,
  19852         0x63200,
  19853         SOC_REG_FLAG_64_BITS |
  19854                           SOC_REG_FLAG_RO,
  19855         0,
  19856         2,
  19857         soc_CLMAC_RX_CDC_ECC_STATUS_BCM56860_A0r_fields,
  19858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19859         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19860         -1,
  19861         -1,
  19862     },
  19863 #endif /* chips */
  19864 
  19865 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19866     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM56960_A0r */
  19867         soc_block_list[16],
  19868         soc_portreg,
  19869         1,
  19870         0,
  19871         0x63100,
  19872         SOC_REG_FLAG_64_BITS |
  19873                           SOC_REG_FLAG_RO,
  19874         0,
  19875         2,
  19876         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19878         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19879         -1,
  19880         -1,
  19881         3,
  19882     },
  19883 #endif /* chips */
  19884 
  19885 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  19886     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  19887     defined(BCM_56980_B0)
  19888     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM56970_A0r */
  19889         soc_block_list[16],
  19890         soc_portreg,
  19891         1,
  19892         0,
  19893         0x63200,
  19894         SOC_REG_FLAG_64_BITS |
  19895                           SOC_REG_FLAG_RO,
  19896         0,
  19897         2,
  19898         soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  19899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19900         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19901         -1,
  19902         -1,
  19903         3,
  19904     },
  19905 #endif /* chips */
  19906 
  19907 #if defined(BCM_88270_A0)
  19908     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM88270_A0r */
  19909         soc_block_list[221],
  19910         soc_portreg,
  19911         1,
  19912         0,
  19913         0x63200,
  19914         SOC_REG_FLAG_64_BITS |
  19915                           SOC_REG_FLAG_RO |
  19916                           SOC_REG_FLAG_SIGNAL,
  19917         0,
  19918         2,
  19919         soc_XLMAC_RX_CDC_ECC_STATUS_BCM88270_A0r_fields,
  19920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19921         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19922         -1,
  19923         -1,
  19924     },
  19925 #endif /* chips */
  19926 
  19927 #if defined(BCM_88375_A0)
  19928     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM88375_A0r */
  19929         soc_block_list[56],
  19930         soc_portreg,
  19931         1,
  19932         0,
  19933         0x63100,
  19934         SOC_REG_FLAG_64_BITS |
  19935                           SOC_REG_FLAG_RO |
  19936                           SOC_REG_FLAG_SIGNAL,
  19937         0,
  19938         2,
  19939         soc_XLMAC_RX_CDC_ECC_STATUS_BCM88375_A0r_fields,
  19940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19941         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19942         -1,
  19943         -1,
  19944     },
  19945 #endif /* chips */
  19946 
  19947 #if defined(BCM_88375_B0)
  19948     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM88375_B0r */
  19949         soc_block_list[56],
  19950         soc_portreg,
  19951         1,
  19952         0,
  19953         0x63200,
  19954         SOC_REG_FLAG_64_BITS |
  19955                           SOC_REG_FLAG_RO |
  19956                           SOC_REG_FLAG_SIGNAL,
  19957         0,
  19958         2,
  19959         soc_XLMAC_RX_CDC_ECC_STATUS_BCM88375_B0r_fields,
  19960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19961         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19962         -1,
  19963         -1,
  19964     },
  19965 #endif /* chips */
  19966 
  19967 #if defined(BCM_88470_A0)
  19968     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM88470_A0r */
  19969         soc_block_list[56],
  19970         soc_portreg,
  19971         1,
  19972         0,
  19973         0x63100,
  19974         SOC_REG_FLAG_64_BITS |
  19975                           SOC_REG_FLAG_RO |
  19976                           SOC_REG_FLAG_SIGNAL,
  19977         0,
  19978         2,
  19979         soc_XLMAC_RX_CDC_ECC_STATUS_BCM88470_A0r_fields,
  19980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19981         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  19982         -1,
  19983         -1,
  19984     },
  19985 #endif /* chips */
  19986 
  19987 #if defined(BCM_88470_B0)
  19988     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM88470_B0r */
  19989         soc_block_list[56],
  19990         soc_portreg,
  19991         1,
  19992         0,
  19993         0x63200,
  19994         SOC_REG_FLAG_64_BITS |
  19995                           SOC_REG_FLAG_RO |
  19996                           SOC_REG_FLAG_SIGNAL,
  19997         0,
  19998         2,
  19999         soc_XLMAC_RX_CDC_ECC_STATUS_BCM88470_B0r_fields,
  20000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20001         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  20002         -1,
  20003         -1,
  20004     },
  20005 #endif /* chips */
  20006 
  20007 #if defined(BCM_88675_A0)
  20008     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM88675_A0r */
  20009         soc_block_list[56],
  20010         soc_portreg,
  20011         1,
  20012         0,
  20013         0x63100,
  20014         SOC_REG_FLAG_64_BITS |
  20015                           SOC_REG_FLAG_RO |
  20016                           SOC_REG_FLAG_SIGNAL,
  20017         0,
  20018         2,
  20019         soc_XLMAC_RX_CDC_ECC_STATUSr_fields,
  20020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20021         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  20022         -1,
  20023         -1,
  20024     },
  20025 #endif /* chips */
  20026 
  20027 #if defined(BCM_88675_B0)
  20028     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM88675_B0r */
  20029         soc_block_list[56],
  20030         soc_portreg,
  20031         1,
  20032         0,
  20033         0x63200,
  20034         SOC_REG_FLAG_64_BITS |
  20035                           SOC_REG_FLAG_RO |
  20036                           SOC_REG_FLAG_SIGNAL,
  20037         0,
  20038         2,
  20039         soc_XLMAC_RX_CDC_ECC_STATUS_BCM88675_B0r_fields,
  20040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20041         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  20042         -1,
  20043         -1,
  20044     },
  20045 #endif /* chips */
  20046 
  20047 #if defined(BCM_88680_A0)
  20048     { /* SOC_REG_INT_XLMAC_RX_CDC_ECC_STATUS_BCM88680_A0r */
  20049         soc_block_list[56],
  20050         soc_portreg,
  20051         1,
  20052         0,
  20053         0x63200,
  20054         SOC_REG_FLAG_64_BITS |
  20055                           SOC_REG_FLAG_RO |
  20056                           SOC_REG_FLAG_SIGNAL,
  20057         0,
  20058         2,
  20059         soc_XLMAC_RX_CDC_ECC_STATUS_BCM88680_A0r_fields,
  20060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20061         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  20062         -1,
  20063         -1,
  20064     },
  20065 #endif /* chips */
  20066 
  20067 #if defined(BCM_2801PM_A0)
  20068     { /* SOC_REG_INT_XLMAC_RX_CTRLr */
  20069         soc_block_list[56],
  20070         soc_portreg,
  20071         1,
  20072         0,
  20073         0x60600,
  20074         0,
  20075         0,
  20076         7,
  20077         soc_XLMAC_RX_CTRLr_fields,
  20078         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  20079         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20080         -1,
  20081         -1,
  20082     },
  20083 #endif /* chips */
  20084 
  20085 #if defined(BCM_53400_A0)
  20086     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM53400_A0r */
  20087         soc_block_list[16],
  20088         soc_portreg,
  20089         1,
  20090         0,
  20091         0x60600,
  20092         SOC_REG_FLAG_64_BITS,
  20093         0,
  20094         7,
  20095         soc_XLMAC_RX_CTRLr_fields,
  20096         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  20097         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20098         -1,
  20099         -1,
  20100     },
  20101 #endif /* chips */
  20102 
  20103 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  20104     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM53570_A0r */
  20105         soc_block_list[16],
  20106         soc_portreg,
  20107         1,
  20108         0,
  20109         0x60500,
  20110         SOC_REG_FLAG_64_BITS,
  20111         0,
  20112         10,
  20113         soc_XLMAC_RX_CTRL_BCM56970_A0r_fields,
  20114         SOC_RESET_VAL_DEC(0x00002404, 0x00000000)
  20115         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  20116         -1,
  20117         -1,
  20118     },
  20119 #endif /* chips */
  20120 
  20121 #if defined(BCM_56150_A0)
  20122     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56150_A0r */
  20123         soc_block_list[16],
  20124         soc_portreg,
  20125         1,
  20126         0,
  20127         0x60600,
  20128         SOC_REG_FLAG_64_BITS,
  20129         0,
  20130         7,
  20131         soc_XLMAC_RX_CTRL_BCM56850_A0r_fields,
  20132         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  20133         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20134         -1,
  20135         -1,
  20136     },
  20137 #endif /* chips */
  20138 
  20139 #if defined(BCM_56160_A0)
  20140     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56160_A0r */
  20141         soc_block_list[16],
  20142         soc_portreg,
  20143         1,
  20144         0,
  20145         0x60600,
  20146         SOC_REG_FLAG_64_BITS,
  20147         0,
  20148         7,
  20149         soc_XLMAC_B0_RX_CTRLr_fields,
  20150         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  20151         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20152         -1,
  20153         -1,
  20154     },
  20155 #endif /* chips */
  20156 
  20157 #if defined(BCM_56260_A0)
  20158     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56260_A0r */
  20159         soc_block_list[220],
  20160         soc_portreg,
  20161         1,
  20162         0,
  20163         0x60600,
  20164         SOC_REG_FLAG_64_BITS,
  20165         0,
  20166         7,
  20167         soc_XLMAC_RX_CTRLr_fields,
  20168         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  20169         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20170         -1,
  20171         -1,
  20172     },
  20173 #endif /* chips */
  20174 
  20175 #if defined(BCM_56260_B0)
  20176     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56260_B0r */
  20177         soc_block_list[220],
  20178         soc_portreg,
  20179         1,
  20180         0,
  20181         0x60600,
  20182         SOC_REG_FLAG_64_BITS,
  20183         0,
  20184         7,
  20185         soc_XLMAC_B0_RX_CTRLr_fields,
  20186         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  20187         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20188         -1,
  20189         -1,
  20190     },
  20191 #endif /* chips */
  20192 
  20193 #if defined(BCM_56270_A0)
  20194     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56270_A0r */
  20195         soc_block_list[220],
  20196         soc_portreg,
  20197         1,
  20198         0,
  20199         0x60600,
  20200         SOC_REG_FLAG_64_BITS,
  20201         0,
  20202         7,
  20203         soc_XLMAC_B0_RX_CTRLr_fields,
  20204         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  20205         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20206         -1,
  20207         -1,
  20208     },
  20209 #endif /* chips */
  20210 
  20211 #if defined(BCM_56370_A0)
  20212     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56370_A0r */
  20213         soc_block_list[16],
  20214         soc_portreg,
  20215         1,
  20216         0,
  20217         0x60600,
  20218         SOC_REG_FLAG_64_BITS,
  20219         0,
  20220         10,
  20221         soc_XLMAC_RX_CTRL_BCM56970_A0r_fields,
  20222         SOC_RESET_VAL_DEC(0x00002404, 0x00000000)
  20223         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  20224         -1,
  20225         -1,
  20226         3,
  20227     },
  20228 #endif /* chips */
  20229 
  20230 #if defined(BCM_56560_A0)
  20231     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56560_A0r */
  20232         soc_block_list[16],
  20233         soc_portreg,
  20234         1,
  20235         0,
  20236         0x60600,
  20237         SOC_REG_FLAG_64_BITS,
  20238         0,
  20239         7,
  20240         soc_XLMAC_RX_CTRLr_fields,
  20241         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  20242         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20243         -1,
  20244         -1,
  20245     },
  20246 #endif /* chips */
  20247 
  20248 #if defined(BCM_56560_B0)
  20249     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56560_B0r */
  20250         soc_block_list[16],
  20251         soc_portreg,
  20252         1,
  20253         0,
  20254         0x60600,
  20255         SOC_REG_FLAG_64_BITS,
  20256         0,
  20257         7,
  20258         soc_XLMAC_B0_RX_CTRLr_fields,
  20259         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  20260         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20261         -1,
  20262         -1,
  20263     },
  20264 #endif /* chips */
  20265 
  20266 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  20267     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56670_A0r */
  20268         soc_block_list[16],
  20269         soc_portreg,
  20270         1,
  20271         0,
  20272         0x60500,
  20273         SOC_REG_FLAG_64_BITS,
  20274         0,
  20275         10,
  20276         soc_XLMAC_RX_CTRL_BCM56970_A0r_fields,
  20277         SOC_RESET_VAL_DEC(0x00002404, 0x00000000)
  20278         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  20279         -1,
  20280         -1,
  20281     },
  20282 #endif /* chips */
  20283 
  20284 #if defined(BCM_56850_A0)
  20285     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56850_A0r */
  20286         soc_block_list[16],
  20287         soc_portreg,
  20288         1,
  20289         0,
  20290         0x60600,
  20291         SOC_REG_FLAG_64_BITS,
  20292         0,
  20293         7,
  20294         soc_XLMAC_RX_CTRL_BCM56850_A0r_fields,
  20295         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  20296         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20297         -1,
  20298         -1,
  20299     },
  20300 #endif /* chips */
  20301 
  20302 #if defined(BCM_56860_A0)
  20303     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56860_A0r */
  20304         soc_block_list[16],
  20305         soc_portreg,
  20306         1,
  20307         0,
  20308         0x60600,
  20309         SOC_REG_FLAG_64_BITS,
  20310         0,
  20311         7,
  20312         soc_XLMAC_RX_CTRL_BCM56860_A0r_fields,
  20313         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  20314         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20315         -1,
  20316         -1,
  20317     },
  20318 #endif /* chips */
  20319 
  20320 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20321     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56960_A0r */
  20322         soc_block_list[16],
  20323         soc_portreg,
  20324         1,
  20325         0,
  20326         0x60600,
  20327         SOC_REG_FLAG_64_BITS,
  20328         0,
  20329         7,
  20330         soc_XLMAC_RX_CTRLr_fields,
  20331         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  20332         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20333         -1,
  20334         -1,
  20335         3,
  20336     },
  20337 #endif /* chips */
  20338 
  20339 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  20340     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  20341     defined(BCM_56980_B0)
  20342     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM56970_A0r */
  20343         soc_block_list[16],
  20344         soc_portreg,
  20345         1,
  20346         0,
  20347         0x60600,
  20348         SOC_REG_FLAG_64_BITS,
  20349         0,
  20350         10,
  20351         soc_XLMAC_RX_CTRL_BCM56970_A0r_fields,
  20352         SOC_RESET_VAL_DEC(0x00002404, 0x00000000)
  20353         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  20354         -1,
  20355         -1,
  20356         3,
  20357     },
  20358 #endif /* chips */
  20359 
  20360 #if defined(BCM_88270_A0)
  20361     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM88270_A0r */
  20362         soc_block_list[221],
  20363         soc_portreg,
  20364         1,
  20365         0,
  20366         0x60600,
  20367         SOC_REG_FLAG_64_BITS,
  20368         0,
  20369         7,
  20370         soc_XLMAC_RX_CTRL_BCM88270_A0r_fields,
  20371         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  20372         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20373         -1,
  20374         -1,
  20375     },
  20376 #endif /* chips */
  20377 
  20378 #if defined(BCM_88375_A0)
  20379     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM88375_A0r */
  20380         soc_block_list[56],
  20381         soc_portreg,
  20382         1,
  20383         0,
  20384         0x60600,
  20385         SOC_REG_FLAG_64_BITS,
  20386         0,
  20387         7,
  20388         soc_XLMAC_RX_CTRL_BCM88375_A0r_fields,
  20389         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  20390         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20391         -1,
  20392         -1,
  20393     },
  20394 #endif /* chips */
  20395 
  20396 #if defined(BCM_88375_B0)
  20397     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM88375_B0r */
  20398         soc_block_list[56],
  20399         soc_portreg,
  20400         1,
  20401         0,
  20402         0x60600,
  20403         SOC_REG_FLAG_64_BITS,
  20404         0,
  20405         7,
  20406         soc_XLMAC_RX_CTRL_BCM88375_B0r_fields,
  20407         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  20408         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20409         -1,
  20410         -1,
  20411     },
  20412 #endif /* chips */
  20413 
  20414 #if defined(BCM_88470_A0)
  20415     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM88470_A0r */
  20416         soc_block_list[56],
  20417         soc_portreg,
  20418         1,
  20419         0,
  20420         0x60600,
  20421         SOC_REG_FLAG_64_BITS,
  20422         0,
  20423         7,
  20424         soc_XLMAC_RX_CTRL_BCM88470_A0r_fields,
  20425         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  20426         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20427         -1,
  20428         -1,
  20429     },
  20430 #endif /* chips */
  20431 
  20432 #if defined(BCM_88470_B0)
  20433     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM88470_B0r */
  20434         soc_block_list[56],
  20435         soc_portreg,
  20436         1,
  20437         0,
  20438         0x60600,
  20439         SOC_REG_FLAG_64_BITS,
  20440         0,
  20441         7,
  20442         soc_XLMAC_RX_CTRL_BCM88470_B0r_fields,
  20443         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  20444         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20445         -1,
  20446         -1,
  20447     },
  20448 #endif /* chips */
  20449 
  20450 #if defined(BCM_88675_A0)
  20451     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM88675_A0r */
  20452         soc_block_list[56],
  20453         soc_portreg,
  20454         1,
  20455         0,
  20456         0x60600,
  20457         SOC_REG_FLAG_64_BITS,
  20458         0,
  20459         7,
  20460         soc_XLMAC_RX_CTRL_BCM88675_A0r_fields,
  20461         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  20462         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20463         -1,
  20464         -1,
  20465     },
  20466 #endif /* chips */
  20467 
  20468 #if defined(BCM_88675_B0)
  20469     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM88675_B0r */
  20470         soc_block_list[56],
  20471         soc_portreg,
  20472         1,
  20473         0,
  20474         0x60600,
  20475         SOC_REG_FLAG_64_BITS,
  20476         0,
  20477         7,
  20478         soc_XLMAC_RX_CTRL_BCM88675_B0r_fields,
  20479         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  20480         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20481         -1,
  20482         -1,
  20483     },
  20484 #endif /* chips */
  20485 
  20486 #if defined(BCM_88680_A0)
  20487     { /* SOC_REG_INT_XLMAC_RX_CTRL_BCM88680_A0r */
  20488         soc_block_list[56],
  20489         soc_portreg,
  20490         1,
  20491         0,
  20492         0x60600,
  20493         SOC_REG_FLAG_64_BITS,
  20494         0,
  20495         7,
  20496         soc_XLMAC_RX_CTRL_BCM88680_A0r_fields,
  20497         SOC_RESET_VAL_DEC(0x00000404, 0x00000000)
  20498         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  20499         -1,
  20500         -1,
  20501     },
  20502 #endif /* chips */
  20503 
  20504 #if defined(BCM_2801PM_A0)
  20505     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDSr */
  20506         soc_block_list[56],
  20507         soc_portreg,
  20508         1,
  20509         0,
  20510         0x61400,
  20511         0,
  20512         0,
  20513         4,
  20514         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20515         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20516         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20517         -1,
  20518         -1,
  20519     },
  20520 #endif /* chips */
  20521 
  20522 #if defined(BCM_53400_A0)
  20523     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM53400_A0r */
  20524         soc_block_list[16],
  20525         soc_portreg,
  20526         1,
  20527         0,
  20528         0x61400,
  20529         SOC_REG_FLAG_64_BITS,
  20530         0,
  20531         4,
  20532         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20533         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20534         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20535         -1,
  20536         -1,
  20537     },
  20538 #endif /* chips */
  20539 
  20540 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  20541     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM53570_A0r */
  20542         soc_block_list[16],
  20543         soc_portreg,
  20544         1,
  20545         0,
  20546         0x61300,
  20547         SOC_REG_FLAG_64_BITS,
  20548         0,
  20549         4,
  20550         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20551         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20552         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20553         -1,
  20554         -1,
  20555     },
  20556 #endif /* chips */
  20557 
  20558 #if defined(BCM_56150_A0)
  20559     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM56150_A0r */
  20560         soc_block_list[16],
  20561         soc_portreg,
  20562         1,
  20563         0,
  20564         0x61400,
  20565         SOC_REG_FLAG_64_BITS,
  20566         0,
  20567         4,
  20568         soc_CMAC_RX_LLFC_MSG_FIELDSr_fields,
  20569         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20570         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20571         -1,
  20572         -1,
  20573     },
  20574 #endif /* chips */
  20575 
  20576 #if defined(BCM_56160_A0)
  20577     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM56160_A0r */
  20578         soc_block_list[16],
  20579         soc_portreg,
  20580         1,
  20581         0,
  20582         0x61400,
  20583         SOC_REG_FLAG_64_BITS,
  20584         0,
  20585         4,
  20586         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20587         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20588         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20589         -1,
  20590         -1,
  20591     },
  20592 #endif /* chips */
  20593 
  20594 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  20595     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM56260_A0r */
  20596         soc_block_list[220],
  20597         soc_portreg,
  20598         1,
  20599         0,
  20600         0x61400,
  20601         SOC_REG_FLAG_64_BITS,
  20602         0,
  20603         4,
  20604         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20605         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20606         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20607         -1,
  20608         -1,
  20609     },
  20610 #endif /* chips */
  20611 
  20612 #if defined(BCM_56270_A0)
  20613     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM56270_A0r */
  20614         soc_block_list[220],
  20615         soc_portreg,
  20616         1,
  20617         0,
  20618         0x61400,
  20619         SOC_REG_FLAG_64_BITS,
  20620         0,
  20621         4,
  20622         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20623         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20624         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20625         -1,
  20626         -1,
  20627     },
  20628 #endif /* chips */
  20629 
  20630 #if defined(BCM_56370_A0)
  20631     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM56370_A0r */
  20632         soc_block_list[16],
  20633         soc_portreg,
  20634         1,
  20635         0,
  20636         0x61400,
  20637         SOC_REG_FLAG_64_BITS,
  20638         0,
  20639         4,
  20640         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20641         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20642         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20643         -1,
  20644         -1,
  20645         3,
  20646     },
  20647 #endif /* chips */
  20648 
  20649 #if defined(BCM_56560_A0)
  20650     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM56560_A0r */
  20651         soc_block_list[16],
  20652         soc_portreg,
  20653         1,
  20654         0,
  20655         0x61400,
  20656         SOC_REG_FLAG_64_BITS,
  20657         0,
  20658         4,
  20659         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20660         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20661         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20662         -1,
  20663         -1,
  20664     },
  20665 #endif /* chips */
  20666 
  20667 #if defined(BCM_56560_B0)
  20668     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM56560_B0r */
  20669         soc_block_list[16],
  20670         soc_portreg,
  20671         1,
  20672         0,
  20673         0x61400,
  20674         SOC_REG_FLAG_64_BITS,
  20675         0,
  20676         4,
  20677         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20678         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20679         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20680         -1,
  20681         -1,
  20682     },
  20683 #endif /* chips */
  20684 
  20685 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  20686     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM56670_A0r */
  20687         soc_block_list[16],
  20688         soc_portreg,
  20689         1,
  20690         0,
  20691         0x61300,
  20692         SOC_REG_FLAG_64_BITS,
  20693         0,
  20694         4,
  20695         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20696         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20697         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20698         -1,
  20699         -1,
  20700     },
  20701 #endif /* chips */
  20702 
  20703 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  20704     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM56850_A0r */
  20705         soc_block_list[16],
  20706         soc_portreg,
  20707         1,
  20708         0,
  20709         0x61400,
  20710         SOC_REG_FLAG_64_BITS,
  20711         0,
  20712         4,
  20713         soc_CMAC_RX_LLFC_MSG_FIELDSr_fields,
  20714         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20715         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20716         -1,
  20717         -1,
  20718     },
  20719 #endif /* chips */
  20720 
  20721 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  20722     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  20723     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  20724     defined(BCM_56980_B0)
  20725     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM56960_A0r */
  20726         soc_block_list[16],
  20727         soc_portreg,
  20728         1,
  20729         0,
  20730         0x61400,
  20731         SOC_REG_FLAG_64_BITS,
  20732         0,
  20733         4,
  20734         soc_CLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20735         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20736         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20737         -1,
  20738         -1,
  20739         3,
  20740     },
  20741 #endif /* chips */
  20742 
  20743 #if defined(BCM_88270_A0)
  20744     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM88270_A0r */
  20745         soc_block_list[221],
  20746         soc_portreg,
  20747         1,
  20748         0,
  20749         0x61400,
  20750         SOC_REG_FLAG_64_BITS,
  20751         0,
  20752         4,
  20753         soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88270_A0r_fields,
  20754         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20755         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20756         -1,
  20757         -1,
  20758     },
  20759 #endif /* chips */
  20760 
  20761 #if defined(BCM_88375_A0)
  20762     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM88375_A0r */
  20763         soc_block_list[56],
  20764         soc_portreg,
  20765         1,
  20766         0,
  20767         0x61400,
  20768         SOC_REG_FLAG_64_BITS,
  20769         0,
  20770         4,
  20771         soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88375_A0r_fields,
  20772         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20773         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20774         -1,
  20775         -1,
  20776     },
  20777 #endif /* chips */
  20778 
  20779 #if defined(BCM_88375_B0)
  20780     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM88375_B0r */
  20781         soc_block_list[56],
  20782         soc_portreg,
  20783         1,
  20784         0,
  20785         0x61400,
  20786         SOC_REG_FLAG_64_BITS,
  20787         0,
  20788         4,
  20789         soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88375_B0r_fields,
  20790         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20791         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20792         -1,
  20793         -1,
  20794     },
  20795 #endif /* chips */
  20796 
  20797 #if defined(BCM_88470_A0)
  20798     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM88470_A0r */
  20799         soc_block_list[56],
  20800         soc_portreg,
  20801         1,
  20802         0,
  20803         0x61400,
  20804         SOC_REG_FLAG_64_BITS,
  20805         0,
  20806         4,
  20807         soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88470_A0r_fields,
  20808         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20809         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20810         -1,
  20811         -1,
  20812     },
  20813 #endif /* chips */
  20814 
  20815 #if defined(BCM_88470_B0)
  20816     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM88470_B0r */
  20817         soc_block_list[56],
  20818         soc_portreg,
  20819         1,
  20820         0,
  20821         0x61400,
  20822         SOC_REG_FLAG_64_BITS,
  20823         0,
  20824         4,
  20825         soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88470_B0r_fields,
  20826         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20827         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20828         -1,
  20829         -1,
  20830     },
  20831 #endif /* chips */
  20832 
  20833 #if defined(BCM_88675_A0)
  20834     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM88675_A0r */
  20835         soc_block_list[56],
  20836         soc_portreg,
  20837         1,
  20838         0,
  20839         0x61400,
  20840         SOC_REG_FLAG_64_BITS,
  20841         0,
  20842         4,
  20843         soc_XLMAC_RX_LLFC_MSG_FIELDSr_fields,
  20844         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20845         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20846         -1,
  20847         -1,
  20848     },
  20849 #endif /* chips */
  20850 
  20851 #if defined(BCM_88675_B0)
  20852     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM88675_B0r */
  20853         soc_block_list[56],
  20854         soc_portreg,
  20855         1,
  20856         0,
  20857         0x61400,
  20858         SOC_REG_FLAG_64_BITS,
  20859         0,
  20860         4,
  20861         soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88675_B0r_fields,
  20862         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20863         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20864         -1,
  20865         -1,
  20866     },
  20867 #endif /* chips */
  20868 
  20869 #if defined(BCM_88680_A0)
  20870     { /* SOC_REG_INT_XLMAC_RX_LLFC_MSG_FIELDS_BCM88680_A0r */
  20871         soc_block_list[56],
  20872         soc_portreg,
  20873         1,
  20874         0,
  20875         0x61400,
  20876         SOC_REG_FLAG_64_BITS,
  20877         0,
  20878         4,
  20879         soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88680_A0r_fields,
  20880         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  20881         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  20882         -1,
  20883         -1,
  20884     },
  20885 #endif /* chips */
  20886 
  20887 #if defined(BCM_2801PM_A0)
  20888     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRLr */
  20889         soc_block_list[56],
  20890         soc_portreg,
  20891         1,
  20892         0,
  20893         0x60a00,
  20894         0,
  20895         0,
  20896         8,
  20897         soc_XLMAC_RX_LSS_CTRLr_fields,
  20898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20899         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  20900         -1,
  20901         -1,
  20902     },
  20903 #endif /* chips */
  20904 
  20905 #if defined(BCM_53400_A0)
  20906     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM53400_A0r */
  20907         soc_block_list[16],
  20908         soc_portreg,
  20909         1,
  20910         0,
  20911         0x60a00,
  20912         SOC_REG_FLAG_64_BITS,
  20913         0,
  20914         8,
  20915         soc_XLMAC_RX_LSS_CTRLr_fields,
  20916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20917         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  20918         -1,
  20919         -1,
  20920     },
  20921 #endif /* chips */
  20922 
  20923 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  20924     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM53570_A0r */
  20925         soc_block_list[16],
  20926         soc_portreg,
  20927         1,
  20928         0,
  20929         0x60900,
  20930         SOC_REG_FLAG_64_BITS,
  20931         0,
  20932         8,
  20933         soc_CLMAC_RX_LSS_CTRLr_fields,
  20934         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  20935         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  20936         -1,
  20937         -1,
  20938     },
  20939 #endif /* chips */
  20940 
  20941 #if defined(BCM_56150_A0)
  20942     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56150_A0r */
  20943         soc_block_list[16],
  20944         soc_portreg,
  20945         1,
  20946         0,
  20947         0x60a00,
  20948         SOC_REG_FLAG_64_BITS,
  20949         0,
  20950         8,
  20951         soc_XMAC_RX_LSS_CTRL_BCM56640_A0r_fields,
  20952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20953         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  20954         -1,
  20955         -1,
  20956     },
  20957 #endif /* chips */
  20958 
  20959 #if defined(BCM_56160_A0)
  20960     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56160_A0r */
  20961         soc_block_list[16],
  20962         soc_portreg,
  20963         1,
  20964         0,
  20965         0x60a00,
  20966         SOC_REG_FLAG_64_BITS,
  20967         0,
  20968         8,
  20969         soc_CLMAC_RX_LSS_CTRLr_fields,
  20970         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  20971         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  20972         -1,
  20973         -1,
  20974     },
  20975 #endif /* chips */
  20976 
  20977 #if defined(BCM_56260_A0)
  20978     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56260_A0r */
  20979         soc_block_list[220],
  20980         soc_portreg,
  20981         1,
  20982         0,
  20983         0x60a00,
  20984         SOC_REG_FLAG_64_BITS,
  20985         0,
  20986         8,
  20987         soc_XLMAC_RX_LSS_CTRLr_fields,
  20988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20989         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  20990         -1,
  20991         -1,
  20992     },
  20993 #endif /* chips */
  20994 
  20995 #if defined(BCM_56260_B0)
  20996     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56260_B0r */
  20997         soc_block_list[220],
  20998         soc_portreg,
  20999         1,
  21000         0,
  21001         0x60a00,
  21002         SOC_REG_FLAG_64_BITS,
  21003         0,
  21004         8,
  21005         soc_CLMAC_RX_LSS_CTRLr_fields,
  21006         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21007         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21008         -1,
  21009         -1,
  21010     },
  21011 #endif /* chips */
  21012 
  21013 #if defined(BCM_56270_A0)
  21014     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56270_A0r */
  21015         soc_block_list[220],
  21016         soc_portreg,
  21017         1,
  21018         0,
  21019         0x60a00,
  21020         SOC_REG_FLAG_64_BITS,
  21021         0,
  21022         8,
  21023         soc_CLMAC_RX_LSS_CTRLr_fields,
  21024         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21025         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21026         -1,
  21027         -1,
  21028     },
  21029 #endif /* chips */
  21030 
  21031 #if defined(BCM_56370_A0)
  21032     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56370_A0r */
  21033         soc_block_list[16],
  21034         soc_portreg,
  21035         1,
  21036         0,
  21037         0x60a00,
  21038         SOC_REG_FLAG_64_BITS,
  21039         0,
  21040         8,
  21041         soc_CLMAC_RX_LSS_CTRLr_fields,
  21042         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21043         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21044         -1,
  21045         -1,
  21046         3,
  21047     },
  21048 #endif /* chips */
  21049 
  21050 #if defined(BCM_56560_A0)
  21051     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56560_A0r */
  21052         soc_block_list[16],
  21053         soc_portreg,
  21054         1,
  21055         0,
  21056         0x60a00,
  21057         SOC_REG_FLAG_64_BITS,
  21058         0,
  21059         8,
  21060         soc_XLMAC_RX_LSS_CTRLr_fields,
  21061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21062         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21063         -1,
  21064         -1,
  21065     },
  21066 #endif /* chips */
  21067 
  21068 #if defined(BCM_56560_B0)
  21069     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56560_B0r */
  21070         soc_block_list[16],
  21071         soc_portreg,
  21072         1,
  21073         0,
  21074         0x60a00,
  21075         SOC_REG_FLAG_64_BITS,
  21076         0,
  21077         8,
  21078         soc_CLMAC_RX_LSS_CTRLr_fields,
  21079         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21080         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21081         -1,
  21082         -1,
  21083     },
  21084 #endif /* chips */
  21085 
  21086 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  21087     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56670_A0r */
  21088         soc_block_list[16],
  21089         soc_portreg,
  21090         1,
  21091         0,
  21092         0x60900,
  21093         SOC_REG_FLAG_64_BITS,
  21094         0,
  21095         8,
  21096         soc_CLMAC_RX_LSS_CTRLr_fields,
  21097         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21098         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21099         -1,
  21100         -1,
  21101     },
  21102 #endif /* chips */
  21103 
  21104 #if defined(BCM_56850_A0)
  21105     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56850_A0r */
  21106         soc_block_list[16],
  21107         soc_portreg,
  21108         1,
  21109         0,
  21110         0x60a00,
  21111         SOC_REG_FLAG_64_BITS,
  21112         0,
  21113         8,
  21114         soc_XMAC_RX_LSS_CTRL_BCM56640_A0r_fields,
  21115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21116         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21117         -1,
  21118         -1,
  21119     },
  21120 #endif /* chips */
  21121 
  21122 #if defined(BCM_56860_A0)
  21123     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56860_A0r */
  21124         soc_block_list[16],
  21125         soc_portreg,
  21126         1,
  21127         0,
  21128         0x60a00,
  21129         SOC_REG_FLAG_64_BITS,
  21130         0,
  21131         8,
  21132         soc_CLMAC_RX_LSS_CTRL_BCM56860_A0r_fields,
  21133         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21134         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21135         -1,
  21136         -1,
  21137     },
  21138 #endif /* chips */
  21139 
  21140 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21141     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56960_A0r */
  21142         soc_block_list[16],
  21143         soc_portreg,
  21144         1,
  21145         0,
  21146         0x60a00,
  21147         SOC_REG_FLAG_64_BITS,
  21148         0,
  21149         8,
  21150         soc_XLMAC_RX_LSS_CTRLr_fields,
  21151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21152         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21153         -1,
  21154         -1,
  21155         3,
  21156     },
  21157 #endif /* chips */
  21158 
  21159 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  21160     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  21161     defined(BCM_56980_B0)
  21162     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM56970_A0r */
  21163         soc_block_list[16],
  21164         soc_portreg,
  21165         1,
  21166         0,
  21167         0x60a00,
  21168         SOC_REG_FLAG_64_BITS,
  21169         0,
  21170         8,
  21171         soc_CLMAC_RX_LSS_CTRLr_fields,
  21172         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21173         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21174         -1,
  21175         -1,
  21176         3,
  21177     },
  21178 #endif /* chips */
  21179 
  21180 #if defined(BCM_88270_A0)
  21181     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM88270_A0r */
  21182         soc_block_list[221],
  21183         soc_portreg,
  21184         1,
  21185         0,
  21186         0x60a00,
  21187         SOC_REG_FLAG_64_BITS,
  21188         0,
  21189         8,
  21190         soc_XLMAC_RX_LSS_CTRL_BCM88270_A0r_fields,
  21191         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21192         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21193         -1,
  21194         -1,
  21195     },
  21196 #endif /* chips */
  21197 
  21198 #if defined(BCM_88375_A0)
  21199     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM88375_A0r */
  21200         soc_block_list[56],
  21201         soc_portreg,
  21202         1,
  21203         0,
  21204         0x60a00,
  21205         SOC_REG_FLAG_64_BITS,
  21206         0,
  21207         8,
  21208         soc_XLMAC_RX_LSS_CTRL_BCM88375_A0r_fields,
  21209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21210         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21211         -1,
  21212         -1,
  21213     },
  21214 #endif /* chips */
  21215 
  21216 #if defined(BCM_88375_B0)
  21217     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM88375_B0r */
  21218         soc_block_list[56],
  21219         soc_portreg,
  21220         1,
  21221         0,
  21222         0x60a00,
  21223         SOC_REG_FLAG_64_BITS,
  21224         0,
  21225         8,
  21226         soc_XLMAC_RX_LSS_CTRL_BCM88375_B0r_fields,
  21227         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21228         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21229         -1,
  21230         -1,
  21231     },
  21232 #endif /* chips */
  21233 
  21234 #if defined(BCM_88470_A0)
  21235     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM88470_A0r */
  21236         soc_block_list[56],
  21237         soc_portreg,
  21238         1,
  21239         0,
  21240         0x60a00,
  21241         SOC_REG_FLAG_64_BITS,
  21242         0,
  21243         8,
  21244         soc_XLMAC_RX_LSS_CTRL_BCM88470_A0r_fields,
  21245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21246         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21247         -1,
  21248         -1,
  21249     },
  21250 #endif /* chips */
  21251 
  21252 #if defined(BCM_88470_B0)
  21253     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM88470_B0r */
  21254         soc_block_list[56],
  21255         soc_portreg,
  21256         1,
  21257         0,
  21258         0x60a00,
  21259         SOC_REG_FLAG_64_BITS,
  21260         0,
  21261         8,
  21262         soc_XLMAC_RX_LSS_CTRL_BCM88470_B0r_fields,
  21263         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21264         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21265         -1,
  21266         -1,
  21267     },
  21268 #endif /* chips */
  21269 
  21270 #if defined(BCM_88675_A0)
  21271     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM88675_A0r */
  21272         soc_block_list[56],
  21273         soc_portreg,
  21274         1,
  21275         0,
  21276         0x60a00,
  21277         SOC_REG_FLAG_64_BITS,
  21278         0,
  21279         8,
  21280         soc_XLMAC_RX_LSS_CTRL_BCM88675_A0r_fields,
  21281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21282         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21283         -1,
  21284         -1,
  21285     },
  21286 #endif /* chips */
  21287 
  21288 #if defined(BCM_88675_B0)
  21289     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM88675_B0r */
  21290         soc_block_list[56],
  21291         soc_portreg,
  21292         1,
  21293         0,
  21294         0x60a00,
  21295         SOC_REG_FLAG_64_BITS,
  21296         0,
  21297         8,
  21298         soc_XLMAC_RX_LSS_CTRL_BCM88675_B0r_fields,
  21299         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21300         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21301         -1,
  21302         -1,
  21303     },
  21304 #endif /* chips */
  21305 
  21306 #if defined(BCM_88680_A0)
  21307     { /* SOC_REG_INT_XLMAC_RX_LSS_CTRL_BCM88680_A0r */
  21308         soc_block_list[56],
  21309         soc_portreg,
  21310         1,
  21311         0,
  21312         0x60a00,
  21313         SOC_REG_FLAG_64_BITS,
  21314         0,
  21315         8,
  21316         soc_XLMAC_RX_LSS_CTRL_BCM88680_A0r_fields,
  21317         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  21318         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21319         -1,
  21320         -1,
  21321     },
  21322 #endif /* chips */
  21323 
  21324 #if defined(BCM_2801PM_A0)
  21325     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUSr */
  21326         soc_block_list[56],
  21327         soc_portreg,
  21328         1,
  21329         0,
  21330         0x60b00,
  21331         SOC_REG_FLAG_RO,
  21332         0,
  21333         3,
  21334         soc_CLMAC_RX_LSS_STATUSr_fields,
  21335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21336         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21337         -1,
  21338         -1,
  21339     },
  21340 #endif /* chips */
  21341 
  21342 #if defined(BCM_53400_A0)
  21343     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM53400_A0r */
  21344         soc_block_list[16],
  21345         soc_portreg,
  21346         1,
  21347         0,
  21348         0x60b00,
  21349         SOC_REG_FLAG_64_BITS |
  21350                           SOC_REG_FLAG_RO,
  21351         0,
  21352         3,
  21353         soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields,
  21354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21355         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21356         -1,
  21357         -1,
  21358     },
  21359 #endif /* chips */
  21360 
  21361 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  21362     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM53570_A0r */
  21363         soc_block_list[16],
  21364         soc_portreg,
  21365         1,
  21366         0,
  21367         0x60a00,
  21368         SOC_REG_FLAG_64_BITS |
  21369                           SOC_REG_FLAG_RO,
  21370         0,
  21371         3,
  21372         soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields,
  21373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21374         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21375         -1,
  21376         -1,
  21377     },
  21378 #endif /* chips */
  21379 
  21380 #if defined(BCM_56150_A0)
  21381     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM56150_A0r */
  21382         soc_block_list[16],
  21383         soc_portreg,
  21384         1,
  21385         0,
  21386         0x60b00,
  21387         SOC_REG_FLAG_64_BITS |
  21388                           SOC_REG_FLAG_RO,
  21389         0,
  21390         3,
  21391         soc_XMAC_RX_LSS_STATUS_BCM56640_A0r_fields,
  21392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21393         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21394         -1,
  21395         -1,
  21396     },
  21397 #endif /* chips */
  21398 
  21399 #if defined(BCM_56160_A0)
  21400     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM56160_A0r */
  21401         soc_block_list[16],
  21402         soc_portreg,
  21403         1,
  21404         0,
  21405         0x60b00,
  21406         SOC_REG_FLAG_64_BITS |
  21407                           SOC_REG_FLAG_RO,
  21408         0,
  21409         3,
  21410         soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields,
  21411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21412         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21413         -1,
  21414         -1,
  21415     },
  21416 #endif /* chips */
  21417 
  21418 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  21419     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM56260_A0r */
  21420         soc_block_list[220],
  21421         soc_portreg,
  21422         1,
  21423         0,
  21424         0x60b00,
  21425         SOC_REG_FLAG_64_BITS |
  21426                           SOC_REG_FLAG_RO,
  21427         0,
  21428         3,
  21429         soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields,
  21430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21431         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21432         -1,
  21433         -1,
  21434     },
  21435 #endif /* chips */
  21436 
  21437 #if defined(BCM_56270_A0)
  21438     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM56270_A0r */
  21439         soc_block_list[220],
  21440         soc_portreg,
  21441         1,
  21442         0,
  21443         0x60b00,
  21444         SOC_REG_FLAG_64_BITS |
  21445                           SOC_REG_FLAG_RO,
  21446         0,
  21447         3,
  21448         soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields,
  21449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21450         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21451         -1,
  21452         -1,
  21453     },
  21454 #endif /* chips */
  21455 
  21456 #if defined(BCM_56370_A0)
  21457     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM56370_A0r */
  21458         soc_block_list[16],
  21459         soc_portreg,
  21460         1,
  21461         0,
  21462         0x60b00,
  21463         SOC_REG_FLAG_64_BITS |
  21464                           SOC_REG_FLAG_RO,
  21465         0,
  21466         3,
  21467         soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields,
  21468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21469         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21470         -1,
  21471         -1,
  21472         3,
  21473     },
  21474 #endif /* chips */
  21475 
  21476 #if defined(BCM_56560_A0)
  21477     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM56560_A0r */
  21478         soc_block_list[16],
  21479         soc_portreg,
  21480         1,
  21481         0,
  21482         0x60b00,
  21483         SOC_REG_FLAG_64_BITS |
  21484                           SOC_REG_FLAG_RO,
  21485         0,
  21486         3,
  21487         soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields,
  21488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21489         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21490         -1,
  21491         -1,
  21492     },
  21493 #endif /* chips */
  21494 
  21495 #if defined(BCM_56560_B0)
  21496     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM56560_B0r */
  21497         soc_block_list[16],
  21498         soc_portreg,
  21499         1,
  21500         0,
  21501         0x60b00,
  21502         SOC_REG_FLAG_64_BITS |
  21503                           SOC_REG_FLAG_RO,
  21504         0,
  21505         3,
  21506         soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields,
  21507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21508         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21509         -1,
  21510         -1,
  21511     },
  21512 #endif /* chips */
  21513 
  21514 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  21515     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM56670_A0r */
  21516         soc_block_list[16],
  21517         soc_portreg,
  21518         1,
  21519         0,
  21520         0x60a00,
  21521         SOC_REG_FLAG_64_BITS |
  21522                           SOC_REG_FLAG_RO,
  21523         0,
  21524         3,
  21525         soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields,
  21526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21527         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21528         -1,
  21529         -1,
  21530     },
  21531 #endif /* chips */
  21532 
  21533 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  21534     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM56850_A0r */
  21535         soc_block_list[16],
  21536         soc_portreg,
  21537         1,
  21538         0,
  21539         0x60b00,
  21540         SOC_REG_FLAG_64_BITS |
  21541                           SOC_REG_FLAG_RO,
  21542         0,
  21543         3,
  21544         soc_XMAC_RX_LSS_STATUS_BCM56640_A0r_fields,
  21545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21546         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21547         -1,
  21548         -1,
  21549     },
  21550 #endif /* chips */
  21551 
  21552 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  21553     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  21554     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  21555     defined(BCM_56980_B0)
  21556     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM56960_A0r */
  21557         soc_block_list[16],
  21558         soc_portreg,
  21559         1,
  21560         0,
  21561         0x60b00,
  21562         SOC_REG_FLAG_64_BITS |
  21563                           SOC_REG_FLAG_RO,
  21564         0,
  21565         3,
  21566         soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields,
  21567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21568         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21569         -1,
  21570         -1,
  21571         3,
  21572     },
  21573 #endif /* chips */
  21574 
  21575 #if defined(BCM_88270_A0)
  21576     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM88270_A0r */
  21577         soc_block_list[221],
  21578         soc_portreg,
  21579         1,
  21580         0,
  21581         0x60b00,
  21582         SOC_REG_FLAG_64_BITS |
  21583                           SOC_REG_FLAG_RO,
  21584         0,
  21585         3,
  21586         soc_XLMAC_RX_LSS_STATUS_BCM88270_A0r_fields,
  21587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21588         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21589         -1,
  21590         -1,
  21591     },
  21592 #endif /* chips */
  21593 
  21594 #if defined(BCM_88375_A0)
  21595     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM88375_A0r */
  21596         soc_block_list[56],
  21597         soc_portreg,
  21598         1,
  21599         0,
  21600         0x60b00,
  21601         SOC_REG_FLAG_64_BITS |
  21602                           SOC_REG_FLAG_RO,
  21603         0,
  21604         3,
  21605         soc_XLMAC_RX_LSS_STATUS_BCM88375_A0r_fields,
  21606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21607         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21608         -1,
  21609         -1,
  21610     },
  21611 #endif /* chips */
  21612 
  21613 #if defined(BCM_88375_B0)
  21614     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM88375_B0r */
  21615         soc_block_list[56],
  21616         soc_portreg,
  21617         1,
  21618         0,
  21619         0x60b00,
  21620         SOC_REG_FLAG_64_BITS |
  21621                           SOC_REG_FLAG_RO,
  21622         0,
  21623         3,
  21624         soc_XLMAC_RX_LSS_STATUS_BCM88375_B0r_fields,
  21625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21626         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21627         -1,
  21628         -1,
  21629     },
  21630 #endif /* chips */
  21631 
  21632 #if defined(BCM_88470_A0)
  21633     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM88470_A0r */
  21634         soc_block_list[56],
  21635         soc_portreg,
  21636         1,
  21637         0,
  21638         0x60b00,
  21639         SOC_REG_FLAG_64_BITS |
  21640                           SOC_REG_FLAG_RO,
  21641         0,
  21642         3,
  21643         soc_XLMAC_RX_LSS_STATUS_BCM88470_A0r_fields,
  21644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21645         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21646         -1,
  21647         -1,
  21648     },
  21649 #endif /* chips */
  21650 
  21651 #if defined(BCM_88470_B0)
  21652     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM88470_B0r */
  21653         soc_block_list[56],
  21654         soc_portreg,
  21655         1,
  21656         0,
  21657         0x60b00,
  21658         SOC_REG_FLAG_64_BITS |
  21659                           SOC_REG_FLAG_RO,
  21660         0,
  21661         3,
  21662         soc_XLMAC_RX_LSS_STATUS_BCM88470_B0r_fields,
  21663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21664         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21665         -1,
  21666         -1,
  21667     },
  21668 #endif /* chips */
  21669 
  21670 #if defined(BCM_88675_A0)
  21671     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM88675_A0r */
  21672         soc_block_list[56],
  21673         soc_portreg,
  21674         1,
  21675         0,
  21676         0x60b00,
  21677         SOC_REG_FLAG_64_BITS |
  21678                           SOC_REG_FLAG_RO,
  21679         0,
  21680         3,
  21681         soc_XLMAC_RX_LSS_STATUSr_fields,
  21682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21683         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21684         -1,
  21685         -1,
  21686     },
  21687 #endif /* chips */
  21688 
  21689 #if defined(BCM_88675_B0)
  21690     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM88675_B0r */
  21691         soc_block_list[56],
  21692         soc_portreg,
  21693         1,
  21694         0,
  21695         0x60b00,
  21696         SOC_REG_FLAG_64_BITS |
  21697                           SOC_REG_FLAG_RO,
  21698         0,
  21699         3,
  21700         soc_XLMAC_RX_LSS_STATUS_BCM88675_B0r_fields,
  21701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21702         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21703         -1,
  21704         -1,
  21705     },
  21706 #endif /* chips */
  21707 
  21708 #if defined(BCM_88680_A0)
  21709     { /* SOC_REG_INT_XLMAC_RX_LSS_STATUS_BCM88680_A0r */
  21710         soc_block_list[56],
  21711         soc_portreg,
  21712         1,
  21713         0,
  21714         0x60b00,
  21715         SOC_REG_FLAG_64_BITS |
  21716                           SOC_REG_FLAG_RO,
  21717         0,
  21718         3,
  21719         soc_XLMAC_RX_LSS_STATUS_BCM88680_A0r_fields,
  21720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21721         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21722         -1,
  21723         -1,
  21724     },
  21725 #endif /* chips */
  21726 
  21727 #if defined(BCM_2801PM_A0)
  21728     { /* SOC_REG_INT_XLMAC_RX_MAC_SAr */
  21729         soc_block_list[56],
  21730         soc_portreg,
  21731         1,
  21732         0,
  21733         0x60700,
  21734         SOC_REG_FLAG_64_BITS,
  21735         0,
  21736         1,
  21737         soc_CLMAC_RX_MAC_SAr_fields,
  21738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21739         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21740         -1,
  21741         -1,
  21742     },
  21743 #endif /* chips */
  21744 
  21745 #if defined(BCM_53400_A0)
  21746     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM53400_A0r */
  21747         soc_block_list[16],
  21748         soc_portreg,
  21749         1,
  21750         0,
  21751         0x60700,
  21752         SOC_REG_FLAG_64_BITS,
  21753         0,
  21754         3,
  21755         soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields,
  21756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21757         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21758         -1,
  21759         -1,
  21760     },
  21761 #endif /* chips */
  21762 
  21763 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  21764     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM53570_A0r */
  21765         soc_block_list[16],
  21766         soc_portreg,
  21767         1,
  21768         0,
  21769         0x60600,
  21770         SOC_REG_FLAG_64_BITS,
  21771         0,
  21772         3,
  21773         soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields,
  21774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21775         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21776         -1,
  21777         -1,
  21778     },
  21779 #endif /* chips */
  21780 
  21781 #if defined(BCM_56150_A0)
  21782     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM56150_A0r */
  21783         soc_block_list[16],
  21784         soc_portreg,
  21785         1,
  21786         0,
  21787         0x60700,
  21788         SOC_REG_FLAG_64_BITS,
  21789         0,
  21790         3,
  21791         soc_CMAC_RX_MAC_SAr_fields,
  21792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21793         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21794         -1,
  21795         -1,
  21796     },
  21797 #endif /* chips */
  21798 
  21799 #if defined(BCM_56160_A0)
  21800     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM56160_A0r */
  21801         soc_block_list[16],
  21802         soc_portreg,
  21803         1,
  21804         0,
  21805         0x60700,
  21806         SOC_REG_FLAG_64_BITS,
  21807         0,
  21808         3,
  21809         soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields,
  21810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21811         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21812         -1,
  21813         -1,
  21814     },
  21815 #endif /* chips */
  21816 
  21817 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  21818     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM56260_A0r */
  21819         soc_block_list[220],
  21820         soc_portreg,
  21821         1,
  21822         0,
  21823         0x60700,
  21824         SOC_REG_FLAG_64_BITS,
  21825         0,
  21826         3,
  21827         soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields,
  21828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21829         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21830         -1,
  21831         -1,
  21832     },
  21833 #endif /* chips */
  21834 
  21835 #if defined(BCM_56270_A0)
  21836     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM56270_A0r */
  21837         soc_block_list[220],
  21838         soc_portreg,
  21839         1,
  21840         0,
  21841         0x60700,
  21842         SOC_REG_FLAG_64_BITS,
  21843         0,
  21844         3,
  21845         soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields,
  21846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21847         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21848         -1,
  21849         -1,
  21850     },
  21851 #endif /* chips */
  21852 
  21853 #if defined(BCM_56370_A0)
  21854     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM56370_A0r */
  21855         soc_block_list[16],
  21856         soc_portreg,
  21857         1,
  21858         0,
  21859         0x60700,
  21860         SOC_REG_FLAG_64_BITS,
  21861         0,
  21862         3,
  21863         soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields,
  21864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21865         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21866         -1,
  21867         -1,
  21868         3,
  21869     },
  21870 #endif /* chips */
  21871 
  21872 #if defined(BCM_56560_A0)
  21873     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM56560_A0r */
  21874         soc_block_list[16],
  21875         soc_portreg,
  21876         1,
  21877         0,
  21878         0x60700,
  21879         SOC_REG_FLAG_64_BITS,
  21880         0,
  21881         3,
  21882         soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields,
  21883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21884         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21885         -1,
  21886         -1,
  21887     },
  21888 #endif /* chips */
  21889 
  21890 #if defined(BCM_56560_B0)
  21891     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM56560_B0r */
  21892         soc_block_list[16],
  21893         soc_portreg,
  21894         1,
  21895         0,
  21896         0x60700,
  21897         SOC_REG_FLAG_64_BITS,
  21898         0,
  21899         3,
  21900         soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields,
  21901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21902         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21903         -1,
  21904         -1,
  21905     },
  21906 #endif /* chips */
  21907 
  21908 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  21909     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM56670_A0r */
  21910         soc_block_list[16],
  21911         soc_portreg,
  21912         1,
  21913         0,
  21914         0x60600,
  21915         SOC_REG_FLAG_64_BITS,
  21916         0,
  21917         3,
  21918         soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields,
  21919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21920         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21921         -1,
  21922         -1,
  21923     },
  21924 #endif /* chips */
  21925 
  21926 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  21927     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM56850_A0r */
  21928         soc_block_list[16],
  21929         soc_portreg,
  21930         1,
  21931         0,
  21932         0x60700,
  21933         SOC_REG_FLAG_64_BITS,
  21934         0,
  21935         3,
  21936         soc_CMAC_RX_MAC_SAr_fields,
  21937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21938         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21939         -1,
  21940         -1,
  21941     },
  21942 #endif /* chips */
  21943 
  21944 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  21945     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  21946     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  21947     defined(BCM_56980_B0)
  21948     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM56960_A0r */
  21949         soc_block_list[16],
  21950         soc_portreg,
  21951         1,
  21952         0,
  21953         0x60700,
  21954         SOC_REG_FLAG_64_BITS,
  21955         0,
  21956         3,
  21957         soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields,
  21958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21959         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21960         -1,
  21961         -1,
  21962         3,
  21963     },
  21964 #endif /* chips */
  21965 
  21966 #if defined(BCM_88270_A0)
  21967     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM88270_A0r */
  21968         soc_block_list[221],
  21969         soc_portreg,
  21970         1,
  21971         0,
  21972         0x60700,
  21973         SOC_REG_FLAG_64_BITS,
  21974         0,
  21975         1,
  21976         soc_XLMAC_RX_MAC_SA_BCM88270_A0r_fields,
  21977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21978         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21979         -1,
  21980         -1,
  21981     },
  21982 #endif /* chips */
  21983 
  21984 #if defined(BCM_88375_A0)
  21985     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM88375_A0r */
  21986         soc_block_list[56],
  21987         soc_portreg,
  21988         1,
  21989         0,
  21990         0x60700,
  21991         SOC_REG_FLAG_64_BITS,
  21992         0,
  21993         1,
  21994         soc_XLMAC_RX_MAC_SA_BCM88375_A0r_fields,
  21995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21996         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21997         -1,
  21998         -1,
  21999     },
  22000 #endif /* chips */
  22001 
  22002 #if defined(BCM_88375_B0)
  22003     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM88375_B0r */
  22004         soc_block_list[56],
  22005         soc_portreg,
  22006         1,
  22007         0,
  22008         0x60700,
  22009         SOC_REG_FLAG_64_BITS,
  22010         0,
  22011         1,
  22012         soc_XLMAC_RX_MAC_SA_BCM88375_B0r_fields,
  22013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22014         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  22015         -1,
  22016         -1,
  22017     },
  22018 #endif /* chips */
  22019 
  22020 #if defined(BCM_88470_A0)
  22021     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM88470_A0r */
  22022         soc_block_list[56],
  22023         soc_portreg,
  22024         1,
  22025         0,
  22026         0x60700,
  22027         SOC_REG_FLAG_64_BITS,
  22028         0,
  22029         1,
  22030         soc_XLMAC_RX_MAC_SA_BCM88470_A0r_fields,
  22031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22032         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  22033         -1,
  22034         -1,
  22035     },
  22036 #endif /* chips */
  22037 
  22038 #if defined(BCM_88470_B0)
  22039     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM88470_B0r */
  22040         soc_block_list[56],
  22041         soc_portreg,
  22042         1,
  22043         0,
  22044         0x60700,
  22045         SOC_REG_FLAG_64_BITS,
  22046         0,
  22047         1,
  22048         soc_XLMAC_RX_MAC_SA_BCM88470_B0r_fields,
  22049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22050         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  22051         -1,
  22052         -1,
  22053     },
  22054 #endif /* chips */
  22055 
  22056 #if defined(BCM_88675_A0)
  22057     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM88675_A0r */
  22058         soc_block_list[56],
  22059         soc_portreg,
  22060         1,
  22061         0,
  22062         0x60700,
  22063         SOC_REG_FLAG_64_BITS,
  22064         0,
  22065         1,
  22066         soc_XLMAC_RX_MAC_SAr_fields,
  22067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22068         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  22069         -1,
  22070         -1,
  22071     },
  22072 #endif /* chips */
  22073 
  22074 #if defined(BCM_88675_B0)
  22075     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM88675_B0r */
  22076         soc_block_list[56],
  22077         soc_portreg,
  22078         1,
  22079         0,
  22080         0x60700,
  22081         SOC_REG_FLAG_64_BITS,
  22082         0,
  22083         1,
  22084         soc_XLMAC_RX_MAC_SA_BCM88675_B0r_fields,
  22085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22086         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  22087         -1,
  22088         -1,
  22089     },
  22090 #endif /* chips */
  22091 
  22092 #if defined(BCM_88680_A0)
  22093     { /* SOC_REG_INT_XLMAC_RX_MAC_SA_BCM88680_A0r */
  22094         soc_block_list[56],
  22095         soc_portreg,
  22096         1,
  22097         0,
  22098         0x60700,
  22099         SOC_REG_FLAG_64_BITS,
  22100         0,
  22101         1,
  22102         soc_XLMAC_RX_MAC_SA_BCM88680_A0r_fields,
  22103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22104         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  22105         -1,
  22106         -1,
  22107     },
  22108 #endif /* chips */
  22109 
  22110 #if defined(BCM_2801PM_A0)
  22111     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZEr */
  22112         soc_block_list[56],
  22113         soc_portreg,
  22114         1,
  22115         0,
  22116         0x60800,
  22117         0,
  22118         0,
  22119         1,
  22120         soc_CLMAC_RX_MAX_SIZEr_fields,
  22121         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22122         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22123         -1,
  22124         -1,
  22125     },
  22126 #endif /* chips */
  22127 
  22128 #if defined(BCM_53400_A0)
  22129     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM53400_A0r */
  22130         soc_block_list[16],
  22131         soc_portreg,
  22132         1,
  22133         0,
  22134         0x60800,
  22135         SOC_REG_FLAG_64_BITS,
  22136         0,
  22137         1,
  22138         soc_CLMAC_RX_MAX_SIZEr_fields,
  22139         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22140         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22141         -1,
  22142         -1,
  22143     },
  22144 #endif /* chips */
  22145 
  22146 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  22147     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM53570_A0r */
  22148         soc_block_list[16],
  22149         soc_portreg,
  22150         1,
  22151         0,
  22152         0x60700,
  22153         SOC_REG_FLAG_64_BITS,
  22154         0,
  22155         1,
  22156         soc_CLMAC_RX_MAX_SIZEr_fields,
  22157         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22158         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22159         -1,
  22160         -1,
  22161     },
  22162 #endif /* chips */
  22163 
  22164 #if defined(BCM_56150_A0)
  22165     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM56150_A0r */
  22166         soc_block_list[16],
  22167         soc_portreg,
  22168         1,
  22169         0,
  22170         0x60800,
  22171         SOC_REG_FLAG_64_BITS,
  22172         0,
  22173         1,
  22174         soc_CMAC_RX_MAX_SIZEr_fields,
  22175         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22176         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22177         -1,
  22178         -1,
  22179     },
  22180 #endif /* chips */
  22181 
  22182 #if defined(BCM_56160_A0)
  22183     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM56160_A0r */
  22184         soc_block_list[16],
  22185         soc_portreg,
  22186         1,
  22187         0,
  22188         0x60800,
  22189         SOC_REG_FLAG_64_BITS,
  22190         0,
  22191         1,
  22192         soc_CLMAC_RX_MAX_SIZEr_fields,
  22193         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22194         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22195         -1,
  22196         -1,
  22197     },
  22198 #endif /* chips */
  22199 
  22200 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  22201     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM56260_A0r */
  22202         soc_block_list[220],
  22203         soc_portreg,
  22204         1,
  22205         0,
  22206         0x60800,
  22207         SOC_REG_FLAG_64_BITS,
  22208         0,
  22209         1,
  22210         soc_CLMAC_RX_MAX_SIZEr_fields,
  22211         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22212         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22213         -1,
  22214         -1,
  22215     },
  22216 #endif /* chips */
  22217 
  22218 #if defined(BCM_56270_A0)
  22219     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM56270_A0r */
  22220         soc_block_list[220],
  22221         soc_portreg,
  22222         1,
  22223         0,
  22224         0x60800,
  22225         SOC_REG_FLAG_64_BITS,
  22226         0,
  22227         1,
  22228         soc_CLMAC_RX_MAX_SIZEr_fields,
  22229         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22230         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22231         -1,
  22232         -1,
  22233     },
  22234 #endif /* chips */
  22235 
  22236 #if defined(BCM_56370_A0)
  22237     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM56370_A0r */
  22238         soc_block_list[16],
  22239         soc_portreg,
  22240         1,
  22241         0,
  22242         0x60800,
  22243         SOC_REG_FLAG_64_BITS,
  22244         0,
  22245         1,
  22246         soc_CLMAC_RX_MAX_SIZEr_fields,
  22247         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22248         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22249         -1,
  22250         -1,
  22251         3,
  22252     },
  22253 #endif /* chips */
  22254 
  22255 #if defined(BCM_56560_A0)
  22256     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM56560_A0r */
  22257         soc_block_list[16],
  22258         soc_portreg,
  22259         1,
  22260         0,
  22261         0x60800,
  22262         SOC_REG_FLAG_64_BITS,
  22263         0,
  22264         1,
  22265         soc_CLMAC_RX_MAX_SIZEr_fields,
  22266         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22267         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22268         -1,
  22269         -1,
  22270     },
  22271 #endif /* chips */
  22272 
  22273 #if defined(BCM_56560_B0)
  22274     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM56560_B0r */
  22275         soc_block_list[16],
  22276         soc_portreg,
  22277         1,
  22278         0,
  22279         0x60800,
  22280         SOC_REG_FLAG_64_BITS,
  22281         0,
  22282         1,
  22283         soc_CLMAC_RX_MAX_SIZEr_fields,
  22284         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22285         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22286         -1,
  22287         -1,
  22288     },
  22289 #endif /* chips */
  22290 
  22291 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  22292     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM56670_A0r */
  22293         soc_block_list[16],
  22294         soc_portreg,
  22295         1,
  22296         0,
  22297         0x60700,
  22298         SOC_REG_FLAG_64_BITS,
  22299         0,
  22300         1,
  22301         soc_CLMAC_RX_MAX_SIZEr_fields,
  22302         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22303         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22304         -1,
  22305         -1,
  22306     },
  22307 #endif /* chips */
  22308 
  22309 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  22310     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM56850_A0r */
  22311         soc_block_list[16],
  22312         soc_portreg,
  22313         1,
  22314         0,
  22315         0x60800,
  22316         SOC_REG_FLAG_64_BITS,
  22317         0,
  22318         1,
  22319         soc_CMAC_RX_MAX_SIZEr_fields,
  22320         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22321         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22322         -1,
  22323         -1,
  22324     },
  22325 #endif /* chips */
  22326 
  22327 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  22328     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  22329     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  22330     defined(BCM_56980_B0)
  22331     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM56960_A0r */
  22332         soc_block_list[16],
  22333         soc_portreg,
  22334         1,
  22335         0,
  22336         0x60800,
  22337         SOC_REG_FLAG_64_BITS,
  22338         0,
  22339         1,
  22340         soc_CLMAC_RX_MAX_SIZEr_fields,
  22341         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22342         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22343         -1,
  22344         -1,
  22345         3,
  22346     },
  22347 #endif /* chips */
  22348 
  22349 #if defined(BCM_88270_A0)
  22350     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM88270_A0r */
  22351         soc_block_list[221],
  22352         soc_portreg,
  22353         1,
  22354         0,
  22355         0x60800,
  22356         SOC_REG_FLAG_64_BITS,
  22357         0,
  22358         1,
  22359         soc_XLMAC_RX_MAX_SIZE_BCM88270_A0r_fields,
  22360         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22361         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22362         -1,
  22363         -1,
  22364     },
  22365 #endif /* chips */
  22366 
  22367 #if defined(BCM_88375_A0)
  22368     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM88375_A0r */
  22369         soc_block_list[56],
  22370         soc_portreg,
  22371         1,
  22372         0,
  22373         0x60800,
  22374         SOC_REG_FLAG_64_BITS,
  22375         0,
  22376         1,
  22377         soc_XLMAC_RX_MAX_SIZE_BCM88375_A0r_fields,
  22378         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22379         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22380         -1,
  22381         -1,
  22382     },
  22383 #endif /* chips */
  22384 
  22385 #if defined(BCM_88375_B0)
  22386     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM88375_B0r */
  22387         soc_block_list[56],
  22388         soc_portreg,
  22389         1,
  22390         0,
  22391         0x60800,
  22392         SOC_REG_FLAG_64_BITS,
  22393         0,
  22394         1,
  22395         soc_XLMAC_RX_MAX_SIZE_BCM88375_B0r_fields,
  22396         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22397         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22398         -1,
  22399         -1,
  22400     },
  22401 #endif /* chips */
  22402 
  22403 #if defined(BCM_88470_A0)
  22404     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM88470_A0r */
  22405         soc_block_list[56],
  22406         soc_portreg,
  22407         1,
  22408         0,
  22409         0x60800,
  22410         SOC_REG_FLAG_64_BITS,
  22411         0,
  22412         1,
  22413         soc_XLMAC_RX_MAX_SIZE_BCM88470_A0r_fields,
  22414         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22415         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22416         -1,
  22417         -1,
  22418     },
  22419 #endif /* chips */
  22420 
  22421 #if defined(BCM_88470_B0)
  22422     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM88470_B0r */
  22423         soc_block_list[56],
  22424         soc_portreg,
  22425         1,
  22426         0,
  22427         0x60800,
  22428         SOC_REG_FLAG_64_BITS,
  22429         0,
  22430         1,
  22431         soc_XLMAC_RX_MAX_SIZE_BCM88470_B0r_fields,
  22432         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22433         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22434         -1,
  22435         -1,
  22436     },
  22437 #endif /* chips */
  22438 
  22439 #if defined(BCM_88675_A0)
  22440     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM88675_A0r */
  22441         soc_block_list[56],
  22442         soc_portreg,
  22443         1,
  22444         0,
  22445         0x60800,
  22446         SOC_REG_FLAG_64_BITS,
  22447         0,
  22448         1,
  22449         soc_XLMAC_RX_MAX_SIZEr_fields,
  22450         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22451         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22452         -1,
  22453         -1,
  22454     },
  22455 #endif /* chips */
  22456 
  22457 #if defined(BCM_88675_B0)
  22458     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM88675_B0r */
  22459         soc_block_list[56],
  22460         soc_portreg,
  22461         1,
  22462         0,
  22463         0x60800,
  22464         SOC_REG_FLAG_64_BITS,
  22465         0,
  22466         1,
  22467         soc_XLMAC_RX_MAX_SIZE_BCM88675_B0r_fields,
  22468         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22469         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22470         -1,
  22471         -1,
  22472     },
  22473 #endif /* chips */
  22474 
  22475 #if defined(BCM_88680_A0)
  22476     { /* SOC_REG_INT_XLMAC_RX_MAX_SIZE_BCM88680_A0r */
  22477         soc_block_list[56],
  22478         soc_portreg,
  22479         1,
  22480         0,
  22481         0x60800,
  22482         SOC_REG_FLAG_64_BITS,
  22483         0,
  22484         1,
  22485         soc_XLMAC_RX_MAX_SIZE_BCM88680_A0r_fields,
  22486         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  22487         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  22488         -1,
  22489         -1,
  22490     },
  22491 #endif /* chips */
  22492 
  22493 #if defined(BCM_2801PM_A0)
  22494     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAGr */
  22495         soc_block_list[56],
  22496         soc_portreg,
  22497         1,
  22498         0,
  22499         0x60900,
  22500         SOC_REG_FLAG_64_BITS,
  22501         0,
  22502         4,
  22503         soc_CLMAC_RX_VLAN_TAGr_fields,
  22504         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22505         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22506         -1,
  22507         -1,
  22508     },
  22509 #endif /* chips */
  22510 
  22511 #if defined(BCM_53400_A0)
  22512     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM53400_A0r */
  22513         soc_block_list[16],
  22514         soc_portreg,
  22515         1,
  22516         0,
  22517         0x60900,
  22518         SOC_REG_FLAG_64_BITS,
  22519         0,
  22520         4,
  22521         soc_CLMAC_RX_VLAN_TAGr_fields,
  22522         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22523         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22524         -1,
  22525         -1,
  22526     },
  22527 #endif /* chips */
  22528 
  22529 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  22530     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM53570_A0r */
  22531         soc_block_list[16],
  22532         soc_portreg,
  22533         1,
  22534         0,
  22535         0x60800,
  22536         SOC_REG_FLAG_64_BITS,
  22537         0,
  22538         4,
  22539         soc_CLMAC_RX_VLAN_TAGr_fields,
  22540         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22542         -1,
  22543         -1,
  22544     },
  22545 #endif /* chips */
  22546 
  22547 #if defined(BCM_56150_A0)
  22548     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM56150_A0r */
  22549         soc_block_list[16],
  22550         soc_portreg,
  22551         1,
  22552         0,
  22553         0x60900,
  22554         SOC_REG_FLAG_64_BITS,
  22555         0,
  22556         4,
  22557         soc_CMAC_RX_VLAN_TAGr_fields,
  22558         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22559         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22560         -1,
  22561         -1,
  22562     },
  22563 #endif /* chips */
  22564 
  22565 #if defined(BCM_56160_A0)
  22566     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM56160_A0r */
  22567         soc_block_list[16],
  22568         soc_portreg,
  22569         1,
  22570         0,
  22571         0x60900,
  22572         SOC_REG_FLAG_64_BITS,
  22573         0,
  22574         4,
  22575         soc_CLMAC_RX_VLAN_TAGr_fields,
  22576         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22577         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22578         -1,
  22579         -1,
  22580     },
  22581 #endif /* chips */
  22582 
  22583 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  22584     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM56260_A0r */
  22585         soc_block_list[220],
  22586         soc_portreg,
  22587         1,
  22588         0,
  22589         0x60900,
  22590         SOC_REG_FLAG_64_BITS,
  22591         0,
  22592         4,
  22593         soc_CLMAC_RX_VLAN_TAGr_fields,
  22594         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22596         -1,
  22597         -1,
  22598     },
  22599 #endif /* chips */
  22600 
  22601 #if defined(BCM_56270_A0)
  22602     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM56270_A0r */
  22603         soc_block_list[220],
  22604         soc_portreg,
  22605         1,
  22606         0,
  22607         0x60900,
  22608         SOC_REG_FLAG_64_BITS,
  22609         0,
  22610         4,
  22611         soc_CLMAC_RX_VLAN_TAGr_fields,
  22612         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22613         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22614         -1,
  22615         -1,
  22616     },
  22617 #endif /* chips */
  22618 
  22619 #if defined(BCM_56370_A0)
  22620     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM56370_A0r */
  22621         soc_block_list[16],
  22622         soc_portreg,
  22623         1,
  22624         0,
  22625         0x60900,
  22626         SOC_REG_FLAG_64_BITS,
  22627         0,
  22628         4,
  22629         soc_CLMAC_RX_VLAN_TAGr_fields,
  22630         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22631         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22632         -1,
  22633         -1,
  22634         3,
  22635     },
  22636 #endif /* chips */
  22637 
  22638 #if defined(BCM_56560_A0)
  22639     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM56560_A0r */
  22640         soc_block_list[16],
  22641         soc_portreg,
  22642         1,
  22643         0,
  22644         0x60900,
  22645         SOC_REG_FLAG_64_BITS,
  22646         0,
  22647         4,
  22648         soc_CLMAC_RX_VLAN_TAGr_fields,
  22649         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22651         -1,
  22652         -1,
  22653     },
  22654 #endif /* chips */
  22655 
  22656 #if defined(BCM_56560_B0)
  22657     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM56560_B0r */
  22658         soc_block_list[16],
  22659         soc_portreg,
  22660         1,
  22661         0,
  22662         0x60900,
  22663         SOC_REG_FLAG_64_BITS,
  22664         0,
  22665         4,
  22666         soc_CLMAC_RX_VLAN_TAGr_fields,
  22667         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22668         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22669         -1,
  22670         -1,
  22671     },
  22672 #endif /* chips */
  22673 
  22674 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  22675     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM56670_A0r */
  22676         soc_block_list[16],
  22677         soc_portreg,
  22678         1,
  22679         0,
  22680         0x60800,
  22681         SOC_REG_FLAG_64_BITS,
  22682         0,
  22683         4,
  22684         soc_CLMAC_RX_VLAN_TAGr_fields,
  22685         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22686         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22687         -1,
  22688         -1,
  22689     },
  22690 #endif /* chips */
  22691 
  22692 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  22693     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM56850_A0r */
  22694         soc_block_list[16],
  22695         soc_portreg,
  22696         1,
  22697         0,
  22698         0x60900,
  22699         SOC_REG_FLAG_64_BITS,
  22700         0,
  22701         4,
  22702         soc_CMAC_RX_VLAN_TAGr_fields,
  22703         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22704         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22705         -1,
  22706         -1,
  22707     },
  22708 #endif /* chips */
  22709 
  22710 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  22711     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  22712     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  22713     defined(BCM_56980_B0)
  22714     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM56960_A0r */
  22715         soc_block_list[16],
  22716         soc_portreg,
  22717         1,
  22718         0,
  22719         0x60900,
  22720         SOC_REG_FLAG_64_BITS,
  22721         0,
  22722         4,
  22723         soc_CLMAC_RX_VLAN_TAGr_fields,
  22724         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22726         -1,
  22727         -1,
  22728         3,
  22729     },
  22730 #endif /* chips */
  22731 
  22732 #if defined(BCM_88270_A0)
  22733     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM88270_A0r */
  22734         soc_block_list[221],
  22735         soc_portreg,
  22736         1,
  22737         0,
  22738         0x60900,
  22739         SOC_REG_FLAG_64_BITS,
  22740         0,
  22741         4,
  22742         soc_XLMAC_RX_VLAN_TAG_BCM88270_A0r_fields,
  22743         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22744         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22745         -1,
  22746         -1,
  22747     },
  22748 #endif /* chips */
  22749 
  22750 #if defined(BCM_88375_A0)
  22751     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM88375_A0r */
  22752         soc_block_list[56],
  22753         soc_portreg,
  22754         1,
  22755         0,
  22756         0x60900,
  22757         SOC_REG_FLAG_64_BITS,
  22758         0,
  22759         4,
  22760         soc_XLMAC_RX_VLAN_TAG_BCM88375_A0r_fields,
  22761         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22762         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22763         -1,
  22764         -1,
  22765     },
  22766 #endif /* chips */
  22767 
  22768 #if defined(BCM_88375_B0)
  22769     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM88375_B0r */
  22770         soc_block_list[56],
  22771         soc_portreg,
  22772         1,
  22773         0,
  22774         0x60900,
  22775         SOC_REG_FLAG_64_BITS,
  22776         0,
  22777         4,
  22778         soc_XLMAC_RX_VLAN_TAG_BCM88375_B0r_fields,
  22779         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22780         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22781         -1,
  22782         -1,
  22783     },
  22784 #endif /* chips */
  22785 
  22786 #if defined(BCM_88470_A0)
  22787     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM88470_A0r */
  22788         soc_block_list[56],
  22789         soc_portreg,
  22790         1,
  22791         0,
  22792         0x60900,
  22793         SOC_REG_FLAG_64_BITS,
  22794         0,
  22795         4,
  22796         soc_XLMAC_RX_VLAN_TAG_BCM88470_A0r_fields,
  22797         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22798         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22799         -1,
  22800         -1,
  22801     },
  22802 #endif /* chips */
  22803 
  22804 #if defined(BCM_88470_B0)
  22805     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM88470_B0r */
  22806         soc_block_list[56],
  22807         soc_portreg,
  22808         1,
  22809         0,
  22810         0x60900,
  22811         SOC_REG_FLAG_64_BITS,
  22812         0,
  22813         4,
  22814         soc_XLMAC_RX_VLAN_TAG_BCM88470_B0r_fields,
  22815         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22816         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22817         -1,
  22818         -1,
  22819     },
  22820 #endif /* chips */
  22821 
  22822 #if defined(BCM_88675_A0)
  22823     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM88675_A0r */
  22824         soc_block_list[56],
  22825         soc_portreg,
  22826         1,
  22827         0,
  22828         0x60900,
  22829         SOC_REG_FLAG_64_BITS,
  22830         0,
  22831         4,
  22832         soc_XLMAC_RX_VLAN_TAGr_fields,
  22833         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22834         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22835         -1,
  22836         -1,
  22837     },
  22838 #endif /* chips */
  22839 
  22840 #if defined(BCM_88675_B0)
  22841     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM88675_B0r */
  22842         soc_block_list[56],
  22843         soc_portreg,
  22844         1,
  22845         0,
  22846         0x60900,
  22847         SOC_REG_FLAG_64_BITS,
  22848         0,
  22849         4,
  22850         soc_XLMAC_RX_VLAN_TAG_BCM88675_B0r_fields,
  22851         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22852         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22853         -1,
  22854         -1,
  22855     },
  22856 #endif /* chips */
  22857 
  22858 #if defined(BCM_88680_A0)
  22859     { /* SOC_REG_INT_XLMAC_RX_VLAN_TAG_BCM88680_A0r */
  22860         soc_block_list[56],
  22861         soc_portreg,
  22862         1,
  22863         0,
  22864         0x60900,
  22865         SOC_REG_FLAG_64_BITS,
  22866         0,
  22867         4,
  22868         soc_XLMAC_RX_VLAN_TAG_BCM88680_A0r_fields,
  22869         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  22870         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  22871         -1,
  22872         -1,
  22873     },
  22874 #endif /* chips */
  22875 
  22876 #if defined(BCM_2801PM_A0)
  22877     { /* SOC_REG_INT_XLMAC_SPARE0r */
  22878         soc_block_list[56],
  22879         soc_portreg,
  22880         1,
  22881         0,
  22882         0x60200,
  22883         0,
  22884         0,
  22885         1,
  22886         soc_CLPORT_SPARE0_REGr_fields,
  22887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22889         -1,
  22890         -1,
  22891     },
  22892 #endif /* chips */
  22893 
  22894 #if defined(BCM_2801PM_A0)
  22895     { /* SOC_REG_INT_XLMAC_SPARE1r */
  22896         soc_block_list[56],
  22897         soc_portreg,
  22898         1,
  22899         0,
  22900         0x60300,
  22901         0,
  22902         0,
  22903         1,
  22904         soc_CLMAC_SPARE1r_fields,
  22905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22906         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  22907         -1,
  22908         -1,
  22909     },
  22910 #endif /* chips */
  22911 
  22912 #if defined(BCM_53400_A0)
  22913     { /* SOC_REG_INT_XLMAC_SPARE0_BCM53400_A0r */
  22914         soc_block_list[16],
  22915         soc_portreg,
  22916         1,
  22917         0,
  22918         0x60200,
  22919         SOC_REG_FLAG_64_BITS,
  22920         0,
  22921         1,
  22922         soc_CLPORT_SPARE0_REGr_fields,
  22923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22924         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22925         -1,
  22926         -1,
  22927     },
  22928 #endif /* chips */
  22929 
  22930 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  22931     { /* SOC_REG_INT_XLMAC_SPARE0_BCM53570_A0r */
  22932         soc_block_list[16],
  22933         soc_portreg,
  22934         1,
  22935         0,
  22936         0x64800,
  22937         SOC_REG_FLAG_64_BITS,
  22938         0,
  22939         1,
  22940         soc_CLPORT_SPARE0_REGr_fields,
  22941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22942         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22943         -1,
  22944         -1,
  22945     },
  22946 #endif /* chips */
  22947 
  22948 #if defined(BCM_56150_A0)
  22949     { /* SOC_REG_INT_XLMAC_SPARE0_BCM56150_A0r */
  22950         soc_block_list[16],
  22951         soc_portreg,
  22952         1,
  22953         0,
  22954         0x60200,
  22955         SOC_REG_FLAG_64_BITS,
  22956         0,
  22957         1,
  22958         soc_CMAC_SPARE0r_fields,
  22959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22960         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22961         -1,
  22962         -1,
  22963     },
  22964 #endif /* chips */
  22965 
  22966 #if defined(BCM_56160_A0)
  22967     { /* SOC_REG_INT_XLMAC_SPARE0_BCM56160_A0r */
  22968         soc_block_list[16],
  22969         soc_portreg,
  22970         1,
  22971         0,
  22972         0x60200,
  22973         SOC_REG_FLAG_64_BITS,
  22974         0,
  22975         1,
  22976         soc_CLPORT_SPARE0_REGr_fields,
  22977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22978         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22979         -1,
  22980         -1,
  22981     },
  22982 #endif /* chips */
  22983 
  22984 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  22985     { /* SOC_REG_INT_XLMAC_SPARE0_BCM56260_A0r */
  22986         soc_block_list[220],
  22987         soc_portreg,
  22988         1,
  22989         0,
  22990         0x60200,
  22991         SOC_REG_FLAG_64_BITS,
  22992         0,
  22993         1,
  22994         soc_CLPORT_SPARE0_REGr_fields,
  22995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22997         -1,
  22998         -1,
  22999     },
  23000 #endif /* chips */
  23001 
  23002 #if defined(BCM_56270_A0)
  23003     { /* SOC_REG_INT_XLMAC_SPARE0_BCM56270_A0r */
  23004         soc_block_list[220],
  23005         soc_portreg,
  23006         1,
  23007         0,
  23008         0x60200,
  23009         SOC_REG_FLAG_64_BITS,
  23010         0,
  23011         1,
  23012         soc_CLPORT_SPARE0_REGr_fields,
  23013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23014         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23015         -1,
  23016         -1,
  23017     },
  23018 #endif /* chips */
  23019 
  23020 #if defined(BCM_56370_A0)
  23021     { /* SOC_REG_INT_XLMAC_SPARE0_BCM56370_A0r */
  23022         soc_block_list[16],
  23023         soc_portreg,
  23024         1,
  23025         0,
  23026         0x60200,
  23027         SOC_REG_FLAG_64_BITS,
  23028         0,
  23029         1,
  23030         soc_CLPORT_SPARE0_REGr_fields,
  23031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23032         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23033         -1,
  23034         -1,
  23035         3,
  23036     },
  23037 #endif /* chips */
  23038 
  23039 #if defined(BCM_56560_A0)
  23040     { /* SOC_REG_INT_XLMAC_SPARE0_BCM56560_A0r */
  23041         soc_block_list[16],
  23042         soc_portreg,
  23043         1,
  23044         0,
  23045         0x60200,
  23046         SOC_REG_FLAG_64_BITS,
  23047         0,
  23048         1,
  23049         soc_CLPORT_SPARE0_REGr_fields,
  23050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23051         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23052         -1,
  23053         -1,
  23054     },
  23055 #endif /* chips */
  23056 
  23057 #if defined(BCM_56560_B0)
  23058     { /* SOC_REG_INT_XLMAC_SPARE0_BCM56560_B0r */
  23059         soc_block_list[16],
  23060         soc_portreg,
  23061         1,
  23062         0,
  23063         0x60200,
  23064         SOC_REG_FLAG_64_BITS,
  23065         0,
  23066         1,
  23067         soc_CLPORT_SPARE0_REGr_fields,
  23068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23069         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23070         -1,
  23071         -1,
  23072     },
  23073 #endif /* chips */
  23074 
  23075 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  23076     { /* SOC_REG_INT_XLMAC_SPARE0_BCM56670_A0r */
  23077         soc_block_list[16],
  23078         soc_portreg,
  23079         1,
  23080         0,
  23081         0x64800,
  23082         SOC_REG_FLAG_64_BITS,
  23083         0,
  23084         1,
  23085         soc_CLPORT_SPARE0_REGr_fields,
  23086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23087         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23088         -1,
  23089         -1,
  23090     },
  23091 #endif /* chips */
  23092 
  23093 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  23094     { /* SOC_REG_INT_XLMAC_SPARE0_BCM56850_A0r */
  23095         soc_block_list[16],
  23096         soc_portreg,
  23097         1,
  23098         0,
  23099         0x60200,
  23100         SOC_REG_FLAG_64_BITS,
  23101         0,
  23102         1,
  23103         soc_CMAC_SPARE0r_fields,
  23104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23105         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23106         -1,
  23107         -1,
  23108     },
  23109 #endif /* chips */
  23110 
  23111 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  23112     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  23113     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  23114     defined(BCM_56980_B0)
  23115     { /* SOC_REG_INT_XLMAC_SPARE0_BCM56960_A0r */
  23116         soc_block_list[16],
  23117         soc_portreg,
  23118         1,
  23119         0,
  23120         0x60200,
  23121         SOC_REG_FLAG_64_BITS,
  23122         0,
  23123         1,
  23124         soc_CLPORT_SPARE0_REGr_fields,
  23125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23126         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23127         -1,
  23128         -1,
  23129         3,
  23130     },
  23131 #endif /* chips */
  23132 
  23133 #if defined(BCM_88270_A0)
  23134     { /* SOC_REG_INT_XLMAC_SPARE0_BCM88270_A0r */
  23135         soc_block_list[221],
  23136         soc_portreg,
  23137         1,
  23138         0,
  23139         0x60200,
  23140         SOC_REG_FLAG_64_BITS,
  23141         0,
  23142         1,
  23143         soc_XLMAC_SPARE0_BCM88270_A0r_fields,
  23144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23145         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23146         -1,
  23147         -1,
  23148     },
  23149 #endif /* chips */
  23150 
  23151 #if defined(BCM_88375_A0)
  23152     { /* SOC_REG_INT_XLMAC_SPARE0_BCM88375_A0r */
  23153         soc_block_list[56],
  23154         soc_portreg,
  23155         1,
  23156         0,
  23157         0x60200,
  23158         SOC_REG_FLAG_64_BITS,
  23159         0,
  23160         1,
  23161         soc_XLMAC_SPARE0_BCM88375_A0r_fields,
  23162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23163         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23164         -1,
  23165         -1,
  23166     },
  23167 #endif /* chips */
  23168 
  23169 #if defined(BCM_88375_B0)
  23170     { /* SOC_REG_INT_XLMAC_SPARE0_BCM88375_B0r */
  23171         soc_block_list[56],
  23172         soc_portreg,
  23173         1,
  23174         0,
  23175         0x60200,
  23176         SOC_REG_FLAG_64_BITS,
  23177         0,
  23178         1,
  23179         soc_XLMAC_SPARE0_BCM88375_B0r_fields,
  23180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23181         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23182         -1,
  23183         -1,
  23184     },
  23185 #endif /* chips */
  23186 
  23187 #if defined(BCM_88470_A0)
  23188     { /* SOC_REG_INT_XLMAC_SPARE0_BCM88470_A0r */
  23189         soc_block_list[56],
  23190         soc_portreg,
  23191         1,
  23192         0,
  23193         0x60200,
  23194         SOC_REG_FLAG_64_BITS,
  23195         0,
  23196         1,
  23197         soc_XLMAC_SPARE0_BCM88470_A0r_fields,
  23198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23199         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23200         -1,
  23201         -1,
  23202     },
  23203 #endif /* chips */
  23204 
  23205 #if defined(BCM_88470_B0)
  23206     { /* SOC_REG_INT_XLMAC_SPARE0_BCM88470_B0r */
  23207         soc_block_list[56],
  23208         soc_portreg,
  23209         1,
  23210         0,
  23211         0x60200,
  23212         SOC_REG_FLAG_64_BITS,
  23213         0,
  23214         1,
  23215         soc_XLMAC_SPARE0_BCM88470_B0r_fields,
  23216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23217         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23218         -1,
  23219         -1,
  23220     },
  23221 #endif /* chips */
  23222 
  23223 #if defined(BCM_88675_A0)
  23224     { /* SOC_REG_INT_XLMAC_SPARE0_BCM88675_A0r */
  23225         soc_block_list[56],
  23226         soc_portreg,
  23227         1,
  23228         0,
  23229         0x60200,
  23230         SOC_REG_FLAG_64_BITS,
  23231         0,
  23232         1,
  23233         soc_XLMAC_SPARE0r_fields,
  23234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23235         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23236         -1,
  23237         -1,
  23238     },
  23239 #endif /* chips */
  23240 
  23241 #if defined(BCM_88675_B0)
  23242     { /* SOC_REG_INT_XLMAC_SPARE0_BCM88675_B0r */
  23243         soc_block_list[56],
  23244         soc_portreg,
  23245         1,
  23246         0,
  23247         0x60200,
  23248         SOC_REG_FLAG_64_BITS,
  23249         0,
  23250         1,
  23251         soc_XLMAC_SPARE0_BCM88675_B0r_fields,
  23252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23253         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23254         -1,
  23255         -1,
  23256     },
  23257 #endif /* chips */
  23258 
  23259 #if defined(BCM_88680_A0)
  23260     { /* SOC_REG_INT_XLMAC_SPARE0_BCM88680_A0r */
  23261         soc_block_list[56],
  23262         soc_portreg,
  23263         1,
  23264         0,
  23265         0x60200,
  23266         SOC_REG_FLAG_64_BITS,
  23267         0,
  23268         1,
  23269         soc_XLMAC_SPARE0_BCM88680_A0r_fields,
  23270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23271         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23272         -1,
  23273         -1,
  23274     },
  23275 #endif /* chips */
  23276 
  23277 #if defined(BCM_53400_A0)
  23278     { /* SOC_REG_INT_XLMAC_SPARE1_BCM53400_A0r */
  23279         soc_block_list[16],
  23280         soc_portreg,
  23281         1,
  23282         0,
  23283         0x60300,
  23284         SOC_REG_FLAG_64_BITS,
  23285         0,
  23286         1,
  23287         soc_CLMAC_SPARE1r_fields,
  23288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23289         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23290         -1,
  23291         -1,
  23292     },
  23293 #endif /* chips */
  23294 
  23295 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  23296     { /* SOC_REG_INT_XLMAC_SPARE1_BCM53570_A0r */
  23297         soc_block_list[16],
  23298         soc_portreg,
  23299         1,
  23300         0,
  23301         0x64900,
  23302         SOC_REG_FLAG_64_BITS,
  23303         0,
  23304         1,
  23305         soc_CLMAC_SPARE1r_fields,
  23306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23307         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23308         -1,
  23309         -1,
  23310     },
  23311 #endif /* chips */
  23312 
  23313 #if defined(BCM_56150_A0)
  23314     { /* SOC_REG_INT_XLMAC_SPARE1_BCM56150_A0r */
  23315         soc_block_list[16],
  23316         soc_portreg,
  23317         1,
  23318         0,
  23319         0x60300,
  23320         SOC_REG_FLAG_64_BITS,
  23321         0,
  23322         1,
  23323         soc_CMAC_SPARE1r_fields,
  23324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23325         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23326         -1,
  23327         -1,
  23328     },
  23329 #endif /* chips */
  23330 
  23331 #if defined(BCM_56160_A0)
  23332     { /* SOC_REG_INT_XLMAC_SPARE1_BCM56160_A0r */
  23333         soc_block_list[16],
  23334         soc_portreg,
  23335         1,
  23336         0,
  23337         0x60300,
  23338         SOC_REG_FLAG_64_BITS,
  23339         0,
  23340         1,
  23341         soc_CLMAC_SPARE1r_fields,
  23342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23343         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23344         -1,
  23345         -1,
  23346     },
  23347 #endif /* chips */
  23348 
  23349 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  23350     { /* SOC_REG_INT_XLMAC_SPARE1_BCM56260_A0r */
  23351         soc_block_list[220],
  23352         soc_portreg,
  23353         1,
  23354         0,
  23355         0x60300,
  23356         SOC_REG_FLAG_64_BITS,
  23357         0,
  23358         1,
  23359         soc_CLMAC_SPARE1r_fields,
  23360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23361         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23362         -1,
  23363         -1,
  23364     },
  23365 #endif /* chips */
  23366 
  23367 #if defined(BCM_56270_A0)
  23368     { /* SOC_REG_INT_XLMAC_SPARE1_BCM56270_A0r */
  23369         soc_block_list[220],
  23370         soc_portreg,
  23371         1,
  23372         0,
  23373         0x60300,
  23374         SOC_REG_FLAG_64_BITS,
  23375         0,
  23376         1,
  23377         soc_CLMAC_SPARE1r_fields,
  23378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23379         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23380         -1,
  23381         -1,
  23382     },
  23383 #endif /* chips */
  23384 
  23385 #if defined(BCM_56370_A0)
  23386     { /* SOC_REG_INT_XLMAC_SPARE1_BCM56370_A0r */
  23387         soc_block_list[16],
  23388         soc_portreg,
  23389         1,
  23390         0,
  23391         0x60300,
  23392         SOC_REG_FLAG_64_BITS,
  23393         0,
  23394         1,
  23395         soc_CLMAC_SPARE1r_fields,
  23396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23397         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23398         -1,
  23399         -1,
  23400         3,
  23401     },
  23402 #endif /* chips */
  23403 
  23404 #if defined(BCM_56560_A0)
  23405     { /* SOC_REG_INT_XLMAC_SPARE1_BCM56560_A0r */
  23406         soc_block_list[16],
  23407         soc_portreg,
  23408         1,
  23409         0,
  23410         0x60300,
  23411         SOC_REG_FLAG_64_BITS,
  23412         0,
  23413         1,
  23414         soc_CLMAC_SPARE1r_fields,
  23415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23416         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23417         -1,
  23418         -1,
  23419     },
  23420 #endif /* chips */
  23421 
  23422 #if defined(BCM_56560_B0)
  23423     { /* SOC_REG_INT_XLMAC_SPARE1_BCM56560_B0r */
  23424         soc_block_list[16],
  23425         soc_portreg,
  23426         1,
  23427         0,
  23428         0x60300,
  23429         SOC_REG_FLAG_64_BITS,
  23430         0,
  23431         1,
  23432         soc_CLMAC_SPARE1r_fields,
  23433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23434         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23435         -1,
  23436         -1,
  23437     },
  23438 #endif /* chips */
  23439 
  23440 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  23441     { /* SOC_REG_INT_XLMAC_SPARE1_BCM56670_A0r */
  23442         soc_block_list[16],
  23443         soc_portreg,
  23444         1,
  23445         0,
  23446         0x64900,
  23447         SOC_REG_FLAG_64_BITS,
  23448         0,
  23449         1,
  23450         soc_CLMAC_SPARE1r_fields,
  23451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23452         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23453         -1,
  23454         -1,
  23455     },
  23456 #endif /* chips */
  23457 
  23458 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  23459     { /* SOC_REG_INT_XLMAC_SPARE1_BCM56850_A0r */
  23460         soc_block_list[16],
  23461         soc_portreg,
  23462         1,
  23463         0,
  23464         0x60300,
  23465         SOC_REG_FLAG_64_BITS,
  23466         0,
  23467         1,
  23468         soc_CMAC_SPARE1r_fields,
  23469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23470         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23471         -1,
  23472         -1,
  23473     },
  23474 #endif /* chips */
  23475 
  23476 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  23477     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  23478     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  23479     defined(BCM_56980_B0)
  23480     { /* SOC_REG_INT_XLMAC_SPARE1_BCM56960_A0r */
  23481         soc_block_list[16],
  23482         soc_portreg,
  23483         1,
  23484         0,
  23485         0x60300,
  23486         SOC_REG_FLAG_64_BITS,
  23487         0,
  23488         1,
  23489         soc_CLMAC_SPARE1r_fields,
  23490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23491         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23492         -1,
  23493         -1,
  23494         3,
  23495     },
  23496 #endif /* chips */
  23497 
  23498 #if defined(BCM_88270_A0)
  23499     { /* SOC_REG_INT_XLMAC_SPARE1_BCM88270_A0r */
  23500         soc_block_list[221],
  23501         soc_portreg,
  23502         1,
  23503         0,
  23504         0x60300,
  23505         SOC_REG_FLAG_64_BITS,
  23506         0,
  23507         1,
  23508         soc_XLMAC_SPARE1_BCM88270_A0r_fields,
  23509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23510         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23511         -1,
  23512         -1,
  23513     },
  23514 #endif /* chips */
  23515 
  23516 #if defined(BCM_88375_A0)
  23517     { /* SOC_REG_INT_XLMAC_SPARE1_BCM88375_A0r */
  23518         soc_block_list[56],
  23519         soc_portreg,
  23520         1,
  23521         0,
  23522         0x60300,
  23523         SOC_REG_FLAG_64_BITS,
  23524         0,
  23525         1,
  23526         soc_XLMAC_SPARE1_BCM88375_A0r_fields,
  23527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23528         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23529         -1,
  23530         -1,
  23531     },
  23532 #endif /* chips */
  23533 
  23534 #if defined(BCM_88375_B0)
  23535     { /* SOC_REG_INT_XLMAC_SPARE1_BCM88375_B0r */
  23536         soc_block_list[56],
  23537         soc_portreg,
  23538         1,
  23539         0,
  23540         0x60300,
  23541         SOC_REG_FLAG_64_BITS,
  23542         0,
  23543         1,
  23544         soc_XLMAC_SPARE1_BCM88375_B0r_fields,
  23545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23546         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23547         -1,
  23548         -1,
  23549     },
  23550 #endif /* chips */
  23551 
  23552 #if defined(BCM_88470_A0)
  23553     { /* SOC_REG_INT_XLMAC_SPARE1_BCM88470_A0r */
  23554         soc_block_list[56],
  23555         soc_portreg,
  23556         1,
  23557         0,
  23558         0x60300,
  23559         SOC_REG_FLAG_64_BITS,
  23560         0,
  23561         1,
  23562         soc_XLMAC_SPARE1_BCM88470_A0r_fields,
  23563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23564         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23565         -1,
  23566         -1,
  23567     },
  23568 #endif /* chips */
  23569 
  23570 #if defined(BCM_88470_B0)
  23571     { /* SOC_REG_INT_XLMAC_SPARE1_BCM88470_B0r */
  23572         soc_block_list[56],
  23573         soc_portreg,
  23574         1,
  23575         0,
  23576         0x60300,
  23577         SOC_REG_FLAG_64_BITS,
  23578         0,
  23579         1,
  23580         soc_XLMAC_SPARE1_BCM88470_B0r_fields,
  23581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23582         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23583         -1,
  23584         -1,
  23585     },
  23586 #endif /* chips */
  23587 
  23588 #if defined(BCM_88675_A0)
  23589     { /* SOC_REG_INT_XLMAC_SPARE1_BCM88675_A0r */
  23590         soc_block_list[56],
  23591         soc_portreg,
  23592         1,
  23593         0,
  23594         0x60300,
  23595         SOC_REG_FLAG_64_BITS,
  23596         0,
  23597         1,
  23598         soc_XLMAC_SPARE1r_fields,
  23599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23600         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23601         -1,
  23602         -1,
  23603     },
  23604 #endif /* chips */
  23605 
  23606 #if defined(BCM_88675_B0)
  23607     { /* SOC_REG_INT_XLMAC_SPARE1_BCM88675_B0r */
  23608         soc_block_list[56],
  23609         soc_portreg,
  23610         1,
  23611         0,
  23612         0x60300,
  23613         SOC_REG_FLAG_64_BITS,
  23614         0,
  23615         1,
  23616         soc_XLMAC_SPARE1_BCM88675_B0r_fields,
  23617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23618         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23619         -1,
  23620         -1,
  23621     },
  23622 #endif /* chips */
  23623 
  23624 #if defined(BCM_88680_A0)
  23625     { /* SOC_REG_INT_XLMAC_SPARE1_BCM88680_A0r */
  23626         soc_block_list[56],
  23627         soc_portreg,
  23628         1,
  23629         0,
  23630         0x60300,
  23631         SOC_REG_FLAG_64_BITS,
  23632         0,
  23633         1,
  23634         soc_XLMAC_SPARE1_BCM88680_A0r_fields,
  23635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23636         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23637         -1,
  23638         -1,
  23639     },
  23640 #endif /* chips */
  23641 
  23642 #if defined(BCM_2801PM_A0)
  23643     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUSTr */
  23644         soc_block_list[56],
  23645         soc_portreg,
  23646         1,
  23647         0,
  23648         0x62000,
  23649         0,
  23650         0,
  23651         3,
  23652         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
  23653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23654         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23655         -1,
  23656         -1,
  23657     },
  23658 #endif /* chips */
  23659 
  23660 #if defined(BCM_53400_A0)
  23661     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM53400_A0r */
  23662         soc_block_list[16],
  23663         soc_portreg,
  23664         1,
  23665         0,
  23666         0x62000,
  23667         SOC_REG_FLAG_64_BITS,
  23668         0,
  23669         3,
  23670         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
  23671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23672         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23673         -1,
  23674         -1,
  23675     },
  23676 #endif /* chips */
  23677 
  23678 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  23679     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM53570_A0r */
  23680         soc_block_list[16],
  23681         soc_portreg,
  23682         1,
  23683         0,
  23684         0x61f00,
  23685         SOC_REG_FLAG_64_BITS,
  23686         0,
  23687         3,
  23688         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
  23689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23690         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23691         -1,
  23692         -1,
  23693     },
  23694 #endif /* chips */
  23695 
  23696 #if defined(BCM_56150_A0)
  23697     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM56150_A0r */
  23698         soc_block_list[16],
  23699         soc_portreg,
  23700         1,
  23701         0,
  23702         0x62000,
  23703         SOC_REG_FLAG_64_BITS,
  23704         0,
  23705         2,
  23706         soc_XLMAC_TIMESTAMP_ADJUST_BCM56850_A0r_fields,
  23707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23708         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  23709         -1,
  23710         -1,
  23711     },
  23712 #endif /* chips */
  23713 
  23714 #if defined(BCM_56160_A0)
  23715     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM56160_A0r */
  23716         soc_block_list[16],
  23717         soc_portreg,
  23718         1,
  23719         0,
  23720         0x62000,
  23721         SOC_REG_FLAG_64_BITS,
  23722         0,
  23723         3,
  23724         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
  23725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23726         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23727         -1,
  23728         -1,
  23729     },
  23730 #endif /* chips */
  23731 
  23732 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  23733     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM56260_A0r */
  23734         soc_block_list[220],
  23735         soc_portreg,
  23736         1,
  23737         0,
  23738         0x62000,
  23739         SOC_REG_FLAG_64_BITS,
  23740         0,
  23741         3,
  23742         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
  23743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23744         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23745         -1,
  23746         -1,
  23747     },
  23748 #endif /* chips */
  23749 
  23750 #if defined(BCM_56270_A0)
  23751     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM56270_A0r */
  23752         soc_block_list[220],
  23753         soc_portreg,
  23754         1,
  23755         0,
  23756         0x62000,
  23757         SOC_REG_FLAG_64_BITS,
  23758         0,
  23759         3,
  23760         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
  23761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23762         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23763         -1,
  23764         -1,
  23765     },
  23766 #endif /* chips */
  23767 
  23768 #if defined(BCM_56370_A0)
  23769     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM56370_A0r */
  23770         soc_block_list[16],
  23771         soc_portreg,
  23772         1,
  23773         0,
  23774         0x62000,
  23775         SOC_REG_FLAG_64_BITS,
  23776         0,
  23777         3,
  23778         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
  23779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23780         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23781         -1,
  23782         -1,
  23783         3,
  23784     },
  23785 #endif /* chips */
  23786 
  23787 #if defined(BCM_56560_A0)
  23788     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM56560_A0r */
  23789         soc_block_list[16],
  23790         soc_portreg,
  23791         1,
  23792         0,
  23793         0x62000,
  23794         SOC_REG_FLAG_64_BITS,
  23795         0,
  23796         3,
  23797         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
  23798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23799         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23800         -1,
  23801         -1,
  23802     },
  23803 #endif /* chips */
  23804 
  23805 #if defined(BCM_56560_B0)
  23806     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM56560_B0r */
  23807         soc_block_list[16],
  23808         soc_portreg,
  23809         1,
  23810         0,
  23811         0x62000,
  23812         SOC_REG_FLAG_64_BITS,
  23813         0,
  23814         3,
  23815         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
  23816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23817         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23818         -1,
  23819         -1,
  23820     },
  23821 #endif /* chips */
  23822 
  23823 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  23824     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM56670_A0r */
  23825         soc_block_list[16],
  23826         soc_portreg,
  23827         1,
  23828         0,
  23829         0x61f00,
  23830         SOC_REG_FLAG_64_BITS,
  23831         0,
  23832         3,
  23833         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
  23834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23835         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23836         -1,
  23837         -1,
  23838     },
  23839 #endif /* chips */
  23840 
  23841 #if defined(BCM_56850_A0)
  23842     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM56850_A0r */
  23843         soc_block_list[16],
  23844         soc_portreg,
  23845         1,
  23846         0,
  23847         0x62000,
  23848         SOC_REG_FLAG_64_BITS,
  23849         0,
  23850         2,
  23851         soc_XLMAC_TIMESTAMP_ADJUST_BCM56850_A0r_fields,
  23852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23853         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  23854         -1,
  23855         -1,
  23856     },
  23857 #endif /* chips */
  23858 
  23859 #if defined(BCM_56860_A0)
  23860     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM56860_A0r */
  23861         soc_block_list[16],
  23862         soc_portreg,
  23863         1,
  23864         0,
  23865         0x62000,
  23866         SOC_REG_FLAG_64_BITS,
  23867         0,
  23868         3,
  23869         soc_CLMAC_TIMESTAMP_ADJUST_BCM56860_A0r_fields,
  23870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23871         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23872         -1,
  23873         -1,
  23874     },
  23875 #endif /* chips */
  23876 
  23877 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  23878     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  23879     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  23880     defined(BCM_56980_B0)
  23881     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM56960_A0r */
  23882         soc_block_list[16],
  23883         soc_portreg,
  23884         1,
  23885         0,
  23886         0x62000,
  23887         SOC_REG_FLAG_64_BITS,
  23888         0,
  23889         3,
  23890         soc_CLMAC_TIMESTAMP_ADJUSTr_fields,
  23891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23892         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23893         -1,
  23894         -1,
  23895         3,
  23896     },
  23897 #endif /* chips */
  23898 
  23899 #if defined(BCM_88270_A0)
  23900     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM88270_A0r */
  23901         soc_block_list[221],
  23902         soc_portreg,
  23903         1,
  23904         0,
  23905         0x62000,
  23906         SOC_REG_FLAG_64_BITS,
  23907         0,
  23908         3,
  23909         soc_XLMAC_TIMESTAMP_ADJUST_BCM88270_A0r_fields,
  23910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23911         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23912         -1,
  23913         -1,
  23914     },
  23915 #endif /* chips */
  23916 
  23917 #if defined(BCM_88375_A0)
  23918     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM88375_A0r */
  23919         soc_block_list[56],
  23920         soc_portreg,
  23921         1,
  23922         0,
  23923         0x62000,
  23924         SOC_REG_FLAG_64_BITS,
  23925         0,
  23926         3,
  23927         soc_XLMAC_TIMESTAMP_ADJUST_BCM88375_A0r_fields,
  23928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23929         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23930         -1,
  23931         -1,
  23932     },
  23933 #endif /* chips */
  23934 
  23935 #if defined(BCM_88375_B0)
  23936     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM88375_B0r */
  23937         soc_block_list[56],
  23938         soc_portreg,
  23939         1,
  23940         0,
  23941         0x62000,
  23942         SOC_REG_FLAG_64_BITS,
  23943         0,
  23944         3,
  23945         soc_XLMAC_TIMESTAMP_ADJUST_BCM88375_B0r_fields,
  23946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23947         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23948         -1,
  23949         -1,
  23950     },
  23951 #endif /* chips */
  23952 
  23953 #if defined(BCM_88470_A0)
  23954     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM88470_A0r */
  23955         soc_block_list[56],
  23956         soc_portreg,
  23957         1,
  23958         0,
  23959         0x62000,
  23960         SOC_REG_FLAG_64_BITS,
  23961         0,
  23962         3,
  23963         soc_XLMAC_TIMESTAMP_ADJUST_BCM88470_A0r_fields,
  23964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23965         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23966         -1,
  23967         -1,
  23968     },
  23969 #endif /* chips */
  23970 
  23971 #if defined(BCM_88470_B0)
  23972     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM88470_B0r */
  23973         soc_block_list[56],
  23974         soc_portreg,
  23975         1,
  23976         0,
  23977         0x62000,
  23978         SOC_REG_FLAG_64_BITS,
  23979         0,
  23980         3,
  23981         soc_XLMAC_TIMESTAMP_ADJUST_BCM88470_B0r_fields,
  23982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23983         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23984         -1,
  23985         -1,
  23986     },
  23987 #endif /* chips */
  23988 
  23989 #if defined(BCM_88675_A0)
  23990     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM88675_A0r */
  23991         soc_block_list[56],
  23992         soc_portreg,
  23993         1,
  23994         0,
  23995         0x62000,
  23996         SOC_REG_FLAG_64_BITS,
  23997         0,
  23998         3,
  23999         soc_XLMAC_TIMESTAMP_ADJUSTr_fields,
  24000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24001         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24002         -1,
  24003         -1,
  24004     },
  24005 #endif /* chips */
  24006 
  24007 #if defined(BCM_88675_B0)
  24008     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM88675_B0r */
  24009         soc_block_list[56],
  24010         soc_portreg,
  24011         1,
  24012         0,
  24013         0x62000,
  24014         SOC_REG_FLAG_64_BITS,
  24015         0,
  24016         3,
  24017         soc_XLMAC_TIMESTAMP_ADJUST_BCM88675_B0r_fields,
  24018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24019         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24020         -1,
  24021         -1,
  24022     },
  24023 #endif /* chips */
  24024 
  24025 #if defined(BCM_88680_A0)
  24026     { /* SOC_REG_INT_XLMAC_TIMESTAMP_ADJUST_BCM88680_A0r */
  24027         soc_block_list[56],
  24028         soc_portreg,
  24029         1,
  24030         0,
  24031         0x62000,
  24032         SOC_REG_FLAG_64_BITS,
  24033         0,
  24034         3,
  24035         soc_XLMAC_TIMESTAMP_ADJUST_BCM88680_A0r_fields,
  24036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24037         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24038         -1,
  24039         -1,
  24040     },
  24041 #endif /* chips */
  24042 
  24043 #if defined(BCM_56860_A0)
  24044     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUSTr */
  24045         soc_block_list[16],
  24046         soc_portreg,
  24047         1,
  24048         0,
  24049         0x62100,
  24050         SOC_REG_FLAG_64_BITS,
  24051         0,
  24052         4,
  24053         soc_XLMAC_TIMESTAMP_BYTE_ADJUSTr_fields,
  24054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24055         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24056         -1,
  24057         -1,
  24058     },
  24059 #endif /* chips */
  24060 
  24061 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  24062     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM53570_A0r */
  24063         soc_block_list[16],
  24064         soc_portreg,
  24065         1,
  24066         0,
  24067         0x62000,
  24068         SOC_REG_FLAG_64_BITS,
  24069         0,
  24070         4,
  24071         soc_XLMAC_B0_TIMESTAMP_BYTE_ADJUSTr_fields,
  24072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24073         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24074         -1,
  24075         -1,
  24076     },
  24077 #endif /* chips */
  24078 
  24079 #if defined(BCM_56160_A0)
  24080     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM56160_A0r */
  24081         soc_block_list[16],
  24082         soc_portreg,
  24083         1,
  24084         0,
  24085         0x62100,
  24086         SOC_REG_FLAG_64_BITS,
  24087         0,
  24088         4,
  24089         soc_XLMAC_B0_TIMESTAMP_BYTE_ADJUSTr_fields,
  24090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24091         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24092         -1,
  24093         -1,
  24094     },
  24095 #endif /* chips */
  24096 
  24097 #if defined(BCM_56260_B0)
  24098     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM56260_B0r */
  24099         soc_block_list[220],
  24100         soc_portreg,
  24101         1,
  24102         0,
  24103         0x62100,
  24104         SOC_REG_FLAG_64_BITS,
  24105         0,
  24106         4,
  24107         soc_XLMAC_B0_TIMESTAMP_BYTE_ADJUSTr_fields,
  24108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24109         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24110         -1,
  24111         -1,
  24112     },
  24113 #endif /* chips */
  24114 
  24115 #if defined(BCM_56270_A0)
  24116     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM56270_A0r */
  24117         soc_block_list[220],
  24118         soc_portreg,
  24119         1,
  24120         0,
  24121         0x62100,
  24122         SOC_REG_FLAG_64_BITS,
  24123         0,
  24124         4,
  24125         soc_XLMAC_B0_TIMESTAMP_BYTE_ADJUSTr_fields,
  24126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24127         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24128         -1,
  24129         -1,
  24130     },
  24131 #endif /* chips */
  24132 
  24133 #if defined(BCM_56370_A0)
  24134     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM56370_A0r */
  24135         soc_block_list[16],
  24136         soc_portreg,
  24137         1,
  24138         0,
  24139         0x62100,
  24140         SOC_REG_FLAG_64_BITS,
  24141         0,
  24142         4,
  24143         soc_XLMAC_B0_TIMESTAMP_BYTE_ADJUSTr_fields,
  24144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24145         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24146         -1,
  24147         -1,
  24148         3,
  24149     },
  24150 #endif /* chips */
  24151 
  24152 #if defined(BCM_56560_B0)
  24153     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM56560_B0r */
  24154         soc_block_list[16],
  24155         soc_portreg,
  24156         1,
  24157         0,
  24158         0x62100,
  24159         SOC_REG_FLAG_64_BITS,
  24160         0,
  24161         4,
  24162         soc_XLMAC_B0_TIMESTAMP_BYTE_ADJUSTr_fields,
  24163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24164         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24165         -1,
  24166         -1,
  24167     },
  24168 #endif /* chips */
  24169 
  24170 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  24171     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM56670_A0r */
  24172         soc_block_list[16],
  24173         soc_portreg,
  24174         1,
  24175         0,
  24176         0x62000,
  24177         SOC_REG_FLAG_64_BITS,
  24178         0,
  24179         4,
  24180         soc_XLMAC_B0_TIMESTAMP_BYTE_ADJUSTr_fields,
  24181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24182         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24183         -1,
  24184         -1,
  24185     },
  24186 #endif /* chips */
  24187 
  24188 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  24189     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  24190     defined(BCM_56980_B0)
  24191     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM56970_A0r */
  24192         soc_block_list[16],
  24193         soc_portreg,
  24194         1,
  24195         0,
  24196         0x62100,
  24197         SOC_REG_FLAG_64_BITS,
  24198         0,
  24199         4,
  24200         soc_XLMAC_B0_TIMESTAMP_BYTE_ADJUSTr_fields,
  24201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24202         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24203         -1,
  24204         -1,
  24205         3,
  24206     },
  24207 #endif /* chips */
  24208 
  24209 #if defined(BCM_88270_A0)
  24210     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88270_A0r */
  24211         soc_block_list[221],
  24212         soc_portreg,
  24213         1,
  24214         0,
  24215         0x62100,
  24216         SOC_REG_FLAG_64_BITS,
  24217         0,
  24218         4,
  24219         soc_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88270_A0r_fields,
  24220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24221         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24222         -1,
  24223         -1,
  24224     },
  24225 #endif /* chips */
  24226 
  24227 #if defined(BCM_88375_B0)
  24228     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88375_B0r */
  24229         soc_block_list[56],
  24230         soc_portreg,
  24231         1,
  24232         0,
  24233         0x62100,
  24234         SOC_REG_FLAG_64_BITS,
  24235         0,
  24236         4,
  24237         soc_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88375_B0r_fields,
  24238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24239         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24240         -1,
  24241         -1,
  24242     },
  24243 #endif /* chips */
  24244 
  24245 #if defined(BCM_88470_B0)
  24246     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88470_B0r */
  24247         soc_block_list[56],
  24248         soc_portreg,
  24249         1,
  24250         0,
  24251         0x62100,
  24252         SOC_REG_FLAG_64_BITS,
  24253         0,
  24254         4,
  24255         soc_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88470_B0r_fields,
  24256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24257         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24258         -1,
  24259         -1,
  24260     },
  24261 #endif /* chips */
  24262 
  24263 #if defined(BCM_88675_B0)
  24264     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88675_B0r */
  24265         soc_block_list[56],
  24266         soc_portreg,
  24267         1,
  24268         0,
  24269         0x62100,
  24270         SOC_REG_FLAG_64_BITS,
  24271         0,
  24272         4,
  24273         soc_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88675_B0r_fields,
  24274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24275         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24276         -1,
  24277         -1,
  24278     },
  24279 #endif /* chips */
  24280 
  24281 #if defined(BCM_88680_A0)
  24282     { /* SOC_REG_INT_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88680_A0r */
  24283         soc_block_list[56],
  24284         soc_portreg,
  24285         1,
  24286         0,
  24287         0x62100,
  24288         SOC_REG_FLAG_64_BITS,
  24289         0,
  24290         4,
  24291         soc_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88680_A0r_fields,
  24292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24293         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  24294         -1,
  24295         -1,
  24296     },
  24297 #endif /* chips */
  24298 
  24299 #if defined(BCM_2801PM_A0)
  24300     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNTr */
  24301         soc_block_list[56],
  24302         soc_portreg,
  24303         1,
  24304         0,
  24305         0x62b00,
  24306         SOC_REG_FLAG_RO,
  24307         0,
  24308         1,
  24309         soc_CLMAC_TXFIFO_CELL_CNTr_fields,
  24310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24311         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24312         -1,
  24313         -1,
  24314     },
  24315 #endif /* chips */
  24316 
  24317 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  24318     defined(BCM_56670_B0)
  24319     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r */
  24320         soc_block_list[16],
  24321         soc_portreg,
  24322         1,
  24323         0,
  24324         0x62b00,
  24325         SOC_REG_FLAG_64_BITS |
  24326                           SOC_REG_FLAG_RO,
  24327         0,
  24328         1,
  24329         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
  24330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24331         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24332         -1,
  24333         -1,
  24334     },
  24335 #endif /* chips */
  24336 
  24337 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  24338     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM53570_A0r */
  24339         soc_block_list[16],
  24340         soc_portreg,
  24341         1,
  24342         0,
  24343         0x62b00,
  24344         SOC_REG_FLAG_64_BITS |
  24345                           SOC_REG_FLAG_RO,
  24346         0,
  24347         1,
  24348         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
  24349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24350         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24351         -1,
  24352         -1,
  24353     },
  24354 #endif /* chips */
  24355 
  24356 #if defined(BCM_56150_A0)
  24357     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56150_A0r */
  24358         soc_block_list[16],
  24359         soc_portreg,
  24360         1,
  24361         0,
  24362         0x62b00,
  24363         SOC_REG_FLAG_64_BITS |
  24364                           SOC_REG_FLAG_RO,
  24365         0,
  24366         1,
  24367         soc_PORT_EHG_RXFIFO_CELL_CNTr_fields,
  24368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24369         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24370         -1,
  24371         -1,
  24372     },
  24373 #endif /* chips */
  24374 
  24375 #if defined(BCM_56160_A0)
  24376     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56160_A0r */
  24377         soc_block_list[16],
  24378         soc_portreg,
  24379         1,
  24380         0,
  24381         0x62c00,
  24382         SOC_REG_FLAG_64_BITS |
  24383                           SOC_REG_FLAG_RO,
  24384         0,
  24385         1,
  24386         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
  24387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24388         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24389         -1,
  24390         -1,
  24391     },
  24392 #endif /* chips */
  24393 
  24394 #if defined(BCM_56260_A0)
  24395     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56260_A0r */
  24396         soc_block_list[220],
  24397         soc_portreg,
  24398         1,
  24399         0,
  24400         0x62b00,
  24401         SOC_REG_FLAG_64_BITS |
  24402                           SOC_REG_FLAG_RO,
  24403         0,
  24404         1,
  24405         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
  24406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24407         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24408         -1,
  24409         -1,
  24410     },
  24411 #endif /* chips */
  24412 
  24413 #if defined(BCM_56260_B0)
  24414     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56260_B0r */
  24415         soc_block_list[220],
  24416         soc_portreg,
  24417         1,
  24418         0,
  24419         0x62c00,
  24420         SOC_REG_FLAG_64_BITS |
  24421                           SOC_REG_FLAG_RO,
  24422         0,
  24423         1,
  24424         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
  24425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24426         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24427         -1,
  24428         -1,
  24429     },
  24430 #endif /* chips */
  24431 
  24432 #if defined(BCM_56270_A0)
  24433     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56270_A0r */
  24434         soc_block_list[220],
  24435         soc_portreg,
  24436         1,
  24437         0,
  24438         0x62c00,
  24439         SOC_REG_FLAG_64_BITS |
  24440                           SOC_REG_FLAG_RO,
  24441         0,
  24442         1,
  24443         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
  24444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24445         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24446         -1,
  24447         -1,
  24448     },
  24449 #endif /* chips */
  24450 
  24451 #if defined(BCM_56370_A0)
  24452     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56370_A0r */
  24453         soc_block_list[16],
  24454         soc_portreg,
  24455         1,
  24456         0,
  24457         0x62c00,
  24458         SOC_REG_FLAG_64_BITS |
  24459                           SOC_REG_FLAG_RO,
  24460         0,
  24461         1,
  24462         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
  24463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24464         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24465         -1,
  24466         -1,
  24467         3,
  24468     },
  24469 #endif /* chips */
  24470 
  24471 #if defined(BCM_56560_A0)
  24472     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56560_A0r */
  24473         soc_block_list[16],
  24474         soc_portreg,
  24475         1,
  24476         0,
  24477         0x62b00,
  24478         SOC_REG_FLAG_64_BITS |
  24479                           SOC_REG_FLAG_RO,
  24480         0,
  24481         1,
  24482         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
  24483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24484         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24485         -1,
  24486         -1,
  24487     },
  24488 #endif /* chips */
  24489 
  24490 #if defined(BCM_56560_B0)
  24491     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56560_B0r */
  24492         soc_block_list[16],
  24493         soc_portreg,
  24494         1,
  24495         0,
  24496         0x62c00,
  24497         SOC_REG_FLAG_64_BITS |
  24498                           SOC_REG_FLAG_RO,
  24499         0,
  24500         1,
  24501         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
  24502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24503         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24504         -1,
  24505         -1,
  24506     },
  24507 #endif /* chips */
  24508 
  24509 #if defined(BCM_56850_A0)
  24510     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56850_A0r */
  24511         soc_block_list[16],
  24512         soc_portreg,
  24513         1,
  24514         0,
  24515         0x62700,
  24516         SOC_REG_FLAG_64_BITS |
  24517                           SOC_REG_FLAG_RO,
  24518         0,
  24519         1,
  24520         soc_PORT_EHG_RXFIFO_CELL_CNTr_fields,
  24521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24522         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24523         -1,
  24524         -1,
  24525     },
  24526 #endif /* chips */
  24527 
  24528 #if defined(BCM_56860_A0)
  24529     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56860_A0r */
  24530         soc_block_list[16],
  24531         soc_portreg,
  24532         1,
  24533         0,
  24534         0x62c00,
  24535         SOC_REG_FLAG_64_BITS |
  24536                           SOC_REG_FLAG_RO,
  24537         0,
  24538         1,
  24539         soc_PORT_EHG_RXFIFO_CELL_CNTr_fields,
  24540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24541         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24542         -1,
  24543         -1,
  24544     },
  24545 #endif /* chips */
  24546 
  24547 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  24548     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56960_A0r */
  24549         soc_block_list[16],
  24550         soc_portreg,
  24551         1,
  24552         0,
  24553         0x62b00,
  24554         SOC_REG_FLAG_64_BITS |
  24555                           SOC_REG_FLAG_RO,
  24556         0,
  24557         1,
  24558         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
  24559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24560         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24561         -1,
  24562         -1,
  24563         3,
  24564     },
  24565 #endif /* chips */
  24566 
  24567 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  24568     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  24569     defined(BCM_56980_B0)
  24570     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM56970_A0r */
  24571         soc_block_list[16],
  24572         soc_portreg,
  24573         1,
  24574         0,
  24575         0x62c00,
  24576         SOC_REG_FLAG_64_BITS |
  24577                           SOC_REG_FLAG_RO,
  24578         0,
  24579         1,
  24580         soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields,
  24581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24582         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24583         -1,
  24584         -1,
  24585         3,
  24586     },
  24587 #endif /* chips */
  24588 
  24589 #if defined(BCM_88270_A0)
  24590     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM88270_A0r */
  24591         soc_block_list[221],
  24592         soc_portreg,
  24593         1,
  24594         0,
  24595         0x62c00,
  24596         SOC_REG_FLAG_64_BITS |
  24597                           SOC_REG_FLAG_RO,
  24598         0,
  24599         1,
  24600         soc_XLMAC_TXFIFO_CELL_CNT_BCM88270_A0r_fields,
  24601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24602         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24603         -1,
  24604         -1,
  24605     },
  24606 #endif /* chips */
  24607 
  24608 #if defined(BCM_88375_A0)
  24609     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM88375_A0r */
  24610         soc_block_list[56],
  24611         soc_portreg,
  24612         1,
  24613         0,
  24614         0x62b00,
  24615         SOC_REG_FLAG_64_BITS |
  24616                           SOC_REG_FLAG_RO,
  24617         0,
  24618         1,
  24619         soc_XLMAC_TXFIFO_CELL_CNT_BCM88375_A0r_fields,
  24620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24621         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24622         -1,
  24623         -1,
  24624     },
  24625 #endif /* chips */
  24626 
  24627 #if defined(BCM_88375_B0)
  24628     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM88375_B0r */
  24629         soc_block_list[56],
  24630         soc_portreg,
  24631         1,
  24632         0,
  24633         0x62c00,
  24634         SOC_REG_FLAG_64_BITS |
  24635                           SOC_REG_FLAG_RO,
  24636         0,
  24637         1,
  24638         soc_XLMAC_TXFIFO_CELL_CNT_BCM88375_B0r_fields,
  24639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24640         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24641         -1,
  24642         -1,
  24643     },
  24644 #endif /* chips */
  24645 
  24646 #if defined(BCM_88470_A0)
  24647     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM88470_A0r */
  24648         soc_block_list[56],
  24649         soc_portreg,
  24650         1,
  24651         0,
  24652         0x62b00,
  24653         SOC_REG_FLAG_64_BITS |
  24654                           SOC_REG_FLAG_RO,
  24655         0,
  24656         1,
  24657         soc_XLMAC_TXFIFO_CELL_CNT_BCM88470_A0r_fields,
  24658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24659         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24660         -1,
  24661         -1,
  24662     },
  24663 #endif /* chips */
  24664 
  24665 #if defined(BCM_88470_B0)
  24666     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM88470_B0r */
  24667         soc_block_list[56],
  24668         soc_portreg,
  24669         1,
  24670         0,
  24671         0x62c00,
  24672         SOC_REG_FLAG_64_BITS |
  24673                           SOC_REG_FLAG_RO,
  24674         0,
  24675         1,
  24676         soc_XLMAC_TXFIFO_CELL_CNT_BCM88470_B0r_fields,
  24677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24678         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24679         -1,
  24680         -1,
  24681     },
  24682 #endif /* chips */
  24683 
  24684 #if defined(BCM_88675_A0)
  24685     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM88675_A0r */
  24686         soc_block_list[56],
  24687         soc_portreg,
  24688         1,
  24689         0,
  24690         0x62b00,
  24691         SOC_REG_FLAG_64_BITS |
  24692                           SOC_REG_FLAG_RO,
  24693         0,
  24694         1,
  24695         soc_XLMAC_TXFIFO_CELL_CNTr_fields,
  24696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24697         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24698         -1,
  24699         -1,
  24700     },
  24701 #endif /* chips */
  24702 
  24703 #if defined(BCM_88675_B0)
  24704     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM88675_B0r */
  24705         soc_block_list[56],
  24706         soc_portreg,
  24707         1,
  24708         0,
  24709         0x62c00,
  24710         SOC_REG_FLAG_64_BITS |
  24711                           SOC_REG_FLAG_RO,
  24712         0,
  24713         1,
  24714         soc_XLMAC_TXFIFO_CELL_CNT_BCM88675_B0r_fields,
  24715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24716         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24717         -1,
  24718         -1,
  24719     },
  24720 #endif /* chips */
  24721 
  24722 #if defined(BCM_88680_A0)
  24723     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_CNT_BCM88680_A0r */
  24724         soc_block_list[56],
  24725         soc_portreg,
  24726         1,
  24727         0,
  24728         0x62c00,
  24729         SOC_REG_FLAG_64_BITS |
  24730                           SOC_REG_FLAG_RO,
  24731         0,
  24732         1,
  24733         soc_XLMAC_TXFIFO_CELL_CNT_BCM88680_A0r_fields,
  24734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24735         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24736         -1,
  24737         -1,
  24738     },
  24739 #endif /* chips */
  24740 
  24741 #if defined(BCM_2801PM_A0)
  24742     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNTr */
  24743         soc_block_list[56],
  24744         soc_portreg,
  24745         1,
  24746         0,
  24747         0x62c00,
  24748         SOC_REG_FLAG_RO,
  24749         0,
  24750         1,
  24751         soc_CLMAC_TXFIFO_CELL_REQ_CNTr_fields,
  24752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24753         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24754         -1,
  24755         -1,
  24756     },
  24757 #endif /* chips */
  24758 
  24759 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  24760     defined(BCM_56670_B0)
  24761     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r */
  24762         soc_block_list[16],
  24763         soc_portreg,
  24764         1,
  24765         0,
  24766         0x62c00,
  24767         SOC_REG_FLAG_64_BITS |
  24768                           SOC_REG_FLAG_RO,
  24769         0,
  24770         1,
  24771         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
  24772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24773         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24774         -1,
  24775         -1,
  24776     },
  24777 #endif /* chips */
  24778 
  24779 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  24780     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53570_A0r */
  24781         soc_block_list[16],
  24782         soc_portreg,
  24783         1,
  24784         0,
  24785         0x62c00,
  24786         SOC_REG_FLAG_64_BITS |
  24787                           SOC_REG_FLAG_RO,
  24788         0,
  24789         1,
  24790         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
  24791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24792         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24793         -1,
  24794         -1,
  24795     },
  24796 #endif /* chips */
  24797 
  24798 #if defined(BCM_56150_A0)
  24799     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56150_A0r */
  24800         soc_block_list[16],
  24801         soc_portreg,
  24802         1,
  24803         0,
  24804         0x62c00,
  24805         SOC_REG_FLAG_64_BITS |
  24806                           SOC_REG_FLAG_RO,
  24807         0,
  24808         1,
  24809         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56850_A0r_fields,
  24810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24811         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24812         -1,
  24813         -1,
  24814     },
  24815 #endif /* chips */
  24816 
  24817 #if defined(BCM_56160_A0)
  24818     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56160_A0r */
  24819         soc_block_list[16],
  24820         soc_portreg,
  24821         1,
  24822         0,
  24823         0x62d00,
  24824         SOC_REG_FLAG_64_BITS |
  24825                           SOC_REG_FLAG_RO,
  24826         0,
  24827         1,
  24828         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
  24829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24830         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24831         -1,
  24832         -1,
  24833     },
  24834 #endif /* chips */
  24835 
  24836 #if defined(BCM_56260_A0)
  24837     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56260_A0r */
  24838         soc_block_list[220],
  24839         soc_portreg,
  24840         1,
  24841         0,
  24842         0x62c00,
  24843         SOC_REG_FLAG_64_BITS |
  24844                           SOC_REG_FLAG_RO,
  24845         0,
  24846         1,
  24847         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
  24848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24849         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24850         -1,
  24851         -1,
  24852     },
  24853 #endif /* chips */
  24854 
  24855 #if defined(BCM_56260_B0)
  24856     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56260_B0r */
  24857         soc_block_list[220],
  24858         soc_portreg,
  24859         1,
  24860         0,
  24861         0x62d00,
  24862         SOC_REG_FLAG_64_BITS |
  24863                           SOC_REG_FLAG_RO,
  24864         0,
  24865         1,
  24866         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
  24867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24868         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24869         -1,
  24870         -1,
  24871     },
  24872 #endif /* chips */
  24873 
  24874 #if defined(BCM_56270_A0)
  24875     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56270_A0r */
  24876         soc_block_list[220],
  24877         soc_portreg,
  24878         1,
  24879         0,
  24880         0x62d00,
  24881         SOC_REG_FLAG_64_BITS |
  24882                           SOC_REG_FLAG_RO,
  24883         0,
  24884         1,
  24885         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
  24886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24887         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24888         -1,
  24889         -1,
  24890     },
  24891 #endif /* chips */
  24892 
  24893 #if defined(BCM_56370_A0)
  24894     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56370_A0r */
  24895         soc_block_list[16],
  24896         soc_portreg,
  24897         1,
  24898         0,
  24899         0x62d00,
  24900         SOC_REG_FLAG_64_BITS |
  24901                           SOC_REG_FLAG_RO,
  24902         0,
  24903         1,
  24904         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
  24905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24906         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24907         -1,
  24908         -1,
  24909         3,
  24910     },
  24911 #endif /* chips */
  24912 
  24913 #if defined(BCM_56560_A0)
  24914     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56560_A0r */
  24915         soc_block_list[16],
  24916         soc_portreg,
  24917         1,
  24918         0,
  24919         0x62c00,
  24920         SOC_REG_FLAG_64_BITS |
  24921                           SOC_REG_FLAG_RO,
  24922         0,
  24923         1,
  24924         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
  24925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24926         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24927         -1,
  24928         -1,
  24929     },
  24930 #endif /* chips */
  24931 
  24932 #if defined(BCM_56560_B0)
  24933     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56560_B0r */
  24934         soc_block_list[16],
  24935         soc_portreg,
  24936         1,
  24937         0,
  24938         0x62d00,
  24939         SOC_REG_FLAG_64_BITS |
  24940                           SOC_REG_FLAG_RO,
  24941         0,
  24942         1,
  24943         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
  24944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24945         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24946         -1,
  24947         -1,
  24948     },
  24949 #endif /* chips */
  24950 
  24951 #if defined(BCM_56850_A0)
  24952     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56850_A0r */
  24953         soc_block_list[16],
  24954         soc_portreg,
  24955         1,
  24956         0,
  24957         0x62800,
  24958         SOC_REG_FLAG_64_BITS |
  24959                           SOC_REG_FLAG_RO,
  24960         0,
  24961         1,
  24962         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56850_A0r_fields,
  24963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24964         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24965         -1,
  24966         -1,
  24967     },
  24968 #endif /* chips */
  24969 
  24970 #if defined(BCM_56860_A0)
  24971     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56860_A0r */
  24972         soc_block_list[16],
  24973         soc_portreg,
  24974         1,
  24975         0,
  24976         0x62d00,
  24977         SOC_REG_FLAG_64_BITS |
  24978                           SOC_REG_FLAG_RO,
  24979         0,
  24980         1,
  24981         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56850_A0r_fields,
  24982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24983         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24984         -1,
  24985         -1,
  24986     },
  24987 #endif /* chips */
  24988 
  24989 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  24990     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56960_A0r */
  24991         soc_block_list[16],
  24992         soc_portreg,
  24993         1,
  24994         0,
  24995         0x62c00,
  24996         SOC_REG_FLAG_64_BITS |
  24997                           SOC_REG_FLAG_RO,
  24998         0,
  24999         1,
  25000         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
  25001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25002         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25003         -1,
  25004         -1,
  25005         3,
  25006     },
  25007 #endif /* chips */
  25008 
  25009 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  25010     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  25011     defined(BCM_56980_B0)
  25012     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56970_A0r */
  25013         soc_block_list[16],
  25014         soc_portreg,
  25015         1,
  25016         0,
  25017         0x62d00,
  25018         SOC_REG_FLAG_64_BITS |
  25019                           SOC_REG_FLAG_RO,
  25020         0,
  25021         1,
  25022         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields,
  25023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25024         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25025         -1,
  25026         -1,
  25027         3,
  25028     },
  25029 #endif /* chips */
  25030 
  25031 #if defined(BCM_88270_A0)
  25032     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88270_A0r */
  25033         soc_block_list[221],
  25034         soc_portreg,
  25035         1,
  25036         0,
  25037         0x62d00,
  25038         SOC_REG_FLAG_64_BITS |
  25039                           SOC_REG_FLAG_RO,
  25040         0,
  25041         1,
  25042         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88270_A0r_fields,
  25043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25044         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25045         -1,
  25046         -1,
  25047     },
  25048 #endif /* chips */
  25049 
  25050 #if defined(BCM_88375_A0)
  25051     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88375_A0r */
  25052         soc_block_list[56],
  25053         soc_portreg,
  25054         1,
  25055         0,
  25056         0x62c00,
  25057         SOC_REG_FLAG_64_BITS |
  25058                           SOC_REG_FLAG_RO,
  25059         0,
  25060         1,
  25061         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88375_A0r_fields,
  25062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25063         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25064         -1,
  25065         -1,
  25066     },
  25067 #endif /* chips */
  25068 
  25069 #if defined(BCM_88375_B0)
  25070     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88375_B0r */
  25071         soc_block_list[56],
  25072         soc_portreg,
  25073         1,
  25074         0,
  25075         0x62d00,
  25076         SOC_REG_FLAG_64_BITS |
  25077                           SOC_REG_FLAG_RO,
  25078         0,
  25079         1,
  25080         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88375_B0r_fields,
  25081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25082         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25083         -1,
  25084         -1,
  25085     },
  25086 #endif /* chips */
  25087 
  25088 #if defined(BCM_88470_A0)
  25089     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88470_A0r */
  25090         soc_block_list[56],
  25091         soc_portreg,
  25092         1,
  25093         0,
  25094         0x62c00,
  25095         SOC_REG_FLAG_64_BITS |
  25096                           SOC_REG_FLAG_RO,
  25097         0,
  25098         1,
  25099         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88470_A0r_fields,
  25100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25101         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25102         -1,
  25103         -1,
  25104     },
  25105 #endif /* chips */
  25106 
  25107 #if defined(BCM_88470_B0)
  25108     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88470_B0r */
  25109         soc_block_list[56],
  25110         soc_portreg,
  25111         1,
  25112         0,
  25113         0x62d00,
  25114         SOC_REG_FLAG_64_BITS |
  25115                           SOC_REG_FLAG_RO,
  25116         0,
  25117         1,
  25118         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88470_B0r_fields,
  25119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25120         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25121         -1,
  25122         -1,
  25123     },
  25124 #endif /* chips */
  25125 
  25126 #if defined(BCM_88675_A0)
  25127     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88675_A0r */
  25128         soc_block_list[56],
  25129         soc_portreg,
  25130         1,
  25131         0,
  25132         0x62c00,
  25133         SOC_REG_FLAG_64_BITS |
  25134                           SOC_REG_FLAG_RO,
  25135         0,
  25136         1,
  25137         soc_XLMAC_TXFIFO_CELL_REQ_CNTr_fields,
  25138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25139         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25140         -1,
  25141         -1,
  25142     },
  25143 #endif /* chips */
  25144 
  25145 #if defined(BCM_88675_B0)
  25146     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88675_B0r */
  25147         soc_block_list[56],
  25148         soc_portreg,
  25149         1,
  25150         0,
  25151         0x62d00,
  25152         SOC_REG_FLAG_64_BITS |
  25153                           SOC_REG_FLAG_RO,
  25154         0,
  25155         1,
  25156         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88675_B0r_fields,
  25157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25158         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25159         -1,
  25160         -1,
  25161     },
  25162 #endif /* chips */
  25163 
  25164 #if defined(BCM_88680_A0)
  25165     { /* SOC_REG_INT_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88680_A0r */
  25166         soc_block_list[56],
  25167         soc_portreg,
  25168         1,
  25169         0,
  25170         0x62d00,
  25171         SOC_REG_FLAG_64_BITS |
  25172                           SOC_REG_FLAG_RO,
  25173         0,
  25174         1,
  25175         soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88680_A0r_fields,
  25176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25177         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25178         -1,
  25179         -1,
  25180     },
  25181 #endif /* chips */
  25182 
  25183 #if defined(BCM_2801PM_A0)
  25184     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUSr */
  25185         soc_block_list[56],
  25186         soc_portreg,
  25187         1,
  25188         0,
  25189         0x63200,
  25190         SOC_REG_FLAG_RO |
  25191                           SOC_REG_FLAG_SIGNAL,
  25192         0,
  25193         2,
  25194         soc_CLMAC_TX_CDC_ECC_STATUSr_fields,
  25195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25196         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25197         -1,
  25198         -1,
  25199     },
  25200 #endif /* chips */
  25201 
  25202 #if defined(BCM_53400_A0)
  25203     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r */
  25204         soc_block_list[16],
  25205         soc_portreg,
  25206         1,
  25207         0,
  25208         0x63200,
  25209         SOC_REG_FLAG_64_BITS |
  25210                           SOC_REG_FLAG_RO,
  25211         0,
  25212         2,
  25213         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25215         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25216         -1,
  25217         -1,
  25218     },
  25219 #endif /* chips */
  25220 
  25221 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  25222     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM53570_A0r */
  25223         soc_block_list[16],
  25224         soc_portreg,
  25225         1,
  25226         0,
  25227         0x63300,
  25228         SOC_REG_FLAG_64_BITS |
  25229                           SOC_REG_FLAG_RO,
  25230         0,
  25231         2,
  25232         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25234         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25235         -1,
  25236         -1,
  25237     },
  25238 #endif /* chips */
  25239 
  25240 #if defined(BCM_56160_A0)
  25241     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM56160_A0r */
  25242         soc_block_list[16],
  25243         soc_portreg,
  25244         1,
  25245         0,
  25246         0x63300,
  25247         SOC_REG_FLAG_64_BITS |
  25248                           SOC_REG_FLAG_RO,
  25249         0,
  25250         2,
  25251         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25253         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25254         -1,
  25255         -1,
  25256     },
  25257 #endif /* chips */
  25258 
  25259 #if defined(BCM_56260_A0)
  25260     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM56260_A0r */
  25261         soc_block_list[220],
  25262         soc_portreg,
  25263         1,
  25264         0,
  25265         0x63200,
  25266         SOC_REG_FLAG_64_BITS |
  25267                           SOC_REG_FLAG_RO,
  25268         0,
  25269         2,
  25270         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25272         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25273         -1,
  25274         -1,
  25275     },
  25276 #endif /* chips */
  25277 
  25278 #if defined(BCM_56260_B0)
  25279     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM56260_B0r */
  25280         soc_block_list[220],
  25281         soc_portreg,
  25282         1,
  25283         0,
  25284         0x63300,
  25285         SOC_REG_FLAG_64_BITS |
  25286                           SOC_REG_FLAG_RO,
  25287         0,
  25288         2,
  25289         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25291         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25292         -1,
  25293         -1,
  25294     },
  25295 #endif /* chips */
  25296 
  25297 #if defined(BCM_56270_A0)
  25298     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM56270_A0r */
  25299         soc_block_list[220],
  25300         soc_portreg,
  25301         1,
  25302         0,
  25303         0x63300,
  25304         SOC_REG_FLAG_64_BITS |
  25305                           SOC_REG_FLAG_RO,
  25306         0,
  25307         2,
  25308         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25310         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25311         -1,
  25312         -1,
  25313     },
  25314 #endif /* chips */
  25315 
  25316 #if defined(BCM_56370_A0)
  25317     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM56370_A0r */
  25318         soc_block_list[16],
  25319         soc_portreg,
  25320         1,
  25321         0,
  25322         0x63300,
  25323         SOC_REG_FLAG_64_BITS |
  25324                           SOC_REG_FLAG_RO,
  25325         0,
  25326         2,
  25327         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25329         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25330         -1,
  25331         -1,
  25332         3,
  25333     },
  25334 #endif /* chips */
  25335 
  25336 #if defined(BCM_56560_A0)
  25337     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM56560_A0r */
  25338         soc_block_list[16],
  25339         soc_portreg,
  25340         1,
  25341         0,
  25342         0x63200,
  25343         SOC_REG_FLAG_64_BITS |
  25344                           SOC_REG_FLAG_RO,
  25345         0,
  25346         2,
  25347         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25349         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25350         -1,
  25351         -1,
  25352     },
  25353 #endif /* chips */
  25354 
  25355 #if defined(BCM_56560_B0)
  25356     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM56560_B0r */
  25357         soc_block_list[16],
  25358         soc_portreg,
  25359         1,
  25360         0,
  25361         0x63300,
  25362         SOC_REG_FLAG_64_BITS |
  25363                           SOC_REG_FLAG_RO,
  25364         0,
  25365         2,
  25366         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25368         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25369         -1,
  25370         -1,
  25371     },
  25372 #endif /* chips */
  25373 
  25374 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  25375     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM56670_A0r */
  25376         soc_block_list[16],
  25377         soc_portreg,
  25378         1,
  25379         0,
  25380         0x63300,
  25381         SOC_REG_FLAG_64_BITS |
  25382                           SOC_REG_FLAG_RO,
  25383         0,
  25384         2,
  25385         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25387         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25388         -1,
  25389         -1,
  25390     },
  25391 #endif /* chips */
  25392 
  25393 #if defined(BCM_56860_A0)
  25394     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM56860_A0r */
  25395         soc_block_list[16],
  25396         soc_portreg,
  25397         1,
  25398         0,
  25399         0x63300,
  25400         SOC_REG_FLAG_64_BITS |
  25401                           SOC_REG_FLAG_RO,
  25402         0,
  25403         2,
  25404         soc_CLMAC_TX_CDC_ECC_STATUS_BCM56860_A0r_fields,
  25405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25406         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25407         -1,
  25408         -1,
  25409     },
  25410 #endif /* chips */
  25411 
  25412 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  25413     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM56960_A0r */
  25414         soc_block_list[16],
  25415         soc_portreg,
  25416         1,
  25417         0,
  25418         0x63200,
  25419         SOC_REG_FLAG_64_BITS |
  25420                           SOC_REG_FLAG_RO,
  25421         0,
  25422         2,
  25423         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25425         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25426         -1,
  25427         -1,
  25428         3,
  25429     },
  25430 #endif /* chips */
  25431 
  25432 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  25433     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  25434     defined(BCM_56980_B0)
  25435     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM56970_A0r */
  25436         soc_block_list[16],
  25437         soc_portreg,
  25438         1,
  25439         0,
  25440         0x63300,
  25441         SOC_REG_FLAG_64_BITS |
  25442                           SOC_REG_FLAG_RO,
  25443         0,
  25444         2,
  25445         soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields,
  25446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25447         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25448         -1,
  25449         -1,
  25450         3,
  25451     },
  25452 #endif /* chips */
  25453 
  25454 #if defined(BCM_88270_A0)
  25455     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM88270_A0r */
  25456         soc_block_list[221],
  25457         soc_portreg,
  25458         1,
  25459         0,
  25460         0x63300,
  25461         SOC_REG_FLAG_64_BITS |
  25462                           SOC_REG_FLAG_RO |
  25463                           SOC_REG_FLAG_SIGNAL,
  25464         0,
  25465         2,
  25466         soc_XLMAC_TX_CDC_ECC_STATUS_BCM88270_A0r_fields,
  25467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25468         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25469         -1,
  25470         -1,
  25471     },
  25472 #endif /* chips */
  25473 
  25474 #if defined(BCM_88375_A0)
  25475     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM88375_A0r */
  25476         soc_block_list[56],
  25477         soc_portreg,
  25478         1,
  25479         0,
  25480         0x63200,
  25481         SOC_REG_FLAG_64_BITS |
  25482                           SOC_REG_FLAG_RO |
  25483                           SOC_REG_FLAG_SIGNAL,
  25484         0,
  25485         2,
  25486         soc_XLMAC_TX_CDC_ECC_STATUS_BCM88375_A0r_fields,
  25487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25488         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25489         -1,
  25490         -1,
  25491     },
  25492 #endif /* chips */
  25493 
  25494 #if defined(BCM_88375_B0)
  25495     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM88375_B0r */
  25496         soc_block_list[56],
  25497         soc_portreg,
  25498         1,
  25499         0,
  25500         0x63300,
  25501         SOC_REG_FLAG_64_BITS |
  25502                           SOC_REG_FLAG_RO |
  25503                           SOC_REG_FLAG_SIGNAL,
  25504         0,
  25505         2,
  25506         soc_XLMAC_TX_CDC_ECC_STATUS_BCM88375_B0r_fields,
  25507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25508         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25509         -1,
  25510         -1,
  25511     },
  25512 #endif /* chips */
  25513 
  25514 #if defined(BCM_88470_A0)
  25515     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM88470_A0r */
  25516         soc_block_list[56],
  25517         soc_portreg,
  25518         1,
  25519         0,
  25520         0x63200,
  25521         SOC_REG_FLAG_64_BITS |
  25522                           SOC_REG_FLAG_RO |
  25523                           SOC_REG_FLAG_SIGNAL,
  25524         0,
  25525         2,
  25526         soc_XLMAC_TX_CDC_ECC_STATUS_BCM88470_A0r_fields,
  25527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25528         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25529         -1,
  25530         -1,
  25531     },
  25532 #endif /* chips */
  25533 
  25534 #if defined(BCM_88470_B0)
  25535     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM88470_B0r */
  25536         soc_block_list[56],
  25537         soc_portreg,
  25538         1,
  25539         0,
  25540         0x63300,
  25541         SOC_REG_FLAG_64_BITS |
  25542                           SOC_REG_FLAG_RO |
  25543                           SOC_REG_FLAG_SIGNAL,
  25544         0,
  25545         2,
  25546         soc_XLMAC_TX_CDC_ECC_STATUS_BCM88470_B0r_fields,
  25547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25548         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25549         -1,
  25550         -1,
  25551     },
  25552 #endif /* chips */
  25553 
  25554 #if defined(BCM_88675_A0)
  25555     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM88675_A0r */
  25556         soc_block_list[56],
  25557         soc_portreg,
  25558         1,
  25559         0,
  25560         0x63200,
  25561         SOC_REG_FLAG_64_BITS |
  25562                           SOC_REG_FLAG_RO |
  25563                           SOC_REG_FLAG_SIGNAL,
  25564         0,
  25565         2,
  25566         soc_XLMAC_TX_CDC_ECC_STATUSr_fields,
  25567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25568         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25569         -1,
  25570         -1,
  25571     },
  25572 #endif /* chips */
  25573 
  25574 #if defined(BCM_88675_B0)
  25575     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM88675_B0r */
  25576         soc_block_list[56],
  25577         soc_portreg,
  25578         1,
  25579         0,
  25580         0x63300,
  25581         SOC_REG_FLAG_64_BITS |
  25582                           SOC_REG_FLAG_RO |
  25583                           SOC_REG_FLAG_SIGNAL,
  25584         0,
  25585         2,
  25586         soc_XLMAC_TX_CDC_ECC_STATUS_BCM88675_B0r_fields,
  25587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25588         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25589         -1,
  25590         -1,
  25591     },
  25592 #endif /* chips */
  25593 
  25594 #if defined(BCM_88680_A0)
  25595     { /* SOC_REG_INT_XLMAC_TX_CDC_ECC_STATUS_BCM88680_A0r */
  25596         soc_block_list[56],
  25597         soc_portreg,
  25598         1,
  25599         0,
  25600         0x63300,
  25601         SOC_REG_FLAG_64_BITS |
  25602                           SOC_REG_FLAG_RO |
  25603                           SOC_REG_FLAG_SIGNAL,
  25604         0,
  25605         2,
  25606         soc_XLMAC_TX_CDC_ECC_STATUS_BCM88680_A0r_fields,
  25607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25608         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  25609         -1,
  25610         -1,
  25611     },
  25612 #endif /* chips */
  25613 
  25614 #if defined(BCM_2801PM_A0)
  25615     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRLr */
  25616         soc_block_list[56],
  25617         soc_portreg,
  25618         1,
  25619         0,
  25620         0x62100,
  25621         SOC_REG_FLAG_64_BITS,
  25622         0,
  25623         4,
  25624         soc_CLMAC_TX_CRC_CORRUPT_CTRLr_fields,
  25625         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25626         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25627         -1,
  25628         -1,
  25629     },
  25630 #endif /* chips */
  25631 
  25632 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  25633     defined(BCM_56670_B0)
  25634     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r */
  25635         soc_block_list[16],
  25636         soc_portreg,
  25637         1,
  25638         0,
  25639         0x62100,
  25640         SOC_REG_FLAG_64_BITS,
  25641         0,
  25642         6,
  25643         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
  25644         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25646         -1,
  25647         -1,
  25648     },
  25649 #endif /* chips */
  25650 
  25651 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  25652     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53570_A0r */
  25653         soc_block_list[16],
  25654         soc_portreg,
  25655         1,
  25656         0,
  25657         0x62100,
  25658         SOC_REG_FLAG_64_BITS,
  25659         0,
  25660         6,
  25661         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
  25662         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25663         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25664         -1,
  25665         -1,
  25666     },
  25667 #endif /* chips */
  25668 
  25669 #if defined(BCM_56160_A0)
  25670     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56160_A0r */
  25671         soc_block_list[16],
  25672         soc_portreg,
  25673         1,
  25674         0,
  25675         0x62200,
  25676         SOC_REG_FLAG_64_BITS,
  25677         0,
  25678         6,
  25679         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
  25680         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25681         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25682         -1,
  25683         -1,
  25684     },
  25685 #endif /* chips */
  25686 
  25687 #if defined(BCM_56260_A0)
  25688     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56260_A0r */
  25689         soc_block_list[220],
  25690         soc_portreg,
  25691         1,
  25692         0,
  25693         0x62100,
  25694         SOC_REG_FLAG_64_BITS,
  25695         0,
  25696         6,
  25697         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
  25698         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25699         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25700         -1,
  25701         -1,
  25702     },
  25703 #endif /* chips */
  25704 
  25705 #if defined(BCM_56260_B0)
  25706     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56260_B0r */
  25707         soc_block_list[220],
  25708         soc_portreg,
  25709         1,
  25710         0,
  25711         0x62200,
  25712         SOC_REG_FLAG_64_BITS,
  25713         0,
  25714         6,
  25715         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
  25716         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25718         -1,
  25719         -1,
  25720     },
  25721 #endif /* chips */
  25722 
  25723 #if defined(BCM_56270_A0)
  25724     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56270_A0r */
  25725         soc_block_list[220],
  25726         soc_portreg,
  25727         1,
  25728         0,
  25729         0x62200,
  25730         SOC_REG_FLAG_64_BITS,
  25731         0,
  25732         6,
  25733         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
  25734         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25736         -1,
  25737         -1,
  25738     },
  25739 #endif /* chips */
  25740 
  25741 #if defined(BCM_56370_A0)
  25742     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56370_A0r */
  25743         soc_block_list[16],
  25744         soc_portreg,
  25745         1,
  25746         0,
  25747         0x62200,
  25748         SOC_REG_FLAG_64_BITS,
  25749         0,
  25750         6,
  25751         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
  25752         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25753         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25754         -1,
  25755         -1,
  25756         3,
  25757     },
  25758 #endif /* chips */
  25759 
  25760 #if defined(BCM_56560_A0)
  25761     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56560_A0r */
  25762         soc_block_list[16],
  25763         soc_portreg,
  25764         1,
  25765         0,
  25766         0x62100,
  25767         SOC_REG_FLAG_64_BITS,
  25768         0,
  25769         6,
  25770         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
  25771         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25772         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25773         -1,
  25774         -1,
  25775     },
  25776 #endif /* chips */
  25777 
  25778 #if defined(BCM_56560_B0)
  25779     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56560_B0r */
  25780         soc_block_list[16],
  25781         soc_portreg,
  25782         1,
  25783         0,
  25784         0x62200,
  25785         SOC_REG_FLAG_64_BITS,
  25786         0,
  25787         6,
  25788         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
  25789         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25790         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25791         -1,
  25792         -1,
  25793     },
  25794 #endif /* chips */
  25795 
  25796 #if defined(BCM_56860_A0)
  25797     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56860_A0r */
  25798         soc_block_list[16],
  25799         soc_portreg,
  25800         1,
  25801         0,
  25802         0x62200,
  25803         SOC_REG_FLAG_64_BITS,
  25804         0,
  25805         6,
  25806         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56860_A0r_fields,
  25807         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25808         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25809         -1,
  25810         -1,
  25811     },
  25812 #endif /* chips */
  25813 
  25814 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  25815     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56960_A0r */
  25816         soc_block_list[16],
  25817         soc_portreg,
  25818         1,
  25819         0,
  25820         0x62100,
  25821         SOC_REG_FLAG_64_BITS,
  25822         0,
  25823         6,
  25824         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
  25825         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25826         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25827         -1,
  25828         -1,
  25829         3,
  25830     },
  25831 #endif /* chips */
  25832 
  25833 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  25834     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  25835     defined(BCM_56980_B0)
  25836     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56970_A0r */
  25837         soc_block_list[16],
  25838         soc_portreg,
  25839         1,
  25840         0,
  25841         0x62200,
  25842         SOC_REG_FLAG_64_BITS,
  25843         0,
  25844         6,
  25845         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields,
  25846         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25847         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25848         -1,
  25849         -1,
  25850         3,
  25851     },
  25852 #endif /* chips */
  25853 
  25854 #if defined(BCM_88270_A0)
  25855     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88270_A0r */
  25856         soc_block_list[221],
  25857         soc_portreg,
  25858         1,
  25859         0,
  25860         0x62200,
  25861         SOC_REG_FLAG_64_BITS,
  25862         0,
  25863         4,
  25864         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88270_A0r_fields,
  25865         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25866         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25867         -1,
  25868         -1,
  25869     },
  25870 #endif /* chips */
  25871 
  25872 #if defined(BCM_88375_A0)
  25873     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88375_A0r */
  25874         soc_block_list[56],
  25875         soc_portreg,
  25876         1,
  25877         0,
  25878         0x62100,
  25879         SOC_REG_FLAG_64_BITS,
  25880         0,
  25881         4,
  25882         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88375_A0r_fields,
  25883         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25884         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25885         -1,
  25886         -1,
  25887     },
  25888 #endif /* chips */
  25889 
  25890 #if defined(BCM_88375_B0)
  25891     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88375_B0r */
  25892         soc_block_list[56],
  25893         soc_portreg,
  25894         1,
  25895         0,
  25896         0x62200,
  25897         SOC_REG_FLAG_64_BITS,
  25898         0,
  25899         4,
  25900         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88375_B0r_fields,
  25901         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25902         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25903         -1,
  25904         -1,
  25905     },
  25906 #endif /* chips */
  25907 
  25908 #if defined(BCM_88470_A0)
  25909     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88470_A0r */
  25910         soc_block_list[56],
  25911         soc_portreg,
  25912         1,
  25913         0,
  25914         0x62100,
  25915         SOC_REG_FLAG_64_BITS,
  25916         0,
  25917         4,
  25918         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88470_A0r_fields,
  25919         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25920         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25921         -1,
  25922         -1,
  25923     },
  25924 #endif /* chips */
  25925 
  25926 #if defined(BCM_88470_B0)
  25927     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88470_B0r */
  25928         soc_block_list[56],
  25929         soc_portreg,
  25930         1,
  25931         0,
  25932         0x62200,
  25933         SOC_REG_FLAG_64_BITS,
  25934         0,
  25935         4,
  25936         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88470_B0r_fields,
  25937         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25938         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25939         -1,
  25940         -1,
  25941     },
  25942 #endif /* chips */
  25943 
  25944 #if defined(BCM_88675_A0)
  25945     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88675_A0r */
  25946         soc_block_list[56],
  25947         soc_portreg,
  25948         1,
  25949         0,
  25950         0x62100,
  25951         SOC_REG_FLAG_64_BITS,
  25952         0,
  25953         4,
  25954         soc_XLMAC_TX_CRC_CORRUPT_CTRLr_fields,
  25955         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25956         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25957         -1,
  25958         -1,
  25959     },
  25960 #endif /* chips */
  25961 
  25962 #if defined(BCM_88675_B0)
  25963     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88675_B0r */
  25964         soc_block_list[56],
  25965         soc_portreg,
  25966         1,
  25967         0,
  25968         0x62200,
  25969         SOC_REG_FLAG_64_BITS,
  25970         0,
  25971         4,
  25972         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88675_B0r_fields,
  25973         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25974         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25975         -1,
  25976         -1,
  25977     },
  25978 #endif /* chips */
  25979 
  25980 #if defined(BCM_88680_A0)
  25981     { /* SOC_REG_INT_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88680_A0r */
  25982         soc_block_list[56],
  25983         soc_portreg,
  25984         1,
  25985         0,
  25986         0x62200,
  25987         SOC_REG_FLAG_64_BITS,
  25988         0,
  25989         4,
  25990         soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88680_A0r_fields,
  25991         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  25992         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25993         -1,
  25994         -1,
  25995     },
  25996 #endif /* chips */
  25997 
  25998 #if defined(BCM_2801PM_A0)
  25999     { /* SOC_REG_INT_XLMAC_TX_CTRLr */
  26000         soc_block_list[56],
  26001         soc_portreg,
  26002         1,
  26003         0,
  26004         0x60400,
  26005         SOC_REG_FLAG_64_BITS,
  26006         0,
  26007         11,
  26008         soc_CLMAC_TX_CTRLr_fields,
  26009         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26010         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26011         -1,
  26012         -1,
  26013     },
  26014 #endif /* chips */
  26015 
  26016 #if defined(BCM_53400_A0)
  26017     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM53400_A0r */
  26018         soc_block_list[16],
  26019         soc_portreg,
  26020         1,
  26021         0,
  26022         0x60400,
  26023         SOC_REG_FLAG_64_BITS,
  26024         0,
  26025         13,
  26026         soc_XLMAC_TX_CTRL_BCM53400_A0r_fields,
  26027         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26028         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26029         -1,
  26030         -1,
  26031     },
  26032 #endif /* chips */
  26033 
  26034 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  26035     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM53570_A0r */
  26036         soc_block_list[16],
  26037         soc_portreg,
  26038         1,
  26039         0,
  26040         0x60300,
  26041         SOC_REG_FLAG_64_BITS,
  26042         0,
  26043         13,
  26044         soc_XLMAC_TX_CTRL_BCM53400_A0r_fields,
  26045         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26046         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26047         -1,
  26048         -1,
  26049     },
  26050 #endif /* chips */
  26051 
  26052 #if defined(BCM_56150_A0)
  26053     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM56150_A0r */
  26054         soc_block_list[16],
  26055         soc_portreg,
  26056         1,
  26057         0,
  26058         0x60400,
  26059         SOC_REG_FLAG_64_BITS,
  26060         0,
  26061         12,
  26062         soc_XLMAC_TX_CTRL_BCM56850_A0r_fields,
  26063         SOC_RESET_VAL_DEC(0x0000c802, 0x00000010)
  26064         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  26065         -1,
  26066         -1,
  26067     },
  26068 #endif /* chips */
  26069 
  26070 #if defined(BCM_56160_A0)
  26071     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM56160_A0r */
  26072         soc_block_list[16],
  26073         soc_portreg,
  26074         1,
  26075         0,
  26076         0x60400,
  26077         SOC_REG_FLAG_64_BITS,
  26078         0,
  26079         13,
  26080         soc_XLMAC_TX_CTRL_BCM53400_A0r_fields,
  26081         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26082         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26083         -1,
  26084         -1,
  26085     },
  26086 #endif /* chips */
  26087 
  26088 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  26089     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM56260_A0r */
  26090         soc_block_list[220],
  26091         soc_portreg,
  26092         1,
  26093         0,
  26094         0x60400,
  26095         SOC_REG_FLAG_64_BITS,
  26096         0,
  26097         13,
  26098         soc_XLMAC_TX_CTRL_BCM53400_A0r_fields,
  26099         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26100         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26101         -1,
  26102         -1,
  26103     },
  26104 #endif /* chips */
  26105 
  26106 #if defined(BCM_56270_A0)
  26107     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM56270_A0r */
  26108         soc_block_list[220],
  26109         soc_portreg,
  26110         1,
  26111         0,
  26112         0x60400,
  26113         SOC_REG_FLAG_64_BITS,
  26114         0,
  26115         13,
  26116         soc_XLMAC_TX_CTRL_BCM53400_A0r_fields,
  26117         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26118         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26119         -1,
  26120         -1,
  26121     },
  26122 #endif /* chips */
  26123 
  26124 #if defined(BCM_56370_A0)
  26125     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM56370_A0r */
  26126         soc_block_list[16],
  26127         soc_portreg,
  26128         1,
  26129         0,
  26130         0x60400,
  26131         SOC_REG_FLAG_64_BITS,
  26132         0,
  26133         13,
  26134         soc_XLMAC_TX_CTRL_BCM53400_A0r_fields,
  26135         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26136         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26137         -1,
  26138         -1,
  26139         3,
  26140     },
  26141 #endif /* chips */
  26142 
  26143 #if defined(BCM_56560_A0)
  26144     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM56560_A0r */
  26145         soc_block_list[16],
  26146         soc_portreg,
  26147         1,
  26148         0,
  26149         0x60400,
  26150         SOC_REG_FLAG_64_BITS,
  26151         0,
  26152         13,
  26153         soc_XLMAC_TX_CTRL_BCM53400_A0r_fields,
  26154         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26155         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26156         -1,
  26157         -1,
  26158     },
  26159 #endif /* chips */
  26160 
  26161 #if defined(BCM_56560_B0)
  26162     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM56560_B0r */
  26163         soc_block_list[16],
  26164         soc_portreg,
  26165         1,
  26166         0,
  26167         0x60400,
  26168         SOC_REG_FLAG_64_BITS,
  26169         0,
  26170         13,
  26171         soc_XLMAC_TX_CTRL_BCM53400_A0r_fields,
  26172         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26173         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26174         -1,
  26175         -1,
  26176     },
  26177 #endif /* chips */
  26178 
  26179 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  26180     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM56670_A0r */
  26181         soc_block_list[16],
  26182         soc_portreg,
  26183         1,
  26184         0,
  26185         0x60300,
  26186         SOC_REG_FLAG_64_BITS,
  26187         0,
  26188         13,
  26189         soc_XLMAC_TX_CTRL_BCM53400_A0r_fields,
  26190         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26191         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26192         -1,
  26193         -1,
  26194     },
  26195 #endif /* chips */
  26196 
  26197 #if defined(BCM_56850_A0)
  26198     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM56850_A0r */
  26199         soc_block_list[16],
  26200         soc_portreg,
  26201         1,
  26202         0,
  26203         0x60400,
  26204         SOC_REG_FLAG_64_BITS,
  26205         0,
  26206         12,
  26207         soc_XLMAC_TX_CTRL_BCM56850_A0r_fields,
  26208         SOC_RESET_VAL_DEC(0x0000c802, 0x00000010)
  26209         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  26210         -1,
  26211         -1,
  26212     },
  26213 #endif /* chips */
  26214 
  26215 #if defined(BCM_56860_A0)
  26216     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM56860_A0r */
  26217         soc_block_list[16],
  26218         soc_portreg,
  26219         1,
  26220         0,
  26221         0x60400,
  26222         SOC_REG_FLAG_64_BITS,
  26223         0,
  26224         13,
  26225         soc_XLMAC_TX_CTRL_BCM56860_A0r_fields,
  26226         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26227         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26228         -1,
  26229         -1,
  26230     },
  26231 #endif /* chips */
  26232 
  26233 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  26234     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  26235     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  26236     defined(BCM_56980_B0)
  26237     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM56960_A0r */
  26238         soc_block_list[16],
  26239         soc_portreg,
  26240         1,
  26241         0,
  26242         0x60400,
  26243         SOC_REG_FLAG_64_BITS,
  26244         0,
  26245         13,
  26246         soc_XLMAC_TX_CTRL_BCM53400_A0r_fields,
  26247         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26248         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26249         -1,
  26250         -1,
  26251         3,
  26252     },
  26253 #endif /* chips */
  26254 
  26255 #if defined(BCM_88270_A0)
  26256     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM88270_A0r */
  26257         soc_block_list[221],
  26258         soc_portreg,
  26259         1,
  26260         0,
  26261         0x60400,
  26262         SOC_REG_FLAG_64_BITS,
  26263         0,
  26264         11,
  26265         soc_XLMAC_TX_CTRL_BCM88270_A0r_fields,
  26266         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26267         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26268         -1,
  26269         -1,
  26270     },
  26271 #endif /* chips */
  26272 
  26273 #if defined(BCM_88375_A0)
  26274     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM88375_A0r */
  26275         soc_block_list[56],
  26276         soc_portreg,
  26277         1,
  26278         0,
  26279         0x60400,
  26280         SOC_REG_FLAG_64_BITS,
  26281         0,
  26282         11,
  26283         soc_XLMAC_TX_CTRL_BCM88375_A0r_fields,
  26284         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26285         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26286         -1,
  26287         -1,
  26288     },
  26289 #endif /* chips */
  26290 
  26291 #if defined(BCM_88375_B0)
  26292     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM88375_B0r */
  26293         soc_block_list[56],
  26294         soc_portreg,
  26295         1,
  26296         0,
  26297         0x60400,
  26298         SOC_REG_FLAG_64_BITS,
  26299         0,
  26300         11,
  26301         soc_XLMAC_TX_CTRL_BCM88375_B0r_fields,
  26302         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26303         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26304         -1,
  26305         -1,
  26306     },
  26307 #endif /* chips */
  26308 
  26309 #if defined(BCM_88470_A0)
  26310     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM88470_A0r */
  26311         soc_block_list[56],
  26312         soc_portreg,
  26313         1,
  26314         0,
  26315         0x60400,
  26316         SOC_REG_FLAG_64_BITS,
  26317         0,
  26318         11,
  26319         soc_XLMAC_TX_CTRL_BCM88470_A0r_fields,
  26320         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26321         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26322         -1,
  26323         -1,
  26324     },
  26325 #endif /* chips */
  26326 
  26327 #if defined(BCM_88470_B0)
  26328     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM88470_B0r */
  26329         soc_block_list[56],
  26330         soc_portreg,
  26331         1,
  26332         0,
  26333         0x60400,
  26334         SOC_REG_FLAG_64_BITS,
  26335         0,
  26336         11,
  26337         soc_XLMAC_TX_CTRL_BCM88470_B0r_fields,
  26338         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26339         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26340         -1,
  26341         -1,
  26342     },
  26343 #endif /* chips */
  26344 
  26345 #if defined(BCM_88675_A0)
  26346     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM88675_A0r */
  26347         soc_block_list[56],
  26348         soc_portreg,
  26349         1,
  26350         0,
  26351         0x60400,
  26352         SOC_REG_FLAG_64_BITS,
  26353         0,
  26354         11,
  26355         soc_XLMAC_TX_CTRLr_fields,
  26356         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26357         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26358         -1,
  26359         -1,
  26360     },
  26361 #endif /* chips */
  26362 
  26363 #if defined(BCM_88675_B0)
  26364     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM88675_B0r */
  26365         soc_block_list[56],
  26366         soc_portreg,
  26367         1,
  26368         0,
  26369         0x60400,
  26370         SOC_REG_FLAG_64_BITS,
  26371         0,
  26372         11,
  26373         soc_XLMAC_TX_CTRL_BCM88675_B0r_fields,
  26374         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26375         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26376         -1,
  26377         -1,
  26378     },
  26379 #endif /* chips */
  26380 
  26381 #if defined(BCM_88680_A0)
  26382     { /* SOC_REG_INT_XLMAC_TX_CTRL_BCM88680_A0r */
  26383         soc_block_list[56],
  26384         soc_portreg,
  26385         1,
  26386         0,
  26387         0x60400,
  26388         SOC_REG_FLAG_64_BITS,
  26389         0,
  26390         11,
  26391         soc_XLMAC_TX_CTRL_BCM88680_A0r_fields,
  26392         SOC_RESET_VAL_DEC(0x0000c802, 0x00000050)
  26393         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  26394         -1,
  26395         -1,
  26396     },
  26397 #endif /* chips */
  26398 
  26399 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  26400     { /* SOC_REG_INT_XLMAC_TX_EP_CREDITS_CONFIGr */
  26401         soc_block_list[16],
  26402         soc_portreg,
  26403         1,
  26404         0,
  26405         0x62e00,
  26406         SOC_REG_FLAG_64_BITS,
  26407         0,
  26408         1,
  26409         soc_XLMAC_TX_EP_CREDITS_CONFIGr_fields,
  26410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26411         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26412         -1,
  26413         -1,
  26414     },
  26415 #endif /* chips */
  26416 
  26417 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  26418     { /* SOC_REG_INT_XLMAC_TX_EP_CREDITS_CONFIG_BCM56670_A0r */
  26419         soc_block_list[16],
  26420         soc_portreg,
  26421         1,
  26422         0,
  26423         0x62e00,
  26424         SOC_REG_FLAG_64_BITS,
  26425         0,
  26426         1,
  26427         soc_XLMAC_TX_EP_CREDITS_CONFIGr_fields,
  26428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26429         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  26430         -1,
  26431         -1,
  26432     },
  26433 #endif /* chips */
  26434 
  26435 #if defined(BCM_2801PM_A0)
  26436     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDSr */
  26437         soc_block_list[56],
  26438         soc_portreg,
  26439         1,
  26440         0,
  26441         0x61300,
  26442         0,
  26443         0,
  26444         3,
  26445         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26446         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26447         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26448         -1,
  26449         -1,
  26450     },
  26451 #endif /* chips */
  26452 
  26453 #if defined(BCM_53400_A0)
  26454     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM53400_A0r */
  26455         soc_block_list[16],
  26456         soc_portreg,
  26457         1,
  26458         0,
  26459         0x61300,
  26460         SOC_REG_FLAG_64_BITS,
  26461         0,
  26462         3,
  26463         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26464         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26465         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26466         -1,
  26467         -1,
  26468     },
  26469 #endif /* chips */
  26470 
  26471 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  26472     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM53570_A0r */
  26473         soc_block_list[16],
  26474         soc_portreg,
  26475         1,
  26476         0,
  26477         0x61200,
  26478         SOC_REG_FLAG_64_BITS,
  26479         0,
  26480         3,
  26481         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26482         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26483         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26484         -1,
  26485         -1,
  26486     },
  26487 #endif /* chips */
  26488 
  26489 #if defined(BCM_56150_A0)
  26490     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM56150_A0r */
  26491         soc_block_list[16],
  26492         soc_portreg,
  26493         1,
  26494         0,
  26495         0x61300,
  26496         SOC_REG_FLAG_64_BITS,
  26497         0,
  26498         3,
  26499         soc_CMAC_TX_LLFC_MSG_FIELDSr_fields,
  26500         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26501         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26502         -1,
  26503         -1,
  26504     },
  26505 #endif /* chips */
  26506 
  26507 #if defined(BCM_56160_A0)
  26508     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM56160_A0r */
  26509         soc_block_list[16],
  26510         soc_portreg,
  26511         1,
  26512         0,
  26513         0x61300,
  26514         SOC_REG_FLAG_64_BITS,
  26515         0,
  26516         3,
  26517         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26518         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26519         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26520         -1,
  26521         -1,
  26522     },
  26523 #endif /* chips */
  26524 
  26525 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  26526     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM56260_A0r */
  26527         soc_block_list[220],
  26528         soc_portreg,
  26529         1,
  26530         0,
  26531         0x61300,
  26532         SOC_REG_FLAG_64_BITS,
  26533         0,
  26534         3,
  26535         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26536         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26537         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26538         -1,
  26539         -1,
  26540     },
  26541 #endif /* chips */
  26542 
  26543 #if defined(BCM_56270_A0)
  26544     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM56270_A0r */
  26545         soc_block_list[220],
  26546         soc_portreg,
  26547         1,
  26548         0,
  26549         0x61300,
  26550         SOC_REG_FLAG_64_BITS,
  26551         0,
  26552         3,
  26553         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26554         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26555         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26556         -1,
  26557         -1,
  26558     },
  26559 #endif /* chips */
  26560 
  26561 #if defined(BCM_56370_A0)
  26562     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM56370_A0r */
  26563         soc_block_list[16],
  26564         soc_portreg,
  26565         1,
  26566         0,
  26567         0x61300,
  26568         SOC_REG_FLAG_64_BITS,
  26569         0,
  26570         3,
  26571         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26572         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26573         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26574         -1,
  26575         -1,
  26576         3,
  26577     },
  26578 #endif /* chips */
  26579 
  26580 #if defined(BCM_56560_A0)
  26581     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM56560_A0r */
  26582         soc_block_list[16],
  26583         soc_portreg,
  26584         1,
  26585         0,
  26586         0x61300,
  26587         SOC_REG_FLAG_64_BITS,
  26588         0,
  26589         3,
  26590         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26591         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26592         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26593         -1,
  26594         -1,
  26595     },
  26596 #endif /* chips */
  26597 
  26598 #if defined(BCM_56560_B0)
  26599     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM56560_B0r */
  26600         soc_block_list[16],
  26601         soc_portreg,
  26602         1,
  26603         0,
  26604         0x61300,
  26605         SOC_REG_FLAG_64_BITS,
  26606         0,
  26607         3,
  26608         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26609         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26610         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26611         -1,
  26612         -1,
  26613     },
  26614 #endif /* chips */
  26615 
  26616 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  26617     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM56670_A0r */
  26618         soc_block_list[16],
  26619         soc_portreg,
  26620         1,
  26621         0,
  26622         0x61200,
  26623         SOC_REG_FLAG_64_BITS,
  26624         0,
  26625         3,
  26626         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26627         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26628         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26629         -1,
  26630         -1,
  26631     },
  26632 #endif /* chips */
  26633 
  26634 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  26635     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM56850_A0r */
  26636         soc_block_list[16],
  26637         soc_portreg,
  26638         1,
  26639         0,
  26640         0x61300,
  26641         SOC_REG_FLAG_64_BITS,
  26642         0,
  26643         3,
  26644         soc_CMAC_TX_LLFC_MSG_FIELDSr_fields,
  26645         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26646         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26647         -1,
  26648         -1,
  26649     },
  26650 #endif /* chips */
  26651 
  26652 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  26653     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  26654     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  26655     defined(BCM_56980_B0)
  26656     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM56960_A0r */
  26657         soc_block_list[16],
  26658         soc_portreg,
  26659         1,
  26660         0,
  26661         0x61300,
  26662         SOC_REG_FLAG_64_BITS,
  26663         0,
  26664         3,
  26665         soc_CLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26666         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26667         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26668         -1,
  26669         -1,
  26670         3,
  26671     },
  26672 #endif /* chips */
  26673 
  26674 #if defined(BCM_88270_A0)
  26675     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM88270_A0r */
  26676         soc_block_list[221],
  26677         soc_portreg,
  26678         1,
  26679         0,
  26680         0x61300,
  26681         SOC_REG_FLAG_64_BITS,
  26682         0,
  26683         3,
  26684         soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88270_A0r_fields,
  26685         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26686         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26687         -1,
  26688         -1,
  26689     },
  26690 #endif /* chips */
  26691 
  26692 #if defined(BCM_88375_A0)
  26693     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM88375_A0r */
  26694         soc_block_list[56],
  26695         soc_portreg,
  26696         1,
  26697         0,
  26698         0x61300,
  26699         SOC_REG_FLAG_64_BITS,
  26700         0,
  26701         3,
  26702         soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88375_A0r_fields,
  26703         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26704         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26705         -1,
  26706         -1,
  26707     },
  26708 #endif /* chips */
  26709 
  26710 #if defined(BCM_88375_B0)
  26711     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM88375_B0r */
  26712         soc_block_list[56],
  26713         soc_portreg,
  26714         1,
  26715         0,
  26716         0x61300,
  26717         SOC_REG_FLAG_64_BITS,
  26718         0,
  26719         3,
  26720         soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88375_B0r_fields,
  26721         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26722         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26723         -1,
  26724         -1,
  26725     },
  26726 #endif /* chips */
  26727 
  26728 #if defined(BCM_88470_A0)
  26729     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM88470_A0r */
  26730         soc_block_list[56],
  26731         soc_portreg,
  26732         1,
  26733         0,
  26734         0x61300,
  26735         SOC_REG_FLAG_64_BITS,
  26736         0,
  26737         3,
  26738         soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88470_A0r_fields,
  26739         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26740         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26741         -1,
  26742         -1,
  26743     },
  26744 #endif /* chips */
  26745 
  26746 #if defined(BCM_88470_B0)
  26747     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM88470_B0r */
  26748         soc_block_list[56],
  26749         soc_portreg,
  26750         1,
  26751         0,
  26752         0x61300,
  26753         SOC_REG_FLAG_64_BITS,
  26754         0,
  26755         3,
  26756         soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88470_B0r_fields,
  26757         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26758         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26759         -1,
  26760         -1,
  26761     },
  26762 #endif /* chips */
  26763 
  26764 #if defined(BCM_88675_A0)
  26765     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM88675_A0r */
  26766         soc_block_list[56],
  26767         soc_portreg,
  26768         1,
  26769         0,
  26770         0x61300,
  26771         SOC_REG_FLAG_64_BITS,
  26772         0,
  26773         3,
  26774         soc_XLMAC_TX_LLFC_MSG_FIELDSr_fields,
  26775         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26776         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26777         -1,
  26778         -1,
  26779     },
  26780 #endif /* chips */
  26781 
  26782 #if defined(BCM_88675_B0)
  26783     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM88675_B0r */
  26784         soc_block_list[56],
  26785         soc_portreg,
  26786         1,
  26787         0,
  26788         0x61300,
  26789         SOC_REG_FLAG_64_BITS,
  26790         0,
  26791         3,
  26792         soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88675_B0r_fields,
  26793         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26794         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26795         -1,
  26796         -1,
  26797     },
  26798 #endif /* chips */
  26799 
  26800 #if defined(BCM_88680_A0)
  26801     { /* SOC_REG_INT_XLMAC_TX_LLFC_MSG_FIELDS_BCM88680_A0r */
  26802         soc_block_list[56],
  26803         soc_portreg,
  26804         1,
  26805         0,
  26806         0x61300,
  26807         SOC_REG_FLAG_64_BITS,
  26808         0,
  26809         3,
  26810         soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88680_A0r_fields,
  26811         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  26812         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  26813         -1,
  26814         -1,
  26815     },
  26816 #endif /* chips */
  26817 
  26818 #if defined(BCM_2801PM_A0)
  26819     { /* SOC_REG_INT_XLMAC_TX_MAC_SAr */
  26820         soc_block_list[56],
  26821         soc_portreg,
  26822         1,
  26823         0,
  26824         0x60500,
  26825         SOC_REG_FLAG_64_BITS,
  26826         0,
  26827         1,
  26828         soc_CLMAC_TX_MAC_SAr_fields,
  26829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26830         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  26831         -1,
  26832         -1,
  26833     },
  26834 #endif /* chips */
  26835 
  26836 #if defined(BCM_53400_A0)
  26837     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM53400_A0r */
  26838         soc_block_list[16],
  26839         soc_portreg,
  26840         1,
  26841         0,
  26842         0x60500,
  26843         SOC_REG_FLAG_64_BITS,
  26844         0,
  26845         3,
  26846         soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields,
  26847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26848         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  26849         -1,
  26850         -1,
  26851     },
  26852 #endif /* chips */
  26853 
  26854 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  26855     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM53570_A0r */
  26856         soc_block_list[16],
  26857         soc_portreg,
  26858         1,
  26859         0,
  26860         0x60400,
  26861         SOC_REG_FLAG_64_BITS,
  26862         0,
  26863         3,
  26864         soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields,
  26865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26866         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  26867         -1,
  26868         -1,
  26869     },
  26870 #endif /* chips */
  26871 
  26872 #if defined(BCM_56150_A0)
  26873     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM56150_A0r */
  26874         soc_block_list[16],
  26875         soc_portreg,
  26876         1,
  26877         0,
  26878         0x60500,
  26879         SOC_REG_FLAG_64_BITS,
  26880         0,
  26881         3,
  26882         soc_CMAC_TX_MAC_SAr_fields,
  26883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26884         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  26885         -1,
  26886         -1,
  26887     },
  26888 #endif /* chips */
  26889 
  26890 #if defined(BCM_56160_A0)
  26891     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM56160_A0r */
  26892         soc_block_list[16],
  26893         soc_portreg,
  26894         1,
  26895         0,
  26896         0x60500,
  26897         SOC_REG_FLAG_64_BITS,
  26898         0,
  26899         3,
  26900         soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields,
  26901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26902         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  26903         -1,
  26904         -1,
  26905     },
  26906 #endif /* chips */
  26907 
  26908 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  26909     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM56260_A0r */
  26910         soc_block_list[220],
  26911         soc_portreg,
  26912         1,
  26913         0,
  26914         0x60500,
  26915         SOC_REG_FLAG_64_BITS,
  26916         0,
  26917         3,
  26918         soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields,
  26919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26920         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  26921         -1,
  26922         -1,
  26923     },
  26924 #endif /* chips */
  26925 
  26926 #if defined(BCM_56270_A0)
  26927     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM56270_A0r */
  26928         soc_block_list[220],
  26929         soc_portreg,
  26930         1,
  26931         0,
  26932         0x60500,
  26933         SOC_REG_FLAG_64_BITS,
  26934         0,
  26935         3,
  26936         soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields,
  26937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26938         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  26939         -1,
  26940         -1,
  26941     },
  26942 #endif /* chips */
  26943 
  26944 #if defined(BCM_56370_A0)
  26945     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM56370_A0r */
  26946         soc_block_list[16],
  26947         soc_portreg,
  26948         1,
  26949         0,
  26950         0x60500,
  26951         SOC_REG_FLAG_64_BITS,
  26952         0,
  26953         3,
  26954         soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields,
  26955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26956         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  26957         -1,
  26958         -1,
  26959         3,
  26960     },
  26961 #endif /* chips */
  26962 
  26963 #if defined(BCM_56560_A0)
  26964     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM56560_A0r */
  26965         soc_block_list[16],
  26966         soc_portreg,
  26967         1,
  26968         0,
  26969         0x60500,
  26970         SOC_REG_FLAG_64_BITS,
  26971         0,
  26972         3,
  26973         soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields,
  26974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26975         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  26976         -1,
  26977         -1,
  26978     },
  26979 #endif /* chips */
  26980 
  26981 #if defined(BCM_56560_B0)
  26982     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM56560_B0r */
  26983         soc_block_list[16],
  26984         soc_portreg,
  26985         1,
  26986         0,
  26987         0x60500,
  26988         SOC_REG_FLAG_64_BITS,
  26989         0,
  26990         3,
  26991         soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields,
  26992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26993         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  26994         -1,
  26995         -1,
  26996     },
  26997 #endif /* chips */
  26998 
  26999 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  27000     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM56670_A0r */
  27001         soc_block_list[16],
  27002         soc_portreg,
  27003         1,
  27004         0,
  27005         0x60400,
  27006         SOC_REG_FLAG_64_BITS,
  27007         0,
  27008         3,
  27009         soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields,
  27010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27011         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27012         -1,
  27013         -1,
  27014     },
  27015 #endif /* chips */
  27016 
  27017 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  27018     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM56850_A0r */
  27019         soc_block_list[16],
  27020         soc_portreg,
  27021         1,
  27022         0,
  27023         0x60500,
  27024         SOC_REG_FLAG_64_BITS,
  27025         0,
  27026         3,
  27027         soc_CMAC_TX_MAC_SAr_fields,
  27028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27029         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27030         -1,
  27031         -1,
  27032     },
  27033 #endif /* chips */
  27034 
  27035 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  27036     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  27037     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  27038     defined(BCM_56980_B0)
  27039     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM56960_A0r */
  27040         soc_block_list[16],
  27041         soc_portreg,
  27042         1,
  27043         0,
  27044         0x60500,
  27045         SOC_REG_FLAG_64_BITS,
  27046         0,
  27047         3,
  27048         soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields,
  27049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27050         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27051         -1,
  27052         -1,
  27053         3,
  27054     },
  27055 #endif /* chips */
  27056 
  27057 #if defined(BCM_88270_A0)
  27058     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM88270_A0r */
  27059         soc_block_list[221],
  27060         soc_portreg,
  27061         1,
  27062         0,
  27063         0x60500,
  27064         SOC_REG_FLAG_64_BITS,
  27065         0,
  27066         1,
  27067         soc_XLMAC_TX_MAC_SA_BCM88270_A0r_fields,
  27068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27069         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27070         -1,
  27071         -1,
  27072     },
  27073 #endif /* chips */
  27074 
  27075 #if defined(BCM_88375_A0)
  27076     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM88375_A0r */
  27077         soc_block_list[56],
  27078         soc_portreg,
  27079         1,
  27080         0,
  27081         0x60500,
  27082         SOC_REG_FLAG_64_BITS,
  27083         0,
  27084         1,
  27085         soc_XLMAC_TX_MAC_SA_BCM88375_A0r_fields,
  27086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27087         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27088         -1,
  27089         -1,
  27090     },
  27091 #endif /* chips */
  27092 
  27093 #if defined(BCM_88375_B0)
  27094     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM88375_B0r */
  27095         soc_block_list[56],
  27096         soc_portreg,
  27097         1,
  27098         0,
  27099         0x60500,
  27100         SOC_REG_FLAG_64_BITS,
  27101         0,
  27102         1,
  27103         soc_XLMAC_TX_MAC_SA_BCM88375_B0r_fields,
  27104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27105         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27106         -1,
  27107         -1,
  27108     },
  27109 #endif /* chips */
  27110 
  27111 #if defined(BCM_88470_A0)
  27112     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM88470_A0r */
  27113         soc_block_list[56],
  27114         soc_portreg,
  27115         1,
  27116         0,
  27117         0x60500,
  27118         SOC_REG_FLAG_64_BITS,
  27119         0,
  27120         1,
  27121         soc_XLMAC_TX_MAC_SA_BCM88470_A0r_fields,
  27122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27123         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27124         -1,
  27125         -1,
  27126     },
  27127 #endif /* chips */
  27128 
  27129 #if defined(BCM_88470_B0)
  27130     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM88470_B0r */
  27131         soc_block_list[56],
  27132         soc_portreg,
  27133         1,
  27134         0,
  27135         0x60500,
  27136         SOC_REG_FLAG_64_BITS,
  27137         0,
  27138         1,
  27139         soc_XLMAC_TX_MAC_SA_BCM88470_B0r_fields,
  27140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27141         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27142         -1,
  27143         -1,
  27144     },
  27145 #endif /* chips */
  27146 
  27147 #if defined(BCM_88675_A0)
  27148     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM88675_A0r */
  27149         soc_block_list[56],
  27150         soc_portreg,
  27151         1,
  27152         0,
  27153         0x60500,
  27154         SOC_REG_FLAG_64_BITS,
  27155         0,
  27156         1,
  27157         soc_XLMAC_TX_MAC_SAr_fields,
  27158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27159         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27160         -1,
  27161         -1,
  27162     },
  27163 #endif /* chips */
  27164 
  27165 #if defined(BCM_88675_B0)
  27166     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM88675_B0r */
  27167         soc_block_list[56],
  27168         soc_portreg,
  27169         1,
  27170         0,
  27171         0x60500,
  27172         SOC_REG_FLAG_64_BITS,
  27173         0,
  27174         1,
  27175         soc_XLMAC_TX_MAC_SA_BCM88675_B0r_fields,
  27176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27177         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27178         -1,
  27179         -1,
  27180     },
  27181 #endif /* chips */
  27182 
  27183 #if defined(BCM_88680_A0)
  27184     { /* SOC_REG_INT_XLMAC_TX_MAC_SA_BCM88680_A0r */
  27185         soc_block_list[56],
  27186         soc_portreg,
  27187         1,
  27188         0,
  27189         0x60500,
  27190         SOC_REG_FLAG_64_BITS,
  27191         0,
  27192         1,
  27193         soc_XLMAC_TX_MAC_SA_BCM88680_A0r_fields,
  27194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27195         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27196         -1,
  27197         -1,
  27198     },
  27199 #endif /* chips */
  27200 
  27201 #if defined(BCM_2801PM_A0)
  27202     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATAr */
  27203         soc_block_list[56],
  27204         soc_portreg,
  27205         1,
  27206         0,
  27207         0x61500,
  27208         SOC_REG_FLAG_64_BITS |
  27209                           SOC_REG_FLAG_RO,
  27210         0,
  27211         3,
  27212         soc_CLMAC_TX_TIMESTAMP_FIFO_DATAr_fields,
  27213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27214         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27215         -1,
  27216         -1,
  27217     },
  27218 #endif /* chips */
  27219 
  27220 #if defined(BCM_53400_A0)
  27221     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r */
  27222         soc_block_list[16],
  27223         soc_portreg,
  27224         1,
  27225         0,
  27226         0x61500,
  27227         SOC_REG_FLAG_64_BITS |
  27228                           SOC_REG_FLAG_RO,
  27229         0,
  27230         3,
  27231         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields,
  27232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27233         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27234         -1,
  27235         -1,
  27236     },
  27237 #endif /* chips */
  27238 
  27239 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27240     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53570_A0r */
  27241         soc_block_list[16],
  27242         soc_portreg,
  27243         1,
  27244         0,
  27245         0x61400,
  27246         SOC_REG_FLAG_64_BITS |
  27247                           SOC_REG_FLAG_RO,
  27248         0,
  27249         3,
  27250         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields,
  27251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27252         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27253         -1,
  27254         -1,
  27255     },
  27256 #endif /* chips */
  27257 
  27258 #if defined(BCM_56150_A0)
  27259     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM56150_A0r */
  27260         soc_block_list[16],
  27261         soc_portreg,
  27262         1,
  27263         0,
  27264         0x61500,
  27265         SOC_REG_FLAG_64_BITS |
  27266                           SOC_REG_FLAG_RO,
  27267         0,
  27268         3,
  27269         soc_CMAC_TX_TIMESTAMP_FIFO_DATAr_fields,
  27270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27271         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27272         -1,
  27273         -1,
  27274     },
  27275 #endif /* chips */
  27276 
  27277 #if defined(BCM_56160_A0)
  27278     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM56160_A0r */
  27279         soc_block_list[16],
  27280         soc_portreg,
  27281         1,
  27282         0,
  27283         0x61500,
  27284         SOC_REG_FLAG_64_BITS |
  27285                           SOC_REG_FLAG_RO,
  27286         0,
  27287         3,
  27288         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields,
  27289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27290         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27291         -1,
  27292         -1,
  27293     },
  27294 #endif /* chips */
  27295 
  27296 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  27297     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM56260_A0r */
  27298         soc_block_list[220],
  27299         soc_portreg,
  27300         1,
  27301         0,
  27302         0x61500,
  27303         SOC_REG_FLAG_64_BITS |
  27304                           SOC_REG_FLAG_RO,
  27305         0,
  27306         3,
  27307         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields,
  27308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27309         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27310         -1,
  27311         -1,
  27312     },
  27313 #endif /* chips */
  27314 
  27315 #if defined(BCM_56270_A0)
  27316     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM56270_A0r */
  27317         soc_block_list[220],
  27318         soc_portreg,
  27319         1,
  27320         0,
  27321         0x61500,
  27322         SOC_REG_FLAG_64_BITS |
  27323                           SOC_REG_FLAG_RO,
  27324         0,
  27325         3,
  27326         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields,
  27327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27328         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27329         -1,
  27330         -1,
  27331     },
  27332 #endif /* chips */
  27333 
  27334 #if defined(BCM_56370_A0)
  27335     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM56370_A0r */
  27336         soc_block_list[16],
  27337         soc_portreg,
  27338         1,
  27339         0,
  27340         0x61500,
  27341         SOC_REG_FLAG_64_BITS |
  27342                           SOC_REG_FLAG_RO,
  27343         0,
  27344         3,
  27345         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields,
  27346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27347         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27348         -1,
  27349         -1,
  27350         3,
  27351     },
  27352 #endif /* chips */
  27353 
  27354 #if defined(BCM_56560_A0)
  27355     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM56560_A0r */
  27356         soc_block_list[16],
  27357         soc_portreg,
  27358         1,
  27359         0,
  27360         0x61500,
  27361         SOC_REG_FLAG_64_BITS |
  27362                           SOC_REG_FLAG_RO,
  27363         0,
  27364         3,
  27365         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields,
  27366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27367         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27368         -1,
  27369         -1,
  27370     },
  27371 #endif /* chips */
  27372 
  27373 #if defined(BCM_56560_B0)
  27374     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM56560_B0r */
  27375         soc_block_list[16],
  27376         soc_portreg,
  27377         1,
  27378         0,
  27379         0x61500,
  27380         SOC_REG_FLAG_64_BITS |
  27381                           SOC_REG_FLAG_RO,
  27382         0,
  27383         3,
  27384         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields,
  27385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27386         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27387         -1,
  27388         -1,
  27389     },
  27390 #endif /* chips */
  27391 
  27392 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  27393     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM56670_A0r */
  27394         soc_block_list[16],
  27395         soc_portreg,
  27396         1,
  27397         0,
  27398         0x61400,
  27399         SOC_REG_FLAG_64_BITS |
  27400                           SOC_REG_FLAG_RO,
  27401         0,
  27402         3,
  27403         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields,
  27404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27405         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27406         -1,
  27407         -1,
  27408     },
  27409 #endif /* chips */
  27410 
  27411 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  27412     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM56850_A0r */
  27413         soc_block_list[16],
  27414         soc_portreg,
  27415         1,
  27416         0,
  27417         0x61500,
  27418         SOC_REG_FLAG_64_BITS |
  27419                           SOC_REG_FLAG_RO,
  27420         0,
  27421         3,
  27422         soc_CMAC_TX_TIMESTAMP_FIFO_DATAr_fields,
  27423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27424         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27425         -1,
  27426         -1,
  27427     },
  27428 #endif /* chips */
  27429 
  27430 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  27431     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  27432     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  27433     defined(BCM_56980_B0)
  27434     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM56960_A0r */
  27435         soc_block_list[16],
  27436         soc_portreg,
  27437         1,
  27438         0,
  27439         0x61500,
  27440         SOC_REG_FLAG_64_BITS |
  27441                           SOC_REG_FLAG_RO,
  27442         0,
  27443         3,
  27444         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields,
  27445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27446         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27447         -1,
  27448         -1,
  27449         3,
  27450     },
  27451 #endif /* chips */
  27452 
  27453 #if defined(BCM_88270_A0)
  27454     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88270_A0r */
  27455         soc_block_list[221],
  27456         soc_portreg,
  27457         1,
  27458         0,
  27459         0x61500,
  27460         SOC_REG_FLAG_64_BITS |
  27461                           SOC_REG_FLAG_RO,
  27462         0,
  27463         3,
  27464         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88270_A0r_fields,
  27465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27466         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27467         -1,
  27468         -1,
  27469     },
  27470 #endif /* chips */
  27471 
  27472 #if defined(BCM_88375_A0)
  27473     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88375_A0r */
  27474         soc_block_list[56],
  27475         soc_portreg,
  27476         1,
  27477         0,
  27478         0x61500,
  27479         SOC_REG_FLAG_64_BITS |
  27480                           SOC_REG_FLAG_RO,
  27481         0,
  27482         3,
  27483         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88375_A0r_fields,
  27484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27485         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27486         -1,
  27487         -1,
  27488     },
  27489 #endif /* chips */
  27490 
  27491 #if defined(BCM_88375_B0)
  27492     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88375_B0r */
  27493         soc_block_list[56],
  27494         soc_portreg,
  27495         1,
  27496         0,
  27497         0x61500,
  27498         SOC_REG_FLAG_64_BITS |
  27499                           SOC_REG_FLAG_RO,
  27500         0,
  27501         3,
  27502         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88375_B0r_fields,
  27503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27504         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27505         -1,
  27506         -1,
  27507     },
  27508 #endif /* chips */
  27509 
  27510 #if defined(BCM_88470_A0)
  27511     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88470_A0r */
  27512         soc_block_list[56],
  27513         soc_portreg,
  27514         1,
  27515         0,
  27516         0x61500,
  27517         SOC_REG_FLAG_64_BITS |
  27518                           SOC_REG_FLAG_RO,
  27519         0,
  27520         3,
  27521         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88470_A0r_fields,
  27522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27523         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27524         -1,
  27525         -1,
  27526     },
  27527 #endif /* chips */
  27528 
  27529 #if defined(BCM_88470_B0)
  27530     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88470_B0r */
  27531         soc_block_list[56],
  27532         soc_portreg,
  27533         1,
  27534         0,
  27535         0x61500,
  27536         SOC_REG_FLAG_64_BITS |
  27537                           SOC_REG_FLAG_RO,
  27538         0,
  27539         3,
  27540         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88470_B0r_fields,
  27541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27542         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27543         -1,
  27544         -1,
  27545     },
  27546 #endif /* chips */
  27547 
  27548 #if defined(BCM_88675_A0)
  27549     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88675_A0r */
  27550         soc_block_list[56],
  27551         soc_portreg,
  27552         1,
  27553         0,
  27554         0x61500,
  27555         SOC_REG_FLAG_64_BITS |
  27556                           SOC_REG_FLAG_RO,
  27557         0,
  27558         3,
  27559         soc_XLMAC_TX_TIMESTAMP_FIFO_DATAr_fields,
  27560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27561         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27562         -1,
  27563         -1,
  27564     },
  27565 #endif /* chips */
  27566 
  27567 #if defined(BCM_88675_B0)
  27568     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88675_B0r */
  27569         soc_block_list[56],
  27570         soc_portreg,
  27571         1,
  27572         0,
  27573         0x61500,
  27574         SOC_REG_FLAG_64_BITS |
  27575                           SOC_REG_FLAG_RO,
  27576         0,
  27577         3,
  27578         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88675_B0r_fields,
  27579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27580         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27581         -1,
  27582         -1,
  27583     },
  27584 #endif /* chips */
  27585 
  27586 #if defined(BCM_88680_A0)
  27587     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88680_A0r */
  27588         soc_block_list[56],
  27589         soc_portreg,
  27590         1,
  27591         0,
  27592         0x61500,
  27593         SOC_REG_FLAG_64_BITS |
  27594                           SOC_REG_FLAG_RO,
  27595         0,
  27596         3,
  27597         soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88680_A0r_fields,
  27598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27599         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  27600         -1,
  27601         -1,
  27602     },
  27603 #endif /* chips */
  27604 
  27605 #if defined(BCM_2801PM_A0)
  27606     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUSr */
  27607         soc_block_list[56],
  27608         soc_portreg,
  27609         1,
  27610         0,
  27611         0x61600,
  27612         SOC_REG_FLAG_RO,
  27613         0,
  27614         1,
  27615         soc_CLMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  27616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27617         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27618         -1,
  27619         -1,
  27620     },
  27621 #endif /* chips */
  27622 
  27623 #if defined(BCM_53400_A0)
  27624     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r */
  27625         soc_block_list[16],
  27626         soc_portreg,
  27627         1,
  27628         0,
  27629         0x61600,
  27630         SOC_REG_FLAG_64_BITS |
  27631                           SOC_REG_FLAG_RO,
  27632         0,
  27633         1,
  27634         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields,
  27635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27636         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27637         -1,
  27638         -1,
  27639     },
  27640 #endif /* chips */
  27641 
  27642 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  27643     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53570_A0r */
  27644         soc_block_list[16],
  27645         soc_portreg,
  27646         1,
  27647         0,
  27648         0x61500,
  27649         SOC_REG_FLAG_64_BITS |
  27650                           SOC_REG_FLAG_RO,
  27651         0,
  27652         1,
  27653         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields,
  27654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27655         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27656         -1,
  27657         -1,
  27658     },
  27659 #endif /* chips */
  27660 
  27661 #if defined(BCM_56150_A0)
  27662     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56150_A0r */
  27663         soc_block_list[16],
  27664         soc_portreg,
  27665         1,
  27666         0,
  27667         0x61600,
  27668         SOC_REG_FLAG_64_BITS |
  27669                           SOC_REG_FLAG_RO,
  27670         0,
  27671         1,
  27672         soc_CMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  27673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27674         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27675         -1,
  27676         -1,
  27677     },
  27678 #endif /* chips */
  27679 
  27680 #if defined(BCM_56160_A0)
  27681     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56160_A0r */
  27682         soc_block_list[16],
  27683         soc_portreg,
  27684         1,
  27685         0,
  27686         0x61600,
  27687         SOC_REG_FLAG_64_BITS |
  27688                           SOC_REG_FLAG_RO,
  27689         0,
  27690         1,
  27691         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields,
  27692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27693         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27694         -1,
  27695         -1,
  27696     },
  27697 #endif /* chips */
  27698 
  27699 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  27700     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56260_A0r */
  27701         soc_block_list[220],
  27702         soc_portreg,
  27703         1,
  27704         0,
  27705         0x61600,
  27706         SOC_REG_FLAG_64_BITS |
  27707                           SOC_REG_FLAG_RO,
  27708         0,
  27709         1,
  27710         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields,
  27711         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27712         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27713         -1,
  27714         -1,
  27715     },
  27716 #endif /* chips */
  27717 
  27718 #if defined(BCM_56270_A0)
  27719     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56270_A0r */
  27720         soc_block_list[220],
  27721         soc_portreg,
  27722         1,
  27723         0,
  27724         0x61600,
  27725         SOC_REG_FLAG_64_BITS |
  27726                           SOC_REG_FLAG_RO,
  27727         0,
  27728         1,
  27729         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields,
  27730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27731         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27732         -1,
  27733         -1,
  27734     },
  27735 #endif /* chips */
  27736 
  27737 #if defined(BCM_56370_A0)
  27738     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56370_A0r */
  27739         soc_block_list[16],
  27740         soc_portreg,
  27741         1,
  27742         0,
  27743         0x61600,
  27744         SOC_REG_FLAG_64_BITS |
  27745                           SOC_REG_FLAG_RO,
  27746         0,
  27747         1,
  27748         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields,
  27749         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27750         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27751         -1,
  27752         -1,
  27753         3,
  27754     },
  27755 #endif /* chips */
  27756 
  27757 #if defined(BCM_56560_A0)
  27758     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56560_A0r */
  27759         soc_block_list[16],
  27760         soc_portreg,
  27761         1,
  27762         0,
  27763         0x61600,
  27764         SOC_REG_FLAG_64_BITS |
  27765                           SOC_REG_FLAG_RO,
  27766         0,
  27767         1,
  27768         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields,
  27769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27770         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27771         -1,
  27772         -1,
  27773     },
  27774 #endif /* chips */
  27775 
  27776 #if defined(BCM_56560_B0)
  27777     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56560_B0r */
  27778         soc_block_list[16],
  27779         soc_portreg,
  27780         1,
  27781         0,
  27782         0x61600,
  27783         SOC_REG_FLAG_64_BITS |
  27784                           SOC_REG_FLAG_RO,
  27785         0,
  27786         1,
  27787         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields,
  27788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27789         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27790         -1,
  27791         -1,
  27792     },
  27793 #endif /* chips */
  27794 
  27795 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  27796     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56670_A0r */
  27797         soc_block_list[16],
  27798         soc_portreg,
  27799         1,
  27800         0,
  27801         0x61500,
  27802         SOC_REG_FLAG_64_BITS |
  27803                           SOC_REG_FLAG_RO,
  27804         0,
  27805         1,
  27806         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields,
  27807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27808         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27809         -1,
  27810         -1,
  27811     },
  27812 #endif /* chips */
  27813 
  27814 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  27815     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56850_A0r */
  27816         soc_block_list[16],
  27817         soc_portreg,
  27818         1,
  27819         0,
  27820         0x61600,
  27821         SOC_REG_FLAG_64_BITS |
  27822                           SOC_REG_FLAG_RO,
  27823         0,
  27824         1,
  27825         soc_CMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  27826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27827         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27828         -1,
  27829         -1,
  27830     },
  27831 #endif /* chips */
  27832 
  27833 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  27834     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  27835     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  27836     defined(BCM_56980_B0)
  27837     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56960_A0r */
  27838         soc_block_list[16],
  27839         soc_portreg,
  27840         1,
  27841         0,
  27842         0x61600,
  27843         SOC_REG_FLAG_64_BITS |
  27844                           SOC_REG_FLAG_RO,
  27845         0,
  27846         1,
  27847         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields,
  27848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27849         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27850         -1,
  27851         -1,
  27852         3,
  27853     },
  27854 #endif /* chips */
  27855 
  27856 #if defined(BCM_88270_A0)
  27857     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88270_A0r */
  27858         soc_block_list[221],
  27859         soc_portreg,
  27860         1,
  27861         0,
  27862         0x61600,
  27863         SOC_REG_FLAG_64_BITS |
  27864                           SOC_REG_FLAG_RO,
  27865         0,
  27866         1,
  27867         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88270_A0r_fields,
  27868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27869         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27870         -1,
  27871         -1,
  27872     },
  27873 #endif /* chips */
  27874 
  27875 #if defined(BCM_88375_A0)
  27876     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88375_A0r */
  27877         soc_block_list[56],
  27878         soc_portreg,
  27879         1,
  27880         0,
  27881         0x61600,
  27882         SOC_REG_FLAG_64_BITS |
  27883                           SOC_REG_FLAG_RO,
  27884         0,
  27885         1,
  27886         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88375_A0r_fields,
  27887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27888         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27889         -1,
  27890         -1,
  27891     },
  27892 #endif /* chips */
  27893 
  27894 #if defined(BCM_88375_B0)
  27895     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88375_B0r */
  27896         soc_block_list[56],
  27897         soc_portreg,
  27898         1,
  27899         0,
  27900         0x61600,
  27901         SOC_REG_FLAG_64_BITS |
  27902                           SOC_REG_FLAG_RO,
  27903         0,
  27904         1,
  27905         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88375_B0r_fields,
  27906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27907         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27908         -1,
  27909         -1,
  27910     },
  27911 #endif /* chips */
  27912 
  27913 #if defined(BCM_88470_A0)
  27914     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88470_A0r */
  27915         soc_block_list[56],
  27916         soc_portreg,
  27917         1,
  27918         0,
  27919         0x61600,
  27920         SOC_REG_FLAG_64_BITS |
  27921                           SOC_REG_FLAG_RO,
  27922         0,
  27923         1,
  27924         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88470_A0r_fields,
  27925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27926         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27927         -1,
  27928         -1,
  27929     },
  27930 #endif /* chips */
  27931 
  27932 #if defined(BCM_88470_B0)
  27933     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88470_B0r */
  27934         soc_block_list[56],
  27935         soc_portreg,
  27936         1,
  27937         0,
  27938         0x61600,
  27939         SOC_REG_FLAG_64_BITS |
  27940                           SOC_REG_FLAG_RO,
  27941         0,
  27942         1,
  27943         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88470_B0r_fields,
  27944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27945         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27946         -1,
  27947         -1,
  27948     },
  27949 #endif /* chips */
  27950 
  27951 #if defined(BCM_88675_A0)
  27952     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88675_A0r */
  27953         soc_block_list[56],
  27954         soc_portreg,
  27955         1,
  27956         0,
  27957         0x61600,
  27958         SOC_REG_FLAG_64_BITS |
  27959                           SOC_REG_FLAG_RO,
  27960         0,
  27961         1,
  27962         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  27963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27964         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27965         -1,
  27966         -1,
  27967     },
  27968 #endif /* chips */
  27969 
  27970 #if defined(BCM_88675_B0)
  27971     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88675_B0r */
  27972         soc_block_list[56],
  27973         soc_portreg,
  27974         1,
  27975         0,
  27976         0x61600,
  27977         SOC_REG_FLAG_64_BITS |
  27978                           SOC_REG_FLAG_RO,
  27979         0,
  27980         1,
  27981         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88675_B0r_fields,
  27982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27983         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  27984         -1,
  27985         -1,
  27986     },
  27987 #endif /* chips */
  27988 
  27989 #if defined(BCM_88680_A0)
  27990     { /* SOC_REG_INT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88680_A0r */
  27991         soc_block_list[56],
  27992         soc_portreg,
  27993         1,
  27994         0,
  27995         0x61600,
  27996         SOC_REG_FLAG_64_BITS |
  27997                           SOC_REG_FLAG_RO,
  27998         0,
  27999         1,
  28000         soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88680_A0r_fields,
  28001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28002         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  28003         -1,
  28004         -1,
  28005     },
  28006 #endif /* chips */
  28007 
  28008 #if defined(BCM_2801PM_A0)
  28009     { /* SOC_REG_INT_XLMAC_VERSION_IDr */
  28010         soc_block_list[56],
  28011         soc_portreg,
  28012         1,
  28013         0,
  28014         0x63400,
  28015         SOC_REG_FLAG_RO,
  28016         0,
  28017         1,
  28018         soc_XLMAC_VERSION_IDr_fields,
  28019         SOC_RESET_VAL_DEC(0x0000a035, 0x00000000)
  28020         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28021         -1,
  28022         -1,
  28023     },
  28024 #endif /* chips */
  28025 
  28026 #if defined(BCM_53400_A0)
  28027     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM53400_A0r */
  28028         soc_block_list[16],
  28029         soc_portreg,
  28030         1,
  28031         0,
  28032         0x63400,
  28033         SOC_REG_FLAG_64_BITS |
  28034                           SOC_REG_FLAG_RO,
  28035         0,
  28036         1,
  28037         soc_XLMAC_VERSION_ID_BCM53400_A0r_fields,
  28038         SOC_RESET_VAL_DEC(0x0000a035, 0x00000000)
  28039         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28040         -1,
  28041         -1,
  28042     },
  28043 #endif /* chips */
  28044 
  28045 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  28046     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM53570_A0r */
  28047         soc_block_list[16],
  28048         soc_portreg,
  28049         1,
  28050         0,
  28051         0x60000,
  28052         SOC_REG_FLAG_64_BITS |
  28053                           SOC_REG_FLAG_RO,
  28054         0,
  28055         1,
  28056         soc_XLMAC_VERSION_ID_BCM53570_A0r_fields,
  28057         SOC_RESET_VAL_DEC(0x0000a044, 0x00000000)
  28058         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28059         -1,
  28060         -1,
  28061     },
  28062 #endif /* chips */
  28063 
  28064 #if defined(BCM_56150_A0)
  28065     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56150_A0r */
  28066         soc_block_list[16],
  28067         soc_portreg,
  28068         1,
  28069         0,
  28070         0x62d00,
  28071         SOC_REG_FLAG_64_BITS |
  28072                           SOC_REG_FLAG_RO,
  28073         0,
  28074         1,
  28075         soc_XLMAC_VERSION_ID_BCM56150_A0r_fields,
  28076         SOC_RESET_VAL_DEC(0x0000a022, 0x00000000)
  28077         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28078         -1,
  28079         -1,
  28080     },
  28081 #endif /* chips */
  28082 
  28083 #if defined(BCM_56160_A0)
  28084     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56160_A0r */
  28085         soc_block_list[16],
  28086         soc_portreg,
  28087         1,
  28088         0,
  28089         0x63500,
  28090         SOC_REG_FLAG_64_BITS |
  28091                           SOC_REG_FLAG_RO,
  28092         0,
  28093         1,
  28094         soc_XLMAC_B0_VERSION_IDr_fields,
  28095         SOC_RESET_VAL_DEC(0x0000a037, 0x00000000)
  28096         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28097         -1,
  28098         -1,
  28099     },
  28100 #endif /* chips */
  28101 
  28102 #if defined(BCM_56260_A0)
  28103     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56260_A0r */
  28104         soc_block_list[220],
  28105         soc_portreg,
  28106         1,
  28107         0,
  28108         0x63400,
  28109         SOC_REG_FLAG_64_BITS |
  28110                           SOC_REG_FLAG_RO,
  28111         0,
  28112         1,
  28113         soc_XLMAC_VERSION_ID_BCM53400_A0r_fields,
  28114         SOC_RESET_VAL_DEC(0x0000a035, 0x00000000)
  28115         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28116         -1,
  28117         -1,
  28118     },
  28119 #endif /* chips */
  28120 
  28121 #if defined(BCM_56260_B0)
  28122     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56260_B0r */
  28123         soc_block_list[220],
  28124         soc_portreg,
  28125         1,
  28126         0,
  28127         0x63500,
  28128         SOC_REG_FLAG_64_BITS |
  28129                           SOC_REG_FLAG_RO,
  28130         0,
  28131         1,
  28132         soc_XLMAC_B0_VERSION_IDr_fields,
  28133         SOC_RESET_VAL_DEC(0x0000a037, 0x00000000)
  28134         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28135         -1,
  28136         -1,
  28137     },
  28138 #endif /* chips */
  28139 
  28140 #if defined(BCM_56270_A0)
  28141     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56270_A0r */
  28142         soc_block_list[220],
  28143         soc_portreg,
  28144         1,
  28145         0,
  28146         0x63500,
  28147         SOC_REG_FLAG_64_BITS |
  28148                           SOC_REG_FLAG_RO,
  28149         0,
  28150         1,
  28151         soc_XLMAC_B0_VERSION_IDr_fields,
  28152         SOC_RESET_VAL_DEC(0x0000a037, 0x00000000)
  28153         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28154         -1,
  28155         -1,
  28156     },
  28157 #endif /* chips */
  28158 
  28159 #if defined(BCM_56370_A0)
  28160     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56370_A0r */
  28161         soc_block_list[16],
  28162         soc_portreg,
  28163         1,
  28164         0,
  28165         0x63700,
  28166         SOC_REG_FLAG_64_BITS |
  28167                           SOC_REG_FLAG_RO,
  28168         0,
  28169         1,
  28170         soc_XLMAC_VERSION_ID_BCM56970_A0r_fields,
  28171         SOC_RESET_VAL_DEC(0x0000a041, 0x00000000)
  28172         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28173         -1,
  28174         -1,
  28175         3,
  28176     },
  28177 #endif /* chips */
  28178 
  28179 #if defined(BCM_56560_A0)
  28180     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56560_A0r */
  28181         soc_block_list[16],
  28182         soc_portreg,
  28183         1,
  28184         0,
  28185         0x63400,
  28186         SOC_REG_FLAG_64_BITS |
  28187                           SOC_REG_FLAG_RO,
  28188         0,
  28189         1,
  28190         soc_XLMAC_VERSION_ID_BCM53400_A0r_fields,
  28191         SOC_RESET_VAL_DEC(0x0000a035, 0x00000000)
  28192         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28193         -1,
  28194         -1,
  28195     },
  28196 #endif /* chips */
  28197 
  28198 #if defined(BCM_56560_B0)
  28199     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56560_B0r */
  28200         soc_block_list[16],
  28201         soc_portreg,
  28202         1,
  28203         0,
  28204         0x63500,
  28205         SOC_REG_FLAG_64_BITS |
  28206                           SOC_REG_FLAG_RO,
  28207         0,
  28208         1,
  28209         soc_XLMAC_B0_VERSION_IDr_fields,
  28210         SOC_RESET_VAL_DEC(0x0000a037, 0x00000000)
  28211         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28212         -1,
  28213         -1,
  28214     },
  28215 #endif /* chips */
  28216 
  28217 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  28218     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56670_A0r */
  28219         soc_block_list[16],
  28220         soc_portreg,
  28221         1,
  28222         0,
  28223         0x60000,
  28224         SOC_REG_FLAG_64_BITS |
  28225                           SOC_REG_FLAG_RO,
  28226         0,
  28227         1,
  28228         soc_XLMAC_VERSION_ID_BCM53570_A0r_fields,
  28229         SOC_RESET_VAL_DEC(0x0000a044, 0x00000000)
  28230         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28231         -1,
  28232         -1,
  28233     },
  28234 #endif /* chips */
  28235 
  28236 #if defined(BCM_56850_A0)
  28237     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56850_A0r */
  28238         soc_block_list[16],
  28239         soc_portreg,
  28240         1,
  28241         0,
  28242         0x62900,
  28243         SOC_REG_FLAG_64_BITS |
  28244                           SOC_REG_FLAG_RO,
  28245         0,
  28246         1,
  28247         soc_XLMAC_VERSION_ID_BCM56850_A0r_fields,
  28248         SOC_RESET_VAL_DEC(0x0000a019, 0x00000000)
  28249         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28250         -1,
  28251         -1,
  28252     },
  28253 #endif /* chips */
  28254 
  28255 #if defined(BCM_56860_A0)
  28256     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56860_A0r */
  28257         soc_block_list[16],
  28258         soc_portreg,
  28259         1,
  28260         0,
  28261         0x63500,
  28262         SOC_REG_FLAG_64_BITS |
  28263                           SOC_REG_FLAG_RO,
  28264         0,
  28265         1,
  28266         soc_XLMAC_VERSION_ID_BCM56860_A0r_fields,
  28267         SOC_RESET_VAL_DEC(0x0000a036, 0x00000000)
  28268         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28269         -1,
  28270         -1,
  28271     },
  28272 #endif /* chips */
  28273 
  28274 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  28275     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56960_A0r */
  28276         soc_block_list[16],
  28277         soc_portreg,
  28278         1,
  28279         0,
  28280         0x63400,
  28281         SOC_REG_FLAG_64_BITS |
  28282                           SOC_REG_FLAG_RO,
  28283         0,
  28284         1,
  28285         soc_XLMAC_VERSION_ID_BCM53400_A0r_fields,
  28286         SOC_RESET_VAL_DEC(0x0000a035, 0x00000000)
  28287         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28288         -1,
  28289         -1,
  28290         3,
  28291     },
  28292 #endif /* chips */
  28293 
  28294 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  28295     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  28296     defined(BCM_56980_B0)
  28297     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM56970_A0r */
  28298         soc_block_list[16],
  28299         soc_portreg,
  28300         1,
  28301         0,
  28302         0x63700,
  28303         SOC_REG_FLAG_64_BITS |
  28304                           SOC_REG_FLAG_RO,
  28305         0,
  28306         1,
  28307         soc_XLMAC_VERSION_ID_BCM56970_A0r_fields,
  28308         SOC_RESET_VAL_DEC(0x0000a041, 0x00000000)
  28309         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28310         -1,
  28311         -1,
  28312         3,
  28313     },
  28314 #endif /* chips */
  28315 
  28316 #if defined(BCM_88270_A0)
  28317     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM88270_A0r */
  28318         soc_block_list[221],
  28319         soc_portreg,
  28320         1,
  28321         0,
  28322         0x63500,
  28323         SOC_REG_FLAG_64_BITS |
  28324                           SOC_REG_FLAG_RO,
  28325         0,
  28326         1,
  28327         soc_XLMAC_VERSION_ID_BCM88270_A0r_fields,
  28328         SOC_RESET_VAL_DEC(0x0000a037, 0x00000000)
  28329         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28330         -1,
  28331         -1,
  28332     },
  28333 #endif /* chips */
  28334 
  28335 #if defined(BCM_88375_A0)
  28336     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM88375_A0r */
  28337         soc_block_list[56],
  28338         soc_portreg,
  28339         1,
  28340         0,
  28341         0x63400,
  28342         SOC_REG_FLAG_64_BITS |
  28343                           SOC_REG_FLAG_RO,
  28344         0,
  28345         1,
  28346         soc_XLMAC_VERSION_ID_BCM88375_A0r_fields,
  28347         SOC_RESET_VAL_DEC(0x0000a035, 0x00000000)
  28348         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28349         -1,
  28350         -1,
  28351     },
  28352 #endif /* chips */
  28353 
  28354 #if defined(BCM_88375_B0)
  28355     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM88375_B0r */
  28356         soc_block_list[56],
  28357         soc_portreg,
  28358         1,
  28359         0,
  28360         0x63500,
  28361         SOC_REG_FLAG_64_BITS |
  28362                           SOC_REG_FLAG_RO,
  28363         0,
  28364         1,
  28365         soc_XLMAC_VERSION_ID_BCM88375_B0r_fields,
  28366         SOC_RESET_VAL_DEC(0x0000a037, 0x00000000)
  28367         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28368         -1,
  28369         -1,
  28370     },
  28371 #endif /* chips */
  28372 
  28373 #if defined(BCM_88470_A0)
  28374     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM88470_A0r */
  28375         soc_block_list[56],
  28376         soc_portreg,
  28377         1,
  28378         0,
  28379         0x63400,
  28380         SOC_REG_FLAG_64_BITS |
  28381                           SOC_REG_FLAG_RO,
  28382         0,
  28383         1,
  28384         soc_XLMAC_VERSION_ID_BCM88470_A0r_fields,
  28385         SOC_RESET_VAL_DEC(0x0000a035, 0x00000000)
  28386         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28387         -1,
  28388         -1,
  28389     },
  28390 #endif /* chips */
  28391 
  28392 #if defined(BCM_88470_B0)
  28393     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM88470_B0r */
  28394         soc_block_list[56],
  28395         soc_portreg,
  28396         1,
  28397         0,
  28398         0x63500,
  28399         SOC_REG_FLAG_64_BITS |
  28400                           SOC_REG_FLAG_RO,
  28401         0,
  28402         1,
  28403         soc_XLMAC_VERSION_ID_BCM88470_B0r_fields,
  28404         SOC_RESET_VAL_DEC(0x0000a037, 0x00000000)
  28405         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28406         -1,
  28407         -1,
  28408     },
  28409 #endif /* chips */
  28410 
  28411 #if defined(BCM_88675_A0)
  28412     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM88675_A0r */
  28413         soc_block_list[56],
  28414         soc_portreg,
  28415         1,
  28416         0,
  28417         0x63400,
  28418         SOC_REG_FLAG_64_BITS |
  28419                           SOC_REG_FLAG_RO,
  28420         0,
  28421         1,
  28422         soc_XLMAC_VERSION_ID_BCM88675_A0r_fields,
  28423         SOC_RESET_VAL_DEC(0x0000a035, 0x00000000)
  28424         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28425         -1,
  28426         -1,
  28427     },
  28428 #endif /* chips */
  28429 
  28430 #if defined(BCM_88675_B0)
  28431     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM88675_B0r */
  28432         soc_block_list[56],
  28433         soc_portreg,
  28434         1,
  28435         0,
  28436         0x63500,
  28437         SOC_REG_FLAG_64_BITS |
  28438                           SOC_REG_FLAG_RO,
  28439         0,
  28440         1,
  28441         soc_XLMAC_VERSION_ID_BCM88675_B0r_fields,
  28442         SOC_RESET_VAL_DEC(0x0000a037, 0x00000000)
  28443         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28444         -1,
  28445         -1,
  28446     },
  28447 #endif /* chips */
  28448 
  28449 #if defined(BCM_88680_A0)
  28450     { /* SOC_REG_INT_XLMAC_VERSION_ID_BCM88680_A0r */
  28451         soc_block_list[56],
  28452         soc_portreg,
  28453         1,
  28454         0,
  28455         0x63500,
  28456         SOC_REG_FLAG_64_BITS |
  28457                           SOC_REG_FLAG_RO,
  28458         0,
  28459         1,
  28460         soc_XLMAC_VERSION_ID_BCM88680_A0r_fields,
  28461         SOC_RESET_VAL_DEC(0x0000a037, 0x00000000)
  28462         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  28463         -1,
  28464         -1,
  28465     },
  28466 #endif /* chips */
  28467 
  28468 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  28469     { /* SOC_REG_INT_XLMIB_R64r */
  28470         soc_block_list[16],
  28471         soc_portreg,
  28472         1,
  28473         0,
  28474         0,
  28475         SOC_REG_FLAG_64_BITS |
  28476                           SOC_REG_FLAG_COUNTER,
  28477         0,
  28478         1,
  28479         soc_R1023_BCM53400_A0r_fields,
  28480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28481         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28482         59,
  28483         -1,
  28484         3,
  28485     },
  28486 #endif /* chips */
  28487 
  28488 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  28489     { /* SOC_REG_INT_XLMIB_R127r */
  28490         soc_block_list[16],
  28491         soc_portreg,
  28492         1,
  28493         0,
  28494         0x100,
  28495         SOC_REG_FLAG_64_BITS |
  28496                           SOC_REG_FLAG_COUNTER,
  28497         0,
  28498         1,
  28499         soc_R1023_BCM53400_A0r_fields,
  28500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28501         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28502         60,
  28503         -1,
  28504         3,
  28505     },
  28506 #endif /* chips */
  28507 
  28508 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  28509     { /* SOC_REG_INT_XLMIB_R255r */
  28510         soc_block_list[16],
  28511         soc_portreg,
  28512         1,
  28513         0,
  28514         0x200,
  28515         SOC_REG_FLAG_64_BITS |
  28516                           SOC_REG_FLAG_COUNTER,
  28517         0,
  28518         1,
  28519         soc_R1023_BCM53400_A0r_fields,
  28520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28521         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28522         61,
  28523         -1,
  28524         3,
  28525     },
  28526 #endif /* chips */
  28527 
  28528 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  28529     { /* SOC_REG_INT_XLMIB_R511r */
  28530         soc_block_list[16],
  28531         soc_portreg,
  28532         1,
  28533         0,
  28534         0x300,
  28535         SOC_REG_FLAG_64_BITS |
  28536                           SOC_REG_FLAG_COUNTER,
  28537         0,
  28538         1,
  28539         soc_R1023_BCM53400_A0r_fields,
  28540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28541         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28542         62,
  28543         -1,
  28544         3,
  28545     },
  28546 #endif /* chips */
  28547 
  28548 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  28549     { /* SOC_REG_INT_XLMIB_R1023r */
  28550         soc_block_list[16],
  28551         soc_portreg,
  28552         1,
  28553         0,
  28554         0x400,
  28555         SOC_REG_FLAG_64_BITS |
  28556                           SOC_REG_FLAG_COUNTER,
  28557         0,
  28558         1,
  28559         soc_R1023_BCM53400_A0r_fields,
  28560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28562         63,
  28563         -1,
  28564         3,
  28565     },
  28566 #endif /* chips */
  28567 
  28568 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  28569     { /* SOC_REG_INT_XLMIB_R1518r */
  28570         soc_block_list[16],
  28571         soc_portreg,
  28572         1,
  28573         0,
  28574         0x500,
  28575         SOC_REG_FLAG_64_BITS |
  28576                           SOC_REG_FLAG_COUNTER,
  28577         0,
  28578         1,
  28579         soc_R1023_BCM53400_A0r_fields,
  28580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28581         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28582         64,
  28583         -1,
  28584         3,
  28585     },
  28586 #endif /* chips */
  28587 
  28588 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  28589     { /* SOC_REG_INT_XLMIB_R2047r */
  28590         soc_block_list[16],
  28591         soc_portreg,
  28592         1,
  28593         0,
  28594         0x700,
  28595         SOC_REG_FLAG_64_BITS |
  28596                           SOC_REG_FLAG_COUNTER,
  28597         0,
  28598         1,
  28599         soc_R1023_BCM53400_A0r_fields,
  28600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28601         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28602         66,
  28603         -1,
  28604         3,
  28605     },
  28606 #endif /* chips */
  28607 
  28608 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  28609     { /* SOC_REG_INT_XLMIB_R4095r */
  28610         soc_block_list[16],
  28611         soc_portreg,
  28612         1,
  28613         0,
  28614         0x800,
  28615         SOC_REG_FLAG_64_BITS |
  28616                           SOC_REG_FLAG_COUNTER,
  28617         0,
  28618         1,
  28619         soc_R1023_BCM53400_A0r_fields,
  28620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28621         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28622         67,
  28623         -1,
  28624         3,
  28625     },
  28626 #endif /* chips */
  28627 
  28628 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  28629     { /* SOC_REG_INT_XLMIB_R9216r */
  28630         soc_block_list[16],
  28631         soc_portreg,
  28632         1,
  28633         0,
  28634         0x900,
  28635         SOC_REG_FLAG_64_BITS |
  28636                           SOC_REG_FLAG_COUNTER,
  28637         0,
  28638         1,
  28639         soc_R1023_BCM53400_A0r_fields,
  28640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28641         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28642         68,
  28643         -1,
  28644         3,
  28645     },
  28646 #endif /* chips */
  28647 
  28648 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  28649     { /* SOC_REG_INT_XLMIB_R16383r */
  28650         soc_block_list[16],
  28651         soc_portreg,
  28652         1,
  28653         0,
  28654         0xa00,
  28655         SOC_REG_FLAG_64_BITS |
  28656                           SOC_REG_FLAG_COUNTER,
  28657         0,
  28658         1,
  28659         soc_R1023_BCM53400_A0r_fields,
  28660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28661         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28662         69,
  28663         -1,
  28664         3,
  28665     },
  28666 #endif /* chips */
  28667 
  28668 #if defined(BCM_53570_A0)
  28669     { /* SOC_REG_INT_XLMIB_R1023_BCM53570_A0r */
  28670         soc_block_list[16],
  28671         soc_portreg,
  28672         1,
  28673         0,
  28674         0x400,
  28675         SOC_REG_FLAG_64_BITS |
  28676                           SOC_REG_FLAG_COUNTER,
  28677         0,
  28678         1,
  28679         soc_R1023_BCM53400_A0r_fields,
  28680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28681         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28682         158,
  28683         -1,
  28684     },
  28685 #endif /* chips */
  28686 
  28687 #if defined(BCM_53570_B0)
  28688     { /* SOC_REG_INT_XLMIB_R1023_BCM53570_B0r */
  28689         soc_block_list[16],
  28690         soc_portreg,
  28691         1,
  28692         0,
  28693         0x400,
  28694         SOC_REG_FLAG_64_BITS |
  28695                           SOC_REG_FLAG_COUNTER,
  28696         0,
  28697         1,
  28698         soc_R1023_BCM53400_A0r_fields,
  28699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28700         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28701         162,
  28702         -1,
  28703     },
  28704 #endif /* chips */
  28705 
  28706 #if defined(BCM_56370_A0)
  28707     { /* SOC_REG_INT_XLMIB_R1023_BCM56370_A0r */
  28708         soc_block_list[16],
  28709         soc_portreg,
  28710         1,
  28711         0,
  28712         0x400,
  28713         SOC_REG_FLAG_64_BITS |
  28714                           SOC_REG_FLAG_COUNTER,
  28715         0,
  28716         1,
  28717         soc_R1023_BCM53400_A0r_fields,
  28718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28719         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28720         64,
  28721         -1,
  28722         3,
  28723     },
  28724 #endif /* chips */
  28725 
  28726 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  28727     { /* SOC_REG_INT_XLMIB_R1023_BCM56980_A0r */
  28728         soc_block_list[16],
  28729         soc_portreg,
  28730         1,
  28731         0,
  28732         0x400,
  28733         SOC_REG_FLAG_64_BITS |
  28734                           SOC_REG_FLAG_COUNTER,
  28735         0,
  28736         1,
  28737         soc_R1023_BCM53400_A0r_fields,
  28738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28739         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28740         39,
  28741         -1,
  28742         3,
  28743     },
  28744 #endif /* chips */
  28745 
  28746 #if defined(BCM_53570_A0)
  28747     { /* SOC_REG_INT_XLMIB_R127_BCM53570_A0r */
  28748         soc_block_list[16],
  28749         soc_portreg,
  28750         1,
  28751         0,
  28752         0x100,
  28753         SOC_REG_FLAG_64_BITS |
  28754                           SOC_REG_FLAG_COUNTER,
  28755         0,
  28756         1,
  28757         soc_R1023_BCM53400_A0r_fields,
  28758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28760         155,
  28761         -1,
  28762     },
  28763 #endif /* chips */
  28764 
  28765 #if defined(BCM_53570_B0)
  28766     { /* SOC_REG_INT_XLMIB_R127_BCM53570_B0r */
  28767         soc_block_list[16],
  28768         soc_portreg,
  28769         1,
  28770         0,
  28771         0x100,
  28772         SOC_REG_FLAG_64_BITS |
  28773                           SOC_REG_FLAG_COUNTER,
  28774         0,
  28775         1,
  28776         soc_R1023_BCM53400_A0r_fields,
  28777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28778         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28779         159,
  28780         -1,
  28781     },
  28782 #endif /* chips */
  28783 
  28784 #if defined(BCM_56370_A0)
  28785     { /* SOC_REG_INT_XLMIB_R127_BCM56370_A0r */
  28786         soc_block_list[16],
  28787         soc_portreg,
  28788         1,
  28789         0,
  28790         0x100,
  28791         SOC_REG_FLAG_64_BITS |
  28792                           SOC_REG_FLAG_COUNTER,
  28793         0,
  28794         1,
  28795         soc_R1023_BCM53400_A0r_fields,
  28796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28797         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28798         61,
  28799         -1,
  28800         3,
  28801     },
  28802 #endif /* chips */
  28803 
  28804 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  28805     { /* SOC_REG_INT_XLMIB_R127_BCM56980_A0r */
  28806         soc_block_list[16],
  28807         soc_portreg,
  28808         1,
  28809         0,
  28810         0x100,
  28811         SOC_REG_FLAG_64_BITS |
  28812                           SOC_REG_FLAG_COUNTER,
  28813         0,
  28814         1,
  28815         soc_R1023_BCM53400_A0r_fields,
  28816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28817         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28818         36,
  28819         -1,
  28820         3,
  28821     },
  28822 #endif /* chips */
  28823 
  28824 #if defined(BCM_53570_A0)
  28825     { /* SOC_REG_INT_XLMIB_R1518_BCM53570_A0r */
  28826         soc_block_list[16],
  28827         soc_portreg,
  28828         1,
  28829         0,
  28830         0x500,
  28831         SOC_REG_FLAG_64_BITS |
  28832                           SOC_REG_FLAG_COUNTER,
  28833         0,
  28834         1,
  28835         soc_R1023_BCM53400_A0r_fields,
  28836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28837         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28838         159,
  28839         -1,
  28840     },
  28841 #endif /* chips */
  28842 
  28843 #if defined(BCM_53570_B0)
  28844     { /* SOC_REG_INT_XLMIB_R1518_BCM53570_B0r */
  28845         soc_block_list[16],
  28846         soc_portreg,
  28847         1,
  28848         0,
  28849         0x500,
  28850         SOC_REG_FLAG_64_BITS |
  28851                           SOC_REG_FLAG_COUNTER,
  28852         0,
  28853         1,
  28854         soc_R1023_BCM53400_A0r_fields,
  28855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28856         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28857         163,
  28858         -1,
  28859     },
  28860 #endif /* chips */
  28861 
  28862 #if defined(BCM_56370_A0)
  28863     { /* SOC_REG_INT_XLMIB_R1518_BCM56370_A0r */
  28864         soc_block_list[16],
  28865         soc_portreg,
  28866         1,
  28867         0,
  28868         0x500,
  28869         SOC_REG_FLAG_64_BITS |
  28870                           SOC_REG_FLAG_COUNTER,
  28871         0,
  28872         1,
  28873         soc_R1023_BCM53400_A0r_fields,
  28874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28875         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28876         65,
  28877         -1,
  28878         3,
  28879     },
  28880 #endif /* chips */
  28881 
  28882 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  28883     { /* SOC_REG_INT_XLMIB_R1518_BCM56980_A0r */
  28884         soc_block_list[16],
  28885         soc_portreg,
  28886         1,
  28887         0,
  28888         0x500,
  28889         SOC_REG_FLAG_64_BITS |
  28890                           SOC_REG_FLAG_COUNTER,
  28891         0,
  28892         1,
  28893         soc_R1023_BCM53400_A0r_fields,
  28894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28895         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28896         40,
  28897         -1,
  28898         3,
  28899     },
  28900 #endif /* chips */
  28901 
  28902 #if defined(BCM_53570_A0)
  28903     { /* SOC_REG_INT_XLMIB_R16383_BCM53570_A0r */
  28904         soc_block_list[16],
  28905         soc_portreg,
  28906         1,
  28907         0,
  28908         0xa00,
  28909         SOC_REG_FLAG_64_BITS |
  28910                           SOC_REG_FLAG_COUNTER,
  28911         0,
  28912         1,
  28913         soc_R1023_BCM53400_A0r_fields,
  28914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28916         164,
  28917         -1,
  28918     },
  28919 #endif /* chips */
  28920 
  28921 #if defined(BCM_53570_B0)
  28922     { /* SOC_REG_INT_XLMIB_R16383_BCM53570_B0r */
  28923         soc_block_list[16],
  28924         soc_portreg,
  28925         1,
  28926         0,
  28927         0xa00,
  28928         SOC_REG_FLAG_64_BITS |
  28929                           SOC_REG_FLAG_COUNTER,
  28930         0,
  28931         1,
  28932         soc_R1023_BCM53400_A0r_fields,
  28933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28934         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28935         168,
  28936         -1,
  28937     },
  28938 #endif /* chips */
  28939 
  28940 #if defined(BCM_56370_A0)
  28941     { /* SOC_REG_INT_XLMIB_R16383_BCM56370_A0r */
  28942         soc_block_list[16],
  28943         soc_portreg,
  28944         1,
  28945         0,
  28946         0xa00,
  28947         SOC_REG_FLAG_64_BITS |
  28948                           SOC_REG_FLAG_COUNTER,
  28949         0,
  28950         1,
  28951         soc_R1023_BCM53400_A0r_fields,
  28952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28953         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28954         70,
  28955         -1,
  28956         3,
  28957     },
  28958 #endif /* chips */
  28959 
  28960 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  28961     { /* SOC_REG_INT_XLMIB_R16383_BCM56980_A0r */
  28962         soc_block_list[16],
  28963         soc_portreg,
  28964         1,
  28965         0,
  28966         0xa00,
  28967         SOC_REG_FLAG_64_BITS |
  28968                           SOC_REG_FLAG_COUNTER,
  28969         0,
  28970         1,
  28971         soc_R1023_BCM53400_A0r_fields,
  28972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28973         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28974         45,
  28975         -1,
  28976         3,
  28977     },
  28978 #endif /* chips */
  28979 
  28980 #if defined(BCM_53570_A0)
  28981     { /* SOC_REG_INT_XLMIB_R2047_BCM53570_A0r */
  28982         soc_block_list[16],
  28983         soc_portreg,
  28984         1,
  28985         0,
  28986         0x700,
  28987         SOC_REG_FLAG_64_BITS |
  28988                           SOC_REG_FLAG_COUNTER,
  28989         0,
  28990         1,
  28991         soc_R1023_BCM53400_A0r_fields,
  28992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28994         161,
  28995         -1,
  28996     },
  28997 #endif /* chips */
  28998 
  28999 #if defined(BCM_53570_B0)
  29000     { /* SOC_REG_INT_XLMIB_R2047_BCM53570_B0r */
  29001         soc_block_list[16],
  29002         soc_portreg,
  29003         1,
  29004         0,
  29005         0x700,
  29006         SOC_REG_FLAG_64_BITS |
  29007                           SOC_REG_FLAG_COUNTER,
  29008         0,
  29009         1,
  29010         soc_R1023_BCM53400_A0r_fields,
  29011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29012         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29013         165,
  29014         -1,
  29015     },
  29016 #endif /* chips */
  29017 
  29018 #if defined(BCM_56370_A0)
  29019     { /* SOC_REG_INT_XLMIB_R2047_BCM56370_A0r */
  29020         soc_block_list[16],
  29021         soc_portreg,
  29022         1,
  29023         0,
  29024         0x700,
  29025         SOC_REG_FLAG_64_BITS |
  29026                           SOC_REG_FLAG_COUNTER,
  29027         0,
  29028         1,
  29029         soc_R1023_BCM53400_A0r_fields,
  29030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29032         67,
  29033         -1,
  29034         3,
  29035     },
  29036 #endif /* chips */
  29037 
  29038 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29039     { /* SOC_REG_INT_XLMIB_R2047_BCM56980_A0r */
  29040         soc_block_list[16],
  29041         soc_portreg,
  29042         1,
  29043         0,
  29044         0x700,
  29045         SOC_REG_FLAG_64_BITS |
  29046                           SOC_REG_FLAG_COUNTER,
  29047         0,
  29048         1,
  29049         soc_R1023_BCM53400_A0r_fields,
  29050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29052         42,
  29053         -1,
  29054         3,
  29055     },
  29056 #endif /* chips */
  29057 
  29058 #if defined(BCM_53570_A0)
  29059     { /* SOC_REG_INT_XLMIB_R255_BCM53570_A0r */
  29060         soc_block_list[16],
  29061         soc_portreg,
  29062         1,
  29063         0,
  29064         0x200,
  29065         SOC_REG_FLAG_64_BITS |
  29066                           SOC_REG_FLAG_COUNTER,
  29067         0,
  29068         1,
  29069         soc_R1023_BCM53400_A0r_fields,
  29070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29071         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29072         156,
  29073         -1,
  29074     },
  29075 #endif /* chips */
  29076 
  29077 #if defined(BCM_53570_B0)
  29078     { /* SOC_REG_INT_XLMIB_R255_BCM53570_B0r */
  29079         soc_block_list[16],
  29080         soc_portreg,
  29081         1,
  29082         0,
  29083         0x200,
  29084         SOC_REG_FLAG_64_BITS |
  29085                           SOC_REG_FLAG_COUNTER,
  29086         0,
  29087         1,
  29088         soc_R1023_BCM53400_A0r_fields,
  29089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29091         160,
  29092         -1,
  29093     },
  29094 #endif /* chips */
  29095 
  29096 #if defined(BCM_56370_A0)
  29097     { /* SOC_REG_INT_XLMIB_R255_BCM56370_A0r */
  29098         soc_block_list[16],
  29099         soc_portreg,
  29100         1,
  29101         0,
  29102         0x200,
  29103         SOC_REG_FLAG_64_BITS |
  29104                           SOC_REG_FLAG_COUNTER,
  29105         0,
  29106         1,
  29107         soc_R1023_BCM53400_A0r_fields,
  29108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29110         62,
  29111         -1,
  29112         3,
  29113     },
  29114 #endif /* chips */
  29115 
  29116 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29117     { /* SOC_REG_INT_XLMIB_R255_BCM56980_A0r */
  29118         soc_block_list[16],
  29119         soc_portreg,
  29120         1,
  29121         0,
  29122         0x200,
  29123         SOC_REG_FLAG_64_BITS |
  29124                           SOC_REG_FLAG_COUNTER,
  29125         0,
  29126         1,
  29127         soc_R1023_BCM53400_A0r_fields,
  29128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29129         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29130         37,
  29131         -1,
  29132         3,
  29133     },
  29134 #endif /* chips */
  29135 
  29136 #if defined(BCM_53570_A0)
  29137     { /* SOC_REG_INT_XLMIB_R4095_BCM53570_A0r */
  29138         soc_block_list[16],
  29139         soc_portreg,
  29140         1,
  29141         0,
  29142         0x800,
  29143         SOC_REG_FLAG_64_BITS |
  29144                           SOC_REG_FLAG_COUNTER,
  29145         0,
  29146         1,
  29147         soc_R1023_BCM53400_A0r_fields,
  29148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29150         162,
  29151         -1,
  29152     },
  29153 #endif /* chips */
  29154 
  29155 #if defined(BCM_53570_B0)
  29156     { /* SOC_REG_INT_XLMIB_R4095_BCM53570_B0r */
  29157         soc_block_list[16],
  29158         soc_portreg,
  29159         1,
  29160         0,
  29161         0x800,
  29162         SOC_REG_FLAG_64_BITS |
  29163                           SOC_REG_FLAG_COUNTER,
  29164         0,
  29165         1,
  29166         soc_R1023_BCM53400_A0r_fields,
  29167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29169         166,
  29170         -1,
  29171     },
  29172 #endif /* chips */
  29173 
  29174 #if defined(BCM_56370_A0)
  29175     { /* SOC_REG_INT_XLMIB_R4095_BCM56370_A0r */
  29176         soc_block_list[16],
  29177         soc_portreg,
  29178         1,
  29179         0,
  29180         0x800,
  29181         SOC_REG_FLAG_64_BITS |
  29182                           SOC_REG_FLAG_COUNTER,
  29183         0,
  29184         1,
  29185         soc_R1023_BCM53400_A0r_fields,
  29186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29187         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29188         68,
  29189         -1,
  29190         3,
  29191     },
  29192 #endif /* chips */
  29193 
  29194 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29195     { /* SOC_REG_INT_XLMIB_R4095_BCM56980_A0r */
  29196         soc_block_list[16],
  29197         soc_portreg,
  29198         1,
  29199         0,
  29200         0x800,
  29201         SOC_REG_FLAG_64_BITS |
  29202                           SOC_REG_FLAG_COUNTER,
  29203         0,
  29204         1,
  29205         soc_R1023_BCM53400_A0r_fields,
  29206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29207         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29208         43,
  29209         -1,
  29210         3,
  29211     },
  29212 #endif /* chips */
  29213 
  29214 #if defined(BCM_53570_A0)
  29215     { /* SOC_REG_INT_XLMIB_R511_BCM53570_A0r */
  29216         soc_block_list[16],
  29217         soc_portreg,
  29218         1,
  29219         0,
  29220         0x300,
  29221         SOC_REG_FLAG_64_BITS |
  29222                           SOC_REG_FLAG_COUNTER,
  29223         0,
  29224         1,
  29225         soc_R1023_BCM53400_A0r_fields,
  29226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29227         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29228         157,
  29229         -1,
  29230     },
  29231 #endif /* chips */
  29232 
  29233 #if defined(BCM_53570_B0)
  29234     { /* SOC_REG_INT_XLMIB_R511_BCM53570_B0r */
  29235         soc_block_list[16],
  29236         soc_portreg,
  29237         1,
  29238         0,
  29239         0x300,
  29240         SOC_REG_FLAG_64_BITS |
  29241                           SOC_REG_FLAG_COUNTER,
  29242         0,
  29243         1,
  29244         soc_R1023_BCM53400_A0r_fields,
  29245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29246         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29247         161,
  29248         -1,
  29249     },
  29250 #endif /* chips */
  29251 
  29252 #if defined(BCM_56370_A0)
  29253     { /* SOC_REG_INT_XLMIB_R511_BCM56370_A0r */
  29254         soc_block_list[16],
  29255         soc_portreg,
  29256         1,
  29257         0,
  29258         0x300,
  29259         SOC_REG_FLAG_64_BITS |
  29260                           SOC_REG_FLAG_COUNTER,
  29261         0,
  29262         1,
  29263         soc_R1023_BCM53400_A0r_fields,
  29264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29265         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29266         63,
  29267         -1,
  29268         3,
  29269     },
  29270 #endif /* chips */
  29271 
  29272 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29273     { /* SOC_REG_INT_XLMIB_R511_BCM56980_A0r */
  29274         soc_block_list[16],
  29275         soc_portreg,
  29276         1,
  29277         0,
  29278         0x300,
  29279         SOC_REG_FLAG_64_BITS |
  29280                           SOC_REG_FLAG_COUNTER,
  29281         0,
  29282         1,
  29283         soc_R1023_BCM53400_A0r_fields,
  29284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29285         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29286         38,
  29287         -1,
  29288         3,
  29289     },
  29290 #endif /* chips */
  29291 
  29292 #if defined(BCM_53570_A0)
  29293     { /* SOC_REG_INT_XLMIB_R64_BCM53570_A0r */
  29294         soc_block_list[16],
  29295         soc_portreg,
  29296         1,
  29297         0,
  29298         0,
  29299         SOC_REG_FLAG_64_BITS |
  29300                           SOC_REG_FLAG_COUNTER,
  29301         0,
  29302         1,
  29303         soc_R1023_BCM53400_A0r_fields,
  29304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29305         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29306         154,
  29307         -1,
  29308     },
  29309 #endif /* chips */
  29310 
  29311 #if defined(BCM_53570_B0)
  29312     { /* SOC_REG_INT_XLMIB_R64_BCM53570_B0r */
  29313         soc_block_list[16],
  29314         soc_portreg,
  29315         1,
  29316         0,
  29317         0,
  29318         SOC_REG_FLAG_64_BITS |
  29319                           SOC_REG_FLAG_COUNTER,
  29320         0,
  29321         1,
  29322         soc_R1023_BCM53400_A0r_fields,
  29323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29324         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29325         158,
  29326         -1,
  29327     },
  29328 #endif /* chips */
  29329 
  29330 #if defined(BCM_56370_A0)
  29331     { /* SOC_REG_INT_XLMIB_R64_BCM56370_A0r */
  29332         soc_block_list[16],
  29333         soc_portreg,
  29334         1,
  29335         0,
  29336         0,
  29337         SOC_REG_FLAG_64_BITS |
  29338                           SOC_REG_FLAG_COUNTER,
  29339         0,
  29340         1,
  29341         soc_R1023_BCM53400_A0r_fields,
  29342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29343         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29344         60,
  29345         -1,
  29346         3,
  29347     },
  29348 #endif /* chips */
  29349 
  29350 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29351     { /* SOC_REG_INT_XLMIB_R64_BCM56980_A0r */
  29352         soc_block_list[16],
  29353         soc_portreg,
  29354         1,
  29355         0,
  29356         0,
  29357         SOC_REG_FLAG_64_BITS |
  29358                           SOC_REG_FLAG_COUNTER,
  29359         0,
  29360         1,
  29361         soc_R1023_BCM53400_A0r_fields,
  29362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29363         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29364         35,
  29365         -1,
  29366         3,
  29367     },
  29368 #endif /* chips */
  29369 
  29370 #if defined(BCM_53570_A0)
  29371     { /* SOC_REG_INT_XLMIB_R9216_BCM53570_A0r */
  29372         soc_block_list[16],
  29373         soc_portreg,
  29374         1,
  29375         0,
  29376         0x900,
  29377         SOC_REG_FLAG_64_BITS |
  29378                           SOC_REG_FLAG_COUNTER,
  29379         0,
  29380         1,
  29381         soc_R1023_BCM53400_A0r_fields,
  29382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29384         163,
  29385         -1,
  29386     },
  29387 #endif /* chips */
  29388 
  29389 #if defined(BCM_53570_B0)
  29390     { /* SOC_REG_INT_XLMIB_R9216_BCM53570_B0r */
  29391         soc_block_list[16],
  29392         soc_portreg,
  29393         1,
  29394         0,
  29395         0x900,
  29396         SOC_REG_FLAG_64_BITS |
  29397                           SOC_REG_FLAG_COUNTER,
  29398         0,
  29399         1,
  29400         soc_R1023_BCM53400_A0r_fields,
  29401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29402         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29403         167,
  29404         -1,
  29405     },
  29406 #endif /* chips */
  29407 
  29408 #if defined(BCM_56370_A0)
  29409     { /* SOC_REG_INT_XLMIB_R9216_BCM56370_A0r */
  29410         soc_block_list[16],
  29411         soc_portreg,
  29412         1,
  29413         0,
  29414         0x900,
  29415         SOC_REG_FLAG_64_BITS |
  29416                           SOC_REG_FLAG_COUNTER,
  29417         0,
  29418         1,
  29419         soc_R1023_BCM53400_A0r_fields,
  29420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29421         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29422         69,
  29423         -1,
  29424         3,
  29425     },
  29426 #endif /* chips */
  29427 
  29428 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29429     { /* SOC_REG_INT_XLMIB_R9216_BCM56980_A0r */
  29430         soc_block_list[16],
  29431         soc_portreg,
  29432         1,
  29433         0,
  29434         0x900,
  29435         SOC_REG_FLAG_64_BITS |
  29436                           SOC_REG_FLAG_COUNTER,
  29437         0,
  29438         1,
  29439         soc_R1023_BCM53400_A0r_fields,
  29440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29441         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29442         44,
  29443         -1,
  29444         3,
  29445     },
  29446 #endif /* chips */
  29447 
  29448 #if defined(BCM_56970_A0)
  29449     { /* SOC_REG_INT_XLMIB_RALNr */
  29450         soc_block_list[16],
  29451         soc_portreg,
  29452         1,
  29453         0,
  29454         0x1600,
  29455         SOC_REG_FLAG_64_BITS |
  29456                           SOC_REG_FLAG_COUNTER,
  29457         0,
  29458         1,
  29459         soc_RALN_BCM53400_A0r_fields,
  29460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29461         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29462         77,
  29463         -1,
  29464         3,
  29465     },
  29466 #endif /* chips */
  29467 
  29468 #if defined(BCM_56370_A0)
  29469     { /* SOC_REG_INT_XLMIB_RALN_BCM56370_A0r */
  29470         soc_block_list[16],
  29471         soc_portreg,
  29472         1,
  29473         0,
  29474         0x1600,
  29475         SOC_REG_FLAG_64_BITS |
  29476                           SOC_REG_FLAG_COUNTER,
  29477         0,
  29478         1,
  29479         soc_RALN_BCM53400_A0r_fields,
  29480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29481         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29482         82,
  29483         -1,
  29484         3,
  29485     },
  29486 #endif /* chips */
  29487 
  29488 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  29489     { /* SOC_REG_INT_XLMIB_RALN_BCM56870_A0r */
  29490         soc_block_list[16],
  29491         soc_portreg,
  29492         1,
  29493         0,
  29494         0x1600,
  29495         SOC_REG_FLAG_64_BITS |
  29496                           SOC_REG_FLAG_COUNTER,
  29497         0,
  29498         1,
  29499         soc_RALN_BCM53400_A0r_fields,
  29500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29501         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29502         81,
  29503         -1,
  29504         3,
  29505     },
  29506 #endif /* chips */
  29507 
  29508 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29509     { /* SOC_REG_INT_XLMIB_RALN_BCM56980_A0r */
  29510         soc_block_list[16],
  29511         soc_portreg,
  29512         1,
  29513         0,
  29514         0x1600,
  29515         SOC_REG_FLAG_64_BITS |
  29516                           SOC_REG_FLAG_COUNTER,
  29517         0,
  29518         1,
  29519         soc_RALN_BCM53400_A0r_fields,
  29520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29521         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29522         57,
  29523         -1,
  29524         3,
  29525     },
  29526 #endif /* chips */
  29527 
  29528 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  29529     { /* SOC_REG_INT_XLMIB_RBCAr */
  29530         soc_block_list[16],
  29531         soc_portreg,
  29532         1,
  29533         0,
  29534         0xe00,
  29535         SOC_REG_FLAG_64_BITS |
  29536                           SOC_REG_FLAG_COUNTER,
  29537         0,
  29538         1,
  29539         soc_R1023_BCM53400_A0r_fields,
  29540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29541         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29542         73,
  29543         -1,
  29544         3,
  29545     },
  29546 #endif /* chips */
  29547 
  29548 #if defined(BCM_53570_A0)
  29549     { /* SOC_REG_INT_XLMIB_RBCA_BCM53570_A0r */
  29550         soc_block_list[16],
  29551         soc_portreg,
  29552         1,
  29553         0,
  29554         0xe00,
  29555         SOC_REG_FLAG_64_BITS |
  29556                           SOC_REG_FLAG_COUNTER,
  29557         0,
  29558         1,
  29559         soc_R1023_BCM53400_A0r_fields,
  29560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29562         168,
  29563         -1,
  29564     },
  29565 #endif /* chips */
  29566 
  29567 #if defined(BCM_53570_B0)
  29568     { /* SOC_REG_INT_XLMIB_RBCA_BCM53570_B0r */
  29569         soc_block_list[16],
  29570         soc_portreg,
  29571         1,
  29572         0,
  29573         0xe00,
  29574         SOC_REG_FLAG_64_BITS |
  29575                           SOC_REG_FLAG_COUNTER,
  29576         0,
  29577         1,
  29578         soc_R1023_BCM53400_A0r_fields,
  29579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29580         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29581         172,
  29582         -1,
  29583     },
  29584 #endif /* chips */
  29585 
  29586 #if defined(BCM_56370_A0)
  29587     { /* SOC_REG_INT_XLMIB_RBCA_BCM56370_A0r */
  29588         soc_block_list[16],
  29589         soc_portreg,
  29590         1,
  29591         0,
  29592         0xe00,
  29593         SOC_REG_FLAG_64_BITS |
  29594                           SOC_REG_FLAG_COUNTER,
  29595         0,
  29596         1,
  29597         soc_R1023_BCM53400_A0r_fields,
  29598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29599         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29600         74,
  29601         -1,
  29602         3,
  29603     },
  29604 #endif /* chips */
  29605 
  29606 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29607     { /* SOC_REG_INT_XLMIB_RBCA_BCM56980_A0r */
  29608         soc_block_list[16],
  29609         soc_portreg,
  29610         1,
  29611         0,
  29612         0xe00,
  29613         SOC_REG_FLAG_64_BITS |
  29614                           SOC_REG_FLAG_COUNTER,
  29615         0,
  29616         1,
  29617         soc_R1023_BCM53400_A0r_fields,
  29618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29619         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29620         49,
  29621         -1,
  29622         3,
  29623     },
  29624 #endif /* chips */
  29625 
  29626 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  29627     { /* SOC_REG_INT_XLMIB_RBYTr */
  29628         soc_block_list[16],
  29629         soc_portreg,
  29630         1,
  29631         0,
  29632         0x3d00,
  29633         SOC_REG_FLAG_64_BITS |
  29634                           SOC_REG_FLAG_COUNTER,
  29635         0,
  29636         1,
  29637         soc_RBYT_BCM53400_A0r_fields,
  29638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29639         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29640         120,
  29641         -1,
  29642         3,
  29643     },
  29644 #endif /* chips */
  29645 
  29646 #if defined(BCM_53570_A0)
  29647     { /* SOC_REG_INT_XLMIB_RBYT_BCM53570_A0r */
  29648         soc_block_list[16],
  29649         soc_portreg,
  29650         1,
  29651         0,
  29652         0x3d00,
  29653         SOC_REG_FLAG_64_BITS |
  29654                           SOC_REG_FLAG_COUNTER,
  29655         0,
  29656         1,
  29657         soc_RBYT_BCM53400_A0r_fields,
  29658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29659         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29660         215,
  29661         -1,
  29662     },
  29663 #endif /* chips */
  29664 
  29665 #if defined(BCM_53570_B0)
  29666     { /* SOC_REG_INT_XLMIB_RBYT_BCM53570_B0r */
  29667         soc_block_list[16],
  29668         soc_portreg,
  29669         1,
  29670         0,
  29671         0x3d00,
  29672         SOC_REG_FLAG_64_BITS |
  29673                           SOC_REG_FLAG_COUNTER,
  29674         0,
  29675         1,
  29676         soc_RBYT_BCM53400_A0r_fields,
  29677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29678         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29679         219,
  29680         -1,
  29681     },
  29682 #endif /* chips */
  29683 
  29684 #if defined(BCM_56370_A0)
  29685     { /* SOC_REG_INT_XLMIB_RBYT_BCM56370_A0r */
  29686         soc_block_list[16],
  29687         soc_portreg,
  29688         1,
  29689         0,
  29690         0x3d00,
  29691         SOC_REG_FLAG_64_BITS |
  29692                           SOC_REG_FLAG_COUNTER,
  29693         0,
  29694         1,
  29695         soc_RBYT_BCM53400_A0r_fields,
  29696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29697         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29698         121,
  29699         -1,
  29700         3,
  29701     },
  29702 #endif /* chips */
  29703 
  29704 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29705     { /* SOC_REG_INT_XLMIB_RBYT_BCM56980_A0r */
  29706         soc_block_list[16],
  29707         soc_portreg,
  29708         1,
  29709         0,
  29710         0x3d00,
  29711         SOC_REG_FLAG_64_BITS |
  29712                           SOC_REG_FLAG_COUNTER,
  29713         0,
  29714         1,
  29715         soc_RBYT_BCM53400_A0r_fields,
  29716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29718         96,
  29719         -1,
  29720         3,
  29721     },
  29722 #endif /* chips */
  29723 
  29724 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  29725     { /* SOC_REG_INT_XLMIB_RDVLNr */
  29726         soc_block_list[16],
  29727         soc_portreg,
  29728         1,
  29729         0,
  29730         0x2000,
  29731         SOC_REG_FLAG_64_BITS |
  29732                           SOC_REG_FLAG_COUNTER,
  29733         0,
  29734         1,
  29735         soc_R1023_BCM53400_A0r_fields,
  29736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29737         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29738         91,
  29739         -1,
  29740         3,
  29741     },
  29742 #endif /* chips */
  29743 
  29744 #if defined(BCM_53570_A0)
  29745     { /* SOC_REG_INT_XLMIB_RDVLN_BCM53570_A0r */
  29746         soc_block_list[16],
  29747         soc_portreg,
  29748         1,
  29749         0,
  29750         0x2000,
  29751         SOC_REG_FLAG_64_BITS |
  29752                           SOC_REG_FLAG_COUNTER,
  29753         0,
  29754         1,
  29755         soc_R1023_BCM53400_A0r_fields,
  29756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29757         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29758         186,
  29759         -1,
  29760     },
  29761 #endif /* chips */
  29762 
  29763 #if defined(BCM_53570_B0)
  29764     { /* SOC_REG_INT_XLMIB_RDVLN_BCM53570_B0r */
  29765         soc_block_list[16],
  29766         soc_portreg,
  29767         1,
  29768         0,
  29769         0x2000,
  29770         SOC_REG_FLAG_64_BITS |
  29771                           SOC_REG_FLAG_COUNTER,
  29772         0,
  29773         1,
  29774         soc_R1023_BCM53400_A0r_fields,
  29775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29776         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29777         190,
  29778         -1,
  29779     },
  29780 #endif /* chips */
  29781 
  29782 #if defined(BCM_56370_A0)
  29783     { /* SOC_REG_INT_XLMIB_RDVLN_BCM56370_A0r */
  29784         soc_block_list[16],
  29785         soc_portreg,
  29786         1,
  29787         0,
  29788         0x2000,
  29789         SOC_REG_FLAG_64_BITS |
  29790                           SOC_REG_FLAG_COUNTER,
  29791         0,
  29792         1,
  29793         soc_R1023_BCM53400_A0r_fields,
  29794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29795         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29796         92,
  29797         -1,
  29798         3,
  29799     },
  29800 #endif /* chips */
  29801 
  29802 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29803     { /* SOC_REG_INT_XLMIB_RDVLN_BCM56980_A0r */
  29804         soc_block_list[16],
  29805         soc_portreg,
  29806         1,
  29807         0,
  29808         0x2000,
  29809         SOC_REG_FLAG_64_BITS |
  29810                           SOC_REG_FLAG_COUNTER,
  29811         0,
  29812         1,
  29813         soc_R1023_BCM53400_A0r_fields,
  29814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29815         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29816         67,
  29817         -1,
  29818         3,
  29819     },
  29820 #endif /* chips */
  29821 
  29822 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  29823     { /* SOC_REG_INT_XLMIB_RERPKTr */
  29824         soc_block_list[16],
  29825         soc_portreg,
  29826         1,
  29827         0,
  29828         0x1800,
  29829         SOC_REG_FLAG_64_BITS |
  29830                           SOC_REG_FLAG_COUNTER |
  29831                           SOC_REG_FLAG_ED_CNTR,
  29832         0,
  29833         1,
  29834         soc_R1023_BCM53400_A0r_fields,
  29835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29836         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29837         83,
  29838         -1,
  29839         3,
  29840     },
  29841 #endif /* chips */
  29842 
  29843 #if defined(BCM_53570_A0)
  29844     { /* SOC_REG_INT_XLMIB_RERPKT_BCM53570_A0r */
  29845         soc_block_list[16],
  29846         soc_portreg,
  29847         1,
  29848         0,
  29849         0x1800,
  29850         SOC_REG_FLAG_64_BITS |
  29851                           SOC_REG_FLAG_COUNTER |
  29852                           SOC_REG_FLAG_ED_CNTR,
  29853         0,
  29854         1,
  29855         soc_R1023_BCM53400_A0r_fields,
  29856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29857         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29858         178,
  29859         -1,
  29860     },
  29861 #endif /* chips */
  29862 
  29863 #if defined(BCM_53570_B0)
  29864     { /* SOC_REG_INT_XLMIB_RERPKT_BCM53570_B0r */
  29865         soc_block_list[16],
  29866         soc_portreg,
  29867         1,
  29868         0,
  29869         0x1800,
  29870         SOC_REG_FLAG_64_BITS |
  29871                           SOC_REG_FLAG_COUNTER |
  29872                           SOC_REG_FLAG_ED_CNTR,
  29873         0,
  29874         1,
  29875         soc_R1023_BCM53400_A0r_fields,
  29876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29877         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29878         182,
  29879         -1,
  29880     },
  29881 #endif /* chips */
  29882 
  29883 #if defined(BCM_56370_A0)
  29884     { /* SOC_REG_INT_XLMIB_RERPKT_BCM56370_A0r */
  29885         soc_block_list[16],
  29886         soc_portreg,
  29887         1,
  29888         0,
  29889         0x1800,
  29890         SOC_REG_FLAG_64_BITS |
  29891                           SOC_REG_FLAG_COUNTER |
  29892                           SOC_REG_FLAG_ED_CNTR,
  29893         0,
  29894         1,
  29895         soc_R1023_BCM53400_A0r_fields,
  29896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29897         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29898         84,
  29899         -1,
  29900         3,
  29901     },
  29902 #endif /* chips */
  29903 
  29904 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29905     { /* SOC_REG_INT_XLMIB_RERPKT_BCM56980_A0r */
  29906         soc_block_list[16],
  29907         soc_portreg,
  29908         1,
  29909         0,
  29910         0x1800,
  29911         SOC_REG_FLAG_64_BITS |
  29912                           SOC_REG_FLAG_COUNTER |
  29913                           SOC_REG_FLAG_ED_CNTR,
  29914         0,
  29915         1,
  29916         soc_R1023_BCM53400_A0r_fields,
  29917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29918         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29919         59,
  29920         -1,
  29921         3,
  29922     },
  29923 #endif /* chips */
  29924 
  29925 #if defined(BCM_56970_A0)
  29926     { /* SOC_REG_INT_XLMIB_RFCRr */
  29927         soc_block_list[16],
  29928         soc_portreg,
  29929         1,
  29930         0,
  29931         0x1900,
  29932         SOC_REG_FLAG_64_BITS |
  29933                           SOC_REG_FLAG_COUNTER,
  29934         0,
  29935         1,
  29936         soc_RALN_BCM53400_A0r_fields,
  29937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29938         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29939         80,
  29940         -1,
  29941         3,
  29942     },
  29943 #endif /* chips */
  29944 
  29945 #if defined(BCM_56370_A0)
  29946     { /* SOC_REG_INT_XLMIB_RFCR_BCM56370_A0r */
  29947         soc_block_list[16],
  29948         soc_portreg,
  29949         1,
  29950         0,
  29951         0x1900,
  29952         SOC_REG_FLAG_64_BITS |
  29953                           SOC_REG_FLAG_COUNTER,
  29954         0,
  29955         1,
  29956         soc_RALN_BCM53400_A0r_fields,
  29957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29958         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29959         85,
  29960         -1,
  29961         3,
  29962     },
  29963 #endif /* chips */
  29964 
  29965 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  29966     { /* SOC_REG_INT_XLMIB_RFCR_BCM56870_A0r */
  29967         soc_block_list[16],
  29968         soc_portreg,
  29969         1,
  29970         0,
  29971         0x1900,
  29972         SOC_REG_FLAG_64_BITS |
  29973                           SOC_REG_FLAG_COUNTER,
  29974         0,
  29975         1,
  29976         soc_RALN_BCM53400_A0r_fields,
  29977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29978         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29979         84,
  29980         -1,
  29981         3,
  29982     },
  29983 #endif /* chips */
  29984 
  29985 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  29986     { /* SOC_REG_INT_XLMIB_RFCR_BCM56980_A0r */
  29987         soc_block_list[16],
  29988         soc_portreg,
  29989         1,
  29990         0,
  29991         0x1900,
  29992         SOC_REG_FLAG_64_BITS |
  29993                           SOC_REG_FLAG_COUNTER,
  29994         0,
  29995         1,
  29996         soc_RALN_BCM53400_A0r_fields,
  29997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29998         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  29999         60,
  30000         -1,
  30001         3,
  30002     },
  30003 #endif /* chips */
  30004 
  30005 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30006     { /* SOC_REG_INT_XLMIB_RFCSr */
  30007         soc_block_list[16],
  30008         soc_portreg,
  30009         1,
  30010         0,
  30011         0xf00,
  30012         SOC_REG_FLAG_64_BITS |
  30013                           SOC_REG_FLAG_COUNTER,
  30014         0,
  30015         1,
  30016         soc_R1023_BCM53400_A0r_fields,
  30017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30018         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30019         74,
  30020         -1,
  30021         3,
  30022     },
  30023 #endif /* chips */
  30024 
  30025 #if defined(BCM_53570_A0)
  30026     { /* SOC_REG_INT_XLMIB_RFCS_BCM53570_A0r */
  30027         soc_block_list[16],
  30028         soc_portreg,
  30029         1,
  30030         0,
  30031         0xf00,
  30032         SOC_REG_FLAG_64_BITS |
  30033                           SOC_REG_FLAG_COUNTER,
  30034         0,
  30035         1,
  30036         soc_R1023_BCM53400_A0r_fields,
  30037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30038         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30039         169,
  30040         -1,
  30041     },
  30042 #endif /* chips */
  30043 
  30044 #if defined(BCM_53570_B0)
  30045     { /* SOC_REG_INT_XLMIB_RFCS_BCM53570_B0r */
  30046         soc_block_list[16],
  30047         soc_portreg,
  30048         1,
  30049         0,
  30050         0xf00,
  30051         SOC_REG_FLAG_64_BITS |
  30052                           SOC_REG_FLAG_COUNTER,
  30053         0,
  30054         1,
  30055         soc_R1023_BCM53400_A0r_fields,
  30056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30057         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30058         173,
  30059         -1,
  30060     },
  30061 #endif /* chips */
  30062 
  30063 #if defined(BCM_56370_A0)
  30064     { /* SOC_REG_INT_XLMIB_RFCS_BCM56370_A0r */
  30065         soc_block_list[16],
  30066         soc_portreg,
  30067         1,
  30068         0,
  30069         0xf00,
  30070         SOC_REG_FLAG_64_BITS |
  30071                           SOC_REG_FLAG_COUNTER,
  30072         0,
  30073         1,
  30074         soc_R1023_BCM53400_A0r_fields,
  30075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30076         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30077         75,
  30078         -1,
  30079         3,
  30080     },
  30081 #endif /* chips */
  30082 
  30083 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  30084     { /* SOC_REG_INT_XLMIB_RFCS_BCM56980_A0r */
  30085         soc_block_list[16],
  30086         soc_portreg,
  30087         1,
  30088         0,
  30089         0xf00,
  30090         SOC_REG_FLAG_64_BITS |
  30091                           SOC_REG_FLAG_COUNTER,
  30092         0,
  30093         1,
  30094         soc_R1023_BCM53400_A0r_fields,
  30095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30096         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30097         50,
  30098         -1,
  30099         3,
  30100     },
  30101 #endif /* chips */
  30102 
  30103 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30104     { /* SOC_REG_INT_XLMIB_RFLRr */
  30105         soc_block_list[16],
  30106         soc_portreg,
  30107         1,
  30108         0,
  30109         0x1700,
  30110         SOC_REG_FLAG_64_BITS |
  30111                           SOC_REG_FLAG_COUNTER |
  30112                           SOC_REG_FLAG_ED_CNTR,
  30113         0,
  30114         1,
  30115         soc_R1023_BCM53400_A0r_fields,
  30116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30118         82,
  30119         -1,
  30120         3,
  30121     },
  30122 #endif /* chips */
  30123 
  30124 #if defined(BCM_53570_A0)
  30125     { /* SOC_REG_INT_XLMIB_RFLR_BCM53570_A0r */
  30126         soc_block_list[16],
  30127         soc_portreg,
  30128         1,
  30129         0,
  30130         0x1700,
  30131         SOC_REG_FLAG_64_BITS |
  30132                           SOC_REG_FLAG_COUNTER |
  30133                           SOC_REG_FLAG_ED_CNTR,
  30134         0,
  30135         1,
  30136         soc_R1023_BCM53400_A0r_fields,
  30137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30138         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30139         177,
  30140         -1,
  30141     },
  30142 #endif /* chips */
  30143 
  30144 #if defined(BCM_53570_B0)
  30145     { /* SOC_REG_INT_XLMIB_RFLR_BCM53570_B0r */
  30146         soc_block_list[16],
  30147         soc_portreg,
  30148         1,
  30149         0,
  30150         0x1700,
  30151         SOC_REG_FLAG_64_BITS |
  30152                           SOC_REG_FLAG_COUNTER |
  30153                           SOC_REG_FLAG_ED_CNTR,
  30154         0,
  30155         1,
  30156         soc_R1023_BCM53400_A0r_fields,
  30157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30158         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30159         181,
  30160         -1,
  30161     },
  30162 #endif /* chips */
  30163 
  30164 #if defined(BCM_56370_A0)
  30165     { /* SOC_REG_INT_XLMIB_RFLR_BCM56370_A0r */
  30166         soc_block_list[16],
  30167         soc_portreg,
  30168         1,
  30169         0,
  30170         0x1700,
  30171         SOC_REG_FLAG_64_BITS |
  30172                           SOC_REG_FLAG_COUNTER |
  30173                           SOC_REG_FLAG_ED_CNTR,
  30174         0,
  30175         1,
  30176         soc_R1023_BCM53400_A0r_fields,
  30177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30178         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30179         83,
  30180         -1,
  30181         3,
  30182     },
  30183 #endif /* chips */
  30184 
  30185 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  30186     { /* SOC_REG_INT_XLMIB_RFLR_BCM56980_A0r */
  30187         soc_block_list[16],
  30188         soc_portreg,
  30189         1,
  30190         0,
  30191         0x1700,
  30192         SOC_REG_FLAG_64_BITS |
  30193                           SOC_REG_FLAG_COUNTER |
  30194                           SOC_REG_FLAG_ED_CNTR,
  30195         0,
  30196         1,
  30197         soc_R1023_BCM53400_A0r_fields,
  30198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30200         58,
  30201         -1,
  30202         3,
  30203     },
  30204 #endif /* chips */
  30205 
  30206 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30207     { /* SOC_REG_INT_XLMIB_RFRGr */
  30208         soc_block_list[16],
  30209         soc_portreg,
  30210         1,
  30211         0,
  30212         0x3500,
  30213         SOC_REG_FLAG_64_BITS |
  30214                           SOC_REG_FLAG_COUNTER |
  30215                           SOC_REG_FLAG_ED_CNTR,
  30216         0,
  30217         1,
  30218         soc_R1023_BCM53400_A0r_fields,
  30219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30220         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30221         112,
  30222         -1,
  30223         3,
  30224     },
  30225 #endif /* chips */
  30226 
  30227 #if defined(BCM_53570_A0)
  30228     { /* SOC_REG_INT_XLMIB_RFRG_BCM53570_A0r */
  30229         soc_block_list[16],
  30230         soc_portreg,
  30231         1,
  30232         0,
  30233         0x3500,
  30234         SOC_REG_FLAG_64_BITS |
  30235                           SOC_REG_FLAG_COUNTER |
  30236                           SOC_REG_FLAG_ED_CNTR,
  30237         0,
  30238         1,
  30239         soc_R1023_BCM53400_A0r_fields,
  30240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30241         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30242         207,
  30243         -1,
  30244     },
  30245 #endif /* chips */
  30246 
  30247 #if defined(BCM_53570_B0)
  30248     { /* SOC_REG_INT_XLMIB_RFRG_BCM53570_B0r */
  30249         soc_block_list[16],
  30250         soc_portreg,
  30251         1,
  30252         0,
  30253         0x3500,
  30254         SOC_REG_FLAG_64_BITS |
  30255                           SOC_REG_FLAG_COUNTER |
  30256                           SOC_REG_FLAG_ED_CNTR,
  30257         0,
  30258         1,
  30259         soc_R1023_BCM53400_A0r_fields,
  30260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30261         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30262         211,
  30263         -1,
  30264     },
  30265 #endif /* chips */
  30266 
  30267 #if defined(BCM_56370_A0)
  30268     { /* SOC_REG_INT_XLMIB_RFRG_BCM56370_A0r */
  30269         soc_block_list[16],
  30270         soc_portreg,
  30271         1,
  30272         0,
  30273         0x3500,
  30274         SOC_REG_FLAG_64_BITS |
  30275                           SOC_REG_FLAG_COUNTER |
  30276                           SOC_REG_FLAG_ED_CNTR,
  30277         0,
  30278         1,
  30279         soc_R1023_BCM53400_A0r_fields,
  30280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30281         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30282         113,
  30283         -1,
  30284         3,
  30285     },
  30286 #endif /* chips */
  30287 
  30288 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  30289     { /* SOC_REG_INT_XLMIB_RFRG_BCM56980_A0r */
  30290         soc_block_list[16],
  30291         soc_portreg,
  30292         1,
  30293         0,
  30294         0x3500,
  30295         SOC_REG_FLAG_64_BITS |
  30296                           SOC_REG_FLAG_COUNTER |
  30297                           SOC_REG_FLAG_ED_CNTR,
  30298         0,
  30299         1,
  30300         soc_R1023_BCM53400_A0r_fields,
  30301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30302         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30303         88,
  30304         -1,
  30305         3,
  30306     },
  30307 #endif /* chips */
  30308 
  30309 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30310     { /* SOC_REG_INT_XLMIB_RJBRr */
  30311         soc_block_list[16],
  30312         soc_portreg,
  30313         1,
  30314         0,
  30315         0x1b00,
  30316         SOC_REG_FLAG_64_BITS |
  30317                           SOC_REG_FLAG_COUNTER |
  30318                           SOC_REG_FLAG_ED_CNTR,
  30319         0,
  30320         1,
  30321         soc_R1023_BCM53400_A0r_fields,
  30322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30323         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30324         86,
  30325         -1,
  30326         3,
  30327     },
  30328 #endif /* chips */
  30329 
  30330 #if defined(BCM_53570_A0)
  30331     { /* SOC_REG_INT_XLMIB_RJBR_BCM53570_A0r */
  30332         soc_block_list[16],
  30333         soc_portreg,
  30334         1,
  30335         0,
  30336         0x1b00,
  30337         SOC_REG_FLAG_64_BITS |
  30338                           SOC_REG_FLAG_COUNTER |
  30339                           SOC_REG_FLAG_ED_CNTR,
  30340         0,
  30341         1,
  30342         soc_R1023_BCM53400_A0r_fields,
  30343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30344         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30345         181,
  30346         -1,
  30347     },
  30348 #endif /* chips */
  30349 
  30350 #if defined(BCM_53570_B0)
  30351     { /* SOC_REG_INT_XLMIB_RJBR_BCM53570_B0r */
  30352         soc_block_list[16],
  30353         soc_portreg,
  30354         1,
  30355         0,
  30356         0x1b00,
  30357         SOC_REG_FLAG_64_BITS |
  30358                           SOC_REG_FLAG_COUNTER |
  30359                           SOC_REG_FLAG_ED_CNTR,
  30360         0,
  30361         1,
  30362         soc_R1023_BCM53400_A0r_fields,
  30363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30364         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30365         185,
  30366         -1,
  30367     },
  30368 #endif /* chips */
  30369 
  30370 #if defined(BCM_56370_A0)
  30371     { /* SOC_REG_INT_XLMIB_RJBR_BCM56370_A0r */
  30372         soc_block_list[16],
  30373         soc_portreg,
  30374         1,
  30375         0,
  30376         0x1b00,
  30377         SOC_REG_FLAG_64_BITS |
  30378                           SOC_REG_FLAG_COUNTER |
  30379                           SOC_REG_FLAG_ED_CNTR,
  30380         0,
  30381         1,
  30382         soc_R1023_BCM53400_A0r_fields,
  30383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30384         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30385         87,
  30386         -1,
  30387         3,
  30388     },
  30389 #endif /* chips */
  30390 
  30391 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  30392     { /* SOC_REG_INT_XLMIB_RJBR_BCM56980_A0r */
  30393         soc_block_list[16],
  30394         soc_portreg,
  30395         1,
  30396         0,
  30397         0x1b00,
  30398         SOC_REG_FLAG_64_BITS |
  30399                           SOC_REG_FLAG_COUNTER |
  30400                           SOC_REG_FLAG_ED_CNTR,
  30401         0,
  30402         1,
  30403         soc_R1023_BCM53400_A0r_fields,
  30404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30405         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30406         62,
  30407         -1,
  30408         3,
  30409     },
  30410 #endif /* chips */
  30411 
  30412 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30413     { /* SOC_REG_INT_XLMIB_RMCAr */
  30414         soc_block_list[16],
  30415         soc_portreg,
  30416         1,
  30417         0,
  30418         0xd00,
  30419         SOC_REG_FLAG_64_BITS |
  30420                           SOC_REG_FLAG_COUNTER,
  30421         0,
  30422         1,
  30423         soc_R1023_BCM53400_A0r_fields,
  30424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30425         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30426         72,
  30427         -1,
  30428         3,
  30429     },
  30430 #endif /* chips */
  30431 
  30432 #if defined(BCM_53570_A0)
  30433     { /* SOC_REG_INT_XLMIB_RMCA_BCM53570_A0r */
  30434         soc_block_list[16],
  30435         soc_portreg,
  30436         1,
  30437         0,
  30438         0xd00,
  30439         SOC_REG_FLAG_64_BITS |
  30440                           SOC_REG_FLAG_COUNTER,
  30441         0,
  30442         1,
  30443         soc_R1023_BCM53400_A0r_fields,
  30444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30445         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30446         167,
  30447         -1,
  30448     },
  30449 #endif /* chips */
  30450 
  30451 #if defined(BCM_53570_B0)
  30452     { /* SOC_REG_INT_XLMIB_RMCA_BCM53570_B0r */
  30453         soc_block_list[16],
  30454         soc_portreg,
  30455         1,
  30456         0,
  30457         0xd00,
  30458         SOC_REG_FLAG_64_BITS |
  30459                           SOC_REG_FLAG_COUNTER,
  30460         0,
  30461         1,
  30462         soc_R1023_BCM53400_A0r_fields,
  30463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30464         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30465         171,
  30466         -1,
  30467     },
  30468 #endif /* chips */
  30469 
  30470 #if defined(BCM_56370_A0)
  30471     { /* SOC_REG_INT_XLMIB_RMCA_BCM56370_A0r */
  30472         soc_block_list[16],
  30473         soc_portreg,
  30474         1,
  30475         0,
  30476         0xd00,
  30477         SOC_REG_FLAG_64_BITS |
  30478                           SOC_REG_FLAG_COUNTER,
  30479         0,
  30480         1,
  30481         soc_R1023_BCM53400_A0r_fields,
  30482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30484         73,
  30485         -1,
  30486         3,
  30487     },
  30488 #endif /* chips */
  30489 
  30490 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  30491     { /* SOC_REG_INT_XLMIB_RMCA_BCM56980_A0r */
  30492         soc_block_list[16],
  30493         soc_portreg,
  30494         1,
  30495         0,
  30496         0xd00,
  30497         SOC_REG_FLAG_64_BITS |
  30498                           SOC_REG_FLAG_COUNTER,
  30499         0,
  30500         1,
  30501         soc_R1023_BCM53400_A0r_fields,
  30502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30503         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30504         48,
  30505         -1,
  30506         3,
  30507     },
  30508 #endif /* chips */
  30509 
  30510 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30511     { /* SOC_REG_INT_XLMIB_RMCRCr */
  30512         soc_block_list[16],
  30513         soc_portreg,
  30514         1,
  30515         0,
  30516         0x1d00,
  30517         SOC_REG_FLAG_64_BITS |
  30518                           SOC_REG_FLAG_COUNTER,
  30519         0,
  30520         1,
  30521         soc_R1023_BCM53400_A0r_fields,
  30522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30523         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30524         88,
  30525         -1,
  30526         3,
  30527     },
  30528 #endif /* chips */
  30529 
  30530 #if defined(BCM_53570_A0)
  30531     { /* SOC_REG_INT_XLMIB_RMCRC_BCM53570_A0r */
  30532         soc_block_list[16],
  30533         soc_portreg,
  30534         1,
  30535         0,
  30536         0x1d00,
  30537         SOC_REG_FLAG_64_BITS |
  30538                           SOC_REG_FLAG_COUNTER,
  30539         0,
  30540         1,
  30541         soc_R1023_BCM53400_A0r_fields,
  30542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30543         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30544         183,
  30545         -1,
  30546     },
  30547 #endif /* chips */
  30548 
  30549 #if defined(BCM_53570_B0)
  30550     { /* SOC_REG_INT_XLMIB_RMCRC_BCM53570_B0r */
  30551         soc_block_list[16],
  30552         soc_portreg,
  30553         1,
  30554         0,
  30555         0x1d00,
  30556         SOC_REG_FLAG_64_BITS |
  30557                           SOC_REG_FLAG_COUNTER,
  30558         0,
  30559         1,
  30560         soc_R1023_BCM53400_A0r_fields,
  30561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30562         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30563         187,
  30564         -1,
  30565     },
  30566 #endif /* chips */
  30567 
  30568 #if defined(BCM_56370_A0)
  30569     { /* SOC_REG_INT_XLMIB_RMCRC_BCM56370_A0r */
  30570         soc_block_list[16],
  30571         soc_portreg,
  30572         1,
  30573         0,
  30574         0x1d00,
  30575         SOC_REG_FLAG_64_BITS |
  30576                           SOC_REG_FLAG_COUNTER,
  30577         0,
  30578         1,
  30579         soc_R1023_BCM53400_A0r_fields,
  30580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30581         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30582         89,
  30583         -1,
  30584         3,
  30585     },
  30586 #endif /* chips */
  30587 
  30588 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  30589     { /* SOC_REG_INT_XLMIB_RMCRC_BCM56980_A0r */
  30590         soc_block_list[16],
  30591         soc_portreg,
  30592         1,
  30593         0,
  30594         0x1d00,
  30595         SOC_REG_FLAG_64_BITS |
  30596                           SOC_REG_FLAG_COUNTER,
  30597         0,
  30598         1,
  30599         soc_R1023_BCM53400_A0r_fields,
  30600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30601         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30602         64,
  30603         -1,
  30604         3,
  30605     },
  30606 #endif /* chips */
  30607 
  30608 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30609     { /* SOC_REG_INT_XLMIB_RMGVr */
  30610         soc_block_list[16],
  30611         soc_portreg,
  30612         1,
  30613         0,
  30614         0x600,
  30615         SOC_REG_FLAG_64_BITS |
  30616                           SOC_REG_FLAG_COUNTER,
  30617         0,
  30618         1,
  30619         soc_R1023_BCM53400_A0r_fields,
  30620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30621         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30622         65,
  30623         -1,
  30624         3,
  30625     },
  30626 #endif /* chips */
  30627 
  30628 #if defined(BCM_53570_A0)
  30629     { /* SOC_REG_INT_XLMIB_RMGV_BCM53570_A0r */
  30630         soc_block_list[16],
  30631         soc_portreg,
  30632         1,
  30633         0,
  30634         0x600,
  30635         SOC_REG_FLAG_64_BITS |
  30636                           SOC_REG_FLAG_COUNTER,
  30637         0,
  30638         1,
  30639         soc_R1023_BCM53400_A0r_fields,
  30640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30641         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30642         160,
  30643         -1,
  30644     },
  30645 #endif /* chips */
  30646 
  30647 #if defined(BCM_53570_B0)
  30648     { /* SOC_REG_INT_XLMIB_RMGV_BCM53570_B0r */
  30649         soc_block_list[16],
  30650         soc_portreg,
  30651         1,
  30652         0,
  30653         0x600,
  30654         SOC_REG_FLAG_64_BITS |
  30655                           SOC_REG_FLAG_COUNTER,
  30656         0,
  30657         1,
  30658         soc_R1023_BCM53400_A0r_fields,
  30659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30660         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30661         164,
  30662         -1,
  30663     },
  30664 #endif /* chips */
  30665 
  30666 #if defined(BCM_56370_A0)
  30667     { /* SOC_REG_INT_XLMIB_RMGV_BCM56370_A0r */
  30668         soc_block_list[16],
  30669         soc_portreg,
  30670         1,
  30671         0,
  30672         0x600,
  30673         SOC_REG_FLAG_64_BITS |
  30674                           SOC_REG_FLAG_COUNTER,
  30675         0,
  30676         1,
  30677         soc_R1023_BCM53400_A0r_fields,
  30678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30679         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30680         66,
  30681         -1,
  30682         3,
  30683     },
  30684 #endif /* chips */
  30685 
  30686 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  30687     { /* SOC_REG_INT_XLMIB_RMGV_BCM56980_A0r */
  30688         soc_block_list[16],
  30689         soc_portreg,
  30690         1,
  30691         0,
  30692         0x600,
  30693         SOC_REG_FLAG_64_BITS |
  30694                           SOC_REG_FLAG_COUNTER,
  30695         0,
  30696         1,
  30697         soc_R1023_BCM53400_A0r_fields,
  30698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30700         41,
  30701         -1,
  30702         3,
  30703     },
  30704 #endif /* chips */
  30705 
  30706 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30707     { /* SOC_REG_INT_XLMIB_RMTUEr */
  30708         soc_block_list[16],
  30709         soc_portreg,
  30710         1,
  30711         0,
  30712         0x1c00,
  30713         SOC_REG_FLAG_64_BITS |
  30714                           SOC_REG_FLAG_COUNTER |
  30715                           SOC_REG_FLAG_ED_CNTR,
  30716         0,
  30717         1,
  30718         soc_R1023_BCM53400_A0r_fields,
  30719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30720         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30721         87,
  30722         -1,
  30723         3,
  30724     },
  30725 #endif /* chips */
  30726 
  30727 #if defined(BCM_53570_A0)
  30728     { /* SOC_REG_INT_XLMIB_RMTUE_BCM53570_A0r */
  30729         soc_block_list[16],
  30730         soc_portreg,
  30731         1,
  30732         0,
  30733         0x1c00,
  30734         SOC_REG_FLAG_64_BITS |
  30735                           SOC_REG_FLAG_COUNTER |
  30736                           SOC_REG_FLAG_ED_CNTR,
  30737         0,
  30738         1,
  30739         soc_R1023_BCM53400_A0r_fields,
  30740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30741         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30742         182,
  30743         -1,
  30744     },
  30745 #endif /* chips */
  30746 
  30747 #if defined(BCM_53570_B0)
  30748     { /* SOC_REG_INT_XLMIB_RMTUE_BCM53570_B0r */
  30749         soc_block_list[16],
  30750         soc_portreg,
  30751         1,
  30752         0,
  30753         0x1c00,
  30754         SOC_REG_FLAG_64_BITS |
  30755                           SOC_REG_FLAG_COUNTER |
  30756                           SOC_REG_FLAG_ED_CNTR,
  30757         0,
  30758         1,
  30759         soc_R1023_BCM53400_A0r_fields,
  30760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30762         186,
  30763         -1,
  30764     },
  30765 #endif /* chips */
  30766 
  30767 #if defined(BCM_56370_A0)
  30768     { /* SOC_REG_INT_XLMIB_RMTUE_BCM56370_A0r */
  30769         soc_block_list[16],
  30770         soc_portreg,
  30771         1,
  30772         0,
  30773         0x1c00,
  30774         SOC_REG_FLAG_64_BITS |
  30775                           SOC_REG_FLAG_COUNTER |
  30776                           SOC_REG_FLAG_ED_CNTR,
  30777         0,
  30778         1,
  30779         soc_R1023_BCM53400_A0r_fields,
  30780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30782         88,
  30783         -1,
  30784         3,
  30785     },
  30786 #endif /* chips */
  30787 
  30788 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  30789     { /* SOC_REG_INT_XLMIB_RMTUE_BCM56980_A0r */
  30790         soc_block_list[16],
  30791         soc_portreg,
  30792         1,
  30793         0,
  30794         0x1c00,
  30795         SOC_REG_FLAG_64_BITS |
  30796                           SOC_REG_FLAG_COUNTER |
  30797                           SOC_REG_FLAG_ED_CNTR,
  30798         0,
  30799         1,
  30800         soc_R1023_BCM53400_A0r_fields,
  30801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30802         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30803         63,
  30804         -1,
  30805         3,
  30806     },
  30807 #endif /* chips */
  30808 
  30809 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30810     { /* SOC_REG_INT_XLMIB_ROVRr */
  30811         soc_block_list[16],
  30812         soc_portreg,
  30813         1,
  30814         0,
  30815         0x1a00,
  30816         SOC_REG_FLAG_64_BITS |
  30817                           SOC_REG_FLAG_COUNTER |
  30818                           SOC_REG_FLAG_ED_CNTR,
  30819         0,
  30820         1,
  30821         soc_R1023_BCM53400_A0r_fields,
  30822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30823         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30824         85,
  30825         -1,
  30826         3,
  30827     },
  30828 #endif /* chips */
  30829 
  30830 #if defined(BCM_53570_A0)
  30831     { /* SOC_REG_INT_XLMIB_ROVR_BCM53570_A0r */
  30832         soc_block_list[16],
  30833         soc_portreg,
  30834         1,
  30835         0,
  30836         0x1a00,
  30837         SOC_REG_FLAG_64_BITS |
  30838                           SOC_REG_FLAG_COUNTER |
  30839                           SOC_REG_FLAG_ED_CNTR,
  30840         0,
  30841         1,
  30842         soc_R1023_BCM53400_A0r_fields,
  30843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30844         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30845         180,
  30846         -1,
  30847     },
  30848 #endif /* chips */
  30849 
  30850 #if defined(BCM_53570_B0)
  30851     { /* SOC_REG_INT_XLMIB_ROVR_BCM53570_B0r */
  30852         soc_block_list[16],
  30853         soc_portreg,
  30854         1,
  30855         0,
  30856         0x1a00,
  30857         SOC_REG_FLAG_64_BITS |
  30858                           SOC_REG_FLAG_COUNTER |
  30859                           SOC_REG_FLAG_ED_CNTR,
  30860         0,
  30861         1,
  30862         soc_R1023_BCM53400_A0r_fields,
  30863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30864         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30865         184,
  30866         -1,
  30867     },
  30868 #endif /* chips */
  30869 
  30870 #if defined(BCM_56370_A0)
  30871     { /* SOC_REG_INT_XLMIB_ROVR_BCM56370_A0r */
  30872         soc_block_list[16],
  30873         soc_portreg,
  30874         1,
  30875         0,
  30876         0x1a00,
  30877         SOC_REG_FLAG_64_BITS |
  30878                           SOC_REG_FLAG_COUNTER |
  30879                           SOC_REG_FLAG_ED_CNTR,
  30880         0,
  30881         1,
  30882         soc_R1023_BCM53400_A0r_fields,
  30883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30884         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30885         86,
  30886         -1,
  30887         3,
  30888     },
  30889 #endif /* chips */
  30890 
  30891 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  30892     { /* SOC_REG_INT_XLMIB_ROVR_BCM56980_A0r */
  30893         soc_block_list[16],
  30894         soc_portreg,
  30895         1,
  30896         0,
  30897         0x1a00,
  30898         SOC_REG_FLAG_64_BITS |
  30899                           SOC_REG_FLAG_COUNTER |
  30900                           SOC_REG_FLAG_ED_CNTR,
  30901         0,
  30902         1,
  30903         soc_R1023_BCM53400_A0r_fields,
  30904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30905         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30906         61,
  30907         -1,
  30908         3,
  30909     },
  30910 #endif /* chips */
  30911 
  30912 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30913     { /* SOC_REG_INT_XLMIB_RPFC0r */
  30914         soc_block_list[16],
  30915         soc_portreg,
  30916         1,
  30917         0,
  30918         0x2b00,
  30919         SOC_REG_FLAG_64_BITS |
  30920                           SOC_REG_FLAG_COUNTER,
  30921         0,
  30922         1,
  30923         soc_R1023_BCM53400_A0r_fields,
  30924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30926         102,
  30927         -1,
  30928         3,
  30929     },
  30930 #endif /* chips */
  30931 
  30932 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30933     { /* SOC_REG_INT_XLMIB_RPFC1r */
  30934         soc_block_list[16],
  30935         soc_portreg,
  30936         1,
  30937         0,
  30938         0x2c00,
  30939         SOC_REG_FLAG_64_BITS |
  30940                           SOC_REG_FLAG_COUNTER,
  30941         0,
  30942         1,
  30943         soc_R1023_BCM53400_A0r_fields,
  30944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30945         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30946         103,
  30947         -1,
  30948         3,
  30949     },
  30950 #endif /* chips */
  30951 
  30952 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30953     { /* SOC_REG_INT_XLMIB_RPFC2r */
  30954         soc_block_list[16],
  30955         soc_portreg,
  30956         1,
  30957         0,
  30958         0x2d00,
  30959         SOC_REG_FLAG_64_BITS |
  30960                           SOC_REG_FLAG_COUNTER,
  30961         0,
  30962         1,
  30963         soc_R1023_BCM53400_A0r_fields,
  30964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30965         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30966         104,
  30967         -1,
  30968         3,
  30969     },
  30970 #endif /* chips */
  30971 
  30972 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30973     { /* SOC_REG_INT_XLMIB_RPFC3r */
  30974         soc_block_list[16],
  30975         soc_portreg,
  30976         1,
  30977         0,
  30978         0x2e00,
  30979         SOC_REG_FLAG_64_BITS |
  30980                           SOC_REG_FLAG_COUNTER,
  30981         0,
  30982         1,
  30983         soc_R1023_BCM53400_A0r_fields,
  30984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30985         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30986         105,
  30987         -1,
  30988         3,
  30989     },
  30990 #endif /* chips */
  30991 
  30992 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  30993     { /* SOC_REG_INT_XLMIB_RPFC4r */
  30994         soc_block_list[16],
  30995         soc_portreg,
  30996         1,
  30997         0,
  30998         0x2f00,
  30999         SOC_REG_FLAG_64_BITS |
  31000                           SOC_REG_FLAG_COUNTER,
  31001         0,
  31002         1,
  31003         soc_R1023_BCM53400_A0r_fields,
  31004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31006         106,
  31007         -1,
  31008         3,
  31009     },
  31010 #endif /* chips */
  31011 
  31012 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  31013     { /* SOC_REG_INT_XLMIB_RPFC5r */
  31014         soc_block_list[16],
  31015         soc_portreg,
  31016         1,
  31017         0,
  31018         0x3000,
  31019         SOC_REG_FLAG_64_BITS |
  31020                           SOC_REG_FLAG_COUNTER,
  31021         0,
  31022         1,
  31023         soc_R1023_BCM53400_A0r_fields,
  31024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31025         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31026         107,
  31027         -1,
  31028         3,
  31029     },
  31030 #endif /* chips */
  31031 
  31032 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  31033     { /* SOC_REG_INT_XLMIB_RPFC6r */
  31034         soc_block_list[16],
  31035         soc_portreg,
  31036         1,
  31037         0,
  31038         0x3100,
  31039         SOC_REG_FLAG_64_BITS |
  31040                           SOC_REG_FLAG_COUNTER,
  31041         0,
  31042         1,
  31043         soc_R1023_BCM53400_A0r_fields,
  31044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31045         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31046         108,
  31047         -1,
  31048         3,
  31049     },
  31050 #endif /* chips */
  31051 
  31052 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  31053     { /* SOC_REG_INT_XLMIB_RPFC7r */
  31054         soc_block_list[16],
  31055         soc_portreg,
  31056         1,
  31057         0,
  31058         0x3200,
  31059         SOC_REG_FLAG_64_BITS |
  31060                           SOC_REG_FLAG_COUNTER,
  31061         0,
  31062         1,
  31063         soc_R1023_BCM53400_A0r_fields,
  31064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31065         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31066         109,
  31067         -1,
  31068         3,
  31069     },
  31070 #endif /* chips */
  31071 
  31072 #if defined(BCM_53570_A0)
  31073     { /* SOC_REG_INT_XLMIB_RPFC0_BCM53570_A0r */
  31074         soc_block_list[16],
  31075         soc_portreg,
  31076         1,
  31077         0,
  31078         0x2b00,
  31079         SOC_REG_FLAG_64_BITS |
  31080                           SOC_REG_FLAG_COUNTER,
  31081         0,
  31082         1,
  31083         soc_R1023_BCM53400_A0r_fields,
  31084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31085         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31086         197,
  31087         -1,
  31088     },
  31089 #endif /* chips */
  31090 
  31091 #if defined(BCM_53570_B0)
  31092     { /* SOC_REG_INT_XLMIB_RPFC0_BCM53570_B0r */
  31093         soc_block_list[16],
  31094         soc_portreg,
  31095         1,
  31096         0,
  31097         0x2b00,
  31098         SOC_REG_FLAG_64_BITS |
  31099                           SOC_REG_FLAG_COUNTER,
  31100         0,
  31101         1,
  31102         soc_R1023_BCM53400_A0r_fields,
  31103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31105         201,
  31106         -1,
  31107     },
  31108 #endif /* chips */
  31109 
  31110 #if defined(BCM_56370_A0)
  31111     { /* SOC_REG_INT_XLMIB_RPFC0_BCM56370_A0r */
  31112         soc_block_list[16],
  31113         soc_portreg,
  31114         1,
  31115         0,
  31116         0x2b00,
  31117         SOC_REG_FLAG_64_BITS |
  31118                           SOC_REG_FLAG_COUNTER,
  31119         0,
  31120         1,
  31121         soc_R1023_BCM53400_A0r_fields,
  31122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31124         103,
  31125         -1,
  31126         3,
  31127     },
  31128 #endif /* chips */
  31129 
  31130 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  31131     { /* SOC_REG_INT_XLMIB_RPFC0_BCM56980_A0r */
  31132         soc_block_list[16],
  31133         soc_portreg,
  31134         1,
  31135         0,
  31136         0x2b00,
  31137         SOC_REG_FLAG_64_BITS |
  31138                           SOC_REG_FLAG_COUNTER,
  31139         0,
  31140         1,
  31141         soc_R1023_BCM53400_A0r_fields,
  31142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31143         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31144         78,
  31145         -1,
  31146         3,
  31147     },
  31148 #endif /* chips */
  31149 
  31150 #if defined(BCM_53570_A0)
  31151     { /* SOC_REG_INT_XLMIB_RPFC1_BCM53570_A0r */
  31152         soc_block_list[16],
  31153         soc_portreg,
  31154         1,
  31155         0,
  31156         0x2c00,
  31157         SOC_REG_FLAG_64_BITS |
  31158                           SOC_REG_FLAG_COUNTER,
  31159         0,
  31160         1,
  31161         soc_R1023_BCM53400_A0r_fields,
  31162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31163         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31164         198,
  31165         -1,
  31166     },
  31167 #endif /* chips */
  31168 
  31169 #if defined(BCM_53570_B0)
  31170     { /* SOC_REG_INT_XLMIB_RPFC1_BCM53570_B0r */
  31171         soc_block_list[16],
  31172         soc_portreg,
  31173         1,
  31174         0,
  31175         0x2c00,
  31176         SOC_REG_FLAG_64_BITS |
  31177                           SOC_REG_FLAG_COUNTER,
  31178         0,
  31179         1,
  31180         soc_R1023_BCM53400_A0r_fields,
  31181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31182         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31183         202,
  31184         -1,
  31185     },
  31186 #endif /* chips */
  31187 
  31188 #if defined(BCM_56370_A0)
  31189     { /* SOC_REG_INT_XLMIB_RPFC1_BCM56370_A0r */
  31190         soc_block_list[16],
  31191         soc_portreg,
  31192         1,
  31193         0,
  31194         0x2c00,
  31195         SOC_REG_FLAG_64_BITS |
  31196                           SOC_REG_FLAG_COUNTER,
  31197         0,
  31198         1,
  31199         soc_R1023_BCM53400_A0r_fields,
  31200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31201         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31202         104,
  31203         -1,
  31204         3,
  31205     },
  31206 #endif /* chips */
  31207 
  31208 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  31209     { /* SOC_REG_INT_XLMIB_RPFC1_BCM56980_A0r */
  31210         soc_block_list[16],
  31211         soc_portreg,
  31212         1,
  31213         0,
  31214         0x2c00,
  31215         SOC_REG_FLAG_64_BITS |
  31216                           SOC_REG_FLAG_COUNTER,
  31217         0,
  31218         1,
  31219         soc_R1023_BCM53400_A0r_fields,
  31220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31221         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31222         79,
  31223         -1,
  31224         3,
  31225     },
  31226 #endif /* chips */
  31227 
  31228 #if defined(BCM_53570_A0)
  31229     { /* SOC_REG_INT_XLMIB_RPFC2_BCM53570_A0r */
  31230         soc_block_list[16],
  31231         soc_portreg,
  31232         1,
  31233         0,
  31234         0x2d00,
  31235         SOC_REG_FLAG_64_BITS |
  31236                           SOC_REG_FLAG_COUNTER,
  31237         0,
  31238         1,
  31239         soc_R1023_BCM53400_A0r_fields,
  31240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31241         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31242         199,
  31243         -1,
  31244     },
  31245 #endif /* chips */
  31246 
  31247 #if defined(BCM_53570_B0)
  31248     { /* SOC_REG_INT_XLMIB_RPFC2_BCM53570_B0r */
  31249         soc_block_list[16],
  31250         soc_portreg,
  31251         1,
  31252         0,
  31253         0x2d00,
  31254         SOC_REG_FLAG_64_BITS |
  31255                           SOC_REG_FLAG_COUNTER,
  31256         0,
  31257         1,
  31258         soc_R1023_BCM53400_A0r_fields,
  31259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31260         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31261         203,
  31262         -1,
  31263     },
  31264 #endif /* chips */
  31265 
  31266 #if defined(BCM_56370_A0)
  31267     { /* SOC_REG_INT_XLMIB_RPFC2_BCM56370_A0r */
  31268         soc_block_list[16],
  31269         soc_portreg,
  31270         1,
  31271         0,
  31272         0x2d00,
  31273         SOC_REG_FLAG_64_BITS |
  31274                           SOC_REG_FLAG_COUNTER,
  31275         0,
  31276         1,
  31277         soc_R1023_BCM53400_A0r_fields,
  31278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31279         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31280         105,
  31281         -1,
  31282         3,
  31283     },
  31284 #endif /* chips */
  31285 
  31286 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  31287     { /* SOC_REG_INT_XLMIB_RPFC2_BCM56980_A0r */
  31288         soc_block_list[16],
  31289         soc_portreg,
  31290         1,
  31291         0,
  31292         0x2d00,
  31293         SOC_REG_FLAG_64_BITS |
  31294                           SOC_REG_FLAG_COUNTER,
  31295         0,
  31296         1,
  31297         soc_R1023_BCM53400_A0r_fields,
  31298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31300         80,
  31301         -1,
  31302         3,
  31303     },
  31304 #endif /* chips */
  31305 
  31306 #if defined(BCM_53570_A0)
  31307     { /* SOC_REG_INT_XLMIB_RPFC3_BCM53570_A0r */
  31308         soc_block_list[16],
  31309         soc_portreg,
  31310         1,
  31311         0,
  31312         0x2e00,
  31313         SOC_REG_FLAG_64_BITS |
  31314                           SOC_REG_FLAG_COUNTER,
  31315         0,
  31316         1,
  31317         soc_R1023_BCM53400_A0r_fields,
  31318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31319         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31320         200,
  31321         -1,
  31322     },
  31323 #endif /* chips */
  31324 
  31325 #if defined(BCM_53570_B0)
  31326     { /* SOC_REG_INT_XLMIB_RPFC3_BCM53570_B0r */
  31327         soc_block_list[16],
  31328         soc_portreg,
  31329         1,
  31330         0,
  31331         0x2e00,
  31332         SOC_REG_FLAG_64_BITS |
  31333                           SOC_REG_FLAG_COUNTER,
  31334         0,
  31335         1,
  31336         soc_R1023_BCM53400_A0r_fields,
  31337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31339         204,
  31340         -1,
  31341     },
  31342 #endif /* chips */
  31343 
  31344 #if defined(BCM_56370_A0)
  31345     { /* SOC_REG_INT_XLMIB_RPFC3_BCM56370_A0r */
  31346         soc_block_list[16],
  31347         soc_portreg,
  31348         1,
  31349         0,
  31350         0x2e00,
  31351         SOC_REG_FLAG_64_BITS |
  31352                           SOC_REG_FLAG_COUNTER,
  31353         0,
  31354         1,
  31355         soc_R1023_BCM53400_A0r_fields,
  31356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31357         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31358         106,
  31359         -1,
  31360         3,
  31361     },
  31362 #endif /* chips */
  31363 
  31364 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  31365     { /* SOC_REG_INT_XLMIB_RPFC3_BCM56980_A0r */
  31366         soc_block_list[16],
  31367         soc_portreg,
  31368         1,
  31369         0,
  31370         0x2e00,
  31371         SOC_REG_FLAG_64_BITS |
  31372                           SOC_REG_FLAG_COUNTER,
  31373         0,
  31374         1,
  31375         soc_R1023_BCM53400_A0r_fields,
  31376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31377         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31378         81,
  31379         -1,
  31380         3,
  31381     },
  31382 #endif /* chips */
  31383 
  31384 #if defined(BCM_53570_A0)
  31385     { /* SOC_REG_INT_XLMIB_RPFC4_BCM53570_A0r */
  31386         soc_block_list[16],
  31387         soc_portreg,
  31388         1,
  31389         0,
  31390         0x2f00,
  31391         SOC_REG_FLAG_64_BITS |
  31392                           SOC_REG_FLAG_COUNTER,
  31393         0,
  31394         1,
  31395         soc_R1023_BCM53400_A0r_fields,
  31396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31397         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31398         201,
  31399         -1,
  31400     },
  31401 #endif /* chips */
  31402 
  31403 #if defined(BCM_53570_B0)
  31404     { /* SOC_REG_INT_XLMIB_RPFC4_BCM53570_B0r */
  31405         soc_block_list[16],
  31406         soc_portreg,
  31407         1,
  31408         0,
  31409         0x2f00,
  31410         SOC_REG_FLAG_64_BITS |
  31411                           SOC_REG_FLAG_COUNTER,
  31412         0,
  31413         1,
  31414         soc_R1023_BCM53400_A0r_fields,
  31415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31416         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31417         205,
  31418         -1,
  31419     },
  31420 #endif /* chips */
  31421 
  31422 #if defined(BCM_56370_A0)
  31423     { /* SOC_REG_INT_XLMIB_RPFC4_BCM56370_A0r */
  31424         soc_block_list[16],
  31425         soc_portreg,
  31426         1,
  31427         0,
  31428         0x2f00,
  31429         SOC_REG_FLAG_64_BITS |
  31430                           SOC_REG_FLAG_COUNTER,
  31431         0,
  31432         1,
  31433         soc_R1023_BCM53400_A0r_fields,
  31434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31435         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31436         107,
  31437         -1,
  31438         3,
  31439     },
  31440 #endif /* chips */
  31441 
  31442 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  31443     { /* SOC_REG_INT_XLMIB_RPFC4_BCM56980_A0r */
  31444         soc_block_list[16],
  31445         soc_portreg,
  31446         1,
  31447         0,
  31448         0x2f00,
  31449         SOC_REG_FLAG_64_BITS |
  31450                           SOC_REG_FLAG_COUNTER,
  31451         0,
  31452         1,
  31453         soc_R1023_BCM53400_A0r_fields,
  31454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31455         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31456         82,
  31457         -1,
  31458         3,
  31459     },
  31460 #endif /* chips */
  31461 
  31462 #if defined(BCM_53570_A0)
  31463     { /* SOC_REG_INT_XLMIB_RPFC5_BCM53570_A0r */
  31464         soc_block_list[16],
  31465         soc_portreg,
  31466         1,
  31467         0,
  31468         0x3000,
  31469         SOC_REG_FLAG_64_BITS |
  31470                           SOC_REG_FLAG_COUNTER,
  31471         0,
  31472         1,
  31473         soc_R1023_BCM53400_A0r_fields,
  31474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31475         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31476         202,
  31477         -1,
  31478     },
  31479 #endif /* chips */
  31480 
  31481 #if defined(BCM_53570_B0)
  31482     { /* SOC_REG_INT_XLMIB_RPFC5_BCM53570_B0r */
  31483         soc_block_list[16],
  31484         soc_portreg,
  31485         1,
  31486         0,
  31487         0x3000,
  31488         SOC_REG_FLAG_64_BITS |
  31489                           SOC_REG_FLAG_COUNTER,
  31490         0,
  31491         1,
  31492         soc_R1023_BCM53400_A0r_fields,
  31493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31494         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31495         206,
  31496         -1,
  31497     },
  31498 #endif /* chips */
  31499 
  31500 #if defined(BCM_56370_A0)
  31501     { /* SOC_REG_INT_XLMIB_RPFC5_BCM56370_A0r */
  31502         soc_block_list[16],
  31503         soc_portreg,
  31504         1,
  31505         0,
  31506         0x3000,
  31507         SOC_REG_FLAG_64_BITS |
  31508                           SOC_REG_FLAG_COUNTER,
  31509         0,
  31510         1,
  31511         soc_R1023_BCM53400_A0r_fields,
  31512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31514         108,
  31515         -1,
  31516         3,
  31517     },
  31518 #endif /* chips */
  31519 
  31520 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  31521     { /* SOC_REG_INT_XLMIB_RPFC5_BCM56980_A0r */
  31522         soc_block_list[16],
  31523         soc_portreg,
  31524         1,
  31525         0,
  31526         0x3000,
  31527         SOC_REG_FLAG_64_BITS |
  31528                           SOC_REG_FLAG_COUNTER,
  31529         0,
  31530         1,
  31531         soc_R1023_BCM53400_A0r_fields,
  31532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31533         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31534         83,
  31535         -1,
  31536         3,
  31537     },
  31538 #endif /* chips */
  31539 
  31540 #if defined(BCM_53570_A0)
  31541     { /* SOC_REG_INT_XLMIB_RPFC6_BCM53570_A0r */
  31542         soc_block_list[16],
  31543         soc_portreg,
  31544         1,
  31545         0,
  31546         0x3100,
  31547         SOC_REG_FLAG_64_BITS |
  31548                           SOC_REG_FLAG_COUNTER,
  31549         0,
  31550         1,
  31551         soc_R1023_BCM53400_A0r_fields,
  31552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31553         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31554         203,
  31555         -1,
  31556     },
  31557 #endif /* chips */
  31558 
  31559 #if defined(BCM_53570_B0)
  31560     { /* SOC_REG_INT_XLMIB_RPFC6_BCM53570_B0r */
  31561         soc_block_list[16],
  31562         soc_portreg,
  31563         1,
  31564         0,
  31565         0x3100,
  31566         SOC_REG_FLAG_64_BITS |
  31567                           SOC_REG_FLAG_COUNTER,
  31568         0,
  31569         1,
  31570         soc_R1023_BCM53400_A0r_fields,
  31571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31572         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31573         207,
  31574         -1,
  31575     },
  31576 #endif /* chips */
  31577 
  31578 #if defined(BCM_56370_A0)
  31579     { /* SOC_REG_INT_XLMIB_RPFC6_BCM56370_A0r */
  31580         soc_block_list[16],
  31581         soc_portreg,
  31582         1,
  31583         0,
  31584         0x3100,
  31585         SOC_REG_FLAG_64_BITS |
  31586                           SOC_REG_FLAG_COUNTER,
  31587         0,
  31588         1,
  31589         soc_R1023_BCM53400_A0r_fields,
  31590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31592         109,
  31593         -1,
  31594         3,
  31595     },
  31596 #endif /* chips */
  31597 
  31598 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  31599     { /* SOC_REG_INT_XLMIB_RPFC6_BCM56980_A0r */
  31600         soc_block_list[16],
  31601         soc_portreg,
  31602         1,
  31603         0,
  31604         0x3100,
  31605         SOC_REG_FLAG_64_BITS |
  31606                           SOC_REG_FLAG_COUNTER,
  31607         0,
  31608         1,
  31609         soc_R1023_BCM53400_A0r_fields,
  31610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31612         84,
  31613         -1,
  31614         3,
  31615     },
  31616 #endif /* chips */
  31617 
  31618 #if defined(BCM_53570_A0)
  31619     { /* SOC_REG_INT_XLMIB_RPFC7_BCM53570_A0r */
  31620         soc_block_list[16],
  31621         soc_portreg,
  31622         1,
  31623         0,
  31624         0x3200,
  31625         SOC_REG_FLAG_64_BITS |
  31626                           SOC_REG_FLAG_COUNTER,
  31627         0,
  31628         1,
  31629         soc_R1023_BCM53400_A0r_fields,
  31630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31632         204,
  31633         -1,
  31634     },
  31635 #endif /* chips */
  31636 
  31637 #if defined(BCM_53570_B0)
  31638     { /* SOC_REG_INT_XLMIB_RPFC7_BCM53570_B0r */
  31639         soc_block_list[16],
  31640         soc_portreg,
  31641         1,
  31642         0,
  31643         0x3200,
  31644         SOC_REG_FLAG_64_BITS |
  31645                           SOC_REG_FLAG_COUNTER,
  31646         0,
  31647         1,
  31648         soc_R1023_BCM53400_A0r_fields,
  31649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31650         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31651         208,
  31652         -1,
  31653     },
  31654 #endif /* chips */
  31655 
  31656 #if defined(BCM_56370_A0)
  31657     { /* SOC_REG_INT_XLMIB_RPFC7_BCM56370_A0r */
  31658         soc_block_list[16],
  31659         soc_portreg,
  31660         1,
  31661         0,
  31662         0x3200,
  31663         SOC_REG_FLAG_64_BITS |
  31664                           SOC_REG_FLAG_COUNTER,
  31665         0,
  31666         1,
  31667         soc_R1023_BCM53400_A0r_fields,
  31668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31670         110,
  31671         -1,
  31672         3,
  31673     },
  31674 #endif /* chips */
  31675 
  31676 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  31677     { /* SOC_REG_INT_XLMIB_RPFC7_BCM56980_A0r */
  31678         soc_block_list[16],
  31679         soc_portreg,
  31680         1,
  31681         0,
  31682         0x3200,
  31683         SOC_REG_FLAG_64_BITS |
  31684                           SOC_REG_FLAG_COUNTER,
  31685         0,
  31686         1,
  31687         soc_R1023_BCM53400_A0r_fields,
  31688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31689         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31690         85,
  31691         -1,
  31692         3,
  31693     },
  31694 #endif /* chips */
  31695 
  31696 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  31697     { /* SOC_REG_INT_XLMIB_RPFCOFF0r */
  31698         soc_block_list[16],
  31699         soc_portreg,
  31700         1,
  31701         0,
  31702         0x2300,
  31703         SOC_REG_FLAG_64_BITS |
  31704                           SOC_REG_FLAG_COUNTER,
  31705         0,
  31706         1,
  31707         soc_R1023_BCM53400_A0r_fields,
  31708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31709         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31710         94,
  31711         -1,
  31712         3,
  31713     },
  31714 #endif /* chips */
  31715 
  31716 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  31717     { /* SOC_REG_INT_XLMIB_RPFCOFF1r */
  31718         soc_block_list[16],
  31719         soc_portreg,
  31720         1,
  31721         0,
  31722         0x2400,
  31723         SOC_REG_FLAG_64_BITS |
  31724                           SOC_REG_FLAG_COUNTER,
  31725         0,
  31726         1,
  31727         soc_R1023_BCM53400_A0r_fields,
  31728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31729         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31730         95,
  31731         -1,
  31732         3,
  31733     },
  31734 #endif /* chips */
  31735 
  31736 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  31737     { /* SOC_REG_INT_XLMIB_RPFCOFF2r */
  31738         soc_block_list[16],
  31739         soc_portreg,
  31740         1,
  31741         0,
  31742         0x2500,
  31743         SOC_REG_FLAG_64_BITS |
  31744                           SOC_REG_FLAG_COUNTER,
  31745         0,
  31746         1,
  31747         soc_R1023_BCM53400_A0r_fields,
  31748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31749         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31750         96,
  31751         -1,
  31752         3,
  31753     },
  31754 #endif /* chips */
  31755 
  31756 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  31757     { /* SOC_REG_INT_XLMIB_RPFCOFF3r */
  31758         soc_block_list[16],
  31759         soc_portreg,
  31760         1,
  31761         0,
  31762         0x2600,
  31763         SOC_REG_FLAG_64_BITS |
  31764                           SOC_REG_FLAG_COUNTER,
  31765         0,
  31766         1,
  31767         soc_R1023_BCM53400_A0r_fields,
  31768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31769         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31770         97,
  31771         -1,
  31772         3,
  31773     },
  31774 #endif /* chips */
  31775 
  31776 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  31777     { /* SOC_REG_INT_XLMIB_RPFCOFF4r */
  31778         soc_block_list[16],
  31779         soc_portreg,
  31780         1,
  31781         0,
  31782         0x2700,
  31783         SOC_REG_FLAG_64_BITS |
  31784                           SOC_REG_FLAG_COUNTER,
  31785         0,
  31786         1,
  31787         soc_R1023_BCM53400_A0r_fields,
  31788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31790         98,
  31791         -1,
  31792         3,
  31793     },
  31794 #endif /* chips */
  31795 
  31796 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  31797     { /* SOC_REG_INT_XLMIB_RPFCOFF5r */
  31798         soc_block_list[16],
  31799         soc_portreg,
  31800         1,
  31801         0,
  31802         0x2800,
  31803         SOC_REG_FLAG_64_BITS |
  31804                           SOC_REG_FLAG_COUNTER,
  31805         0,
  31806         1,
  31807         soc_R1023_BCM53400_A0r_fields,
  31808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31809         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31810         99,
  31811         -1,
  31812         3,
  31813     },
  31814 #endif /* chips */
  31815 
  31816 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  31817     { /* SOC_REG_INT_XLMIB_RPFCOFF6r */
  31818         soc_block_list[16],
  31819         soc_portreg,
  31820         1,
  31821         0,
  31822         0x2900,
  31823         SOC_REG_FLAG_64_BITS |
  31824                           SOC_REG_FLAG_COUNTER,
  31825         0,
  31826         1,
  31827         soc_R1023_BCM53400_A0r_fields,
  31828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31829         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31830         100,
  31831         -1,
  31832         3,
  31833     },
  31834 #endif /* chips */
  31835 
  31836 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  31837     { /* SOC_REG_INT_XLMIB_RPFCOFF7r */
  31838         soc_block_list[16],
  31839         soc_portreg,
  31840         1,
  31841         0,
  31842         0x2a00,
  31843         SOC_REG_FLAG_64_BITS |
  31844                           SOC_REG_FLAG_COUNTER,
  31845         0,
  31846         1,
  31847         soc_R1023_BCM53400_A0r_fields,
  31848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31849         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31850         101,
  31851         -1,
  31852         3,
  31853     },
  31854 #endif /* chips */
  31855 
  31856 #if defined(BCM_53570_A0)
  31857     { /* SOC_REG_INT_XLMIB_RPFCOFF0_BCM53570_A0r */
  31858         soc_block_list[16],
  31859         soc_portreg,
  31860         1,
  31861         0,
  31862         0x2300,
  31863         SOC_REG_FLAG_64_BITS |
  31864                           SOC_REG_FLAG_COUNTER,
  31865         0,
  31866         1,
  31867         soc_R1023_BCM53400_A0r_fields,
  31868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31869         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31870         189,
  31871         -1,
  31872     },
  31873 #endif /* chips */
  31874 
  31875 #if defined(BCM_53570_B0)
  31876     { /* SOC_REG_INT_XLMIB_RPFCOFF0_BCM53570_B0r */
  31877         soc_block_list[16],
  31878         soc_portreg,
  31879         1,
  31880         0,
  31881         0x2300,
  31882         SOC_REG_FLAG_64_BITS |
  31883                           SOC_REG_FLAG_COUNTER,
  31884         0,
  31885         1,
  31886         soc_R1023_BCM53400_A0r_fields,
  31887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31888         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31889         193,
  31890         -1,
  31891     },
  31892 #endif /* chips */
  31893 
  31894 #if defined(BCM_56370_A0)
  31895     { /* SOC_REG_INT_XLMIB_RPFCOFF0_BCM56370_A0r */
  31896         soc_block_list[16],
  31897         soc_portreg,
  31898         1,
  31899         0,
  31900         0x2300,
  31901         SOC_REG_FLAG_64_BITS |
  31902                           SOC_REG_FLAG_COUNTER,
  31903         0,
  31904         1,
  31905         soc_R1023_BCM53400_A0r_fields,
  31906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31907         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31908         95,
  31909         -1,
  31910         3,
  31911     },
  31912 #endif /* chips */
  31913 
  31914 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  31915     { /* SOC_REG_INT_XLMIB_RPFCOFF0_BCM56980_A0r */
  31916         soc_block_list[16],
  31917         soc_portreg,
  31918         1,
  31919         0,
  31920         0x2300,
  31921         SOC_REG_FLAG_64_BITS |
  31922                           SOC_REG_FLAG_COUNTER,
  31923         0,
  31924         1,
  31925         soc_R1023_BCM53400_A0r_fields,
  31926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31927         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31928         70,
  31929         -1,
  31930         3,
  31931     },
  31932 #endif /* chips */
  31933 
  31934 #if defined(BCM_53570_A0)
  31935     { /* SOC_REG_INT_XLMIB_RPFCOFF1_BCM53570_A0r */
  31936         soc_block_list[16],
  31937         soc_portreg,
  31938         1,
  31939         0,
  31940         0x2400,
  31941         SOC_REG_FLAG_64_BITS |
  31942                           SOC_REG_FLAG_COUNTER,
  31943         0,
  31944         1,
  31945         soc_R1023_BCM53400_A0r_fields,
  31946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31947         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31948         190,
  31949         -1,
  31950     },
  31951 #endif /* chips */
  31952 
  31953 #if defined(BCM_53570_B0)
  31954     { /* SOC_REG_INT_XLMIB_RPFCOFF1_BCM53570_B0r */
  31955         soc_block_list[16],
  31956         soc_portreg,
  31957         1,
  31958         0,
  31959         0x2400,
  31960         SOC_REG_FLAG_64_BITS |
  31961                           SOC_REG_FLAG_COUNTER,
  31962         0,
  31963         1,
  31964         soc_R1023_BCM53400_A0r_fields,
  31965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31966         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31967         194,
  31968         -1,
  31969     },
  31970 #endif /* chips */
  31971 
  31972 #if defined(BCM_56370_A0)
  31973     { /* SOC_REG_INT_XLMIB_RPFCOFF1_BCM56370_A0r */
  31974         soc_block_list[16],
  31975         soc_portreg,
  31976         1,
  31977         0,
  31978         0x2400,
  31979         SOC_REG_FLAG_64_BITS |
  31980                           SOC_REG_FLAG_COUNTER,
  31981         0,
  31982         1,
  31983         soc_R1023_BCM53400_A0r_fields,
  31984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31985         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  31986         96,
  31987         -1,
  31988         3,
  31989     },
  31990 #endif /* chips */
  31991 
  31992 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  31993     { /* SOC_REG_INT_XLMIB_RPFCOFF1_BCM56980_A0r */
  31994         soc_block_list[16],
  31995         soc_portreg,
  31996         1,
  31997         0,
  31998         0x2400,
  31999         SOC_REG_FLAG_64_BITS |
  32000                           SOC_REG_FLAG_COUNTER,
  32001         0,
  32002         1,
  32003         soc_R1023_BCM53400_A0r_fields,
  32004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32006         71,
  32007         -1,
  32008         3,
  32009     },
  32010 #endif /* chips */
  32011 
  32012 #if defined(BCM_53570_A0)
  32013     { /* SOC_REG_INT_XLMIB_RPFCOFF2_BCM53570_A0r */
  32014         soc_block_list[16],
  32015         soc_portreg,
  32016         1,
  32017         0,
  32018         0x2500,
  32019         SOC_REG_FLAG_64_BITS |
  32020                           SOC_REG_FLAG_COUNTER,
  32021         0,
  32022         1,
  32023         soc_R1023_BCM53400_A0r_fields,
  32024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32025         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32026         191,
  32027         -1,
  32028     },
  32029 #endif /* chips */
  32030 
  32031 #if defined(BCM_53570_B0)
  32032     { /* SOC_REG_INT_XLMIB_RPFCOFF2_BCM53570_B0r */
  32033         soc_block_list[16],
  32034         soc_portreg,
  32035         1,
  32036         0,
  32037         0x2500,
  32038         SOC_REG_FLAG_64_BITS |
  32039                           SOC_REG_FLAG_COUNTER,
  32040         0,
  32041         1,
  32042         soc_R1023_BCM53400_A0r_fields,
  32043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32044         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32045         195,
  32046         -1,
  32047     },
  32048 #endif /* chips */
  32049 
  32050 #if defined(BCM_56370_A0)
  32051     { /* SOC_REG_INT_XLMIB_RPFCOFF2_BCM56370_A0r */
  32052         soc_block_list[16],
  32053         soc_portreg,
  32054         1,
  32055         0,
  32056         0x2500,
  32057         SOC_REG_FLAG_64_BITS |
  32058                           SOC_REG_FLAG_COUNTER,
  32059         0,
  32060         1,
  32061         soc_R1023_BCM53400_A0r_fields,
  32062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32064         97,
  32065         -1,
  32066         3,
  32067     },
  32068 #endif /* chips */
  32069 
  32070 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  32071     { /* SOC_REG_INT_XLMIB_RPFCOFF2_BCM56980_A0r */
  32072         soc_block_list[16],
  32073         soc_portreg,
  32074         1,
  32075         0,
  32076         0x2500,
  32077         SOC_REG_FLAG_64_BITS |
  32078                           SOC_REG_FLAG_COUNTER,
  32079         0,
  32080         1,
  32081         soc_R1023_BCM53400_A0r_fields,
  32082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32083         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32084         72,
  32085         -1,
  32086         3,
  32087     },
  32088 #endif /* chips */
  32089 
  32090 #if defined(BCM_53570_A0)
  32091     { /* SOC_REG_INT_XLMIB_RPFCOFF3_BCM53570_A0r */
  32092         soc_block_list[16],
  32093         soc_portreg,
  32094         1,
  32095         0,
  32096         0x2600,
  32097         SOC_REG_FLAG_64_BITS |
  32098                           SOC_REG_FLAG_COUNTER,
  32099         0,
  32100         1,
  32101         soc_R1023_BCM53400_A0r_fields,
  32102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32103         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32104         192,
  32105         -1,
  32106     },
  32107 #endif /* chips */
  32108 
  32109 #if defined(BCM_53570_B0)
  32110     { /* SOC_REG_INT_XLMIB_RPFCOFF3_BCM53570_B0r */
  32111         soc_block_list[16],
  32112         soc_portreg,
  32113         1,
  32114         0,
  32115         0x2600,
  32116         SOC_REG_FLAG_64_BITS |
  32117                           SOC_REG_FLAG_COUNTER,
  32118         0,
  32119         1,
  32120         soc_R1023_BCM53400_A0r_fields,
  32121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32122         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32123         196,
  32124         -1,
  32125     },
  32126 #endif /* chips */
  32127 
  32128 #if defined(BCM_56370_A0)
  32129     { /* SOC_REG_INT_XLMIB_RPFCOFF3_BCM56370_A0r */
  32130         soc_block_list[16],
  32131         soc_portreg,
  32132         1,
  32133         0,
  32134         0x2600,
  32135         SOC_REG_FLAG_64_BITS |
  32136                           SOC_REG_FLAG_COUNTER,
  32137         0,
  32138         1,
  32139         soc_R1023_BCM53400_A0r_fields,
  32140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32141         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32142         98,
  32143         -1,
  32144         3,
  32145     },
  32146 #endif /* chips */
  32147 
  32148 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  32149     { /* SOC_REG_INT_XLMIB_RPFCOFF3_BCM56980_A0r */
  32150         soc_block_list[16],
  32151         soc_portreg,
  32152         1,
  32153         0,
  32154         0x2600,
  32155         SOC_REG_FLAG_64_BITS |
  32156                           SOC_REG_FLAG_COUNTER,
  32157         0,
  32158         1,
  32159         soc_R1023_BCM53400_A0r_fields,
  32160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32161         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32162         73,
  32163         -1,
  32164         3,
  32165     },
  32166 #endif /* chips */
  32167 
  32168 #if defined(BCM_53570_A0)
  32169     { /* SOC_REG_INT_XLMIB_RPFCOFF4_BCM53570_A0r */
  32170         soc_block_list[16],
  32171         soc_portreg,
  32172         1,
  32173         0,
  32174         0x2700,
  32175         SOC_REG_FLAG_64_BITS |
  32176                           SOC_REG_FLAG_COUNTER,
  32177         0,
  32178         1,
  32179         soc_R1023_BCM53400_A0r_fields,
  32180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32182         193,
  32183         -1,
  32184     },
  32185 #endif /* chips */
  32186 
  32187 #if defined(BCM_53570_B0)
  32188     { /* SOC_REG_INT_XLMIB_RPFCOFF4_BCM53570_B0r */
  32189         soc_block_list[16],
  32190         soc_portreg,
  32191         1,
  32192         0,
  32193         0x2700,
  32194         SOC_REG_FLAG_64_BITS |
  32195                           SOC_REG_FLAG_COUNTER,
  32196         0,
  32197         1,
  32198         soc_R1023_BCM53400_A0r_fields,
  32199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32200         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32201         197,
  32202         -1,
  32203     },
  32204 #endif /* chips */
  32205 
  32206 #if defined(BCM_56370_A0)
  32207     { /* SOC_REG_INT_XLMIB_RPFCOFF4_BCM56370_A0r */
  32208         soc_block_list[16],
  32209         soc_portreg,
  32210         1,
  32211         0,
  32212         0x2700,
  32213         SOC_REG_FLAG_64_BITS |
  32214                           SOC_REG_FLAG_COUNTER,
  32215         0,
  32216         1,
  32217         soc_R1023_BCM53400_A0r_fields,
  32218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32219         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32220         99,
  32221         -1,
  32222         3,
  32223     },
  32224 #endif /* chips */
  32225 
  32226 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  32227     { /* SOC_REG_INT_XLMIB_RPFCOFF4_BCM56980_A0r */
  32228         soc_block_list[16],
  32229         soc_portreg,
  32230         1,
  32231         0,
  32232         0x2700,
  32233         SOC_REG_FLAG_64_BITS |
  32234                           SOC_REG_FLAG_COUNTER,
  32235         0,
  32236         1,
  32237         soc_R1023_BCM53400_A0r_fields,
  32238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32239         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32240         74,
  32241         -1,
  32242         3,
  32243     },
  32244 #endif /* chips */
  32245 
  32246 #if defined(BCM_53570_A0)
  32247     { /* SOC_REG_INT_XLMIB_RPFCOFF5_BCM53570_A0r */
  32248         soc_block_list[16],
  32249         soc_portreg,
  32250         1,
  32251         0,
  32252         0x2800,
  32253         SOC_REG_FLAG_64_BITS |
  32254                           SOC_REG_FLAG_COUNTER,
  32255         0,
  32256         1,
  32257         soc_R1023_BCM53400_A0r_fields,
  32258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32259         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32260         194,
  32261         -1,
  32262     },
  32263 #endif /* chips */
  32264 
  32265 #if defined(BCM_53570_B0)
  32266     { /* SOC_REG_INT_XLMIB_RPFCOFF5_BCM53570_B0r */
  32267         soc_block_list[16],
  32268         soc_portreg,
  32269         1,
  32270         0,
  32271         0x2800,
  32272         SOC_REG_FLAG_64_BITS |
  32273                           SOC_REG_FLAG_COUNTER,
  32274         0,
  32275         1,
  32276         soc_R1023_BCM53400_A0r_fields,
  32277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32278         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32279         198,
  32280         -1,
  32281     },
  32282 #endif /* chips */
  32283 
  32284 #if defined(BCM_56370_A0)
  32285     { /* SOC_REG_INT_XLMIB_RPFCOFF5_BCM56370_A0r */
  32286         soc_block_list[16],
  32287         soc_portreg,
  32288         1,
  32289         0,
  32290         0x2800,
  32291         SOC_REG_FLAG_64_BITS |
  32292                           SOC_REG_FLAG_COUNTER,
  32293         0,
  32294         1,
  32295         soc_R1023_BCM53400_A0r_fields,
  32296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32297         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32298         100,
  32299         -1,
  32300         3,
  32301     },
  32302 #endif /* chips */
  32303 
  32304 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  32305     { /* SOC_REG_INT_XLMIB_RPFCOFF5_BCM56980_A0r */
  32306         soc_block_list[16],
  32307         soc_portreg,
  32308         1,
  32309         0,
  32310         0x2800,
  32311         SOC_REG_FLAG_64_BITS |
  32312                           SOC_REG_FLAG_COUNTER,
  32313         0,
  32314         1,
  32315         soc_R1023_BCM53400_A0r_fields,
  32316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32317         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32318         75,
  32319         -1,
  32320         3,
  32321     },
  32322 #endif /* chips */
  32323 
  32324 #if defined(BCM_53570_A0)
  32325     { /* SOC_REG_INT_XLMIB_RPFCOFF6_BCM53570_A0r */
  32326         soc_block_list[16],
  32327         soc_portreg,
  32328         1,
  32329         0,
  32330         0x2900,
  32331         SOC_REG_FLAG_64_BITS |
  32332                           SOC_REG_FLAG_COUNTER,
  32333         0,
  32334         1,
  32335         soc_R1023_BCM53400_A0r_fields,
  32336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32337         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32338         195,
  32339         -1,
  32340     },
  32341 #endif /* chips */
  32342 
  32343 #if defined(BCM_53570_B0)
  32344     { /* SOC_REG_INT_XLMIB_RPFCOFF6_BCM53570_B0r */
  32345         soc_block_list[16],
  32346         soc_portreg,
  32347         1,
  32348         0,
  32349         0x2900,
  32350         SOC_REG_FLAG_64_BITS |
  32351                           SOC_REG_FLAG_COUNTER,
  32352         0,
  32353         1,
  32354         soc_R1023_BCM53400_A0r_fields,
  32355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32357         199,
  32358         -1,
  32359     },
  32360 #endif /* chips */
  32361 
  32362 #if defined(BCM_56370_A0)
  32363     { /* SOC_REG_INT_XLMIB_RPFCOFF6_BCM56370_A0r */
  32364         soc_block_list[16],
  32365         soc_portreg,
  32366         1,
  32367         0,
  32368         0x2900,
  32369         SOC_REG_FLAG_64_BITS |
  32370                           SOC_REG_FLAG_COUNTER,
  32371         0,
  32372         1,
  32373         soc_R1023_BCM53400_A0r_fields,
  32374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32375         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32376         101,
  32377         -1,
  32378         3,
  32379     },
  32380 #endif /* chips */
  32381 
  32382 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  32383     { /* SOC_REG_INT_XLMIB_RPFCOFF6_BCM56980_A0r */
  32384         soc_block_list[16],
  32385         soc_portreg,
  32386         1,
  32387         0,
  32388         0x2900,
  32389         SOC_REG_FLAG_64_BITS |
  32390                           SOC_REG_FLAG_COUNTER,
  32391         0,
  32392         1,
  32393         soc_R1023_BCM53400_A0r_fields,
  32394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32395         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32396         76,
  32397         -1,
  32398         3,
  32399     },
  32400 #endif /* chips */
  32401 
  32402 #if defined(BCM_53570_A0)
  32403     { /* SOC_REG_INT_XLMIB_RPFCOFF7_BCM53570_A0r */
  32404         soc_block_list[16],
  32405         soc_portreg,
  32406         1,
  32407         0,
  32408         0x2a00,
  32409         SOC_REG_FLAG_64_BITS |
  32410                           SOC_REG_FLAG_COUNTER,
  32411         0,
  32412         1,
  32413         soc_R1023_BCM53400_A0r_fields,
  32414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32415         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32416         196,
  32417         -1,
  32418     },
  32419 #endif /* chips */
  32420 
  32421 #if defined(BCM_53570_B0)
  32422     { /* SOC_REG_INT_XLMIB_RPFCOFF7_BCM53570_B0r */
  32423         soc_block_list[16],
  32424         soc_portreg,
  32425         1,
  32426         0,
  32427         0x2a00,
  32428         SOC_REG_FLAG_64_BITS |
  32429                           SOC_REG_FLAG_COUNTER,
  32430         0,
  32431         1,
  32432         soc_R1023_BCM53400_A0r_fields,
  32433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32434         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32435         200,
  32436         -1,
  32437     },
  32438 #endif /* chips */
  32439 
  32440 #if defined(BCM_56370_A0)
  32441     { /* SOC_REG_INT_XLMIB_RPFCOFF7_BCM56370_A0r */
  32442         soc_block_list[16],
  32443         soc_portreg,
  32444         1,
  32445         0,
  32446         0x2a00,
  32447         SOC_REG_FLAG_64_BITS |
  32448                           SOC_REG_FLAG_COUNTER,
  32449         0,
  32450         1,
  32451         soc_R1023_BCM53400_A0r_fields,
  32452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32453         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32454         102,
  32455         -1,
  32456         3,
  32457     },
  32458 #endif /* chips */
  32459 
  32460 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  32461     { /* SOC_REG_INT_XLMIB_RPFCOFF7_BCM56980_A0r */
  32462         soc_block_list[16],
  32463         soc_portreg,
  32464         1,
  32465         0,
  32466         0x2a00,
  32467         SOC_REG_FLAG_64_BITS |
  32468                           SOC_REG_FLAG_COUNTER,
  32469         0,
  32470         1,
  32471         soc_R1023_BCM53400_A0r_fields,
  32472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32473         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32474         77,
  32475         -1,
  32476         3,
  32477     },
  32478 #endif /* chips */
  32479 
  32480 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  32481     { /* SOC_REG_INT_XLMIB_RPKTr */
  32482         soc_block_list[16],
  32483         soc_portreg,
  32484         1,
  32485         0,
  32486         0xb00,
  32487         SOC_REG_FLAG_64_BITS |
  32488                           SOC_REG_FLAG_COUNTER,
  32489         0,
  32490         1,
  32491         soc_R1023_BCM53400_A0r_fields,
  32492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32493         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32494         70,
  32495         -1,
  32496         3,
  32497     },
  32498 #endif /* chips */
  32499 
  32500 #if defined(BCM_53570_A0)
  32501     { /* SOC_REG_INT_XLMIB_RPKT_BCM53570_A0r */
  32502         soc_block_list[16],
  32503         soc_portreg,
  32504         1,
  32505         0,
  32506         0xb00,
  32507         SOC_REG_FLAG_64_BITS |
  32508                           SOC_REG_FLAG_COUNTER,
  32509         0,
  32510         1,
  32511         soc_R1023_BCM53400_A0r_fields,
  32512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32514         165,
  32515         -1,
  32516     },
  32517 #endif /* chips */
  32518 
  32519 #if defined(BCM_53570_B0)
  32520     { /* SOC_REG_INT_XLMIB_RPKT_BCM53570_B0r */
  32521         soc_block_list[16],
  32522         soc_portreg,
  32523         1,
  32524         0,
  32525         0xb00,
  32526         SOC_REG_FLAG_64_BITS |
  32527                           SOC_REG_FLAG_COUNTER,
  32528         0,
  32529         1,
  32530         soc_R1023_BCM53400_A0r_fields,
  32531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32532         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32533         169,
  32534         -1,
  32535     },
  32536 #endif /* chips */
  32537 
  32538 #if defined(BCM_56370_A0)
  32539     { /* SOC_REG_INT_XLMIB_RPKT_BCM56370_A0r */
  32540         soc_block_list[16],
  32541         soc_portreg,
  32542         1,
  32543         0,
  32544         0xb00,
  32545         SOC_REG_FLAG_64_BITS |
  32546                           SOC_REG_FLAG_COUNTER,
  32547         0,
  32548         1,
  32549         soc_R1023_BCM53400_A0r_fields,
  32550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32551         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32552         71,
  32553         -1,
  32554         3,
  32555     },
  32556 #endif /* chips */
  32557 
  32558 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  32559     { /* SOC_REG_INT_XLMIB_RPKT_BCM56980_A0r */
  32560         soc_block_list[16],
  32561         soc_portreg,
  32562         1,
  32563         0,
  32564         0xb00,
  32565         SOC_REG_FLAG_64_BITS |
  32566                           SOC_REG_FLAG_COUNTER,
  32567         0,
  32568         1,
  32569         soc_R1023_BCM53400_A0r_fields,
  32570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32572         46,
  32573         -1,
  32574         3,
  32575     },
  32576 #endif /* chips */
  32577 
  32578 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  32579     { /* SOC_REG_INT_XLMIB_RPOKr */
  32580         soc_block_list[16],
  32581         soc_portreg,
  32582         1,
  32583         0,
  32584         0x2200,
  32585         SOC_REG_FLAG_64_BITS |
  32586                           SOC_REG_FLAG_COUNTER,
  32587         0,
  32588         1,
  32589         soc_R1023_BCM53400_A0r_fields,
  32590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32592         93,
  32593         -1,
  32594         3,
  32595     },
  32596 #endif /* chips */
  32597 
  32598 #if defined(BCM_53570_A0)
  32599     { /* SOC_REG_INT_XLMIB_RPOK_BCM53570_A0r */
  32600         soc_block_list[16],
  32601         soc_portreg,
  32602         1,
  32603         0,
  32604         0x2200,
  32605         SOC_REG_FLAG_64_BITS |
  32606                           SOC_REG_FLAG_COUNTER,
  32607         0,
  32608         1,
  32609         soc_R1023_BCM53400_A0r_fields,
  32610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32612         188,
  32613         -1,
  32614     },
  32615 #endif /* chips */
  32616 
  32617 #if defined(BCM_53570_B0)
  32618     { /* SOC_REG_INT_XLMIB_RPOK_BCM53570_B0r */
  32619         soc_block_list[16],
  32620         soc_portreg,
  32621         1,
  32622         0,
  32623         0x2200,
  32624         SOC_REG_FLAG_64_BITS |
  32625                           SOC_REG_FLAG_COUNTER,
  32626         0,
  32627         1,
  32628         soc_R1023_BCM53400_A0r_fields,
  32629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32630         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32631         192,
  32632         -1,
  32633     },
  32634 #endif /* chips */
  32635 
  32636 #if defined(BCM_56370_A0)
  32637     { /* SOC_REG_INT_XLMIB_RPOK_BCM56370_A0r */
  32638         soc_block_list[16],
  32639         soc_portreg,
  32640         1,
  32641         0,
  32642         0x2200,
  32643         SOC_REG_FLAG_64_BITS |
  32644                           SOC_REG_FLAG_COUNTER,
  32645         0,
  32646         1,
  32647         soc_R1023_BCM53400_A0r_fields,
  32648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32649         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32650         94,
  32651         -1,
  32652         3,
  32653     },
  32654 #endif /* chips */
  32655 
  32656 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  32657     { /* SOC_REG_INT_XLMIB_RPOK_BCM56980_A0r */
  32658         soc_block_list[16],
  32659         soc_portreg,
  32660         1,
  32661         0,
  32662         0x2200,
  32663         SOC_REG_FLAG_64_BITS |
  32664                           SOC_REG_FLAG_COUNTER,
  32665         0,
  32666         1,
  32667         soc_R1023_BCM53400_A0r_fields,
  32668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32670         69,
  32671         -1,
  32672         3,
  32673     },
  32674 #endif /* chips */
  32675 
  32676 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  32677     { /* SOC_REG_INT_XLMIB_RPRMr */
  32678         soc_block_list[16],
  32679         soc_portreg,
  32680         1,
  32681         0,
  32682         0x1e00,
  32683         SOC_REG_FLAG_64_BITS |
  32684                           SOC_REG_FLAG_COUNTER,
  32685         0,
  32686         1,
  32687         soc_R1023_BCM53400_A0r_fields,
  32688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32689         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32690         89,
  32691         -1,
  32692         3,
  32693     },
  32694 #endif /* chips */
  32695 
  32696 #if defined(BCM_53570_A0)
  32697     { /* SOC_REG_INT_XLMIB_RPRM_BCM53570_A0r */
  32698         soc_block_list[16],
  32699         soc_portreg,
  32700         1,
  32701         0,
  32702         0x1e00,
  32703         SOC_REG_FLAG_64_BITS |
  32704                           SOC_REG_FLAG_COUNTER,
  32705         0,
  32706         1,
  32707         soc_R1023_BCM53400_A0r_fields,
  32708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32709         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32710         184,
  32711         -1,
  32712     },
  32713 #endif /* chips */
  32714 
  32715 #if defined(BCM_53570_B0)
  32716     { /* SOC_REG_INT_XLMIB_RPRM_BCM53570_B0r */
  32717         soc_block_list[16],
  32718         soc_portreg,
  32719         1,
  32720         0,
  32721         0x1e00,
  32722         SOC_REG_FLAG_64_BITS |
  32723                           SOC_REG_FLAG_COUNTER,
  32724         0,
  32725         1,
  32726         soc_R1023_BCM53400_A0r_fields,
  32727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32728         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32729         188,
  32730         -1,
  32731     },
  32732 #endif /* chips */
  32733 
  32734 #if defined(BCM_56370_A0)
  32735     { /* SOC_REG_INT_XLMIB_RPRM_BCM56370_A0r */
  32736         soc_block_list[16],
  32737         soc_portreg,
  32738         1,
  32739         0,
  32740         0x1e00,
  32741         SOC_REG_FLAG_64_BITS |
  32742                           SOC_REG_FLAG_COUNTER,
  32743         0,
  32744         1,
  32745         soc_R1023_BCM53400_A0r_fields,
  32746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32747         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32748         90,
  32749         -1,
  32750         3,
  32751     },
  32752 #endif /* chips */
  32753 
  32754 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  32755     { /* SOC_REG_INT_XLMIB_RPRM_BCM56980_A0r */
  32756         soc_block_list[16],
  32757         soc_portreg,
  32758         1,
  32759         0,
  32760         0x1e00,
  32761         SOC_REG_FLAG_64_BITS |
  32762                           SOC_REG_FLAG_COUNTER,
  32763         0,
  32764         1,
  32765         soc_R1023_BCM53400_A0r_fields,
  32766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32767         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32768         65,
  32769         -1,
  32770         3,
  32771     },
  32772 #endif /* chips */
  32773 
  32774 #if defined(BCM_56970_A0)
  32775     { /* SOC_REG_INT_XLMIB_RPROG0r */
  32776         soc_block_list[16],
  32777         soc_portreg,
  32778         1,
  32779         0,
  32780         0x7500,
  32781         SOC_REG_FLAG_64_BITS |
  32782                           SOC_REG_FLAG_COUNTER,
  32783         0,
  32784         1,
  32785         soc_R1023_BCM53400_A0r_fields,
  32786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32787         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32788         172,
  32789         -1,
  32790         3,
  32791     },
  32792 #endif /* chips */
  32793 
  32794 #if defined(BCM_56970_A0)
  32795     { /* SOC_REG_INT_XLMIB_RPROG1r */
  32796         soc_block_list[16],
  32797         soc_portreg,
  32798         1,
  32799         0,
  32800         0x7600,
  32801         SOC_REG_FLAG_64_BITS |
  32802                           SOC_REG_FLAG_COUNTER,
  32803         0,
  32804         1,
  32805         soc_R1023_BCM53400_A0r_fields,
  32806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32807         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32808         173,
  32809         -1,
  32810         3,
  32811     },
  32812 #endif /* chips */
  32813 
  32814 #if defined(BCM_56970_A0)
  32815     { /* SOC_REG_INT_XLMIB_RPROG2r */
  32816         soc_block_list[16],
  32817         soc_portreg,
  32818         1,
  32819         0,
  32820         0x7700,
  32821         SOC_REG_FLAG_64_BITS |
  32822                           SOC_REG_FLAG_COUNTER,
  32823         0,
  32824         1,
  32825         soc_R1023_BCM53400_A0r_fields,
  32826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32827         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32828         174,
  32829         -1,
  32830         3,
  32831     },
  32832 #endif /* chips */
  32833 
  32834 #if defined(BCM_56970_A0)
  32835     { /* SOC_REG_INT_XLMIB_RPROG3r */
  32836         soc_block_list[16],
  32837         soc_portreg,
  32838         1,
  32839         0,
  32840         0x7800,
  32841         SOC_REG_FLAG_64_BITS |
  32842                           SOC_REG_FLAG_COUNTER,
  32843         0,
  32844         1,
  32845         soc_R1023_BCM53400_A0r_fields,
  32846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32847         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32848         175,
  32849         -1,
  32850         3,
  32851     },
  32852 #endif /* chips */
  32853 
  32854 #if defined(BCM_53570_A0)
  32855     { /* SOC_REG_INT_XLMIB_RPROG0_BCM53570_A0r */
  32856         soc_block_list[16],
  32857         soc_portreg,
  32858         1,
  32859         0,
  32860         0x7500,
  32861         SOC_REG_FLAG_64_BITS |
  32862                           SOC_REG_FLAG_COUNTER,
  32863         0,
  32864         1,
  32865         soc_R1023_BCM53400_A0r_fields,
  32866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32867         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32868         271,
  32869         -1,
  32870     },
  32871 #endif /* chips */
  32872 
  32873 #if defined(BCM_53570_B0)
  32874     { /* SOC_REG_INT_XLMIB_RPROG0_BCM53570_B0r */
  32875         soc_block_list[16],
  32876         soc_portreg,
  32877         1,
  32878         0,
  32879         0x7500,
  32880         SOC_REG_FLAG_64_BITS |
  32881                           SOC_REG_FLAG_COUNTER,
  32882         0,
  32883         1,
  32884         soc_R1023_BCM53400_A0r_fields,
  32885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32886         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32887         275,
  32888         -1,
  32889     },
  32890 #endif /* chips */
  32891 
  32892 #if defined(BCM_56370_A0)
  32893     { /* SOC_REG_INT_XLMIB_RPROG0_BCM56370_A0r */
  32894         soc_block_list[16],
  32895         soc_portreg,
  32896         1,
  32897         0,
  32898         0x7500,
  32899         SOC_REG_FLAG_64_BITS |
  32900                           SOC_REG_FLAG_COUNTER,
  32901         0,
  32902         1,
  32903         soc_R1023_BCM53400_A0r_fields,
  32904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32905         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32906         177,
  32907         -1,
  32908         3,
  32909     },
  32910 #endif /* chips */
  32911 
  32912 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  32913     { /* SOC_REG_INT_XLMIB_RPROG0_BCM56870_A0r */
  32914         soc_block_list[16],
  32915         soc_portreg,
  32916         1,
  32917         0,
  32918         0x7500,
  32919         SOC_REG_FLAG_64_BITS |
  32920                           SOC_REG_FLAG_COUNTER,
  32921         0,
  32922         1,
  32923         soc_R1023_BCM53400_A0r_fields,
  32924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32926         176,
  32927         -1,
  32928         3,
  32929     },
  32930 #endif /* chips */
  32931 
  32932 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  32933     { /* SOC_REG_INT_XLMIB_RPROG0_BCM56980_A0r */
  32934         soc_block_list[16],
  32935         soc_portreg,
  32936         1,
  32937         0,
  32938         0x7500,
  32939         SOC_REG_FLAG_64_BITS |
  32940                           SOC_REG_FLAG_COUNTER,
  32941         0,
  32942         1,
  32943         soc_R1023_BCM53400_A0r_fields,
  32944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32945         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32946         152,
  32947         -1,
  32948         3,
  32949     },
  32950 #endif /* chips */
  32951 
  32952 #if defined(BCM_53570_A0)
  32953     { /* SOC_REG_INT_XLMIB_RPROG1_BCM53570_A0r */
  32954         soc_block_list[16],
  32955         soc_portreg,
  32956         1,
  32957         0,
  32958         0x7600,
  32959         SOC_REG_FLAG_64_BITS |
  32960                           SOC_REG_FLAG_COUNTER,
  32961         0,
  32962         1,
  32963         soc_R1023_BCM53400_A0r_fields,
  32964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32965         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32966         272,
  32967         -1,
  32968     },
  32969 #endif /* chips */
  32970 
  32971 #if defined(BCM_53570_B0)
  32972     { /* SOC_REG_INT_XLMIB_RPROG1_BCM53570_B0r */
  32973         soc_block_list[16],
  32974         soc_portreg,
  32975         1,
  32976         0,
  32977         0x7600,
  32978         SOC_REG_FLAG_64_BITS |
  32979                           SOC_REG_FLAG_COUNTER,
  32980         0,
  32981         1,
  32982         soc_R1023_BCM53400_A0r_fields,
  32983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32984         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32985         276,
  32986         -1,
  32987     },
  32988 #endif /* chips */
  32989 
  32990 #if defined(BCM_56370_A0)
  32991     { /* SOC_REG_INT_XLMIB_RPROG1_BCM56370_A0r */
  32992         soc_block_list[16],
  32993         soc_portreg,
  32994         1,
  32995         0,
  32996         0x7600,
  32997         SOC_REG_FLAG_64_BITS |
  32998                           SOC_REG_FLAG_COUNTER,
  32999         0,
  33000         1,
  33001         soc_R1023_BCM53400_A0r_fields,
  33002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33003         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33004         178,
  33005         -1,
  33006         3,
  33007     },
  33008 #endif /* chips */
  33009 
  33010 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  33011     { /* SOC_REG_INT_XLMIB_RPROG1_BCM56870_A0r */
  33012         soc_block_list[16],
  33013         soc_portreg,
  33014         1,
  33015         0,
  33016         0x7600,
  33017         SOC_REG_FLAG_64_BITS |
  33018                           SOC_REG_FLAG_COUNTER,
  33019         0,
  33020         1,
  33021         soc_R1023_BCM53400_A0r_fields,
  33022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33023         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33024         177,
  33025         -1,
  33026         3,
  33027     },
  33028 #endif /* chips */
  33029 
  33030 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  33031     { /* SOC_REG_INT_XLMIB_RPROG1_BCM56980_A0r */
  33032         soc_block_list[16],
  33033         soc_portreg,
  33034         1,
  33035         0,
  33036         0x7600,
  33037         SOC_REG_FLAG_64_BITS |
  33038                           SOC_REG_FLAG_COUNTER,
  33039         0,
  33040         1,
  33041         soc_R1023_BCM53400_A0r_fields,
  33042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33043         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33044         153,
  33045         -1,
  33046         3,
  33047     },
  33048 #endif /* chips */
  33049 
  33050 #if defined(BCM_53570_A0)
  33051     { /* SOC_REG_INT_XLMIB_RPROG2_BCM53570_A0r */
  33052         soc_block_list[16],
  33053         soc_portreg,
  33054         1,
  33055         0,
  33056         0x7700,
  33057         SOC_REG_FLAG_64_BITS |
  33058                           SOC_REG_FLAG_COUNTER,
  33059         0,
  33060         1,
  33061         soc_R1023_BCM53400_A0r_fields,
  33062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33064         273,
  33065         -1,
  33066     },
  33067 #endif /* chips */
  33068 
  33069 #if defined(BCM_53570_B0)
  33070     { /* SOC_REG_INT_XLMIB_RPROG2_BCM53570_B0r */
  33071         soc_block_list[16],
  33072         soc_portreg,
  33073         1,
  33074         0,
  33075         0x7700,
  33076         SOC_REG_FLAG_64_BITS |
  33077                           SOC_REG_FLAG_COUNTER,
  33078         0,
  33079         1,
  33080         soc_R1023_BCM53400_A0r_fields,
  33081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33082         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33083         277,
  33084         -1,
  33085     },
  33086 #endif /* chips */
  33087 
  33088 #if defined(BCM_56370_A0)
  33089     { /* SOC_REG_INT_XLMIB_RPROG2_BCM56370_A0r */
  33090         soc_block_list[16],
  33091         soc_portreg,
  33092         1,
  33093         0,
  33094         0x7700,
  33095         SOC_REG_FLAG_64_BITS |
  33096                           SOC_REG_FLAG_COUNTER,
  33097         0,
  33098         1,
  33099         soc_R1023_BCM53400_A0r_fields,
  33100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33101         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33102         179,
  33103         -1,
  33104         3,
  33105     },
  33106 #endif /* chips */
  33107 
  33108 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  33109     { /* SOC_REG_INT_XLMIB_RPROG2_BCM56870_A0r */
  33110         soc_block_list[16],
  33111         soc_portreg,
  33112         1,
  33113         0,
  33114         0x7700,
  33115         SOC_REG_FLAG_64_BITS |
  33116                           SOC_REG_FLAG_COUNTER,
  33117         0,
  33118         1,
  33119         soc_R1023_BCM53400_A0r_fields,
  33120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33121         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33122         178,
  33123         -1,
  33124         3,
  33125     },
  33126 #endif /* chips */
  33127 
  33128 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  33129     { /* SOC_REG_INT_XLMIB_RPROG2_BCM56980_A0r */
  33130         soc_block_list[16],
  33131         soc_portreg,
  33132         1,
  33133         0,
  33134         0x7700,
  33135         SOC_REG_FLAG_64_BITS |
  33136                           SOC_REG_FLAG_COUNTER,
  33137         0,
  33138         1,
  33139         soc_R1023_BCM53400_A0r_fields,
  33140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33141         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33142         154,
  33143         -1,
  33144         3,
  33145     },
  33146 #endif /* chips */
  33147 
  33148 #if defined(BCM_53570_A0)
  33149     { /* SOC_REG_INT_XLMIB_RPROG3_BCM53570_A0r */
  33150         soc_block_list[16],
  33151         soc_portreg,
  33152         1,
  33153         0,
  33154         0x7800,
  33155         SOC_REG_FLAG_64_BITS |
  33156                           SOC_REG_FLAG_COUNTER,
  33157         0,
  33158         1,
  33159         soc_R1023_BCM53400_A0r_fields,
  33160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33161         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33162         274,
  33163         -1,
  33164     },
  33165 #endif /* chips */
  33166 
  33167 #if defined(BCM_53570_B0)
  33168     { /* SOC_REG_INT_XLMIB_RPROG3_BCM53570_B0r */
  33169         soc_block_list[16],
  33170         soc_portreg,
  33171         1,
  33172         0,
  33173         0x7800,
  33174         SOC_REG_FLAG_64_BITS |
  33175                           SOC_REG_FLAG_COUNTER,
  33176         0,
  33177         1,
  33178         soc_R1023_BCM53400_A0r_fields,
  33179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33180         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33181         278,
  33182         -1,
  33183     },
  33184 #endif /* chips */
  33185 
  33186 #if defined(BCM_56370_A0)
  33187     { /* SOC_REG_INT_XLMIB_RPROG3_BCM56370_A0r */
  33188         soc_block_list[16],
  33189         soc_portreg,
  33190         1,
  33191         0,
  33192         0x7800,
  33193         SOC_REG_FLAG_64_BITS |
  33194                           SOC_REG_FLAG_COUNTER,
  33195         0,
  33196         1,
  33197         soc_R1023_BCM53400_A0r_fields,
  33198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33200         180,
  33201         -1,
  33202         3,
  33203     },
  33204 #endif /* chips */
  33205 
  33206 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  33207     { /* SOC_REG_INT_XLMIB_RPROG3_BCM56870_A0r */
  33208         soc_block_list[16],
  33209         soc_portreg,
  33210         1,
  33211         0,
  33212         0x7800,
  33213         SOC_REG_FLAG_64_BITS |
  33214                           SOC_REG_FLAG_COUNTER,
  33215         0,
  33216         1,
  33217         soc_R1023_BCM53400_A0r_fields,
  33218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33219         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33220         179,
  33221         -1,
  33222         3,
  33223     },
  33224 #endif /* chips */
  33225 
  33226 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  33227     { /* SOC_REG_INT_XLMIB_RPROG3_BCM56980_A0r */
  33228         soc_block_list[16],
  33229         soc_portreg,
  33230         1,
  33231         0,
  33232         0x7800,
  33233         SOC_REG_FLAG_64_BITS |
  33234                           SOC_REG_FLAG_COUNTER,
  33235         0,
  33236         1,
  33237         soc_R1023_BCM53400_A0r_fields,
  33238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33239         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33240         155,
  33241         -1,
  33242         3,
  33243     },
  33244 #endif /* chips */
  33245 
  33246 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  33247     { /* SOC_REG_INT_XLMIB_RRBYTr */
  33248         soc_block_list[16],
  33249         soc_portreg,
  33250         1,
  33251         0,
  33252         0x3e00,
  33253         SOC_REG_FLAG_64_BITS |
  33254                           SOC_REG_FLAG_COUNTER |
  33255                           SOC_REG_FLAG_ED_CNTR,
  33256         0,
  33257         1,
  33258         soc_RBYT_BCM53400_A0r_fields,
  33259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33260         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33261         121,
  33262         -1,
  33263         3,
  33264     },
  33265 #endif /* chips */
  33266 
  33267 #if defined(BCM_53570_A0)
  33268     { /* SOC_REG_INT_XLMIB_RRBYT_BCM53570_A0r */
  33269         soc_block_list[16],
  33270         soc_portreg,
  33271         1,
  33272         0,
  33273         0x3e00,
  33274         SOC_REG_FLAG_64_BITS |
  33275                           SOC_REG_FLAG_COUNTER |
  33276                           SOC_REG_FLAG_ED_CNTR,
  33277         0,
  33278         1,
  33279         soc_RBYT_BCM53400_A0r_fields,
  33280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33281         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33282         216,
  33283         -1,
  33284     },
  33285 #endif /* chips */
  33286 
  33287 #if defined(BCM_53570_B0)
  33288     { /* SOC_REG_INT_XLMIB_RRBYT_BCM53570_B0r */
  33289         soc_block_list[16],
  33290         soc_portreg,
  33291         1,
  33292         0,
  33293         0x3e00,
  33294         SOC_REG_FLAG_64_BITS |
  33295                           SOC_REG_FLAG_COUNTER |
  33296                           SOC_REG_FLAG_ED_CNTR,
  33297         0,
  33298         1,
  33299         soc_RBYT_BCM53400_A0r_fields,
  33300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33301         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33302         220,
  33303         -1,
  33304     },
  33305 #endif /* chips */
  33306 
  33307 #if defined(BCM_56370_A0)
  33308     { /* SOC_REG_INT_XLMIB_RRBYT_BCM56370_A0r */
  33309         soc_block_list[16],
  33310         soc_portreg,
  33311         1,
  33312         0,
  33313         0x3e00,
  33314         SOC_REG_FLAG_64_BITS |
  33315                           SOC_REG_FLAG_COUNTER |
  33316                           SOC_REG_FLAG_ED_CNTR,
  33317         0,
  33318         1,
  33319         soc_RBYT_BCM53400_A0r_fields,
  33320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33321         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33322         122,
  33323         -1,
  33324         3,
  33325     },
  33326 #endif /* chips */
  33327 
  33328 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  33329     { /* SOC_REG_INT_XLMIB_RRBYT_BCM56980_A0r */
  33330         soc_block_list[16],
  33331         soc_portreg,
  33332         1,
  33333         0,
  33334         0x3e00,
  33335         SOC_REG_FLAG_64_BITS |
  33336                           SOC_REG_FLAG_COUNTER |
  33337                           SOC_REG_FLAG_ED_CNTR,
  33338         0,
  33339         1,
  33340         soc_RBYT_BCM53400_A0r_fields,
  33341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33342         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33343         97,
  33344         -1,
  33345         3,
  33346     },
  33347 #endif /* chips */
  33348 
  33349 #if defined(BCM_53570_A0)
  33350     { /* SOC_REG_INT_XLMIB_RREPLYr */
  33351         soc_block_list[16],
  33352         soc_portreg,
  33353         1,
  33354         0,
  33355         0x1900,
  33356         SOC_REG_FLAG_64_BITS |
  33357                           SOC_REG_FLAG_COUNTER,
  33358         0,
  33359         1,
  33360         soc_R1023_BCM53400_A0r_fields,
  33361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33362         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33363         179,
  33364         -1,
  33365     },
  33366 #endif /* chips */
  33367 
  33368 #if defined(BCM_53570_B0)
  33369     { /* SOC_REG_INT_XLMIB_RREPLY_BCM53570_B0r */
  33370         soc_block_list[16],
  33371         soc_portreg,
  33372         1,
  33373         0,
  33374         0x1900,
  33375         SOC_REG_FLAG_64_BITS |
  33376                           SOC_REG_FLAG_COUNTER,
  33377         0,
  33378         1,
  33379         soc_R1023_BCM53400_A0r_fields,
  33380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33381         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33382         183,
  33383         -1,
  33384     },
  33385 #endif /* chips */
  33386 
  33387 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  33388     { /* SOC_REG_INT_XLMIB_RRPKTr */
  33389         soc_block_list[16],
  33390         soc_portreg,
  33391         1,
  33392         0,
  33393         0x3f00,
  33394         SOC_REG_FLAG_64_BITS |
  33395                           SOC_REG_FLAG_COUNTER |
  33396                           SOC_REG_FLAG_ED_CNTR,
  33397         0,
  33398         1,
  33399         soc_R1023_BCM53400_A0r_fields,
  33400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33401         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33402         122,
  33403         -1,
  33404         3,
  33405     },
  33406 #endif /* chips */
  33407 
  33408 #if defined(BCM_53570_A0)
  33409     { /* SOC_REG_INT_XLMIB_RRPKT_BCM53570_A0r */
  33410         soc_block_list[16],
  33411         soc_portreg,
  33412         1,
  33413         0,
  33414         0x3f00,
  33415         SOC_REG_FLAG_64_BITS |
  33416                           SOC_REG_FLAG_COUNTER |
  33417                           SOC_REG_FLAG_ED_CNTR,
  33418         0,
  33419         1,
  33420         soc_R1023_BCM53400_A0r_fields,
  33421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33422         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33423         217,
  33424         -1,
  33425     },
  33426 #endif /* chips */
  33427 
  33428 #if defined(BCM_53570_B0)
  33429     { /* SOC_REG_INT_XLMIB_RRPKT_BCM53570_B0r */
  33430         soc_block_list[16],
  33431         soc_portreg,
  33432         1,
  33433         0,
  33434         0x3f00,
  33435         SOC_REG_FLAG_64_BITS |
  33436                           SOC_REG_FLAG_COUNTER |
  33437                           SOC_REG_FLAG_ED_CNTR,
  33438         0,
  33439         1,
  33440         soc_R1023_BCM53400_A0r_fields,
  33441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33442         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33443         221,
  33444         -1,
  33445     },
  33446 #endif /* chips */
  33447 
  33448 #if defined(BCM_56370_A0)
  33449     { /* SOC_REG_INT_XLMIB_RRPKT_BCM56370_A0r */
  33450         soc_block_list[16],
  33451         soc_portreg,
  33452         1,
  33453         0,
  33454         0x3f00,
  33455         SOC_REG_FLAG_64_BITS |
  33456                           SOC_REG_FLAG_COUNTER |
  33457                           SOC_REG_FLAG_ED_CNTR,
  33458         0,
  33459         1,
  33460         soc_R1023_BCM53400_A0r_fields,
  33461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33462         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33463         123,
  33464         -1,
  33465         3,
  33466     },
  33467 #endif /* chips */
  33468 
  33469 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  33470     { /* SOC_REG_INT_XLMIB_RRPKT_BCM56980_A0r */
  33471         soc_block_list[16],
  33472         soc_portreg,
  33473         1,
  33474         0,
  33475         0x3f00,
  33476         SOC_REG_FLAG_64_BITS |
  33477                           SOC_REG_FLAG_COUNTER |
  33478                           SOC_REG_FLAG_ED_CNTR,
  33479         0,
  33480         1,
  33481         soc_R1023_BCM53400_A0r_fields,
  33482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33484         98,
  33485         -1,
  33486         3,
  33487     },
  33488 #endif /* chips */
  33489 
  33490 #if defined(BCM_56970_A0)
  33491     { /* SOC_REG_INT_XLMIB_RSCHCRCr */
  33492         soc_block_list[16],
  33493         soc_portreg,
  33494         1,
  33495         0,
  33496         0x3300,
  33497         SOC_REG_FLAG_64_BITS |
  33498                           SOC_REG_FLAG_COUNTER,
  33499         0,
  33500         1,
  33501         soc_RSCHCRC_BCM53400_A0r_fields,
  33502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33503         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33504         106,
  33505         -1,
  33506         3,
  33507     },
  33508 #endif /* chips */
  33509 
  33510 #if defined(BCM_53570_A0)
  33511     { /* SOC_REG_INT_XLMIB_RSCHCRC_BCM53570_A0r */
  33512         soc_block_list[16],
  33513         soc_portreg,
  33514         1,
  33515         0,
  33516         0x3300,
  33517         SOC_REG_FLAG_64_BITS |
  33518                           SOC_REG_FLAG_COUNTER,
  33519         0,
  33520         1,
  33521         soc_XLMIB_RSCHCRCr_fields,
  33522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33523         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33524         205,
  33525         -1,
  33526     },
  33527 #endif /* chips */
  33528 
  33529 #if defined(BCM_53570_B0)
  33530     { /* SOC_REG_INT_XLMIB_RSCHCRC_BCM53570_B0r */
  33531         soc_block_list[16],
  33532         soc_portreg,
  33533         1,
  33534         0,
  33535         0x3300,
  33536         SOC_REG_FLAG_64_BITS |
  33537                           SOC_REG_FLAG_COUNTER,
  33538         0,
  33539         1,
  33540         soc_XLMIB_RSCHCRCr_fields,
  33541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33542         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33543         209,
  33544         -1,
  33545     },
  33546 #endif /* chips */
  33547 
  33548 #if defined(BCM_56370_A0)
  33549     { /* SOC_REG_INT_XLMIB_RSCHCRC_BCM56370_A0r */
  33550         soc_block_list[16],
  33551         soc_portreg,
  33552         1,
  33553         0,
  33554         0x3300,
  33555         SOC_REG_FLAG_64_BITS |
  33556                           SOC_REG_FLAG_COUNTER,
  33557         0,
  33558         1,
  33559         soc_RSCHCRC_BCM53400_A0r_fields,
  33560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33562         111,
  33563         -1,
  33564         3,
  33565     },
  33566 #endif /* chips */
  33567 
  33568 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  33569     { /* SOC_REG_INT_XLMIB_RSCHCRC_BCM56870_A0r */
  33570         soc_block_list[16],
  33571         soc_portreg,
  33572         1,
  33573         0,
  33574         0x3300,
  33575         SOC_REG_FLAG_64_BITS |
  33576                           SOC_REG_FLAG_COUNTER,
  33577         0,
  33578         1,
  33579         soc_RSCHCRC_BCM53400_A0r_fields,
  33580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33581         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33582         110,
  33583         -1,
  33584         3,
  33585     },
  33586 #endif /* chips */
  33587 
  33588 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  33589     { /* SOC_REG_INT_XLMIB_RSCHCRC_BCM56980_A0r */
  33590         soc_block_list[16],
  33591         soc_portreg,
  33592         1,
  33593         0,
  33594         0x3300,
  33595         SOC_REG_FLAG_64_BITS |
  33596                           SOC_REG_FLAG_COUNTER,
  33597         0,
  33598         1,
  33599         soc_RSCHCRC_BCM53400_A0r_fields,
  33600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33601         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33602         86,
  33603         -1,
  33604         3,
  33605     },
  33606 #endif /* chips */
  33607 
  33608 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  33609     { /* SOC_REG_INT_XLMIB_RTRFUr */
  33610         soc_block_list[16],
  33611         soc_portreg,
  33612         1,
  33613         0,
  33614         0x2100,
  33615         SOC_REG_FLAG_64_BITS |
  33616                           SOC_REG_FLAG_COUNTER,
  33617         0,
  33618         1,
  33619         soc_R1023_BCM53400_A0r_fields,
  33620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33621         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33622         92,
  33623         -1,
  33624         3,
  33625     },
  33626 #endif /* chips */
  33627 
  33628 #if defined(BCM_53570_A0)
  33629     { /* SOC_REG_INT_XLMIB_RTRFU_BCM53570_A0r */
  33630         soc_block_list[16],
  33631         soc_portreg,
  33632         1,
  33633         0,
  33634         0x2100,
  33635         SOC_REG_FLAG_64_BITS |
  33636                           SOC_REG_FLAG_COUNTER,
  33637         0,
  33638         1,
  33639         soc_R1023_BCM53400_A0r_fields,
  33640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33641         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33642         187,
  33643         -1,
  33644     },
  33645 #endif /* chips */
  33646 
  33647 #if defined(BCM_53570_B0)
  33648     { /* SOC_REG_INT_XLMIB_RTRFU_BCM53570_B0r */
  33649         soc_block_list[16],
  33650         soc_portreg,
  33651         1,
  33652         0,
  33653         0x2100,
  33654         SOC_REG_FLAG_64_BITS |
  33655                           SOC_REG_FLAG_COUNTER,
  33656         0,
  33657         1,
  33658         soc_R1023_BCM53400_A0r_fields,
  33659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33660         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33661         191,
  33662         -1,
  33663     },
  33664 #endif /* chips */
  33665 
  33666 #if defined(BCM_56370_A0)
  33667     { /* SOC_REG_INT_XLMIB_RTRFU_BCM56370_A0r */
  33668         soc_block_list[16],
  33669         soc_portreg,
  33670         1,
  33671         0,
  33672         0x2100,
  33673         SOC_REG_FLAG_64_BITS |
  33674                           SOC_REG_FLAG_COUNTER,
  33675         0,
  33676         1,
  33677         soc_R1023_BCM53400_A0r_fields,
  33678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33679         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33680         93,
  33681         -1,
  33682         3,
  33683     },
  33684 #endif /* chips */
  33685 
  33686 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  33687     { /* SOC_REG_INT_XLMIB_RTRFU_BCM56980_A0r */
  33688         soc_block_list[16],
  33689         soc_portreg,
  33690         1,
  33691         0,
  33692         0x2100,
  33693         SOC_REG_FLAG_64_BITS |
  33694                           SOC_REG_FLAG_COUNTER,
  33695         0,
  33696         1,
  33697         soc_R1023_BCM53400_A0r_fields,
  33698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33700         68,
  33701         -1,
  33702         3,
  33703     },
  33704 #endif /* chips */
  33705 
  33706 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  33707     { /* SOC_REG_INT_XLMIB_RUCAr */
  33708         soc_block_list[16],
  33709         soc_portreg,
  33710         1,
  33711         0,
  33712         0xc00,
  33713         SOC_REG_FLAG_64_BITS |
  33714                           SOC_REG_FLAG_COUNTER,
  33715         0,
  33716         1,
  33717         soc_R1023_BCM53400_A0r_fields,
  33718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33719         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33720         71,
  33721         -1,
  33722         3,
  33723     },
  33724 #endif /* chips */
  33725 
  33726 #if defined(BCM_53570_A0)
  33727     { /* SOC_REG_INT_XLMIB_RUCA_BCM53570_A0r */
  33728         soc_block_list[16],
  33729         soc_portreg,
  33730         1,
  33731         0,
  33732         0xc00,
  33733         SOC_REG_FLAG_64_BITS |
  33734                           SOC_REG_FLAG_COUNTER,
  33735         0,
  33736         1,
  33737         soc_R1023_BCM53400_A0r_fields,
  33738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33739         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33740         166,
  33741         -1,
  33742     },
  33743 #endif /* chips */
  33744 
  33745 #if defined(BCM_53570_B0)
  33746     { /* SOC_REG_INT_XLMIB_RUCA_BCM53570_B0r */
  33747         soc_block_list[16],
  33748         soc_portreg,
  33749         1,
  33750         0,
  33751         0xc00,
  33752         SOC_REG_FLAG_64_BITS |
  33753                           SOC_REG_FLAG_COUNTER,
  33754         0,
  33755         1,
  33756         soc_R1023_BCM53400_A0r_fields,
  33757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33758         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33759         170,
  33760         -1,
  33761     },
  33762 #endif /* chips */
  33763 
  33764 #if defined(BCM_56370_A0)
  33765     { /* SOC_REG_INT_XLMIB_RUCA_BCM56370_A0r */
  33766         soc_block_list[16],
  33767         soc_portreg,
  33768         1,
  33769         0,
  33770         0xc00,
  33771         SOC_REG_FLAG_64_BITS |
  33772                           SOC_REG_FLAG_COUNTER,
  33773         0,
  33774         1,
  33775         soc_R1023_BCM53400_A0r_fields,
  33776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33777         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33778         72,
  33779         -1,
  33780         3,
  33781     },
  33782 #endif /* chips */
  33783 
  33784 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  33785     { /* SOC_REG_INT_XLMIB_RUCA_BCM56980_A0r */
  33786         soc_block_list[16],
  33787         soc_portreg,
  33788         1,
  33789         0,
  33790         0xc00,
  33791         SOC_REG_FLAG_64_BITS |
  33792                           SOC_REG_FLAG_COUNTER,
  33793         0,
  33794         1,
  33795         soc_R1023_BCM53400_A0r_fields,
  33796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33797         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33798         47,
  33799         -1,
  33800         3,
  33801     },
  33802 #endif /* chips */
  33803 
  33804 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  33805     { /* SOC_REG_INT_XLMIB_RUNDr */
  33806         soc_block_list[16],
  33807         soc_portreg,
  33808         1,
  33809         0,
  33810         0x3400,
  33811         SOC_REG_FLAG_64_BITS |
  33812                           SOC_REG_FLAG_COUNTER |
  33813                           SOC_REG_FLAG_ED_CNTR,
  33814         0,
  33815         1,
  33816         soc_R1023_BCM53400_A0r_fields,
  33817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33818         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33819         111,
  33820         -1,
  33821         3,
  33822     },
  33823 #endif /* chips */
  33824 
  33825 #if defined(BCM_53570_A0)
  33826     { /* SOC_REG_INT_XLMIB_RUND_BCM53570_A0r */
  33827         soc_block_list[16],
  33828         soc_portreg,
  33829         1,
  33830         0,
  33831         0x3400,
  33832         SOC_REG_FLAG_64_BITS |
  33833                           SOC_REG_FLAG_COUNTER |
  33834                           SOC_REG_FLAG_ED_CNTR,
  33835         0,
  33836         1,
  33837         soc_R1023_BCM53400_A0r_fields,
  33838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33839         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33840         206,
  33841         -1,
  33842     },
  33843 #endif /* chips */
  33844 
  33845 #if defined(BCM_53570_B0)
  33846     { /* SOC_REG_INT_XLMIB_RUND_BCM53570_B0r */
  33847         soc_block_list[16],
  33848         soc_portreg,
  33849         1,
  33850         0,
  33851         0x3400,
  33852         SOC_REG_FLAG_64_BITS |
  33853                           SOC_REG_FLAG_COUNTER |
  33854                           SOC_REG_FLAG_ED_CNTR,
  33855         0,
  33856         1,
  33857         soc_R1023_BCM53400_A0r_fields,
  33858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33859         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33860         210,
  33861         -1,
  33862     },
  33863 #endif /* chips */
  33864 
  33865 #if defined(BCM_56370_A0)
  33866     { /* SOC_REG_INT_XLMIB_RUND_BCM56370_A0r */
  33867         soc_block_list[16],
  33868         soc_portreg,
  33869         1,
  33870         0,
  33871         0x3400,
  33872         SOC_REG_FLAG_64_BITS |
  33873                           SOC_REG_FLAG_COUNTER |
  33874                           SOC_REG_FLAG_ED_CNTR,
  33875         0,
  33876         1,
  33877         soc_R1023_BCM53400_A0r_fields,
  33878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33879         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33880         112,
  33881         -1,
  33882         3,
  33883     },
  33884 #endif /* chips */
  33885 
  33886 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  33887     { /* SOC_REG_INT_XLMIB_RUND_BCM56980_A0r */
  33888         soc_block_list[16],
  33889         soc_portreg,
  33890         1,
  33891         0,
  33892         0x3400,
  33893         SOC_REG_FLAG_64_BITS |
  33894                           SOC_REG_FLAG_COUNTER |
  33895                           SOC_REG_FLAG_ED_CNTR,
  33896         0,
  33897         1,
  33898         soc_R1023_BCM53400_A0r_fields,
  33899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33900         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33901         87,
  33902         -1,
  33903         3,
  33904     },
  33905 #endif /* chips */
  33906 
  33907 #if defined(BCM_53570_A0)
  33908     { /* SOC_REG_INT_XLMIB_RVERIFYr */
  33909         soc_block_list[16],
  33910         soc_portreg,
  33911         1,
  33912         0,
  33913         0x1600,
  33914         SOC_REG_FLAG_64_BITS |
  33915                           SOC_REG_FLAG_COUNTER,
  33916         0,
  33917         1,
  33918         soc_R1023_BCM53400_A0r_fields,
  33919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33920         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33921         176,
  33922         -1,
  33923     },
  33924 #endif /* chips */
  33925 
  33926 #if defined(BCM_53570_B0)
  33927     { /* SOC_REG_INT_XLMIB_RVERIFY_BCM53570_B0r */
  33928         soc_block_list[16],
  33929         soc_portreg,
  33930         1,
  33931         0,
  33932         0x1600,
  33933         SOC_REG_FLAG_64_BITS |
  33934                           SOC_REG_FLAG_COUNTER,
  33935         0,
  33936         1,
  33937         soc_R1023_BCM53400_A0r_fields,
  33938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33939         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33940         180,
  33941         -1,
  33942     },
  33943 #endif /* chips */
  33944 
  33945 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  33946     { /* SOC_REG_INT_XLMIB_RVLNr */
  33947         soc_block_list[16],
  33948         soc_portreg,
  33949         1,
  33950         0,
  33951         0x1f00,
  33952         SOC_REG_FLAG_64_BITS |
  33953                           SOC_REG_FLAG_COUNTER,
  33954         0,
  33955         1,
  33956         soc_R1023_BCM53400_A0r_fields,
  33957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33958         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33959         90,
  33960         -1,
  33961         3,
  33962     },
  33963 #endif /* chips */
  33964 
  33965 #if defined(BCM_53570_A0)
  33966     { /* SOC_REG_INT_XLMIB_RVLN_BCM53570_A0r */
  33967         soc_block_list[16],
  33968         soc_portreg,
  33969         1,
  33970         0,
  33971         0x1f00,
  33972         SOC_REG_FLAG_64_BITS |
  33973                           SOC_REG_FLAG_COUNTER,
  33974         0,
  33975         1,
  33976         soc_R1023_BCM53400_A0r_fields,
  33977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33978         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33979         185,
  33980         -1,
  33981     },
  33982 #endif /* chips */
  33983 
  33984 #if defined(BCM_53570_B0)
  33985     { /* SOC_REG_INT_XLMIB_RVLN_BCM53570_B0r */
  33986         soc_block_list[16],
  33987         soc_portreg,
  33988         1,
  33989         0,
  33990         0x1f00,
  33991         SOC_REG_FLAG_64_BITS |
  33992                           SOC_REG_FLAG_COUNTER,
  33993         0,
  33994         1,
  33995         soc_R1023_BCM53400_A0r_fields,
  33996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33997         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33998         189,
  33999         -1,
  34000     },
  34001 #endif /* chips */
  34002 
  34003 #if defined(BCM_56370_A0)
  34004     { /* SOC_REG_INT_XLMIB_RVLN_BCM56370_A0r */
  34005         soc_block_list[16],
  34006         soc_portreg,
  34007         1,
  34008         0,
  34009         0x1f00,
  34010         SOC_REG_FLAG_64_BITS |
  34011                           SOC_REG_FLAG_COUNTER,
  34012         0,
  34013         1,
  34014         soc_R1023_BCM53400_A0r_fields,
  34015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34016         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34017         91,
  34018         -1,
  34019         3,
  34020     },
  34021 #endif /* chips */
  34022 
  34023 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  34024     { /* SOC_REG_INT_XLMIB_RVLN_BCM56980_A0r */
  34025         soc_block_list[16],
  34026         soc_portreg,
  34027         1,
  34028         0,
  34029         0x1f00,
  34030         SOC_REG_FLAG_64_BITS |
  34031                           SOC_REG_FLAG_COUNTER,
  34032         0,
  34033         1,
  34034         soc_R1023_BCM53400_A0r_fields,
  34035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34036         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34037         66,
  34038         -1,
  34039         3,
  34040     },
  34041 #endif /* chips */
  34042 
  34043 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34044     { /* SOC_REG_INT_XLMIB_RXCFr */
  34045         soc_block_list[16],
  34046         soc_portreg,
  34047         1,
  34048         0,
  34049         0x1000,
  34050         SOC_REG_FLAG_64_BITS |
  34051                           SOC_REG_FLAG_COUNTER,
  34052         0,
  34053         1,
  34054         soc_R1023_BCM53400_A0r_fields,
  34055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34056         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34057         75,
  34058         -1,
  34059         3,
  34060     },
  34061 #endif /* chips */
  34062 
  34063 #if defined(BCM_53570_A0)
  34064     { /* SOC_REG_INT_XLMIB_RXCF_BCM53570_A0r */
  34065         soc_block_list[16],
  34066         soc_portreg,
  34067         1,
  34068         0,
  34069         0x1000,
  34070         SOC_REG_FLAG_64_BITS |
  34071                           SOC_REG_FLAG_COUNTER,
  34072         0,
  34073         1,
  34074         soc_R1023_BCM53400_A0r_fields,
  34075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34076         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34077         170,
  34078         -1,
  34079     },
  34080 #endif /* chips */
  34081 
  34082 #if defined(BCM_53570_B0)
  34083     { /* SOC_REG_INT_XLMIB_RXCF_BCM53570_B0r */
  34084         soc_block_list[16],
  34085         soc_portreg,
  34086         1,
  34087         0,
  34088         0x1000,
  34089         SOC_REG_FLAG_64_BITS |
  34090                           SOC_REG_FLAG_COUNTER,
  34091         0,
  34092         1,
  34093         soc_R1023_BCM53400_A0r_fields,
  34094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34095         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34096         174,
  34097         -1,
  34098     },
  34099 #endif /* chips */
  34100 
  34101 #if defined(BCM_56370_A0)
  34102     { /* SOC_REG_INT_XLMIB_RXCF_BCM56370_A0r */
  34103         soc_block_list[16],
  34104         soc_portreg,
  34105         1,
  34106         0,
  34107         0x1000,
  34108         SOC_REG_FLAG_64_BITS |
  34109                           SOC_REG_FLAG_COUNTER,
  34110         0,
  34111         1,
  34112         soc_R1023_BCM53400_A0r_fields,
  34113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34114         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34115         76,
  34116         -1,
  34117         3,
  34118     },
  34119 #endif /* chips */
  34120 
  34121 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  34122     { /* SOC_REG_INT_XLMIB_RXCF_BCM56980_A0r */
  34123         soc_block_list[16],
  34124         soc_portreg,
  34125         1,
  34126         0,
  34127         0x1000,
  34128         SOC_REG_FLAG_64_BITS |
  34129                           SOC_REG_FLAG_COUNTER,
  34130         0,
  34131         1,
  34132         soc_R1023_BCM53400_A0r_fields,
  34133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34134         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34135         51,
  34136         -1,
  34137         3,
  34138     },
  34139 #endif /* chips */
  34140 
  34141 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34142     { /* SOC_REG_INT_XLMIB_RXPFr */
  34143         soc_block_list[16],
  34144         soc_portreg,
  34145         1,
  34146         0,
  34147         0x1100,
  34148         SOC_REG_FLAG_64_BITS |
  34149                           SOC_REG_FLAG_COUNTER,
  34150         0,
  34151         1,
  34152         soc_R1023_BCM53400_A0r_fields,
  34153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34154         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34155         76,
  34156         -1,
  34157         3,
  34158     },
  34159 #endif /* chips */
  34160 
  34161 #if defined(BCM_53570_A0)
  34162     { /* SOC_REG_INT_XLMIB_RXPF_BCM53570_A0r */
  34163         soc_block_list[16],
  34164         soc_portreg,
  34165         1,
  34166         0,
  34167         0x1100,
  34168         SOC_REG_FLAG_64_BITS |
  34169                           SOC_REG_FLAG_COUNTER,
  34170         0,
  34171         1,
  34172         soc_R1023_BCM53400_A0r_fields,
  34173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34174         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34175         171,
  34176         -1,
  34177     },
  34178 #endif /* chips */
  34179 
  34180 #if defined(BCM_53570_B0)
  34181     { /* SOC_REG_INT_XLMIB_RXPF_BCM53570_B0r */
  34182         soc_block_list[16],
  34183         soc_portreg,
  34184         1,
  34185         0,
  34186         0x1100,
  34187         SOC_REG_FLAG_64_BITS |
  34188                           SOC_REG_FLAG_COUNTER,
  34189         0,
  34190         1,
  34191         soc_R1023_BCM53400_A0r_fields,
  34192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34193         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34194         175,
  34195         -1,
  34196     },
  34197 #endif /* chips */
  34198 
  34199 #if defined(BCM_56370_A0)
  34200     { /* SOC_REG_INT_XLMIB_RXPF_BCM56370_A0r */
  34201         soc_block_list[16],
  34202         soc_portreg,
  34203         1,
  34204         0,
  34205         0x1100,
  34206         SOC_REG_FLAG_64_BITS |
  34207                           SOC_REG_FLAG_COUNTER,
  34208         0,
  34209         1,
  34210         soc_R1023_BCM53400_A0r_fields,
  34211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34212         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34213         77,
  34214         -1,
  34215         3,
  34216     },
  34217 #endif /* chips */
  34218 
  34219 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  34220     { /* SOC_REG_INT_XLMIB_RXPF_BCM56980_A0r */
  34221         soc_block_list[16],
  34222         soc_portreg,
  34223         1,
  34224         0,
  34225         0x1100,
  34226         SOC_REG_FLAG_64_BITS |
  34227                           SOC_REG_FLAG_COUNTER,
  34228         0,
  34229         1,
  34230         soc_R1023_BCM53400_A0r_fields,
  34231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34232         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34233         52,
  34234         -1,
  34235         3,
  34236     },
  34237 #endif /* chips */
  34238 
  34239 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34240     { /* SOC_REG_INT_XLMIB_RXPPr */
  34241         soc_block_list[16],
  34242         soc_portreg,
  34243         1,
  34244         0,
  34245         0x1200,
  34246         SOC_REG_FLAG_64_BITS |
  34247                           SOC_REG_FLAG_COUNTER,
  34248         0,
  34249         1,
  34250         soc_R1023_BCM53400_A0r_fields,
  34251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34252         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34253         77,
  34254         -1,
  34255         3,
  34256     },
  34257 #endif /* chips */
  34258 
  34259 #if defined(BCM_53570_A0)
  34260     { /* SOC_REG_INT_XLMIB_RXPP_BCM53570_A0r */
  34261         soc_block_list[16],
  34262         soc_portreg,
  34263         1,
  34264         0,
  34265         0x1200,
  34266         SOC_REG_FLAG_64_BITS |
  34267                           SOC_REG_FLAG_COUNTER,
  34268         0,
  34269         1,
  34270         soc_R1023_BCM53400_A0r_fields,
  34271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34272         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34273         172,
  34274         -1,
  34275     },
  34276 #endif /* chips */
  34277 
  34278 #if defined(BCM_53570_B0)
  34279     { /* SOC_REG_INT_XLMIB_RXPP_BCM53570_B0r */
  34280         soc_block_list[16],
  34281         soc_portreg,
  34282         1,
  34283         0,
  34284         0x1200,
  34285         SOC_REG_FLAG_64_BITS |
  34286                           SOC_REG_FLAG_COUNTER,
  34287         0,
  34288         1,
  34289         soc_R1023_BCM53400_A0r_fields,
  34290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34291         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34292         176,
  34293         -1,
  34294     },
  34295 #endif /* chips */
  34296 
  34297 #if defined(BCM_56370_A0)
  34298     { /* SOC_REG_INT_XLMIB_RXPP_BCM56370_A0r */
  34299         soc_block_list[16],
  34300         soc_portreg,
  34301         1,
  34302         0,
  34303         0x1200,
  34304         SOC_REG_FLAG_64_BITS |
  34305                           SOC_REG_FLAG_COUNTER,
  34306         0,
  34307         1,
  34308         soc_R1023_BCM53400_A0r_fields,
  34309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34310         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34311         78,
  34312         -1,
  34313         3,
  34314     },
  34315 #endif /* chips */
  34316 
  34317 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  34318     { /* SOC_REG_INT_XLMIB_RXPP_BCM56980_A0r */
  34319         soc_block_list[16],
  34320         soc_portreg,
  34321         1,
  34322         0,
  34323         0x1200,
  34324         SOC_REG_FLAG_64_BITS |
  34325                           SOC_REG_FLAG_COUNTER,
  34326         0,
  34327         1,
  34328         soc_R1023_BCM53400_A0r_fields,
  34329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34330         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34331         53,
  34332         -1,
  34333         3,
  34334     },
  34335 #endif /* chips */
  34336 
  34337 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34338     { /* SOC_REG_INT_XLMIB_RXUDAr */
  34339         soc_block_list[16],
  34340         soc_portreg,
  34341         1,
  34342         0,
  34343         0x1400,
  34344         SOC_REG_FLAG_64_BITS |
  34345                           SOC_REG_FLAG_COUNTER,
  34346         0,
  34347         1,
  34348         soc_R1023_BCM53400_A0r_fields,
  34349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34350         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34351         79,
  34352         -1,
  34353         3,
  34354     },
  34355 #endif /* chips */
  34356 
  34357 #if defined(BCM_53570_A0)
  34358     { /* SOC_REG_INT_XLMIB_RXUDA_BCM53570_A0r */
  34359         soc_block_list[16],
  34360         soc_portreg,
  34361         1,
  34362         0,
  34363         0x1400,
  34364         SOC_REG_FLAG_64_BITS |
  34365                           SOC_REG_FLAG_COUNTER,
  34366         0,
  34367         1,
  34368         soc_R1023_BCM53400_A0r_fields,
  34369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34370         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34371         174,
  34372         -1,
  34373     },
  34374 #endif /* chips */
  34375 
  34376 #if defined(BCM_53570_B0)
  34377     { /* SOC_REG_INT_XLMIB_RXUDA_BCM53570_B0r */
  34378         soc_block_list[16],
  34379         soc_portreg,
  34380         1,
  34381         0,
  34382         0x1400,
  34383         SOC_REG_FLAG_64_BITS |
  34384                           SOC_REG_FLAG_COUNTER,
  34385         0,
  34386         1,
  34387         soc_R1023_BCM53400_A0r_fields,
  34388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34389         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34390         178,
  34391         -1,
  34392     },
  34393 #endif /* chips */
  34394 
  34395 #if defined(BCM_56370_A0)
  34396     { /* SOC_REG_INT_XLMIB_RXUDA_BCM56370_A0r */
  34397         soc_block_list[16],
  34398         soc_portreg,
  34399         1,
  34400         0,
  34401         0x1400,
  34402         SOC_REG_FLAG_64_BITS |
  34403                           SOC_REG_FLAG_COUNTER,
  34404         0,
  34405         1,
  34406         soc_R1023_BCM53400_A0r_fields,
  34407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34408         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34409         80,
  34410         -1,
  34411         3,
  34412     },
  34413 #endif /* chips */
  34414 
  34415 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  34416     { /* SOC_REG_INT_XLMIB_RXUDA_BCM56980_A0r */
  34417         soc_block_list[16],
  34418         soc_portreg,
  34419         1,
  34420         0,
  34421         0x1400,
  34422         SOC_REG_FLAG_64_BITS |
  34423                           SOC_REG_FLAG_COUNTER,
  34424         0,
  34425         1,
  34426         soc_R1023_BCM53400_A0r_fields,
  34427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34429         55,
  34430         -1,
  34431         3,
  34432     },
  34433 #endif /* chips */
  34434 
  34435 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34436     { /* SOC_REG_INT_XLMIB_RXUOr */
  34437         soc_block_list[16],
  34438         soc_portreg,
  34439         1,
  34440         0,
  34441         0x1300,
  34442         SOC_REG_FLAG_64_BITS |
  34443                           SOC_REG_FLAG_COUNTER,
  34444         0,
  34445         1,
  34446         soc_R1023_BCM53400_A0r_fields,
  34447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34448         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34449         78,
  34450         -1,
  34451         3,
  34452     },
  34453 #endif /* chips */
  34454 
  34455 #if defined(BCM_53570_A0)
  34456     { /* SOC_REG_INT_XLMIB_RXUO_BCM53570_A0r */
  34457         soc_block_list[16],
  34458         soc_portreg,
  34459         1,
  34460         0,
  34461         0x1300,
  34462         SOC_REG_FLAG_64_BITS |
  34463                           SOC_REG_FLAG_COUNTER,
  34464         0,
  34465         1,
  34466         soc_R1023_BCM53400_A0r_fields,
  34467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34468         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34469         173,
  34470         -1,
  34471     },
  34472 #endif /* chips */
  34473 
  34474 #if defined(BCM_53570_B0)
  34475     { /* SOC_REG_INT_XLMIB_RXUO_BCM53570_B0r */
  34476         soc_block_list[16],
  34477         soc_portreg,
  34478         1,
  34479         0,
  34480         0x1300,
  34481         SOC_REG_FLAG_64_BITS |
  34482                           SOC_REG_FLAG_COUNTER,
  34483         0,
  34484         1,
  34485         soc_R1023_BCM53400_A0r_fields,
  34486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34488         177,
  34489         -1,
  34490     },
  34491 #endif /* chips */
  34492 
  34493 #if defined(BCM_56370_A0)
  34494     { /* SOC_REG_INT_XLMIB_RXUO_BCM56370_A0r */
  34495         soc_block_list[16],
  34496         soc_portreg,
  34497         1,
  34498         0,
  34499         0x1300,
  34500         SOC_REG_FLAG_64_BITS |
  34501                           SOC_REG_FLAG_COUNTER,
  34502         0,
  34503         1,
  34504         soc_R1023_BCM53400_A0r_fields,
  34505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34506         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34507         79,
  34508         -1,
  34509         3,
  34510     },
  34511 #endif /* chips */
  34512 
  34513 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  34514     { /* SOC_REG_INT_XLMIB_RXUO_BCM56980_A0r */
  34515         soc_block_list[16],
  34516         soc_portreg,
  34517         1,
  34518         0,
  34519         0x1300,
  34520         SOC_REG_FLAG_64_BITS |
  34521                           SOC_REG_FLAG_COUNTER,
  34522         0,
  34523         1,
  34524         soc_R1023_BCM53400_A0r_fields,
  34525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34526         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34527         54,
  34528         -1,
  34529         3,
  34530     },
  34531 #endif /* chips */
  34532 
  34533 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34534     { /* SOC_REG_INT_XLMIB_RXWSAr */
  34535         soc_block_list[16],
  34536         soc_portreg,
  34537         1,
  34538         0,
  34539         0x1500,
  34540         SOC_REG_FLAG_64_BITS |
  34541                           SOC_REG_FLAG_COUNTER,
  34542         0,
  34543         1,
  34544         soc_R1023_BCM53400_A0r_fields,
  34545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34546         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34547         80,
  34548         -1,
  34549         3,
  34550     },
  34551 #endif /* chips */
  34552 
  34553 #if defined(BCM_53570_A0)
  34554     { /* SOC_REG_INT_XLMIB_RXWSA_BCM53570_A0r */
  34555         soc_block_list[16],
  34556         soc_portreg,
  34557         1,
  34558         0,
  34559         0x1500,
  34560         SOC_REG_FLAG_64_BITS |
  34561                           SOC_REG_FLAG_COUNTER,
  34562         0,
  34563         1,
  34564         soc_R1023_BCM53400_A0r_fields,
  34565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34566         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34567         175,
  34568         -1,
  34569     },
  34570 #endif /* chips */
  34571 
  34572 #if defined(BCM_53570_B0)
  34573     { /* SOC_REG_INT_XLMIB_RXWSA_BCM53570_B0r */
  34574         soc_block_list[16],
  34575         soc_portreg,
  34576         1,
  34577         0,
  34578         0x1500,
  34579         SOC_REG_FLAG_64_BITS |
  34580                           SOC_REG_FLAG_COUNTER,
  34581         0,
  34582         1,
  34583         soc_R1023_BCM53400_A0r_fields,
  34584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34585         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34586         179,
  34587         -1,
  34588     },
  34589 #endif /* chips */
  34590 
  34591 #if defined(BCM_56370_A0)
  34592     { /* SOC_REG_INT_XLMIB_RXWSA_BCM56370_A0r */
  34593         soc_block_list[16],
  34594         soc_portreg,
  34595         1,
  34596         0,
  34597         0x1500,
  34598         SOC_REG_FLAG_64_BITS |
  34599                           SOC_REG_FLAG_COUNTER,
  34600         0,
  34601         1,
  34602         soc_R1023_BCM53400_A0r_fields,
  34603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34604         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34605         81,
  34606         -1,
  34607         3,
  34608     },
  34609 #endif /* chips */
  34610 
  34611 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  34612     { /* SOC_REG_INT_XLMIB_RXWSA_BCM56980_A0r */
  34613         soc_block_list[16],
  34614         soc_portreg,
  34615         1,
  34616         0,
  34617         0x1500,
  34618         SOC_REG_FLAG_64_BITS |
  34619                           SOC_REG_FLAG_COUNTER,
  34620         0,
  34621         1,
  34622         soc_R1023_BCM53400_A0r_fields,
  34623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34624         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34625         56,
  34626         -1,
  34627         3,
  34628     },
  34629 #endif /* chips */
  34630 
  34631 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34632     { /* SOC_REG_INT_XLMIB_RX_EEE_LPI_DURATION_COUNTERr */
  34633         soc_block_list[16],
  34634         soc_portreg,
  34635         1,
  34636         0,
  34637         0x3700,
  34638         SOC_REG_FLAG_64_BITS |
  34639                           SOC_REG_FLAG_COUNTER,
  34640         0,
  34641         1,
  34642         soc_R1023_BCM53400_A0r_fields,
  34643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34644         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34645         114,
  34646         -1,
  34647         3,
  34648     },
  34649 #endif /* chips */
  34650 
  34651 #if defined(BCM_53570_A0)
  34652     { /* SOC_REG_INT_XLMIB_RX_EEE_LPI_DURATION_COUNTER_BCM53570_A0r */
  34653         soc_block_list[16],
  34654         soc_portreg,
  34655         1,
  34656         0,
  34657         0x3700,
  34658         SOC_REG_FLAG_64_BITS |
  34659                           SOC_REG_FLAG_COUNTER,
  34660         0,
  34661         1,
  34662         soc_R1023_BCM53400_A0r_fields,
  34663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34664         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34665         209,
  34666         -1,
  34667     },
  34668 #endif /* chips */
  34669 
  34670 #if defined(BCM_53570_B0)
  34671     { /* SOC_REG_INT_XLMIB_RX_EEE_LPI_DURATION_COUNTER_BCM53570_B0r */
  34672         soc_block_list[16],
  34673         soc_portreg,
  34674         1,
  34675         0,
  34676         0x3700,
  34677         SOC_REG_FLAG_64_BITS |
  34678                           SOC_REG_FLAG_COUNTER,
  34679         0,
  34680         1,
  34681         soc_R1023_BCM53400_A0r_fields,
  34682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34683         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34684         213,
  34685         -1,
  34686     },
  34687 #endif /* chips */
  34688 
  34689 #if defined(BCM_56370_A0)
  34690     { /* SOC_REG_INT_XLMIB_RX_EEE_LPI_DURATION_COUNTER_BCM56370_A0r */
  34691         soc_block_list[16],
  34692         soc_portreg,
  34693         1,
  34694         0,
  34695         0x3700,
  34696         SOC_REG_FLAG_64_BITS |
  34697                           SOC_REG_FLAG_COUNTER,
  34698         0,
  34699         1,
  34700         soc_R1023_BCM53400_A0r_fields,
  34701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34702         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34703         115,
  34704         -1,
  34705         3,
  34706     },
  34707 #endif /* chips */
  34708 
  34709 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  34710     { /* SOC_REG_INT_XLMIB_RX_EEE_LPI_DURATION_COUNTER_BCM56980_A0r */
  34711         soc_block_list[16],
  34712         soc_portreg,
  34713         1,
  34714         0,
  34715         0x3700,
  34716         SOC_REG_FLAG_64_BITS |
  34717                           SOC_REG_FLAG_COUNTER,
  34718         0,
  34719         1,
  34720         soc_R1023_BCM53400_A0r_fields,
  34721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34722         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34723         90,
  34724         -1,
  34725         3,
  34726     },
  34727 #endif /* chips */
  34728 
  34729 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34730     { /* SOC_REG_INT_XLMIB_RX_EEE_LPI_EVENT_COUNTERr */
  34731         soc_block_list[16],
  34732         soc_portreg,
  34733         1,
  34734         0,
  34735         0x3600,
  34736         SOC_REG_FLAG_64_BITS |
  34737                           SOC_REG_FLAG_COUNTER,
  34738         0,
  34739         1,
  34740         soc_R1023_BCM53400_A0r_fields,
  34741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34742         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34743         113,
  34744         -1,
  34745         3,
  34746     },
  34747 #endif /* chips */
  34748 
  34749 #if defined(BCM_53570_A0)
  34750     { /* SOC_REG_INT_XLMIB_RX_EEE_LPI_EVENT_COUNTER_BCM53570_A0r */
  34751         soc_block_list[16],
  34752         soc_portreg,
  34753         1,
  34754         0,
  34755         0x3600,
  34756         SOC_REG_FLAG_64_BITS |
  34757                           SOC_REG_FLAG_COUNTER,
  34758         0,
  34759         1,
  34760         soc_R1023_BCM53400_A0r_fields,
  34761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34762         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34763         208,
  34764         -1,
  34765     },
  34766 #endif /* chips */
  34767 
  34768 #if defined(BCM_53570_B0)
  34769     { /* SOC_REG_INT_XLMIB_RX_EEE_LPI_EVENT_COUNTER_BCM53570_B0r */
  34770         soc_block_list[16],
  34771         soc_portreg,
  34772         1,
  34773         0,
  34774         0x3600,
  34775         SOC_REG_FLAG_64_BITS |
  34776                           SOC_REG_FLAG_COUNTER,
  34777         0,
  34778         1,
  34779         soc_R1023_BCM53400_A0r_fields,
  34780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34782         212,
  34783         -1,
  34784     },
  34785 #endif /* chips */
  34786 
  34787 #if defined(BCM_56370_A0)
  34788     { /* SOC_REG_INT_XLMIB_RX_EEE_LPI_EVENT_COUNTER_BCM56370_A0r */
  34789         soc_block_list[16],
  34790         soc_portreg,
  34791         1,
  34792         0,
  34793         0x3600,
  34794         SOC_REG_FLAG_64_BITS |
  34795                           SOC_REG_FLAG_COUNTER,
  34796         0,
  34797         1,
  34798         soc_R1023_BCM53400_A0r_fields,
  34799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34800         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34801         114,
  34802         -1,
  34803         3,
  34804     },
  34805 #endif /* chips */
  34806 
  34807 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  34808     { /* SOC_REG_INT_XLMIB_RX_EEE_LPI_EVENT_COUNTER_BCM56980_A0r */
  34809         soc_block_list[16],
  34810         soc_portreg,
  34811         1,
  34812         0,
  34813         0x3600,
  34814         SOC_REG_FLAG_64_BITS |
  34815                           SOC_REG_FLAG_COUNTER,
  34816         0,
  34817         1,
  34818         soc_R1023_BCM53400_A0r_fields,
  34819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34820         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34821         89,
  34822         -1,
  34823         3,
  34824     },
  34825 #endif /* chips */
  34826 
  34827 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34828     { /* SOC_REG_INT_XLMIB_RX_HCFC_COUNTERr */
  34829         soc_block_list[16],
  34830         soc_portreg,
  34831         1,
  34832         0,
  34833         0x3b00,
  34834         SOC_REG_FLAG_64_BITS |
  34835                           SOC_REG_FLAG_COUNTER,
  34836         0,
  34837         1,
  34838         soc_R1023_BCM53400_A0r_fields,
  34839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34840         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34841         118,
  34842         -1,
  34843         3,
  34844     },
  34845 #endif /* chips */
  34846 
  34847 #if defined(BCM_53570_A0)
  34848     { /* SOC_REG_INT_XLMIB_RX_HCFC_COUNTER_BCM53570_A0r */
  34849         soc_block_list[16],
  34850         soc_portreg,
  34851         1,
  34852         0,
  34853         0x3b00,
  34854         SOC_REG_FLAG_64_BITS |
  34855                           SOC_REG_FLAG_COUNTER,
  34856         0,
  34857         1,
  34858         soc_XLMIB_RSCHCRCr_fields,
  34859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34860         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34861         213,
  34862         -1,
  34863     },
  34864 #endif /* chips */
  34865 
  34866 #if defined(BCM_53570_B0)
  34867     { /* SOC_REG_INT_XLMIB_RX_HCFC_COUNTER_BCM53570_B0r */
  34868         soc_block_list[16],
  34869         soc_portreg,
  34870         1,
  34871         0,
  34872         0x3b00,
  34873         SOC_REG_FLAG_64_BITS |
  34874                           SOC_REG_FLAG_COUNTER,
  34875         0,
  34876         1,
  34877         soc_XLMIB_RSCHCRCr_fields,
  34878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34879         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34880         217,
  34881         -1,
  34882     },
  34883 #endif /* chips */
  34884 
  34885 #if defined(BCM_56370_A0)
  34886     { /* SOC_REG_INT_XLMIB_RX_HCFC_COUNTER_BCM56370_A0r */
  34887         soc_block_list[16],
  34888         soc_portreg,
  34889         1,
  34890         0,
  34891         0x3b00,
  34892         SOC_REG_FLAG_64_BITS |
  34893                           SOC_REG_FLAG_COUNTER,
  34894         0,
  34895         1,
  34896         soc_R1023_BCM53400_A0r_fields,
  34897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34898         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34899         119,
  34900         -1,
  34901         3,
  34902     },
  34903 #endif /* chips */
  34904 
  34905 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  34906     { /* SOC_REG_INT_XLMIB_RX_HCFC_COUNTER_BCM56980_A0r */
  34907         soc_block_list[16],
  34908         soc_portreg,
  34909         1,
  34910         0,
  34911         0x3b00,
  34912         SOC_REG_FLAG_64_BITS |
  34913                           SOC_REG_FLAG_COUNTER,
  34914         0,
  34915         1,
  34916         soc_R1023_BCM53400_A0r_fields,
  34917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34918         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34919         94,
  34920         -1,
  34921         3,
  34922     },
  34923 #endif /* chips */
  34924 
  34925 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  34926     { /* SOC_REG_INT_XLMIB_RX_HCFC_CRC_COUNTERr */
  34927         soc_block_list[16],
  34928         soc_portreg,
  34929         1,
  34930         0,
  34931         0x3c00,
  34932         SOC_REG_FLAG_64_BITS |
  34933                           SOC_REG_FLAG_COUNTER,
  34934         0,
  34935         1,
  34936         soc_R1023_BCM53400_A0r_fields,
  34937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34938         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34939         119,
  34940         -1,
  34941         3,
  34942     },
  34943 #endif /* chips */
  34944 
  34945 #if defined(BCM_53570_A0)
  34946     { /* SOC_REG_INT_XLMIB_RX_HCFC_CRC_COUNTER_BCM53570_A0r */
  34947         soc_block_list[16],
  34948         soc_portreg,
  34949         1,
  34950         0,
  34951         0x3c00,
  34952         SOC_REG_FLAG_64_BITS |
  34953                           SOC_REG_FLAG_COUNTER,
  34954         0,
  34955         1,
  34956         soc_XLMIB_RSCHCRCr_fields,
  34957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34958         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34959         214,
  34960         -1,
  34961     },
  34962 #endif /* chips */
  34963 
  34964 #if defined(BCM_53570_B0)
  34965     { /* SOC_REG_INT_XLMIB_RX_HCFC_CRC_COUNTER_BCM53570_B0r */
  34966         soc_block_list[16],
  34967         soc_portreg,
  34968         1,
  34969         0,
  34970         0x3c00,
  34971         SOC_REG_FLAG_64_BITS |
  34972                           SOC_REG_FLAG_COUNTER,
  34973         0,
  34974         1,
  34975         soc_XLMIB_RSCHCRCr_fields,
  34976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34977         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34978         218,
  34979         -1,
  34980     },
  34981 #endif /* chips */
  34982 
  34983 #if defined(BCM_56370_A0)
  34984     { /* SOC_REG_INT_XLMIB_RX_HCFC_CRC_COUNTER_BCM56370_A0r */
  34985         soc_block_list[16],
  34986         soc_portreg,
  34987         1,
  34988         0,
  34989         0x3c00,
  34990         SOC_REG_FLAG_64_BITS |
  34991                           SOC_REG_FLAG_COUNTER,
  34992         0,
  34993         1,
  34994         soc_R1023_BCM53400_A0r_fields,
  34995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34996         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  34997         120,
  34998         -1,
  34999         3,
  35000     },
  35001 #endif /* chips */
  35002 
  35003 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  35004     { /* SOC_REG_INT_XLMIB_RX_HCFC_CRC_COUNTER_BCM56980_A0r */
  35005         soc_block_list[16],
  35006         soc_portreg,
  35007         1,
  35008         0,
  35009         0x3c00,
  35010         SOC_REG_FLAG_64_BITS |
  35011                           SOC_REG_FLAG_COUNTER,
  35012         0,
  35013         1,
  35014         soc_R1023_BCM53400_A0r_fields,
  35015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35016         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35017         95,
  35018         -1,
  35019         3,
  35020     },
  35021 #endif /* chips */
  35022 
  35023 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35024     { /* SOC_REG_INT_XLMIB_RX_LLFC_CRC_COUNTERr */
  35025         soc_block_list[16],
  35026         soc_portreg,
  35027         1,
  35028         0,
  35029         0x3a00,
  35030         SOC_REG_FLAG_64_BITS |
  35031                           SOC_REG_FLAG_COUNTER,
  35032         0,
  35033         1,
  35034         soc_R1023_BCM53400_A0r_fields,
  35035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35036         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35037         117,
  35038         -1,
  35039         3,
  35040     },
  35041 #endif /* chips */
  35042 
  35043 #if defined(BCM_53570_A0)
  35044     { /* SOC_REG_INT_XLMIB_RX_LLFC_CRC_COUNTER_BCM53570_A0r */
  35045         soc_block_list[16],
  35046         soc_portreg,
  35047         1,
  35048         0,
  35049         0x3a00,
  35050         SOC_REG_FLAG_64_BITS |
  35051                           SOC_REG_FLAG_COUNTER,
  35052         0,
  35053         1,
  35054         soc_R1023_BCM53400_A0r_fields,
  35055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35056         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35057         212,
  35058         -1,
  35059     },
  35060 #endif /* chips */
  35061 
  35062 #if defined(BCM_53570_B0)
  35063     { /* SOC_REG_INT_XLMIB_RX_LLFC_CRC_COUNTER_BCM53570_B0r */
  35064         soc_block_list[16],
  35065         soc_portreg,
  35066         1,
  35067         0,
  35068         0x3a00,
  35069         SOC_REG_FLAG_64_BITS |
  35070                           SOC_REG_FLAG_COUNTER,
  35071         0,
  35072         1,
  35073         soc_R1023_BCM53400_A0r_fields,
  35074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35075         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35076         216,
  35077         -1,
  35078     },
  35079 #endif /* chips */
  35080 
  35081 #if defined(BCM_56370_A0)
  35082     { /* SOC_REG_INT_XLMIB_RX_LLFC_CRC_COUNTER_BCM56370_A0r */
  35083         soc_block_list[16],
  35084         soc_portreg,
  35085         1,
  35086         0,
  35087         0x3a00,
  35088         SOC_REG_FLAG_64_BITS |
  35089                           SOC_REG_FLAG_COUNTER,
  35090         0,
  35091         1,
  35092         soc_R1023_BCM53400_A0r_fields,
  35093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35094         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35095         118,
  35096         -1,
  35097         3,
  35098     },
  35099 #endif /* chips */
  35100 
  35101 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  35102     { /* SOC_REG_INT_XLMIB_RX_LLFC_CRC_COUNTER_BCM56980_A0r */
  35103         soc_block_list[16],
  35104         soc_portreg,
  35105         1,
  35106         0,
  35107         0x3a00,
  35108         SOC_REG_FLAG_64_BITS |
  35109                           SOC_REG_FLAG_COUNTER,
  35110         0,
  35111         1,
  35112         soc_R1023_BCM53400_A0r_fields,
  35113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35114         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35115         93,
  35116         -1,
  35117         3,
  35118     },
  35119 #endif /* chips */
  35120 
  35121 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35122     { /* SOC_REG_INT_XLMIB_RX_LLFC_LOG_COUNTERr */
  35123         soc_block_list[16],
  35124         soc_portreg,
  35125         1,
  35126         0,
  35127         0x3900,
  35128         SOC_REG_FLAG_64_BITS |
  35129                           SOC_REG_FLAG_COUNTER,
  35130         0,
  35131         1,
  35132         soc_R1023_BCM53400_A0r_fields,
  35133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35134         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35135         116,
  35136         -1,
  35137         3,
  35138     },
  35139 #endif /* chips */
  35140 
  35141 #if defined(BCM_53570_A0)
  35142     { /* SOC_REG_INT_XLMIB_RX_LLFC_LOG_COUNTER_BCM53570_A0r */
  35143         soc_block_list[16],
  35144         soc_portreg,
  35145         1,
  35146         0,
  35147         0x3900,
  35148         SOC_REG_FLAG_64_BITS |
  35149                           SOC_REG_FLAG_COUNTER,
  35150         0,
  35151         1,
  35152         soc_R1023_BCM53400_A0r_fields,
  35153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35154         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35155         211,
  35156         -1,
  35157     },
  35158 #endif /* chips */
  35159 
  35160 #if defined(BCM_53570_B0)
  35161     { /* SOC_REG_INT_XLMIB_RX_LLFC_LOG_COUNTER_BCM53570_B0r */
  35162         soc_block_list[16],
  35163         soc_portreg,
  35164         1,
  35165         0,
  35166         0x3900,
  35167         SOC_REG_FLAG_64_BITS |
  35168                           SOC_REG_FLAG_COUNTER,
  35169         0,
  35170         1,
  35171         soc_R1023_BCM53400_A0r_fields,
  35172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35174         215,
  35175         -1,
  35176     },
  35177 #endif /* chips */
  35178 
  35179 #if defined(BCM_56370_A0)
  35180     { /* SOC_REG_INT_XLMIB_RX_LLFC_LOG_COUNTER_BCM56370_A0r */
  35181         soc_block_list[16],
  35182         soc_portreg,
  35183         1,
  35184         0,
  35185         0x3900,
  35186         SOC_REG_FLAG_64_BITS |
  35187                           SOC_REG_FLAG_COUNTER,
  35188         0,
  35189         1,
  35190         soc_R1023_BCM53400_A0r_fields,
  35191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35192         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35193         117,
  35194         -1,
  35195         3,
  35196     },
  35197 #endif /* chips */
  35198 
  35199 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  35200     { /* SOC_REG_INT_XLMIB_RX_LLFC_LOG_COUNTER_BCM56980_A0r */
  35201         soc_block_list[16],
  35202         soc_portreg,
  35203         1,
  35204         0,
  35205         0x3900,
  35206         SOC_REG_FLAG_64_BITS |
  35207                           SOC_REG_FLAG_COUNTER,
  35208         0,
  35209         1,
  35210         soc_R1023_BCM53400_A0r_fields,
  35211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35212         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35213         92,
  35214         -1,
  35215         3,
  35216     },
  35217 #endif /* chips */
  35218 
  35219 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35220     { /* SOC_REG_INT_XLMIB_RX_LLFC_PHY_COUNTERr */
  35221         soc_block_list[16],
  35222         soc_portreg,
  35223         1,
  35224         0,
  35225         0x3800,
  35226         SOC_REG_FLAG_64_BITS |
  35227                           SOC_REG_FLAG_COUNTER,
  35228         0,
  35229         1,
  35230         soc_R1023_BCM53400_A0r_fields,
  35231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35232         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35233         115,
  35234         -1,
  35235         3,
  35236     },
  35237 #endif /* chips */
  35238 
  35239 #if defined(BCM_53570_A0)
  35240     { /* SOC_REG_INT_XLMIB_RX_LLFC_PHY_COUNTER_BCM53570_A0r */
  35241         soc_block_list[16],
  35242         soc_portreg,
  35243         1,
  35244         0,
  35245         0x3800,
  35246         SOC_REG_FLAG_64_BITS |
  35247                           SOC_REG_FLAG_COUNTER,
  35248         0,
  35249         1,
  35250         soc_R1023_BCM53400_A0r_fields,
  35251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35252         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35253         210,
  35254         -1,
  35255     },
  35256 #endif /* chips */
  35257 
  35258 #if defined(BCM_53570_B0)
  35259     { /* SOC_REG_INT_XLMIB_RX_LLFC_PHY_COUNTER_BCM53570_B0r */
  35260         soc_block_list[16],
  35261         soc_portreg,
  35262         1,
  35263         0,
  35264         0x3800,
  35265         SOC_REG_FLAG_64_BITS |
  35266                           SOC_REG_FLAG_COUNTER,
  35267         0,
  35268         1,
  35269         soc_R1023_BCM53400_A0r_fields,
  35270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35271         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35272         214,
  35273         -1,
  35274     },
  35275 #endif /* chips */
  35276 
  35277 #if defined(BCM_56370_A0)
  35278     { /* SOC_REG_INT_XLMIB_RX_LLFC_PHY_COUNTER_BCM56370_A0r */
  35279         soc_block_list[16],
  35280         soc_portreg,
  35281         1,
  35282         0,
  35283         0x3800,
  35284         SOC_REG_FLAG_64_BITS |
  35285                           SOC_REG_FLAG_COUNTER,
  35286         0,
  35287         1,
  35288         soc_R1023_BCM53400_A0r_fields,
  35289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35290         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35291         116,
  35292         -1,
  35293         3,
  35294     },
  35295 #endif /* chips */
  35296 
  35297 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  35298     { /* SOC_REG_INT_XLMIB_RX_LLFC_PHY_COUNTER_BCM56980_A0r */
  35299         soc_block_list[16],
  35300         soc_portreg,
  35301         1,
  35302         0,
  35303         0x3800,
  35304         SOC_REG_FLAG_64_BITS |
  35305                           SOC_REG_FLAG_COUNTER,
  35306         0,
  35307         1,
  35308         soc_R1023_BCM53400_A0r_fields,
  35309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35310         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35311         91,
  35312         -1,
  35313         3,
  35314     },
  35315 #endif /* chips */
  35316 
  35317 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35318     { /* SOC_REG_INT_XLMIB_T64r */
  35319         soc_block_list[16],
  35320         soc_portreg,
  35321         1,
  35322         0,
  35323         0x4000,
  35324         SOC_REG_FLAG_64_BITS |
  35325                           SOC_REG_FLAG_COUNTER,
  35326         0,
  35327         1,
  35328         soc_R1023_BCM53400_A0r_fields,
  35329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35330         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35331         123,
  35332         -1,
  35333         3,
  35334     },
  35335 #endif /* chips */
  35336 
  35337 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35338     { /* SOC_REG_INT_XLMIB_T127r */
  35339         soc_block_list[16],
  35340         soc_portreg,
  35341         1,
  35342         0,
  35343         0x4100,
  35344         SOC_REG_FLAG_64_BITS |
  35345                           SOC_REG_FLAG_COUNTER,
  35346         0,
  35347         1,
  35348         soc_R1023_BCM53400_A0r_fields,
  35349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35350         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35351         124,
  35352         -1,
  35353         3,
  35354     },
  35355 #endif /* chips */
  35356 
  35357 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35358     { /* SOC_REG_INT_XLMIB_T255r */
  35359         soc_block_list[16],
  35360         soc_portreg,
  35361         1,
  35362         0,
  35363         0x4200,
  35364         SOC_REG_FLAG_64_BITS |
  35365                           SOC_REG_FLAG_COUNTER,
  35366         0,
  35367         1,
  35368         soc_R1023_BCM53400_A0r_fields,
  35369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35370         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35371         125,
  35372         -1,
  35373         3,
  35374     },
  35375 #endif /* chips */
  35376 
  35377 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35378     { /* SOC_REG_INT_XLMIB_T511r */
  35379         soc_block_list[16],
  35380         soc_portreg,
  35381         1,
  35382         0,
  35383         0x4300,
  35384         SOC_REG_FLAG_64_BITS |
  35385                           SOC_REG_FLAG_COUNTER,
  35386         0,
  35387         1,
  35388         soc_R1023_BCM53400_A0r_fields,
  35389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35390         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35391         126,
  35392         -1,
  35393         3,
  35394     },
  35395 #endif /* chips */
  35396 
  35397 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35398     { /* SOC_REG_INT_XLMIB_T1023r */
  35399         soc_block_list[16],
  35400         soc_portreg,
  35401         1,
  35402         0,
  35403         0x4400,
  35404         SOC_REG_FLAG_64_BITS |
  35405                           SOC_REG_FLAG_COUNTER,
  35406         0,
  35407         1,
  35408         soc_R1023_BCM53400_A0r_fields,
  35409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35410         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35411         127,
  35412         -1,
  35413         3,
  35414     },
  35415 #endif /* chips */
  35416 
  35417 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35418     { /* SOC_REG_INT_XLMIB_T1518r */
  35419         soc_block_list[16],
  35420         soc_portreg,
  35421         1,
  35422         0,
  35423         0x4500,
  35424         SOC_REG_FLAG_64_BITS |
  35425                           SOC_REG_FLAG_COUNTER,
  35426         0,
  35427         1,
  35428         soc_R1023_BCM53400_A0r_fields,
  35429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35430         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35431         128,
  35432         -1,
  35433         3,
  35434     },
  35435 #endif /* chips */
  35436 
  35437 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35438     { /* SOC_REG_INT_XLMIB_T2047r */
  35439         soc_block_list[16],
  35440         soc_portreg,
  35441         1,
  35442         0,
  35443         0x4700,
  35444         SOC_REG_FLAG_64_BITS |
  35445                           SOC_REG_FLAG_COUNTER,
  35446         0,
  35447         1,
  35448         soc_R1023_BCM53400_A0r_fields,
  35449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35450         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35451         130,
  35452         -1,
  35453         3,
  35454     },
  35455 #endif /* chips */
  35456 
  35457 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35458     { /* SOC_REG_INT_XLMIB_T4095r */
  35459         soc_block_list[16],
  35460         soc_portreg,
  35461         1,
  35462         0,
  35463         0x4800,
  35464         SOC_REG_FLAG_64_BITS |
  35465                           SOC_REG_FLAG_COUNTER,
  35466         0,
  35467         1,
  35468         soc_R1023_BCM53400_A0r_fields,
  35469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35470         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35471         131,
  35472         -1,
  35473         3,
  35474     },
  35475 #endif /* chips */
  35476 
  35477 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35478     { /* SOC_REG_INT_XLMIB_T9216r */
  35479         soc_block_list[16],
  35480         soc_portreg,
  35481         1,
  35482         0,
  35483         0x4900,
  35484         SOC_REG_FLAG_64_BITS |
  35485                           SOC_REG_FLAG_COUNTER,
  35486         0,
  35487         1,
  35488         soc_R1023_BCM53400_A0r_fields,
  35489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35490         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35491         132,
  35492         -1,
  35493         3,
  35494     },
  35495 #endif /* chips */
  35496 
  35497 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  35498     { /* SOC_REG_INT_XLMIB_T16383r */
  35499         soc_block_list[16],
  35500         soc_portreg,
  35501         1,
  35502         0,
  35503         0x4a00,
  35504         SOC_REG_FLAG_64_BITS |
  35505                           SOC_REG_FLAG_COUNTER,
  35506         0,
  35507         1,
  35508         soc_R1023_BCM53400_A0r_fields,
  35509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35510         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35511         133,
  35512         -1,
  35513         3,
  35514     },
  35515 #endif /* chips */
  35516 
  35517 #if defined(BCM_53570_A0)
  35518     { /* SOC_REG_INT_XLMIB_T1023_BCM53570_A0r */
  35519         soc_block_list[16],
  35520         soc_portreg,
  35521         1,
  35522         0,
  35523         0x4400,
  35524         SOC_REG_FLAG_64_BITS |
  35525                           SOC_REG_FLAG_COUNTER,
  35526         0,
  35527         1,
  35528         soc_R1023_BCM53400_A0r_fields,
  35529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35530         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35531         222,
  35532         -1,
  35533     },
  35534 #endif /* chips */
  35535 
  35536 #if defined(BCM_53570_B0)
  35537     { /* SOC_REG_INT_XLMIB_T1023_BCM53570_B0r */
  35538         soc_block_list[16],
  35539         soc_portreg,
  35540         1,
  35541         0,
  35542         0x4400,
  35543         SOC_REG_FLAG_64_BITS |
  35544                           SOC_REG_FLAG_COUNTER,
  35545         0,
  35546         1,
  35547         soc_R1023_BCM53400_A0r_fields,
  35548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35549         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35550         226,
  35551         -1,
  35552     },
  35553 #endif /* chips */
  35554 
  35555 #if defined(BCM_56370_A0)
  35556     { /* SOC_REG_INT_XLMIB_T1023_BCM56370_A0r */
  35557         soc_block_list[16],
  35558         soc_portreg,
  35559         1,
  35560         0,
  35561         0x4400,
  35562         SOC_REG_FLAG_64_BITS |
  35563                           SOC_REG_FLAG_COUNTER,
  35564         0,
  35565         1,
  35566         soc_R1023_BCM53400_A0r_fields,
  35567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35568         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35569         128,
  35570         -1,
  35571         3,
  35572     },
  35573 #endif /* chips */
  35574 
  35575 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  35576     { /* SOC_REG_INT_XLMIB_T1023_BCM56980_A0r */
  35577         soc_block_list[16],
  35578         soc_portreg,
  35579         1,
  35580         0,
  35581         0x4400,
  35582         SOC_REG_FLAG_64_BITS |
  35583                           SOC_REG_FLAG_COUNTER,
  35584         0,
  35585         1,
  35586         soc_R1023_BCM53400_A0r_fields,
  35587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35588         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35589         103,
  35590         -1,
  35591         3,
  35592     },
  35593 #endif /* chips */
  35594 
  35595 #if defined(BCM_53570_A0)
  35596     { /* SOC_REG_INT_XLMIB_T127_BCM53570_A0r */
  35597         soc_block_list[16],
  35598         soc_portreg,
  35599         1,
  35600         0,
  35601         0x4100,
  35602         SOC_REG_FLAG_64_BITS |
  35603                           SOC_REG_FLAG_COUNTER,
  35604         0,
  35605         1,
  35606         soc_R1023_BCM53400_A0r_fields,
  35607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35608         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35609         219,
  35610         -1,
  35611     },
  35612 #endif /* chips */
  35613 
  35614 #if defined(BCM_53570_B0)
  35615     { /* SOC_REG_INT_XLMIB_T127_BCM53570_B0r */
  35616         soc_block_list[16],
  35617         soc_portreg,
  35618         1,
  35619         0,
  35620         0x4100,
  35621         SOC_REG_FLAG_64_BITS |
  35622                           SOC_REG_FLAG_COUNTER,
  35623         0,
  35624         1,
  35625         soc_R1023_BCM53400_A0r_fields,
  35626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35628         223,
  35629         -1,
  35630     },
  35631 #endif /* chips */
  35632 
  35633 #if defined(BCM_56370_A0)
  35634     { /* SOC_REG_INT_XLMIB_T127_BCM56370_A0r */
  35635         soc_block_list[16],
  35636         soc_portreg,
  35637         1,
  35638         0,
  35639         0x4100,
  35640         SOC_REG_FLAG_64_BITS |
  35641                           SOC_REG_FLAG_COUNTER,
  35642         0,
  35643         1,
  35644         soc_R1023_BCM53400_A0r_fields,
  35645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35646         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35647         125,
  35648         -1,
  35649         3,
  35650     },
  35651 #endif /* chips */
  35652 
  35653 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  35654     { /* SOC_REG_INT_XLMIB_T127_BCM56980_A0r */
  35655         soc_block_list[16],
  35656         soc_portreg,
  35657         1,
  35658         0,
  35659         0x4100,
  35660         SOC_REG_FLAG_64_BITS |
  35661                           SOC_REG_FLAG_COUNTER,
  35662         0,
  35663         1,
  35664         soc_R1023_BCM53400_A0r_fields,
  35665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35666         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35667         100,
  35668         -1,
  35669         3,
  35670     },
  35671 #endif /* chips */
  35672 
  35673 #if defined(BCM_53570_A0)
  35674     { /* SOC_REG_INT_XLMIB_T1518_BCM53570_A0r */
  35675         soc_block_list[16],
  35676         soc_portreg,
  35677         1,
  35678         0,
  35679         0x4500,
  35680         SOC_REG_FLAG_64_BITS |
  35681                           SOC_REG_FLAG_COUNTER,
  35682         0,
  35683         1,
  35684         soc_R1023_BCM53400_A0r_fields,
  35685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35686         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35687         223,
  35688         -1,
  35689     },
  35690 #endif /* chips */
  35691 
  35692 #if defined(BCM_53570_B0)
  35693     { /* SOC_REG_INT_XLMIB_T1518_BCM53570_B0r */
  35694         soc_block_list[16],
  35695         soc_portreg,
  35696         1,
  35697         0,
  35698         0x4500,
  35699         SOC_REG_FLAG_64_BITS |
  35700                           SOC_REG_FLAG_COUNTER,
  35701         0,
  35702         1,
  35703         soc_R1023_BCM53400_A0r_fields,
  35704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35706         227,
  35707         -1,
  35708     },
  35709 #endif /* chips */
  35710 
  35711 #if defined(BCM_56370_A0)
  35712     { /* SOC_REG_INT_XLMIB_T1518_BCM56370_A0r */
  35713         soc_block_list[16],
  35714         soc_portreg,
  35715         1,
  35716         0,
  35717         0x4500,
  35718         SOC_REG_FLAG_64_BITS |
  35719                           SOC_REG_FLAG_COUNTER,
  35720         0,
  35721         1,
  35722         soc_R1023_BCM53400_A0r_fields,
  35723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35724         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35725         129,
  35726         -1,
  35727         3,
  35728     },
  35729 #endif /* chips */
  35730 
  35731 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  35732     { /* SOC_REG_INT_XLMIB_T1518_BCM56980_A0r */
  35733         soc_block_list[16],
  35734         soc_portreg,
  35735         1,
  35736         0,
  35737         0x4500,
  35738         SOC_REG_FLAG_64_BITS |
  35739                           SOC_REG_FLAG_COUNTER,
  35740         0,
  35741         1,
  35742         soc_R1023_BCM53400_A0r_fields,
  35743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35744         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35745         104,
  35746         -1,
  35747         3,
  35748     },
  35749 #endif /* chips */
  35750 
  35751 #if defined(BCM_53570_A0)
  35752     { /* SOC_REG_INT_XLMIB_T16383_BCM53570_A0r */
  35753         soc_block_list[16],
  35754         soc_portreg,
  35755         1,
  35756         0,
  35757         0x4a00,
  35758         SOC_REG_FLAG_64_BITS |
  35759                           SOC_REG_FLAG_COUNTER,
  35760         0,
  35761         1,
  35762         soc_R1023_BCM53400_A0r_fields,
  35763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35764         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35765         228,
  35766         -1,
  35767     },
  35768 #endif /* chips */
  35769 
  35770 #if defined(BCM_53570_B0)
  35771     { /* SOC_REG_INT_XLMIB_T16383_BCM53570_B0r */
  35772         soc_block_list[16],
  35773         soc_portreg,
  35774         1,
  35775         0,
  35776         0x4a00,
  35777         SOC_REG_FLAG_64_BITS |
  35778                           SOC_REG_FLAG_COUNTER,
  35779         0,
  35780         1,
  35781         soc_R1023_BCM53400_A0r_fields,
  35782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35783         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35784         232,
  35785         -1,
  35786     },
  35787 #endif /* chips */
  35788 
  35789 #if defined(BCM_56370_A0)
  35790     { /* SOC_REG_INT_XLMIB_T16383_BCM56370_A0r */
  35791         soc_block_list[16],
  35792         soc_portreg,
  35793         1,
  35794         0,
  35795         0x4a00,
  35796         SOC_REG_FLAG_64_BITS |
  35797                           SOC_REG_FLAG_COUNTER,
  35798         0,
  35799         1,
  35800         soc_R1023_BCM53400_A0r_fields,
  35801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35802         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35803         134,
  35804         -1,
  35805         3,
  35806     },
  35807 #endif /* chips */
  35808 
  35809 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  35810     { /* SOC_REG_INT_XLMIB_T16383_BCM56980_A0r */
  35811         soc_block_list[16],
  35812         soc_portreg,
  35813         1,
  35814         0,
  35815         0x4a00,
  35816         SOC_REG_FLAG_64_BITS |
  35817                           SOC_REG_FLAG_COUNTER,
  35818         0,
  35819         1,
  35820         soc_R1023_BCM53400_A0r_fields,
  35821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35822         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35823         109,
  35824         -1,
  35825         3,
  35826     },
  35827 #endif /* chips */
  35828 
  35829 #if defined(BCM_53570_A0)
  35830     { /* SOC_REG_INT_XLMIB_T2047_BCM53570_A0r */
  35831         soc_block_list[16],
  35832         soc_portreg,
  35833         1,
  35834         0,
  35835         0x4700,
  35836         SOC_REG_FLAG_64_BITS |
  35837                           SOC_REG_FLAG_COUNTER,
  35838         0,
  35839         1,
  35840         soc_R1023_BCM53400_A0r_fields,
  35841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35842         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35843         225,
  35844         -1,
  35845     },
  35846 #endif /* chips */
  35847 
  35848 #if defined(BCM_53570_B0)
  35849     { /* SOC_REG_INT_XLMIB_T2047_BCM53570_B0r */
  35850         soc_block_list[16],
  35851         soc_portreg,
  35852         1,
  35853         0,
  35854         0x4700,
  35855         SOC_REG_FLAG_64_BITS |
  35856                           SOC_REG_FLAG_COUNTER,
  35857         0,
  35858         1,
  35859         soc_R1023_BCM53400_A0r_fields,
  35860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35861         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35862         229,
  35863         -1,
  35864     },
  35865 #endif /* chips */
  35866 
  35867 #if defined(BCM_56370_A0)
  35868     { /* SOC_REG_INT_XLMIB_T2047_BCM56370_A0r */
  35869         soc_block_list[16],
  35870         soc_portreg,
  35871         1,
  35872         0,
  35873         0x4700,
  35874         SOC_REG_FLAG_64_BITS |
  35875                           SOC_REG_FLAG_COUNTER,
  35876         0,
  35877         1,
  35878         soc_R1023_BCM53400_A0r_fields,
  35879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35880         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35881         131,
  35882         -1,
  35883         3,
  35884     },
  35885 #endif /* chips */
  35886 
  35887 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  35888     { /* SOC_REG_INT_XLMIB_T2047_BCM56980_A0r */
  35889         soc_block_list[16],
  35890         soc_portreg,
  35891         1,
  35892         0,
  35893         0x4700,
  35894         SOC_REG_FLAG_64_BITS |
  35895                           SOC_REG_FLAG_COUNTER,
  35896         0,
  35897         1,
  35898         soc_R1023_BCM53400_A0r_fields,
  35899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35900         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35901         106,
  35902         -1,
  35903         3,
  35904     },
  35905 #endif /* chips */
  35906 
  35907 #if defined(BCM_53570_A0)
  35908     { /* SOC_REG_INT_XLMIB_T255_BCM53570_A0r */
  35909         soc_block_list[16],
  35910         soc_portreg,
  35911         1,
  35912         0,
  35913         0x4200,
  35914         SOC_REG_FLAG_64_BITS |
  35915                           SOC_REG_FLAG_COUNTER,
  35916         0,
  35917         1,
  35918         soc_R1023_BCM53400_A0r_fields,
  35919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35920         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35921         220,
  35922         -1,
  35923     },
  35924 #endif /* chips */
  35925 
  35926 #if defined(BCM_53570_B0)
  35927     { /* SOC_REG_INT_XLMIB_T255_BCM53570_B0r */
  35928         soc_block_list[16],
  35929         soc_portreg,
  35930         1,
  35931         0,
  35932         0x4200,
  35933         SOC_REG_FLAG_64_BITS |
  35934                           SOC_REG_FLAG_COUNTER,
  35935         0,
  35936         1,
  35937         soc_R1023_BCM53400_A0r_fields,
  35938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35939         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35940         224,
  35941         -1,
  35942     },
  35943 #endif /* chips */
  35944 
  35945 #if defined(BCM_56370_A0)
  35946     { /* SOC_REG_INT_XLMIB_T255_BCM56370_A0r */
  35947         soc_block_list[16],
  35948         soc_portreg,
  35949         1,
  35950         0,
  35951         0x4200,
  35952         SOC_REG_FLAG_64_BITS |
  35953                           SOC_REG_FLAG_COUNTER,
  35954         0,
  35955         1,
  35956         soc_R1023_BCM53400_A0r_fields,
  35957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35958         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35959         126,
  35960         -1,
  35961         3,
  35962     },
  35963 #endif /* chips */
  35964 
  35965 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  35966     { /* SOC_REG_INT_XLMIB_T255_BCM56980_A0r */
  35967         soc_block_list[16],
  35968         soc_portreg,
  35969         1,
  35970         0,
  35971         0x4200,
  35972         SOC_REG_FLAG_64_BITS |
  35973                           SOC_REG_FLAG_COUNTER,
  35974         0,
  35975         1,
  35976         soc_R1023_BCM53400_A0r_fields,
  35977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35978         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35979         101,
  35980         -1,
  35981         3,
  35982     },
  35983 #endif /* chips */
  35984 
  35985 #if defined(BCM_53570_A0)
  35986     { /* SOC_REG_INT_XLMIB_T4095_BCM53570_A0r */
  35987         soc_block_list[16],
  35988         soc_portreg,
  35989         1,
  35990         0,
  35991         0x4800,
  35992         SOC_REG_FLAG_64_BITS |
  35993                           SOC_REG_FLAG_COUNTER,
  35994         0,
  35995         1,
  35996         soc_R1023_BCM53400_A0r_fields,
  35997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35998         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  35999         226,
  36000         -1,
  36001     },
  36002 #endif /* chips */
  36003 
  36004 #if defined(BCM_53570_B0)
  36005     { /* SOC_REG_INT_XLMIB_T4095_BCM53570_B0r */
  36006         soc_block_list[16],
  36007         soc_portreg,
  36008         1,
  36009         0,
  36010         0x4800,
  36011         SOC_REG_FLAG_64_BITS |
  36012                           SOC_REG_FLAG_COUNTER,
  36013         0,
  36014         1,
  36015         soc_R1023_BCM53400_A0r_fields,
  36016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36017         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36018         230,
  36019         -1,
  36020     },
  36021 #endif /* chips */
  36022 
  36023 #if defined(BCM_56370_A0)
  36024     { /* SOC_REG_INT_XLMIB_T4095_BCM56370_A0r */
  36025         soc_block_list[16],
  36026         soc_portreg,
  36027         1,
  36028         0,
  36029         0x4800,
  36030         SOC_REG_FLAG_64_BITS |
  36031                           SOC_REG_FLAG_COUNTER,
  36032         0,
  36033         1,
  36034         soc_R1023_BCM53400_A0r_fields,
  36035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36036         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36037         132,
  36038         -1,
  36039         3,
  36040     },
  36041 #endif /* chips */
  36042 
  36043 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  36044     { /* SOC_REG_INT_XLMIB_T4095_BCM56980_A0r */
  36045         soc_block_list[16],
  36046         soc_portreg,
  36047         1,
  36048         0,
  36049         0x4800,
  36050         SOC_REG_FLAG_64_BITS |
  36051                           SOC_REG_FLAG_COUNTER,
  36052         0,
  36053         1,
  36054         soc_R1023_BCM53400_A0r_fields,
  36055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36056         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36057         107,
  36058         -1,
  36059         3,
  36060     },
  36061 #endif /* chips */
  36062 
  36063 #if defined(BCM_53570_A0)
  36064     { /* SOC_REG_INT_XLMIB_T511_BCM53570_A0r */
  36065         soc_block_list[16],
  36066         soc_portreg,
  36067         1,
  36068         0,
  36069         0x4300,
  36070         SOC_REG_FLAG_64_BITS |
  36071                           SOC_REG_FLAG_COUNTER,
  36072         0,
  36073         1,
  36074         soc_R1023_BCM53400_A0r_fields,
  36075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36076         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36077         221,
  36078         -1,
  36079     },
  36080 #endif /* chips */
  36081 
  36082 #if defined(BCM_53570_B0)
  36083     { /* SOC_REG_INT_XLMIB_T511_BCM53570_B0r */
  36084         soc_block_list[16],
  36085         soc_portreg,
  36086         1,
  36087         0,
  36088         0x4300,
  36089         SOC_REG_FLAG_64_BITS |
  36090                           SOC_REG_FLAG_COUNTER,
  36091         0,
  36092         1,
  36093         soc_R1023_BCM53400_A0r_fields,
  36094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36095         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36096         225,
  36097         -1,
  36098     },
  36099 #endif /* chips */
  36100 
  36101 #if defined(BCM_56370_A0)
  36102     { /* SOC_REG_INT_XLMIB_T511_BCM56370_A0r */
  36103         soc_block_list[16],
  36104         soc_portreg,
  36105         1,
  36106         0,
  36107         0x4300,
  36108         SOC_REG_FLAG_64_BITS |
  36109                           SOC_REG_FLAG_COUNTER,
  36110         0,
  36111         1,
  36112         soc_R1023_BCM53400_A0r_fields,
  36113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36114         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36115         127,
  36116         -1,
  36117         3,
  36118     },
  36119 #endif /* chips */
  36120 
  36121 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  36122     { /* SOC_REG_INT_XLMIB_T511_BCM56980_A0r */
  36123         soc_block_list[16],
  36124         soc_portreg,
  36125         1,
  36126         0,
  36127         0x4300,
  36128         SOC_REG_FLAG_64_BITS |
  36129                           SOC_REG_FLAG_COUNTER,
  36130         0,
  36131         1,
  36132         soc_R1023_BCM53400_A0r_fields,
  36133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36134         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36135         102,
  36136         -1,
  36137         3,
  36138     },
  36139 #endif /* chips */
  36140 
  36141 #if defined(BCM_53570_A0)
  36142     { /* SOC_REG_INT_XLMIB_T64_BCM53570_A0r */
  36143         soc_block_list[16],
  36144         soc_portreg,
  36145         1,
  36146         0,
  36147         0x4000,
  36148         SOC_REG_FLAG_64_BITS |
  36149                           SOC_REG_FLAG_COUNTER,
  36150         0,
  36151         1,
  36152         soc_R1023_BCM53400_A0r_fields,
  36153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36154         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36155         218,
  36156         -1,
  36157     },
  36158 #endif /* chips */
  36159 
  36160 #if defined(BCM_53570_B0)
  36161     { /* SOC_REG_INT_XLMIB_T64_BCM53570_B0r */
  36162         soc_block_list[16],
  36163         soc_portreg,
  36164         1,
  36165         0,
  36166         0x4000,
  36167         SOC_REG_FLAG_64_BITS |
  36168                           SOC_REG_FLAG_COUNTER,
  36169         0,
  36170         1,
  36171         soc_R1023_BCM53400_A0r_fields,
  36172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36174         222,
  36175         -1,
  36176     },
  36177 #endif /* chips */
  36178 
  36179 #if defined(BCM_56370_A0)
  36180     { /* SOC_REG_INT_XLMIB_T64_BCM56370_A0r */
  36181         soc_block_list[16],
  36182         soc_portreg,
  36183         1,
  36184         0,
  36185         0x4000,
  36186         SOC_REG_FLAG_64_BITS |
  36187                           SOC_REG_FLAG_COUNTER,
  36188         0,
  36189         1,
  36190         soc_R1023_BCM53400_A0r_fields,
  36191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36192         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36193         124,
  36194         -1,
  36195         3,
  36196     },
  36197 #endif /* chips */
  36198 
  36199 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  36200     { /* SOC_REG_INT_XLMIB_T64_BCM56980_A0r */
  36201         soc_block_list[16],
  36202         soc_portreg,
  36203         1,
  36204         0,
  36205         0x4000,
  36206         SOC_REG_FLAG_64_BITS |
  36207                           SOC_REG_FLAG_COUNTER,
  36208         0,
  36209         1,
  36210         soc_R1023_BCM53400_A0r_fields,
  36211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36212         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36213         99,
  36214         -1,
  36215         3,
  36216     },
  36217 #endif /* chips */
  36218 
  36219 #if defined(BCM_53570_A0)
  36220     { /* SOC_REG_INT_XLMIB_T9216_BCM53570_A0r */
  36221         soc_block_list[16],
  36222         soc_portreg,
  36223         1,
  36224         0,
  36225         0x4900,
  36226         SOC_REG_FLAG_64_BITS |
  36227                           SOC_REG_FLAG_COUNTER,
  36228         0,
  36229         1,
  36230         soc_R1023_BCM53400_A0r_fields,
  36231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36232         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36233         227,
  36234         -1,
  36235     },
  36236 #endif /* chips */
  36237 
  36238 #if defined(BCM_53570_B0)
  36239     { /* SOC_REG_INT_XLMIB_T9216_BCM53570_B0r */
  36240         soc_block_list[16],
  36241         soc_portreg,
  36242         1,
  36243         0,
  36244         0x4900,
  36245         SOC_REG_FLAG_64_BITS |
  36246                           SOC_REG_FLAG_COUNTER,
  36247         0,
  36248         1,
  36249         soc_R1023_BCM53400_A0r_fields,
  36250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36252         231,
  36253         -1,
  36254     },
  36255 #endif /* chips */
  36256 
  36257 #if defined(BCM_56370_A0)
  36258     { /* SOC_REG_INT_XLMIB_T9216_BCM56370_A0r */
  36259         soc_block_list[16],
  36260         soc_portreg,
  36261         1,
  36262         0,
  36263         0x4900,
  36264         SOC_REG_FLAG_64_BITS |
  36265                           SOC_REG_FLAG_COUNTER,
  36266         0,
  36267         1,
  36268         soc_R1023_BCM53400_A0r_fields,
  36269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36270         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36271         133,
  36272         -1,
  36273         3,
  36274     },
  36275 #endif /* chips */
  36276 
  36277 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  36278     { /* SOC_REG_INT_XLMIB_T9216_BCM56980_A0r */
  36279         soc_block_list[16],
  36280         soc_portreg,
  36281         1,
  36282         0,
  36283         0x4900,
  36284         SOC_REG_FLAG_64_BITS |
  36285                           SOC_REG_FLAG_COUNTER,
  36286         0,
  36287         1,
  36288         soc_R1023_BCM53400_A0r_fields,
  36289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36290         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36291         108,
  36292         -1,
  36293         3,
  36294     },
  36295 #endif /* chips */
  36296 
  36297 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  36298     { /* SOC_REG_INT_XLMIB_TBCAr */
  36299         soc_block_list[16],
  36300         soc_portreg,
  36301         1,
  36302         0,
  36303         0x4f00,
  36304         SOC_REG_FLAG_64_BITS |
  36305                           SOC_REG_FLAG_COUNTER,
  36306         0,
  36307         1,
  36308         soc_R1023_BCM53400_A0r_fields,
  36309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36310         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36311         138,
  36312         -1,
  36313         3,
  36314     },
  36315 #endif /* chips */
  36316 
  36317 #if defined(BCM_53570_A0)
  36318     { /* SOC_REG_INT_XLMIB_TBCA_BCM53570_A0r */
  36319         soc_block_list[16],
  36320         soc_portreg,
  36321         1,
  36322         0,
  36323         0x4f00,
  36324         SOC_REG_FLAG_64_BITS |
  36325                           SOC_REG_FLAG_COUNTER,
  36326         0,
  36327         1,
  36328         soc_R1023_BCM53400_A0r_fields,
  36329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36330         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36331         233,
  36332         -1,
  36333     },
  36334 #endif /* chips */
  36335 
  36336 #if defined(BCM_53570_B0)
  36337     { /* SOC_REG_INT_XLMIB_TBCA_BCM53570_B0r */
  36338         soc_block_list[16],
  36339         soc_portreg,
  36340         1,
  36341         0,
  36342         0x4f00,
  36343         SOC_REG_FLAG_64_BITS |
  36344                           SOC_REG_FLAG_COUNTER,
  36345         0,
  36346         1,
  36347         soc_R1023_BCM53400_A0r_fields,
  36348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36349         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36350         237,
  36351         -1,
  36352     },
  36353 #endif /* chips */
  36354 
  36355 #if defined(BCM_56370_A0)
  36356     { /* SOC_REG_INT_XLMIB_TBCA_BCM56370_A0r */
  36357         soc_block_list[16],
  36358         soc_portreg,
  36359         1,
  36360         0,
  36361         0x4f00,
  36362         SOC_REG_FLAG_64_BITS |
  36363                           SOC_REG_FLAG_COUNTER,
  36364         0,
  36365         1,
  36366         soc_R1023_BCM53400_A0r_fields,
  36367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36368         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36369         139,
  36370         -1,
  36371         3,
  36372     },
  36373 #endif /* chips */
  36374 
  36375 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  36376     { /* SOC_REG_INT_XLMIB_TBCA_BCM56980_A0r */
  36377         soc_block_list[16],
  36378         soc_portreg,
  36379         1,
  36380         0,
  36381         0x4f00,
  36382         SOC_REG_FLAG_64_BITS |
  36383                           SOC_REG_FLAG_COUNTER,
  36384         0,
  36385         1,
  36386         soc_R1023_BCM53400_A0r_fields,
  36387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36388         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36389         114,
  36390         -1,
  36391         3,
  36392     },
  36393 #endif /* chips */
  36394 
  36395 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  36396     { /* SOC_REG_INT_XLMIB_TBYTr */
  36397         soc_block_list[16],
  36398         soc_portreg,
  36399         1,
  36400         0,
  36401         0x6f00,
  36402         SOC_REG_FLAG_64_BITS |
  36403                           SOC_REG_FLAG_COUNTER,
  36404         0,
  36405         1,
  36406         soc_RBYT_BCM53400_A0r_fields,
  36407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36408         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36409         170,
  36410         -1,
  36411         3,
  36412     },
  36413 #endif /* chips */
  36414 
  36415 #if defined(BCM_53570_A0)
  36416     { /* SOC_REG_INT_XLMIB_TBYT_BCM53570_A0r */
  36417         soc_block_list[16],
  36418         soc_portreg,
  36419         1,
  36420         0,
  36421         0x6f00,
  36422         SOC_REG_FLAG_64_BITS |
  36423                           SOC_REG_FLAG_COUNTER,
  36424         0,
  36425         1,
  36426         soc_RBYT_BCM53400_A0r_fields,
  36427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36429         265,
  36430         -1,
  36431     },
  36432 #endif /* chips */
  36433 
  36434 #if defined(BCM_53570_B0)
  36435     { /* SOC_REG_INT_XLMIB_TBYT_BCM53570_B0r */
  36436         soc_block_list[16],
  36437         soc_portreg,
  36438         1,
  36439         0,
  36440         0x6f00,
  36441         SOC_REG_FLAG_64_BITS |
  36442                           SOC_REG_FLAG_COUNTER,
  36443         0,
  36444         1,
  36445         soc_RBYT_BCM53400_A0r_fields,
  36446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36447         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36448         269,
  36449         -1,
  36450     },
  36451 #endif /* chips */
  36452 
  36453 #if defined(BCM_56370_A0)
  36454     { /* SOC_REG_INT_XLMIB_TBYT_BCM56370_A0r */
  36455         soc_block_list[16],
  36456         soc_portreg,
  36457         1,
  36458         0,
  36459         0x6f00,
  36460         SOC_REG_FLAG_64_BITS |
  36461                           SOC_REG_FLAG_COUNTER,
  36462         0,
  36463         1,
  36464         soc_RBYT_BCM53400_A0r_fields,
  36465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36466         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36467         171,
  36468         -1,
  36469         3,
  36470     },
  36471 #endif /* chips */
  36472 
  36473 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  36474     { /* SOC_REG_INT_XLMIB_TBYT_BCM56980_A0r */
  36475         soc_block_list[16],
  36476         soc_portreg,
  36477         1,
  36478         0,
  36479         0x6f00,
  36480         SOC_REG_FLAG_64_BITS |
  36481                           SOC_REG_FLAG_COUNTER,
  36482         0,
  36483         1,
  36484         soc_RBYT_BCM53400_A0r_fields,
  36485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36486         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36487         146,
  36488         -1,
  36489         3,
  36490     },
  36491 #endif /* chips */
  36492 
  36493 #if defined(BCM_56970_A0)
  36494     { /* SOC_REG_INT_XLMIB_TDFRr */
  36495         soc_block_list[16],
  36496         soc_portreg,
  36497         1,
  36498         0,
  36499         0x5600,
  36500         SOC_REG_FLAG_64_BITS |
  36501                           SOC_REG_FLAG_COUNTER |
  36502                           SOC_REG_FLAG_ED_CNTR,
  36503         0,
  36504         1,
  36505         soc_RALN_BCM53400_A0r_fields,
  36506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36507         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36508         141,
  36509         -1,
  36510         3,
  36511     },
  36512 #endif /* chips */
  36513 
  36514 #if defined(BCM_56370_A0)
  36515     { /* SOC_REG_INT_XLMIB_TDFR_BCM56370_A0r */
  36516         soc_block_list[16],
  36517         soc_portreg,
  36518         1,
  36519         0,
  36520         0x5600,
  36521         SOC_REG_FLAG_64_BITS |
  36522                           SOC_REG_FLAG_COUNTER |
  36523                           SOC_REG_FLAG_ED_CNTR,
  36524         0,
  36525         1,
  36526         soc_RALN_BCM53400_A0r_fields,
  36527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36528         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36529         146,
  36530         -1,
  36531         3,
  36532     },
  36533 #endif /* chips */
  36534 
  36535 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  36536     { /* SOC_REG_INT_XLMIB_TDFR_BCM56870_A0r */
  36537         soc_block_list[16],
  36538         soc_portreg,
  36539         1,
  36540         0,
  36541         0x5600,
  36542         SOC_REG_FLAG_64_BITS |
  36543                           SOC_REG_FLAG_COUNTER |
  36544                           SOC_REG_FLAG_ED_CNTR,
  36545         0,
  36546         1,
  36547         soc_RALN_BCM53400_A0r_fields,
  36548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36549         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36550         145,
  36551         -1,
  36552         3,
  36553     },
  36554 #endif /* chips */
  36555 
  36556 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  36557     { /* SOC_REG_INT_XLMIB_TDFR_BCM56980_A0r */
  36558         soc_block_list[16],
  36559         soc_portreg,
  36560         1,
  36561         0,
  36562         0x5600,
  36563         SOC_REG_FLAG_64_BITS |
  36564                           SOC_REG_FLAG_COUNTER |
  36565                           SOC_REG_FLAG_ED_CNTR,
  36566         0,
  36567         1,
  36568         soc_RALN_BCM53400_A0r_fields,
  36569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36570         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36571         121,
  36572         -1,
  36573         3,
  36574     },
  36575 #endif /* chips */
  36576 
  36577 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  36578     { /* SOC_REG_INT_XLMIB_TDVLNr */
  36579         soc_block_list[16],
  36580         soc_portreg,
  36581         1,
  36582         0,
  36583         0x5f00,
  36584         SOC_REG_FLAG_64_BITS |
  36585                           SOC_REG_FLAG_COUNTER,
  36586         0,
  36587         1,
  36588         soc_R1023_BCM53400_A0r_fields,
  36589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36590         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36591         154,
  36592         -1,
  36593         3,
  36594     },
  36595 #endif /* chips */
  36596 
  36597 #if defined(BCM_53570_A0)
  36598     { /* SOC_REG_INT_XLMIB_TDVLN_BCM53570_A0r */
  36599         soc_block_list[16],
  36600         soc_portreg,
  36601         1,
  36602         0,
  36603         0x5f00,
  36604         SOC_REG_FLAG_64_BITS |
  36605                           SOC_REG_FLAG_COUNTER,
  36606         0,
  36607         1,
  36608         soc_R1023_BCM53400_A0r_fields,
  36609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36610         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36611         249,
  36612         -1,
  36613     },
  36614 #endif /* chips */
  36615 
  36616 #if defined(BCM_53570_B0)
  36617     { /* SOC_REG_INT_XLMIB_TDVLN_BCM53570_B0r */
  36618         soc_block_list[16],
  36619         soc_portreg,
  36620         1,
  36621         0,
  36622         0x5f00,
  36623         SOC_REG_FLAG_64_BITS |
  36624                           SOC_REG_FLAG_COUNTER,
  36625         0,
  36626         1,
  36627         soc_R1023_BCM53400_A0r_fields,
  36628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36629         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36630         253,
  36631         -1,
  36632     },
  36633 #endif /* chips */
  36634 
  36635 #if defined(BCM_56370_A0)
  36636     { /* SOC_REG_INT_XLMIB_TDVLN_BCM56370_A0r */
  36637         soc_block_list[16],
  36638         soc_portreg,
  36639         1,
  36640         0,
  36641         0x5f00,
  36642         SOC_REG_FLAG_64_BITS |
  36643                           SOC_REG_FLAG_COUNTER,
  36644         0,
  36645         1,
  36646         soc_R1023_BCM53400_A0r_fields,
  36647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36649         155,
  36650         -1,
  36651         3,
  36652     },
  36653 #endif /* chips */
  36654 
  36655 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  36656     { /* SOC_REG_INT_XLMIB_TDVLN_BCM56980_A0r */
  36657         soc_block_list[16],
  36658         soc_portreg,
  36659         1,
  36660         0,
  36661         0x5f00,
  36662         SOC_REG_FLAG_64_BITS |
  36663                           SOC_REG_FLAG_COUNTER,
  36664         0,
  36665         1,
  36666         soc_R1023_BCM53400_A0r_fields,
  36667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36668         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36669         130,
  36670         -1,
  36671         3,
  36672     },
  36673 #endif /* chips */
  36674 
  36675 #if defined(BCM_56970_A0)
  36676     { /* SOC_REG_INT_XLMIB_TEDFr */
  36677         soc_block_list[16],
  36678         soc_portreg,
  36679         1,
  36680         0,
  36681         0x5700,
  36682         SOC_REG_FLAG_64_BITS |
  36683                           SOC_REG_FLAG_COUNTER |
  36684                           SOC_REG_FLAG_ED_CNTR,
  36685         0,
  36686         1,
  36687         soc_RALN_BCM53400_A0r_fields,
  36688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36689         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36690         142,
  36691         -1,
  36692         3,
  36693     },
  36694 #endif /* chips */
  36695 
  36696 #if defined(BCM_56370_A0)
  36697     { /* SOC_REG_INT_XLMIB_TEDF_BCM56370_A0r */
  36698         soc_block_list[16],
  36699         soc_portreg,
  36700         1,
  36701         0,
  36702         0x5700,
  36703         SOC_REG_FLAG_64_BITS |
  36704                           SOC_REG_FLAG_COUNTER |
  36705                           SOC_REG_FLAG_ED_CNTR,
  36706         0,
  36707         1,
  36708         soc_RALN_BCM53400_A0r_fields,
  36709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36710         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36711         147,
  36712         -1,
  36713         3,
  36714     },
  36715 #endif /* chips */
  36716 
  36717 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  36718     { /* SOC_REG_INT_XLMIB_TEDF_BCM56870_A0r */
  36719         soc_block_list[16],
  36720         soc_portreg,
  36721         1,
  36722         0,
  36723         0x5700,
  36724         SOC_REG_FLAG_64_BITS |
  36725                           SOC_REG_FLAG_COUNTER |
  36726                           SOC_REG_FLAG_ED_CNTR,
  36727         0,
  36728         1,
  36729         soc_RALN_BCM53400_A0r_fields,
  36730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36731         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36732         146,
  36733         -1,
  36734         3,
  36735     },
  36736 #endif /* chips */
  36737 
  36738 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  36739     { /* SOC_REG_INT_XLMIB_TEDF_BCM56980_A0r */
  36740         soc_block_list[16],
  36741         soc_portreg,
  36742         1,
  36743         0,
  36744         0x5700,
  36745         SOC_REG_FLAG_64_BITS |
  36746                           SOC_REG_FLAG_COUNTER |
  36747                           SOC_REG_FLAG_ED_CNTR,
  36748         0,
  36749         1,
  36750         soc_RALN_BCM53400_A0r_fields,
  36751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36752         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36753         122,
  36754         -1,
  36755         3,
  36756     },
  36757 #endif /* chips */
  36758 
  36759 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  36760     { /* SOC_REG_INT_XLMIB_TERRr */
  36761         soc_block_list[16],
  36762         soc_portreg,
  36763         1,
  36764         0,
  36765         0x5d00,
  36766         SOC_REG_FLAG_64_BITS |
  36767                           SOC_REG_FLAG_COUNTER |
  36768                           SOC_REG_FLAG_ED_CNTR,
  36769         0,
  36770         1,
  36771         soc_R1023_BCM53400_A0r_fields,
  36772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36773         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36774         152,
  36775         -1,
  36776         3,
  36777     },
  36778 #endif /* chips */
  36779 
  36780 #if defined(BCM_53570_A0)
  36781     { /* SOC_REG_INT_XLMIB_TERR_BCM53570_A0r */
  36782         soc_block_list[16],
  36783         soc_portreg,
  36784         1,
  36785         0,
  36786         0x5d00,
  36787         SOC_REG_FLAG_64_BITS |
  36788                           SOC_REG_FLAG_COUNTER |
  36789                           SOC_REG_FLAG_ED_CNTR,
  36790         0,
  36791         1,
  36792         soc_R1023_BCM53400_A0r_fields,
  36793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36794         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36795         247,
  36796         -1,
  36797     },
  36798 #endif /* chips */
  36799 
  36800 #if defined(BCM_53570_B0)
  36801     { /* SOC_REG_INT_XLMIB_TERR_BCM53570_B0r */
  36802         soc_block_list[16],
  36803         soc_portreg,
  36804         1,
  36805         0,
  36806         0x5d00,
  36807         SOC_REG_FLAG_64_BITS |
  36808                           SOC_REG_FLAG_COUNTER |
  36809                           SOC_REG_FLAG_ED_CNTR,
  36810         0,
  36811         1,
  36812         soc_R1023_BCM53400_A0r_fields,
  36813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36814         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36815         251,
  36816         -1,
  36817     },
  36818 #endif /* chips */
  36819 
  36820 #if defined(BCM_56370_A0)
  36821     { /* SOC_REG_INT_XLMIB_TERR_BCM56370_A0r */
  36822         soc_block_list[16],
  36823         soc_portreg,
  36824         1,
  36825         0,
  36826         0x5d00,
  36827         SOC_REG_FLAG_64_BITS |
  36828                           SOC_REG_FLAG_COUNTER |
  36829                           SOC_REG_FLAG_ED_CNTR,
  36830         0,
  36831         1,
  36832         soc_R1023_BCM53400_A0r_fields,
  36833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36835         153,
  36836         -1,
  36837         3,
  36838     },
  36839 #endif /* chips */
  36840 
  36841 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  36842     { /* SOC_REG_INT_XLMIB_TERR_BCM56980_A0r */
  36843         soc_block_list[16],
  36844         soc_portreg,
  36845         1,
  36846         0,
  36847         0x5d00,
  36848         SOC_REG_FLAG_64_BITS |
  36849                           SOC_REG_FLAG_COUNTER |
  36850                           SOC_REG_FLAG_ED_CNTR,
  36851         0,
  36852         1,
  36853         soc_R1023_BCM53400_A0r_fields,
  36854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36855         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36856         128,
  36857         -1,
  36858         3,
  36859     },
  36860 #endif /* chips */
  36861 
  36862 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  36863     { /* SOC_REG_INT_XLMIB_TFCSr */
  36864         soc_block_list[16],
  36865         soc_portreg,
  36866         1,
  36867         0,
  36868         0x5300,
  36869         SOC_REG_FLAG_64_BITS |
  36870                           SOC_REG_FLAG_COUNTER |
  36871                           SOC_REG_FLAG_ED_CNTR,
  36872         0,
  36873         1,
  36874         soc_R1023_BCM53400_A0r_fields,
  36875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36876         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36877         142,
  36878         -1,
  36879         3,
  36880     },
  36881 #endif /* chips */
  36882 
  36883 #if defined(BCM_53570_A0)
  36884     { /* SOC_REG_INT_XLMIB_TFCS_BCM53570_A0r */
  36885         soc_block_list[16],
  36886         soc_portreg,
  36887         1,
  36888         0,
  36889         0x5300,
  36890         SOC_REG_FLAG_64_BITS |
  36891                           SOC_REG_FLAG_COUNTER |
  36892                           SOC_REG_FLAG_ED_CNTR,
  36893         0,
  36894         1,
  36895         soc_R1023_BCM53400_A0r_fields,
  36896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36897         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36898         237,
  36899         -1,
  36900     },
  36901 #endif /* chips */
  36902 
  36903 #if defined(BCM_53570_B0)
  36904     { /* SOC_REG_INT_XLMIB_TFCS_BCM53570_B0r */
  36905         soc_block_list[16],
  36906         soc_portreg,
  36907         1,
  36908         0,
  36909         0x5300,
  36910         SOC_REG_FLAG_64_BITS |
  36911                           SOC_REG_FLAG_COUNTER |
  36912                           SOC_REG_FLAG_ED_CNTR,
  36913         0,
  36914         1,
  36915         soc_R1023_BCM53400_A0r_fields,
  36916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36918         241,
  36919         -1,
  36920     },
  36921 #endif /* chips */
  36922 
  36923 #if defined(BCM_56370_A0)
  36924     { /* SOC_REG_INT_XLMIB_TFCS_BCM56370_A0r */
  36925         soc_block_list[16],
  36926         soc_portreg,
  36927         1,
  36928         0,
  36929         0x5300,
  36930         SOC_REG_FLAG_64_BITS |
  36931                           SOC_REG_FLAG_COUNTER |
  36932                           SOC_REG_FLAG_ED_CNTR,
  36933         0,
  36934         1,
  36935         soc_R1023_BCM53400_A0r_fields,
  36936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36937         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36938         143,
  36939         -1,
  36940         3,
  36941     },
  36942 #endif /* chips */
  36943 
  36944 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  36945     { /* SOC_REG_INT_XLMIB_TFCS_BCM56980_A0r */
  36946         soc_block_list[16],
  36947         soc_portreg,
  36948         1,
  36949         0,
  36950         0x5300,
  36951         SOC_REG_FLAG_64_BITS |
  36952                           SOC_REG_FLAG_COUNTER |
  36953                           SOC_REG_FLAG_ED_CNTR,
  36954         0,
  36955         1,
  36956         soc_R1023_BCM53400_A0r_fields,
  36957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36958         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36959         118,
  36960         -1,
  36961         3,
  36962     },
  36963 #endif /* chips */
  36964 
  36965 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  36966     { /* SOC_REG_INT_XLMIB_TFRGr */
  36967         soc_block_list[16],
  36968         soc_portreg,
  36969         1,
  36970         0,
  36971         0x5c00,
  36972         SOC_REG_FLAG_64_BITS |
  36973                           SOC_REG_FLAG_COUNTER |
  36974                           SOC_REG_FLAG_ED_CNTR,
  36975         0,
  36976         1,
  36977         soc_R1023_BCM53400_A0r_fields,
  36978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36979         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  36980         151,
  36981         -1,
  36982         3,
  36983     },
  36984 #endif /* chips */
  36985 
  36986 #if defined(BCM_53570_A0)
  36987     { /* SOC_REG_INT_XLMIB_TFRG_BCM53570_A0r */
  36988         soc_block_list[16],
  36989         soc_portreg,
  36990         1,
  36991         0,
  36992         0x5c00,
  36993         SOC_REG_FLAG_64_BITS |
  36994                           SOC_REG_FLAG_COUNTER |
  36995                           SOC_REG_FLAG_ED_CNTR,
  36996         0,
  36997         1,
  36998         soc_R1023_BCM53400_A0r_fields,
  36999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37000         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37001         246,
  37002         -1,
  37003     },
  37004 #endif /* chips */
  37005 
  37006 #if defined(BCM_53570_B0)
  37007     { /* SOC_REG_INT_XLMIB_TFRG_BCM53570_B0r */
  37008         soc_block_list[16],
  37009         soc_portreg,
  37010         1,
  37011         0,
  37012         0x5c00,
  37013         SOC_REG_FLAG_64_BITS |
  37014                           SOC_REG_FLAG_COUNTER |
  37015                           SOC_REG_FLAG_ED_CNTR,
  37016         0,
  37017         1,
  37018         soc_R1023_BCM53400_A0r_fields,
  37019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37020         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37021         250,
  37022         -1,
  37023     },
  37024 #endif /* chips */
  37025 
  37026 #if defined(BCM_56370_A0)
  37027     { /* SOC_REG_INT_XLMIB_TFRG_BCM56370_A0r */
  37028         soc_block_list[16],
  37029         soc_portreg,
  37030         1,
  37031         0,
  37032         0x5c00,
  37033         SOC_REG_FLAG_64_BITS |
  37034                           SOC_REG_FLAG_COUNTER |
  37035                           SOC_REG_FLAG_ED_CNTR,
  37036         0,
  37037         1,
  37038         soc_R1023_BCM53400_A0r_fields,
  37039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37040         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37041         152,
  37042         -1,
  37043         3,
  37044     },
  37045 #endif /* chips */
  37046 
  37047 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  37048     { /* SOC_REG_INT_XLMIB_TFRG_BCM56980_A0r */
  37049         soc_block_list[16],
  37050         soc_portreg,
  37051         1,
  37052         0,
  37053         0x5c00,
  37054         SOC_REG_FLAG_64_BITS |
  37055                           SOC_REG_FLAG_COUNTER |
  37056                           SOC_REG_FLAG_ED_CNTR,
  37057         0,
  37058         1,
  37059         soc_R1023_BCM53400_A0r_fields,
  37060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37061         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37062         127,
  37063         -1,
  37064         3,
  37065     },
  37066 #endif /* chips */
  37067 
  37068 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37069     { /* SOC_REG_INT_XLMIB_TJBRr */
  37070         soc_block_list[16],
  37071         soc_portreg,
  37072         1,
  37073         0,
  37074         0x5200,
  37075         SOC_REG_FLAG_64_BITS |
  37076                           SOC_REG_FLAG_COUNTER |
  37077                           SOC_REG_FLAG_ED_CNTR,
  37078         0,
  37079         1,
  37080         soc_R1023_BCM53400_A0r_fields,
  37081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37082         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37083         141,
  37084         -1,
  37085         3,
  37086     },
  37087 #endif /* chips */
  37088 
  37089 #if defined(BCM_53570_A0)
  37090     { /* SOC_REG_INT_XLMIB_TJBR_BCM53570_A0r */
  37091         soc_block_list[16],
  37092         soc_portreg,
  37093         1,
  37094         0,
  37095         0x5200,
  37096         SOC_REG_FLAG_64_BITS |
  37097                           SOC_REG_FLAG_COUNTER |
  37098                           SOC_REG_FLAG_ED_CNTR,
  37099         0,
  37100         1,
  37101         soc_R1023_BCM53400_A0r_fields,
  37102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37103         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37104         236,
  37105         -1,
  37106     },
  37107 #endif /* chips */
  37108 
  37109 #if defined(BCM_53570_B0)
  37110     { /* SOC_REG_INT_XLMIB_TJBR_BCM53570_B0r */
  37111         soc_block_list[16],
  37112         soc_portreg,
  37113         1,
  37114         0,
  37115         0x5200,
  37116         SOC_REG_FLAG_64_BITS |
  37117                           SOC_REG_FLAG_COUNTER |
  37118                           SOC_REG_FLAG_ED_CNTR,
  37119         0,
  37120         1,
  37121         soc_R1023_BCM53400_A0r_fields,
  37122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37124         240,
  37125         -1,
  37126     },
  37127 #endif /* chips */
  37128 
  37129 #if defined(BCM_56370_A0)
  37130     { /* SOC_REG_INT_XLMIB_TJBR_BCM56370_A0r */
  37131         soc_block_list[16],
  37132         soc_portreg,
  37133         1,
  37134         0,
  37135         0x5200,
  37136         SOC_REG_FLAG_64_BITS |
  37137                           SOC_REG_FLAG_COUNTER |
  37138                           SOC_REG_FLAG_ED_CNTR,
  37139         0,
  37140         1,
  37141         soc_R1023_BCM53400_A0r_fields,
  37142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37143         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37144         142,
  37145         -1,
  37146         3,
  37147     },
  37148 #endif /* chips */
  37149 
  37150 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  37151     { /* SOC_REG_INT_XLMIB_TJBR_BCM56980_A0r */
  37152         soc_block_list[16],
  37153         soc_portreg,
  37154         1,
  37155         0,
  37156         0x5200,
  37157         SOC_REG_FLAG_64_BITS |
  37158                           SOC_REG_FLAG_COUNTER |
  37159                           SOC_REG_FLAG_ED_CNTR,
  37160         0,
  37161         1,
  37162         soc_R1023_BCM53400_A0r_fields,
  37163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37164         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37165         117,
  37166         -1,
  37167         3,
  37168     },
  37169 #endif /* chips */
  37170 
  37171 #if defined(BCM_56970_A0)
  37172     { /* SOC_REG_INT_XLMIB_TLCLr */
  37173         soc_block_list[16],
  37174         soc_portreg,
  37175         1,
  37176         0,
  37177         0x5a00,
  37178         SOC_REG_FLAG_64_BITS |
  37179                           SOC_REG_FLAG_COUNTER |
  37180                           SOC_REG_FLAG_ED_CNTR,
  37181         0,
  37182         1,
  37183         soc_RALN_BCM53400_A0r_fields,
  37184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37185         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37186         145,
  37187         -1,
  37188         3,
  37189     },
  37190 #endif /* chips */
  37191 
  37192 #if defined(BCM_53570_A0)
  37193     { /* SOC_REG_INT_XLMIB_TLCL_BCM53570_A0r */
  37194         soc_block_list[16],
  37195         soc_portreg,
  37196         1,
  37197         0,
  37198         0x5a00,
  37199         SOC_REG_FLAG_64_BITS |
  37200                           SOC_REG_FLAG_COUNTER |
  37201                           SOC_REG_FLAG_ED_CNTR,
  37202         0,
  37203         1,
  37204         soc_XLMIB_RSCHCRCr_fields,
  37205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37206         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37207         244,
  37208         -1,
  37209     },
  37210 #endif /* chips */
  37211 
  37212 #if defined(BCM_53570_B0)
  37213     { /* SOC_REG_INT_XLMIB_TLCL_BCM53570_B0r */
  37214         soc_block_list[16],
  37215         soc_portreg,
  37216         1,
  37217         0,
  37218         0x5a00,
  37219         SOC_REG_FLAG_64_BITS |
  37220                           SOC_REG_FLAG_COUNTER |
  37221                           SOC_REG_FLAG_ED_CNTR,
  37222         0,
  37223         1,
  37224         soc_XLMIB_RSCHCRCr_fields,
  37225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37226         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37227         248,
  37228         -1,
  37229     },
  37230 #endif /* chips */
  37231 
  37232 #if defined(BCM_56370_A0)
  37233     { /* SOC_REG_INT_XLMIB_TLCL_BCM56370_A0r */
  37234         soc_block_list[16],
  37235         soc_portreg,
  37236         1,
  37237         0,
  37238         0x5a00,
  37239         SOC_REG_FLAG_64_BITS |
  37240                           SOC_REG_FLAG_COUNTER |
  37241                           SOC_REG_FLAG_ED_CNTR,
  37242         0,
  37243         1,
  37244         soc_RALN_BCM53400_A0r_fields,
  37245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37246         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37247         150,
  37248         -1,
  37249         3,
  37250     },
  37251 #endif /* chips */
  37252 
  37253 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37254     { /* SOC_REG_INT_XLMIB_TLCL_BCM56870_A0r */
  37255         soc_block_list[16],
  37256         soc_portreg,
  37257         1,
  37258         0,
  37259         0x5a00,
  37260         SOC_REG_FLAG_64_BITS |
  37261                           SOC_REG_FLAG_COUNTER |
  37262                           SOC_REG_FLAG_ED_CNTR,
  37263         0,
  37264         1,
  37265         soc_RALN_BCM53400_A0r_fields,
  37266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37267         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37268         149,
  37269         -1,
  37270         3,
  37271     },
  37272 #endif /* chips */
  37273 
  37274 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  37275     { /* SOC_REG_INT_XLMIB_TLCL_BCM56980_A0r */
  37276         soc_block_list[16],
  37277         soc_portreg,
  37278         1,
  37279         0,
  37280         0x5a00,
  37281         SOC_REG_FLAG_64_BITS |
  37282                           SOC_REG_FLAG_COUNTER |
  37283                           SOC_REG_FLAG_ED_CNTR,
  37284         0,
  37285         1,
  37286         soc_RALN_BCM53400_A0r_fields,
  37287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37288         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37289         125,
  37290         -1,
  37291         3,
  37292     },
  37293 #endif /* chips */
  37294 
  37295 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37296     { /* SOC_REG_INT_XLMIB_TMCAr */
  37297         soc_block_list[16],
  37298         soc_portreg,
  37299         1,
  37300         0,
  37301         0x4e00,
  37302         SOC_REG_FLAG_64_BITS |
  37303                           SOC_REG_FLAG_COUNTER,
  37304         0,
  37305         1,
  37306         soc_R1023_BCM53400_A0r_fields,
  37307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37308         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37309         137,
  37310         -1,
  37311         3,
  37312     },
  37313 #endif /* chips */
  37314 
  37315 #if defined(BCM_53570_A0)
  37316     { /* SOC_REG_INT_XLMIB_TMCA_BCM53570_A0r */
  37317         soc_block_list[16],
  37318         soc_portreg,
  37319         1,
  37320         0,
  37321         0x4e00,
  37322         SOC_REG_FLAG_64_BITS |
  37323                           SOC_REG_FLAG_COUNTER,
  37324         0,
  37325         1,
  37326         soc_R1023_BCM53400_A0r_fields,
  37327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37328         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37329         232,
  37330         -1,
  37331     },
  37332 #endif /* chips */
  37333 
  37334 #if defined(BCM_53570_B0)
  37335     { /* SOC_REG_INT_XLMIB_TMCA_BCM53570_B0r */
  37336         soc_block_list[16],
  37337         soc_portreg,
  37338         1,
  37339         0,
  37340         0x4e00,
  37341         SOC_REG_FLAG_64_BITS |
  37342                           SOC_REG_FLAG_COUNTER,
  37343         0,
  37344         1,
  37345         soc_R1023_BCM53400_A0r_fields,
  37346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37347         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37348         236,
  37349         -1,
  37350     },
  37351 #endif /* chips */
  37352 
  37353 #if defined(BCM_56370_A0)
  37354     { /* SOC_REG_INT_XLMIB_TMCA_BCM56370_A0r */
  37355         soc_block_list[16],
  37356         soc_portreg,
  37357         1,
  37358         0,
  37359         0x4e00,
  37360         SOC_REG_FLAG_64_BITS |
  37361                           SOC_REG_FLAG_COUNTER,
  37362         0,
  37363         1,
  37364         soc_R1023_BCM53400_A0r_fields,
  37365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37366         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37367         138,
  37368         -1,
  37369         3,
  37370     },
  37371 #endif /* chips */
  37372 
  37373 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  37374     { /* SOC_REG_INT_XLMIB_TMCA_BCM56980_A0r */
  37375         soc_block_list[16],
  37376         soc_portreg,
  37377         1,
  37378         0,
  37379         0x4e00,
  37380         SOC_REG_FLAG_64_BITS |
  37381                           SOC_REG_FLAG_COUNTER,
  37382         0,
  37383         1,
  37384         soc_R1023_BCM53400_A0r_fields,
  37385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37386         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37387         113,
  37388         -1,
  37389         3,
  37390     },
  37391 #endif /* chips */
  37392 
  37393 #if defined(BCM_56970_A0)
  37394     { /* SOC_REG_INT_XLMIB_TMCLr */
  37395         soc_block_list[16],
  37396         soc_portreg,
  37397         1,
  37398         0,
  37399         0x5900,
  37400         SOC_REG_FLAG_64_BITS |
  37401                           SOC_REG_FLAG_COUNTER |
  37402                           SOC_REG_FLAG_ED_CNTR,
  37403         0,
  37404         1,
  37405         soc_RALN_BCM53400_A0r_fields,
  37406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37408         144,
  37409         -1,
  37410         3,
  37411     },
  37412 #endif /* chips */
  37413 
  37414 #if defined(BCM_53570_A0)
  37415     { /* SOC_REG_INT_XLMIB_TMCL_BCM53570_A0r */
  37416         soc_block_list[16],
  37417         soc_portreg,
  37418         1,
  37419         0,
  37420         0x5900,
  37421         SOC_REG_FLAG_64_BITS |
  37422                           SOC_REG_FLAG_COUNTER |
  37423                           SOC_REG_FLAG_ED_CNTR,
  37424         0,
  37425         1,
  37426         soc_XLMIB_RSCHCRCr_fields,
  37427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37429         243,
  37430         -1,
  37431     },
  37432 #endif /* chips */
  37433 
  37434 #if defined(BCM_53570_B0)
  37435     { /* SOC_REG_INT_XLMIB_TMCL_BCM53570_B0r */
  37436         soc_block_list[16],
  37437         soc_portreg,
  37438         1,
  37439         0,
  37440         0x5900,
  37441         SOC_REG_FLAG_64_BITS |
  37442                           SOC_REG_FLAG_COUNTER |
  37443                           SOC_REG_FLAG_ED_CNTR,
  37444         0,
  37445         1,
  37446         soc_XLMIB_RSCHCRCr_fields,
  37447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37448         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37449         247,
  37450         -1,
  37451     },
  37452 #endif /* chips */
  37453 
  37454 #if defined(BCM_56370_A0)
  37455     { /* SOC_REG_INT_XLMIB_TMCL_BCM56370_A0r */
  37456         soc_block_list[16],
  37457         soc_portreg,
  37458         1,
  37459         0,
  37460         0x5900,
  37461         SOC_REG_FLAG_64_BITS |
  37462                           SOC_REG_FLAG_COUNTER |
  37463                           SOC_REG_FLAG_ED_CNTR,
  37464         0,
  37465         1,
  37466         soc_RALN_BCM53400_A0r_fields,
  37467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37468         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37469         149,
  37470         -1,
  37471         3,
  37472     },
  37473 #endif /* chips */
  37474 
  37475 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37476     { /* SOC_REG_INT_XLMIB_TMCL_BCM56870_A0r */
  37477         soc_block_list[16],
  37478         soc_portreg,
  37479         1,
  37480         0,
  37481         0x5900,
  37482         SOC_REG_FLAG_64_BITS |
  37483                           SOC_REG_FLAG_COUNTER |
  37484                           SOC_REG_FLAG_ED_CNTR,
  37485         0,
  37486         1,
  37487         soc_RALN_BCM53400_A0r_fields,
  37488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37489         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37490         148,
  37491         -1,
  37492         3,
  37493     },
  37494 #endif /* chips */
  37495 
  37496 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  37497     { /* SOC_REG_INT_XLMIB_TMCL_BCM56980_A0r */
  37498         soc_block_list[16],
  37499         soc_portreg,
  37500         1,
  37501         0,
  37502         0x5900,
  37503         SOC_REG_FLAG_64_BITS |
  37504                           SOC_REG_FLAG_COUNTER |
  37505                           SOC_REG_FLAG_ED_CNTR,
  37506         0,
  37507         1,
  37508         soc_RALN_BCM53400_A0r_fields,
  37509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37510         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37511         124,
  37512         -1,
  37513         3,
  37514     },
  37515 #endif /* chips */
  37516 
  37517 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37518     { /* SOC_REG_INT_XLMIB_TMGVr */
  37519         soc_block_list[16],
  37520         soc_portreg,
  37521         1,
  37522         0,
  37523         0x4600,
  37524         SOC_REG_FLAG_64_BITS |
  37525                           SOC_REG_FLAG_COUNTER,
  37526         0,
  37527         1,
  37528         soc_R1023_BCM53400_A0r_fields,
  37529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37530         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37531         129,
  37532         -1,
  37533         3,
  37534     },
  37535 #endif /* chips */
  37536 
  37537 #if defined(BCM_53570_A0)
  37538     { /* SOC_REG_INT_XLMIB_TMGV_BCM53570_A0r */
  37539         soc_block_list[16],
  37540         soc_portreg,
  37541         1,
  37542         0,
  37543         0x4600,
  37544         SOC_REG_FLAG_64_BITS |
  37545                           SOC_REG_FLAG_COUNTER,
  37546         0,
  37547         1,
  37548         soc_R1023_BCM53400_A0r_fields,
  37549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37550         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37551         224,
  37552         -1,
  37553     },
  37554 #endif /* chips */
  37555 
  37556 #if defined(BCM_53570_B0)
  37557     { /* SOC_REG_INT_XLMIB_TMGV_BCM53570_B0r */
  37558         soc_block_list[16],
  37559         soc_portreg,
  37560         1,
  37561         0,
  37562         0x4600,
  37563         SOC_REG_FLAG_64_BITS |
  37564                           SOC_REG_FLAG_COUNTER,
  37565         0,
  37566         1,
  37567         soc_R1023_BCM53400_A0r_fields,
  37568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37569         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37570         228,
  37571         -1,
  37572     },
  37573 #endif /* chips */
  37574 
  37575 #if defined(BCM_56370_A0)
  37576     { /* SOC_REG_INT_XLMIB_TMGV_BCM56370_A0r */
  37577         soc_block_list[16],
  37578         soc_portreg,
  37579         1,
  37580         0,
  37581         0x4600,
  37582         SOC_REG_FLAG_64_BITS |
  37583                           SOC_REG_FLAG_COUNTER,
  37584         0,
  37585         1,
  37586         soc_R1023_BCM53400_A0r_fields,
  37587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37588         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37589         130,
  37590         -1,
  37591         3,
  37592     },
  37593 #endif /* chips */
  37594 
  37595 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  37596     { /* SOC_REG_INT_XLMIB_TMGV_BCM56980_A0r */
  37597         soc_block_list[16],
  37598         soc_portreg,
  37599         1,
  37600         0,
  37601         0x4600,
  37602         SOC_REG_FLAG_64_BITS |
  37603                           SOC_REG_FLAG_COUNTER,
  37604         0,
  37605         1,
  37606         soc_R1023_BCM53400_A0r_fields,
  37607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37608         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37609         105,
  37610         -1,
  37611         3,
  37612     },
  37613 #endif /* chips */
  37614 
  37615 #if defined(BCM_56970_A0)
  37616     { /* SOC_REG_INT_XLMIB_TNCLr */
  37617         soc_block_list[16],
  37618         soc_portreg,
  37619         1,
  37620         0,
  37621         0x6e00,
  37622         SOC_REG_FLAG_64_BITS |
  37623                           SOC_REG_FLAG_COUNTER,
  37624         0,
  37625         1,
  37626         soc_RALN_BCM53400_A0r_fields,
  37627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37628         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37629         165,
  37630         -1,
  37631         3,
  37632     },
  37633 #endif /* chips */
  37634 
  37635 #if defined(BCM_53570_A0)
  37636     { /* SOC_REG_INT_XLMIB_TNCL_BCM53570_A0r */
  37637         soc_block_list[16],
  37638         soc_portreg,
  37639         1,
  37640         0,
  37641         0x6e00,
  37642         SOC_REG_FLAG_64_BITS |
  37643                           SOC_REG_FLAG_COUNTER,
  37644         0,
  37645         1,
  37646         soc_XLMIB_RSCHCRCr_fields,
  37647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37649         264,
  37650         -1,
  37651     },
  37652 #endif /* chips */
  37653 
  37654 #if defined(BCM_53570_B0)
  37655     { /* SOC_REG_INT_XLMIB_TNCL_BCM53570_B0r */
  37656         soc_block_list[16],
  37657         soc_portreg,
  37658         1,
  37659         0,
  37660         0x6e00,
  37661         SOC_REG_FLAG_64_BITS |
  37662                           SOC_REG_FLAG_COUNTER,
  37663         0,
  37664         1,
  37665         soc_XLMIB_RSCHCRCr_fields,
  37666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37667         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37668         268,
  37669         -1,
  37670     },
  37671 #endif /* chips */
  37672 
  37673 #if defined(BCM_56370_A0)
  37674     { /* SOC_REG_INT_XLMIB_TNCL_BCM56370_A0r */
  37675         soc_block_list[16],
  37676         soc_portreg,
  37677         1,
  37678         0,
  37679         0x6e00,
  37680         SOC_REG_FLAG_64_BITS |
  37681                           SOC_REG_FLAG_COUNTER,
  37682         0,
  37683         1,
  37684         soc_RALN_BCM53400_A0r_fields,
  37685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37686         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37687         170,
  37688         -1,
  37689         3,
  37690     },
  37691 #endif /* chips */
  37692 
  37693 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37694     { /* SOC_REG_INT_XLMIB_TNCL_BCM56870_A0r */
  37695         soc_block_list[16],
  37696         soc_portreg,
  37697         1,
  37698         0,
  37699         0x6e00,
  37700         SOC_REG_FLAG_64_BITS |
  37701                           SOC_REG_FLAG_COUNTER,
  37702         0,
  37703         1,
  37704         soc_RALN_BCM53400_A0r_fields,
  37705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37706         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37707         169,
  37708         -1,
  37709         3,
  37710     },
  37711 #endif /* chips */
  37712 
  37713 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  37714     { /* SOC_REG_INT_XLMIB_TNCL_BCM56980_A0r */
  37715         soc_block_list[16],
  37716         soc_portreg,
  37717         1,
  37718         0,
  37719         0x6e00,
  37720         SOC_REG_FLAG_64_BITS |
  37721                           SOC_REG_FLAG_COUNTER,
  37722         0,
  37723         1,
  37724         soc_RALN_BCM53400_A0r_fields,
  37725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37726         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37727         145,
  37728         -1,
  37729         3,
  37730     },
  37731 #endif /* chips */
  37732 
  37733 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37734     { /* SOC_REG_INT_XLMIB_TOVRr */
  37735         soc_block_list[16],
  37736         soc_portreg,
  37737         1,
  37738         0,
  37739         0x5500,
  37740         SOC_REG_FLAG_64_BITS |
  37741                           SOC_REG_FLAG_COUNTER |
  37742                           SOC_REG_FLAG_ED_CNTR,
  37743         0,
  37744         1,
  37745         soc_R1023_BCM53400_A0r_fields,
  37746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37747         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37748         144,
  37749         -1,
  37750         3,
  37751     },
  37752 #endif /* chips */
  37753 
  37754 #if defined(BCM_53570_A0)
  37755     { /* SOC_REG_INT_XLMIB_TOVR_BCM53570_A0r */
  37756         soc_block_list[16],
  37757         soc_portreg,
  37758         1,
  37759         0,
  37760         0x5500,
  37761         SOC_REG_FLAG_64_BITS |
  37762                           SOC_REG_FLAG_COUNTER |
  37763                           SOC_REG_FLAG_ED_CNTR,
  37764         0,
  37765         1,
  37766         soc_R1023_BCM53400_A0r_fields,
  37767         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37768         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37769         239,
  37770         -1,
  37771     },
  37772 #endif /* chips */
  37773 
  37774 #if defined(BCM_53570_B0)
  37775     { /* SOC_REG_INT_XLMIB_TOVR_BCM53570_B0r */
  37776         soc_block_list[16],
  37777         soc_portreg,
  37778         1,
  37779         0,
  37780         0x5500,
  37781         SOC_REG_FLAG_64_BITS |
  37782                           SOC_REG_FLAG_COUNTER |
  37783                           SOC_REG_FLAG_ED_CNTR,
  37784         0,
  37785         1,
  37786         soc_R1023_BCM53400_A0r_fields,
  37787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37788         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37789         243,
  37790         -1,
  37791     },
  37792 #endif /* chips */
  37793 
  37794 #if defined(BCM_56370_A0)
  37795     { /* SOC_REG_INT_XLMIB_TOVR_BCM56370_A0r */
  37796         soc_block_list[16],
  37797         soc_portreg,
  37798         1,
  37799         0,
  37800         0x5500,
  37801         SOC_REG_FLAG_64_BITS |
  37802                           SOC_REG_FLAG_COUNTER |
  37803                           SOC_REG_FLAG_ED_CNTR,
  37804         0,
  37805         1,
  37806         soc_R1023_BCM53400_A0r_fields,
  37807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37808         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37809         145,
  37810         -1,
  37811         3,
  37812     },
  37813 #endif /* chips */
  37814 
  37815 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  37816     { /* SOC_REG_INT_XLMIB_TOVR_BCM56980_A0r */
  37817         soc_block_list[16],
  37818         soc_portreg,
  37819         1,
  37820         0,
  37821         0x5500,
  37822         SOC_REG_FLAG_64_BITS |
  37823                           SOC_REG_FLAG_COUNTER |
  37824                           SOC_REG_FLAG_ED_CNTR,
  37825         0,
  37826         1,
  37827         soc_R1023_BCM53400_A0r_fields,
  37828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37829         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37830         120,
  37831         -1,
  37832         3,
  37833     },
  37834 #endif /* chips */
  37835 
  37836 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37837     { /* SOC_REG_INT_XLMIB_TPFC0r */
  37838         soc_block_list[16],
  37839         soc_portreg,
  37840         1,
  37841         0,
  37842         0x6200,
  37843         SOC_REG_FLAG_64_BITS |
  37844                           SOC_REG_FLAG_COUNTER,
  37845         0,
  37846         1,
  37847         soc_R1023_BCM53400_A0r_fields,
  37848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37849         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37850         157,
  37851         -1,
  37852         3,
  37853     },
  37854 #endif /* chips */
  37855 
  37856 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37857     { /* SOC_REG_INT_XLMIB_TPFC1r */
  37858         soc_block_list[16],
  37859         soc_portreg,
  37860         1,
  37861         0,
  37862         0x6300,
  37863         SOC_REG_FLAG_64_BITS |
  37864                           SOC_REG_FLAG_COUNTER,
  37865         0,
  37866         1,
  37867         soc_R1023_BCM53400_A0r_fields,
  37868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37869         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37870         158,
  37871         -1,
  37872         3,
  37873     },
  37874 #endif /* chips */
  37875 
  37876 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37877     { /* SOC_REG_INT_XLMIB_TPFC2r */
  37878         soc_block_list[16],
  37879         soc_portreg,
  37880         1,
  37881         0,
  37882         0x6400,
  37883         SOC_REG_FLAG_64_BITS |
  37884                           SOC_REG_FLAG_COUNTER,
  37885         0,
  37886         1,
  37887         soc_R1023_BCM53400_A0r_fields,
  37888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37889         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37890         159,
  37891         -1,
  37892         3,
  37893     },
  37894 #endif /* chips */
  37895 
  37896 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37897     { /* SOC_REG_INT_XLMIB_TPFC3r */
  37898         soc_block_list[16],
  37899         soc_portreg,
  37900         1,
  37901         0,
  37902         0x6500,
  37903         SOC_REG_FLAG_64_BITS |
  37904                           SOC_REG_FLAG_COUNTER,
  37905         0,
  37906         1,
  37907         soc_R1023_BCM53400_A0r_fields,
  37908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37909         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37910         160,
  37911         -1,
  37912         3,
  37913     },
  37914 #endif /* chips */
  37915 
  37916 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37917     { /* SOC_REG_INT_XLMIB_TPFC4r */
  37918         soc_block_list[16],
  37919         soc_portreg,
  37920         1,
  37921         0,
  37922         0x6600,
  37923         SOC_REG_FLAG_64_BITS |
  37924                           SOC_REG_FLAG_COUNTER,
  37925         0,
  37926         1,
  37927         soc_R1023_BCM53400_A0r_fields,
  37928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37929         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37930         161,
  37931         -1,
  37932         3,
  37933     },
  37934 #endif /* chips */
  37935 
  37936 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37937     { /* SOC_REG_INT_XLMIB_TPFC5r */
  37938         soc_block_list[16],
  37939         soc_portreg,
  37940         1,
  37941         0,
  37942         0x6700,
  37943         SOC_REG_FLAG_64_BITS |
  37944                           SOC_REG_FLAG_COUNTER,
  37945         0,
  37946         1,
  37947         soc_R1023_BCM53400_A0r_fields,
  37948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37949         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37950         162,
  37951         -1,
  37952         3,
  37953     },
  37954 #endif /* chips */
  37955 
  37956 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37957     { /* SOC_REG_INT_XLMIB_TPFC6r */
  37958         soc_block_list[16],
  37959         soc_portreg,
  37960         1,
  37961         0,
  37962         0x6800,
  37963         SOC_REG_FLAG_64_BITS |
  37964                           SOC_REG_FLAG_COUNTER,
  37965         0,
  37966         1,
  37967         soc_R1023_BCM53400_A0r_fields,
  37968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37969         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37970         163,
  37971         -1,
  37972         3,
  37973     },
  37974 #endif /* chips */
  37975 
  37976 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  37977     { /* SOC_REG_INT_XLMIB_TPFC7r */
  37978         soc_block_list[16],
  37979         soc_portreg,
  37980         1,
  37981         0,
  37982         0x6900,
  37983         SOC_REG_FLAG_64_BITS |
  37984                           SOC_REG_FLAG_COUNTER,
  37985         0,
  37986         1,
  37987         soc_R1023_BCM53400_A0r_fields,
  37988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  37990         164,
  37991         -1,
  37992         3,
  37993     },
  37994 #endif /* chips */
  37995 
  37996 #if defined(BCM_53570_A0)
  37997     { /* SOC_REG_INT_XLMIB_TPFC0_BCM53570_A0r */
  37998         soc_block_list[16],
  37999         soc_portreg,
  38000         1,
  38001         0,
  38002         0x6200,
  38003         SOC_REG_FLAG_64_BITS |
  38004                           SOC_REG_FLAG_COUNTER,
  38005         0,
  38006         1,
  38007         soc_R1023_BCM53400_A0r_fields,
  38008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38009         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38010         252,
  38011         -1,
  38012     },
  38013 #endif /* chips */
  38014 
  38015 #if defined(BCM_53570_B0)
  38016     { /* SOC_REG_INT_XLMIB_TPFC0_BCM53570_B0r */
  38017         soc_block_list[16],
  38018         soc_portreg,
  38019         1,
  38020         0,
  38021         0x6200,
  38022         SOC_REG_FLAG_64_BITS |
  38023                           SOC_REG_FLAG_COUNTER,
  38024         0,
  38025         1,
  38026         soc_R1023_BCM53400_A0r_fields,
  38027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38028         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38029         256,
  38030         -1,
  38031     },
  38032 #endif /* chips */
  38033 
  38034 #if defined(BCM_56370_A0)
  38035     { /* SOC_REG_INT_XLMIB_TPFC0_BCM56370_A0r */
  38036         soc_block_list[16],
  38037         soc_portreg,
  38038         1,
  38039         0,
  38040         0x6200,
  38041         SOC_REG_FLAG_64_BITS |
  38042                           SOC_REG_FLAG_COUNTER,
  38043         0,
  38044         1,
  38045         soc_R1023_BCM53400_A0r_fields,
  38046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38048         158,
  38049         -1,
  38050         3,
  38051     },
  38052 #endif /* chips */
  38053 
  38054 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  38055     { /* SOC_REG_INT_XLMIB_TPFC0_BCM56980_A0r */
  38056         soc_block_list[16],
  38057         soc_portreg,
  38058         1,
  38059         0,
  38060         0x6200,
  38061         SOC_REG_FLAG_64_BITS |
  38062                           SOC_REG_FLAG_COUNTER,
  38063         0,
  38064         1,
  38065         soc_R1023_BCM53400_A0r_fields,
  38066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38067         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38068         133,
  38069         -1,
  38070         3,
  38071     },
  38072 #endif /* chips */
  38073 
  38074 #if defined(BCM_53570_A0)
  38075     { /* SOC_REG_INT_XLMIB_TPFC1_BCM53570_A0r */
  38076         soc_block_list[16],
  38077         soc_portreg,
  38078         1,
  38079         0,
  38080         0x6300,
  38081         SOC_REG_FLAG_64_BITS |
  38082                           SOC_REG_FLAG_COUNTER,
  38083         0,
  38084         1,
  38085         soc_R1023_BCM53400_A0r_fields,
  38086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38088         253,
  38089         -1,
  38090     },
  38091 #endif /* chips */
  38092 
  38093 #if defined(BCM_53570_B0)
  38094     { /* SOC_REG_INT_XLMIB_TPFC1_BCM53570_B0r */
  38095         soc_block_list[16],
  38096         soc_portreg,
  38097         1,
  38098         0,
  38099         0x6300,
  38100         SOC_REG_FLAG_64_BITS |
  38101                           SOC_REG_FLAG_COUNTER,
  38102         0,
  38103         1,
  38104         soc_R1023_BCM53400_A0r_fields,
  38105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38106         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38107         257,
  38108         -1,
  38109     },
  38110 #endif /* chips */
  38111 
  38112 #if defined(BCM_56370_A0)
  38113     { /* SOC_REG_INT_XLMIB_TPFC1_BCM56370_A0r */
  38114         soc_block_list[16],
  38115         soc_portreg,
  38116         1,
  38117         0,
  38118         0x6300,
  38119         SOC_REG_FLAG_64_BITS |
  38120                           SOC_REG_FLAG_COUNTER,
  38121         0,
  38122         1,
  38123         soc_R1023_BCM53400_A0r_fields,
  38124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38125         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38126         159,
  38127         -1,
  38128         3,
  38129     },
  38130 #endif /* chips */
  38131 
  38132 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  38133     { /* SOC_REG_INT_XLMIB_TPFC1_BCM56980_A0r */
  38134         soc_block_list[16],
  38135         soc_portreg,
  38136         1,
  38137         0,
  38138         0x6300,
  38139         SOC_REG_FLAG_64_BITS |
  38140                           SOC_REG_FLAG_COUNTER,
  38141         0,
  38142         1,
  38143         soc_R1023_BCM53400_A0r_fields,
  38144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38145         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38146         134,
  38147         -1,
  38148         3,
  38149     },
  38150 #endif /* chips */
  38151 
  38152 #if defined(BCM_53570_A0)
  38153     { /* SOC_REG_INT_XLMIB_TPFC2_BCM53570_A0r */
  38154         soc_block_list[16],
  38155         soc_portreg,
  38156         1,
  38157         0,
  38158         0x6400,
  38159         SOC_REG_FLAG_64_BITS |
  38160                           SOC_REG_FLAG_COUNTER,
  38161         0,
  38162         1,
  38163         soc_R1023_BCM53400_A0r_fields,
  38164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38165         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38166         254,
  38167         -1,
  38168     },
  38169 #endif /* chips */
  38170 
  38171 #if defined(BCM_53570_B0)
  38172     { /* SOC_REG_INT_XLMIB_TPFC2_BCM53570_B0r */
  38173         soc_block_list[16],
  38174         soc_portreg,
  38175         1,
  38176         0,
  38177         0x6400,
  38178         SOC_REG_FLAG_64_BITS |
  38179                           SOC_REG_FLAG_COUNTER,
  38180         0,
  38181         1,
  38182         soc_R1023_BCM53400_A0r_fields,
  38183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38184         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38185         258,
  38186         -1,
  38187     },
  38188 #endif /* chips */
  38189 
  38190 #if defined(BCM_56370_A0)
  38191     { /* SOC_REG_INT_XLMIB_TPFC2_BCM56370_A0r */
  38192         soc_block_list[16],
  38193         soc_portreg,
  38194         1,
  38195         0,
  38196         0x6400,
  38197         SOC_REG_FLAG_64_BITS |
  38198                           SOC_REG_FLAG_COUNTER,
  38199         0,
  38200         1,
  38201         soc_R1023_BCM53400_A0r_fields,
  38202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38203         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38204         160,
  38205         -1,
  38206         3,
  38207     },
  38208 #endif /* chips */
  38209 
  38210 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  38211     { /* SOC_REG_INT_XLMIB_TPFC2_BCM56980_A0r */
  38212         soc_block_list[16],
  38213         soc_portreg,
  38214         1,
  38215         0,
  38216         0x6400,
  38217         SOC_REG_FLAG_64_BITS |
  38218                           SOC_REG_FLAG_COUNTER,
  38219         0,
  38220         1,
  38221         soc_R1023_BCM53400_A0r_fields,
  38222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38223         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38224         135,
  38225         -1,
  38226         3,
  38227     },
  38228 #endif /* chips */
  38229 
  38230 #if defined(BCM_53570_A0)
  38231     { /* SOC_REG_INT_XLMIB_TPFC3_BCM53570_A0r */
  38232         soc_block_list[16],
  38233         soc_portreg,
  38234         1,
  38235         0,
  38236         0x6500,
  38237         SOC_REG_FLAG_64_BITS |
  38238                           SOC_REG_FLAG_COUNTER,
  38239         0,
  38240         1,
  38241         soc_R1023_BCM53400_A0r_fields,
  38242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38243         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38244         255,
  38245         -1,
  38246     },
  38247 #endif /* chips */
  38248 
  38249 #if defined(BCM_53570_B0)
  38250     { /* SOC_REG_INT_XLMIB_TPFC3_BCM53570_B0r */
  38251         soc_block_list[16],
  38252         soc_portreg,
  38253         1,
  38254         0,
  38255         0x6500,
  38256         SOC_REG_FLAG_64_BITS |
  38257                           SOC_REG_FLAG_COUNTER,
  38258         0,
  38259         1,
  38260         soc_R1023_BCM53400_A0r_fields,
  38261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38262         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38263         259,
  38264         -1,
  38265     },
  38266 #endif /* chips */
  38267 
  38268 #if defined(BCM_56370_A0)
  38269     { /* SOC_REG_INT_XLMIB_TPFC3_BCM56370_A0r */
  38270         soc_block_list[16],
  38271         soc_portreg,
  38272         1,
  38273         0,
  38274         0x6500,
  38275         SOC_REG_FLAG_64_BITS |
  38276                           SOC_REG_FLAG_COUNTER,
  38277         0,
  38278         1,
  38279         soc_R1023_BCM53400_A0r_fields,
  38280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38281         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38282         161,
  38283         -1,
  38284         3,
  38285     },
  38286 #endif /* chips */
  38287 
  38288 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  38289     { /* SOC_REG_INT_XLMIB_TPFC3_BCM56980_A0r */
  38290         soc_block_list[16],
  38291         soc_portreg,
  38292         1,
  38293         0,
  38294         0x6500,
  38295         SOC_REG_FLAG_64_BITS |
  38296                           SOC_REG_FLAG_COUNTER,
  38297         0,
  38298         1,
  38299         soc_R1023_BCM53400_A0r_fields,
  38300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38301         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38302         136,
  38303         -1,
  38304         3,
  38305     },
  38306 #endif /* chips */
  38307 
  38308 #if defined(BCM_53570_A0)
  38309     { /* SOC_REG_INT_XLMIB_TPFC4_BCM53570_A0r */
  38310         soc_block_list[16],
  38311         soc_portreg,
  38312         1,
  38313         0,
  38314         0x6600,
  38315         SOC_REG_FLAG_64_BITS |
  38316                           SOC_REG_FLAG_COUNTER,
  38317         0,
  38318         1,
  38319         soc_R1023_BCM53400_A0r_fields,
  38320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38321         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38322         256,
  38323         -1,
  38324     },
  38325 #endif /* chips */
  38326 
  38327 #if defined(BCM_53570_B0)
  38328     { /* SOC_REG_INT_XLMIB_TPFC4_BCM53570_B0r */
  38329         soc_block_list[16],
  38330         soc_portreg,
  38331         1,
  38332         0,
  38333         0x6600,
  38334         SOC_REG_FLAG_64_BITS |
  38335                           SOC_REG_FLAG_COUNTER,
  38336         0,
  38337         1,
  38338         soc_R1023_BCM53400_A0r_fields,
  38339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38340         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38341         260,
  38342         -1,
  38343     },
  38344 #endif /* chips */
  38345 
  38346 #if defined(BCM_56370_A0)
  38347     { /* SOC_REG_INT_XLMIB_TPFC4_BCM56370_A0r */
  38348         soc_block_list[16],
  38349         soc_portreg,
  38350         1,
  38351         0,
  38352         0x6600,
  38353         SOC_REG_FLAG_64_BITS |
  38354                           SOC_REG_FLAG_COUNTER,
  38355         0,
  38356         1,
  38357         soc_R1023_BCM53400_A0r_fields,
  38358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38359         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38360         162,
  38361         -1,
  38362         3,
  38363     },
  38364 #endif /* chips */
  38365 
  38366 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  38367     { /* SOC_REG_INT_XLMIB_TPFC4_BCM56980_A0r */
  38368         soc_block_list[16],
  38369         soc_portreg,
  38370         1,
  38371         0,
  38372         0x6600,
  38373         SOC_REG_FLAG_64_BITS |
  38374                           SOC_REG_FLAG_COUNTER,
  38375         0,
  38376         1,
  38377         soc_R1023_BCM53400_A0r_fields,
  38378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38379         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38380         137,
  38381         -1,
  38382         3,
  38383     },
  38384 #endif /* chips */
  38385 
  38386 #if defined(BCM_53570_A0)
  38387     { /* SOC_REG_INT_XLMIB_TPFC5_BCM53570_A0r */
  38388         soc_block_list[16],
  38389         soc_portreg,
  38390         1,
  38391         0,
  38392         0x6700,
  38393         SOC_REG_FLAG_64_BITS |
  38394                           SOC_REG_FLAG_COUNTER,
  38395         0,
  38396         1,
  38397         soc_R1023_BCM53400_A0r_fields,
  38398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38399         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38400         257,
  38401         -1,
  38402     },
  38403 #endif /* chips */
  38404 
  38405 #if defined(BCM_53570_B0)
  38406     { /* SOC_REG_INT_XLMIB_TPFC5_BCM53570_B0r */
  38407         soc_block_list[16],
  38408         soc_portreg,
  38409         1,
  38410         0,
  38411         0x6700,
  38412         SOC_REG_FLAG_64_BITS |
  38413                           SOC_REG_FLAG_COUNTER,
  38414         0,
  38415         1,
  38416         soc_R1023_BCM53400_A0r_fields,
  38417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38418         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38419         261,
  38420         -1,
  38421     },
  38422 #endif /* chips */
  38423 
  38424 #if defined(BCM_56370_A0)
  38425     { /* SOC_REG_INT_XLMIB_TPFC5_BCM56370_A0r */
  38426         soc_block_list[16],
  38427         soc_portreg,
  38428         1,
  38429         0,
  38430         0x6700,
  38431         SOC_REG_FLAG_64_BITS |
  38432                           SOC_REG_FLAG_COUNTER,
  38433         0,
  38434         1,
  38435         soc_R1023_BCM53400_A0r_fields,
  38436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38437         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38438         163,
  38439         -1,
  38440         3,
  38441     },
  38442 #endif /* chips */
  38443 
  38444 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  38445     { /* SOC_REG_INT_XLMIB_TPFC5_BCM56980_A0r */
  38446         soc_block_list[16],
  38447         soc_portreg,
  38448         1,
  38449         0,
  38450         0x6700,
  38451         SOC_REG_FLAG_64_BITS |
  38452                           SOC_REG_FLAG_COUNTER,
  38453         0,
  38454         1,
  38455         soc_R1023_BCM53400_A0r_fields,
  38456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38457         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38458         138,
  38459         -1,
  38460         3,
  38461     },
  38462 #endif /* chips */
  38463 
  38464 #if defined(BCM_53570_A0)
  38465     { /* SOC_REG_INT_XLMIB_TPFC6_BCM53570_A0r */
  38466         soc_block_list[16],
  38467         soc_portreg,
  38468         1,
  38469         0,
  38470         0x6800,
  38471         SOC_REG_FLAG_64_BITS |
  38472                           SOC_REG_FLAG_COUNTER,
  38473         0,
  38474         1,
  38475         soc_R1023_BCM53400_A0r_fields,
  38476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38477         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38478         258,
  38479         -1,
  38480     },
  38481 #endif /* chips */
  38482 
  38483 #if defined(BCM_53570_B0)
  38484     { /* SOC_REG_INT_XLMIB_TPFC6_BCM53570_B0r */
  38485         soc_block_list[16],
  38486         soc_portreg,
  38487         1,
  38488         0,
  38489         0x6800,
  38490         SOC_REG_FLAG_64_BITS |
  38491                           SOC_REG_FLAG_COUNTER,
  38492         0,
  38493         1,
  38494         soc_R1023_BCM53400_A0r_fields,
  38495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38496         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38497         262,
  38498         -1,
  38499     },
  38500 #endif /* chips */
  38501 
  38502 #if defined(BCM_56370_A0)
  38503     { /* SOC_REG_INT_XLMIB_TPFC6_BCM56370_A0r */
  38504         soc_block_list[16],
  38505         soc_portreg,
  38506         1,
  38507         0,
  38508         0x6800,
  38509         SOC_REG_FLAG_64_BITS |
  38510                           SOC_REG_FLAG_COUNTER,
  38511         0,
  38512         1,
  38513         soc_R1023_BCM53400_A0r_fields,
  38514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38515         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38516         164,
  38517         -1,
  38518         3,
  38519     },
  38520 #endif /* chips */
  38521 
  38522 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  38523     { /* SOC_REG_INT_XLMIB_TPFC6_BCM56980_A0r */
  38524         soc_block_list[16],
  38525         soc_portreg,
  38526         1,
  38527         0,
  38528         0x6800,
  38529         SOC_REG_FLAG_64_BITS |
  38530                           SOC_REG_FLAG_COUNTER,
  38531         0,
  38532         1,
  38533         soc_R1023_BCM53400_A0r_fields,
  38534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38535         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38536         139,
  38537         -1,
  38538         3,
  38539     },
  38540 #endif /* chips */
  38541 
  38542 #if defined(BCM_53570_A0)
  38543     { /* SOC_REG_INT_XLMIB_TPFC7_BCM53570_A0r */
  38544         soc_block_list[16],
  38545         soc_portreg,
  38546         1,
  38547         0,
  38548         0x6900,
  38549         SOC_REG_FLAG_64_BITS |
  38550                           SOC_REG_FLAG_COUNTER,
  38551         0,
  38552         1,
  38553         soc_R1023_BCM53400_A0r_fields,
  38554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38556         259,
  38557         -1,
  38558     },
  38559 #endif /* chips */
  38560 
  38561 #if defined(BCM_53570_B0)
  38562     { /* SOC_REG_INT_XLMIB_TPFC7_BCM53570_B0r */
  38563         soc_block_list[16],
  38564         soc_portreg,
  38565         1,
  38566         0,
  38567         0x6900,
  38568         SOC_REG_FLAG_64_BITS |
  38569                           SOC_REG_FLAG_COUNTER,
  38570         0,
  38571         1,
  38572         soc_R1023_BCM53400_A0r_fields,
  38573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38574         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38575         263,
  38576         -1,
  38577     },
  38578 #endif /* chips */
  38579 
  38580 #if defined(BCM_56370_A0)
  38581     { /* SOC_REG_INT_XLMIB_TPFC7_BCM56370_A0r */
  38582         soc_block_list[16],
  38583         soc_portreg,
  38584         1,
  38585         0,
  38586         0x6900,
  38587         SOC_REG_FLAG_64_BITS |
  38588                           SOC_REG_FLAG_COUNTER,
  38589         0,
  38590         1,
  38591         soc_R1023_BCM53400_A0r_fields,
  38592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38593         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38594         165,
  38595         -1,
  38596         3,
  38597     },
  38598 #endif /* chips */
  38599 
  38600 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  38601     { /* SOC_REG_INT_XLMIB_TPFC7_BCM56980_A0r */
  38602         soc_block_list[16],
  38603         soc_portreg,
  38604         1,
  38605         0,
  38606         0x6900,
  38607         SOC_REG_FLAG_64_BITS |
  38608                           SOC_REG_FLAG_COUNTER,
  38609         0,
  38610         1,
  38611         soc_R1023_BCM53400_A0r_fields,
  38612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38613         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38614         140,
  38615         -1,
  38616         3,
  38617     },
  38618 #endif /* chips */
  38619 
  38620 #if defined(BCM_56970_A0)
  38621     { /* SOC_REG_INT_XLMIB_TPFCOFF0r */
  38622         soc_block_list[16],
  38623         soc_portreg,
  38624         1,
  38625         0,
  38626         0x7900,
  38627         SOC_REG_FLAG_64_BITS |
  38628                           SOC_REG_FLAG_COUNTER,
  38629         0,
  38630         1,
  38631         soc_R1023_BCM53400_A0r_fields,
  38632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38634         176,
  38635         -1,
  38636         3,
  38637     },
  38638 #endif /* chips */
  38639 
  38640 #if defined(BCM_56970_A0)
  38641     { /* SOC_REG_INT_XLMIB_TPFCOFF1r */
  38642         soc_block_list[16],
  38643         soc_portreg,
  38644         1,
  38645         0,
  38646         0x7a00,
  38647         SOC_REG_FLAG_64_BITS |
  38648                           SOC_REG_FLAG_COUNTER,
  38649         0,
  38650         1,
  38651         soc_R1023_BCM53400_A0r_fields,
  38652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38653         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38654         177,
  38655         -1,
  38656         3,
  38657     },
  38658 #endif /* chips */
  38659 
  38660 #if defined(BCM_56970_A0)
  38661     { /* SOC_REG_INT_XLMIB_TPFCOFF2r */
  38662         soc_block_list[16],
  38663         soc_portreg,
  38664         1,
  38665         0,
  38666         0x7b00,
  38667         SOC_REG_FLAG_64_BITS |
  38668                           SOC_REG_FLAG_COUNTER,
  38669         0,
  38670         1,
  38671         soc_R1023_BCM53400_A0r_fields,
  38672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38673         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38674         178,
  38675         -1,
  38676         3,
  38677     },
  38678 #endif /* chips */
  38679 
  38680 #if defined(BCM_56970_A0)
  38681     { /* SOC_REG_INT_XLMIB_TPFCOFF3r */
  38682         soc_block_list[16],
  38683         soc_portreg,
  38684         1,
  38685         0,
  38686         0x7c00,
  38687         SOC_REG_FLAG_64_BITS |
  38688                           SOC_REG_FLAG_COUNTER,
  38689         0,
  38690         1,
  38691         soc_R1023_BCM53400_A0r_fields,
  38692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38693         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38694         179,
  38695         -1,
  38696         3,
  38697     },
  38698 #endif /* chips */
  38699 
  38700 #if defined(BCM_56970_A0)
  38701     { /* SOC_REG_INT_XLMIB_TPFCOFF4r */
  38702         soc_block_list[16],
  38703         soc_portreg,
  38704         1,
  38705         0,
  38706         0x7d00,
  38707         SOC_REG_FLAG_64_BITS |
  38708                           SOC_REG_FLAG_COUNTER,
  38709         0,
  38710         1,
  38711         soc_R1023_BCM53400_A0r_fields,
  38712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38713         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38714         180,
  38715         -1,
  38716         3,
  38717     },
  38718 #endif /* chips */
  38719 
  38720 #if defined(BCM_56970_A0)
  38721     { /* SOC_REG_INT_XLMIB_TPFCOFF5r */
  38722         soc_block_list[16],
  38723         soc_portreg,
  38724         1,
  38725         0,
  38726         0x7e00,
  38727         SOC_REG_FLAG_64_BITS |
  38728                           SOC_REG_FLAG_COUNTER,
  38729         0,
  38730         1,
  38731         soc_R1023_BCM53400_A0r_fields,
  38732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38733         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38734         181,
  38735         -1,
  38736         3,
  38737     },
  38738 #endif /* chips */
  38739 
  38740 #if defined(BCM_56970_A0)
  38741     { /* SOC_REG_INT_XLMIB_TPFCOFF6r */
  38742         soc_block_list[16],
  38743         soc_portreg,
  38744         1,
  38745         0,
  38746         0x7f00,
  38747         SOC_REG_FLAG_64_BITS |
  38748                           SOC_REG_FLAG_COUNTER,
  38749         0,
  38750         1,
  38751         soc_R1023_BCM53400_A0r_fields,
  38752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38754         182,
  38755         -1,
  38756         3,
  38757     },
  38758 #endif /* chips */
  38759 
  38760 #if defined(BCM_56970_A0)
  38761     { /* SOC_REG_INT_XLMIB_TPFCOFF7r */
  38762         soc_block_list[16],
  38763         soc_portreg,
  38764         1,
  38765         0,
  38766         0x8000,
  38767         SOC_REG_FLAG_64_BITS |
  38768                           SOC_REG_FLAG_COUNTER,
  38769         0,
  38770         1,
  38771         soc_R1023_BCM53400_A0r_fields,
  38772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38773         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38774         183,
  38775         -1,
  38776         3,
  38777     },
  38778 #endif /* chips */
  38779 
  38780 #if defined(BCM_53570_A0)
  38781     { /* SOC_REG_INT_XLMIB_TPFCOFF0_BCM53570_A0r */
  38782         soc_block_list[16],
  38783         soc_portreg,
  38784         1,
  38785         0,
  38786         0x7900,
  38787         SOC_REG_FLAG_64_BITS |
  38788                           SOC_REG_FLAG_COUNTER,
  38789         0,
  38790         1,
  38791         soc_R1023_BCM53400_A0r_fields,
  38792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38793         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38794         275,
  38795         -1,
  38796     },
  38797 #endif /* chips */
  38798 
  38799 #if defined(BCM_53570_B0)
  38800     { /* SOC_REG_INT_XLMIB_TPFCOFF0_BCM53570_B0r */
  38801         soc_block_list[16],
  38802         soc_portreg,
  38803         1,
  38804         0,
  38805         0x7900,
  38806         SOC_REG_FLAG_64_BITS |
  38807                           SOC_REG_FLAG_COUNTER,
  38808         0,
  38809         1,
  38810         soc_R1023_BCM53400_A0r_fields,
  38811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38812         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38813         279,
  38814         -1,
  38815     },
  38816 #endif /* chips */
  38817 
  38818 #if defined(BCM_56370_A0)
  38819     { /* SOC_REG_INT_XLMIB_TPFCOFF0_BCM56370_A0r */
  38820         soc_block_list[16],
  38821         soc_portreg,
  38822         1,
  38823         0,
  38824         0x7900,
  38825         SOC_REG_FLAG_64_BITS |
  38826                           SOC_REG_FLAG_COUNTER,
  38827         0,
  38828         1,
  38829         soc_R1023_BCM53400_A0r_fields,
  38830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38831         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38832         181,
  38833         -1,
  38834         3,
  38835     },
  38836 #endif /* chips */
  38837 
  38838 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  38839     { /* SOC_REG_INT_XLMIB_TPFCOFF0_BCM56870_A0r */
  38840         soc_block_list[16],
  38841         soc_portreg,
  38842         1,
  38843         0,
  38844         0x7900,
  38845         SOC_REG_FLAG_64_BITS |
  38846                           SOC_REG_FLAG_COUNTER,
  38847         0,
  38848         1,
  38849         soc_R1023_BCM53400_A0r_fields,
  38850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38851         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38852         180,
  38853         -1,
  38854         3,
  38855     },
  38856 #endif /* chips */
  38857 
  38858 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  38859     { /* SOC_REG_INT_XLMIB_TPFCOFF0_BCM56980_A0r */
  38860         soc_block_list[16],
  38861         soc_portreg,
  38862         1,
  38863         0,
  38864         0x7900,
  38865         SOC_REG_FLAG_64_BITS |
  38866                           SOC_REG_FLAG_COUNTER,
  38867         0,
  38868         1,
  38869         soc_R1023_BCM53400_A0r_fields,
  38870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38871         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38872         156,
  38873         -1,
  38874         3,
  38875     },
  38876 #endif /* chips */
  38877 
  38878 #if defined(BCM_53570_A0)
  38879     { /* SOC_REG_INT_XLMIB_TPFCOFF1_BCM53570_A0r */
  38880         soc_block_list[16],
  38881         soc_portreg,
  38882         1,
  38883         0,
  38884         0x7a00,
  38885         SOC_REG_FLAG_64_BITS |
  38886                           SOC_REG_FLAG_COUNTER,
  38887         0,
  38888         1,
  38889         soc_R1023_BCM53400_A0r_fields,
  38890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38892         276,
  38893         -1,
  38894     },
  38895 #endif /* chips */
  38896 
  38897 #if defined(BCM_53570_B0)
  38898     { /* SOC_REG_INT_XLMIB_TPFCOFF1_BCM53570_B0r */
  38899         soc_block_list[16],
  38900         soc_portreg,
  38901         1,
  38902         0,
  38903         0x7a00,
  38904         SOC_REG_FLAG_64_BITS |
  38905                           SOC_REG_FLAG_COUNTER,
  38906         0,
  38907         1,
  38908         soc_R1023_BCM53400_A0r_fields,
  38909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38910         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38911         280,
  38912         -1,
  38913     },
  38914 #endif /* chips */
  38915 
  38916 #if defined(BCM_56370_A0)
  38917     { /* SOC_REG_INT_XLMIB_TPFCOFF1_BCM56370_A0r */
  38918         soc_block_list[16],
  38919         soc_portreg,
  38920         1,
  38921         0,
  38922         0x7a00,
  38923         SOC_REG_FLAG_64_BITS |
  38924                           SOC_REG_FLAG_COUNTER,
  38925         0,
  38926         1,
  38927         soc_R1023_BCM53400_A0r_fields,
  38928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38929         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38930         182,
  38931         -1,
  38932         3,
  38933     },
  38934 #endif /* chips */
  38935 
  38936 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  38937     { /* SOC_REG_INT_XLMIB_TPFCOFF1_BCM56870_A0r */
  38938         soc_block_list[16],
  38939         soc_portreg,
  38940         1,
  38941         0,
  38942         0x7a00,
  38943         SOC_REG_FLAG_64_BITS |
  38944                           SOC_REG_FLAG_COUNTER,
  38945         0,
  38946         1,
  38947         soc_R1023_BCM53400_A0r_fields,
  38948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38949         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38950         181,
  38951         -1,
  38952         3,
  38953     },
  38954 #endif /* chips */
  38955 
  38956 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  38957     { /* SOC_REG_INT_XLMIB_TPFCOFF1_BCM56980_A0r */
  38958         soc_block_list[16],
  38959         soc_portreg,
  38960         1,
  38961         0,
  38962         0x7a00,
  38963         SOC_REG_FLAG_64_BITS |
  38964                           SOC_REG_FLAG_COUNTER,
  38965         0,
  38966         1,
  38967         soc_R1023_BCM53400_A0r_fields,
  38968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38969         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38970         157,
  38971         -1,
  38972         3,
  38973     },
  38974 #endif /* chips */
  38975 
  38976 #if defined(BCM_53570_A0)
  38977     { /* SOC_REG_INT_XLMIB_TPFCOFF2_BCM53570_A0r */
  38978         soc_block_list[16],
  38979         soc_portreg,
  38980         1,
  38981         0,
  38982         0x7b00,
  38983         SOC_REG_FLAG_64_BITS |
  38984                           SOC_REG_FLAG_COUNTER,
  38985         0,
  38986         1,
  38987         soc_R1023_BCM53400_A0r_fields,
  38988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  38990         277,
  38991         -1,
  38992     },
  38993 #endif /* chips */
  38994 
  38995 #if defined(BCM_53570_B0)
  38996     { /* SOC_REG_INT_XLMIB_TPFCOFF2_BCM53570_B0r */
  38997         soc_block_list[16],
  38998         soc_portreg,
  38999         1,
  39000         0,
  39001         0x7b00,
  39002         SOC_REG_FLAG_64_BITS |
  39003                           SOC_REG_FLAG_COUNTER,
  39004         0,
  39005         1,
  39006         soc_R1023_BCM53400_A0r_fields,
  39007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39008         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39009         281,
  39010         -1,
  39011     },
  39012 #endif /* chips */
  39013 
  39014 #if defined(BCM_56370_A0)
  39015     { /* SOC_REG_INT_XLMIB_TPFCOFF2_BCM56370_A0r */
  39016         soc_block_list[16],
  39017         soc_portreg,
  39018         1,
  39019         0,
  39020         0x7b00,
  39021         SOC_REG_FLAG_64_BITS |
  39022                           SOC_REG_FLAG_COUNTER,
  39023         0,
  39024         1,
  39025         soc_R1023_BCM53400_A0r_fields,
  39026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39027         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39028         183,
  39029         -1,
  39030         3,
  39031     },
  39032 #endif /* chips */
  39033 
  39034 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  39035     { /* SOC_REG_INT_XLMIB_TPFCOFF2_BCM56870_A0r */
  39036         soc_block_list[16],
  39037         soc_portreg,
  39038         1,
  39039         0,
  39040         0x7b00,
  39041         SOC_REG_FLAG_64_BITS |
  39042                           SOC_REG_FLAG_COUNTER,
  39043         0,
  39044         1,
  39045         soc_R1023_BCM53400_A0r_fields,
  39046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39048         182,
  39049         -1,
  39050         3,
  39051     },
  39052 #endif /* chips */
  39053 
  39054 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  39055     { /* SOC_REG_INT_XLMIB_TPFCOFF2_BCM56980_A0r */
  39056         soc_block_list[16],
  39057         soc_portreg,
  39058         1,
  39059         0,
  39060         0x7b00,
  39061         SOC_REG_FLAG_64_BITS |
  39062                           SOC_REG_FLAG_COUNTER,
  39063         0,
  39064         1,
  39065         soc_R1023_BCM53400_A0r_fields,
  39066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39067         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39068         158,
  39069         -1,
  39070         3,
  39071     },
  39072 #endif /* chips */
  39073 
  39074 #if defined(BCM_53570_A0)
  39075     { /* SOC_REG_INT_XLMIB_TPFCOFF3_BCM53570_A0r */
  39076         soc_block_list[16],
  39077         soc_portreg,
  39078         1,
  39079         0,
  39080         0x7c00,
  39081         SOC_REG_FLAG_64_BITS |
  39082                           SOC_REG_FLAG_COUNTER,
  39083         0,
  39084         1,
  39085         soc_R1023_BCM53400_A0r_fields,
  39086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39088         278,
  39089         -1,
  39090     },
  39091 #endif /* chips */
  39092 
  39093 #if defined(BCM_53570_B0)
  39094     { /* SOC_REG_INT_XLMIB_TPFCOFF3_BCM53570_B0r */
  39095         soc_block_list[16],
  39096         soc_portreg,
  39097         1,
  39098         0,
  39099         0x7c00,
  39100         SOC_REG_FLAG_64_BITS |
  39101                           SOC_REG_FLAG_COUNTER,
  39102         0,
  39103         1,
  39104         soc_R1023_BCM53400_A0r_fields,
  39105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39106         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39107         282,
  39108         -1,
  39109     },
  39110 #endif /* chips */
  39111 
  39112 #if defined(BCM_56370_A0)
  39113     { /* SOC_REG_INT_XLMIB_TPFCOFF3_BCM56370_A0r */
  39114         soc_block_list[16],
  39115         soc_portreg,
  39116         1,
  39117         0,
  39118         0x7c00,
  39119         SOC_REG_FLAG_64_BITS |
  39120                           SOC_REG_FLAG_COUNTER,
  39121         0,
  39122         1,
  39123         soc_R1023_BCM53400_A0r_fields,
  39124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39125         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39126         184,
  39127         -1,
  39128         3,
  39129     },
  39130 #endif /* chips */
  39131 
  39132 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  39133     { /* SOC_REG_INT_XLMIB_TPFCOFF3_BCM56870_A0r */
  39134         soc_block_list[16],
  39135         soc_portreg,
  39136         1,
  39137         0,
  39138         0x7c00,
  39139         SOC_REG_FLAG_64_BITS |
  39140                           SOC_REG_FLAG_COUNTER,
  39141         0,
  39142         1,
  39143         soc_R1023_BCM53400_A0r_fields,
  39144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39145         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39146         183,
  39147         -1,
  39148         3,
  39149     },
  39150 #endif /* chips */
  39151 
  39152 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  39153     { /* SOC_REG_INT_XLMIB_TPFCOFF3_BCM56980_A0r */
  39154         soc_block_list[16],
  39155         soc_portreg,
  39156         1,
  39157         0,
  39158         0x7c00,
  39159         SOC_REG_FLAG_64_BITS |
  39160                           SOC_REG_FLAG_COUNTER,
  39161         0,
  39162         1,
  39163         soc_R1023_BCM53400_A0r_fields,
  39164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39165         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39166         159,
  39167         -1,
  39168         3,
  39169     },
  39170 #endif /* chips */
  39171 
  39172 #if defined(BCM_53570_A0)
  39173     { /* SOC_REG_INT_XLMIB_TPFCOFF4_BCM53570_A0r */
  39174         soc_block_list[16],
  39175         soc_portreg,
  39176         1,
  39177         0,
  39178         0x7d00,
  39179         SOC_REG_FLAG_64_BITS |
  39180                           SOC_REG_FLAG_COUNTER,
  39181         0,
  39182         1,
  39183         soc_R1023_BCM53400_A0r_fields,
  39184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39185         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39186         279,
  39187         -1,
  39188     },
  39189 #endif /* chips */
  39190 
  39191 #if defined(BCM_53570_B0)
  39192     { /* SOC_REG_INT_XLMIB_TPFCOFF4_BCM53570_B0r */
  39193         soc_block_list[16],
  39194         soc_portreg,
  39195         1,
  39196         0,
  39197         0x7d00,
  39198         SOC_REG_FLAG_64_BITS |
  39199                           SOC_REG_FLAG_COUNTER,
  39200         0,
  39201         1,
  39202         soc_R1023_BCM53400_A0r_fields,
  39203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39204         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39205         283,
  39206         -1,
  39207     },
  39208 #endif /* chips */
  39209 
  39210 #if defined(BCM_56370_A0)
  39211     { /* SOC_REG_INT_XLMIB_TPFCOFF4_BCM56370_A0r */
  39212         soc_block_list[16],
  39213         soc_portreg,
  39214         1,
  39215         0,
  39216         0x7d00,
  39217         SOC_REG_FLAG_64_BITS |
  39218                           SOC_REG_FLAG_COUNTER,
  39219         0,
  39220         1,
  39221         soc_R1023_BCM53400_A0r_fields,
  39222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39223         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39224         185,
  39225         -1,
  39226         3,
  39227     },
  39228 #endif /* chips */
  39229 
  39230 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  39231     { /* SOC_REG_INT_XLMIB_TPFCOFF4_BCM56870_A0r */
  39232         soc_block_list[16],
  39233         soc_portreg,
  39234         1,
  39235         0,
  39236         0x7d00,
  39237         SOC_REG_FLAG_64_BITS |
  39238                           SOC_REG_FLAG_COUNTER,
  39239         0,
  39240         1,
  39241         soc_R1023_BCM53400_A0r_fields,
  39242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39243         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39244         184,
  39245         -1,
  39246         3,
  39247     },
  39248 #endif /* chips */
  39249 
  39250 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  39251     { /* SOC_REG_INT_XLMIB_TPFCOFF4_BCM56980_A0r */
  39252         soc_block_list[16],
  39253         soc_portreg,
  39254         1,
  39255         0,
  39256         0x7d00,
  39257         SOC_REG_FLAG_64_BITS |
  39258                           SOC_REG_FLAG_COUNTER,
  39259         0,
  39260         1,
  39261         soc_R1023_BCM53400_A0r_fields,
  39262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39264         160,
  39265         -1,
  39266         3,
  39267     },
  39268 #endif /* chips */
  39269 
  39270 #if defined(BCM_53570_A0)
  39271     { /* SOC_REG_INT_XLMIB_TPFCOFF5_BCM53570_A0r */
  39272         soc_block_list[16],
  39273         soc_portreg,
  39274         1,
  39275         0,
  39276         0x7e00,
  39277         SOC_REG_FLAG_64_BITS |
  39278                           SOC_REG_FLAG_COUNTER,
  39279         0,
  39280         1,
  39281         soc_R1023_BCM53400_A0r_fields,
  39282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39283         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39284         280,
  39285         -1,
  39286     },
  39287 #endif /* chips */
  39288 
  39289 #if defined(BCM_53570_B0)
  39290     { /* SOC_REG_INT_XLMIB_TPFCOFF5_BCM53570_B0r */
  39291         soc_block_list[16],
  39292         soc_portreg,
  39293         1,
  39294         0,
  39295         0x7e00,
  39296         SOC_REG_FLAG_64_BITS |
  39297                           SOC_REG_FLAG_COUNTER,
  39298         0,
  39299         1,
  39300         soc_R1023_BCM53400_A0r_fields,
  39301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39302         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39303         284,
  39304         -1,
  39305     },
  39306 #endif /* chips */
  39307 
  39308 #if defined(BCM_56370_A0)
  39309     { /* SOC_REG_INT_XLMIB_TPFCOFF5_BCM56370_A0r */
  39310         soc_block_list[16],
  39311         soc_portreg,
  39312         1,
  39313         0,
  39314         0x7e00,
  39315         SOC_REG_FLAG_64_BITS |
  39316                           SOC_REG_FLAG_COUNTER,
  39317         0,
  39318         1,
  39319         soc_R1023_BCM53400_A0r_fields,
  39320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39321         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39322         186,
  39323         -1,
  39324         3,
  39325     },
  39326 #endif /* chips */
  39327 
  39328 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  39329     { /* SOC_REG_INT_XLMIB_TPFCOFF5_BCM56870_A0r */
  39330         soc_block_list[16],
  39331         soc_portreg,
  39332         1,
  39333         0,
  39334         0x7e00,
  39335         SOC_REG_FLAG_64_BITS |
  39336                           SOC_REG_FLAG_COUNTER,
  39337         0,
  39338         1,
  39339         soc_R1023_BCM53400_A0r_fields,
  39340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39341         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39342         185,
  39343         -1,
  39344         3,
  39345     },
  39346 #endif /* chips */
  39347 
  39348 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  39349     { /* SOC_REG_INT_XLMIB_TPFCOFF5_BCM56980_A0r */
  39350         soc_block_list[16],
  39351         soc_portreg,
  39352         1,
  39353         0,
  39354         0x7e00,
  39355         SOC_REG_FLAG_64_BITS |
  39356                           SOC_REG_FLAG_COUNTER,
  39357         0,
  39358         1,
  39359         soc_R1023_BCM53400_A0r_fields,
  39360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39361         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39362         161,
  39363         -1,
  39364         3,
  39365     },
  39366 #endif /* chips */
  39367 
  39368 #if defined(BCM_53570_A0)
  39369     { /* SOC_REG_INT_XLMIB_TPFCOFF6_BCM53570_A0r */
  39370         soc_block_list[16],
  39371         soc_portreg,
  39372         1,
  39373         0,
  39374         0x7f00,
  39375         SOC_REG_FLAG_64_BITS |
  39376                           SOC_REG_FLAG_COUNTER,
  39377         0,
  39378         1,
  39379         soc_R1023_BCM53400_A0r_fields,
  39380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39381         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39382         281,
  39383         -1,
  39384     },
  39385 #endif /* chips */
  39386 
  39387 #if defined(BCM_53570_B0)
  39388     { /* SOC_REG_INT_XLMIB_TPFCOFF6_BCM53570_B0r */
  39389         soc_block_list[16],
  39390         soc_portreg,
  39391         1,
  39392         0,
  39393         0x7f00,
  39394         SOC_REG_FLAG_64_BITS |
  39395                           SOC_REG_FLAG_COUNTER,
  39396         0,
  39397         1,
  39398         soc_R1023_BCM53400_A0r_fields,
  39399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39400         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39401         285,
  39402         -1,
  39403     },
  39404 #endif /* chips */
  39405 
  39406 #if defined(BCM_56370_A0)
  39407     { /* SOC_REG_INT_XLMIB_TPFCOFF6_BCM56370_A0r */
  39408         soc_block_list[16],
  39409         soc_portreg,
  39410         1,
  39411         0,
  39412         0x7f00,
  39413         SOC_REG_FLAG_64_BITS |
  39414                           SOC_REG_FLAG_COUNTER,
  39415         0,
  39416         1,
  39417         soc_R1023_BCM53400_A0r_fields,
  39418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39419         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39420         187,
  39421         -1,
  39422         3,
  39423     },
  39424 #endif /* chips */
  39425 
  39426 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  39427     { /* SOC_REG_INT_XLMIB_TPFCOFF6_BCM56870_A0r */
  39428         soc_block_list[16],
  39429         soc_portreg,
  39430         1,
  39431         0,
  39432         0x7f00,
  39433         SOC_REG_FLAG_64_BITS |
  39434                           SOC_REG_FLAG_COUNTER,
  39435         0,
  39436         1,
  39437         soc_R1023_BCM53400_A0r_fields,
  39438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39439         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39440         186,
  39441         -1,
  39442         3,
  39443     },
  39444 #endif /* chips */
  39445 
  39446 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  39447     { /* SOC_REG_INT_XLMIB_TPFCOFF6_BCM56980_A0r */
  39448         soc_block_list[16],
  39449         soc_portreg,
  39450         1,
  39451         0,
  39452         0x7f00,
  39453         SOC_REG_FLAG_64_BITS |
  39454                           SOC_REG_FLAG_COUNTER,
  39455         0,
  39456         1,
  39457         soc_R1023_BCM53400_A0r_fields,
  39458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39459         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39460         162,
  39461         -1,
  39462         3,
  39463     },
  39464 #endif /* chips */
  39465 
  39466 #if defined(BCM_53570_A0)
  39467     { /* SOC_REG_INT_XLMIB_TPFCOFF7_BCM53570_A0r */
  39468         soc_block_list[16],
  39469         soc_portreg,
  39470         1,
  39471         0,
  39472         0x8000,
  39473         SOC_REG_FLAG_64_BITS |
  39474                           SOC_REG_FLAG_COUNTER,
  39475         0,
  39476         1,
  39477         soc_R1023_BCM53400_A0r_fields,
  39478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39479         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39480         282,
  39481         -1,
  39482     },
  39483 #endif /* chips */
  39484 
  39485 #if defined(BCM_53570_B0)
  39486     { /* SOC_REG_INT_XLMIB_TPFCOFF7_BCM53570_B0r */
  39487         soc_block_list[16],
  39488         soc_portreg,
  39489         1,
  39490         0,
  39491         0x8000,
  39492         SOC_REG_FLAG_64_BITS |
  39493                           SOC_REG_FLAG_COUNTER,
  39494         0,
  39495         1,
  39496         soc_R1023_BCM53400_A0r_fields,
  39497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39498         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39499         286,
  39500         -1,
  39501     },
  39502 #endif /* chips */
  39503 
  39504 #if defined(BCM_56370_A0)
  39505     { /* SOC_REG_INT_XLMIB_TPFCOFF7_BCM56370_A0r */
  39506         soc_block_list[16],
  39507         soc_portreg,
  39508         1,
  39509         0,
  39510         0x8000,
  39511         SOC_REG_FLAG_64_BITS |
  39512                           SOC_REG_FLAG_COUNTER,
  39513         0,
  39514         1,
  39515         soc_R1023_BCM53400_A0r_fields,
  39516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39517         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39518         188,
  39519         -1,
  39520         3,
  39521     },
  39522 #endif /* chips */
  39523 
  39524 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  39525     { /* SOC_REG_INT_XLMIB_TPFCOFF7_BCM56870_A0r */
  39526         soc_block_list[16],
  39527         soc_portreg,
  39528         1,
  39529         0,
  39530         0x8000,
  39531         SOC_REG_FLAG_64_BITS |
  39532                           SOC_REG_FLAG_COUNTER,
  39533         0,
  39534         1,
  39535         soc_R1023_BCM53400_A0r_fields,
  39536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39537         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39538         187,
  39539         -1,
  39540         3,
  39541     },
  39542 #endif /* chips */
  39543 
  39544 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  39545     { /* SOC_REG_INT_XLMIB_TPFCOFF7_BCM56980_A0r */
  39546         soc_block_list[16],
  39547         soc_portreg,
  39548         1,
  39549         0,
  39550         0x8000,
  39551         SOC_REG_FLAG_64_BITS |
  39552                           SOC_REG_FLAG_COUNTER,
  39553         0,
  39554         1,
  39555         soc_R1023_BCM53400_A0r_fields,
  39556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39558         163,
  39559         -1,
  39560         3,
  39561     },
  39562 #endif /* chips */
  39563 
  39564 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  39565     { /* SOC_REG_INT_XLMIB_TPKTr */
  39566         soc_block_list[16],
  39567         soc_portreg,
  39568         1,
  39569         0,
  39570         0x4c00,
  39571         SOC_REG_FLAG_64_BITS |
  39572                           SOC_REG_FLAG_COUNTER,
  39573         0,
  39574         1,
  39575         soc_R1023_BCM53400_A0r_fields,
  39576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39577         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39578         135,
  39579         -1,
  39580         3,
  39581     },
  39582 #endif /* chips */
  39583 
  39584 #if defined(BCM_53570_A0)
  39585     { /* SOC_REG_INT_XLMIB_TPKT_BCM53570_A0r */
  39586         soc_block_list[16],
  39587         soc_portreg,
  39588         1,
  39589         0,
  39590         0x4c00,
  39591         SOC_REG_FLAG_64_BITS |
  39592                           SOC_REG_FLAG_COUNTER,
  39593         0,
  39594         1,
  39595         soc_R1023_BCM53400_A0r_fields,
  39596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39598         230,
  39599         -1,
  39600     },
  39601 #endif /* chips */
  39602 
  39603 #if defined(BCM_53570_B0)
  39604     { /* SOC_REG_INT_XLMIB_TPKT_BCM53570_B0r */
  39605         soc_block_list[16],
  39606         soc_portreg,
  39607         1,
  39608         0,
  39609         0x4c00,
  39610         SOC_REG_FLAG_64_BITS |
  39611                           SOC_REG_FLAG_COUNTER,
  39612         0,
  39613         1,
  39614         soc_R1023_BCM53400_A0r_fields,
  39615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39616         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39617         234,
  39618         -1,
  39619     },
  39620 #endif /* chips */
  39621 
  39622 #if defined(BCM_56370_A0)
  39623     { /* SOC_REG_INT_XLMIB_TPKT_BCM56370_A0r */
  39624         soc_block_list[16],
  39625         soc_portreg,
  39626         1,
  39627         0,
  39628         0x4c00,
  39629         SOC_REG_FLAG_64_BITS |
  39630                           SOC_REG_FLAG_COUNTER,
  39631         0,
  39632         1,
  39633         soc_R1023_BCM53400_A0r_fields,
  39634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39635         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39636         136,
  39637         -1,
  39638         3,
  39639     },
  39640 #endif /* chips */
  39641 
  39642 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  39643     { /* SOC_REG_INT_XLMIB_TPKT_BCM56980_A0r */
  39644         soc_block_list[16],
  39645         soc_portreg,
  39646         1,
  39647         0,
  39648         0x4c00,
  39649         SOC_REG_FLAG_64_BITS |
  39650                           SOC_REG_FLAG_COUNTER,
  39651         0,
  39652         1,
  39653         soc_R1023_BCM53400_A0r_fields,
  39654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39655         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39656         111,
  39657         -1,
  39658         3,
  39659     },
  39660 #endif /* chips */
  39661 
  39662 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  39663     { /* SOC_REG_INT_XLMIB_TPOKr */
  39664         soc_block_list[16],
  39665         soc_portreg,
  39666         1,
  39667         0,
  39668         0x4b00,
  39669         SOC_REG_FLAG_64_BITS |
  39670                           SOC_REG_FLAG_COUNTER,
  39671         0,
  39672         1,
  39673         soc_R1023_BCM53400_A0r_fields,
  39674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39675         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39676         134,
  39677         -1,
  39678         3,
  39679     },
  39680 #endif /* chips */
  39681 
  39682 #if defined(BCM_53570_A0)
  39683     { /* SOC_REG_INT_XLMIB_TPOK_BCM53570_A0r */
  39684         soc_block_list[16],
  39685         soc_portreg,
  39686         1,
  39687         0,
  39688         0x4b00,
  39689         SOC_REG_FLAG_64_BITS |
  39690                           SOC_REG_FLAG_COUNTER,
  39691         0,
  39692         1,
  39693         soc_R1023_BCM53400_A0r_fields,
  39694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39695         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39696         229,
  39697         -1,
  39698     },
  39699 #endif /* chips */
  39700 
  39701 #if defined(BCM_53570_B0)
  39702     { /* SOC_REG_INT_XLMIB_TPOK_BCM53570_B0r */
  39703         soc_block_list[16],
  39704         soc_portreg,
  39705         1,
  39706         0,
  39707         0x4b00,
  39708         SOC_REG_FLAG_64_BITS |
  39709                           SOC_REG_FLAG_COUNTER,
  39710         0,
  39711         1,
  39712         soc_R1023_BCM53400_A0r_fields,
  39713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39714         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39715         233,
  39716         -1,
  39717     },
  39718 #endif /* chips */
  39719 
  39720 #if defined(BCM_56370_A0)
  39721     { /* SOC_REG_INT_XLMIB_TPOK_BCM56370_A0r */
  39722         soc_block_list[16],
  39723         soc_portreg,
  39724         1,
  39725         0,
  39726         0x4b00,
  39727         SOC_REG_FLAG_64_BITS |
  39728                           SOC_REG_FLAG_COUNTER,
  39729         0,
  39730         1,
  39731         soc_R1023_BCM53400_A0r_fields,
  39732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39733         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39734         135,
  39735         -1,
  39736         3,
  39737     },
  39738 #endif /* chips */
  39739 
  39740 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  39741     { /* SOC_REG_INT_XLMIB_TPOK_BCM56980_A0r */
  39742         soc_block_list[16],
  39743         soc_portreg,
  39744         1,
  39745         0,
  39746         0x4b00,
  39747         SOC_REG_FLAG_64_BITS |
  39748                           SOC_REG_FLAG_COUNTER,
  39749         0,
  39750         1,
  39751         soc_R1023_BCM53400_A0r_fields,
  39752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39754         110,
  39755         -1,
  39756         3,
  39757     },
  39758 #endif /* chips */
  39759 
  39760 #if defined(BCM_53570_A0)
  39761     { /* SOC_REG_INT_XLMIB_TREPLYr */
  39762         soc_block_list[16],
  39763         soc_portreg,
  39764         1,
  39765         0,
  39766         0x5700,
  39767         SOC_REG_FLAG_64_BITS |
  39768                           SOC_REG_FLAG_COUNTER |
  39769                           SOC_REG_FLAG_ED_CNTR,
  39770         0,
  39771         1,
  39772         soc_R1023_BCM53400_A0r_fields,
  39773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39774         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39775         241,
  39776         -1,
  39777     },
  39778 #endif /* chips */
  39779 
  39780 #if defined(BCM_53570_B0)
  39781     { /* SOC_REG_INT_XLMIB_TREPLY_BCM53570_B0r */
  39782         soc_block_list[16],
  39783         soc_portreg,
  39784         1,
  39785         0,
  39786         0x5700,
  39787         SOC_REG_FLAG_64_BITS |
  39788                           SOC_REG_FLAG_COUNTER |
  39789                           SOC_REG_FLAG_ED_CNTR,
  39790         0,
  39791         1,
  39792         soc_R1023_BCM53400_A0r_fields,
  39793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39794         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39795         245,
  39796         -1,
  39797     },
  39798 #endif /* chips */
  39799 
  39800 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  39801     { /* SOC_REG_INT_XLMIB_TRPKTr */
  39802         soc_block_list[16],
  39803         soc_portreg,
  39804         1,
  39805         0,
  39806         0x6000,
  39807         SOC_REG_FLAG_64_BITS |
  39808                           SOC_REG_FLAG_COUNTER |
  39809                           SOC_REG_FLAG_ED_CNTR,
  39810         0,
  39811         1,
  39812         soc_R1023_BCM53400_A0r_fields,
  39813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39814         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39815         155,
  39816         -1,
  39817         3,
  39818     },
  39819 #endif /* chips */
  39820 
  39821 #if defined(BCM_53570_A0)
  39822     { /* SOC_REG_INT_XLMIB_TRPKT_BCM53570_A0r */
  39823         soc_block_list[16],
  39824         soc_portreg,
  39825         1,
  39826         0,
  39827         0x6000,
  39828         SOC_REG_FLAG_64_BITS |
  39829                           SOC_REG_FLAG_COUNTER |
  39830                           SOC_REG_FLAG_ED_CNTR,
  39831         0,
  39832         1,
  39833         soc_R1023_BCM53400_A0r_fields,
  39834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39835         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39836         250,
  39837         -1,
  39838     },
  39839 #endif /* chips */
  39840 
  39841 #if defined(BCM_53570_B0)
  39842     { /* SOC_REG_INT_XLMIB_TRPKT_BCM53570_B0r */
  39843         soc_block_list[16],
  39844         soc_portreg,
  39845         1,
  39846         0,
  39847         0x6000,
  39848         SOC_REG_FLAG_64_BITS |
  39849                           SOC_REG_FLAG_COUNTER |
  39850                           SOC_REG_FLAG_ED_CNTR,
  39851         0,
  39852         1,
  39853         soc_R1023_BCM53400_A0r_fields,
  39854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39855         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39856         254,
  39857         -1,
  39858     },
  39859 #endif /* chips */
  39860 
  39861 #if defined(BCM_56370_A0)
  39862     { /* SOC_REG_INT_XLMIB_TRPKT_BCM56370_A0r */
  39863         soc_block_list[16],
  39864         soc_portreg,
  39865         1,
  39866         0,
  39867         0x6000,
  39868         SOC_REG_FLAG_64_BITS |
  39869                           SOC_REG_FLAG_COUNTER |
  39870                           SOC_REG_FLAG_ED_CNTR,
  39871         0,
  39872         1,
  39873         soc_R1023_BCM53400_A0r_fields,
  39874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39875         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39876         156,
  39877         -1,
  39878         3,
  39879     },
  39880 #endif /* chips */
  39881 
  39882 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  39883     { /* SOC_REG_INT_XLMIB_TRPKT_BCM56980_A0r */
  39884         soc_block_list[16],
  39885         soc_portreg,
  39886         1,
  39887         0,
  39888         0x6000,
  39889         SOC_REG_FLAG_64_BITS |
  39890                           SOC_REG_FLAG_COUNTER |
  39891                           SOC_REG_FLAG_ED_CNTR,
  39892         0,
  39893         1,
  39894         soc_R1023_BCM53400_A0r_fields,
  39895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39896         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39897         131,
  39898         -1,
  39899         3,
  39900     },
  39901 #endif /* chips */
  39902 
  39903 #if defined(BCM_56970_A0)
  39904     { /* SOC_REG_INT_XLMIB_TSCLr */
  39905         soc_block_list[16],
  39906         soc_portreg,
  39907         1,
  39908         0,
  39909         0x5800,
  39910         SOC_REG_FLAG_64_BITS |
  39911                           SOC_REG_FLAG_COUNTER |
  39912                           SOC_REG_FLAG_ED_CNTR,
  39913         0,
  39914         1,
  39915         soc_RALN_BCM53400_A0r_fields,
  39916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39918         143,
  39919         -1,
  39920         3,
  39921     },
  39922 #endif /* chips */
  39923 
  39924 #if defined(BCM_53570_A0)
  39925     { /* SOC_REG_INT_XLMIB_TSCL_BCM53570_A0r */
  39926         soc_block_list[16],
  39927         soc_portreg,
  39928         1,
  39929         0,
  39930         0x5800,
  39931         SOC_REG_FLAG_64_BITS |
  39932                           SOC_REG_FLAG_COUNTER |
  39933                           SOC_REG_FLAG_ED_CNTR,
  39934         0,
  39935         1,
  39936         soc_XLMIB_RSCHCRCr_fields,
  39937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39938         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39939         242,
  39940         -1,
  39941     },
  39942 #endif /* chips */
  39943 
  39944 #if defined(BCM_53570_B0)
  39945     { /* SOC_REG_INT_XLMIB_TSCL_BCM53570_B0r */
  39946         soc_block_list[16],
  39947         soc_portreg,
  39948         1,
  39949         0,
  39950         0x5800,
  39951         SOC_REG_FLAG_64_BITS |
  39952                           SOC_REG_FLAG_COUNTER |
  39953                           SOC_REG_FLAG_ED_CNTR,
  39954         0,
  39955         1,
  39956         soc_XLMIB_RSCHCRCr_fields,
  39957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39958         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39959         246,
  39960         -1,
  39961     },
  39962 #endif /* chips */
  39963 
  39964 #if defined(BCM_56370_A0)
  39965     { /* SOC_REG_INT_XLMIB_TSCL_BCM56370_A0r */
  39966         soc_block_list[16],
  39967         soc_portreg,
  39968         1,
  39969         0,
  39970         0x5800,
  39971         SOC_REG_FLAG_64_BITS |
  39972                           SOC_REG_FLAG_COUNTER |
  39973                           SOC_REG_FLAG_ED_CNTR,
  39974         0,
  39975         1,
  39976         soc_RALN_BCM53400_A0r_fields,
  39977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39978         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  39979         148,
  39980         -1,
  39981         3,
  39982     },
  39983 #endif /* chips */
  39984 
  39985 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  39986     { /* SOC_REG_INT_XLMIB_TSCL_BCM56870_A0r */
  39987         soc_block_list[16],
  39988         soc_portreg,
  39989         1,
  39990         0,
  39991         0x5800,
  39992         SOC_REG_FLAG_64_BITS |
  39993                           SOC_REG_FLAG_COUNTER |
  39994                           SOC_REG_FLAG_ED_CNTR,
  39995         0,
  39996         1,
  39997         soc_RALN_BCM53400_A0r_fields,
  39998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39999         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40000         147,
  40001         -1,
  40002         3,
  40003     },
  40004 #endif /* chips */
  40005 
  40006 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  40007     { /* SOC_REG_INT_XLMIB_TSCL_BCM56980_A0r */
  40008         soc_block_list[16],
  40009         soc_portreg,
  40010         1,
  40011         0,
  40012         0x5800,
  40013         SOC_REG_FLAG_64_BITS |
  40014                           SOC_REG_FLAG_COUNTER |
  40015                           SOC_REG_FLAG_ED_CNTR,
  40016         0,
  40017         1,
  40018         soc_RALN_BCM53400_A0r_fields,
  40019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40020         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40021         123,
  40022         -1,
  40023         3,
  40024     },
  40025 #endif /* chips */
  40026 
  40027 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  40028     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  40029     defined(BCM_56980_B0)
  40030     { /* SOC_REG_INT_XLMIB_TSPARE0r */
  40031         soc_block_list[16],
  40032         soc_portreg,
  40033         1,
  40034         0,
  40035         0x7100,
  40036         SOC_REG_FLAG_64_BITS,
  40037         0,
  40038         1,
  40039         soc_TSPARE0r_fields,
  40040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40041         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40042         -1,
  40043         -1,
  40044         3,
  40045     },
  40046 #endif /* chips */
  40047 
  40048 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  40049     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  40050     defined(BCM_56980_B0)
  40051     { /* SOC_REG_INT_XLMIB_TSPARE1r */
  40052         soc_block_list[16],
  40053         soc_portreg,
  40054         1,
  40055         0,
  40056         0x7200,
  40057         SOC_REG_FLAG_64_BITS,
  40058         0,
  40059         1,
  40060         soc_TSPARE0r_fields,
  40061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40062         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40063         -1,
  40064         -1,
  40065         3,
  40066     },
  40067 #endif /* chips */
  40068 
  40069 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  40070     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  40071     defined(BCM_56980_B0)
  40072     { /* SOC_REG_INT_XLMIB_TSPARE2r */
  40073         soc_block_list[16],
  40074         soc_portreg,
  40075         1,
  40076         0,
  40077         0x7300,
  40078         SOC_REG_FLAG_64_BITS,
  40079         0,
  40080         1,
  40081         soc_TSPARE0r_fields,
  40082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40083         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40084         -1,
  40085         -1,
  40086         3,
  40087     },
  40088 #endif /* chips */
  40089 
  40090 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  40091     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  40092     defined(BCM_56980_B0)
  40093     { /* SOC_REG_INT_XLMIB_TSPARE3r */
  40094         soc_block_list[16],
  40095         soc_portreg,
  40096         1,
  40097         0,
  40098         0x7400,
  40099         SOC_REG_FLAG_64_BITS,
  40100         0,
  40101         1,
  40102         soc_TSPARE0r_fields,
  40103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40105         -1,
  40106         -1,
  40107         3,
  40108     },
  40109 #endif /* chips */
  40110 
  40111 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  40112     { /* SOC_REG_INT_XLMIB_TSPARE0_BCM53570_A0r */
  40113         soc_block_list[16],
  40114         soc_portreg,
  40115         1,
  40116         0,
  40117         0x7100,
  40118         SOC_REG_FLAG_64_BITS,
  40119         0,
  40120         1,
  40121         soc_TSPARE0r_fields,
  40122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40124         -1,
  40125         -1,
  40126     },
  40127 #endif /* chips */
  40128 
  40129 #if defined(BCM_56370_A0)
  40130     { /* SOC_REG_INT_XLMIB_TSPARE0_BCM56370_A0r */
  40131         soc_block_list[16],
  40132         soc_portreg,
  40133         1,
  40134         0,
  40135         0x7100,
  40136         SOC_REG_FLAG_64_BITS,
  40137         0,
  40138         1,
  40139         soc_TSPARE0r_fields,
  40140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40141         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40142         -1,
  40143         -1,
  40144         3,
  40145     },
  40146 #endif /* chips */
  40147 
  40148 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  40149     { /* SOC_REG_INT_XLMIB_TSPARE1_BCM53570_A0r */
  40150         soc_block_list[16],
  40151         soc_portreg,
  40152         1,
  40153         0,
  40154         0x7200,
  40155         SOC_REG_FLAG_64_BITS,
  40156         0,
  40157         1,
  40158         soc_TSPARE0r_fields,
  40159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40160         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40161         -1,
  40162         -1,
  40163     },
  40164 #endif /* chips */
  40165 
  40166 #if defined(BCM_56370_A0)
  40167     { /* SOC_REG_INT_XLMIB_TSPARE1_BCM56370_A0r */
  40168         soc_block_list[16],
  40169         soc_portreg,
  40170         1,
  40171         0,
  40172         0x7200,
  40173         SOC_REG_FLAG_64_BITS,
  40174         0,
  40175         1,
  40176         soc_TSPARE0r_fields,
  40177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40178         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40179         -1,
  40180         -1,
  40181         3,
  40182     },
  40183 #endif /* chips */
  40184 
  40185 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  40186     { /* SOC_REG_INT_XLMIB_TSPARE2_BCM53570_A0r */
  40187         soc_block_list[16],
  40188         soc_portreg,
  40189         1,
  40190         0,
  40191         0x7300,
  40192         SOC_REG_FLAG_64_BITS,
  40193         0,
  40194         1,
  40195         soc_TSPARE0r_fields,
  40196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40197         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40198         -1,
  40199         -1,
  40200     },
  40201 #endif /* chips */
  40202 
  40203 #if defined(BCM_56370_A0)
  40204     { /* SOC_REG_INT_XLMIB_TSPARE2_BCM56370_A0r */
  40205         soc_block_list[16],
  40206         soc_portreg,
  40207         1,
  40208         0,
  40209         0x7300,
  40210         SOC_REG_FLAG_64_BITS,
  40211         0,
  40212         1,
  40213         soc_TSPARE0r_fields,
  40214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40215         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40216         -1,
  40217         -1,
  40218         3,
  40219     },
  40220 #endif /* chips */
  40221 
  40222 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  40223     { /* SOC_REG_INT_XLMIB_TSPARE3_BCM53570_A0r */
  40224         soc_block_list[16],
  40225         soc_portreg,
  40226         1,
  40227         0,
  40228         0x7400,
  40229         SOC_REG_FLAG_64_BITS,
  40230         0,
  40231         1,
  40232         soc_TSPARE0r_fields,
  40233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40234         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40235         -1,
  40236         -1,
  40237     },
  40238 #endif /* chips */
  40239 
  40240 #if defined(BCM_56370_A0)
  40241     { /* SOC_REG_INT_XLMIB_TSPARE3_BCM56370_A0r */
  40242         soc_block_list[16],
  40243         soc_portreg,
  40244         1,
  40245         0,
  40246         0x7400,
  40247         SOC_REG_FLAG_64_BITS,
  40248         0,
  40249         1,
  40250         soc_TSPARE0r_fields,
  40251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40252         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40253         -1,
  40254         -1,
  40255         3,
  40256     },
  40257 #endif /* chips */
  40258 
  40259 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  40260     { /* SOC_REG_INT_XLMIB_TUCAr */
  40261         soc_block_list[16],
  40262         soc_portreg,
  40263         1,
  40264         0,
  40265         0x4d00,
  40266         SOC_REG_FLAG_64_BITS |
  40267                           SOC_REG_FLAG_COUNTER,
  40268         0,
  40269         1,
  40270         soc_R1023_BCM53400_A0r_fields,
  40271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40272         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40273         136,
  40274         -1,
  40275         3,
  40276     },
  40277 #endif /* chips */
  40278 
  40279 #if defined(BCM_53570_A0)
  40280     { /* SOC_REG_INT_XLMIB_TUCA_BCM53570_A0r */
  40281         soc_block_list[16],
  40282         soc_portreg,
  40283         1,
  40284         0,
  40285         0x4d00,
  40286         SOC_REG_FLAG_64_BITS |
  40287                           SOC_REG_FLAG_COUNTER,
  40288         0,
  40289         1,
  40290         soc_R1023_BCM53400_A0r_fields,
  40291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40292         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40293         231,
  40294         -1,
  40295     },
  40296 #endif /* chips */
  40297 
  40298 #if defined(BCM_53570_B0)
  40299     { /* SOC_REG_INT_XLMIB_TUCA_BCM53570_B0r */
  40300         soc_block_list[16],
  40301         soc_portreg,
  40302         1,
  40303         0,
  40304         0x4d00,
  40305         SOC_REG_FLAG_64_BITS |
  40306                           SOC_REG_FLAG_COUNTER,
  40307         0,
  40308         1,
  40309         soc_R1023_BCM53400_A0r_fields,
  40310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40311         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40312         235,
  40313         -1,
  40314     },
  40315 #endif /* chips */
  40316 
  40317 #if defined(BCM_56370_A0)
  40318     { /* SOC_REG_INT_XLMIB_TUCA_BCM56370_A0r */
  40319         soc_block_list[16],
  40320         soc_portreg,
  40321         1,
  40322         0,
  40323         0x4d00,
  40324         SOC_REG_FLAG_64_BITS |
  40325                           SOC_REG_FLAG_COUNTER,
  40326         0,
  40327         1,
  40328         soc_R1023_BCM53400_A0r_fields,
  40329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40330         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40331         137,
  40332         -1,
  40333         3,
  40334     },
  40335 #endif /* chips */
  40336 
  40337 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  40338     { /* SOC_REG_INT_XLMIB_TUCA_BCM56980_A0r */
  40339         soc_block_list[16],
  40340         soc_portreg,
  40341         1,
  40342         0,
  40343         0x4d00,
  40344         SOC_REG_FLAG_64_BITS |
  40345                           SOC_REG_FLAG_COUNTER,
  40346         0,
  40347         1,
  40348         soc_R1023_BCM53400_A0r_fields,
  40349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40350         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40351         112,
  40352         -1,
  40353         3,
  40354     },
  40355 #endif /* chips */
  40356 
  40357 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  40358     { /* SOC_REG_INT_XLMIB_TUFLr */
  40359         soc_block_list[16],
  40360         soc_portreg,
  40361         1,
  40362         0,
  40363         0x6100,
  40364         SOC_REG_FLAG_64_BITS |
  40365                           SOC_REG_FLAG_COUNTER |
  40366                           SOC_REG_FLAG_ED_CNTR,
  40367         0,
  40368         1,
  40369         soc_R1023_BCM53400_A0r_fields,
  40370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40372         156,
  40373         -1,
  40374         3,
  40375     },
  40376 #endif /* chips */
  40377 
  40378 #if defined(BCM_53570_A0)
  40379     { /* SOC_REG_INT_XLMIB_TUFL_BCM53570_A0r */
  40380         soc_block_list[16],
  40381         soc_portreg,
  40382         1,
  40383         0,
  40384         0x6100,
  40385         SOC_REG_FLAG_64_BITS |
  40386                           SOC_REG_FLAG_COUNTER |
  40387                           SOC_REG_FLAG_ED_CNTR,
  40388         0,
  40389         1,
  40390         soc_R1023_BCM53400_A0r_fields,
  40391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40392         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40393         251,
  40394         -1,
  40395     },
  40396 #endif /* chips */
  40397 
  40398 #if defined(BCM_53570_B0)
  40399     { /* SOC_REG_INT_XLMIB_TUFL_BCM53570_B0r */
  40400         soc_block_list[16],
  40401         soc_portreg,
  40402         1,
  40403         0,
  40404         0x6100,
  40405         SOC_REG_FLAG_64_BITS |
  40406                           SOC_REG_FLAG_COUNTER |
  40407                           SOC_REG_FLAG_ED_CNTR,
  40408         0,
  40409         1,
  40410         soc_R1023_BCM53400_A0r_fields,
  40411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40412         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40413         255,
  40414         -1,
  40415     },
  40416 #endif /* chips */
  40417 
  40418 #if defined(BCM_56370_A0)
  40419     { /* SOC_REG_INT_XLMIB_TUFL_BCM56370_A0r */
  40420         soc_block_list[16],
  40421         soc_portreg,
  40422         1,
  40423         0,
  40424         0x6100,
  40425         SOC_REG_FLAG_64_BITS |
  40426                           SOC_REG_FLAG_COUNTER |
  40427                           SOC_REG_FLAG_ED_CNTR,
  40428         0,
  40429         1,
  40430         soc_R1023_BCM53400_A0r_fields,
  40431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40433         157,
  40434         -1,
  40435         3,
  40436     },
  40437 #endif /* chips */
  40438 
  40439 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  40440     { /* SOC_REG_INT_XLMIB_TUFL_BCM56980_A0r */
  40441         soc_block_list[16],
  40442         soc_portreg,
  40443         1,
  40444         0,
  40445         0x6100,
  40446         SOC_REG_FLAG_64_BITS |
  40447                           SOC_REG_FLAG_COUNTER |
  40448                           SOC_REG_FLAG_ED_CNTR,
  40449         0,
  40450         1,
  40451         soc_R1023_BCM53400_A0r_fields,
  40452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40453         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40454         132,
  40455         -1,
  40456         3,
  40457     },
  40458 #endif /* chips */
  40459 
  40460 #if defined(BCM_53570_A0)
  40461     { /* SOC_REG_INT_XLMIB_TVERIFYr */
  40462         soc_block_list[16],
  40463         soc_portreg,
  40464         1,
  40465         0,
  40466         0x5600,
  40467         SOC_REG_FLAG_64_BITS |
  40468                           SOC_REG_FLAG_COUNTER |
  40469                           SOC_REG_FLAG_ED_CNTR,
  40470         0,
  40471         1,
  40472         soc_R1023_BCM53400_A0r_fields,
  40473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40474         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40475         240,
  40476         -1,
  40477     },
  40478 #endif /* chips */
  40479 
  40480 #if defined(BCM_53570_B0)
  40481     { /* SOC_REG_INT_XLMIB_TVERIFY_BCM53570_B0r */
  40482         soc_block_list[16],
  40483         soc_portreg,
  40484         1,
  40485         0,
  40486         0x5600,
  40487         SOC_REG_FLAG_64_BITS |
  40488                           SOC_REG_FLAG_COUNTER |
  40489                           SOC_REG_FLAG_ED_CNTR,
  40490         0,
  40491         1,
  40492         soc_R1023_BCM53400_A0r_fields,
  40493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40494         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40495         244,
  40496         -1,
  40497     },
  40498 #endif /* chips */
  40499 
  40500 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  40501     { /* SOC_REG_INT_XLMIB_TVLNr */
  40502         soc_block_list[16],
  40503         soc_portreg,
  40504         1,
  40505         0,
  40506         0x5e00,
  40507         SOC_REG_FLAG_64_BITS |
  40508                           SOC_REG_FLAG_COUNTER,
  40509         0,
  40510         1,
  40511         soc_R1023_BCM53400_A0r_fields,
  40512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40514         153,
  40515         -1,
  40516         3,
  40517     },
  40518 #endif /* chips */
  40519 
  40520 #if defined(BCM_53570_A0)
  40521     { /* SOC_REG_INT_XLMIB_TVLN_BCM53570_A0r */
  40522         soc_block_list[16],
  40523         soc_portreg,
  40524         1,
  40525         0,
  40526         0x5e00,
  40527         SOC_REG_FLAG_64_BITS |
  40528                           SOC_REG_FLAG_COUNTER,
  40529         0,
  40530         1,
  40531         soc_R1023_BCM53400_A0r_fields,
  40532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40533         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40534         248,
  40535         -1,
  40536     },
  40537 #endif /* chips */
  40538 
  40539 #if defined(BCM_53570_B0)
  40540     { /* SOC_REG_INT_XLMIB_TVLN_BCM53570_B0r */
  40541         soc_block_list[16],
  40542         soc_portreg,
  40543         1,
  40544         0,
  40545         0x5e00,
  40546         SOC_REG_FLAG_64_BITS |
  40547                           SOC_REG_FLAG_COUNTER,
  40548         0,
  40549         1,
  40550         soc_R1023_BCM53400_A0r_fields,
  40551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40552         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40553         252,
  40554         -1,
  40555     },
  40556 #endif /* chips */
  40557 
  40558 #if defined(BCM_56370_A0)
  40559     { /* SOC_REG_INT_XLMIB_TVLN_BCM56370_A0r */
  40560         soc_block_list[16],
  40561         soc_portreg,
  40562         1,
  40563         0,
  40564         0x5e00,
  40565         SOC_REG_FLAG_64_BITS |
  40566                           SOC_REG_FLAG_COUNTER,
  40567         0,
  40568         1,
  40569         soc_R1023_BCM53400_A0r_fields,
  40570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40572         154,
  40573         -1,
  40574         3,
  40575     },
  40576 #endif /* chips */
  40577 
  40578 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  40579     { /* SOC_REG_INT_XLMIB_TVLN_BCM56980_A0r */
  40580         soc_block_list[16],
  40581         soc_portreg,
  40582         1,
  40583         0,
  40584         0x5e00,
  40585         SOC_REG_FLAG_64_BITS |
  40586                           SOC_REG_FLAG_COUNTER,
  40587         0,
  40588         1,
  40589         soc_R1023_BCM53400_A0r_fields,
  40590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40592         129,
  40593         -1,
  40594         3,
  40595     },
  40596 #endif /* chips */
  40597 
  40598 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  40599     { /* SOC_REG_INT_XLMIB_TXCFr */
  40600         soc_block_list[16],
  40601         soc_portreg,
  40602         1,
  40603         0,
  40604         0x5400,
  40605         SOC_REG_FLAG_64_BITS |
  40606                           SOC_REG_FLAG_COUNTER,
  40607         0,
  40608         1,
  40609         soc_R1023_BCM53400_A0r_fields,
  40610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40612         143,
  40613         -1,
  40614         3,
  40615     },
  40616 #endif /* chips */
  40617 
  40618 #if defined(BCM_53570_A0)
  40619     { /* SOC_REG_INT_XLMIB_TXCF_BCM53570_A0r */
  40620         soc_block_list[16],
  40621         soc_portreg,
  40622         1,
  40623         0,
  40624         0x5400,
  40625         SOC_REG_FLAG_64_BITS |
  40626                           SOC_REG_FLAG_COUNTER,
  40627         0,
  40628         1,
  40629         soc_R1023_BCM53400_A0r_fields,
  40630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40632         238,
  40633         -1,
  40634     },
  40635 #endif /* chips */
  40636 
  40637 #if defined(BCM_53570_B0)
  40638     { /* SOC_REG_INT_XLMIB_TXCF_BCM53570_B0r */
  40639         soc_block_list[16],
  40640         soc_portreg,
  40641         1,
  40642         0,
  40643         0x5400,
  40644         SOC_REG_FLAG_64_BITS |
  40645                           SOC_REG_FLAG_COUNTER,
  40646         0,
  40647         1,
  40648         soc_R1023_BCM53400_A0r_fields,
  40649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40650         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40651         242,
  40652         -1,
  40653     },
  40654 #endif /* chips */
  40655 
  40656 #if defined(BCM_56370_A0)
  40657     { /* SOC_REG_INT_XLMIB_TXCF_BCM56370_A0r */
  40658         soc_block_list[16],
  40659         soc_portreg,
  40660         1,
  40661         0,
  40662         0x5400,
  40663         SOC_REG_FLAG_64_BITS |
  40664                           SOC_REG_FLAG_COUNTER,
  40665         0,
  40666         1,
  40667         soc_R1023_BCM53400_A0r_fields,
  40668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40670         144,
  40671         -1,
  40672         3,
  40673     },
  40674 #endif /* chips */
  40675 
  40676 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  40677     { /* SOC_REG_INT_XLMIB_TXCF_BCM56980_A0r */
  40678         soc_block_list[16],
  40679         soc_portreg,
  40680         1,
  40681         0,
  40682         0x5400,
  40683         SOC_REG_FLAG_64_BITS |
  40684                           SOC_REG_FLAG_COUNTER,
  40685         0,
  40686         1,
  40687         soc_R1023_BCM53400_A0r_fields,
  40688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40689         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40690         119,
  40691         -1,
  40692         3,
  40693     },
  40694 #endif /* chips */
  40695 
  40696 #if defined(BCM_56970_A0)
  40697     { /* SOC_REG_INT_XLMIB_TXCLr */
  40698         soc_block_list[16],
  40699         soc_portreg,
  40700         1,
  40701         0,
  40702         0x5b00,
  40703         SOC_REG_FLAG_64_BITS |
  40704                           SOC_REG_FLAG_COUNTER |
  40705                           SOC_REG_FLAG_ED_CNTR,
  40706         0,
  40707         1,
  40708         soc_RALN_BCM53400_A0r_fields,
  40709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40710         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40711         146,
  40712         -1,
  40713         3,
  40714     },
  40715 #endif /* chips */
  40716 
  40717 #if defined(BCM_53570_A0)
  40718     { /* SOC_REG_INT_XLMIB_TXCL_BCM53570_A0r */
  40719         soc_block_list[16],
  40720         soc_portreg,
  40721         1,
  40722         0,
  40723         0x5b00,
  40724         SOC_REG_FLAG_64_BITS |
  40725                           SOC_REG_FLAG_COUNTER |
  40726                           SOC_REG_FLAG_ED_CNTR,
  40727         0,
  40728         1,
  40729         soc_XLMIB_RSCHCRCr_fields,
  40730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40731         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40732         245,
  40733         -1,
  40734     },
  40735 #endif /* chips */
  40736 
  40737 #if defined(BCM_53570_B0)
  40738     { /* SOC_REG_INT_XLMIB_TXCL_BCM53570_B0r */
  40739         soc_block_list[16],
  40740         soc_portreg,
  40741         1,
  40742         0,
  40743         0x5b00,
  40744         SOC_REG_FLAG_64_BITS |
  40745                           SOC_REG_FLAG_COUNTER |
  40746                           SOC_REG_FLAG_ED_CNTR,
  40747         0,
  40748         1,
  40749         soc_XLMIB_RSCHCRCr_fields,
  40750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40751         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40752         249,
  40753         -1,
  40754     },
  40755 #endif /* chips */
  40756 
  40757 #if defined(BCM_56370_A0)
  40758     { /* SOC_REG_INT_XLMIB_TXCL_BCM56370_A0r */
  40759         soc_block_list[16],
  40760         soc_portreg,
  40761         1,
  40762         0,
  40763         0x5b00,
  40764         SOC_REG_FLAG_64_BITS |
  40765                           SOC_REG_FLAG_COUNTER |
  40766                           SOC_REG_FLAG_ED_CNTR,
  40767         0,
  40768         1,
  40769         soc_RALN_BCM53400_A0r_fields,
  40770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40772         151,
  40773         -1,
  40774         3,
  40775     },
  40776 #endif /* chips */
  40777 
  40778 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  40779     { /* SOC_REG_INT_XLMIB_TXCL_BCM56870_A0r */
  40780         soc_block_list[16],
  40781         soc_portreg,
  40782         1,
  40783         0,
  40784         0x5b00,
  40785         SOC_REG_FLAG_64_BITS |
  40786                           SOC_REG_FLAG_COUNTER |
  40787                           SOC_REG_FLAG_ED_CNTR,
  40788         0,
  40789         1,
  40790         soc_RALN_BCM53400_A0r_fields,
  40791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40792         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40793         150,
  40794         -1,
  40795         3,
  40796     },
  40797 #endif /* chips */
  40798 
  40799 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  40800     { /* SOC_REG_INT_XLMIB_TXCL_BCM56980_A0r */
  40801         soc_block_list[16],
  40802         soc_portreg,
  40803         1,
  40804         0,
  40805         0x5b00,
  40806         SOC_REG_FLAG_64_BITS |
  40807                           SOC_REG_FLAG_COUNTER |
  40808                           SOC_REG_FLAG_ED_CNTR,
  40809         0,
  40810         1,
  40811         soc_RALN_BCM53400_A0r_fields,
  40812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40814         126,
  40815         -1,
  40816         3,
  40817     },
  40818 #endif /* chips */
  40819 
  40820 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  40821     { /* SOC_REG_INT_XLMIB_TXPFr */
  40822         soc_block_list[16],
  40823         soc_portreg,
  40824         1,
  40825         0,
  40826         0x5000,
  40827         SOC_REG_FLAG_64_BITS |
  40828                           SOC_REG_FLAG_COUNTER,
  40829         0,
  40830         1,
  40831         soc_R1023_BCM53400_A0r_fields,
  40832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40833         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40834         139,
  40835         -1,
  40836         3,
  40837     },
  40838 #endif /* chips */
  40839 
  40840 #if defined(BCM_53570_A0)
  40841     { /* SOC_REG_INT_XLMIB_TXPF_BCM53570_A0r */
  40842         soc_block_list[16],
  40843         soc_portreg,
  40844         1,
  40845         0,
  40846         0x5000,
  40847         SOC_REG_FLAG_64_BITS |
  40848                           SOC_REG_FLAG_COUNTER,
  40849         0,
  40850         1,
  40851         soc_R1023_BCM53400_A0r_fields,
  40852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40853         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40854         234,
  40855         -1,
  40856     },
  40857 #endif /* chips */
  40858 
  40859 #if defined(BCM_53570_B0)
  40860     { /* SOC_REG_INT_XLMIB_TXPF_BCM53570_B0r */
  40861         soc_block_list[16],
  40862         soc_portreg,
  40863         1,
  40864         0,
  40865         0x5000,
  40866         SOC_REG_FLAG_64_BITS |
  40867                           SOC_REG_FLAG_COUNTER,
  40868         0,
  40869         1,
  40870         soc_R1023_BCM53400_A0r_fields,
  40871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40872         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40873         238,
  40874         -1,
  40875     },
  40876 #endif /* chips */
  40877 
  40878 #if defined(BCM_56370_A0)
  40879     { /* SOC_REG_INT_XLMIB_TXPF_BCM56370_A0r */
  40880         soc_block_list[16],
  40881         soc_portreg,
  40882         1,
  40883         0,
  40884         0x5000,
  40885         SOC_REG_FLAG_64_BITS |
  40886                           SOC_REG_FLAG_COUNTER,
  40887         0,
  40888         1,
  40889         soc_R1023_BCM53400_A0r_fields,
  40890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40892         140,
  40893         -1,
  40894         3,
  40895     },
  40896 #endif /* chips */
  40897 
  40898 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  40899     { /* SOC_REG_INT_XLMIB_TXPF_BCM56980_A0r */
  40900         soc_block_list[16],
  40901         soc_portreg,
  40902         1,
  40903         0,
  40904         0x5000,
  40905         SOC_REG_FLAG_64_BITS |
  40906                           SOC_REG_FLAG_COUNTER,
  40907         0,
  40908         1,
  40909         soc_R1023_BCM53400_A0r_fields,
  40910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40912         115,
  40913         -1,
  40914         3,
  40915     },
  40916 #endif /* chips */
  40917 
  40918 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  40919     { /* SOC_REG_INT_XLMIB_TXPPr */
  40920         soc_block_list[16],
  40921         soc_portreg,
  40922         1,
  40923         0,
  40924         0x5100,
  40925         SOC_REG_FLAG_64_BITS |
  40926                           SOC_REG_FLAG_COUNTER,
  40927         0,
  40928         1,
  40929         soc_R1023_BCM53400_A0r_fields,
  40930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40931         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40932         140,
  40933         -1,
  40934         3,
  40935     },
  40936 #endif /* chips */
  40937 
  40938 #if defined(BCM_53570_A0)
  40939     { /* SOC_REG_INT_XLMIB_TXPP_BCM53570_A0r */
  40940         soc_block_list[16],
  40941         soc_portreg,
  40942         1,
  40943         0,
  40944         0x5100,
  40945         SOC_REG_FLAG_64_BITS |
  40946                           SOC_REG_FLAG_COUNTER,
  40947         0,
  40948         1,
  40949         soc_R1023_BCM53400_A0r_fields,
  40950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40952         235,
  40953         -1,
  40954     },
  40955 #endif /* chips */
  40956 
  40957 #if defined(BCM_53570_B0)
  40958     { /* SOC_REG_INT_XLMIB_TXPP_BCM53570_B0r */
  40959         soc_block_list[16],
  40960         soc_portreg,
  40961         1,
  40962         0,
  40963         0x5100,
  40964         SOC_REG_FLAG_64_BITS |
  40965                           SOC_REG_FLAG_COUNTER,
  40966         0,
  40967         1,
  40968         soc_R1023_BCM53400_A0r_fields,
  40969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40970         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40971         239,
  40972         -1,
  40973     },
  40974 #endif /* chips */
  40975 
  40976 #if defined(BCM_56370_A0)
  40977     { /* SOC_REG_INT_XLMIB_TXPP_BCM56370_A0r */
  40978         soc_block_list[16],
  40979         soc_portreg,
  40980         1,
  40981         0,
  40982         0x5100,
  40983         SOC_REG_FLAG_64_BITS |
  40984                           SOC_REG_FLAG_COUNTER,
  40985         0,
  40986         1,
  40987         soc_R1023_BCM53400_A0r_fields,
  40988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  40990         141,
  40991         -1,
  40992         3,
  40993     },
  40994 #endif /* chips */
  40995 
  40996 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  40997     { /* SOC_REG_INT_XLMIB_TXPP_BCM56980_A0r */
  40998         soc_block_list[16],
  40999         soc_portreg,
  41000         1,
  41001         0,
  41002         0x5100,
  41003         SOC_REG_FLAG_64_BITS |
  41004                           SOC_REG_FLAG_COUNTER,
  41005         0,
  41006         1,
  41007         soc_R1023_BCM53400_A0r_fields,
  41008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41009         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41010         116,
  41011         -1,
  41012         3,
  41013     },
  41014 #endif /* chips */
  41015 
  41016 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  41017     { /* SOC_REG_INT_XLMIB_TX_EEE_LPI_DURATION_COUNTERr */
  41018         soc_block_list[16],
  41019         soc_portreg,
  41020         1,
  41021         0,
  41022         0x6b00,
  41023         SOC_REG_FLAG_64_BITS |
  41024                           SOC_REG_FLAG_COUNTER,
  41025         0,
  41026         1,
  41027         soc_R1023_BCM53400_A0r_fields,
  41028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41029         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41030         166,
  41031         -1,
  41032         3,
  41033     },
  41034 #endif /* chips */
  41035 
  41036 #if defined(BCM_53570_A0)
  41037     { /* SOC_REG_INT_XLMIB_TX_EEE_LPI_DURATION_COUNTER_BCM53570_A0r */
  41038         soc_block_list[16],
  41039         soc_portreg,
  41040         1,
  41041         0,
  41042         0x6b00,
  41043         SOC_REG_FLAG_64_BITS |
  41044                           SOC_REG_FLAG_COUNTER,
  41045         0,
  41046         1,
  41047         soc_R1023_BCM53400_A0r_fields,
  41048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41049         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41050         261,
  41051         -1,
  41052     },
  41053 #endif /* chips */
  41054 
  41055 #if defined(BCM_53570_B0)
  41056     { /* SOC_REG_INT_XLMIB_TX_EEE_LPI_DURATION_COUNTER_BCM53570_B0r */
  41057         soc_block_list[16],
  41058         soc_portreg,
  41059         1,
  41060         0,
  41061         0x6b00,
  41062         SOC_REG_FLAG_64_BITS |
  41063                           SOC_REG_FLAG_COUNTER,
  41064         0,
  41065         1,
  41066         soc_R1023_BCM53400_A0r_fields,
  41067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41068         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41069         265,
  41070         -1,
  41071     },
  41072 #endif /* chips */
  41073 
  41074 #if defined(BCM_56370_A0)
  41075     { /* SOC_REG_INT_XLMIB_TX_EEE_LPI_DURATION_COUNTER_BCM56370_A0r */
  41076         soc_block_list[16],
  41077         soc_portreg,
  41078         1,
  41079         0,
  41080         0x6b00,
  41081         SOC_REG_FLAG_64_BITS |
  41082                           SOC_REG_FLAG_COUNTER,
  41083         0,
  41084         1,
  41085         soc_R1023_BCM53400_A0r_fields,
  41086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41088         167,
  41089         -1,
  41090         3,
  41091     },
  41092 #endif /* chips */
  41093 
  41094 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  41095     { /* SOC_REG_INT_XLMIB_TX_EEE_LPI_DURATION_COUNTER_BCM56980_A0r */
  41096         soc_block_list[16],
  41097         soc_portreg,
  41098         1,
  41099         0,
  41100         0x6b00,
  41101         SOC_REG_FLAG_64_BITS |
  41102                           SOC_REG_FLAG_COUNTER,
  41103         0,
  41104         1,
  41105         soc_R1023_BCM53400_A0r_fields,
  41106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41107         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41108         142,
  41109         -1,
  41110         3,
  41111     },
  41112 #endif /* chips */
  41113 
  41114 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  41115     { /* SOC_REG_INT_XLMIB_TX_EEE_LPI_EVENT_COUNTERr */
  41116         soc_block_list[16],
  41117         soc_portreg,
  41118         1,
  41119         0,
  41120         0x6a00,
  41121         SOC_REG_FLAG_64_BITS |
  41122                           SOC_REG_FLAG_COUNTER,
  41123         0,
  41124         1,
  41125         soc_R1023_BCM53400_A0r_fields,
  41126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41127         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41128         165,
  41129         -1,
  41130         3,
  41131     },
  41132 #endif /* chips */
  41133 
  41134 #if defined(BCM_53570_A0)
  41135     { /* SOC_REG_INT_XLMIB_TX_EEE_LPI_EVENT_COUNTER_BCM53570_A0r */
  41136         soc_block_list[16],
  41137         soc_portreg,
  41138         1,
  41139         0,
  41140         0x6a00,
  41141         SOC_REG_FLAG_64_BITS |
  41142                           SOC_REG_FLAG_COUNTER,
  41143         0,
  41144         1,
  41145         soc_R1023_BCM53400_A0r_fields,
  41146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41147         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41148         260,
  41149         -1,
  41150     },
  41151 #endif /* chips */
  41152 
  41153 #if defined(BCM_53570_B0)
  41154     { /* SOC_REG_INT_XLMIB_TX_EEE_LPI_EVENT_COUNTER_BCM53570_B0r */
  41155         soc_block_list[16],
  41156         soc_portreg,
  41157         1,
  41158         0,
  41159         0x6a00,
  41160         SOC_REG_FLAG_64_BITS |
  41161                           SOC_REG_FLAG_COUNTER,
  41162         0,
  41163         1,
  41164         soc_R1023_BCM53400_A0r_fields,
  41165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41166         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41167         264,
  41168         -1,
  41169     },
  41170 #endif /* chips */
  41171 
  41172 #if defined(BCM_56370_A0)
  41173     { /* SOC_REG_INT_XLMIB_TX_EEE_LPI_EVENT_COUNTER_BCM56370_A0r */
  41174         soc_block_list[16],
  41175         soc_portreg,
  41176         1,
  41177         0,
  41178         0x6a00,
  41179         SOC_REG_FLAG_64_BITS |
  41180                           SOC_REG_FLAG_COUNTER,
  41181         0,
  41182         1,
  41183         soc_R1023_BCM53400_A0r_fields,
  41184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41185         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41186         166,
  41187         -1,
  41188         3,
  41189     },
  41190 #endif /* chips */
  41191 
  41192 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  41193     { /* SOC_REG_INT_XLMIB_TX_EEE_LPI_EVENT_COUNTER_BCM56980_A0r */
  41194         soc_block_list[16],
  41195         soc_portreg,
  41196         1,
  41197         0,
  41198         0x6a00,
  41199         SOC_REG_FLAG_64_BITS |
  41200                           SOC_REG_FLAG_COUNTER,
  41201         0,
  41202         1,
  41203         soc_R1023_BCM53400_A0r_fields,
  41204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41205         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41206         141,
  41207         -1,
  41208         3,
  41209     },
  41210 #endif /* chips */
  41211 
  41212 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  41213     { /* SOC_REG_INT_XLMIB_TX_HCFC_COUNTERr */
  41214         soc_block_list[16],
  41215         soc_portreg,
  41216         1,
  41217         0,
  41218         0x6d00,
  41219         SOC_REG_FLAG_64_BITS |
  41220                           SOC_REG_FLAG_COUNTER,
  41221         0,
  41222         1,
  41223         soc_R1023_BCM53400_A0r_fields,
  41224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41225         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41226         168,
  41227         -1,
  41228         3,
  41229     },
  41230 #endif /* chips */
  41231 
  41232 #if defined(BCM_53570_A0)
  41233     { /* SOC_REG_INT_XLMIB_TX_HCFC_COUNTER_BCM53570_A0r */
  41234         soc_block_list[16],
  41235         soc_portreg,
  41236         1,
  41237         0,
  41238         0x6d00,
  41239         SOC_REG_FLAG_64_BITS |
  41240                           SOC_REG_FLAG_COUNTER,
  41241         0,
  41242         1,
  41243         soc_XLMIB_RSCHCRCr_fields,
  41244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41245         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41246         263,
  41247         -1,
  41248     },
  41249 #endif /* chips */
  41250 
  41251 #if defined(BCM_53570_B0)
  41252     { /* SOC_REG_INT_XLMIB_TX_HCFC_COUNTER_BCM53570_B0r */
  41253         soc_block_list[16],
  41254         soc_portreg,
  41255         1,
  41256         0,
  41257         0x6d00,
  41258         SOC_REG_FLAG_64_BITS |
  41259                           SOC_REG_FLAG_COUNTER,
  41260         0,
  41261         1,
  41262         soc_XLMIB_RSCHCRCr_fields,
  41263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41264         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41265         267,
  41266         -1,
  41267     },
  41268 #endif /* chips */
  41269 
  41270 #if defined(BCM_56370_A0)
  41271     { /* SOC_REG_INT_XLMIB_TX_HCFC_COUNTER_BCM56370_A0r */
  41272         soc_block_list[16],
  41273         soc_portreg,
  41274         1,
  41275         0,
  41276         0x6d00,
  41277         SOC_REG_FLAG_64_BITS |
  41278                           SOC_REG_FLAG_COUNTER,
  41279         0,
  41280         1,
  41281         soc_R1023_BCM53400_A0r_fields,
  41282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41283         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41284         169,
  41285         -1,
  41286         3,
  41287     },
  41288 #endif /* chips */
  41289 
  41290 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  41291     { /* SOC_REG_INT_XLMIB_TX_HCFC_COUNTER_BCM56980_A0r */
  41292         soc_block_list[16],
  41293         soc_portreg,
  41294         1,
  41295         0,
  41296         0x6d00,
  41297         SOC_REG_FLAG_64_BITS |
  41298                           SOC_REG_FLAG_COUNTER,
  41299         0,
  41300         1,
  41301         soc_R1023_BCM53400_A0r_fields,
  41302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41303         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41304         144,
  41305         -1,
  41306         3,
  41307     },
  41308 #endif /* chips */
  41309 
  41310 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  41311     { /* SOC_REG_INT_XLMIB_TX_LLFC_LOG_COUNTERr */
  41312         soc_block_list[16],
  41313         soc_portreg,
  41314         1,
  41315         0,
  41316         0x6c00,
  41317         SOC_REG_FLAG_64_BITS |
  41318                           SOC_REG_FLAG_COUNTER,
  41319         0,
  41320         1,
  41321         soc_R1023_BCM53400_A0r_fields,
  41322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41323         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41324         167,
  41325         -1,
  41326         3,
  41327     },
  41328 #endif /* chips */
  41329 
  41330 #if defined(BCM_53570_A0)
  41331     { /* SOC_REG_INT_XLMIB_TX_LLFC_LOG_COUNTER_BCM53570_A0r */
  41332         soc_block_list[16],
  41333         soc_portreg,
  41334         1,
  41335         0,
  41336         0x6c00,
  41337         SOC_REG_FLAG_64_BITS |
  41338                           SOC_REG_FLAG_COUNTER,
  41339         0,
  41340         1,
  41341         soc_R1023_BCM53400_A0r_fields,
  41342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41343         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41344         262,
  41345         -1,
  41346     },
  41347 #endif /* chips */
  41348 
  41349 #if defined(BCM_53570_B0)
  41350     { /* SOC_REG_INT_XLMIB_TX_LLFC_LOG_COUNTER_BCM53570_B0r */
  41351         soc_block_list[16],
  41352         soc_portreg,
  41353         1,
  41354         0,
  41355         0x6c00,
  41356         SOC_REG_FLAG_64_BITS |
  41357                           SOC_REG_FLAG_COUNTER,
  41358         0,
  41359         1,
  41360         soc_R1023_BCM53400_A0r_fields,
  41361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41362         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41363         266,
  41364         -1,
  41365     },
  41366 #endif /* chips */
  41367 
  41368 #if defined(BCM_56370_A0)
  41369     { /* SOC_REG_INT_XLMIB_TX_LLFC_LOG_COUNTER_BCM56370_A0r */
  41370         soc_block_list[16],
  41371         soc_portreg,
  41372         1,
  41373         0,
  41374         0x6c00,
  41375         SOC_REG_FLAG_64_BITS |
  41376                           SOC_REG_FLAG_COUNTER,
  41377         0,
  41378         1,
  41379         soc_R1023_BCM53400_A0r_fields,
  41380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41381         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41382         168,
  41383         -1,
  41384         3,
  41385     },
  41386 #endif /* chips */
  41387 
  41388 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  41389     { /* SOC_REG_INT_XLMIB_TX_LLFC_LOG_COUNTER_BCM56980_A0r */
  41390         soc_block_list[16],
  41391         soc_portreg,
  41392         1,
  41393         0,
  41394         0x6c00,
  41395         SOC_REG_FLAG_64_BITS |
  41396                           SOC_REG_FLAG_COUNTER,
  41397         0,
  41398         1,
  41399         soc_R1023_BCM53400_A0r_fields,
  41400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41401         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41402         143,
  41403         -1,
  41404         3,
  41405     },
  41406 #endif /* chips */
  41407 
  41408 #if defined(BCM_56970_A0)
  41409     { /* SOC_REG_INT_XLMIB_XTHOLr */
  41410         soc_block_list[16],
  41411         soc_portreg,
  41412         1,
  41413         0,
  41414         0x7000,
  41415         SOC_REG_FLAG_64_BITS |
  41416                           SOC_REG_FLAG_COUNTER,
  41417         0,
  41418         1,
  41419         soc_R1023_BCM2801PM_A0r_fields,
  41420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41421         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  41422         167,
  41423         -1,
  41424         3,
  41425     },
  41426 #endif /* chips */
  41427 
  41428 #if defined(BCM_53570_A0)
  41429     { /* SOC_REG_INT_XLMIB_XTHOL_BCM53570_A0r */
  41430         soc_block_list[16],
  41431         soc_portreg,
  41432         1,
  41433         0,
  41434         0x7000,
  41435         SOC_REG_FLAG_64_BITS |
  41436                           SOC_REG_FLAG_COUNTER,
  41437         0,
  41438         1,
  41439         soc_R1023_BCM2801PM_A0r_fields,
  41440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41441         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  41442         266,
  41443         -1,
  41444     },
  41445 #endif /* chips */
  41446 
  41447 #if defined(BCM_53570_B0)
  41448     { /* SOC_REG_INT_XLMIB_XTHOL_BCM53570_B0r */
  41449         soc_block_list[16],
  41450         soc_portreg,
  41451         1,
  41452         0,
  41453         0x7000,
  41454         SOC_REG_FLAG_64_BITS |
  41455                           SOC_REG_FLAG_COUNTER,
  41456         0,
  41457         1,
  41458         soc_R1023_BCM2801PM_A0r_fields,
  41459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41460         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  41461         270,
  41462         -1,
  41463     },
  41464 #endif /* chips */
  41465 
  41466 #if defined(BCM_56370_A0)
  41467     { /* SOC_REG_INT_XLMIB_XTHOL_BCM56370_A0r */
  41468         soc_block_list[16],
  41469         soc_portreg,
  41470         1,
  41471         0,
  41472         0x7000,
  41473         SOC_REG_FLAG_64_BITS |
  41474                           SOC_REG_FLAG_COUNTER,
  41475         0,
  41476         1,
  41477         soc_R1023_BCM2801PM_A0r_fields,
  41478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41479         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  41480         172,
  41481         -1,
  41482         3,
  41483     },
  41484 #endif /* chips */
  41485 
  41486 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  41487     { /* SOC_REG_INT_XLMIB_XTHOL_BCM56870_A0r */
  41488         soc_block_list[16],
  41489         soc_portreg,
  41490         1,
  41491         0,
  41492         0x7000,
  41493         SOC_REG_FLAG_64_BITS |
  41494                           SOC_REG_FLAG_COUNTER,
  41495         0,
  41496         1,
  41497         soc_R1023_BCM2801PM_A0r_fields,
  41498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41499         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  41500         171,
  41501         -1,
  41502         3,
  41503     },
  41504 #endif /* chips */
  41505 
  41506 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  41507     { /* SOC_REG_INT_XLMIB_XTHOL_BCM56980_A0r */
  41508         soc_block_list[16],
  41509         soc_portreg,
  41510         1,
  41511         0,
  41512         0x7000,
  41513         SOC_REG_FLAG_64_BITS |
  41514                           SOC_REG_FLAG_COUNTER,
  41515         0,
  41516         1,
  41517         soc_R1023_BCM2801PM_A0r_fields,
  41518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41519         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  41520         147,
  41521         -1,
  41522         3,
  41523     },
  41524 #endif /* chips */
  41525 
  41526 #if defined(BCM_53570_A0)
  41527     { /* SOC_REG_INT_XLPMIB_R64r */
  41528         soc_block_list[16],
  41529         soc_portreg,
  41530         1,
  41531         0,
  41532         0x10000,
  41533         SOC_REG_FLAG_64_BITS |
  41534                           SOC_REG_FLAG_COUNTER,
  41535         0,
  41536         1,
  41537         soc_R1023_BCM53400_A0r_fields,
  41538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41540         283,
  41541         -1,
  41542     },
  41543 #endif /* chips */
  41544 
  41545 #if defined(BCM_53570_A0)
  41546     { /* SOC_REG_INT_XLPMIB_R127r */
  41547         soc_block_list[16],
  41548         soc_portreg,
  41549         1,
  41550         0,
  41551         0x10100,
  41552         SOC_REG_FLAG_64_BITS |
  41553                           SOC_REG_FLAG_COUNTER,
  41554         0,
  41555         1,
  41556         soc_R1023_BCM53400_A0r_fields,
  41557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41559         284,
  41560         -1,
  41561     },
  41562 #endif /* chips */
  41563 
  41564 #if defined(BCM_53570_A0)
  41565     { /* SOC_REG_INT_XLPMIB_R255r */
  41566         soc_block_list[16],
  41567         soc_portreg,
  41568         1,
  41569         0,
  41570         0x10200,
  41571         SOC_REG_FLAG_64_BITS |
  41572                           SOC_REG_FLAG_COUNTER,
  41573         0,
  41574         1,
  41575         soc_R1023_BCM53400_A0r_fields,
  41576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41577         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41578         285,
  41579         -1,
  41580     },
  41581 #endif /* chips */
  41582 
  41583 #if defined(BCM_53570_A0)
  41584     { /* SOC_REG_INT_XLPMIB_R511r */
  41585         soc_block_list[16],
  41586         soc_portreg,
  41587         1,
  41588         0,
  41589         0x10300,
  41590         SOC_REG_FLAG_64_BITS |
  41591                           SOC_REG_FLAG_COUNTER,
  41592         0,
  41593         1,
  41594         soc_R1023_BCM53400_A0r_fields,
  41595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41596         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41597         286,
  41598         -1,
  41599     },
  41600 #endif /* chips */
  41601 
  41602 #if defined(BCM_53570_A0)
  41603     { /* SOC_REG_INT_XLPMIB_R1023r */
  41604         soc_block_list[16],
  41605         soc_portreg,
  41606         1,
  41607         0,
  41608         0x10400,
  41609         SOC_REG_FLAG_64_BITS |
  41610                           SOC_REG_FLAG_COUNTER,
  41611         0,
  41612         1,
  41613         soc_R1023_BCM53400_A0r_fields,
  41614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41616         287,
  41617         -1,
  41618     },
  41619 #endif /* chips */
  41620 
  41621 #if defined(BCM_53570_A0)
  41622     { /* SOC_REG_INT_XLPMIB_R1518r */
  41623         soc_block_list[16],
  41624         soc_portreg,
  41625         1,
  41626         0,
  41627         0x10500,
  41628         SOC_REG_FLAG_64_BITS |
  41629                           SOC_REG_FLAG_COUNTER,
  41630         0,
  41631         1,
  41632         soc_R1023_BCM53400_A0r_fields,
  41633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41634         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41635         288,
  41636         -1,
  41637     },
  41638 #endif /* chips */
  41639 
  41640 #if defined(BCM_53570_A0)
  41641     { /* SOC_REG_INT_XLPMIB_R2047r */
  41642         soc_block_list[16],
  41643         soc_portreg,
  41644         1,
  41645         0,
  41646         0x10700,
  41647         SOC_REG_FLAG_64_BITS |
  41648                           SOC_REG_FLAG_COUNTER,
  41649         0,
  41650         1,
  41651         soc_R1023_BCM53400_A0r_fields,
  41652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41653         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41654         290,
  41655         -1,
  41656     },
  41657 #endif /* chips */
  41658 
  41659 #if defined(BCM_53570_A0)
  41660     { /* SOC_REG_INT_XLPMIB_R4095r */
  41661         soc_block_list[16],
  41662         soc_portreg,
  41663         1,
  41664         0,
  41665         0x10800,
  41666         SOC_REG_FLAG_64_BITS |
  41667                           SOC_REG_FLAG_COUNTER,
  41668         0,
  41669         1,
  41670         soc_R1023_BCM53400_A0r_fields,
  41671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41672         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41673         291,
  41674         -1,
  41675     },
  41676 #endif /* chips */
  41677 
  41678 #if defined(BCM_53570_A0)
  41679     { /* SOC_REG_INT_XLPMIB_R9216r */
  41680         soc_block_list[16],
  41681         soc_portreg,
  41682         1,
  41683         0,
  41684         0x10900,
  41685         SOC_REG_FLAG_64_BITS |
  41686                           SOC_REG_FLAG_COUNTER,
  41687         0,
  41688         1,
  41689         soc_R1023_BCM53400_A0r_fields,
  41690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41692         292,
  41693         -1,
  41694     },
  41695 #endif /* chips */
  41696 
  41697 #if defined(BCM_53570_A0)
  41698     { /* SOC_REG_INT_XLPMIB_R16383r */
  41699         soc_block_list[16],
  41700         soc_portreg,
  41701         1,
  41702         0,
  41703         0x10a00,
  41704         SOC_REG_FLAG_64_BITS |
  41705                           SOC_REG_FLAG_COUNTER,
  41706         0,
  41707         1,
  41708         soc_R1023_BCM53400_A0r_fields,
  41709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41710         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41711         293,
  41712         -1,
  41713     },
  41714 #endif /* chips */
  41715 
  41716 #if defined(BCM_53570_B0)
  41717     { /* SOC_REG_INT_XLPMIB_R1023_BCM53570_B0r */
  41718         soc_block_list[16],
  41719         soc_portreg,
  41720         1,
  41721         0,
  41722         0x10400,
  41723         SOC_REG_FLAG_64_BITS |
  41724                           SOC_REG_FLAG_COUNTER,
  41725         0,
  41726         1,
  41727         soc_R1023_BCM53400_A0r_fields,
  41728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41729         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41730         291,
  41731         -1,
  41732     },
  41733 #endif /* chips */
  41734 
  41735 #if defined(BCM_53570_B0)
  41736     { /* SOC_REG_INT_XLPMIB_R127_BCM53570_B0r */
  41737         soc_block_list[16],
  41738         soc_portreg,
  41739         1,
  41740         0,
  41741         0x10100,
  41742         SOC_REG_FLAG_64_BITS |
  41743                           SOC_REG_FLAG_COUNTER,
  41744         0,
  41745         1,
  41746         soc_R1023_BCM53400_A0r_fields,
  41747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41748         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41749         288,
  41750         -1,
  41751     },
  41752 #endif /* chips */
  41753 
  41754 #if defined(BCM_53570_B0)
  41755     { /* SOC_REG_INT_XLPMIB_R1518_BCM53570_B0r */
  41756         soc_block_list[16],
  41757         soc_portreg,
  41758         1,
  41759         0,
  41760         0x10500,
  41761         SOC_REG_FLAG_64_BITS |
  41762                           SOC_REG_FLAG_COUNTER,
  41763         0,
  41764         1,
  41765         soc_R1023_BCM53400_A0r_fields,
  41766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41767         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41768         292,
  41769         -1,
  41770     },
  41771 #endif /* chips */
  41772 
  41773 #if defined(BCM_53570_B0)
  41774     { /* SOC_REG_INT_XLPMIB_R16383_BCM53570_B0r */
  41775         soc_block_list[16],
  41776         soc_portreg,
  41777         1,
  41778         0,
  41779         0x10a00,
  41780         SOC_REG_FLAG_64_BITS |
  41781                           SOC_REG_FLAG_COUNTER,
  41782         0,
  41783         1,
  41784         soc_R1023_BCM53400_A0r_fields,
  41785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41786         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41787         297,
  41788         -1,
  41789     },
  41790 #endif /* chips */
  41791 
  41792 #if defined(BCM_53570_B0)
  41793     { /* SOC_REG_INT_XLPMIB_R2047_BCM53570_B0r */
  41794         soc_block_list[16],
  41795         soc_portreg,
  41796         1,
  41797         0,
  41798         0x10700,
  41799         SOC_REG_FLAG_64_BITS |
  41800                           SOC_REG_FLAG_COUNTER,
  41801         0,
  41802         1,
  41803         soc_R1023_BCM53400_A0r_fields,
  41804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41805         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41806         294,
  41807         -1,
  41808     },
  41809 #endif /* chips */
  41810 
  41811 #if defined(BCM_53570_B0)
  41812     { /* SOC_REG_INT_XLPMIB_R255_BCM53570_B0r */
  41813         soc_block_list[16],
  41814         soc_portreg,
  41815         1,
  41816         0,
  41817         0x10200,
  41818         SOC_REG_FLAG_64_BITS |
  41819                           SOC_REG_FLAG_COUNTER,
  41820         0,
  41821         1,
  41822         soc_R1023_BCM53400_A0r_fields,
  41823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41824         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41825         289,
  41826         -1,
  41827     },
  41828 #endif /* chips */
  41829 
  41830 #if defined(BCM_53570_B0)
  41831     { /* SOC_REG_INT_XLPMIB_R4095_BCM53570_B0r */
  41832         soc_block_list[16],
  41833         soc_portreg,
  41834         1,
  41835         0,
  41836         0x10800,
  41837         SOC_REG_FLAG_64_BITS |
  41838                           SOC_REG_FLAG_COUNTER,
  41839         0,
  41840         1,
  41841         soc_R1023_BCM53400_A0r_fields,
  41842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41843         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41844         295,
  41845         -1,
  41846     },
  41847 #endif /* chips */
  41848 
  41849 #if defined(BCM_53570_B0)
  41850     { /* SOC_REG_INT_XLPMIB_R511_BCM53570_B0r */
  41851         soc_block_list[16],
  41852         soc_portreg,
  41853         1,
  41854         0,
  41855         0x10300,
  41856         SOC_REG_FLAG_64_BITS |
  41857                           SOC_REG_FLAG_COUNTER,
  41858         0,
  41859         1,
  41860         soc_R1023_BCM53400_A0r_fields,
  41861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41862         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41863         290,
  41864         -1,
  41865     },
  41866 #endif /* chips */
  41867 
  41868 #if defined(BCM_53570_B0)
  41869     { /* SOC_REG_INT_XLPMIB_R64_BCM53570_B0r */
  41870         soc_block_list[16],
  41871         soc_portreg,
  41872         1,
  41873         0,
  41874         0x10000,
  41875         SOC_REG_FLAG_64_BITS |
  41876                           SOC_REG_FLAG_COUNTER,
  41877         0,
  41878         1,
  41879         soc_R1023_BCM53400_A0r_fields,
  41880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41881         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41882         287,
  41883         -1,
  41884     },
  41885 #endif /* chips */
  41886 
  41887 #if defined(BCM_53570_B0)
  41888     { /* SOC_REG_INT_XLPMIB_R9216_BCM53570_B0r */
  41889         soc_block_list[16],
  41890         soc_portreg,
  41891         1,
  41892         0,
  41893         0x10900,
  41894         SOC_REG_FLAG_64_BITS |
  41895                           SOC_REG_FLAG_COUNTER,
  41896         0,
  41897         1,
  41898         soc_R1023_BCM53400_A0r_fields,
  41899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41900         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41901         296,
  41902         -1,
  41903     },
  41904 #endif /* chips */
  41905 
  41906 #if defined(BCM_53570_A0)
  41907     { /* SOC_REG_INT_XLPMIB_RALNr */
  41908         soc_block_list[16],
  41909         soc_portreg,
  41910         1,
  41911         0,
  41912         0x11600,
  41913         SOC_REG_FLAG_64_BITS |
  41914                           SOC_REG_FLAG_COUNTER,
  41915         0,
  41916         1,
  41917         soc_XLMIB_RSCHCRCr_fields,
  41918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41919         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41920         305,
  41921         -1,
  41922     },
  41923 #endif /* chips */
  41924 
  41925 #if defined(BCM_53570_B0)
  41926     { /* SOC_REG_INT_XLPMIB_RALN_BCM53570_B0r */
  41927         soc_block_list[16],
  41928         soc_portreg,
  41929         1,
  41930         0,
  41931         0x11600,
  41932         SOC_REG_FLAG_64_BITS |
  41933                           SOC_REG_FLAG_COUNTER,
  41934         0,
  41935         1,
  41936         soc_XLMIB_RSCHCRCr_fields,
  41937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41938         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41939         309,
  41940         -1,
  41941     },
  41942 #endif /* chips */
  41943 
  41944 #if defined(BCM_53570_A0)
  41945     { /* SOC_REG_INT_XLPMIB_RBCAr */
  41946         soc_block_list[16],
  41947         soc_portreg,
  41948         1,
  41949         0,
  41950         0x10e00,
  41951         SOC_REG_FLAG_64_BITS |
  41952                           SOC_REG_FLAG_COUNTER,
  41953         0,
  41954         1,
  41955         soc_R1023_BCM53400_A0r_fields,
  41956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41957         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41958         297,
  41959         -1,
  41960     },
  41961 #endif /* chips */
  41962 
  41963 #if defined(BCM_53570_B0)
  41964     { /* SOC_REG_INT_XLPMIB_RBCA_BCM53570_B0r */
  41965         soc_block_list[16],
  41966         soc_portreg,
  41967         1,
  41968         0,
  41969         0x10e00,
  41970         SOC_REG_FLAG_64_BITS |
  41971                           SOC_REG_FLAG_COUNTER,
  41972         0,
  41973         1,
  41974         soc_R1023_BCM53400_A0r_fields,
  41975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41976         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41977         301,
  41978         -1,
  41979     },
  41980 #endif /* chips */
  41981 
  41982 #if defined(BCM_53570_A0)
  41983     { /* SOC_REG_INT_XLPMIB_RBYTr */
  41984         soc_block_list[16],
  41985         soc_portreg,
  41986         1,
  41987         0,
  41988         0x13d00,
  41989         SOC_REG_FLAG_64_BITS |
  41990                           SOC_REG_FLAG_COUNTER,
  41991         0,
  41992         1,
  41993         soc_RBYT_BCM53400_A0r_fields,
  41994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41995         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  41996         344,
  41997         -1,
  41998     },
  41999 #endif /* chips */
  42000 
  42001 #if defined(BCM_53570_B0)
  42002     { /* SOC_REG_INT_XLPMIB_RBYT_BCM53570_B0r */
  42003         soc_block_list[16],
  42004         soc_portreg,
  42005         1,
  42006         0,
  42007         0x13d00,
  42008         SOC_REG_FLAG_64_BITS |
  42009                           SOC_REG_FLAG_COUNTER,
  42010         0,
  42011         1,
  42012         soc_RBYT_BCM53400_A0r_fields,
  42013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42014         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42015         348,
  42016         -1,
  42017     },
  42018 #endif /* chips */
  42019 
  42020 #if defined(BCM_53570_A0)
  42021     { /* SOC_REG_INT_XLPMIB_RDVLNr */
  42022         soc_block_list[16],
  42023         soc_portreg,
  42024         1,
  42025         0,
  42026         0x12000,
  42027         SOC_REG_FLAG_64_BITS |
  42028                           SOC_REG_FLAG_COUNTER,
  42029         0,
  42030         1,
  42031         soc_R1023_BCM53400_A0r_fields,
  42032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42033         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42034         315,
  42035         -1,
  42036     },
  42037 #endif /* chips */
  42038 
  42039 #if defined(BCM_53570_B0)
  42040     { /* SOC_REG_INT_XLPMIB_RDVLN_BCM53570_B0r */
  42041         soc_block_list[16],
  42042         soc_portreg,
  42043         1,
  42044         0,
  42045         0x12000,
  42046         SOC_REG_FLAG_64_BITS |
  42047                           SOC_REG_FLAG_COUNTER,
  42048         0,
  42049         1,
  42050         soc_R1023_BCM53400_A0r_fields,
  42051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42052         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42053         319,
  42054         -1,
  42055     },
  42056 #endif /* chips */
  42057 
  42058 #if defined(BCM_53570_A0)
  42059     { /* SOC_REG_INT_XLPMIB_RERPKTr */
  42060         soc_block_list[16],
  42061         soc_portreg,
  42062         1,
  42063         0,
  42064         0x11800,
  42065         SOC_REG_FLAG_64_BITS |
  42066                           SOC_REG_FLAG_COUNTER |
  42067                           SOC_REG_FLAG_ED_CNTR,
  42068         0,
  42069         1,
  42070         soc_R1023_BCM53400_A0r_fields,
  42071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42072         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42073         307,
  42074         -1,
  42075     },
  42076 #endif /* chips */
  42077 
  42078 #if defined(BCM_53570_B0)
  42079     { /* SOC_REG_INT_XLPMIB_RERPKT_BCM53570_B0r */
  42080         soc_block_list[16],
  42081         soc_portreg,
  42082         1,
  42083         0,
  42084         0x11800,
  42085         SOC_REG_FLAG_64_BITS |
  42086                           SOC_REG_FLAG_COUNTER |
  42087                           SOC_REG_FLAG_ED_CNTR,
  42088         0,
  42089         1,
  42090         soc_R1023_BCM53400_A0r_fields,
  42091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42092         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42093         311,
  42094         -1,
  42095     },
  42096 #endif /* chips */
  42097 
  42098 #if defined(BCM_53570_A0)
  42099     { /* SOC_REG_INT_XLPMIB_RFCRr */
  42100         soc_block_list[16],
  42101         soc_portreg,
  42102         1,
  42103         0,
  42104         0x11900,
  42105         SOC_REG_FLAG_64_BITS |
  42106                           SOC_REG_FLAG_COUNTER,
  42107         0,
  42108         1,
  42109         soc_XLMIB_RSCHCRCr_fields,
  42110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42111         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42112         308,
  42113         -1,
  42114     },
  42115 #endif /* chips */
  42116 
  42117 #if defined(BCM_53570_B0)
  42118     { /* SOC_REG_INT_XLPMIB_RFCR_BCM53570_B0r */
  42119         soc_block_list[16],
  42120         soc_portreg,
  42121         1,
  42122         0,
  42123         0x11900,
  42124         SOC_REG_FLAG_64_BITS |
  42125                           SOC_REG_FLAG_COUNTER,
  42126         0,
  42127         1,
  42128         soc_XLMIB_RSCHCRCr_fields,
  42129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42130         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42131         312,
  42132         -1,
  42133     },
  42134 #endif /* chips */
  42135 
  42136 #if defined(BCM_53570_A0)
  42137     { /* SOC_REG_INT_XLPMIB_RFCSr */
  42138         soc_block_list[16],
  42139         soc_portreg,
  42140         1,
  42141         0,
  42142         0x10f00,
  42143         SOC_REG_FLAG_64_BITS |
  42144                           SOC_REG_FLAG_COUNTER,
  42145         0,
  42146         1,
  42147         soc_R1023_BCM53400_A0r_fields,
  42148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42150         298,
  42151         -1,
  42152     },
  42153 #endif /* chips */
  42154 
  42155 #if defined(BCM_53570_B0)
  42156     { /* SOC_REG_INT_XLPMIB_RFCS_BCM53570_B0r */
  42157         soc_block_list[16],
  42158         soc_portreg,
  42159         1,
  42160         0,
  42161         0x10f00,
  42162         SOC_REG_FLAG_64_BITS |
  42163                           SOC_REG_FLAG_COUNTER,
  42164         0,
  42165         1,
  42166         soc_R1023_BCM53400_A0r_fields,
  42167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42169         302,
  42170         -1,
  42171     },
  42172 #endif /* chips */
  42173 
  42174 #if defined(BCM_53570_A0)
  42175     { /* SOC_REG_INT_XLPMIB_RFFMSEr */
  42176         soc_block_list[16],
  42177         soc_portreg,
  42178         1,
  42179         0,
  42180         0x12900,
  42181         SOC_REG_FLAG_64_BITS |
  42182                           SOC_REG_FLAG_COUNTER,
  42183         0,
  42184         1,
  42185         soc_R1023_BCM53400_A0r_fields,
  42186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42187         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42188         324,
  42189         -1,
  42190     },
  42191 #endif /* chips */
  42192 
  42193 #if defined(BCM_53570_B0)
  42194     { /* SOC_REG_INT_XLPMIB_RFFMSE_BCM53570_B0r */
  42195         soc_block_list[16],
  42196         soc_portreg,
  42197         1,
  42198         0,
  42199         0x12900,
  42200         SOC_REG_FLAG_64_BITS |
  42201                           SOC_REG_FLAG_COUNTER,
  42202         0,
  42203         1,
  42204         soc_R1023_BCM53400_A0r_fields,
  42205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42206         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42207         328,
  42208         -1,
  42209     },
  42210 #endif /* chips */
  42211 
  42212 #if defined(BCM_53570_A0)
  42213     { /* SOC_REG_INT_XLPMIB_RFLRr */
  42214         soc_block_list[16],
  42215         soc_portreg,
  42216         1,
  42217         0,
  42218         0x11700,
  42219         SOC_REG_FLAG_64_BITS |
  42220                           SOC_REG_FLAG_COUNTER |
  42221                           SOC_REG_FLAG_ED_CNTR,
  42222         0,
  42223         1,
  42224         soc_R1023_BCM53400_A0r_fields,
  42225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42226         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42227         306,
  42228         -1,
  42229     },
  42230 #endif /* chips */
  42231 
  42232 #if defined(BCM_53570_B0)
  42233     { /* SOC_REG_INT_XLPMIB_RFLR_BCM53570_B0r */
  42234         soc_block_list[16],
  42235         soc_portreg,
  42236         1,
  42237         0,
  42238         0x11700,
  42239         SOC_REG_FLAG_64_BITS |
  42240                           SOC_REG_FLAG_COUNTER |
  42241                           SOC_REG_FLAG_ED_CNTR,
  42242         0,
  42243         1,
  42244         soc_R1023_BCM53400_A0r_fields,
  42245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42246         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42247         310,
  42248         -1,
  42249     },
  42250 #endif /* chips */
  42251 
  42252 #if defined(BCM_53570_A0)
  42253     { /* SOC_REG_INT_XLPMIB_RFRGr */
  42254         soc_block_list[16],
  42255         soc_portreg,
  42256         1,
  42257         0,
  42258         0x13500,
  42259         SOC_REG_FLAG_64_BITS |
  42260                           SOC_REG_FLAG_COUNTER |
  42261                           SOC_REG_FLAG_ED_CNTR,
  42262         0,
  42263         1,
  42264         soc_R1023_BCM53400_A0r_fields,
  42265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42266         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42267         336,
  42268         -1,
  42269     },
  42270 #endif /* chips */
  42271 
  42272 #if defined(BCM_53570_B0)
  42273     { /* SOC_REG_INT_XLPMIB_RFRG_BCM53570_B0r */
  42274         soc_block_list[16],
  42275         soc_portreg,
  42276         1,
  42277         0,
  42278         0x13500,
  42279         SOC_REG_FLAG_64_BITS |
  42280                           SOC_REG_FLAG_COUNTER |
  42281                           SOC_REG_FLAG_ED_CNTR,
  42282         0,
  42283         1,
  42284         soc_R1023_BCM53400_A0r_fields,
  42285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42286         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42287         340,
  42288         -1,
  42289     },
  42290 #endif /* chips */
  42291 
  42292 #if defined(BCM_53570_A0)
  42293     { /* SOC_REG_INT_XLPMIB_RJBRr */
  42294         soc_block_list[16],
  42295         soc_portreg,
  42296         1,
  42297         0,
  42298         0x11b00,
  42299         SOC_REG_FLAG_64_BITS |
  42300                           SOC_REG_FLAG_COUNTER |
  42301                           SOC_REG_FLAG_ED_CNTR,
  42302         0,
  42303         1,
  42304         soc_R1023_BCM53400_A0r_fields,
  42305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42307         310,
  42308         -1,
  42309     },
  42310 #endif /* chips */
  42311 
  42312 #if defined(BCM_53570_B0)
  42313     { /* SOC_REG_INT_XLPMIB_RJBR_BCM53570_B0r */
  42314         soc_block_list[16],
  42315         soc_portreg,
  42316         1,
  42317         0,
  42318         0x11b00,
  42319         SOC_REG_FLAG_64_BITS |
  42320                           SOC_REG_FLAG_COUNTER |
  42321                           SOC_REG_FLAG_ED_CNTR,
  42322         0,
  42323         1,
  42324         soc_R1023_BCM53400_A0r_fields,
  42325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42326         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42327         314,
  42328         -1,
  42329     },
  42330 #endif /* chips */
  42331 
  42332 #if defined(BCM_53570_A0)
  42333     { /* SOC_REG_INT_XLPMIB_RMCAr */
  42334         soc_block_list[16],
  42335         soc_portreg,
  42336         1,
  42337         0,
  42338         0x10d00,
  42339         SOC_REG_FLAG_64_BITS |
  42340                           SOC_REG_FLAG_COUNTER,
  42341         0,
  42342         1,
  42343         soc_R1023_BCM53400_A0r_fields,
  42344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42345         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42346         296,
  42347         -1,
  42348     },
  42349 #endif /* chips */
  42350 
  42351 #if defined(BCM_53570_B0)
  42352     { /* SOC_REG_INT_XLPMIB_RMCA_BCM53570_B0r */
  42353         soc_block_list[16],
  42354         soc_portreg,
  42355         1,
  42356         0,
  42357         0x10d00,
  42358         SOC_REG_FLAG_64_BITS |
  42359                           SOC_REG_FLAG_COUNTER,
  42360         0,
  42361         1,
  42362         soc_R1023_BCM53400_A0r_fields,
  42363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42364         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42365         300,
  42366         -1,
  42367     },
  42368 #endif /* chips */
  42369 
  42370 #if defined(BCM_53570_A0)
  42371     { /* SOC_REG_INT_XLPMIB_RMCRCr */
  42372         soc_block_list[16],
  42373         soc_portreg,
  42374         1,
  42375         0,
  42376         0x11d00,
  42377         SOC_REG_FLAG_64_BITS |
  42378                           SOC_REG_FLAG_COUNTER,
  42379         0,
  42380         1,
  42381         soc_R1023_BCM53400_A0r_fields,
  42382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42384         312,
  42385         -1,
  42386     },
  42387 #endif /* chips */
  42388 
  42389 #if defined(BCM_53570_B0)
  42390     { /* SOC_REG_INT_XLPMIB_RMCRC_BCM53570_B0r */
  42391         soc_block_list[16],
  42392         soc_portreg,
  42393         1,
  42394         0,
  42395         0x11d00,
  42396         SOC_REG_FLAG_64_BITS |
  42397                           SOC_REG_FLAG_COUNTER,
  42398         0,
  42399         1,
  42400         soc_R1023_BCM53400_A0r_fields,
  42401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42402         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42403         316,
  42404         -1,
  42405     },
  42406 #endif /* chips */
  42407 
  42408 #if defined(BCM_53570_A0)
  42409     { /* SOC_REG_INT_XLPMIB_RMDISr */
  42410         soc_block_list[16],
  42411         soc_portreg,
  42412         1,
  42413         0,
  42414         0x12700,
  42415         SOC_REG_FLAG_64_BITS |
  42416                           SOC_REG_FLAG_COUNTER,
  42417         0,
  42418         1,
  42419         soc_R1023_BCM53400_A0r_fields,
  42420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42421         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42422         322,
  42423         -1,
  42424     },
  42425 #endif /* chips */
  42426 
  42427 #if defined(BCM_53570_B0)
  42428     { /* SOC_REG_INT_XLPMIB_RMDIS_BCM53570_B0r */
  42429         soc_block_list[16],
  42430         soc_portreg,
  42431         1,
  42432         0,
  42433         0x12700,
  42434         SOC_REG_FLAG_64_BITS |
  42435                           SOC_REG_FLAG_COUNTER,
  42436         0,
  42437         1,
  42438         soc_R1023_BCM53400_A0r_fields,
  42439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42440         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42441         326,
  42442         -1,
  42443     },
  42444 #endif /* chips */
  42445 
  42446 #if defined(BCM_53570_A0)
  42447     { /* SOC_REG_INT_XLPMIB_RMFAEr */
  42448         soc_block_list[16],
  42449         soc_portreg,
  42450         1,
  42451         0,
  42452         0x12400,
  42453         SOC_REG_FLAG_64_BITS |
  42454                           SOC_REG_FLAG_COUNTER,
  42455         0,
  42456         1,
  42457         soc_R1023_BCM53400_A0r_fields,
  42458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42459         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42460         319,
  42461         -1,
  42462     },
  42463 #endif /* chips */
  42464 
  42465 #if defined(BCM_53570_B0)
  42466     { /* SOC_REG_INT_XLPMIB_RMFAE_BCM53570_B0r */
  42467         soc_block_list[16],
  42468         soc_portreg,
  42469         1,
  42470         0,
  42471         0x12400,
  42472         SOC_REG_FLAG_64_BITS |
  42473                           SOC_REG_FLAG_COUNTER,
  42474         0,
  42475         1,
  42476         soc_R1023_BCM53400_A0r_fields,
  42477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42478         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42479         323,
  42480         -1,
  42481     },
  42482 #endif /* chips */
  42483 
  42484 #if defined(BCM_53570_A0)
  42485     { /* SOC_REG_INT_XLPMIB_RMFAOr */
  42486         soc_block_list[16],
  42487         soc_portreg,
  42488         1,
  42489         0,
  42490         0x12500,
  42491         SOC_REG_FLAG_64_BITS |
  42492                           SOC_REG_FLAG_COUNTER,
  42493         0,
  42494         1,
  42495         soc_R1023_BCM53400_A0r_fields,
  42496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42497         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42498         320,
  42499         -1,
  42500     },
  42501 #endif /* chips */
  42502 
  42503 #if defined(BCM_53570_B0)
  42504     { /* SOC_REG_INT_XLPMIB_RMFAO_BCM53570_B0r */
  42505         soc_block_list[16],
  42506         soc_portreg,
  42507         1,
  42508         0,
  42509         0x12500,
  42510         SOC_REG_FLAG_64_BITS |
  42511                           SOC_REG_FLAG_COUNTER,
  42512         0,
  42513         1,
  42514         soc_R1023_BCM53400_A0r_fields,
  42515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42516         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42517         324,
  42518         -1,
  42519     },
  42520 #endif /* chips */
  42521 
  42522 #if defined(BCM_53570_A0)
  42523     { /* SOC_REG_INT_XLPMIB_RMFCr */
  42524         soc_block_list[16],
  42525         soc_portreg,
  42526         1,
  42527         0,
  42528         0x12600,
  42529         SOC_REG_FLAG_64_BITS |
  42530                           SOC_REG_FLAG_COUNTER,
  42531         0,
  42532         1,
  42533         soc_R1023_BCM53400_A0r_fields,
  42534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42535         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42536         321,
  42537         -1,
  42538     },
  42539 #endif /* chips */
  42540 
  42541 #if defined(BCM_53570_B0)
  42542     { /* SOC_REG_INT_XLPMIB_RMFC_BCM53570_B0r */
  42543         soc_block_list[16],
  42544         soc_portreg,
  42545         1,
  42546         0,
  42547         0x12600,
  42548         SOC_REG_FLAG_64_BITS |
  42549                           SOC_REG_FLAG_COUNTER,
  42550         0,
  42551         1,
  42552         soc_R1023_BCM53400_A0r_fields,
  42553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42554         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42555         325,
  42556         -1,
  42557     },
  42558 #endif /* chips */
  42559 
  42560 #if defined(BCM_53570_A0)
  42561     { /* SOC_REG_INT_XLPMIB_RMFSEr */
  42562         soc_block_list[16],
  42563         soc_portreg,
  42564         1,
  42565         0,
  42566         0x12300,
  42567         SOC_REG_FLAG_64_BITS |
  42568                           SOC_REG_FLAG_COUNTER,
  42569         0,
  42570         1,
  42571         soc_R1023_BCM53400_A0r_fields,
  42572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42573         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42574         318,
  42575         -1,
  42576     },
  42577 #endif /* chips */
  42578 
  42579 #if defined(BCM_53570_B0)
  42580     { /* SOC_REG_INT_XLPMIB_RMFSE_BCM53570_B0r */
  42581         soc_block_list[16],
  42582         soc_portreg,
  42583         1,
  42584         0,
  42585         0x12300,
  42586         SOC_REG_FLAG_64_BITS |
  42587                           SOC_REG_FLAG_COUNTER,
  42588         0,
  42589         1,
  42590         soc_R1023_BCM53400_A0r_fields,
  42591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42592         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42593         322,
  42594         -1,
  42595     },
  42596 #endif /* chips */
  42597 
  42598 #if defined(BCM_53570_A0)
  42599     { /* SOC_REG_INT_XLPMIB_RMGVr */
  42600         soc_block_list[16],
  42601         soc_portreg,
  42602         1,
  42603         0,
  42604         0x10600,
  42605         SOC_REG_FLAG_64_BITS |
  42606                           SOC_REG_FLAG_COUNTER,
  42607         0,
  42608         1,
  42609         soc_R1023_BCM53400_A0r_fields,
  42610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42612         289,
  42613         -1,
  42614     },
  42615 #endif /* chips */
  42616 
  42617 #if defined(BCM_53570_B0)
  42618     { /* SOC_REG_INT_XLPMIB_RMGV_BCM53570_B0r */
  42619         soc_block_list[16],
  42620         soc_portreg,
  42621         1,
  42622         0,
  42623         0x10600,
  42624         SOC_REG_FLAG_64_BITS |
  42625                           SOC_REG_FLAG_COUNTER,
  42626         0,
  42627         1,
  42628         soc_R1023_BCM53400_A0r_fields,
  42629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42630         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42631         293,
  42632         -1,
  42633     },
  42634 #endif /* chips */
  42635 
  42636 #if defined(BCM_53570_A0)
  42637     { /* SOC_REG_INT_XLPMIB_RMTUEr */
  42638         soc_block_list[16],
  42639         soc_portreg,
  42640         1,
  42641         0,
  42642         0x11c00,
  42643         SOC_REG_FLAG_64_BITS |
  42644                           SOC_REG_FLAG_COUNTER |
  42645                           SOC_REG_FLAG_ED_CNTR,
  42646         0,
  42647         1,
  42648         soc_R1023_BCM53400_A0r_fields,
  42649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42650         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42651         311,
  42652         -1,
  42653     },
  42654 #endif /* chips */
  42655 
  42656 #if defined(BCM_53570_B0)
  42657     { /* SOC_REG_INT_XLPMIB_RMTUE_BCM53570_B0r */
  42658         soc_block_list[16],
  42659         soc_portreg,
  42660         1,
  42661         0,
  42662         0x11c00,
  42663         SOC_REG_FLAG_64_BITS |
  42664                           SOC_REG_FLAG_COUNTER |
  42665                           SOC_REG_FLAG_ED_CNTR,
  42666         0,
  42667         1,
  42668         soc_R1023_BCM53400_A0r_fields,
  42669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42670         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42671         315,
  42672         -1,
  42673     },
  42674 #endif /* chips */
  42675 
  42676 #if defined(BCM_53570_A0)
  42677     { /* SOC_REG_INT_XLPMIB_RNFFMSEr */
  42678         soc_block_list[16],
  42679         soc_portreg,
  42680         1,
  42681         0,
  42682         0x12800,
  42683         SOC_REG_FLAG_64_BITS |
  42684                           SOC_REG_FLAG_COUNTER,
  42685         0,
  42686         1,
  42687         soc_R1023_BCM53400_A0r_fields,
  42688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42689         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42690         323,
  42691         -1,
  42692     },
  42693 #endif /* chips */
  42694 
  42695 #if defined(BCM_53570_B0)
  42696     { /* SOC_REG_INT_XLPMIB_RNFFMSE_BCM53570_B0r */
  42697         soc_block_list[16],
  42698         soc_portreg,
  42699         1,
  42700         0,
  42701         0x12800,
  42702         SOC_REG_FLAG_64_BITS |
  42703                           SOC_REG_FLAG_COUNTER,
  42704         0,
  42705         1,
  42706         soc_R1023_BCM53400_A0r_fields,
  42707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42708         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42709         327,
  42710         -1,
  42711     },
  42712 #endif /* chips */
  42713 
  42714 #if defined(BCM_53570_A0)
  42715     { /* SOC_REG_INT_XLPMIB_ROVRr */
  42716         soc_block_list[16],
  42717         soc_portreg,
  42718         1,
  42719         0,
  42720         0x11a00,
  42721         SOC_REG_FLAG_64_BITS |
  42722                           SOC_REG_FLAG_COUNTER |
  42723                           SOC_REG_FLAG_ED_CNTR,
  42724         0,
  42725         1,
  42726         soc_R1023_BCM53400_A0r_fields,
  42727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42728         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42729         309,
  42730         -1,
  42731     },
  42732 #endif /* chips */
  42733 
  42734 #if defined(BCM_53570_B0)
  42735     { /* SOC_REG_INT_XLPMIB_ROVR_BCM53570_B0r */
  42736         soc_block_list[16],
  42737         soc_portreg,
  42738         1,
  42739         0,
  42740         0x11a00,
  42741         SOC_REG_FLAG_64_BITS |
  42742                           SOC_REG_FLAG_COUNTER |
  42743                           SOC_REG_FLAG_ED_CNTR,
  42744         0,
  42745         1,
  42746         soc_R1023_BCM53400_A0r_fields,
  42747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42748         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42749         313,
  42750         -1,
  42751     },
  42752 #endif /* chips */
  42753 
  42754 #if defined(BCM_53570_A0)
  42755     { /* SOC_REG_INT_XLPMIB_RPFC0r */
  42756         soc_block_list[16],
  42757         soc_portreg,
  42758         1,
  42759         0,
  42760         0x12b00,
  42761         SOC_REG_FLAG_64_BITS |
  42762                           SOC_REG_FLAG_COUNTER,
  42763         0,
  42764         1,
  42765         soc_XLMIB_RSCHCRCr_fields,
  42766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42767         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42768         326,
  42769         -1,
  42770     },
  42771 #endif /* chips */
  42772 
  42773 #if defined(BCM_53570_A0)
  42774     { /* SOC_REG_INT_XLPMIB_RPFC1r */
  42775         soc_block_list[16],
  42776         soc_portreg,
  42777         1,
  42778         0,
  42779         0x12c00,
  42780         SOC_REG_FLAG_64_BITS |
  42781                           SOC_REG_FLAG_COUNTER,
  42782         0,
  42783         1,
  42784         soc_XLMIB_RSCHCRCr_fields,
  42785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42786         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42787         327,
  42788         -1,
  42789     },
  42790 #endif /* chips */
  42791 
  42792 #if defined(BCM_53570_A0)
  42793     { /* SOC_REG_INT_XLPMIB_RPFC2r */
  42794         soc_block_list[16],
  42795         soc_portreg,
  42796         1,
  42797         0,
  42798         0x12d00,
  42799         SOC_REG_FLAG_64_BITS |
  42800                           SOC_REG_FLAG_COUNTER,
  42801         0,
  42802         1,
  42803         soc_XLMIB_RSCHCRCr_fields,
  42804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42805         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42806         328,
  42807         -1,
  42808     },
  42809 #endif /* chips */
  42810 
  42811 #if defined(BCM_53570_A0)
  42812     { /* SOC_REG_INT_XLPMIB_RPFC3r */
  42813         soc_block_list[16],
  42814         soc_portreg,
  42815         1,
  42816         0,
  42817         0x12e00,
  42818         SOC_REG_FLAG_64_BITS |
  42819                           SOC_REG_FLAG_COUNTER,
  42820         0,
  42821         1,
  42822         soc_XLMIB_RSCHCRCr_fields,
  42823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42824         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42825         329,
  42826         -1,
  42827     },
  42828 #endif /* chips */
  42829 
  42830 #if defined(BCM_53570_A0)
  42831     { /* SOC_REG_INT_XLPMIB_RPFC4r */
  42832         soc_block_list[16],
  42833         soc_portreg,
  42834         1,
  42835         0,
  42836         0x12f00,
  42837         SOC_REG_FLAG_64_BITS |
  42838                           SOC_REG_FLAG_COUNTER,
  42839         0,
  42840         1,
  42841         soc_XLMIB_RSCHCRCr_fields,
  42842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42843         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42844         330,
  42845         -1,
  42846     },
  42847 #endif /* chips */
  42848 
  42849 #if defined(BCM_53570_A0)
  42850     { /* SOC_REG_INT_XLPMIB_RPFC5r */
  42851         soc_block_list[16],
  42852         soc_portreg,
  42853         1,
  42854         0,
  42855         0x13000,
  42856         SOC_REG_FLAG_64_BITS |
  42857                           SOC_REG_FLAG_COUNTER,
  42858         0,
  42859         1,
  42860         soc_XLMIB_RSCHCRCr_fields,
  42861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42862         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42863         331,
  42864         -1,
  42865     },
  42866 #endif /* chips */
  42867 
  42868 #if defined(BCM_53570_A0)
  42869     { /* SOC_REG_INT_XLPMIB_RPFC6r */
  42870         soc_block_list[16],
  42871         soc_portreg,
  42872         1,
  42873         0,
  42874         0x13100,
  42875         SOC_REG_FLAG_64_BITS |
  42876                           SOC_REG_FLAG_COUNTER,
  42877         0,
  42878         1,
  42879         soc_XLMIB_RSCHCRCr_fields,
  42880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42881         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42882         332,
  42883         -1,
  42884     },
  42885 #endif /* chips */
  42886 
  42887 #if defined(BCM_53570_A0)
  42888     { /* SOC_REG_INT_XLPMIB_RPFC7r */
  42889         soc_block_list[16],
  42890         soc_portreg,
  42891         1,
  42892         0,
  42893         0x13200,
  42894         SOC_REG_FLAG_64_BITS |
  42895                           SOC_REG_FLAG_COUNTER,
  42896         0,
  42897         1,
  42898         soc_XLMIB_RSCHCRCr_fields,
  42899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42900         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42901         333,
  42902         -1,
  42903     },
  42904 #endif /* chips */
  42905 
  42906 #if defined(BCM_53570_B0)
  42907     { /* SOC_REG_INT_XLPMIB_RPFC0_BCM53570_B0r */
  42908         soc_block_list[16],
  42909         soc_portreg,
  42910         1,
  42911         0,
  42912         0x12b00,
  42913         SOC_REG_FLAG_64_BITS |
  42914                           SOC_REG_FLAG_COUNTER,
  42915         0,
  42916         1,
  42917         soc_XLMIB_RSCHCRCr_fields,
  42918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42919         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42920         330,
  42921         -1,
  42922     },
  42923 #endif /* chips */
  42924 
  42925 #if defined(BCM_53570_B0)
  42926     { /* SOC_REG_INT_XLPMIB_RPFC1_BCM53570_B0r */
  42927         soc_block_list[16],
  42928         soc_portreg,
  42929         1,
  42930         0,
  42931         0x12c00,
  42932         SOC_REG_FLAG_64_BITS |
  42933                           SOC_REG_FLAG_COUNTER,
  42934         0,
  42935         1,
  42936         soc_XLMIB_RSCHCRCr_fields,
  42937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42938         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42939         331,
  42940         -1,
  42941     },
  42942 #endif /* chips */
  42943 
  42944 #if defined(BCM_53570_B0)
  42945     { /* SOC_REG_INT_XLPMIB_RPFC2_BCM53570_B0r */
  42946         soc_block_list[16],
  42947         soc_portreg,
  42948         1,
  42949         0,
  42950         0x12d00,
  42951         SOC_REG_FLAG_64_BITS |
  42952                           SOC_REG_FLAG_COUNTER,
  42953         0,
  42954         1,
  42955         soc_XLMIB_RSCHCRCr_fields,
  42956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42957         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42958         332,
  42959         -1,
  42960     },
  42961 #endif /* chips */
  42962 
  42963 #if defined(BCM_53570_B0)
  42964     { /* SOC_REG_INT_XLPMIB_RPFC3_BCM53570_B0r */
  42965         soc_block_list[16],
  42966         soc_portreg,
  42967         1,
  42968         0,
  42969         0x12e00,
  42970         SOC_REG_FLAG_64_BITS |
  42971                           SOC_REG_FLAG_COUNTER,
  42972         0,
  42973         1,
  42974         soc_XLMIB_RSCHCRCr_fields,
  42975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42976         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42977         333,
  42978         -1,
  42979     },
  42980 #endif /* chips */
  42981 
  42982 #if defined(BCM_53570_B0)
  42983     { /* SOC_REG_INT_XLPMIB_RPFC4_BCM53570_B0r */
  42984         soc_block_list[16],
  42985         soc_portreg,
  42986         1,
  42987         0,
  42988         0x12f00,
  42989         SOC_REG_FLAG_64_BITS |
  42990                           SOC_REG_FLAG_COUNTER,
  42991         0,
  42992         1,
  42993         soc_XLMIB_RSCHCRCr_fields,
  42994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42995         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  42996         334,
  42997         -1,
  42998     },
  42999 #endif /* chips */
  43000 
  43001 #if defined(BCM_53570_B0)
  43002     { /* SOC_REG_INT_XLPMIB_RPFC5_BCM53570_B0r */
  43003         soc_block_list[16],
  43004         soc_portreg,
  43005         1,
  43006         0,
  43007         0x13000,
  43008         SOC_REG_FLAG_64_BITS |
  43009                           SOC_REG_FLAG_COUNTER,
  43010         0,
  43011         1,
  43012         soc_XLMIB_RSCHCRCr_fields,
  43013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43014         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43015         335,
  43016         -1,
  43017     },
  43018 #endif /* chips */
  43019 
  43020 #if defined(BCM_53570_B0)
  43021     { /* SOC_REG_INT_XLPMIB_RPFC6_BCM53570_B0r */
  43022         soc_block_list[16],
  43023         soc_portreg,
  43024         1,
  43025         0,
  43026         0x13100,
  43027         SOC_REG_FLAG_64_BITS |
  43028                           SOC_REG_FLAG_COUNTER,
  43029         0,
  43030         1,
  43031         soc_XLMIB_RSCHCRCr_fields,
  43032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43033         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43034         336,
  43035         -1,
  43036     },
  43037 #endif /* chips */
  43038 
  43039 #if defined(BCM_53570_B0)
  43040     { /* SOC_REG_INT_XLPMIB_RPFC7_BCM53570_B0r */
  43041         soc_block_list[16],
  43042         soc_portreg,
  43043         1,
  43044         0,
  43045         0x13200,
  43046         SOC_REG_FLAG_64_BITS |
  43047                           SOC_REG_FLAG_COUNTER,
  43048         0,
  43049         1,
  43050         soc_XLMIB_RSCHCRCr_fields,
  43051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43052         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43053         337,
  43054         -1,
  43055     },
  43056 #endif /* chips */
  43057 
  43058 #if defined(BCM_53570_A0)
  43059     { /* SOC_REG_INT_XLPMIB_RPFCOFF7r */
  43060         soc_block_list[16],
  43061         soc_portreg,
  43062         1,
  43063         0,
  43064         0x12a00,
  43065         SOC_REG_FLAG_64_BITS |
  43066                           SOC_REG_FLAG_COUNTER,
  43067         0,
  43068         1,
  43069         soc_XLMIB_RSCHCRCr_fields,
  43070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43071         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43072         325,
  43073         -1,
  43074     },
  43075 #endif /* chips */
  43076 
  43077 #if defined(BCM_53570_B0)
  43078     { /* SOC_REG_INT_XLPMIB_RPFCOFF7_BCM53570_B0r */
  43079         soc_block_list[16],
  43080         soc_portreg,
  43081         1,
  43082         0,
  43083         0x12a00,
  43084         SOC_REG_FLAG_64_BITS |
  43085                           SOC_REG_FLAG_COUNTER,
  43086         0,
  43087         1,
  43088         soc_XLMIB_RSCHCRCr_fields,
  43089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43091         329,
  43092         -1,
  43093     },
  43094 #endif /* chips */
  43095 
  43096 #if defined(BCM_53570_A0)
  43097     { /* SOC_REG_INT_XLPMIB_RPKTr */
  43098         soc_block_list[16],
  43099         soc_portreg,
  43100         1,
  43101         0,
  43102         0x10b00,
  43103         SOC_REG_FLAG_64_BITS |
  43104                           SOC_REG_FLAG_COUNTER,
  43105         0,
  43106         1,
  43107         soc_R1023_BCM53400_A0r_fields,
  43108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43110         294,
  43111         -1,
  43112     },
  43113 #endif /* chips */
  43114 
  43115 #if defined(BCM_53570_B0)
  43116     { /* SOC_REG_INT_XLPMIB_RPKT_BCM53570_B0r */
  43117         soc_block_list[16],
  43118         soc_portreg,
  43119         1,
  43120         0,
  43121         0x10b00,
  43122         SOC_REG_FLAG_64_BITS |
  43123                           SOC_REG_FLAG_COUNTER,
  43124         0,
  43125         1,
  43126         soc_R1023_BCM53400_A0r_fields,
  43127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43128         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43129         298,
  43130         -1,
  43131     },
  43132 #endif /* chips */
  43133 
  43134 #if defined(BCM_53570_A0)
  43135     { /* SOC_REG_INT_XLPMIB_RPOKr */
  43136         soc_block_list[16],
  43137         soc_portreg,
  43138         1,
  43139         0,
  43140         0x12200,
  43141         SOC_REG_FLAG_64_BITS |
  43142                           SOC_REG_FLAG_COUNTER,
  43143         0,
  43144         1,
  43145         soc_R1023_BCM53400_A0r_fields,
  43146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43147         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43148         317,
  43149         -1,
  43150     },
  43151 #endif /* chips */
  43152 
  43153 #if defined(BCM_53570_B0)
  43154     { /* SOC_REG_INT_XLPMIB_RPOK_BCM53570_B0r */
  43155         soc_block_list[16],
  43156         soc_portreg,
  43157         1,
  43158         0,
  43159         0x12200,
  43160         SOC_REG_FLAG_64_BITS |
  43161                           SOC_REG_FLAG_COUNTER,
  43162         0,
  43163         1,
  43164         soc_R1023_BCM53400_A0r_fields,
  43165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43166         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43167         321,
  43168         -1,
  43169     },
  43170 #endif /* chips */
  43171 
  43172 #if defined(BCM_53570_A0)
  43173     { /* SOC_REG_INT_XLPMIB_RPRMr */
  43174         soc_block_list[16],
  43175         soc_portreg,
  43176         1,
  43177         0,
  43178         0x11e00,
  43179         SOC_REG_FLAG_64_BITS |
  43180                           SOC_REG_FLAG_COUNTER,
  43181         0,
  43182         1,
  43183         soc_R1023_BCM53400_A0r_fields,
  43184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43185         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43186         313,
  43187         -1,
  43188     },
  43189 #endif /* chips */
  43190 
  43191 #if defined(BCM_53570_B0)
  43192     { /* SOC_REG_INT_XLPMIB_RPRM_BCM53570_B0r */
  43193         soc_block_list[16],
  43194         soc_portreg,
  43195         1,
  43196         0,
  43197         0x11e00,
  43198         SOC_REG_FLAG_64_BITS |
  43199                           SOC_REG_FLAG_COUNTER,
  43200         0,
  43201         1,
  43202         soc_R1023_BCM53400_A0r_fields,
  43203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43204         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43205         317,
  43206         -1,
  43207     },
  43208 #endif /* chips */
  43209 
  43210 #if defined(BCM_53570_A0)
  43211     { /* SOC_REG_INT_XLPMIB_RPROG0r */
  43212         soc_block_list[16],
  43213         soc_portreg,
  43214         1,
  43215         0,
  43216         0x17500,
  43217         SOC_REG_FLAG_64_BITS |
  43218                           SOC_REG_FLAG_COUNTER,
  43219         0,
  43220         1,
  43221         soc_R1023_BCM53400_A0r_fields,
  43222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43223         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43224         400,
  43225         -1,
  43226     },
  43227 #endif /* chips */
  43228 
  43229 #if defined(BCM_53570_A0)
  43230     { /* SOC_REG_INT_XLPMIB_RPROG1r */
  43231         soc_block_list[16],
  43232         soc_portreg,
  43233         1,
  43234         0,
  43235         0x17600,
  43236         SOC_REG_FLAG_64_BITS |
  43237                           SOC_REG_FLAG_COUNTER,
  43238         0,
  43239         1,
  43240         soc_R1023_BCM53400_A0r_fields,
  43241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43242         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43243         401,
  43244         -1,
  43245     },
  43246 #endif /* chips */
  43247 
  43248 #if defined(BCM_53570_A0)
  43249     { /* SOC_REG_INT_XLPMIB_RPROG2r */
  43250         soc_block_list[16],
  43251         soc_portreg,
  43252         1,
  43253         0,
  43254         0x17700,
  43255         SOC_REG_FLAG_64_BITS |
  43256                           SOC_REG_FLAG_COUNTER,
  43257         0,
  43258         1,
  43259         soc_R1023_BCM53400_A0r_fields,
  43260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43261         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43262         402,
  43263         -1,
  43264     },
  43265 #endif /* chips */
  43266 
  43267 #if defined(BCM_53570_A0)
  43268     { /* SOC_REG_INT_XLPMIB_RPROG3r */
  43269         soc_block_list[16],
  43270         soc_portreg,
  43271         1,
  43272         0,
  43273         0x17800,
  43274         SOC_REG_FLAG_64_BITS |
  43275                           SOC_REG_FLAG_COUNTER,
  43276         0,
  43277         1,
  43278         soc_R1023_BCM53400_A0r_fields,
  43279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43280         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43281         403,
  43282         -1,
  43283     },
  43284 #endif /* chips */
  43285 
  43286 #if defined(BCM_53570_B0)
  43287     { /* SOC_REG_INT_XLPMIB_RPROG0_BCM53570_B0r */
  43288         soc_block_list[16],
  43289         soc_portreg,
  43290         1,
  43291         0,
  43292         0x17500,
  43293         SOC_REG_FLAG_64_BITS |
  43294                           SOC_REG_FLAG_COUNTER,
  43295         0,
  43296         1,
  43297         soc_R1023_BCM53400_A0r_fields,
  43298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43300         404,
  43301         -1,
  43302     },
  43303 #endif /* chips */
  43304 
  43305 #if defined(BCM_53570_B0)
  43306     { /* SOC_REG_INT_XLPMIB_RPROG1_BCM53570_B0r */
  43307         soc_block_list[16],
  43308         soc_portreg,
  43309         1,
  43310         0,
  43311         0x17600,
  43312         SOC_REG_FLAG_64_BITS |
  43313                           SOC_REG_FLAG_COUNTER,
  43314         0,
  43315         1,
  43316         soc_R1023_BCM53400_A0r_fields,
  43317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43318         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43319         405,
  43320         -1,
  43321     },
  43322 #endif /* chips */
  43323 
  43324 #if defined(BCM_53570_B0)
  43325     { /* SOC_REG_INT_XLPMIB_RPROG2_BCM53570_B0r */
  43326         soc_block_list[16],
  43327         soc_portreg,
  43328         1,
  43329         0,
  43330         0x17700,
  43331         SOC_REG_FLAG_64_BITS |
  43332                           SOC_REG_FLAG_COUNTER,
  43333         0,
  43334         1,
  43335         soc_R1023_BCM53400_A0r_fields,
  43336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43337         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43338         406,
  43339         -1,
  43340     },
  43341 #endif /* chips */
  43342 
  43343 #if defined(BCM_53570_B0)
  43344     { /* SOC_REG_INT_XLPMIB_RPROG3_BCM53570_B0r */
  43345         soc_block_list[16],
  43346         soc_portreg,
  43347         1,
  43348         0,
  43349         0x17800,
  43350         SOC_REG_FLAG_64_BITS |
  43351                           SOC_REG_FLAG_COUNTER,
  43352         0,
  43353         1,
  43354         soc_R1023_BCM53400_A0r_fields,
  43355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43357         407,
  43358         -1,
  43359     },
  43360 #endif /* chips */
  43361 
  43362 #if defined(BCM_53570_A0)
  43363     { /* SOC_REG_INT_XLPMIB_RRBYTr */
  43364         soc_block_list[16],
  43365         soc_portreg,
  43366         1,
  43367         0,
  43368         0x13e00,
  43369         SOC_REG_FLAG_64_BITS |
  43370                           SOC_REG_FLAG_COUNTER |
  43371                           SOC_REG_FLAG_ED_CNTR,
  43372         0,
  43373         1,
  43374         soc_RBYT_BCM53400_A0r_fields,
  43375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43376         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43377         345,
  43378         -1,
  43379     },
  43380 #endif /* chips */
  43381 
  43382 #if defined(BCM_53570_B0)
  43383     { /* SOC_REG_INT_XLPMIB_RRBYT_BCM53570_B0r */
  43384         soc_block_list[16],
  43385         soc_portreg,
  43386         1,
  43387         0,
  43388         0x13e00,
  43389         SOC_REG_FLAG_64_BITS |
  43390                           SOC_REG_FLAG_COUNTER |
  43391                           SOC_REG_FLAG_ED_CNTR,
  43392         0,
  43393         1,
  43394         soc_RBYT_BCM53400_A0r_fields,
  43395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43396         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43397         349,
  43398         -1,
  43399     },
  43400 #endif /* chips */
  43401 
  43402 #if defined(BCM_53570_A0)
  43403     { /* SOC_REG_INT_XLPMIB_RRPKTr */
  43404         soc_block_list[16],
  43405         soc_portreg,
  43406         1,
  43407         0,
  43408         0x13f00,
  43409         SOC_REG_FLAG_64_BITS |
  43410                           SOC_REG_FLAG_COUNTER |
  43411                           SOC_REG_FLAG_ED_CNTR,
  43412         0,
  43413         1,
  43414         soc_R1023_BCM53400_A0r_fields,
  43415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43416         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43417         346,
  43418         -1,
  43419     },
  43420 #endif /* chips */
  43421 
  43422 #if defined(BCM_53570_B0)
  43423     { /* SOC_REG_INT_XLPMIB_RRPKT_BCM53570_B0r */
  43424         soc_block_list[16],
  43425         soc_portreg,
  43426         1,
  43427         0,
  43428         0x13f00,
  43429         SOC_REG_FLAG_64_BITS |
  43430                           SOC_REG_FLAG_COUNTER |
  43431                           SOC_REG_FLAG_ED_CNTR,
  43432         0,
  43433         1,
  43434         soc_R1023_BCM53400_A0r_fields,
  43435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43436         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43437         350,
  43438         -1,
  43439     },
  43440 #endif /* chips */
  43441 
  43442 #if defined(BCM_53570_A0)
  43443     { /* SOC_REG_INT_XLPMIB_RSCHCRCr */
  43444         soc_block_list[16],
  43445         soc_portreg,
  43446         1,
  43447         0,
  43448         0x13300,
  43449         SOC_REG_FLAG_64_BITS |
  43450                           SOC_REG_FLAG_COUNTER,
  43451         0,
  43452         1,
  43453         soc_XLMIB_RSCHCRCr_fields,
  43454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43455         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43456         334,
  43457         -1,
  43458     },
  43459 #endif /* chips */
  43460 
  43461 #if defined(BCM_53570_B0)
  43462     { /* SOC_REG_INT_XLPMIB_RSCHCRC_BCM53570_B0r */
  43463         soc_block_list[16],
  43464         soc_portreg,
  43465         1,
  43466         0,
  43467         0x13300,
  43468         SOC_REG_FLAG_64_BITS |
  43469                           SOC_REG_FLAG_COUNTER,
  43470         0,
  43471         1,
  43472         soc_XLMIB_RSCHCRCr_fields,
  43473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43474         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43475         338,
  43476         -1,
  43477     },
  43478 #endif /* chips */
  43479 
  43480 #if defined(BCM_53570_A0)
  43481     { /* SOC_REG_INT_XLPMIB_RTRFUr */
  43482         soc_block_list[16],
  43483         soc_portreg,
  43484         1,
  43485         0,
  43486         0x12100,
  43487         SOC_REG_FLAG_64_BITS |
  43488                           SOC_REG_FLAG_COUNTER,
  43489         0,
  43490         1,
  43491         soc_R1023_BCM53400_A0r_fields,
  43492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43493         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43494         316,
  43495         -1,
  43496     },
  43497 #endif /* chips */
  43498 
  43499 #if defined(BCM_53570_B0)
  43500     { /* SOC_REG_INT_XLPMIB_RTRFU_BCM53570_B0r */
  43501         soc_block_list[16],
  43502         soc_portreg,
  43503         1,
  43504         0,
  43505         0x12100,
  43506         SOC_REG_FLAG_64_BITS |
  43507                           SOC_REG_FLAG_COUNTER,
  43508         0,
  43509         1,
  43510         soc_R1023_BCM53400_A0r_fields,
  43511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43512         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43513         320,
  43514         -1,
  43515     },
  43516 #endif /* chips */
  43517 
  43518 #if defined(BCM_53570_A0)
  43519     { /* SOC_REG_INT_XLPMIB_RUCAr */
  43520         soc_block_list[16],
  43521         soc_portreg,
  43522         1,
  43523         0,
  43524         0x10c00,
  43525         SOC_REG_FLAG_64_BITS |
  43526                           SOC_REG_FLAG_COUNTER,
  43527         0,
  43528         1,
  43529         soc_R1023_BCM53400_A0r_fields,
  43530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43531         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43532         295,
  43533         -1,
  43534     },
  43535 #endif /* chips */
  43536 
  43537 #if defined(BCM_53570_B0)
  43538     { /* SOC_REG_INT_XLPMIB_RUCA_BCM53570_B0r */
  43539         soc_block_list[16],
  43540         soc_portreg,
  43541         1,
  43542         0,
  43543         0x10c00,
  43544         SOC_REG_FLAG_64_BITS |
  43545                           SOC_REG_FLAG_COUNTER,
  43546         0,
  43547         1,
  43548         soc_R1023_BCM53400_A0r_fields,
  43549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43550         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43551         299,
  43552         -1,
  43553     },
  43554 #endif /* chips */
  43555 
  43556 #if defined(BCM_53570_A0)
  43557     { /* SOC_REG_INT_XLPMIB_RUNDr */
  43558         soc_block_list[16],
  43559         soc_portreg,
  43560         1,
  43561         0,
  43562         0x13400,
  43563         SOC_REG_FLAG_64_BITS |
  43564                           SOC_REG_FLAG_COUNTER |
  43565                           SOC_REG_FLAG_ED_CNTR,
  43566         0,
  43567         1,
  43568         soc_R1023_BCM53400_A0r_fields,
  43569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43570         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43571         335,
  43572         -1,
  43573     },
  43574 #endif /* chips */
  43575 
  43576 #if defined(BCM_53570_B0)
  43577     { /* SOC_REG_INT_XLPMIB_RUND_BCM53570_B0r */
  43578         soc_block_list[16],
  43579         soc_portreg,
  43580         1,
  43581         0,
  43582         0x13400,
  43583         SOC_REG_FLAG_64_BITS |
  43584                           SOC_REG_FLAG_COUNTER |
  43585                           SOC_REG_FLAG_ED_CNTR,
  43586         0,
  43587         1,
  43588         soc_R1023_BCM53400_A0r_fields,
  43589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43590         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43591         339,
  43592         -1,
  43593     },
  43594 #endif /* chips */
  43595 
  43596 #if defined(BCM_53570_A0)
  43597     { /* SOC_REG_INT_XLPMIB_RVLNr */
  43598         soc_block_list[16],
  43599         soc_portreg,
  43600         1,
  43601         0,
  43602         0x11f00,
  43603         SOC_REG_FLAG_64_BITS |
  43604                           SOC_REG_FLAG_COUNTER,
  43605         0,
  43606         1,
  43607         soc_R1023_BCM53400_A0r_fields,
  43608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43609         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43610         314,
  43611         -1,
  43612     },
  43613 #endif /* chips */
  43614 
  43615 #if defined(BCM_53570_B0)
  43616     { /* SOC_REG_INT_XLPMIB_RVLN_BCM53570_B0r */
  43617         soc_block_list[16],
  43618         soc_portreg,
  43619         1,
  43620         0,
  43621         0x11f00,
  43622         SOC_REG_FLAG_64_BITS |
  43623                           SOC_REG_FLAG_COUNTER,
  43624         0,
  43625         1,
  43626         soc_R1023_BCM53400_A0r_fields,
  43627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43628         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43629         318,
  43630         -1,
  43631     },
  43632 #endif /* chips */
  43633 
  43634 #if defined(BCM_53570_A0)
  43635     { /* SOC_REG_INT_XLPMIB_RXCFr */
  43636         soc_block_list[16],
  43637         soc_portreg,
  43638         1,
  43639         0,
  43640         0x11000,
  43641         SOC_REG_FLAG_64_BITS |
  43642                           SOC_REG_FLAG_COUNTER,
  43643         0,
  43644         1,
  43645         soc_XLMIB_RSCHCRCr_fields,
  43646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43647         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43648         299,
  43649         -1,
  43650     },
  43651 #endif /* chips */
  43652 
  43653 #if defined(BCM_53570_B0)
  43654     { /* SOC_REG_INT_XLPMIB_RXCF_BCM53570_B0r */
  43655         soc_block_list[16],
  43656         soc_portreg,
  43657         1,
  43658         0,
  43659         0x11000,
  43660         SOC_REG_FLAG_64_BITS |
  43661                           SOC_REG_FLAG_COUNTER,
  43662         0,
  43663         1,
  43664         soc_XLMIB_RSCHCRCr_fields,
  43665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43666         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43667         303,
  43668         -1,
  43669     },
  43670 #endif /* chips */
  43671 
  43672 #if defined(BCM_53570_A0)
  43673     { /* SOC_REG_INT_XLPMIB_RXPFr */
  43674         soc_block_list[16],
  43675         soc_portreg,
  43676         1,
  43677         0,
  43678         0x11100,
  43679         SOC_REG_FLAG_64_BITS |
  43680                           SOC_REG_FLAG_COUNTER,
  43681         0,
  43682         1,
  43683         soc_XLMIB_RSCHCRCr_fields,
  43684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43685         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43686         300,
  43687         -1,
  43688     },
  43689 #endif /* chips */
  43690 
  43691 #if defined(BCM_53570_B0)
  43692     { /* SOC_REG_INT_XLPMIB_RXPF_BCM53570_B0r */
  43693         soc_block_list[16],
  43694         soc_portreg,
  43695         1,
  43696         0,
  43697         0x11100,
  43698         SOC_REG_FLAG_64_BITS |
  43699                           SOC_REG_FLAG_COUNTER,
  43700         0,
  43701         1,
  43702         soc_XLMIB_RSCHCRCr_fields,
  43703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43704         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43705         304,
  43706         -1,
  43707     },
  43708 #endif /* chips */
  43709 
  43710 #if defined(BCM_53570_A0)
  43711     { /* SOC_REG_INT_XLPMIB_RXPPr */
  43712         soc_block_list[16],
  43713         soc_portreg,
  43714         1,
  43715         0,
  43716         0x11200,
  43717         SOC_REG_FLAG_64_BITS |
  43718                           SOC_REG_FLAG_COUNTER,
  43719         0,
  43720         1,
  43721         soc_XLMIB_RSCHCRCr_fields,
  43722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43723         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43724         301,
  43725         -1,
  43726     },
  43727 #endif /* chips */
  43728 
  43729 #if defined(BCM_53570_B0)
  43730     { /* SOC_REG_INT_XLPMIB_RXPP_BCM53570_B0r */
  43731         soc_block_list[16],
  43732         soc_portreg,
  43733         1,
  43734         0,
  43735         0x11200,
  43736         SOC_REG_FLAG_64_BITS |
  43737                           SOC_REG_FLAG_COUNTER,
  43738         0,
  43739         1,
  43740         soc_XLMIB_RSCHCRCr_fields,
  43741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43742         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43743         305,
  43744         -1,
  43745     },
  43746 #endif /* chips */
  43747 
  43748 #if defined(BCM_53570_A0)
  43749     { /* SOC_REG_INT_XLPMIB_RXUDAr */
  43750         soc_block_list[16],
  43751         soc_portreg,
  43752         1,
  43753         0,
  43754         0x11400,
  43755         SOC_REG_FLAG_64_BITS |
  43756                           SOC_REG_FLAG_COUNTER,
  43757         0,
  43758         1,
  43759         soc_XLMIB_RSCHCRCr_fields,
  43760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43762         303,
  43763         -1,
  43764     },
  43765 #endif /* chips */
  43766 
  43767 #if defined(BCM_53570_B0)
  43768     { /* SOC_REG_INT_XLPMIB_RXUDA_BCM53570_B0r */
  43769         soc_block_list[16],
  43770         soc_portreg,
  43771         1,
  43772         0,
  43773         0x11400,
  43774         SOC_REG_FLAG_64_BITS |
  43775                           SOC_REG_FLAG_COUNTER,
  43776         0,
  43777         1,
  43778         soc_XLMIB_RSCHCRCr_fields,
  43779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43780         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43781         307,
  43782         -1,
  43783     },
  43784 #endif /* chips */
  43785 
  43786 #if defined(BCM_53570_A0)
  43787     { /* SOC_REG_INT_XLPMIB_RXUOr */
  43788         soc_block_list[16],
  43789         soc_portreg,
  43790         1,
  43791         0,
  43792         0x11300,
  43793         SOC_REG_FLAG_64_BITS |
  43794                           SOC_REG_FLAG_COUNTER,
  43795         0,
  43796         1,
  43797         soc_RALN_BCM53400_A0r_fields,
  43798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43799         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43800         302,
  43801         -1,
  43802     },
  43803 #endif /* chips */
  43804 
  43805 #if defined(BCM_53570_B0)
  43806     { /* SOC_REG_INT_XLPMIB_RXUO_BCM53570_B0r */
  43807         soc_block_list[16],
  43808         soc_portreg,
  43809         1,
  43810         0,
  43811         0x11300,
  43812         SOC_REG_FLAG_64_BITS |
  43813                           SOC_REG_FLAG_COUNTER,
  43814         0,
  43815         1,
  43816         soc_RALN_BCM53400_A0r_fields,
  43817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43818         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43819         306,
  43820         -1,
  43821     },
  43822 #endif /* chips */
  43823 
  43824 #if defined(BCM_53570_A0)
  43825     { /* SOC_REG_INT_XLPMIB_RXWSAr */
  43826         soc_block_list[16],
  43827         soc_portreg,
  43828         1,
  43829         0,
  43830         0x11500,
  43831         SOC_REG_FLAG_64_BITS |
  43832                           SOC_REG_FLAG_COUNTER,
  43833         0,
  43834         1,
  43835         soc_R1023_BCM53400_A0r_fields,
  43836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43837         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43838         304,
  43839         -1,
  43840     },
  43841 #endif /* chips */
  43842 
  43843 #if defined(BCM_53570_B0)
  43844     { /* SOC_REG_INT_XLPMIB_RXWSA_BCM53570_B0r */
  43845         soc_block_list[16],
  43846         soc_portreg,
  43847         1,
  43848         0,
  43849         0x11500,
  43850         SOC_REG_FLAG_64_BITS |
  43851                           SOC_REG_FLAG_COUNTER,
  43852         0,
  43853         1,
  43854         soc_R1023_BCM53400_A0r_fields,
  43855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43856         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43857         308,
  43858         -1,
  43859     },
  43860 #endif /* chips */
  43861 
  43862 #if defined(BCM_53570_A0)
  43863     { /* SOC_REG_INT_XLPMIB_RX_EEE_LPI_DURATION_COUNTERr */
  43864         soc_block_list[16],
  43865         soc_portreg,
  43866         1,
  43867         0,
  43868         0x13700,
  43869         SOC_REG_FLAG_64_BITS |
  43870                           SOC_REG_FLAG_COUNTER,
  43871         0,
  43872         1,
  43873         soc_RALN_BCM53400_A0r_fields,
  43874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43875         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43876         338,
  43877         -1,
  43878     },
  43879 #endif /* chips */
  43880 
  43881 #if defined(BCM_53570_B0)
  43882     { /* SOC_REG_INT_XLPMIB_RX_EEE_LPI_DURATION_COUNTER_BCM53570_B0r */
  43883         soc_block_list[16],
  43884         soc_portreg,
  43885         1,
  43886         0,
  43887         0x13700,
  43888         SOC_REG_FLAG_64_BITS |
  43889                           SOC_REG_FLAG_COUNTER,
  43890         0,
  43891         1,
  43892         soc_RALN_BCM53400_A0r_fields,
  43893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43894         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43895         342,
  43896         -1,
  43897     },
  43898 #endif /* chips */
  43899 
  43900 #if defined(BCM_53570_A0)
  43901     { /* SOC_REG_INT_XLPMIB_RX_EEE_LPI_EVENT_COUNTERr */
  43902         soc_block_list[16],
  43903         soc_portreg,
  43904         1,
  43905         0,
  43906         0x13600,
  43907         SOC_REG_FLAG_64_BITS |
  43908                           SOC_REG_FLAG_COUNTER,
  43909         0,
  43910         1,
  43911         soc_RALN_BCM53400_A0r_fields,
  43912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43913         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43914         337,
  43915         -1,
  43916     },
  43917 #endif /* chips */
  43918 
  43919 #if defined(BCM_53570_B0)
  43920     { /* SOC_REG_INT_XLPMIB_RX_EEE_LPI_EVENT_COUNTER_BCM53570_B0r */
  43921         soc_block_list[16],
  43922         soc_portreg,
  43923         1,
  43924         0,
  43925         0x13600,
  43926         SOC_REG_FLAG_64_BITS |
  43927                           SOC_REG_FLAG_COUNTER,
  43928         0,
  43929         1,
  43930         soc_RALN_BCM53400_A0r_fields,
  43931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43932         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43933         341,
  43934         -1,
  43935     },
  43936 #endif /* chips */
  43937 
  43938 #if defined(BCM_53570_A0)
  43939     { /* SOC_REG_INT_XLPMIB_RX_HCFC_COUNTERr */
  43940         soc_block_list[16],
  43941         soc_portreg,
  43942         1,
  43943         0,
  43944         0x13b00,
  43945         SOC_REG_FLAG_64_BITS |
  43946                           SOC_REG_FLAG_COUNTER,
  43947         0,
  43948         1,
  43949         soc_XLMIB_RSCHCRCr_fields,
  43950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43952         342,
  43953         -1,
  43954     },
  43955 #endif /* chips */
  43956 
  43957 #if defined(BCM_53570_B0)
  43958     { /* SOC_REG_INT_XLPMIB_RX_HCFC_COUNTER_BCM53570_B0r */
  43959         soc_block_list[16],
  43960         soc_portreg,
  43961         1,
  43962         0,
  43963         0x13b00,
  43964         SOC_REG_FLAG_64_BITS |
  43965                           SOC_REG_FLAG_COUNTER,
  43966         0,
  43967         1,
  43968         soc_XLMIB_RSCHCRCr_fields,
  43969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43970         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43971         346,
  43972         -1,
  43973     },
  43974 #endif /* chips */
  43975 
  43976 #if defined(BCM_53570_A0)
  43977     { /* SOC_REG_INT_XLPMIB_RX_HCFC_CRC_COUNTERr */
  43978         soc_block_list[16],
  43979         soc_portreg,
  43980         1,
  43981         0,
  43982         0x13c00,
  43983         SOC_REG_FLAG_64_BITS |
  43984                           SOC_REG_FLAG_COUNTER,
  43985         0,
  43986         1,
  43987         soc_XLMIB_RSCHCRCr_fields,
  43988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  43990         343,
  43991         -1,
  43992     },
  43993 #endif /* chips */
  43994 
  43995 #if defined(BCM_53570_B0)
  43996     { /* SOC_REG_INT_XLPMIB_RX_HCFC_CRC_COUNTER_BCM53570_B0r */
  43997         soc_block_list[16],
  43998         soc_portreg,
  43999         1,
  44000         0,
  44001         0x13c00,
  44002         SOC_REG_FLAG_64_BITS |
  44003                           SOC_REG_FLAG_COUNTER,
  44004         0,
  44005         1,
  44006         soc_XLMIB_RSCHCRCr_fields,
  44007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44008         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44009         347,
  44010         -1,
  44011     },
  44012 #endif /* chips */
  44013 
  44014 #if defined(BCM_53570_A0)
  44015     { /* SOC_REG_INT_XLPMIB_RX_LLFC_CRC_COUNTERr */
  44016         soc_block_list[16],
  44017         soc_portreg,
  44018         1,
  44019         0,
  44020         0x13a00,
  44021         SOC_REG_FLAG_64_BITS |
  44022                           SOC_REG_FLAG_COUNTER,
  44023         0,
  44024         1,
  44025         soc_RALN_BCM53400_A0r_fields,
  44026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44027         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44028         341,
  44029         -1,
  44030     },
  44031 #endif /* chips */
  44032 
  44033 #if defined(BCM_53570_B0)
  44034     { /* SOC_REG_INT_XLPMIB_RX_LLFC_CRC_COUNTER_BCM53570_B0r */
  44035         soc_block_list[16],
  44036         soc_portreg,
  44037         1,
  44038         0,
  44039         0x13a00,
  44040         SOC_REG_FLAG_64_BITS |
  44041                           SOC_REG_FLAG_COUNTER,
  44042         0,
  44043         1,
  44044         soc_RALN_BCM53400_A0r_fields,
  44045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44046         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44047         345,
  44048         -1,
  44049     },
  44050 #endif /* chips */
  44051 
  44052 #if defined(BCM_53570_A0)
  44053     { /* SOC_REG_INT_XLPMIB_RX_LLFC_LOG_COUNTERr */
  44054         soc_block_list[16],
  44055         soc_portreg,
  44056         1,
  44057         0,
  44058         0x13900,
  44059         SOC_REG_FLAG_64_BITS |
  44060                           SOC_REG_FLAG_COUNTER,
  44061         0,
  44062         1,
  44063         soc_RALN_BCM53400_A0r_fields,
  44064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44065         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44066         340,
  44067         -1,
  44068     },
  44069 #endif /* chips */
  44070 
  44071 #if defined(BCM_53570_B0)
  44072     { /* SOC_REG_INT_XLPMIB_RX_LLFC_LOG_COUNTER_BCM53570_B0r */
  44073         soc_block_list[16],
  44074         soc_portreg,
  44075         1,
  44076         0,
  44077         0x13900,
  44078         SOC_REG_FLAG_64_BITS |
  44079                           SOC_REG_FLAG_COUNTER,
  44080         0,
  44081         1,
  44082         soc_RALN_BCM53400_A0r_fields,
  44083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44084         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44085         344,
  44086         -1,
  44087     },
  44088 #endif /* chips */
  44089 
  44090 #if defined(BCM_53570_A0)
  44091     { /* SOC_REG_INT_XLPMIB_RX_LLFC_PHY_COUNTERr */
  44092         soc_block_list[16],
  44093         soc_portreg,
  44094         1,
  44095         0,
  44096         0x13800,
  44097         SOC_REG_FLAG_64_BITS |
  44098                           SOC_REG_FLAG_COUNTER,
  44099         0,
  44100         1,
  44101         soc_RALN_BCM53400_A0r_fields,
  44102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44103         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44104         339,
  44105         -1,
  44106     },
  44107 #endif /* chips */
  44108 
  44109 #if defined(BCM_53570_B0)
  44110     { /* SOC_REG_INT_XLPMIB_RX_LLFC_PHY_COUNTER_BCM53570_B0r */
  44111         soc_block_list[16],
  44112         soc_portreg,
  44113         1,
  44114         0,
  44115         0x13800,
  44116         SOC_REG_FLAG_64_BITS |
  44117                           SOC_REG_FLAG_COUNTER,
  44118         0,
  44119         1,
  44120         soc_RALN_BCM53400_A0r_fields,
  44121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44122         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44123         343,
  44124         -1,
  44125     },
  44126 #endif /* chips */
  44127 
  44128 #if defined(BCM_53570_A0)
  44129     { /* SOC_REG_INT_XLPMIB_T64r */
  44130         soc_block_list[16],
  44131         soc_portreg,
  44132         1,
  44133         0,
  44134         0x14000,
  44135         SOC_REG_FLAG_64_BITS |
  44136                           SOC_REG_FLAG_COUNTER,
  44137         0,
  44138         1,
  44139         soc_R1023_BCM53400_A0r_fields,
  44140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44141         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44142         347,
  44143         -1,
  44144     },
  44145 #endif /* chips */
  44146 
  44147 #if defined(BCM_53570_A0)
  44148     { /* SOC_REG_INT_XLPMIB_T127r */
  44149         soc_block_list[16],
  44150         soc_portreg,
  44151         1,
  44152         0,
  44153         0x14100,
  44154         SOC_REG_FLAG_64_BITS |
  44155                           SOC_REG_FLAG_COUNTER,
  44156         0,
  44157         1,
  44158         soc_R1023_BCM53400_A0r_fields,
  44159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44160         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44161         348,
  44162         -1,
  44163     },
  44164 #endif /* chips */
  44165 
  44166 #if defined(BCM_53570_A0)
  44167     { /* SOC_REG_INT_XLPMIB_T255r */
  44168         soc_block_list[16],
  44169         soc_portreg,
  44170         1,
  44171         0,
  44172         0x14200,
  44173         SOC_REG_FLAG_64_BITS |
  44174                           SOC_REG_FLAG_COUNTER,
  44175         0,
  44176         1,
  44177         soc_R1023_BCM53400_A0r_fields,
  44178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44179         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44180         349,
  44181         -1,
  44182     },
  44183 #endif /* chips */
  44184 
  44185 #if defined(BCM_53570_A0)
  44186     { /* SOC_REG_INT_XLPMIB_T511r */
  44187         soc_block_list[16],
  44188         soc_portreg,
  44189         1,
  44190         0,
  44191         0x14300,
  44192         SOC_REG_FLAG_64_BITS |
  44193                           SOC_REG_FLAG_COUNTER,
  44194         0,
  44195         1,
  44196         soc_R1023_BCM53400_A0r_fields,
  44197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44198         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44199         350,
  44200         -1,
  44201     },
  44202 #endif /* chips */
  44203 
  44204 #if defined(BCM_53570_A0)
  44205     { /* SOC_REG_INT_XLPMIB_T1023r */
  44206         soc_block_list[16],
  44207         soc_portreg,
  44208         1,
  44209         0,
  44210         0x14400,
  44211         SOC_REG_FLAG_64_BITS |
  44212                           SOC_REG_FLAG_COUNTER,
  44213         0,
  44214         1,
  44215         soc_R1023_BCM53400_A0r_fields,
  44216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44217         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44218         351,
  44219         -1,
  44220     },
  44221 #endif /* chips */
  44222 
  44223 #if defined(BCM_53570_A0)
  44224     { /* SOC_REG_INT_XLPMIB_T1518r */
  44225         soc_block_list[16],
  44226         soc_portreg,
  44227         1,
  44228         0,
  44229         0x14500,
  44230         SOC_REG_FLAG_64_BITS |
  44231                           SOC_REG_FLAG_COUNTER,
  44232         0,
  44233         1,
  44234         soc_R1023_BCM53400_A0r_fields,
  44235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44236         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44237         352,
  44238         -1,
  44239     },
  44240 #endif /* chips */
  44241 
  44242 #if defined(BCM_53570_A0)
  44243     { /* SOC_REG_INT_XLPMIB_T2047r */
  44244         soc_block_list[16],
  44245         soc_portreg,
  44246         1,
  44247         0,
  44248         0x14700,
  44249         SOC_REG_FLAG_64_BITS |
  44250                           SOC_REG_FLAG_COUNTER,
  44251         0,
  44252         1,
  44253         soc_R1023_BCM53400_A0r_fields,
  44254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44255         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44256         354,
  44257         -1,
  44258     },
  44259 #endif /* chips */
  44260 
  44261 #if defined(BCM_53570_A0)
  44262     { /* SOC_REG_INT_XLPMIB_T4095r */
  44263         soc_block_list[16],
  44264         soc_portreg,
  44265         1,
  44266         0,
  44267         0x14800,
  44268         SOC_REG_FLAG_64_BITS |
  44269                           SOC_REG_FLAG_COUNTER,
  44270         0,
  44271         1,
  44272         soc_R1023_BCM53400_A0r_fields,
  44273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44274         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44275         355,
  44276         -1,
  44277     },
  44278 #endif /* chips */
  44279 
  44280 #if defined(BCM_53570_A0)
  44281     { /* SOC_REG_INT_XLPMIB_T9216r */
  44282         soc_block_list[16],
  44283         soc_portreg,
  44284         1,
  44285         0,
  44286         0x14900,
  44287         SOC_REG_FLAG_64_BITS |
  44288                           SOC_REG_FLAG_COUNTER,
  44289         0,
  44290         1,
  44291         soc_R1023_BCM53400_A0r_fields,
  44292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44293         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44294         356,
  44295         -1,
  44296     },
  44297 #endif /* chips */
  44298 
  44299 #if defined(BCM_53570_A0)
  44300     { /* SOC_REG_INT_XLPMIB_T16383r */
  44301         soc_block_list[16],
  44302         soc_portreg,
  44303         1,
  44304         0,
  44305         0x14a00,
  44306         SOC_REG_FLAG_64_BITS |
  44307                           SOC_REG_FLAG_COUNTER,
  44308         0,
  44309         1,
  44310         soc_R1023_BCM53400_A0r_fields,
  44311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44312         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44313         357,
  44314         -1,
  44315     },
  44316 #endif /* chips */
  44317 
  44318 #if defined(BCM_53570_B0)
  44319     { /* SOC_REG_INT_XLPMIB_T1023_BCM53570_B0r */
  44320         soc_block_list[16],
  44321         soc_portreg,
  44322         1,
  44323         0,
  44324         0x14400,
  44325         SOC_REG_FLAG_64_BITS |
  44326                           SOC_REG_FLAG_COUNTER,
  44327         0,
  44328         1,
  44329         soc_R1023_BCM53400_A0r_fields,
  44330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44331         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44332         355,
  44333         -1,
  44334     },
  44335 #endif /* chips */
  44336 
  44337 #if defined(BCM_53570_B0)
  44338     { /* SOC_REG_INT_XLPMIB_T127_BCM53570_B0r */
  44339         soc_block_list[16],
  44340         soc_portreg,
  44341         1,
  44342         0,
  44343         0x14100,
  44344         SOC_REG_FLAG_64_BITS |
  44345                           SOC_REG_FLAG_COUNTER,
  44346         0,
  44347         1,
  44348         soc_R1023_BCM53400_A0r_fields,
  44349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44350         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44351         352,
  44352         -1,
  44353     },
  44354 #endif /* chips */
  44355 
  44356 #if defined(BCM_53570_B0)
  44357     { /* SOC_REG_INT_XLPMIB_T1518_BCM53570_B0r */
  44358         soc_block_list[16],
  44359         soc_portreg,
  44360         1,
  44361         0,
  44362         0x14500,
  44363         SOC_REG_FLAG_64_BITS |
  44364                           SOC_REG_FLAG_COUNTER,
  44365         0,
  44366         1,
  44367         soc_R1023_BCM53400_A0r_fields,
  44368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44369         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44370         356,
  44371         -1,
  44372     },
  44373 #endif /* chips */
  44374 
  44375 #if defined(BCM_53570_B0)
  44376     { /* SOC_REG_INT_XLPMIB_T16383_BCM53570_B0r */
  44377         soc_block_list[16],
  44378         soc_portreg,
  44379         1,
  44380         0,
  44381         0x14a00,
  44382         SOC_REG_FLAG_64_BITS |
  44383                           SOC_REG_FLAG_COUNTER,
  44384         0,
  44385         1,
  44386         soc_R1023_BCM53400_A0r_fields,
  44387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44388         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44389         361,
  44390         -1,
  44391     },
  44392 #endif /* chips */
  44393 
  44394 #if defined(BCM_53570_B0)
  44395     { /* SOC_REG_INT_XLPMIB_T2047_BCM53570_B0r */
  44396         soc_block_list[16],
  44397         soc_portreg,
  44398         1,
  44399         0,
  44400         0x14700,
  44401         SOC_REG_FLAG_64_BITS |
  44402                           SOC_REG_FLAG_COUNTER,
  44403         0,
  44404         1,
  44405         soc_R1023_BCM53400_A0r_fields,
  44406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44408         358,
  44409         -1,
  44410     },
  44411 #endif /* chips */
  44412 
  44413 #if defined(BCM_53570_B0)
  44414     { /* SOC_REG_INT_XLPMIB_T255_BCM53570_B0r */
  44415         soc_block_list[16],
  44416         soc_portreg,
  44417         1,
  44418         0,
  44419         0x14200,
  44420         SOC_REG_FLAG_64_BITS |
  44421                           SOC_REG_FLAG_COUNTER,
  44422         0,
  44423         1,
  44424         soc_R1023_BCM53400_A0r_fields,
  44425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44426         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44427         353,
  44428         -1,
  44429     },
  44430 #endif /* chips */
  44431 
  44432 #if defined(BCM_53570_B0)
  44433     { /* SOC_REG_INT_XLPMIB_T4095_BCM53570_B0r */
  44434         soc_block_list[16],
  44435         soc_portreg,
  44436         1,
  44437         0,
  44438         0x14800,
  44439         SOC_REG_FLAG_64_BITS |
  44440                           SOC_REG_FLAG_COUNTER,
  44441         0,
  44442         1,
  44443         soc_R1023_BCM53400_A0r_fields,
  44444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44445         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44446         359,
  44447         -1,
  44448     },
  44449 #endif /* chips */
  44450 
  44451 #if defined(BCM_53570_B0)
  44452     { /* SOC_REG_INT_XLPMIB_T511_BCM53570_B0r */
  44453         soc_block_list[16],
  44454         soc_portreg,
  44455         1,
  44456         0,
  44457         0x14300,
  44458         SOC_REG_FLAG_64_BITS |
  44459                           SOC_REG_FLAG_COUNTER,
  44460         0,
  44461         1,
  44462         soc_R1023_BCM53400_A0r_fields,
  44463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44464         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44465         354,
  44466         -1,
  44467     },
  44468 #endif /* chips */
  44469 
  44470 #if defined(BCM_53570_B0)
  44471     { /* SOC_REG_INT_XLPMIB_T64_BCM53570_B0r */
  44472         soc_block_list[16],
  44473         soc_portreg,
  44474         1,
  44475         0,
  44476         0x14000,
  44477         SOC_REG_FLAG_64_BITS |
  44478                           SOC_REG_FLAG_COUNTER,
  44479         0,
  44480         1,
  44481         soc_R1023_BCM53400_A0r_fields,
  44482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44484         351,
  44485         -1,
  44486     },
  44487 #endif /* chips */
  44488 
  44489 #if defined(BCM_53570_B0)
  44490     { /* SOC_REG_INT_XLPMIB_T9216_BCM53570_B0r */
  44491         soc_block_list[16],
  44492         soc_portreg,
  44493         1,
  44494         0,
  44495         0x14900,
  44496         SOC_REG_FLAG_64_BITS |
  44497                           SOC_REG_FLAG_COUNTER,
  44498         0,
  44499         1,
  44500         soc_R1023_BCM53400_A0r_fields,
  44501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44502         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44503         360,
  44504         -1,
  44505     },
  44506 #endif /* chips */
  44507 
  44508 #if defined(BCM_53570_A0)
  44509     { /* SOC_REG_INT_XLPMIB_TBCAr */
  44510         soc_block_list[16],
  44511         soc_portreg,
  44512         1,
  44513         0,
  44514         0x14f00,
  44515         SOC_REG_FLAG_64_BITS |
  44516                           SOC_REG_FLAG_COUNTER,
  44517         0,
  44518         1,
  44519         soc_R1023_BCM53400_A0r_fields,
  44520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44521         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44522         362,
  44523         -1,
  44524     },
  44525 #endif /* chips */
  44526 
  44527 #if defined(BCM_53570_B0)
  44528     { /* SOC_REG_INT_XLPMIB_TBCA_BCM53570_B0r */
  44529         soc_block_list[16],
  44530         soc_portreg,
  44531         1,
  44532         0,
  44533         0x14f00,
  44534         SOC_REG_FLAG_64_BITS |
  44535                           SOC_REG_FLAG_COUNTER,
  44536         0,
  44537         1,
  44538         soc_R1023_BCM53400_A0r_fields,
  44539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44540         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44541         366,
  44542         -1,
  44543     },
  44544 #endif /* chips */
  44545 
  44546 #if defined(BCM_53570_A0)
  44547     { /* SOC_REG_INT_XLPMIB_TBYTr */
  44548         soc_block_list[16],
  44549         soc_portreg,
  44550         1,
  44551         0,
  44552         0x16f00,
  44553         SOC_REG_FLAG_64_BITS |
  44554                           SOC_REG_FLAG_COUNTER,
  44555         0,
  44556         1,
  44557         soc_RBYT_BCM53400_A0r_fields,
  44558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44559         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44560         394,
  44561         -1,
  44562     },
  44563 #endif /* chips */
  44564 
  44565 #if defined(BCM_53570_B0)
  44566     { /* SOC_REG_INT_XLPMIB_TBYT_BCM53570_B0r */
  44567         soc_block_list[16],
  44568         soc_portreg,
  44569         1,
  44570         0,
  44571         0x16f00,
  44572         SOC_REG_FLAG_64_BITS |
  44573                           SOC_REG_FLAG_COUNTER,
  44574         0,
  44575         1,
  44576         soc_RBYT_BCM53400_A0r_fields,
  44577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44578         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44579         398,
  44580         -1,
  44581     },
  44582 #endif /* chips */
  44583 
  44584 #if defined(BCM_53570_A0)
  44585     { /* SOC_REG_INT_XLPMIB_TDVLNr */
  44586         soc_block_list[16],
  44587         soc_portreg,
  44588         1,
  44589         0,
  44590         0x15f00,
  44591         SOC_REG_FLAG_64_BITS |
  44592                           SOC_REG_FLAG_COUNTER,
  44593         0,
  44594         1,
  44595         soc_R1023_BCM53400_A0r_fields,
  44596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44598         378,
  44599         -1,
  44600     },
  44601 #endif /* chips */
  44602 
  44603 #if defined(BCM_53570_B0)
  44604     { /* SOC_REG_INT_XLPMIB_TDVLN_BCM53570_B0r */
  44605         soc_block_list[16],
  44606         soc_portreg,
  44607         1,
  44608         0,
  44609         0x15f00,
  44610         SOC_REG_FLAG_64_BITS |
  44611                           SOC_REG_FLAG_COUNTER,
  44612         0,
  44613         1,
  44614         soc_R1023_BCM53400_A0r_fields,
  44615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44616         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44617         382,
  44618         -1,
  44619     },
  44620 #endif /* chips */
  44621 
  44622 #if defined(BCM_53570_A0)
  44623     { /* SOC_REG_INT_XLPMIB_TERRr */
  44624         soc_block_list[16],
  44625         soc_portreg,
  44626         1,
  44627         0,
  44628         0x15d00,
  44629         SOC_REG_FLAG_64_BITS |
  44630                           SOC_REG_FLAG_COUNTER |
  44631                           SOC_REG_FLAG_ED_CNTR,
  44632         0,
  44633         1,
  44634         soc_R1023_BCM53400_A0r_fields,
  44635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44636         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44637         376,
  44638         -1,
  44639     },
  44640 #endif /* chips */
  44641 
  44642 #if defined(BCM_53570_B0)
  44643     { /* SOC_REG_INT_XLPMIB_TERR_BCM53570_B0r */
  44644         soc_block_list[16],
  44645         soc_portreg,
  44646         1,
  44647         0,
  44648         0x15d00,
  44649         SOC_REG_FLAG_64_BITS |
  44650                           SOC_REG_FLAG_COUNTER |
  44651                           SOC_REG_FLAG_ED_CNTR,
  44652         0,
  44653         1,
  44654         soc_R1023_BCM53400_A0r_fields,
  44655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44656         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44657         380,
  44658         -1,
  44659     },
  44660 #endif /* chips */
  44661 
  44662 #if defined(BCM_53570_A0)
  44663     { /* SOC_REG_INT_XLPMIB_TFCSr */
  44664         soc_block_list[16],
  44665         soc_portreg,
  44666         1,
  44667         0,
  44668         0x15300,
  44669         SOC_REG_FLAG_64_BITS |
  44670                           SOC_REG_FLAG_COUNTER |
  44671                           SOC_REG_FLAG_ED_CNTR,
  44672         0,
  44673         1,
  44674         soc_R1023_BCM53400_A0r_fields,
  44675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44676         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44677         366,
  44678         -1,
  44679     },
  44680 #endif /* chips */
  44681 
  44682 #if defined(BCM_53570_B0)
  44683     { /* SOC_REG_INT_XLPMIB_TFCS_BCM53570_B0r */
  44684         soc_block_list[16],
  44685         soc_portreg,
  44686         1,
  44687         0,
  44688         0x15300,
  44689         SOC_REG_FLAG_64_BITS |
  44690                           SOC_REG_FLAG_COUNTER |
  44691                           SOC_REG_FLAG_ED_CNTR,
  44692         0,
  44693         1,
  44694         soc_R1023_BCM53400_A0r_fields,
  44695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44696         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44697         370,
  44698         -1,
  44699     },
  44700 #endif /* chips */
  44701 
  44702 #if defined(BCM_53570_A0)
  44703     { /* SOC_REG_INT_XLPMIB_TFRGr */
  44704         soc_block_list[16],
  44705         soc_portreg,
  44706         1,
  44707         0,
  44708         0x15c00,
  44709         SOC_REG_FLAG_64_BITS |
  44710                           SOC_REG_FLAG_COUNTER |
  44711                           SOC_REG_FLAG_ED_CNTR,
  44712         0,
  44713         1,
  44714         soc_R1023_BCM53400_A0r_fields,
  44715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44716         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44717         375,
  44718         -1,
  44719     },
  44720 #endif /* chips */
  44721 
  44722 #if defined(BCM_53570_B0)
  44723     { /* SOC_REG_INT_XLPMIB_TFRG_BCM53570_B0r */
  44724         soc_block_list[16],
  44725         soc_portreg,
  44726         1,
  44727         0,
  44728         0x15c00,
  44729         SOC_REG_FLAG_64_BITS |
  44730                           SOC_REG_FLAG_COUNTER |
  44731                           SOC_REG_FLAG_ED_CNTR,
  44732         0,
  44733         1,
  44734         soc_R1023_BCM53400_A0r_fields,
  44735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44736         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44737         379,
  44738         -1,
  44739     },
  44740 #endif /* chips */
  44741 
  44742 #if defined(BCM_53570_A0)
  44743     { /* SOC_REG_INT_XLPMIB_TJBRr */
  44744         soc_block_list[16],
  44745         soc_portreg,
  44746         1,
  44747         0,
  44748         0x15200,
  44749         SOC_REG_FLAG_64_BITS |
  44750                           SOC_REG_FLAG_COUNTER |
  44751                           SOC_REG_FLAG_ED_CNTR,
  44752         0,
  44753         1,
  44754         soc_R1023_BCM53400_A0r_fields,
  44755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44756         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44757         365,
  44758         -1,
  44759     },
  44760 #endif /* chips */
  44761 
  44762 #if defined(BCM_53570_B0)
  44763     { /* SOC_REG_INT_XLPMIB_TJBR_BCM53570_B0r */
  44764         soc_block_list[16],
  44765         soc_portreg,
  44766         1,
  44767         0,
  44768         0x15200,
  44769         SOC_REG_FLAG_64_BITS |
  44770                           SOC_REG_FLAG_COUNTER |
  44771                           SOC_REG_FLAG_ED_CNTR,
  44772         0,
  44773         1,
  44774         soc_R1023_BCM53400_A0r_fields,
  44775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44776         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44777         369,
  44778         -1,
  44779     },
  44780 #endif /* chips */
  44781 
  44782 #if defined(BCM_53570_A0)
  44783     { /* SOC_REG_INT_XLPMIB_TLCLr */
  44784         soc_block_list[16],
  44785         soc_portreg,
  44786         1,
  44787         0,
  44788         0x15a00,
  44789         SOC_REG_FLAG_64_BITS |
  44790                           SOC_REG_FLAG_COUNTER |
  44791                           SOC_REG_FLAG_ED_CNTR,
  44792         0,
  44793         1,
  44794         soc_XLMIB_RSCHCRCr_fields,
  44795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44796         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44797         373,
  44798         -1,
  44799     },
  44800 #endif /* chips */
  44801 
  44802 #if defined(BCM_53570_B0)
  44803     { /* SOC_REG_INT_XLPMIB_TLCL_BCM53570_B0r */
  44804         soc_block_list[16],
  44805         soc_portreg,
  44806         1,
  44807         0,
  44808         0x15a00,
  44809         SOC_REG_FLAG_64_BITS |
  44810                           SOC_REG_FLAG_COUNTER |
  44811                           SOC_REG_FLAG_ED_CNTR,
  44812         0,
  44813         1,
  44814         soc_XLMIB_RSCHCRCr_fields,
  44815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44816         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44817         377,
  44818         -1,
  44819     },
  44820 #endif /* chips */
  44821 
  44822 #if defined(BCM_53570_A0)
  44823     { /* SOC_REG_INT_XLPMIB_TMCAr */
  44824         soc_block_list[16],
  44825         soc_portreg,
  44826         1,
  44827         0,
  44828         0x14e00,
  44829         SOC_REG_FLAG_64_BITS |
  44830                           SOC_REG_FLAG_COUNTER,
  44831         0,
  44832         1,
  44833         soc_R1023_BCM53400_A0r_fields,
  44834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44835         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44836         361,
  44837         -1,
  44838     },
  44839 #endif /* chips */
  44840 
  44841 #if defined(BCM_53570_B0)
  44842     { /* SOC_REG_INT_XLPMIB_TMCA_BCM53570_B0r */
  44843         soc_block_list[16],
  44844         soc_portreg,
  44845         1,
  44846         0,
  44847         0x14e00,
  44848         SOC_REG_FLAG_64_BITS |
  44849                           SOC_REG_FLAG_COUNTER,
  44850         0,
  44851         1,
  44852         soc_R1023_BCM53400_A0r_fields,
  44853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44854         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44855         365,
  44856         -1,
  44857     },
  44858 #endif /* chips */
  44859 
  44860 #if defined(BCM_53570_A0)
  44861     { /* SOC_REG_INT_XLPMIB_TMCLr */
  44862         soc_block_list[16],
  44863         soc_portreg,
  44864         1,
  44865         0,
  44866         0x15900,
  44867         SOC_REG_FLAG_64_BITS |
  44868                           SOC_REG_FLAG_COUNTER |
  44869                           SOC_REG_FLAG_ED_CNTR,
  44870         0,
  44871         1,
  44872         soc_XLMIB_RSCHCRCr_fields,
  44873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44874         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44875         372,
  44876         -1,
  44877     },
  44878 #endif /* chips */
  44879 
  44880 #if defined(BCM_53570_B0)
  44881     { /* SOC_REG_INT_XLPMIB_TMCL_BCM53570_B0r */
  44882         soc_block_list[16],
  44883         soc_portreg,
  44884         1,
  44885         0,
  44886         0x15900,
  44887         SOC_REG_FLAG_64_BITS |
  44888                           SOC_REG_FLAG_COUNTER |
  44889                           SOC_REG_FLAG_ED_CNTR,
  44890         0,
  44891         1,
  44892         soc_XLMIB_RSCHCRCr_fields,
  44893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44894         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44895         376,
  44896         -1,
  44897     },
  44898 #endif /* chips */
  44899 
  44900 #if defined(BCM_53570_A0)
  44901     { /* SOC_REG_INT_XLPMIB_TMFAEr */
  44902         soc_block_list[16],
  44903         soc_portreg,
  44904         1,
  44905         0,
  44906         0x15600,
  44907         SOC_REG_FLAG_64_BITS |
  44908                           SOC_REG_FLAG_COUNTER |
  44909                           SOC_REG_FLAG_ED_CNTR,
  44910         0,
  44911         1,
  44912         soc_RALN_BCM53400_A0r_fields,
  44913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44914         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44915         369,
  44916         -1,
  44917     },
  44918 #endif /* chips */
  44919 
  44920 #if defined(BCM_53570_B0)
  44921     { /* SOC_REG_INT_XLPMIB_TMFAE_BCM53570_B0r */
  44922         soc_block_list[16],
  44923         soc_portreg,
  44924         1,
  44925         0,
  44926         0x15600,
  44927         SOC_REG_FLAG_64_BITS |
  44928                           SOC_REG_FLAG_COUNTER |
  44929                           SOC_REG_FLAG_ED_CNTR,
  44930         0,
  44931         1,
  44932         soc_RALN_BCM53400_A0r_fields,
  44933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44934         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44935         373,
  44936         -1,
  44937     },
  44938 #endif /* chips */
  44939 
  44940 #if defined(BCM_53570_A0)
  44941     { /* SOC_REG_INT_XLPMIB_TMFCr */
  44942         soc_block_list[16],
  44943         soc_portreg,
  44944         1,
  44945         0,
  44946         0x15700,
  44947         SOC_REG_FLAG_64_BITS |
  44948                           SOC_REG_FLAG_COUNTER |
  44949                           SOC_REG_FLAG_ED_CNTR,
  44950         0,
  44951         1,
  44952         soc_R1023_BCM53400_A0r_fields,
  44953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44954         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44955         370,
  44956         -1,
  44957     },
  44958 #endif /* chips */
  44959 
  44960 #if defined(BCM_53570_B0)
  44961     { /* SOC_REG_INT_XLPMIB_TMFC_BCM53570_B0r */
  44962         soc_block_list[16],
  44963         soc_portreg,
  44964         1,
  44965         0,
  44966         0x15700,
  44967         SOC_REG_FLAG_64_BITS |
  44968                           SOC_REG_FLAG_COUNTER |
  44969                           SOC_REG_FLAG_ED_CNTR,
  44970         0,
  44971         1,
  44972         soc_R1023_BCM53400_A0r_fields,
  44973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44974         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44975         374,
  44976         -1,
  44977     },
  44978 #endif /* chips */
  44979 
  44980 #if defined(BCM_53570_A0)
  44981     { /* SOC_REG_INT_XLPMIB_TMGVr */
  44982         soc_block_list[16],
  44983         soc_portreg,
  44984         1,
  44985         0,
  44986         0x14600,
  44987         SOC_REG_FLAG_64_BITS |
  44988                           SOC_REG_FLAG_COUNTER,
  44989         0,
  44990         1,
  44991         soc_R1023_BCM53400_A0r_fields,
  44992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  44994         353,
  44995         -1,
  44996     },
  44997 #endif /* chips */
  44998 
  44999 #if defined(BCM_53570_B0)
  45000     { /* SOC_REG_INT_XLPMIB_TMGV_BCM53570_B0r */
  45001         soc_block_list[16],
  45002         soc_portreg,
  45003         1,
  45004         0,
  45005         0x14600,
  45006         SOC_REG_FLAG_64_BITS |
  45007                           SOC_REG_FLAG_COUNTER,
  45008         0,
  45009         1,
  45010         soc_R1023_BCM53400_A0r_fields,
  45011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45012         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45013         357,
  45014         -1,
  45015     },
  45016 #endif /* chips */
  45017 
  45018 #if defined(BCM_53570_A0)
  45019     { /* SOC_REG_INT_XLPMIB_TNCLr */
  45020         soc_block_list[16],
  45021         soc_portreg,
  45022         1,
  45023         0,
  45024         0x16e00,
  45025         SOC_REG_FLAG_64_BITS |
  45026                           SOC_REG_FLAG_COUNTER,
  45027         0,
  45028         1,
  45029         soc_XLMIB_RSCHCRCr_fields,
  45030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45032         393,
  45033         -1,
  45034     },
  45035 #endif /* chips */
  45036 
  45037 #if defined(BCM_53570_B0)
  45038     { /* SOC_REG_INT_XLPMIB_TNCL_BCM53570_B0r */
  45039         soc_block_list[16],
  45040         soc_portreg,
  45041         1,
  45042         0,
  45043         0x16e00,
  45044         SOC_REG_FLAG_64_BITS |
  45045                           SOC_REG_FLAG_COUNTER,
  45046         0,
  45047         1,
  45048         soc_XLMIB_RSCHCRCr_fields,
  45049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45050         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45051         397,
  45052         -1,
  45053     },
  45054 #endif /* chips */
  45055 
  45056 #if defined(BCM_53570_A0)
  45057     { /* SOC_REG_INT_XLPMIB_TOVRr */
  45058         soc_block_list[16],
  45059         soc_portreg,
  45060         1,
  45061         0,
  45062         0x15500,
  45063         SOC_REG_FLAG_64_BITS |
  45064                           SOC_REG_FLAG_COUNTER |
  45065                           SOC_REG_FLAG_ED_CNTR,
  45066         0,
  45067         1,
  45068         soc_R1023_BCM53400_A0r_fields,
  45069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45070         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45071         368,
  45072         -1,
  45073     },
  45074 #endif /* chips */
  45075 
  45076 #if defined(BCM_53570_B0)
  45077     { /* SOC_REG_INT_XLPMIB_TOVR_BCM53570_B0r */
  45078         soc_block_list[16],
  45079         soc_portreg,
  45080         1,
  45081         0,
  45082         0x15500,
  45083         SOC_REG_FLAG_64_BITS |
  45084                           SOC_REG_FLAG_COUNTER |
  45085                           SOC_REG_FLAG_ED_CNTR,
  45086         0,
  45087         1,
  45088         soc_R1023_BCM53400_A0r_fields,
  45089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45091         372,
  45092         -1,
  45093     },
  45094 #endif /* chips */
  45095 
  45096 #if defined(BCM_53570_A0)
  45097     { /* SOC_REG_INT_XLPMIB_TPFC0r */
  45098         soc_block_list[16],
  45099         soc_portreg,
  45100         1,
  45101         0,
  45102         0x16200,
  45103         SOC_REG_FLAG_64_BITS |
  45104                           SOC_REG_FLAG_COUNTER,
  45105         0,
  45106         1,
  45107         soc_XLMIB_RSCHCRCr_fields,
  45108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45110         381,
  45111         -1,
  45112     },
  45113 #endif /* chips */
  45114 
  45115 #if defined(BCM_53570_A0)
  45116     { /* SOC_REG_INT_XLPMIB_TPFC1r */
  45117         soc_block_list[16],
  45118         soc_portreg,
  45119         1,
  45120         0,
  45121         0x16300,
  45122         SOC_REG_FLAG_64_BITS |
  45123                           SOC_REG_FLAG_COUNTER,
  45124         0,
  45125         1,
  45126         soc_XLMIB_RSCHCRCr_fields,
  45127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45128         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45129         382,
  45130         -1,
  45131     },
  45132 #endif /* chips */
  45133 
  45134 #if defined(BCM_53570_A0)
  45135     { /* SOC_REG_INT_XLPMIB_TPFC2r */
  45136         soc_block_list[16],
  45137         soc_portreg,
  45138         1,
  45139         0,
  45140         0x16400,
  45141         SOC_REG_FLAG_64_BITS |
  45142                           SOC_REG_FLAG_COUNTER,
  45143         0,
  45144         1,
  45145         soc_XLMIB_RSCHCRCr_fields,
  45146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45147         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45148         383,
  45149         -1,
  45150     },
  45151 #endif /* chips */
  45152 
  45153 #if defined(BCM_53570_A0)
  45154     { /* SOC_REG_INT_XLPMIB_TPFC3r */
  45155         soc_block_list[16],
  45156         soc_portreg,
  45157         1,
  45158         0,
  45159         0x16500,
  45160         SOC_REG_FLAG_64_BITS |
  45161                           SOC_REG_FLAG_COUNTER,
  45162         0,
  45163         1,
  45164         soc_XLMIB_RSCHCRCr_fields,
  45165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45166         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45167         384,
  45168         -1,
  45169     },
  45170 #endif /* chips */
  45171 
  45172 #if defined(BCM_53570_A0)
  45173     { /* SOC_REG_INT_XLPMIB_TPFC4r */
  45174         soc_block_list[16],
  45175         soc_portreg,
  45176         1,
  45177         0,
  45178         0x16600,
  45179         SOC_REG_FLAG_64_BITS |
  45180                           SOC_REG_FLAG_COUNTER,
  45181         0,
  45182         1,
  45183         soc_XLMIB_RSCHCRCr_fields,
  45184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45185         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45186         385,
  45187         -1,
  45188     },
  45189 #endif /* chips */
  45190 
  45191 #if defined(BCM_53570_A0)
  45192     { /* SOC_REG_INT_XLPMIB_TPFC5r */
  45193         soc_block_list[16],
  45194         soc_portreg,
  45195         1,
  45196         0,
  45197         0x16700,
  45198         SOC_REG_FLAG_64_BITS |
  45199                           SOC_REG_FLAG_COUNTER,
  45200         0,
  45201         1,
  45202         soc_XLMIB_RSCHCRCr_fields,
  45203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45204         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45205         386,
  45206         -1,
  45207     },
  45208 #endif /* chips */
  45209 
  45210 #if defined(BCM_53570_A0)
  45211     { /* SOC_REG_INT_XLPMIB_TPFC6r */
  45212         soc_block_list[16],
  45213         soc_portreg,
  45214         1,
  45215         0,
  45216         0x16800,
  45217         SOC_REG_FLAG_64_BITS |
  45218                           SOC_REG_FLAG_COUNTER,
  45219         0,
  45220         1,
  45221         soc_XLMIB_RSCHCRCr_fields,
  45222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45223         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45224         387,
  45225         -1,
  45226     },
  45227 #endif /* chips */
  45228 
  45229 #if defined(BCM_53570_A0)
  45230     { /* SOC_REG_INT_XLPMIB_TPFC7r */
  45231         soc_block_list[16],
  45232         soc_portreg,
  45233         1,
  45234         0,
  45235         0x16900,
  45236         SOC_REG_FLAG_64_BITS |
  45237                           SOC_REG_FLAG_COUNTER,
  45238         0,
  45239         1,
  45240         soc_XLMIB_RSCHCRCr_fields,
  45241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45242         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45243         388,
  45244         -1,
  45245     },
  45246 #endif /* chips */
  45247 
  45248 #if defined(BCM_53570_B0)
  45249     { /* SOC_REG_INT_XLPMIB_TPFC0_BCM53570_B0r */
  45250         soc_block_list[16],
  45251         soc_portreg,
  45252         1,
  45253         0,
  45254         0x16200,
  45255         SOC_REG_FLAG_64_BITS |
  45256                           SOC_REG_FLAG_COUNTER,
  45257         0,
  45258         1,
  45259         soc_XLMIB_RSCHCRCr_fields,
  45260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45261         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45262         385,
  45263         -1,
  45264     },
  45265 #endif /* chips */
  45266 
  45267 #if defined(BCM_53570_B0)
  45268     { /* SOC_REG_INT_XLPMIB_TPFC1_BCM53570_B0r */
  45269         soc_block_list[16],
  45270         soc_portreg,
  45271         1,
  45272         0,
  45273         0x16300,
  45274         SOC_REG_FLAG_64_BITS |
  45275                           SOC_REG_FLAG_COUNTER,
  45276         0,
  45277         1,
  45278         soc_XLMIB_RSCHCRCr_fields,
  45279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45280         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45281         386,
  45282         -1,
  45283     },
  45284 #endif /* chips */
  45285 
  45286 #if defined(BCM_53570_B0)
  45287     { /* SOC_REG_INT_XLPMIB_TPFC2_BCM53570_B0r */
  45288         soc_block_list[16],
  45289         soc_portreg,
  45290         1,
  45291         0,
  45292         0x16400,
  45293         SOC_REG_FLAG_64_BITS |
  45294                           SOC_REG_FLAG_COUNTER,
  45295         0,
  45296         1,
  45297         soc_XLMIB_RSCHCRCr_fields,
  45298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45300         387,
  45301         -1,
  45302     },
  45303 #endif /* chips */
  45304 
  45305 #if defined(BCM_53570_B0)
  45306     { /* SOC_REG_INT_XLPMIB_TPFC3_BCM53570_B0r */
  45307         soc_block_list[16],
  45308         soc_portreg,
  45309         1,
  45310         0,
  45311         0x16500,
  45312         SOC_REG_FLAG_64_BITS |
  45313                           SOC_REG_FLAG_COUNTER,
  45314         0,
  45315         1,
  45316         soc_XLMIB_RSCHCRCr_fields,
  45317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45318         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45319         388,
  45320         -1,
  45321     },
  45322 #endif /* chips */
  45323 
  45324 #if defined(BCM_53570_B0)
  45325     { /* SOC_REG_INT_XLPMIB_TPFC4_BCM53570_B0r */
  45326         soc_block_list[16],
  45327         soc_portreg,
  45328         1,
  45329         0,
  45330         0x16600,
  45331         SOC_REG_FLAG_64_BITS |
  45332                           SOC_REG_FLAG_COUNTER,
  45333         0,
  45334         1,
  45335         soc_XLMIB_RSCHCRCr_fields,
  45336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45337         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45338         389,
  45339         -1,
  45340     },
  45341 #endif /* chips */
  45342 
  45343 #if defined(BCM_53570_B0)
  45344     { /* SOC_REG_INT_XLPMIB_TPFC5_BCM53570_B0r */
  45345         soc_block_list[16],
  45346         soc_portreg,
  45347         1,
  45348         0,
  45349         0x16700,
  45350         SOC_REG_FLAG_64_BITS |
  45351                           SOC_REG_FLAG_COUNTER,
  45352         0,
  45353         1,
  45354         soc_XLMIB_RSCHCRCr_fields,
  45355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45357         390,
  45358         -1,
  45359     },
  45360 #endif /* chips */
  45361 
  45362 #if defined(BCM_53570_B0)
  45363     { /* SOC_REG_INT_XLPMIB_TPFC6_BCM53570_B0r */
  45364         soc_block_list[16],
  45365         soc_portreg,
  45366         1,
  45367         0,
  45368         0x16800,
  45369         SOC_REG_FLAG_64_BITS |
  45370                           SOC_REG_FLAG_COUNTER,
  45371         0,
  45372         1,
  45373         soc_XLMIB_RSCHCRCr_fields,
  45374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45375         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45376         391,
  45377         -1,
  45378     },
  45379 #endif /* chips */
  45380 
  45381 #if defined(BCM_53570_B0)
  45382     { /* SOC_REG_INT_XLPMIB_TPFC7_BCM53570_B0r */
  45383         soc_block_list[16],
  45384         soc_portreg,
  45385         1,
  45386         0,
  45387         0x16900,
  45388         SOC_REG_FLAG_64_BITS |
  45389                           SOC_REG_FLAG_COUNTER,
  45390         0,
  45391         1,
  45392         soc_XLMIB_RSCHCRCr_fields,
  45393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45394         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45395         392,
  45396         -1,
  45397     },
  45398 #endif /* chips */
  45399 
  45400 #if defined(BCM_53570_A0)
  45401     { /* SOC_REG_INT_XLPMIB_TPFCOFF0r */
  45402         soc_block_list[16],
  45403         soc_portreg,
  45404         1,
  45405         0,
  45406         0x17900,
  45407         SOC_REG_FLAG_64_BITS |
  45408                           SOC_REG_FLAG_COUNTER,
  45409         0,
  45410         1,
  45411         soc_XLMIB_RSCHCRCr_fields,
  45412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45413         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45414         404,
  45415         -1,
  45416     },
  45417 #endif /* chips */
  45418 
  45419 #if defined(BCM_53570_A0)
  45420     { /* SOC_REG_INT_XLPMIB_TPFCOFF1r */
  45421         soc_block_list[16],
  45422         soc_portreg,
  45423         1,
  45424         0,
  45425         0x17a00,
  45426         SOC_REG_FLAG_64_BITS |
  45427                           SOC_REG_FLAG_COUNTER,
  45428         0,
  45429         1,
  45430         soc_XLMIB_RSCHCRCr_fields,
  45431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45433         405,
  45434         -1,
  45435     },
  45436 #endif /* chips */
  45437 
  45438 #if defined(BCM_53570_A0)
  45439     { /* SOC_REG_INT_XLPMIB_TPFCOFF2r */
  45440         soc_block_list[16],
  45441         soc_portreg,
  45442         1,
  45443         0,
  45444         0x17b00,
  45445         SOC_REG_FLAG_64_BITS |
  45446                           SOC_REG_FLAG_COUNTER,
  45447         0,
  45448         1,
  45449         soc_XLMIB_RSCHCRCr_fields,
  45450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45451         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45452         406,
  45453         -1,
  45454     },
  45455 #endif /* chips */
  45456 
  45457 #if defined(BCM_53570_A0)
  45458     { /* SOC_REG_INT_XLPMIB_TPFCOFF3r */
  45459         soc_block_list[16],
  45460         soc_portreg,
  45461         1,
  45462         0,
  45463         0x17c00,
  45464         SOC_REG_FLAG_64_BITS |
  45465                           SOC_REG_FLAG_COUNTER,
  45466         0,
  45467         1,
  45468         soc_XLMIB_RSCHCRCr_fields,
  45469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45470         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45471         407,
  45472         -1,
  45473     },
  45474 #endif /* chips */
  45475 
  45476 #if defined(BCM_53570_A0)
  45477     { /* SOC_REG_INT_XLPMIB_TPFCOFF4r */
  45478         soc_block_list[16],
  45479         soc_portreg,
  45480         1,
  45481         0,
  45482         0x17d00,
  45483         SOC_REG_FLAG_64_BITS |
  45484                           SOC_REG_FLAG_COUNTER,
  45485         0,
  45486         1,
  45487         soc_XLMIB_RSCHCRCr_fields,
  45488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45489         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45490         408,
  45491         -1,
  45492     },
  45493 #endif /* chips */
  45494 
  45495 #if defined(BCM_53570_A0)
  45496     { /* SOC_REG_INT_XLPMIB_TPFCOFF5r */
  45497         soc_block_list[16],
  45498         soc_portreg,
  45499         1,
  45500         0,
  45501         0x17e00,
  45502         SOC_REG_FLAG_64_BITS |
  45503                           SOC_REG_FLAG_COUNTER,
  45504         0,
  45505         1,
  45506         soc_XLMIB_RSCHCRCr_fields,
  45507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45508         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45509         409,
  45510         -1,
  45511     },
  45512 #endif /* chips */
  45513 
  45514 #if defined(BCM_53570_A0)
  45515     { /* SOC_REG_INT_XLPMIB_TPFCOFF6r */
  45516         soc_block_list[16],
  45517         soc_portreg,
  45518         1,
  45519         0,
  45520         0x17f00,
  45521         SOC_REG_FLAG_64_BITS |
  45522                           SOC_REG_FLAG_COUNTER,
  45523         0,
  45524         1,
  45525         soc_XLMIB_RSCHCRCr_fields,
  45526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45527         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45528         410,
  45529         -1,
  45530     },
  45531 #endif /* chips */
  45532 
  45533 #if defined(BCM_53570_A0)
  45534     { /* SOC_REG_INT_XLPMIB_TPFCOFF7r */
  45535         soc_block_list[16],
  45536         soc_portreg,
  45537         1,
  45538         0,
  45539         0x18000,
  45540         SOC_REG_FLAG_64_BITS |
  45541                           SOC_REG_FLAG_COUNTER,
  45542         0,
  45543         1,
  45544         soc_XLMIB_RSCHCRCr_fields,
  45545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45546         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45547         411,
  45548         -1,
  45549     },
  45550 #endif /* chips */
  45551 
  45552 #if defined(BCM_53570_B0)
  45553     { /* SOC_REG_INT_XLPMIB_TPFCOFF0_BCM53570_B0r */
  45554         soc_block_list[16],
  45555         soc_portreg,
  45556         1,
  45557         0,
  45558         0x17900,
  45559         SOC_REG_FLAG_64_BITS |
  45560                           SOC_REG_FLAG_COUNTER,
  45561         0,
  45562         1,
  45563         soc_XLMIB_RSCHCRCr_fields,
  45564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45565         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45566         408,
  45567         -1,
  45568     },
  45569 #endif /* chips */
  45570 
  45571 #if defined(BCM_53570_B0)
  45572     { /* SOC_REG_INT_XLPMIB_TPFCOFF1_BCM53570_B0r */
  45573         soc_block_list[16],
  45574         soc_portreg,
  45575         1,
  45576         0,
  45577         0x17a00,
  45578         SOC_REG_FLAG_64_BITS |
  45579                           SOC_REG_FLAG_COUNTER,
  45580         0,
  45581         1,
  45582         soc_XLMIB_RSCHCRCr_fields,
  45583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45584         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45585         409,
  45586         -1,
  45587     },
  45588 #endif /* chips */
  45589 
  45590 #if defined(BCM_53570_B0)
  45591     { /* SOC_REG_INT_XLPMIB_TPFCOFF2_BCM53570_B0r */
  45592         soc_block_list[16],
  45593         soc_portreg,
  45594         1,
  45595         0,
  45596         0x17b00,
  45597         SOC_REG_FLAG_64_BITS |
  45598                           SOC_REG_FLAG_COUNTER,
  45599         0,
  45600         1,
  45601         soc_XLMIB_RSCHCRCr_fields,
  45602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45603         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45604         410,
  45605         -1,
  45606     },
  45607 #endif /* chips */
  45608 
  45609 #if defined(BCM_53570_B0)
  45610     { /* SOC_REG_INT_XLPMIB_TPFCOFF3_BCM53570_B0r */
  45611         soc_block_list[16],
  45612         soc_portreg,
  45613         1,
  45614         0,
  45615         0x17c00,
  45616         SOC_REG_FLAG_64_BITS |
  45617                           SOC_REG_FLAG_COUNTER,
  45618         0,
  45619         1,
  45620         soc_XLMIB_RSCHCRCr_fields,
  45621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45622         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45623         411,
  45624         -1,
  45625     },
  45626 #endif /* chips */
  45627 
  45628 #if defined(BCM_53570_B0)
  45629     { /* SOC_REG_INT_XLPMIB_TPFCOFF4_BCM53570_B0r */
  45630         soc_block_list[16],
  45631         soc_portreg,
  45632         1,
  45633         0,
  45634         0x17d00,
  45635         SOC_REG_FLAG_64_BITS |
  45636                           SOC_REG_FLAG_COUNTER,
  45637         0,
  45638         1,
  45639         soc_XLMIB_RSCHCRCr_fields,
  45640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45641         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45642         412,
  45643         -1,
  45644     },
  45645 #endif /* chips */
  45646 
  45647 #if defined(BCM_53570_B0)
  45648     { /* SOC_REG_INT_XLPMIB_TPFCOFF5_BCM53570_B0r */
  45649         soc_block_list[16],
  45650         soc_portreg,
  45651         1,
  45652         0,
  45653         0x17e00,
  45654         SOC_REG_FLAG_64_BITS |
  45655                           SOC_REG_FLAG_COUNTER,
  45656         0,
  45657         1,
  45658         soc_XLMIB_RSCHCRCr_fields,
  45659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45660         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45661         413,
  45662         -1,
  45663     },
  45664 #endif /* chips */
  45665 
  45666 #if defined(BCM_53570_B0)
  45667     { /* SOC_REG_INT_XLPMIB_TPFCOFF6_BCM53570_B0r */
  45668         soc_block_list[16],
  45669         soc_portreg,
  45670         1,
  45671         0,
  45672         0x17f00,
  45673         SOC_REG_FLAG_64_BITS |
  45674                           SOC_REG_FLAG_COUNTER,
  45675         0,
  45676         1,
  45677         soc_XLMIB_RSCHCRCr_fields,
  45678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45679         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45680         414,
  45681         -1,
  45682     },
  45683 #endif /* chips */
  45684 
  45685 #if defined(BCM_53570_B0)
  45686     { /* SOC_REG_INT_XLPMIB_TPFCOFF7_BCM53570_B0r */
  45687         soc_block_list[16],
  45688         soc_portreg,
  45689         1,
  45690         0,
  45691         0x18000,
  45692         SOC_REG_FLAG_64_BITS |
  45693                           SOC_REG_FLAG_COUNTER,
  45694         0,
  45695         1,
  45696         soc_XLMIB_RSCHCRCr_fields,
  45697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45698         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45699         415,
  45700         -1,
  45701     },
  45702 #endif /* chips */
  45703 
  45704 #if defined(BCM_53570_A0)
  45705     { /* SOC_REG_INT_XLPMIB_TPKTr */
  45706         soc_block_list[16],
  45707         soc_portreg,
  45708         1,
  45709         0,
  45710         0x14c00,
  45711         SOC_REG_FLAG_64_BITS |
  45712                           SOC_REG_FLAG_COUNTER,
  45713         0,
  45714         1,
  45715         soc_R1023_BCM53400_A0r_fields,
  45716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45718         359,
  45719         -1,
  45720     },
  45721 #endif /* chips */
  45722 
  45723 #if defined(BCM_53570_B0)
  45724     { /* SOC_REG_INT_XLPMIB_TPKT_BCM53570_B0r */
  45725         soc_block_list[16],
  45726         soc_portreg,
  45727         1,
  45728         0,
  45729         0x14c00,
  45730         SOC_REG_FLAG_64_BITS |
  45731                           SOC_REG_FLAG_COUNTER,
  45732         0,
  45733         1,
  45734         soc_R1023_BCM53400_A0r_fields,
  45735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45736         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45737         363,
  45738         -1,
  45739     },
  45740 #endif /* chips */
  45741 
  45742 #if defined(BCM_53570_A0)
  45743     { /* SOC_REG_INT_XLPMIB_TPOKr */
  45744         soc_block_list[16],
  45745         soc_portreg,
  45746         1,
  45747         0,
  45748         0x14b00,
  45749         SOC_REG_FLAG_64_BITS |
  45750                           SOC_REG_FLAG_COUNTER,
  45751         0,
  45752         1,
  45753         soc_R1023_BCM53400_A0r_fields,
  45754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45755         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45756         358,
  45757         -1,
  45758     },
  45759 #endif /* chips */
  45760 
  45761 #if defined(BCM_53570_B0)
  45762     { /* SOC_REG_INT_XLPMIB_TPOK_BCM53570_B0r */
  45763         soc_block_list[16],
  45764         soc_portreg,
  45765         1,
  45766         0,
  45767         0x14b00,
  45768         SOC_REG_FLAG_64_BITS |
  45769                           SOC_REG_FLAG_COUNTER,
  45770         0,
  45771         1,
  45772         soc_R1023_BCM53400_A0r_fields,
  45773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45774         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45775         362,
  45776         -1,
  45777     },
  45778 #endif /* chips */
  45779 
  45780 #if defined(BCM_53570_A0)
  45781     { /* SOC_REG_INT_XLPMIB_TRPKTr */
  45782         soc_block_list[16],
  45783         soc_portreg,
  45784         1,
  45785         0,
  45786         0x16000,
  45787         SOC_REG_FLAG_64_BITS |
  45788                           SOC_REG_FLAG_COUNTER |
  45789                           SOC_REG_FLAG_ED_CNTR,
  45790         0,
  45791         1,
  45792         soc_R1023_BCM53400_A0r_fields,
  45793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45794         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45795         379,
  45796         -1,
  45797     },
  45798 #endif /* chips */
  45799 
  45800 #if defined(BCM_53570_B0)
  45801     { /* SOC_REG_INT_XLPMIB_TRPKT_BCM53570_B0r */
  45802         soc_block_list[16],
  45803         soc_portreg,
  45804         1,
  45805         0,
  45806         0x16000,
  45807         SOC_REG_FLAG_64_BITS |
  45808                           SOC_REG_FLAG_COUNTER |
  45809                           SOC_REG_FLAG_ED_CNTR,
  45810         0,
  45811         1,
  45812         soc_R1023_BCM53400_A0r_fields,
  45813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45814         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45815         383,
  45816         -1,
  45817     },
  45818 #endif /* chips */
  45819 
  45820 #if defined(BCM_53570_A0)
  45821     { /* SOC_REG_INT_XLPMIB_TSCLr */
  45822         soc_block_list[16],
  45823         soc_portreg,
  45824         1,
  45825         0,
  45826         0x15800,
  45827         SOC_REG_FLAG_64_BITS |
  45828                           SOC_REG_FLAG_COUNTER |
  45829                           SOC_REG_FLAG_ED_CNTR,
  45830         0,
  45831         1,
  45832         soc_XLMIB_RSCHCRCr_fields,
  45833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45835         371,
  45836         -1,
  45837     },
  45838 #endif /* chips */
  45839 
  45840 #if defined(BCM_53570_B0)
  45841     { /* SOC_REG_INT_XLPMIB_TSCL_BCM53570_B0r */
  45842         soc_block_list[16],
  45843         soc_portreg,
  45844         1,
  45845         0,
  45846         0x15800,
  45847         SOC_REG_FLAG_64_BITS |
  45848                           SOC_REG_FLAG_COUNTER |
  45849                           SOC_REG_FLAG_ED_CNTR,
  45850         0,
  45851         1,
  45852         soc_XLMIB_RSCHCRCr_fields,
  45853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45854         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45855         375,
  45856         -1,
  45857     },
  45858 #endif /* chips */
  45859 
  45860 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  45861     { /* SOC_REG_INT_XLPMIB_TSPARE0r */
  45862         soc_block_list[16],
  45863         soc_portreg,
  45864         1,
  45865         0,
  45866         0x17100,
  45867         SOC_REG_FLAG_64_BITS,
  45868         0,
  45869         1,
  45870         soc_TSPARE0r_fields,
  45871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45872         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45873         -1,
  45874         -1,
  45875     },
  45876 #endif /* chips */
  45877 
  45878 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  45879     { /* SOC_REG_INT_XLPMIB_TSPARE1r */
  45880         soc_block_list[16],
  45881         soc_portreg,
  45882         1,
  45883         0,
  45884         0x17200,
  45885         SOC_REG_FLAG_64_BITS,
  45886         0,
  45887         1,
  45888         soc_TSPARE0r_fields,
  45889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45890         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45891         -1,
  45892         -1,
  45893     },
  45894 #endif /* chips */
  45895 
  45896 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  45897     { /* SOC_REG_INT_XLPMIB_TSPARE2r */
  45898         soc_block_list[16],
  45899         soc_portreg,
  45900         1,
  45901         0,
  45902         0x17300,
  45903         SOC_REG_FLAG_64_BITS,
  45904         0,
  45905         1,
  45906         soc_TSPARE0r_fields,
  45907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45908         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45909         -1,
  45910         -1,
  45911     },
  45912 #endif /* chips */
  45913 
  45914 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  45915     { /* SOC_REG_INT_XLPMIB_TSPARE3r */
  45916         soc_block_list[16],
  45917         soc_portreg,
  45918         1,
  45919         0,
  45920         0x17400,
  45921         SOC_REG_FLAG_64_BITS,
  45922         0,
  45923         1,
  45924         soc_TSPARE0r_fields,
  45925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45926         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45927         -1,
  45928         -1,
  45929     },
  45930 #endif /* chips */
  45931 
  45932 #if defined(BCM_53570_A0)
  45933     { /* SOC_REG_INT_XLPMIB_TUCAr */
  45934         soc_block_list[16],
  45935         soc_portreg,
  45936         1,
  45937         0,
  45938         0x14d00,
  45939         SOC_REG_FLAG_64_BITS |
  45940                           SOC_REG_FLAG_COUNTER,
  45941         0,
  45942         1,
  45943         soc_R1023_BCM53400_A0r_fields,
  45944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45945         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45946         360,
  45947         -1,
  45948     },
  45949 #endif /* chips */
  45950 
  45951 #if defined(BCM_53570_B0)
  45952     { /* SOC_REG_INT_XLPMIB_TUCA_BCM53570_B0r */
  45953         soc_block_list[16],
  45954         soc_portreg,
  45955         1,
  45956         0,
  45957         0x14d00,
  45958         SOC_REG_FLAG_64_BITS |
  45959                           SOC_REG_FLAG_COUNTER,
  45960         0,
  45961         1,
  45962         soc_R1023_BCM53400_A0r_fields,
  45963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45964         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45965         364,
  45966         -1,
  45967     },
  45968 #endif /* chips */
  45969 
  45970 #if defined(BCM_53570_A0)
  45971     { /* SOC_REG_INT_XLPMIB_TUFLr */
  45972         soc_block_list[16],
  45973         soc_portreg,
  45974         1,
  45975         0,
  45976         0x16100,
  45977         SOC_REG_FLAG_64_BITS |
  45978                           SOC_REG_FLAG_COUNTER |
  45979                           SOC_REG_FLAG_ED_CNTR,
  45980         0,
  45981         1,
  45982         soc_R1023_BCM53400_A0r_fields,
  45983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45984         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45985         380,
  45986         -1,
  45987     },
  45988 #endif /* chips */
  45989 
  45990 #if defined(BCM_53570_B0)
  45991     { /* SOC_REG_INT_XLPMIB_TUFL_BCM53570_B0r */
  45992         soc_block_list[16],
  45993         soc_portreg,
  45994         1,
  45995         0,
  45996         0x16100,
  45997         SOC_REG_FLAG_64_BITS |
  45998                           SOC_REG_FLAG_COUNTER |
  45999                           SOC_REG_FLAG_ED_CNTR,
  46000         0,
  46001         1,
  46002         soc_R1023_BCM53400_A0r_fields,
  46003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46004         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46005         384,
  46006         -1,
  46007     },
  46008 #endif /* chips */
  46009 
  46010 #if defined(BCM_53570_A0)
  46011     { /* SOC_REG_INT_XLPMIB_TVLNr */
  46012         soc_block_list[16],
  46013         soc_portreg,
  46014         1,
  46015         0,
  46016         0x15e00,
  46017         SOC_REG_FLAG_64_BITS |
  46018                           SOC_REG_FLAG_COUNTER,
  46019         0,
  46020         1,
  46021         soc_R1023_BCM53400_A0r_fields,
  46022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46023         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46024         377,
  46025         -1,
  46026     },
  46027 #endif /* chips */
  46028 
  46029 #if defined(BCM_53570_B0)
  46030     { /* SOC_REG_INT_XLPMIB_TVLN_BCM53570_B0r */
  46031         soc_block_list[16],
  46032         soc_portreg,
  46033         1,
  46034         0,
  46035         0x15e00,
  46036         SOC_REG_FLAG_64_BITS |
  46037                           SOC_REG_FLAG_COUNTER,
  46038         0,
  46039         1,
  46040         soc_R1023_BCM53400_A0r_fields,
  46041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46042         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46043         381,
  46044         -1,
  46045     },
  46046 #endif /* chips */
  46047 
  46048 #if defined(BCM_53570_A0)
  46049     { /* SOC_REG_INT_XLPMIB_TXCFr */
  46050         soc_block_list[16],
  46051         soc_portreg,
  46052         1,
  46053         0,
  46054         0x15400,
  46055         SOC_REG_FLAG_64_BITS |
  46056                           SOC_REG_FLAG_COUNTER,
  46057         0,
  46058         1,
  46059         soc_XLMIB_RSCHCRCr_fields,
  46060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46061         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46062         367,
  46063         -1,
  46064     },
  46065 #endif /* chips */
  46066 
  46067 #if defined(BCM_53570_B0)
  46068     { /* SOC_REG_INT_XLPMIB_TXCF_BCM53570_B0r */
  46069         soc_block_list[16],
  46070         soc_portreg,
  46071         1,
  46072         0,
  46073         0x15400,
  46074         SOC_REG_FLAG_64_BITS |
  46075                           SOC_REG_FLAG_COUNTER,
  46076         0,
  46077         1,
  46078         soc_XLMIB_RSCHCRCr_fields,
  46079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46080         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46081         371,
  46082         -1,
  46083     },
  46084 #endif /* chips */
  46085 
  46086 #if defined(BCM_53570_A0)
  46087     { /* SOC_REG_INT_XLPMIB_TXCLr */
  46088         soc_block_list[16],
  46089         soc_portreg,
  46090         1,
  46091         0,
  46092         0x15b00,
  46093         SOC_REG_FLAG_64_BITS |
  46094                           SOC_REG_FLAG_COUNTER |
  46095                           SOC_REG_FLAG_ED_CNTR,
  46096         0,
  46097         1,
  46098         soc_XLMIB_RSCHCRCr_fields,
  46099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46100         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46101         374,
  46102         -1,
  46103     },
  46104 #endif /* chips */
  46105 
  46106 #if defined(BCM_53570_B0)
  46107     { /* SOC_REG_INT_XLPMIB_TXCL_BCM53570_B0r */
  46108         soc_block_list[16],
  46109         soc_portreg,
  46110         1,
  46111         0,
  46112         0x15b00,
  46113         SOC_REG_FLAG_64_BITS |
  46114                           SOC_REG_FLAG_COUNTER |
  46115                           SOC_REG_FLAG_ED_CNTR,
  46116         0,
  46117         1,
  46118         soc_XLMIB_RSCHCRCr_fields,
  46119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46120         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46121         378,
  46122         -1,
  46123     },
  46124 #endif /* chips */
  46125 
  46126 #if defined(BCM_53570_A0)
  46127     { /* SOC_REG_INT_XLPMIB_TXPFr */
  46128         soc_block_list[16],
  46129         soc_portreg,
  46130         1,
  46131         0,
  46132         0x15000,
  46133         SOC_REG_FLAG_64_BITS |
  46134                           SOC_REG_FLAG_COUNTER,
  46135         0,
  46136         1,
  46137         soc_XLMIB_RSCHCRCr_fields,
  46138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46139         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46140         363,
  46141         -1,
  46142     },
  46143 #endif /* chips */
  46144 
  46145 #if defined(BCM_53570_B0)
  46146     { /* SOC_REG_INT_XLPMIB_TXPF_BCM53570_B0r */
  46147         soc_block_list[16],
  46148         soc_portreg,
  46149         1,
  46150         0,
  46151         0x15000,
  46152         SOC_REG_FLAG_64_BITS |
  46153                           SOC_REG_FLAG_COUNTER,
  46154         0,
  46155         1,
  46156         soc_XLMIB_RSCHCRCr_fields,
  46157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46158         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46159         367,
  46160         -1,
  46161     },
  46162 #endif /* chips */
  46163 
  46164 #if defined(BCM_53570_A0)
  46165     { /* SOC_REG_INT_XLPMIB_TXPPr */
  46166         soc_block_list[16],
  46167         soc_portreg,
  46168         1,
  46169         0,
  46170         0x15100,
  46171         SOC_REG_FLAG_64_BITS |
  46172                           SOC_REG_FLAG_COUNTER,
  46173         0,
  46174         1,
  46175         soc_XLMIB_RSCHCRCr_fields,
  46176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46177         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46178         364,
  46179         -1,
  46180     },
  46181 #endif /* chips */
  46182 
  46183 #if defined(BCM_53570_B0)
  46184     { /* SOC_REG_INT_XLPMIB_TXPP_BCM53570_B0r */
  46185         soc_block_list[16],
  46186         soc_portreg,
  46187         1,
  46188         0,
  46189         0x15100,
  46190         SOC_REG_FLAG_64_BITS |
  46191                           SOC_REG_FLAG_COUNTER,
  46192         0,
  46193         1,
  46194         soc_XLMIB_RSCHCRCr_fields,
  46195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46196         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46197         368,
  46198         -1,
  46199     },
  46200 #endif /* chips */
  46201 
  46202 #if defined(BCM_53570_A0)
  46203     { /* SOC_REG_INT_XLPMIB_TX_EEE_LPI_DURATION_COUNTERr */
  46204         soc_block_list[16],
  46205         soc_portreg,
  46206         1,
  46207         0,
  46208         0x16b00,
  46209         SOC_REG_FLAG_64_BITS |
  46210                           SOC_REG_FLAG_COUNTER,
  46211         0,
  46212         1,
  46213         soc_RALN_BCM53400_A0r_fields,
  46214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46215         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46216         390,
  46217         -1,
  46218     },
  46219 #endif /* chips */
  46220 
  46221 #if defined(BCM_53570_B0)
  46222     { /* SOC_REG_INT_XLPMIB_TX_EEE_LPI_DURATION_COUNTER_BCM53570_B0r */
  46223         soc_block_list[16],
  46224         soc_portreg,
  46225         1,
  46226         0,
  46227         0x16b00,
  46228         SOC_REG_FLAG_64_BITS |
  46229                           SOC_REG_FLAG_COUNTER,
  46230         0,
  46231         1,
  46232         soc_RALN_BCM53400_A0r_fields,
  46233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46234         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46235         394,
  46236         -1,
  46237     },
  46238 #endif /* chips */
  46239 
  46240 #if defined(BCM_53570_A0)
  46241     { /* SOC_REG_INT_XLPMIB_TX_EEE_LPI_EVENT_COUNTERr */
  46242         soc_block_list[16],
  46243         soc_portreg,
  46244         1,
  46245         0,
  46246         0x16a00,
  46247         SOC_REG_FLAG_64_BITS |
  46248                           SOC_REG_FLAG_COUNTER,
  46249         0,
  46250         1,
  46251         soc_RALN_BCM53400_A0r_fields,
  46252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46253         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46254         389,
  46255         -1,
  46256     },
  46257 #endif /* chips */
  46258 
  46259 #if defined(BCM_53570_B0)
  46260     { /* SOC_REG_INT_XLPMIB_TX_EEE_LPI_EVENT_COUNTER_BCM53570_B0r */
  46261         soc_block_list[16],
  46262         soc_portreg,
  46263         1,
  46264         0,
  46265         0x16a00,
  46266         SOC_REG_FLAG_64_BITS |
  46267                           SOC_REG_FLAG_COUNTER,
  46268         0,
  46269         1,
  46270         soc_RALN_BCM53400_A0r_fields,
  46271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46272         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46273         393,
  46274         -1,
  46275     },
  46276 #endif /* chips */
  46277 
  46278 #if defined(BCM_53570_A0)
  46279     { /* SOC_REG_INT_XLPMIB_TX_HCFC_COUNTERr */
  46280         soc_block_list[16],
  46281         soc_portreg,
  46282         1,
  46283         0,
  46284         0x16d00,
  46285         SOC_REG_FLAG_64_BITS |
  46286                           SOC_REG_FLAG_COUNTER,
  46287         0,
  46288         1,
  46289         soc_XLMIB_RSCHCRCr_fields,
  46290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46291         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46292         392,
  46293         -1,
  46294     },
  46295 #endif /* chips */
  46296 
  46297 #if defined(BCM_53570_B0)
  46298     { /* SOC_REG_INT_XLPMIB_TX_HCFC_COUNTER_BCM53570_B0r */
  46299         soc_block_list[16],
  46300         soc_portreg,
  46301         1,
  46302         0,
  46303         0x16d00,
  46304         SOC_REG_FLAG_64_BITS |
  46305                           SOC_REG_FLAG_COUNTER,
  46306         0,
  46307         1,
  46308         soc_XLMIB_RSCHCRCr_fields,
  46309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46310         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46311         396,
  46312         -1,
  46313     },
  46314 #endif /* chips */
  46315 
  46316 #if defined(BCM_53570_A0)
  46317     { /* SOC_REG_INT_XLPMIB_TX_LLFC_LOG_COUNTERr */
  46318         soc_block_list[16],
  46319         soc_portreg,
  46320         1,
  46321         0,
  46322         0x16c00,
  46323         SOC_REG_FLAG_64_BITS |
  46324                           SOC_REG_FLAG_COUNTER,
  46325         0,
  46326         1,
  46327         soc_RALN_BCM53400_A0r_fields,
  46328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46329         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46330         391,
  46331         -1,
  46332     },
  46333 #endif /* chips */
  46334 
  46335 #if defined(BCM_53570_B0)
  46336     { /* SOC_REG_INT_XLPMIB_TX_LLFC_LOG_COUNTER_BCM53570_B0r */
  46337         soc_block_list[16],
  46338         soc_portreg,
  46339         1,
  46340         0,
  46341         0x16c00,
  46342         SOC_REG_FLAG_64_BITS |
  46343                           SOC_REG_FLAG_COUNTER,
  46344         0,
  46345         1,
  46346         soc_RALN_BCM53400_A0r_fields,
  46347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46348         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46349         395,
  46350         -1,
  46351     },
  46352 #endif /* chips */
  46353 
  46354 #if defined(BCM_53570_A0)
  46355     { /* SOC_REG_INT_XLPMIB_XTHOLr */
  46356         soc_block_list[16],
  46357         soc_portreg,
  46358         1,
  46359         0,
  46360         0x17000,
  46361         SOC_REG_FLAG_64_BITS |
  46362                           SOC_REG_FLAG_COUNTER,
  46363         0,
  46364         1,
  46365         soc_XLPMIB_XTHOLr_fields,
  46366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46367         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46368         395,
  46369         -1,
  46370     },
  46371 #endif /* chips */
  46372 
  46373 #if defined(BCM_53570_B0)
  46374     { /* SOC_REG_INT_XLPMIB_XTHOL_BCM53570_B0r */
  46375         soc_block_list[16],
  46376         soc_portreg,
  46377         1,
  46378         0,
  46379         0x17000,
  46380         SOC_REG_FLAG_64_BITS |
  46381                           SOC_REG_FLAG_COUNTER,
  46382         0,
  46383         1,
  46384         soc_XLPMIB_XTHOLr_fields,
  46385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46386         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46387         399,
  46388         -1,
  46389     },
  46390 #endif /* chips */
  46391 
  46392 #if defined(BCM_56150_A0)
  46393     { /* SOC_REG_INT_XLPORT_BOD_OVERFLOW_ERRORr */
  46394         soc_block_list[16],
  46395         soc_genreg,
  46396         1,
  46397         0,
  46398         0x2022700,
  46399         SOC_REG_FLAG_RO,
  46400         0,
  46401         1,
  46402         soc_XLPORT_BOD_OVERFLOW_ERRORr_fields,
  46403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46404         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  46405         -1,
  46406         -1,
  46407     },
  46408 #endif /* chips */
  46409 
  46410 #if defined(BCM_56150_A0)
  46411     { /* SOC_REG_INT_XLPORT_BOD_XLP0_ECC_STATUSr */
  46412         soc_block_list[16],
  46413         soc_genreg,
  46414         1,
  46415         0,
  46416         0x2022100,
  46417         0,
  46418         0,
  46419         4,
  46420         soc_PGW_BOD_XLP0_ECC_STATUSr_fields,
  46421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46422         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46423         -1,
  46424         -1,
  46425     },
  46426 #endif /* chips */
  46427 
  46428 #if defined(BCM_2801PM_A0)
  46429     { /* SOC_REG_INT_XLPORT_CNTMAXSIZEr */
  46430         soc_block_list[56],
  46431         soc_portreg,
  46432         1,
  46433         0,
  46434         0x20100,
  46435         0,
  46436         0,
  46437         1,
  46438         soc_CLPORT_CNTMAXSIZEr_fields,
  46439         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46440         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46441         -1,
  46442         -1,
  46443     },
  46444 #endif /* chips */
  46445 
  46446 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  46447     defined(BCM_56670_B0)
  46448     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM53400_A0r */
  46449         soc_block_list[16],
  46450         soc_portreg,
  46451         1,
  46452         0,
  46453         0x20100,
  46454         0,
  46455         0,
  46456         1,
  46457         soc_CLPORT_CNTMAXSIZEr_fields,
  46458         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46459         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46460         -1,
  46461         -1,
  46462     },
  46463 #endif /* chips */
  46464 
  46465 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  46466     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM53570_A0r */
  46467         soc_block_list[16],
  46468         soc_portreg,
  46469         1,
  46470         0,
  46471         0x20100,
  46472         0,
  46473         0,
  46474         1,
  46475         soc_CLPORT_CNTMAXSIZEr_fields,
  46476         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46477         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46478         -1,
  46479         -1,
  46480     },
  46481 #endif /* chips */
  46482 
  46483 #if defined(BCM_56150_A0)
  46484     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM56150_A0r */
  46485         soc_block_list[16],
  46486         soc_portreg,
  46487         1,
  46488         0,
  46489         0x20100,
  46490         0,
  46491         0,
  46492         1,
  46493         soc_PORT_CNTMAXSIZE_BCM56640_A0r_fields,
  46494         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46495         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46496         -1,
  46497         -1,
  46498     },
  46499 #endif /* chips */
  46500 
  46501 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  46502     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM56160_A0r */
  46503         soc_block_list[16],
  46504         soc_portreg,
  46505         1,
  46506         0,
  46507         0x20100,
  46508         0,
  46509         0,
  46510         1,
  46511         soc_CLPORT_CNTMAXSIZEr_fields,
  46512         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46513         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46514         -1,
  46515         -1,
  46516     },
  46517 #endif /* chips */
  46518 
  46519 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46520     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM56260_A0r */
  46521         soc_block_list[16],
  46522         soc_portreg,
  46523         1,
  46524         0,
  46525         0x20100,
  46526         0,
  46527         0,
  46528         1,
  46529         soc_CLPORT_CNTMAXSIZEr_fields,
  46530         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46531         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46532         -1,
  46533         -1,
  46534     },
  46535 #endif /* chips */
  46536 
  46537 #if defined(BCM_56370_A0)
  46538     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM56370_A0r */
  46539         soc_block_list[16],
  46540         soc_portreg,
  46541         1,
  46542         0,
  46543         0x20100,
  46544         0,
  46545         0,
  46546         1,
  46547         soc_CLPORT_CNTMAXSIZEr_fields,
  46548         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46549         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46550         -1,
  46551         -1,
  46552         3,
  46553     },
  46554 #endif /* chips */
  46555 
  46556 #if defined(BCM_56560_A0)
  46557     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM56560_A0r */
  46558         soc_block_list[217],
  46559         soc_portreg,
  46560         1,
  46561         0,
  46562         0x20100,
  46563         0,
  46564         0,
  46565         1,
  46566         soc_CLPORT_CNTMAXSIZEr_fields,
  46567         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46568         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46569         -1,
  46570         -1,
  46571     },
  46572 #endif /* chips */
  46573 
  46574 #if defined(BCM_56560_B0)
  46575     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM56560_B0r */
  46576         soc_block_list[16],
  46577         soc_portreg,
  46578         1,
  46579         0,
  46580         0x20100,
  46581         0,
  46582         0,
  46583         1,
  46584         soc_CLPORT_CNTMAXSIZEr_fields,
  46585         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46586         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46587         -1,
  46588         -1,
  46589     },
  46590 #endif /* chips */
  46591 
  46592 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  46593     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  46594     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  46595     defined(BCM_56980_B0)
  46596     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM56960_A0r */
  46597         soc_block_list[16],
  46598         soc_portreg,
  46599         1,
  46600         0,
  46601         0x20100,
  46602         0,
  46603         0,
  46604         1,
  46605         soc_CLPORT_CNTMAXSIZEr_fields,
  46606         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46607         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46608         -1,
  46609         -1,
  46610         3,
  46611     },
  46612 #endif /* chips */
  46613 
  46614 #if defined(BCM_88270_A0)
  46615     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM88270_A0r */
  46616         soc_block_list[56],
  46617         soc_portreg,
  46618         1,
  46619         0,
  46620         0x20100,
  46621         0,
  46622         0,
  46623         1,
  46624         soc_XLPORT_CNTMAXSIZE_BCM88270_A0r_fields,
  46625         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46626         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46627         -1,
  46628         -1,
  46629     },
  46630 #endif /* chips */
  46631 
  46632 #if defined(BCM_88375_A0)
  46633     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM88375_A0r */
  46634         soc_block_list[56],
  46635         soc_portreg,
  46636         1,
  46637         0,
  46638         0x20100,
  46639         0,
  46640         0,
  46641         1,
  46642         soc_XLPORT_CNTMAXSIZE_BCM88375_A0r_fields,
  46643         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46644         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46645         -1,
  46646         -1,
  46647     },
  46648 #endif /* chips */
  46649 
  46650 #if defined(BCM_88375_B0)
  46651     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM88375_B0r */
  46652         soc_block_list[56],
  46653         soc_portreg,
  46654         1,
  46655         0,
  46656         0x20100,
  46657         0,
  46658         0,
  46659         1,
  46660         soc_XLPORT_CNTMAXSIZE_BCM88375_B0r_fields,
  46661         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46662         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46663         -1,
  46664         -1,
  46665     },
  46666 #endif /* chips */
  46667 
  46668 #if defined(BCM_88470_A0)
  46669     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM88470_A0r */
  46670         soc_block_list[56],
  46671         soc_portreg,
  46672         1,
  46673         0,
  46674         0x20100,
  46675         0,
  46676         0,
  46677         1,
  46678         soc_XLPORT_CNTMAXSIZE_BCM88470_A0r_fields,
  46679         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46680         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46681         -1,
  46682         -1,
  46683     },
  46684 #endif /* chips */
  46685 
  46686 #if defined(BCM_88470_B0)
  46687     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM88470_B0r */
  46688         soc_block_list[56],
  46689         soc_portreg,
  46690         1,
  46691         0,
  46692         0x20100,
  46693         0,
  46694         0,
  46695         1,
  46696         soc_XLPORT_CNTMAXSIZE_BCM88470_B0r_fields,
  46697         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46698         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46699         -1,
  46700         -1,
  46701     },
  46702 #endif /* chips */
  46703 
  46704 #if defined(BCM_88675_A0)
  46705     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM88675_A0r */
  46706         soc_block_list[56],
  46707         soc_portreg,
  46708         1,
  46709         0,
  46710         0x20100,
  46711         0,
  46712         0,
  46713         1,
  46714         soc_XLPORT_CNTMAXSIZEr_fields,
  46715         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46716         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46717         -1,
  46718         -1,
  46719     },
  46720 #endif /* chips */
  46721 
  46722 #if defined(BCM_88675_B0)
  46723     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM88675_B0r */
  46724         soc_block_list[56],
  46725         soc_portreg,
  46726         1,
  46727         0,
  46728         0x20100,
  46729         0,
  46730         0,
  46731         1,
  46732         soc_XLPORT_CNTMAXSIZE_BCM88675_B0r_fields,
  46733         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46734         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46735         -1,
  46736         -1,
  46737     },
  46738 #endif /* chips */
  46739 
  46740 #if defined(BCM_88680_A0)
  46741     { /* SOC_REG_INT_XLPORT_CNTMAXSIZE_BCM88680_A0r */
  46742         soc_block_list[56],
  46743         soc_portreg,
  46744         1,
  46745         0,
  46746         0x20100,
  46747         0,
  46748         0,
  46749         1,
  46750         soc_XLPORT_CNTMAXSIZE_BCM88680_A0r_fields,
  46751         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  46752         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  46753         -1,
  46754         -1,
  46755     },
  46756 #endif /* chips */
  46757 
  46758 #if defined(BCM_56840_A0)
  46759     { /* SOC_REG_INT_XLPORT_CONFIGr */
  46760         soc_block_list[16],
  46761         soc_portreg,
  46762         1,
  46763         0,
  46764         0x200,
  46765         0,
  46766         0,
  46767         12,
  46768         soc_XLPORT_CONFIGr_fields,
  46769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46770         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  46771         -1,
  46772         -1,
  46773     },
  46774 #endif /* chips */
  46775 
  46776 #if defined(BCM_2801PM_A0)
  46777     { /* SOC_REG_INT_XLPORT_CONFIG_BCM2801PM_A0r */
  46778         soc_block_list[56],
  46779         soc_portreg,
  46780         1,
  46781         0,
  46782         0x20000,
  46783         0,
  46784         0,
  46785         6,
  46786         soc_CLPORT_CONFIGr_fields,
  46787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46788         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46789         -1,
  46790         -1,
  46791     },
  46792 #endif /* chips */
  46793 
  46794 #if defined(BCM_53400_A0)
  46795     { /* SOC_REG_INT_XLPORT_CONFIG_BCM53400_A0r */
  46796         soc_block_list[16],
  46797         soc_portreg,
  46798         1,
  46799         0,
  46800         0x20000,
  46801         0,
  46802         0,
  46803         6,
  46804         soc_XLPORT_CONFIG_BCM53400_A0r_fields,
  46805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46806         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46807         -1,
  46808         -1,
  46809     },
  46810 #endif /* chips */
  46811 
  46812 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  46813     { /* SOC_REG_INT_XLPORT_CONFIG_BCM53570_A0r */
  46814         soc_block_list[16],
  46815         soc_portreg,
  46816         1,
  46817         0,
  46818         0x20000,
  46819         0,
  46820         0,
  46821         6,
  46822         soc_CLPORT_CONFIG_BCM56965_A0r_fields,
  46823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46824         SOC_RESET_MASK_DEC(0x0000fe01, 0x00000000)
  46825         -1,
  46826         -1,
  46827     },
  46828 #endif /* chips */
  46829 
  46830 #if defined(BCM_56150_A0)
  46831     { /* SOC_REG_INT_XLPORT_CONFIG_BCM56150_A0r */
  46832         soc_block_list[16],
  46833         soc_portreg,
  46834         1,
  46835         0,
  46836         0x20000,
  46837         0,
  46838         0,
  46839         6,
  46840         soc_XLPORT_CONFIG_BCM56850_A0r_fields,
  46841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46842         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46843         -1,
  46844         -1,
  46845     },
  46846 #endif /* chips */
  46847 
  46848 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  46849     { /* SOC_REG_INT_XLPORT_CONFIG_BCM56160_A0r */
  46850         soc_block_list[16],
  46851         soc_portreg,
  46852         1,
  46853         0,
  46854         0x20000,
  46855         0,
  46856         0,
  46857         6,
  46858         soc_XLPORT_CONFIG_BCM53400_A0r_fields,
  46859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46860         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46861         -1,
  46862         -1,
  46863     },
  46864 #endif /* chips */
  46865 
  46866 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46867     { /* SOC_REG_INT_XLPORT_CONFIG_BCM56260_A0r */
  46868         soc_block_list[16],
  46869         soc_portreg,
  46870         1,
  46871         0,
  46872         0x20000,
  46873         0,
  46874         0,
  46875         6,
  46876         soc_XLPORT_CONFIG_BCM53400_A0r_fields,
  46877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46878         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46879         -1,
  46880         -1,
  46881     },
  46882 #endif /* chips */
  46883 
  46884 #if defined(BCM_56370_A0)
  46885     { /* SOC_REG_INT_XLPORT_CONFIG_BCM56370_A0r */
  46886         soc_block_list[16],
  46887         soc_portreg,
  46888         1,
  46889         0,
  46890         0x20000,
  46891         0,
  46892         0,
  46893         6,
  46894         soc_CLPORT_CONFIG_BCM56965_A0r_fields,
  46895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46896         SOC_RESET_MASK_DEC(0x0000fe01, 0x00000000)
  46897         -1,
  46898         -1,
  46899         3,
  46900     },
  46901 #endif /* chips */
  46902 
  46903 #if defined(BCM_56560_A0)
  46904     { /* SOC_REG_INT_XLPORT_CONFIG_BCM56560_A0r */
  46905         soc_block_list[217],
  46906         soc_portreg,
  46907         1,
  46908         0,
  46909         0x20000,
  46910         0,
  46911         0,
  46912         6,
  46913         soc_XLPORT_CONFIG_BCM53400_A0r_fields,
  46914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46915         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46916         -1,
  46917         -1,
  46918     },
  46919 #endif /* chips */
  46920 
  46921 #if defined(BCM_56560_B0)
  46922     { /* SOC_REG_INT_XLPORT_CONFIG_BCM56560_B0r */
  46923         soc_block_list[16],
  46924         soc_portreg,
  46925         1,
  46926         0,
  46927         0x20000,
  46928         0,
  46929         0,
  46930         6,
  46931         soc_XLPORT_CONFIG_BCM53400_A0r_fields,
  46932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46933         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46934         -1,
  46935         -1,
  46936     },
  46937 #endif /* chips */
  46938 
  46939 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  46940     { /* SOC_REG_INT_XLPORT_CONFIG_BCM56670_A0r */
  46941         soc_block_list[16],
  46942         soc_portreg,
  46943         1,
  46944         0,
  46945         0x20000,
  46946         0,
  46947         0,
  46948         6,
  46949         soc_CLPORT_CONFIG_BCM56965_A0r_fields,
  46950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46951         SOC_RESET_MASK_DEC(0x0000fe01, 0x00000000)
  46952         -1,
  46953         -1,
  46954     },
  46955 #endif /* chips */
  46956 
  46957 #if defined(BCM_56840_B0)
  46958     { /* SOC_REG_INT_XLPORT_CONFIG_BCM56840_B0r */
  46959         soc_block_list[16],
  46960         soc_portreg,
  46961         1,
  46962         0,
  46963         0x200,
  46964         0,
  46965         0,
  46966         12,
  46967         soc_XLPORT_CONFIGr_fields,
  46968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46969         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  46970         -1,
  46971         -1,
  46972     },
  46973 #endif /* chips */
  46974 
  46975 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  46976     { /* SOC_REG_INT_XLPORT_CONFIG_BCM56850_A0r */
  46977         soc_block_list[16],
  46978         soc_portreg,
  46979         1,
  46980         0,
  46981         0x20000,
  46982         0,
  46983         0,
  46984         6,
  46985         soc_XLPORT_CONFIG_BCM56850_A0r_fields,
  46986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46987         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  46988         -1,
  46989         -1,
  46990     },
  46991 #endif /* chips */
  46992 
  46993 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  46994     { /* SOC_REG_INT_XLPORT_CONFIG_BCM56960_A0r */
  46995         soc_block_list[16],
  46996         soc_portreg,
  46997         1,
  46998         0,
  46999         0x20000,
  47000         0,
  47001         0,
  47002         6,
  47003         soc_XLPORT_CONFIG_BCM53400_A0r_fields,
  47004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47005         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47006         -1,
  47007         -1,
  47008         3,
  47009     },
  47010 #endif /* chips */
  47011 
  47012 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  47013     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  47014     defined(BCM_56980_B0)
  47015     { /* SOC_REG_INT_XLPORT_CONFIG_BCM56970_A0r */
  47016         soc_block_list[16],
  47017         soc_portreg,
  47018         1,
  47019         0,
  47020         0x20000,
  47021         0,
  47022         0,
  47023         6,
  47024         soc_CLPORT_CONFIG_BCM56965_A0r_fields,
  47025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47026         SOC_RESET_MASK_DEC(0x0000fe01, 0x00000000)
  47027         -1,
  47028         -1,
  47029         3,
  47030     },
  47031 #endif /* chips */
  47032 
  47033 #if defined(BCM_88270_A0)
  47034     { /* SOC_REG_INT_XLPORT_CONFIG_BCM88270_A0r */
  47035         soc_block_list[56],
  47036         soc_portreg,
  47037         1,
  47038         0,
  47039         0x20000,
  47040         0,
  47041         0,
  47042         6,
  47043         soc_XLPORT_CONFIG_BCM88270_A0r_fields,
  47044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47045         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47046         -1,
  47047         -1,
  47048     },
  47049 #endif /* chips */
  47050 
  47051 #if defined(BCM_88375_A0)
  47052     { /* SOC_REG_INT_XLPORT_CONFIG_BCM88375_A0r */
  47053         soc_block_list[56],
  47054         soc_portreg,
  47055         1,
  47056         0,
  47057         0x20000,
  47058         0,
  47059         0,
  47060         6,
  47061         soc_XLPORT_CONFIG_BCM88375_A0r_fields,
  47062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47063         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47064         -1,
  47065         -1,
  47066     },
  47067 #endif /* chips */
  47068 
  47069 #if defined(BCM_88375_B0)
  47070     { /* SOC_REG_INT_XLPORT_CONFIG_BCM88375_B0r */
  47071         soc_block_list[56],
  47072         soc_portreg,
  47073         1,
  47074         0,
  47075         0x20000,
  47076         0,
  47077         0,
  47078         6,
  47079         soc_XLPORT_CONFIG_BCM88375_B0r_fields,
  47080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47081         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47082         -1,
  47083         -1,
  47084     },
  47085 #endif /* chips */
  47086 
  47087 #if defined(BCM_88470_A0)
  47088     { /* SOC_REG_INT_XLPORT_CONFIG_BCM88470_A0r */
  47089         soc_block_list[56],
  47090         soc_portreg,
  47091         1,
  47092         0,
  47093         0x20000,
  47094         0,
  47095         0,
  47096         6,
  47097         soc_XLPORT_CONFIG_BCM88470_A0r_fields,
  47098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47099         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47100         -1,
  47101         -1,
  47102     },
  47103 #endif /* chips */
  47104 
  47105 #if defined(BCM_88470_B0)
  47106     { /* SOC_REG_INT_XLPORT_CONFIG_BCM88470_B0r */
  47107         soc_block_list[56],
  47108         soc_portreg,
  47109         1,
  47110         0,
  47111         0x20000,
  47112         0,
  47113         0,
  47114         6,
  47115         soc_XLPORT_CONFIG_BCM88470_B0r_fields,
  47116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47117         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47118         -1,
  47119         -1,
  47120     },
  47121 #endif /* chips */
  47122 
  47123 #if defined(BCM_88675_A0)
  47124     { /* SOC_REG_INT_XLPORT_CONFIG_BCM88675_A0r */
  47125         soc_block_list[56],
  47126         soc_portreg,
  47127         1,
  47128         0,
  47129         0x20000,
  47130         0,
  47131         0,
  47132         6,
  47133         soc_XLPORT_CONFIG_BCM88675_A0r_fields,
  47134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47135         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47136         -1,
  47137         -1,
  47138     },
  47139 #endif /* chips */
  47140 
  47141 #if defined(BCM_88675_B0)
  47142     { /* SOC_REG_INT_XLPORT_CONFIG_BCM88675_B0r */
  47143         soc_block_list[56],
  47144         soc_portreg,
  47145         1,
  47146         0,
  47147         0x20000,
  47148         0,
  47149         0,
  47150         6,
  47151         soc_XLPORT_CONFIG_BCM88675_B0r_fields,
  47152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47153         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47154         -1,
  47155         -1,
  47156     },
  47157 #endif /* chips */
  47158 
  47159 #if defined(BCM_88680_A0)
  47160     { /* SOC_REG_INT_XLPORT_CONFIG_BCM88680_A0r */
  47161         soc_block_list[56],
  47162         soc_portreg,
  47163         1,
  47164         0,
  47165         0x20000,
  47166         0,
  47167         0,
  47168         6,
  47169         soc_XLPORT_CONFIG_BCM88680_A0r_fields,
  47170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47171         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47172         -1,
  47173         -1,
  47174     },
  47175 #endif /* chips */
  47176 
  47177 #if defined(BCM_88732_A0)
  47178     { /* SOC_REG_INT_XLPORT_CONFIG_BCM88732_A0r */
  47179         soc_block_list[16],
  47180         soc_portreg,
  47181         1,
  47182         0,
  47183         0x200,
  47184         0,
  47185         0,
  47186         12,
  47187         soc_XLPORT_CONFIGr_fields,
  47188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47189         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  47190         -1,
  47191         -1,
  47192     },
  47193 #endif /* chips */
  47194 
  47195 #if defined(BCM_56840_A0)
  47196     { /* SOC_REG_INT_XLPORT_ECC_CONTROLr */
  47197         soc_block_list[16],
  47198         soc_genreg,
  47199         1,
  47200         0,
  47201         0x80242,
  47202         0,
  47203         0,
  47204         3,
  47205         soc_XLPORT_ECC_CONTROLr_fields,
  47206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47207         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  47208         -1,
  47209         -1,
  47210     },
  47211 #endif /* chips */
  47212 
  47213 #if defined(BCM_2801PM_A0)
  47214     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM2801PM_A0r */
  47215         soc_block_list[56],
  47216         soc_genreg,
  47217         1,
  47218         0,
  47219         0x2021a00,
  47220         0,
  47221         0,
  47222         6,
  47223         soc_CLPORT_ECC_CONTROLr_fields,
  47224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47225         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47226         -1,
  47227         -1,
  47228     },
  47229 #endif /* chips */
  47230 
  47231 #if defined(BCM_53400_A0)
  47232     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM53400_A0r */
  47233         soc_block_list[16],
  47234         soc_genreg,
  47235         1,
  47236         0,
  47237         0x2021a00,
  47238         0,
  47239         0,
  47240         6,
  47241         soc_XLPORT_ECC_CONTROL_BCM53400_A0r_fields,
  47242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47243         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47244         -1,
  47245         -1,
  47246     },
  47247 #endif /* chips */
  47248 
  47249 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  47250     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM53570_A0r */
  47251         soc_block_list[16],
  47252         soc_genreg,
  47253         1,
  47254         0,
  47255         0x2021a00,
  47256         0,
  47257         0,
  47258         13,
  47259         soc_XLPORT_ECC_CONTROL_BCM53570_A0r_fields,
  47260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47261         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  47262         -1,
  47263         -1,
  47264     },
  47265 #endif /* chips */
  47266 
  47267 #if defined(BCM_56150_A0)
  47268     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM56150_A0r */
  47269         soc_block_list[16],
  47270         soc_genreg,
  47271         1,
  47272         0,
  47273         0x2021a00,
  47274         0,
  47275         0,
  47276         9,
  47277         soc_XLPORT_ECC_CONTROL_BCM56150_A0r_fields,
  47278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47279         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  47280         -1,
  47281         -1,
  47282     },
  47283 #endif /* chips */
  47284 
  47285 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  47286     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM56160_A0r */
  47287         soc_block_list[16],
  47288         soc_genreg,
  47289         1,
  47290         0,
  47291         0x2021a00,
  47292         0,
  47293         0,
  47294         6,
  47295         soc_XLPORT_ECC_CONTROL_BCM53400_A0r_fields,
  47296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47297         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47298         -1,
  47299         -1,
  47300     },
  47301 #endif /* chips */
  47302 
  47303 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47304     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM56260_A0r */
  47305         soc_block_list[16],
  47306         soc_genreg,
  47307         1,
  47308         0,
  47309         0x2021a00,
  47310         0,
  47311         0,
  47312         6,
  47313         soc_XLPORT_ECC_CONTROL_BCM53400_A0r_fields,
  47314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47315         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47316         -1,
  47317         -1,
  47318     },
  47319 #endif /* chips */
  47320 
  47321 #if defined(BCM_56370_A0)
  47322     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM56370_A0r */
  47323         soc_block_list[16],
  47324         soc_genreg,
  47325         1,
  47326         0,
  47327         0x2021a00,
  47328         0,
  47329         0,
  47330         6,
  47331         soc_XLPORT_ECC_CONTROL_BCM53400_A0r_fields,
  47332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47333         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47334         -1,
  47335         -1,
  47336         3,
  47337     },
  47338 #endif /* chips */
  47339 
  47340 #if defined(BCM_56560_A0)
  47341     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM56560_A0r */
  47342         soc_block_list[217],
  47343         soc_genreg,
  47344         1,
  47345         0,
  47346         0x2021a00,
  47347         0,
  47348         0,
  47349         6,
  47350         soc_XLPORT_ECC_CONTROL_BCM53400_A0r_fields,
  47351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47352         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47353         -1,
  47354         -1,
  47355     },
  47356 #endif /* chips */
  47357 
  47358 #if defined(BCM_56560_B0)
  47359     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM56560_B0r */
  47360         soc_block_list[16],
  47361         soc_genreg,
  47362         1,
  47363         0,
  47364         0x2021a00,
  47365         0,
  47366         0,
  47367         6,
  47368         soc_XLPORT_ECC_CONTROL_BCM53400_A0r_fields,
  47369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47370         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47371         -1,
  47372         -1,
  47373     },
  47374 #endif /* chips */
  47375 
  47376 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  47377     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM56670_A0r */
  47378         soc_block_list[16],
  47379         soc_genreg,
  47380         1,
  47381         0,
  47382         0x2021a00,
  47383         0,
  47384         0,
  47385         13,
  47386         soc_XLPORT_ECC_CONTROL_BCM53570_A0r_fields,
  47387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47388         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  47389         -1,
  47390         -1,
  47391     },
  47392 #endif /* chips */
  47393 
  47394 #if defined(BCM_56840_B0)
  47395     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM56840_B0r */
  47396         soc_block_list[16],
  47397         soc_genreg,
  47398         1,
  47399         0,
  47400         0x80242,
  47401         0,
  47402         0,
  47403         3,
  47404         soc_XLPORT_ECC_CONTROLr_fields,
  47405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47406         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  47407         -1,
  47408         -1,
  47409     },
  47410 #endif /* chips */
  47411 
  47412 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  47413     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  47414     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  47415     defined(BCM_56980_B0)
  47416     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM56960_A0r */
  47417         soc_block_list[16],
  47418         soc_genreg,
  47419         1,
  47420         0,
  47421         0x2021a00,
  47422         0,
  47423         0,
  47424         6,
  47425         soc_XLPORT_ECC_CONTROL_BCM53400_A0r_fields,
  47426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47427         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47428         -1,
  47429         -1,
  47430         3,
  47431     },
  47432 #endif /* chips */
  47433 
  47434 #if defined(BCM_88270_A0)
  47435     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM88270_A0r */
  47436         soc_block_list[56],
  47437         soc_genreg,
  47438         1,
  47439         0,
  47440         0x2021a00,
  47441         0,
  47442         0,
  47443         6,
  47444         soc_XLPORT_ECC_CONTROL_BCM88270_A0r_fields,
  47445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47446         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47447         -1,
  47448         -1,
  47449     },
  47450 #endif /* chips */
  47451 
  47452 #if defined(BCM_88375_A0)
  47453     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM88375_A0r */
  47454         soc_block_list[56],
  47455         soc_genreg,
  47456         1,
  47457         0,
  47458         0x2021a00,
  47459         0,
  47460         0,
  47461         6,
  47462         soc_XLPORT_ECC_CONTROL_BCM88375_A0r_fields,
  47463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47464         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47465         -1,
  47466         -1,
  47467     },
  47468 #endif /* chips */
  47469 
  47470 #if defined(BCM_88375_B0)
  47471     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM88375_B0r */
  47472         soc_block_list[56],
  47473         soc_genreg,
  47474         1,
  47475         0,
  47476         0x2021a00,
  47477         0,
  47478         0,
  47479         6,
  47480         soc_XLPORT_ECC_CONTROL_BCM88375_B0r_fields,
  47481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47482         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47483         -1,
  47484         -1,
  47485     },
  47486 #endif /* chips */
  47487 
  47488 #if defined(BCM_88470_A0)
  47489     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM88470_A0r */
  47490         soc_block_list[56],
  47491         soc_genreg,
  47492         1,
  47493         0,
  47494         0x2021a00,
  47495         0,
  47496         0,
  47497         6,
  47498         soc_XLPORT_ECC_CONTROL_BCM88470_A0r_fields,
  47499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47500         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47501         -1,
  47502         -1,
  47503     },
  47504 #endif /* chips */
  47505 
  47506 #if defined(BCM_88470_B0)
  47507     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM88470_B0r */
  47508         soc_block_list[56],
  47509         soc_genreg,
  47510         1,
  47511         0,
  47512         0x2021a00,
  47513         0,
  47514         0,
  47515         6,
  47516         soc_XLPORT_ECC_CONTROL_BCM88470_B0r_fields,
  47517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47518         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47519         -1,
  47520         -1,
  47521     },
  47522 #endif /* chips */
  47523 
  47524 #if defined(BCM_88675_A0)
  47525     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM88675_A0r */
  47526         soc_block_list[56],
  47527         soc_genreg,
  47528         1,
  47529         0,
  47530         0x2021a00,
  47531         0,
  47532         0,
  47533         6,
  47534         soc_XLPORT_ECC_CONTROL_BCM88675_A0r_fields,
  47535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47536         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47537         -1,
  47538         -1,
  47539     },
  47540 #endif /* chips */
  47541 
  47542 #if defined(BCM_88675_B0)
  47543     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM88675_B0r */
  47544         soc_block_list[56],
  47545         soc_genreg,
  47546         1,
  47547         0,
  47548         0x2021a00,
  47549         0,
  47550         0,
  47551         6,
  47552         soc_XLPORT_ECC_CONTROL_BCM88675_B0r_fields,
  47553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47554         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47555         -1,
  47556         -1,
  47557     },
  47558 #endif /* chips */
  47559 
  47560 #if defined(BCM_88680_A0)
  47561     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM88680_A0r */
  47562         soc_block_list[56],
  47563         soc_genreg,
  47564         1,
  47565         0,
  47566         0x2021a00,
  47567         0,
  47568         0,
  47569         6,
  47570         soc_XLPORT_ECC_CONTROL_BCM88680_A0r_fields,
  47571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47572         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47573         -1,
  47574         -1,
  47575     },
  47576 #endif /* chips */
  47577 
  47578 #if defined(BCM_88732_A0)
  47579     { /* SOC_REG_INT_XLPORT_ECC_CONTROL_BCM88732_A0r */
  47580         soc_block_list[16],
  47581         soc_genreg,
  47582         1,
  47583         0,
  47584         0x80242,
  47585         0,
  47586         0,
  47587         3,
  47588         soc_XLPORT_ECC_CONTROLr_fields,
  47589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47590         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  47591         -1,
  47592         -1,
  47593     },
  47594 #endif /* chips */
  47595 
  47596 #if defined(BCM_2801PM_A0)
  47597     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATEr */
  47598         soc_block_list[56],
  47599         soc_genreg,
  47600         1,
  47601         0,
  47602         0x2020e00,
  47603         0,
  47604         0,
  47605         1,
  47606         soc_CLPORT_EEE_CLOCK_GATEr_fields,
  47607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47608         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47609         -1,
  47610         -1,
  47611     },
  47612 #endif /* chips */
  47613 
  47614 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  47615     defined(BCM_56670_B0)
  47616     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM53400_A0r */
  47617         soc_block_list[16],
  47618         soc_genreg,
  47619         1,
  47620         0,
  47621         0x2020e00,
  47622         0,
  47623         0,
  47624         1,
  47625         soc_XLPORT_EEE_CLOCK_GATE_BCM53400_A0r_fields,
  47626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47628         -1,
  47629         -1,
  47630     },
  47631 #endif /* chips */
  47632 
  47633 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  47634     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM53570_A0r */
  47635         soc_block_list[16],
  47636         soc_genreg,
  47637         1,
  47638         0,
  47639         0x2020e00,
  47640         0,
  47641         0,
  47642         1,
  47643         soc_XLPORT_EEE_CLOCK_GATE_BCM53400_A0r_fields,
  47644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47646         -1,
  47647         -1,
  47648     },
  47649 #endif /* chips */
  47650 
  47651 #if defined(BCM_56150_A0)
  47652     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM56150_A0r */
  47653         soc_block_list[16],
  47654         soc_genreg,
  47655         1,
  47656         0,
  47657         0x2020e00,
  47658         0,
  47659         0,
  47660         1,
  47661         soc_CPORT_EEE_CLOCK_GATEr_fields,
  47662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47663         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47664         -1,
  47665         -1,
  47666     },
  47667 #endif /* chips */
  47668 
  47669 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  47670     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM56160_A0r */
  47671         soc_block_list[16],
  47672         soc_genreg,
  47673         1,
  47674         0,
  47675         0x2020e00,
  47676         0,
  47677         0,
  47678         1,
  47679         soc_XLPORT_EEE_CLOCK_GATE_BCM53400_A0r_fields,
  47680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47681         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47682         -1,
  47683         -1,
  47684     },
  47685 #endif /* chips */
  47686 
  47687 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47688     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM56260_A0r */
  47689         soc_block_list[16],
  47690         soc_genreg,
  47691         1,
  47692         0,
  47693         0x2020e00,
  47694         0,
  47695         0,
  47696         1,
  47697         soc_XLPORT_EEE_CLOCK_GATE_BCM53400_A0r_fields,
  47698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47700         -1,
  47701         -1,
  47702     },
  47703 #endif /* chips */
  47704 
  47705 #if defined(BCM_56370_A0)
  47706     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM56370_A0r */
  47707         soc_block_list[16],
  47708         soc_genreg,
  47709         1,
  47710         0,
  47711         0x2020e00,
  47712         0,
  47713         0,
  47714         1,
  47715         soc_XLPORT_EEE_CLOCK_GATE_BCM53400_A0r_fields,
  47716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47718         -1,
  47719         -1,
  47720         3,
  47721     },
  47722 #endif /* chips */
  47723 
  47724 #if defined(BCM_56560_A0)
  47725     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM56560_A0r */
  47726         soc_block_list[217],
  47727         soc_genreg,
  47728         1,
  47729         0,
  47730         0x2020e00,
  47731         0,
  47732         0,
  47733         1,
  47734         soc_XLPORT_EEE_CLOCK_GATE_BCM53400_A0r_fields,
  47735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47736         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47737         -1,
  47738         -1,
  47739     },
  47740 #endif /* chips */
  47741 
  47742 #if defined(BCM_56560_B0)
  47743     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM56560_B0r */
  47744         soc_block_list[16],
  47745         soc_genreg,
  47746         1,
  47747         0,
  47748         0x2020e00,
  47749         0,
  47750         0,
  47751         1,
  47752         soc_XLPORT_EEE_CLOCK_GATE_BCM53400_A0r_fields,
  47753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47754         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47755         -1,
  47756         -1,
  47757     },
  47758 #endif /* chips */
  47759 
  47760 #if defined(BCM_56850_A0)
  47761     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM56850_A0r */
  47762         soc_block_list[16],
  47763         soc_genreg,
  47764         1,
  47765         0,
  47766         0x2020a00,
  47767         0,
  47768         0,
  47769         1,
  47770         soc_CPORT_EEE_CLOCK_GATEr_fields,
  47771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47772         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47773         -1,
  47774         -1,
  47775     },
  47776 #endif /* chips */
  47777 
  47778 #if defined(BCM_56860_A0)
  47779     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM56860_A0r */
  47780         soc_block_list[16],
  47781         soc_genreg,
  47782         1,
  47783         0,
  47784         0x2020b00,
  47785         0,
  47786         0,
  47787         1,
  47788         soc_CPORT_EEE_CLOCK_GATEr_fields,
  47789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47790         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47791         -1,
  47792         -1,
  47793     },
  47794 #endif /* chips */
  47795 
  47796 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  47797     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  47798     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  47799     defined(BCM_56980_B0)
  47800     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM56960_A0r */
  47801         soc_block_list[16],
  47802         soc_genreg,
  47803         1,
  47804         0,
  47805         0x2020e00,
  47806         0,
  47807         0,
  47808         1,
  47809         soc_XLPORT_EEE_CLOCK_GATE_BCM53400_A0r_fields,
  47810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47811         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47812         -1,
  47813         -1,
  47814         3,
  47815     },
  47816 #endif /* chips */
  47817 
  47818 #if defined(BCM_88270_A0)
  47819     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM88270_A0r */
  47820         soc_block_list[56],
  47821         soc_genreg,
  47822         1,
  47823         0,
  47824         0x2020e00,
  47825         0,
  47826         0,
  47827         1,
  47828         soc_XLPORT_EEE_CLOCK_GATE_BCM88270_A0r_fields,
  47829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47830         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47831         -1,
  47832         -1,
  47833     },
  47834 #endif /* chips */
  47835 
  47836 #if defined(BCM_88375_A0)
  47837     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM88375_A0r */
  47838         soc_block_list[56],
  47839         soc_genreg,
  47840         1,
  47841         0,
  47842         0x2020e00,
  47843         0,
  47844         0,
  47845         1,
  47846         soc_XLPORT_EEE_CLOCK_GATE_BCM88375_A0r_fields,
  47847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47848         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47849         -1,
  47850         -1,
  47851     },
  47852 #endif /* chips */
  47853 
  47854 #if defined(BCM_88375_B0)
  47855     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM88375_B0r */
  47856         soc_block_list[56],
  47857         soc_genreg,
  47858         1,
  47859         0,
  47860         0x2020e00,
  47861         0,
  47862         0,
  47863         1,
  47864         soc_XLPORT_EEE_CLOCK_GATE_BCM88375_B0r_fields,
  47865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47866         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47867         -1,
  47868         -1,
  47869     },
  47870 #endif /* chips */
  47871 
  47872 #if defined(BCM_88470_A0)
  47873     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM88470_A0r */
  47874         soc_block_list[56],
  47875         soc_genreg,
  47876         1,
  47877         0,
  47878         0x2020e00,
  47879         0,
  47880         0,
  47881         1,
  47882         soc_XLPORT_EEE_CLOCK_GATE_BCM88470_A0r_fields,
  47883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47884         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47885         -1,
  47886         -1,
  47887     },
  47888 #endif /* chips */
  47889 
  47890 #if defined(BCM_88470_B0)
  47891     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM88470_B0r */
  47892         soc_block_list[56],
  47893         soc_genreg,
  47894         1,
  47895         0,
  47896         0x2020e00,
  47897         0,
  47898         0,
  47899         1,
  47900         soc_XLPORT_EEE_CLOCK_GATE_BCM88470_B0r_fields,
  47901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47902         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47903         -1,
  47904         -1,
  47905     },
  47906 #endif /* chips */
  47907 
  47908 #if defined(BCM_88675_A0)
  47909     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM88675_A0r */
  47910         soc_block_list[56],
  47911         soc_genreg,
  47912         1,
  47913         0,
  47914         0x2020e00,
  47915         0,
  47916         0,
  47917         1,
  47918         soc_XLPORT_EEE_CLOCK_GATEr_fields,
  47919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47920         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47921         -1,
  47922         -1,
  47923     },
  47924 #endif /* chips */
  47925 
  47926 #if defined(BCM_88675_B0)
  47927     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM88675_B0r */
  47928         soc_block_list[56],
  47929         soc_genreg,
  47930         1,
  47931         0,
  47932         0x2020e00,
  47933         0,
  47934         0,
  47935         1,
  47936         soc_XLPORT_EEE_CLOCK_GATE_BCM88675_B0r_fields,
  47937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47938         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47939         -1,
  47940         -1,
  47941     },
  47942 #endif /* chips */
  47943 
  47944 #if defined(BCM_88680_A0)
  47945     { /* SOC_REG_INT_XLPORT_EEE_CLOCK_GATE_BCM88680_A0r */
  47946         soc_block_list[56],
  47947         soc_genreg,
  47948         1,
  47949         0,
  47950         0x2020e00,
  47951         0,
  47952         0,
  47953         1,
  47954         soc_XLPORT_EEE_CLOCK_GATE_BCM88680_A0r_fields,
  47955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47956         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  47957         -1,
  47958         -1,
  47959     },
  47960 #endif /* chips */
  47961 
  47962 #if defined(BCM_2801PM_A0)
  47963     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr */
  47964         soc_block_list[56],
  47965         soc_genreg,
  47966         1,
  47967         0,
  47968         0x2020f00,
  47969         0,
  47970         0,
  47971         1,
  47972         soc_CLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
  47973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47974         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  47975         -1,
  47976         -1,
  47977     },
  47978 #endif /* chips */
  47979 
  47980 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  47981     defined(BCM_56670_B0)
  47982     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM53400_A0r */
  47983         soc_block_list[16],
  47984         soc_genreg,
  47985         1,
  47986         0,
  47987         0x2020f00,
  47988         0,
  47989         0,
  47990         1,
  47991         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM53400_A0r_fields,
  47992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47994         -1,
  47995         -1,
  47996     },
  47997 #endif /* chips */
  47998 
  47999 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  48000     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM53570_A0r */
  48001         soc_block_list[16],
  48002         soc_genreg,
  48003         1,
  48004         0,
  48005         0x2020f00,
  48006         0,
  48007         0,
  48008         1,
  48009         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM53400_A0r_fields,
  48010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48012         -1,
  48013         -1,
  48014     },
  48015 #endif /* chips */
  48016 
  48017 #if defined(BCM_56150_A0)
  48018     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM56150_A0r */
  48019         soc_block_list[16],
  48020         soc_genreg,
  48021         1,
  48022         0,
  48023         0x2020f00,
  48024         0,
  48025         0,
  48026         1,
  48027         soc_PORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
  48028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48029         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48030         -1,
  48031         -1,
  48032     },
  48033 #endif /* chips */
  48034 
  48035 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  48036     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM56160_A0r */
  48037         soc_block_list[16],
  48038         soc_genreg,
  48039         1,
  48040         0,
  48041         0x2020f00,
  48042         0,
  48043         0,
  48044         1,
  48045         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM53400_A0r_fields,
  48046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48048         -1,
  48049         -1,
  48050     },
  48051 #endif /* chips */
  48052 
  48053 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48054     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM56260_A0r */
  48055         soc_block_list[16],
  48056         soc_genreg,
  48057         1,
  48058         0,
  48059         0x2020f00,
  48060         0,
  48061         0,
  48062         1,
  48063         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM53400_A0r_fields,
  48064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48065         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48066         -1,
  48067         -1,
  48068     },
  48069 #endif /* chips */
  48070 
  48071 #if defined(BCM_56370_A0)
  48072     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM56370_A0r */
  48073         soc_block_list[16],
  48074         soc_genreg,
  48075         1,
  48076         0,
  48077         0x2020f00,
  48078         0,
  48079         0,
  48080         1,
  48081         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM53400_A0r_fields,
  48082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48083         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48084         -1,
  48085         -1,
  48086         3,
  48087     },
  48088 #endif /* chips */
  48089 
  48090 #if defined(BCM_56560_A0)
  48091     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM56560_A0r */
  48092         soc_block_list[217],
  48093         soc_genreg,
  48094         1,
  48095         0,
  48096         0x2020f00,
  48097         0,
  48098         0,
  48099         1,
  48100         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM53400_A0r_fields,
  48101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48102         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48103         -1,
  48104         -1,
  48105     },
  48106 #endif /* chips */
  48107 
  48108 #if defined(BCM_56560_B0)
  48109     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM56560_B0r */
  48110         soc_block_list[16],
  48111         soc_genreg,
  48112         1,
  48113         0,
  48114         0x2020f00,
  48115         0,
  48116         0,
  48117         1,
  48118         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM53400_A0r_fields,
  48119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48120         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48121         -1,
  48122         -1,
  48123     },
  48124 #endif /* chips */
  48125 
  48126 #if defined(BCM_56850_A0)
  48127     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM56850_A0r */
  48128         soc_block_list[16],
  48129         soc_genreg,
  48130         1,
  48131         0,
  48132         0x2020b00,
  48133         0,
  48134         0,
  48135         1,
  48136         soc_PORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
  48137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48138         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48139         -1,
  48140         -1,
  48141     },
  48142 #endif /* chips */
  48143 
  48144 #if defined(BCM_56860_A0)
  48145     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM56860_A0r */
  48146         soc_block_list[16],
  48147         soc_genreg,
  48148         1,
  48149         0,
  48150         0x2020c00,
  48151         0,
  48152         0,
  48153         1,
  48154         soc_PORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
  48155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48157         -1,
  48158         -1,
  48159     },
  48160 #endif /* chips */
  48161 
  48162 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  48163     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  48164     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  48165     defined(BCM_56980_B0)
  48166     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM56960_A0r */
  48167         soc_block_list[16],
  48168         soc_genreg,
  48169         1,
  48170         0,
  48171         0x2020f00,
  48172         0,
  48173         0,
  48174         1,
  48175         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM53400_A0r_fields,
  48176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48177         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  48178         -1,
  48179         -1,
  48180         3,
  48181     },
  48182 #endif /* chips */
  48183 
  48184 #if defined(BCM_88270_A0)
  48185     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88270_A0r */
  48186         soc_block_list[56],
  48187         soc_genreg,
  48188         1,
  48189         0,
  48190         0x2020f00,
  48191         0,
  48192         0,
  48193         1,
  48194         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88270_A0r_fields,
  48195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48196         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48197         -1,
  48198         -1,
  48199     },
  48200 #endif /* chips */
  48201 
  48202 #if defined(BCM_88375_A0)
  48203     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88375_A0r */
  48204         soc_block_list[56],
  48205         soc_genreg,
  48206         1,
  48207         0,
  48208         0x2020f00,
  48209         0,
  48210         0,
  48211         1,
  48212         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88375_A0r_fields,
  48213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48214         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48215         -1,
  48216         -1,
  48217     },
  48218 #endif /* chips */
  48219 
  48220 #if defined(BCM_88375_B0)
  48221     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88375_B0r */
  48222         soc_block_list[56],
  48223         soc_genreg,
  48224         1,
  48225         0,
  48226         0x2020f00,
  48227         0,
  48228         0,
  48229         1,
  48230         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88375_B0r_fields,
  48231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48232         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48233         -1,
  48234         -1,
  48235     },
  48236 #endif /* chips */
  48237 
  48238 #if defined(BCM_88470_A0)
  48239     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88470_A0r */
  48240         soc_block_list[56],
  48241         soc_genreg,
  48242         1,
  48243         0,
  48244         0x2020f00,
  48245         0,
  48246         0,
  48247         1,
  48248         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88470_A0r_fields,
  48249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48250         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48251         -1,
  48252         -1,
  48253     },
  48254 #endif /* chips */
  48255 
  48256 #if defined(BCM_88470_B0)
  48257     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88470_B0r */
  48258         soc_block_list[56],
  48259         soc_genreg,
  48260         1,
  48261         0,
  48262         0x2020f00,
  48263         0,
  48264         0,
  48265         1,
  48266         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88470_B0r_fields,
  48267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48268         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48269         -1,
  48270         -1,
  48271     },
  48272 #endif /* chips */
  48273 
  48274 #if defined(BCM_88675_A0)
  48275     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88675_A0r */
  48276         soc_block_list[56],
  48277         soc_genreg,
  48278         1,
  48279         0,
  48280         0x2020f00,
  48281         0,
  48282         0,
  48283         1,
  48284         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
  48285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48286         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48287         -1,
  48288         -1,
  48289     },
  48290 #endif /* chips */
  48291 
  48292 #if defined(BCM_88675_B0)
  48293     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88675_B0r */
  48294         soc_block_list[56],
  48295         soc_genreg,
  48296         1,
  48297         0,
  48298         0x2020f00,
  48299         0,
  48300         0,
  48301         1,
  48302         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88675_B0r_fields,
  48303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48304         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48305         -1,
  48306         -1,
  48307     },
  48308 #endif /* chips */
  48309 
  48310 #if defined(BCM_88680_A0)
  48311     { /* SOC_REG_INT_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88680_A0r */
  48312         soc_block_list[56],
  48313         soc_genreg,
  48314         1,
  48315         0,
  48316         0x2020f00,
  48317         0,
  48318         0,
  48319         1,
  48320         soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88680_A0r_fields,
  48321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48322         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48323         -1,
  48324         -1,
  48325     },
  48326 #endif /* chips */
  48327 
  48328 #if defined(BCM_2801PM_A0)
  48329     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODEr */
  48330         soc_block_list[56],
  48331         soc_portreg,
  48332         1,
  48333         0,
  48334         0x20300,
  48335         0,
  48336         0,
  48337         1,
  48338         soc_CLPORT_EEE_COUNTER_MODEr_fields,
  48339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48340         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48341         -1,
  48342         -1,
  48343     },
  48344 #endif /* chips */
  48345 
  48346 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  48347     defined(BCM_56670_B0)
  48348     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM53400_A0r */
  48349         soc_block_list[16],
  48350         soc_portreg,
  48351         1,
  48352         0,
  48353         0x20300,
  48354         0,
  48355         0,
  48356         1,
  48357         soc_XLPORT_EEE_COUNTER_MODE_BCM53400_A0r_fields,
  48358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48359         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48360         -1,
  48361         -1,
  48362     },
  48363 #endif /* chips */
  48364 
  48365 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  48366     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM53570_A0r */
  48367         soc_block_list[16],
  48368         soc_portreg,
  48369         1,
  48370         0,
  48371         0x20300,
  48372         0,
  48373         0,
  48374         1,
  48375         soc_XLPORT_EEE_COUNTER_MODE_BCM53400_A0r_fields,
  48376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48377         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48378         -1,
  48379         -1,
  48380     },
  48381 #endif /* chips */
  48382 
  48383 #if defined(BCM_56150_A0)
  48384     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM56150_A0r */
  48385         soc_block_list[16],
  48386         soc_portreg,
  48387         1,
  48388         0,
  48389         0x20400,
  48390         0,
  48391         0,
  48392         1,
  48393         soc_PORT_EEE_COUNTER_MODE_BCM56640_A0r_fields,
  48394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48395         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48396         -1,
  48397         -1,
  48398     },
  48399 #endif /* chips */
  48400 
  48401 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  48402     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM56160_A0r */
  48403         soc_block_list[16],
  48404         soc_portreg,
  48405         1,
  48406         0,
  48407         0x20300,
  48408         0,
  48409         0,
  48410         1,
  48411         soc_XLPORT_EEE_COUNTER_MODE_BCM53400_A0r_fields,
  48412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48413         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48414         -1,
  48415         -1,
  48416     },
  48417 #endif /* chips */
  48418 
  48419 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48420     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM56260_A0r */
  48421         soc_block_list[16],
  48422         soc_portreg,
  48423         1,
  48424         0,
  48425         0x20300,
  48426         0,
  48427         0,
  48428         1,
  48429         soc_XLPORT_EEE_COUNTER_MODE_BCM53400_A0r_fields,
  48430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48431         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48432         -1,
  48433         -1,
  48434     },
  48435 #endif /* chips */
  48436 
  48437 #if defined(BCM_56370_A0)
  48438     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM56370_A0r */
  48439         soc_block_list[16],
  48440         soc_portreg,
  48441         1,
  48442         0,
  48443         0x20300,
  48444         0,
  48445         0,
  48446         1,
  48447         soc_XLPORT_EEE_COUNTER_MODE_BCM53400_A0r_fields,
  48448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48449         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48450         -1,
  48451         -1,
  48452         3,
  48453     },
  48454 #endif /* chips */
  48455 
  48456 #if defined(BCM_56560_A0)
  48457     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM56560_A0r */
  48458         soc_block_list[217],
  48459         soc_portreg,
  48460         1,
  48461         0,
  48462         0x20300,
  48463         0,
  48464         0,
  48465         1,
  48466         soc_XLPORT_EEE_COUNTER_MODE_BCM53400_A0r_fields,
  48467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48468         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48469         -1,
  48470         -1,
  48471     },
  48472 #endif /* chips */
  48473 
  48474 #if defined(BCM_56560_B0)
  48475     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM56560_B0r */
  48476         soc_block_list[16],
  48477         soc_portreg,
  48478         1,
  48479         0,
  48480         0x20300,
  48481         0,
  48482         0,
  48483         1,
  48484         soc_XLPORT_EEE_COUNTER_MODE_BCM53400_A0r_fields,
  48485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48486         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48487         -1,
  48488         -1,
  48489     },
  48490 #endif /* chips */
  48491 
  48492 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  48493     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  48494     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  48495     defined(BCM_56980_B0)
  48496     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM56960_A0r */
  48497         soc_block_list[16],
  48498         soc_portreg,
  48499         1,
  48500         0,
  48501         0x20300,
  48502         0,
  48503         0,
  48504         1,
  48505         soc_XLPORT_EEE_COUNTER_MODE_BCM53400_A0r_fields,
  48506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48507         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48508         -1,
  48509         -1,
  48510         3,
  48511     },
  48512 #endif /* chips */
  48513 
  48514 #if defined(BCM_88270_A0)
  48515     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM88270_A0r */
  48516         soc_block_list[56],
  48517         soc_portreg,
  48518         1,
  48519         0,
  48520         0x20300,
  48521         0,
  48522         0,
  48523         1,
  48524         soc_XLPORT_EEE_COUNTER_MODE_BCM88270_A0r_fields,
  48525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48526         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48527         -1,
  48528         -1,
  48529     },
  48530 #endif /* chips */
  48531 
  48532 #if defined(BCM_88375_A0)
  48533     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM88375_A0r */
  48534         soc_block_list[56],
  48535         soc_portreg,
  48536         1,
  48537         0,
  48538         0x20300,
  48539         0,
  48540         0,
  48541         1,
  48542         soc_XLPORT_EEE_COUNTER_MODE_BCM88375_A0r_fields,
  48543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48544         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48545         -1,
  48546         -1,
  48547     },
  48548 #endif /* chips */
  48549 
  48550 #if defined(BCM_88375_B0)
  48551     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM88375_B0r */
  48552         soc_block_list[56],
  48553         soc_portreg,
  48554         1,
  48555         0,
  48556         0x20300,
  48557         0,
  48558         0,
  48559         1,
  48560         soc_XLPORT_EEE_COUNTER_MODE_BCM88375_B0r_fields,
  48561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48562         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48563         -1,
  48564         -1,
  48565     },
  48566 #endif /* chips */
  48567 
  48568 #if defined(BCM_88470_A0)
  48569     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM88470_A0r */
  48570         soc_block_list[56],
  48571         soc_portreg,
  48572         1,
  48573         0,
  48574         0x20300,
  48575         0,
  48576         0,
  48577         1,
  48578         soc_XLPORT_EEE_COUNTER_MODE_BCM88470_A0r_fields,
  48579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48580         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48581         -1,
  48582         -1,
  48583     },
  48584 #endif /* chips */
  48585 
  48586 #if defined(BCM_88470_B0)
  48587     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM88470_B0r */
  48588         soc_block_list[56],
  48589         soc_portreg,
  48590         1,
  48591         0,
  48592         0x20300,
  48593         0,
  48594         0,
  48595         1,
  48596         soc_XLPORT_EEE_COUNTER_MODE_BCM88470_B0r_fields,
  48597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48598         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48599         -1,
  48600         -1,
  48601     },
  48602 #endif /* chips */
  48603 
  48604 #if defined(BCM_88675_A0)
  48605     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM88675_A0r */
  48606         soc_block_list[56],
  48607         soc_portreg,
  48608         1,
  48609         0,
  48610         0x20300,
  48611         0,
  48612         0,
  48613         1,
  48614         soc_XLPORT_EEE_COUNTER_MODEr_fields,
  48615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48616         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48617         -1,
  48618         -1,
  48619     },
  48620 #endif /* chips */
  48621 
  48622 #if defined(BCM_88675_B0)
  48623     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM88675_B0r */
  48624         soc_block_list[56],
  48625         soc_portreg,
  48626         1,
  48627         0,
  48628         0x20300,
  48629         0,
  48630         0,
  48631         1,
  48632         soc_XLPORT_EEE_COUNTER_MODE_BCM88675_B0r_fields,
  48633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48634         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48635         -1,
  48636         -1,
  48637     },
  48638 #endif /* chips */
  48639 
  48640 #if defined(BCM_88680_A0)
  48641     { /* SOC_REG_INT_XLPORT_EEE_COUNTER_MODE_BCM88680_A0r */
  48642         soc_block_list[56],
  48643         soc_portreg,
  48644         1,
  48645         0,
  48646         0x20300,
  48647         0,
  48648         0,
  48649         1,
  48650         soc_XLPORT_EEE_COUNTER_MODE_BCM88680_A0r_fields,
  48651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48652         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48653         -1,
  48654         -1,
  48655     },
  48656 #endif /* chips */
  48657 
  48658 #if defined(BCM_56840_A0)
  48659     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSEr */
  48660         soc_block_list[16],
  48661         soc_genreg,
  48662         1,
  48663         0,
  48664         0x8022e,
  48665         0,
  48666         0,
  48667         1,
  48668         soc_XLPORT_EEE_DURATION_TIMER_PULSEr_fields,
  48669         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48670         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48671         -1,
  48672         -1,
  48673     },
  48674 #endif /* chips */
  48675 
  48676 #if defined(BCM_2801PM_A0)
  48677     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM2801PM_A0r */
  48678         soc_block_list[56],
  48679         soc_genreg,
  48680         1,
  48681         0,
  48682         0x2021200,
  48683         0,
  48684         0,
  48685         1,
  48686         soc_CLPORT_EEE_DURATION_TIMER_PULSEr_fields,
  48687         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48688         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48689         -1,
  48690         -1,
  48691     },
  48692 #endif /* chips */
  48693 
  48694 #if defined(BCM_53400_A0)
  48695     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r */
  48696         soc_block_list[16],
  48697         soc_genreg,
  48698         1,
  48699         0,
  48700         0x2021200,
  48701         0,
  48702         0,
  48703         1,
  48704         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r_fields,
  48705         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48706         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48707         -1,
  48708         -1,
  48709     },
  48710 #endif /* chips */
  48711 
  48712 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  48713     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53570_A0r */
  48714         soc_block_list[16],
  48715         soc_genreg,
  48716         1,
  48717         0,
  48718         0x2021200,
  48719         0,
  48720         0,
  48721         1,
  48722         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r_fields,
  48723         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48724         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48725         -1,
  48726         -1,
  48727     },
  48728 #endif /* chips */
  48729 
  48730 #if defined(BCM_56150_A0)
  48731     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56150_A0r */
  48732         soc_block_list[16],
  48733         soc_genreg,
  48734         1,
  48735         0,
  48736         0x2021200,
  48737         0,
  48738         0,
  48739         1,
  48740         soc_PORT_EEE_DURATION_TIMER_PULSE_BCM56640_A0r_fields,
  48741         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48742         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48743         -1,
  48744         -1,
  48745     },
  48746 #endif /* chips */
  48747 
  48748 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  48749     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56160_A0r */
  48750         soc_block_list[16],
  48751         soc_genreg,
  48752         1,
  48753         0,
  48754         0x2021200,
  48755         0,
  48756         0,
  48757         1,
  48758         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r_fields,
  48759         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48760         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48761         -1,
  48762         -1,
  48763     },
  48764 #endif /* chips */
  48765 
  48766 #if defined(BCM_56260_A0)
  48767     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56260_A0r */
  48768         soc_block_list[16],
  48769         soc_genreg,
  48770         1,
  48771         0,
  48772         0x2021200,
  48773         0,
  48774         0,
  48775         1,
  48776         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r_fields,
  48777         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48778         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48779         -1,
  48780         -1,
  48781     },
  48782 #endif /* chips */
  48783 
  48784 #if defined(BCM_56260_B0)
  48785     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56260_B0r */
  48786         soc_block_list[16],
  48787         soc_genreg,
  48788         1,
  48789         0,
  48790         0x2021200,
  48791         0,
  48792         0,
  48793         1,
  48794         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r_fields,
  48795         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48796         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48797         -1,
  48798         -1,
  48799     },
  48800 #endif /* chips */
  48801 
  48802 #if defined(BCM_56370_A0)
  48803     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56370_A0r */
  48804         soc_block_list[16],
  48805         soc_genreg,
  48806         1,
  48807         0,
  48808         0x2021200,
  48809         0,
  48810         0,
  48811         1,
  48812         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r_fields,
  48813         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48814         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48815         -1,
  48816         -1,
  48817         3,
  48818     },
  48819 #endif /* chips */
  48820 
  48821 #if defined(BCM_56560_A0)
  48822     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56560_A0r */
  48823         soc_block_list[217],
  48824         soc_genreg,
  48825         1,
  48826         0,
  48827         0x2021200,
  48828         0,
  48829         0,
  48830         1,
  48831         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r_fields,
  48832         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48833         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48834         -1,
  48835         -1,
  48836     },
  48837 #endif /* chips */
  48838 
  48839 #if defined(BCM_56560_B0)
  48840     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56560_B0r */
  48841         soc_block_list[16],
  48842         soc_genreg,
  48843         1,
  48844         0,
  48845         0x2021200,
  48846         0,
  48847         0,
  48848         1,
  48849         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r_fields,
  48850         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48851         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48852         -1,
  48853         -1,
  48854     },
  48855 #endif /* chips */
  48856 
  48857 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  48858     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56670_A0r */
  48859         soc_block_list[16],
  48860         soc_genreg,
  48861         1,
  48862         0,
  48863         0x2021200,
  48864         0,
  48865         0,
  48866         1,
  48867         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r_fields,
  48868         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48869         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48870         -1,
  48871         -1,
  48872     },
  48873 #endif /* chips */
  48874 
  48875 #if defined(BCM_56840_B0)
  48876     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56840_B0r */
  48877         soc_block_list[16],
  48878         soc_genreg,
  48879         1,
  48880         0,
  48881         0x8022e,
  48882         0,
  48883         0,
  48884         1,
  48885         soc_XLPORT_EEE_DURATION_TIMER_PULSEr_fields,
  48886         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48887         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48888         -1,
  48889         -1,
  48890     },
  48891 #endif /* chips */
  48892 
  48893 #if defined(BCM_56850_A0)
  48894     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56850_A0r */
  48895         soc_block_list[16],
  48896         soc_genreg,
  48897         1,
  48898         0,
  48899         0x2020d00,
  48900         0,
  48901         0,
  48902         1,
  48903         soc_PORT_EEE_DURATION_TIMER_PULSE_BCM56640_A0r_fields,
  48904         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48905         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48906         -1,
  48907         -1,
  48908     },
  48909 #endif /* chips */
  48910 
  48911 #if defined(BCM_56860_A0)
  48912     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56860_A0r */
  48913         soc_block_list[16],
  48914         soc_genreg,
  48915         1,
  48916         0,
  48917         0x2020e00,
  48918         0,
  48919         0,
  48920         1,
  48921         soc_PORT_EEE_DURATION_TIMER_PULSE_BCM56640_A0r_fields,
  48922         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48923         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48924         -1,
  48925         -1,
  48926     },
  48927 #endif /* chips */
  48928 
  48929 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  48930     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  48931     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  48932     defined(BCM_56980_B0)
  48933     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM56960_A0r */
  48934         soc_block_list[16],
  48935         soc_genreg,
  48936         1,
  48937         0,
  48938         0x2021200,
  48939         0,
  48940         0,
  48941         1,
  48942         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r_fields,
  48943         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48944         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48945         -1,
  48946         -1,
  48947         3,
  48948     },
  48949 #endif /* chips */
  48950 
  48951 #if defined(BCM_88270_A0)
  48952     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88270_A0r */
  48953         soc_block_list[56],
  48954         soc_genreg,
  48955         1,
  48956         0,
  48957         0x2021200,
  48958         0,
  48959         0,
  48960         1,
  48961         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88270_A0r_fields,
  48962         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48963         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48964         -1,
  48965         -1,
  48966     },
  48967 #endif /* chips */
  48968 
  48969 #if defined(BCM_88375_A0)
  48970     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88375_A0r */
  48971         soc_block_list[56],
  48972         soc_genreg,
  48973         1,
  48974         0,
  48975         0x2021200,
  48976         0,
  48977         0,
  48978         1,
  48979         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88375_A0r_fields,
  48980         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48981         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  48982         -1,
  48983         -1,
  48984     },
  48985 #endif /* chips */
  48986 
  48987 #if defined(BCM_88375_B0)
  48988     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88375_B0r */
  48989         soc_block_list[56],
  48990         soc_genreg,
  48991         1,
  48992         0,
  48993         0x2021200,
  48994         0,
  48995         0,
  48996         1,
  48997         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88375_B0r_fields,
  48998         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  48999         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49000         -1,
  49001         -1,
  49002     },
  49003 #endif /* chips */
  49004 
  49005 #if defined(BCM_88470_A0)
  49006     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88470_A0r */
  49007         soc_block_list[56],
  49008         soc_genreg,
  49009         1,
  49010         0,
  49011         0x2021200,
  49012         0,
  49013         0,
  49014         1,
  49015         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88470_A0r_fields,
  49016         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  49017         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49018         -1,
  49019         -1,
  49020     },
  49021 #endif /* chips */
  49022 
  49023 #if defined(BCM_88470_B0)
  49024     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88470_B0r */
  49025         soc_block_list[56],
  49026         soc_genreg,
  49027         1,
  49028         0,
  49029         0x2021200,
  49030         0,
  49031         0,
  49032         1,
  49033         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88470_B0r_fields,
  49034         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  49035         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49036         -1,
  49037         -1,
  49038     },
  49039 #endif /* chips */
  49040 
  49041 #if defined(BCM_88675_A0)
  49042     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88675_A0r */
  49043         soc_block_list[56],
  49044         soc_genreg,
  49045         1,
  49046         0,
  49047         0x2021200,
  49048         0,
  49049         0,
  49050         1,
  49051         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88675_A0r_fields,
  49052         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  49053         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49054         -1,
  49055         -1,
  49056     },
  49057 #endif /* chips */
  49058 
  49059 #if defined(BCM_88675_B0)
  49060     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88675_B0r */
  49061         soc_block_list[56],
  49062         soc_genreg,
  49063         1,
  49064         0,
  49065         0x2021200,
  49066         0,
  49067         0,
  49068         1,
  49069         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88675_B0r_fields,
  49070         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  49071         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49072         -1,
  49073         -1,
  49074     },
  49075 #endif /* chips */
  49076 
  49077 #if defined(BCM_88680_A0)
  49078     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88680_A0r */
  49079         soc_block_list[56],
  49080         soc_genreg,
  49081         1,
  49082         0,
  49083         0x2021200,
  49084         0,
  49085         0,
  49086         1,
  49087         soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88680_A0r_fields,
  49088         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  49089         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49090         -1,
  49091         -1,
  49092     },
  49093 #endif /* chips */
  49094 
  49095 #if defined(BCM_88732_A0)
  49096     { /* SOC_REG_INT_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88732_A0r */
  49097         soc_block_list[16],
  49098         soc_genreg,
  49099         1,
  49100         0,
  49101         0x8022e,
  49102         0,
  49103         0,
  49104         1,
  49105         soc_XLPORT_EEE_DURATION_TIMER_PULSEr_fields,
  49106         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  49107         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49108         -1,
  49109         -1,
  49110     },
  49111 #endif /* chips */
  49112 
  49113 #if defined(BCM_2801PM_A0)
  49114     { /* SOC_REG_INT_XLPORT_ENABLE_REGr */
  49115         soc_block_list[56],
  49116         soc_genreg,
  49117         1,
  49118         0,
  49119         0x2020b00,
  49120         0,
  49121         0,
  49122         4,
  49123         soc_CLPORT_ENABLE_REGr_fields,
  49124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49125         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49126         -1,
  49127         -1,
  49128     },
  49129 #endif /* chips */
  49130 
  49131 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  49132     defined(BCM_56670_B0)
  49133     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM53400_A0r */
  49134         soc_block_list[16],
  49135         soc_genreg,
  49136         1,
  49137         0,
  49138         0x2020b00,
  49139         0,
  49140         0,
  49141         4,
  49142         soc_XLPORT_ENABLE_REG_BCM53400_A0r_fields,
  49143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49144         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49145         -1,
  49146         -1,
  49147     },
  49148 #endif /* chips */
  49149 
  49150 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  49151     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM53570_A0r */
  49152         soc_block_list[16],
  49153         soc_genreg,
  49154         1,
  49155         0,
  49156         0x2020b00,
  49157         0,
  49158         0,
  49159         4,
  49160         soc_XLPORT_ENABLE_REG_BCM53400_A0r_fields,
  49161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49162         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49163         -1,
  49164         -1,
  49165     },
  49166 #endif /* chips */
  49167 
  49168 #if defined(BCM_56150_A0)
  49169     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM56150_A0r */
  49170         soc_block_list[16],
  49171         soc_genreg,
  49172         1,
  49173         0,
  49174         0x2020b00,
  49175         0,
  49176         0,
  49177         4,
  49178         soc_XLPORT_ENABLE_REG_BCM56850_A0r_fields,
  49179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49180         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49181         -1,
  49182         -1,
  49183     },
  49184 #endif /* chips */
  49185 
  49186 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  49187     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM56160_A0r */
  49188         soc_block_list[16],
  49189         soc_genreg,
  49190         1,
  49191         0,
  49192         0x2020b00,
  49193         0,
  49194         0,
  49195         4,
  49196         soc_XLPORT_ENABLE_REG_BCM53400_A0r_fields,
  49197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49198         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49199         -1,
  49200         -1,
  49201     },
  49202 #endif /* chips */
  49203 
  49204 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49205     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM56260_A0r */
  49206         soc_block_list[16],
  49207         soc_genreg,
  49208         1,
  49209         0,
  49210         0x2020b00,
  49211         0,
  49212         0,
  49213         4,
  49214         soc_XLPORT_ENABLE_REG_BCM53400_A0r_fields,
  49215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49216         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49217         -1,
  49218         -1,
  49219     },
  49220 #endif /* chips */
  49221 
  49222 #if defined(BCM_56370_A0)
  49223     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM56370_A0r */
  49224         soc_block_list[16],
  49225         soc_genreg,
  49226         1,
  49227         0,
  49228         0x2020b00,
  49229         0,
  49230         0,
  49231         4,
  49232         soc_XLPORT_ENABLE_REG_BCM53400_A0r_fields,
  49233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49234         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49235         -1,
  49236         -1,
  49237         3,
  49238     },
  49239 #endif /* chips */
  49240 
  49241 #if defined(BCM_56560_A0)
  49242     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM56560_A0r */
  49243         soc_block_list[217],
  49244         soc_genreg,
  49245         1,
  49246         0,
  49247         0x2020b00,
  49248         0,
  49249         0,
  49250         4,
  49251         soc_XLPORT_ENABLE_REG_BCM53400_A0r_fields,
  49252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49253         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49254         -1,
  49255         -1,
  49256     },
  49257 #endif /* chips */
  49258 
  49259 #if defined(BCM_56560_B0)
  49260     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM56560_B0r */
  49261         soc_block_list[16],
  49262         soc_genreg,
  49263         1,
  49264         0,
  49265         0x2020b00,
  49266         0,
  49267         0,
  49268         4,
  49269         soc_XLPORT_ENABLE_REG_BCM53400_A0r_fields,
  49270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49271         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49272         -1,
  49273         -1,
  49274     },
  49275 #endif /* chips */
  49276 
  49277 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  49278     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM56850_A0r */
  49279         soc_block_list[16],
  49280         soc_genreg,
  49281         1,
  49282         0,
  49283         0x2020700,
  49284         0,
  49285         0,
  49286         4,
  49287         soc_XLPORT_ENABLE_REG_BCM56850_A0r_fields,
  49288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49289         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49290         -1,
  49291         -1,
  49292     },
  49293 #endif /* chips */
  49294 
  49295 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  49296     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  49297     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  49298     defined(BCM_56980_B0)
  49299     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM56960_A0r */
  49300         soc_block_list[16],
  49301         soc_genreg,
  49302         1,
  49303         0,
  49304         0x2020b00,
  49305         0,
  49306         0,
  49307         4,
  49308         soc_XLPORT_ENABLE_REG_BCM53400_A0r_fields,
  49309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49310         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49311         -1,
  49312         -1,
  49313         3,
  49314     },
  49315 #endif /* chips */
  49316 
  49317 #if defined(BCM_88270_A0)
  49318     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM88270_A0r */
  49319         soc_block_list[56],
  49320         soc_genreg,
  49321         1,
  49322         0,
  49323         0x2020b00,
  49324         0,
  49325         0,
  49326         4,
  49327         soc_XLPORT_ENABLE_REG_BCM88270_A0r_fields,
  49328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49329         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49330         -1,
  49331         -1,
  49332     },
  49333 #endif /* chips */
  49334 
  49335 #if defined(BCM_88375_A0)
  49336     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM88375_A0r */
  49337         soc_block_list[56],
  49338         soc_genreg,
  49339         1,
  49340         0,
  49341         0x2020b00,
  49342         0,
  49343         0,
  49344         4,
  49345         soc_XLPORT_ENABLE_REG_BCM88375_A0r_fields,
  49346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49347         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49348         -1,
  49349         -1,
  49350     },
  49351 #endif /* chips */
  49352 
  49353 #if defined(BCM_88375_B0)
  49354     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM88375_B0r */
  49355         soc_block_list[56],
  49356         soc_genreg,
  49357         1,
  49358         0,
  49359         0x2020b00,
  49360         0,
  49361         0,
  49362         4,
  49363         soc_XLPORT_ENABLE_REG_BCM88375_B0r_fields,
  49364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49365         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49366         -1,
  49367         -1,
  49368     },
  49369 #endif /* chips */
  49370 
  49371 #if defined(BCM_88470_A0)
  49372     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM88470_A0r */
  49373         soc_block_list[56],
  49374         soc_genreg,
  49375         1,
  49376         0,
  49377         0x2020b00,
  49378         0,
  49379         0,
  49380         4,
  49381         soc_XLPORT_ENABLE_REG_BCM88470_A0r_fields,
  49382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49383         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49384         -1,
  49385         -1,
  49386     },
  49387 #endif /* chips */
  49388 
  49389 #if defined(BCM_88470_B0)
  49390     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM88470_B0r */
  49391         soc_block_list[56],
  49392         soc_genreg,
  49393         1,
  49394         0,
  49395         0x2020b00,
  49396         0,
  49397         0,
  49398         4,
  49399         soc_XLPORT_ENABLE_REG_BCM88470_B0r_fields,
  49400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49401         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49402         -1,
  49403         -1,
  49404     },
  49405 #endif /* chips */
  49406 
  49407 #if defined(BCM_88675_A0)
  49408     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM88675_A0r */
  49409         soc_block_list[56],
  49410         soc_genreg,
  49411         1,
  49412         0,
  49413         0x2020b00,
  49414         0,
  49415         0,
  49416         4,
  49417         soc_XLPORT_ENABLE_REGr_fields,
  49418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49419         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49420         -1,
  49421         -1,
  49422     },
  49423 #endif /* chips */
  49424 
  49425 #if defined(BCM_88675_B0)
  49426     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM88675_B0r */
  49427         soc_block_list[56],
  49428         soc_genreg,
  49429         1,
  49430         0,
  49431         0x2020b00,
  49432         0,
  49433         0,
  49434         4,
  49435         soc_XLPORT_ENABLE_REG_BCM88675_B0r_fields,
  49436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49437         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49438         -1,
  49439         -1,
  49440     },
  49441 #endif /* chips */
  49442 
  49443 #if defined(BCM_88680_A0)
  49444     { /* SOC_REG_INT_XLPORT_ENABLE_REG_BCM88680_A0r */
  49445         soc_block_list[56],
  49446         soc_genreg,
  49447         1,
  49448         0,
  49449         0x2020b00,
  49450         0,
  49451         0,
  49452         4,
  49453         soc_XLPORT_ENABLE_REG_BCM88680_A0r_fields,
  49454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49455         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49456         -1,
  49457         -1,
  49458     },
  49459 #endif /* chips */
  49460 
  49461 #if defined(BCM_2801PM_A0)
  49462     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUSr */
  49463         soc_block_list[56],
  49464         soc_portreg,
  49465         1,
  49466         0,
  49467         0x20500,
  49468         0,
  49469         0,
  49470         2,
  49471         soc_CLPORT_FAULT_LINK_STATUSr_fields,
  49472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49473         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49474         -1,
  49475         -1,
  49476     },
  49477 #endif /* chips */
  49478 
  49479 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  49480     defined(BCM_56670_B0)
  49481     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM53400_A0r */
  49482         soc_block_list[16],
  49483         soc_portreg,
  49484         1,
  49485         0,
  49486         0x20500,
  49487         0,
  49488         0,
  49489         2,
  49490         soc_CLPORT_FAULT_LINK_STATUSr_fields,
  49491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49492         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49493         -1,
  49494         -1,
  49495     },
  49496 #endif /* chips */
  49497 
  49498 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  49499     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM53570_A0r */
  49500         soc_block_list[16],
  49501         soc_portreg,
  49502         1,
  49503         0,
  49504         0x20500,
  49505         0,
  49506         0,
  49507         2,
  49508         soc_CLPORT_FAULT_LINK_STATUSr_fields,
  49509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49510         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49511         -1,
  49512         -1,
  49513     },
  49514 #endif /* chips */
  49515 
  49516 #if defined(BCM_56150_A0)
  49517     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM56150_A0r */
  49518         soc_block_list[16],
  49519         soc_portreg,
  49520         1,
  49521         0,
  49522         0x20600,
  49523         0,
  49524         0,
  49525         2,
  49526         soc_PORT_FAULT_LINK_STATUS_BCM56640_A0r_fields,
  49527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49528         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49529         -1,
  49530         -1,
  49531     },
  49532 #endif /* chips */
  49533 
  49534 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  49535     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM56160_A0r */
  49536         soc_block_list[16],
  49537         soc_portreg,
  49538         1,
  49539         0,
  49540         0x20500,
  49541         0,
  49542         0,
  49543         2,
  49544         soc_CLPORT_FAULT_LINK_STATUSr_fields,
  49545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49546         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49547         -1,
  49548         -1,
  49549     },
  49550 #endif /* chips */
  49551 
  49552 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49553     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM56260_A0r */
  49554         soc_block_list[16],
  49555         soc_portreg,
  49556         1,
  49557         0,
  49558         0x20500,
  49559         0,
  49560         0,
  49561         2,
  49562         soc_CLPORT_FAULT_LINK_STATUSr_fields,
  49563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49564         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49565         -1,
  49566         -1,
  49567     },
  49568 #endif /* chips */
  49569 
  49570 #if defined(BCM_56370_A0)
  49571     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM56370_A0r */
  49572         soc_block_list[16],
  49573         soc_portreg,
  49574         1,
  49575         0,
  49576         0x20500,
  49577         0,
  49578         0,
  49579         2,
  49580         soc_CLPORT_FAULT_LINK_STATUSr_fields,
  49581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49582         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49583         -1,
  49584         -1,
  49585         3,
  49586     },
  49587 #endif /* chips */
  49588 
  49589 #if defined(BCM_56560_A0)
  49590     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM56560_A0r */
  49591         soc_block_list[217],
  49592         soc_portreg,
  49593         1,
  49594         0,
  49595         0x20500,
  49596         0,
  49597         0,
  49598         2,
  49599         soc_CLPORT_FAULT_LINK_STATUSr_fields,
  49600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49601         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49602         -1,
  49603         -1,
  49604     },
  49605 #endif /* chips */
  49606 
  49607 #if defined(BCM_56560_B0)
  49608     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM56560_B0r */
  49609         soc_block_list[16],
  49610         soc_portreg,
  49611         1,
  49612         0,
  49613         0x20500,
  49614         0,
  49615         0,
  49616         2,
  49617         soc_CLPORT_FAULT_LINK_STATUSr_fields,
  49618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49619         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49620         -1,
  49621         -1,
  49622     },
  49623 #endif /* chips */
  49624 
  49625 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  49626     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM56850_A0r */
  49627         soc_block_list[16],
  49628         soc_portreg,
  49629         1,
  49630         0,
  49631         0x20300,
  49632         0,
  49633         0,
  49634         2,
  49635         soc_PORT_FAULT_LINK_STATUS_BCM56640_A0r_fields,
  49636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49637         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49638         -1,
  49639         -1,
  49640     },
  49641 #endif /* chips */
  49642 
  49643 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  49644     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  49645     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  49646     defined(BCM_56980_B0)
  49647     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM56960_A0r */
  49648         soc_block_list[16],
  49649         soc_portreg,
  49650         1,
  49651         0,
  49652         0x20500,
  49653         0,
  49654         0,
  49655         2,
  49656         soc_CLPORT_FAULT_LINK_STATUSr_fields,
  49657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49658         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49659         -1,
  49660         -1,
  49661         3,
  49662     },
  49663 #endif /* chips */
  49664 
  49665 #if defined(BCM_88270_A0)
  49666     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM88270_A0r */
  49667         soc_block_list[56],
  49668         soc_portreg,
  49669         1,
  49670         0,
  49671         0x20500,
  49672         0,
  49673         0,
  49674         2,
  49675         soc_XLPORT_FAULT_LINK_STATUS_BCM88270_A0r_fields,
  49676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49677         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49678         -1,
  49679         -1,
  49680     },
  49681 #endif /* chips */
  49682 
  49683 #if defined(BCM_88375_A0)
  49684     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM88375_A0r */
  49685         soc_block_list[56],
  49686         soc_portreg,
  49687         1,
  49688         0,
  49689         0x20500,
  49690         0,
  49691         0,
  49692         2,
  49693         soc_XLPORT_FAULT_LINK_STATUS_BCM88375_A0r_fields,
  49694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49695         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49696         -1,
  49697         -1,
  49698     },
  49699 #endif /* chips */
  49700 
  49701 #if defined(BCM_88375_B0)
  49702     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM88375_B0r */
  49703         soc_block_list[56],
  49704         soc_portreg,
  49705         1,
  49706         0,
  49707         0x20500,
  49708         0,
  49709         0,
  49710         2,
  49711         soc_XLPORT_FAULT_LINK_STATUS_BCM88375_B0r_fields,
  49712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49713         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49714         -1,
  49715         -1,
  49716     },
  49717 #endif /* chips */
  49718 
  49719 #if defined(BCM_88470_A0)
  49720     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM88470_A0r */
  49721         soc_block_list[56],
  49722         soc_portreg,
  49723         1,
  49724         0,
  49725         0x20500,
  49726         0,
  49727         0,
  49728         2,
  49729         soc_XLPORT_FAULT_LINK_STATUS_BCM88470_A0r_fields,
  49730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49731         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49732         -1,
  49733         -1,
  49734     },
  49735 #endif /* chips */
  49736 
  49737 #if defined(BCM_88470_B0)
  49738     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM88470_B0r */
  49739         soc_block_list[56],
  49740         soc_portreg,
  49741         1,
  49742         0,
  49743         0x20500,
  49744         0,
  49745         0,
  49746         2,
  49747         soc_XLPORT_FAULT_LINK_STATUS_BCM88470_B0r_fields,
  49748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49749         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49750         -1,
  49751         -1,
  49752     },
  49753 #endif /* chips */
  49754 
  49755 #if defined(BCM_88675_A0)
  49756     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM88675_A0r */
  49757         soc_block_list[56],
  49758         soc_portreg,
  49759         1,
  49760         0,
  49761         0x20500,
  49762         0,
  49763         0,
  49764         2,
  49765         soc_XLPORT_FAULT_LINK_STATUSr_fields,
  49766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49767         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49768         -1,
  49769         -1,
  49770     },
  49771 #endif /* chips */
  49772 
  49773 #if defined(BCM_88675_B0)
  49774     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM88675_B0r */
  49775         soc_block_list[56],
  49776         soc_portreg,
  49777         1,
  49778         0,
  49779         0x20500,
  49780         0,
  49781         0,
  49782         2,
  49783         soc_XLPORT_FAULT_LINK_STATUS_BCM88675_B0r_fields,
  49784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49785         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49786         -1,
  49787         -1,
  49788     },
  49789 #endif /* chips */
  49790 
  49791 #if defined(BCM_88680_A0)
  49792     { /* SOC_REG_INT_XLPORT_FAULT_LINK_STATUS_BCM88680_A0r */
  49793         soc_block_list[56],
  49794         soc_portreg,
  49795         1,
  49796         0,
  49797         0x20500,
  49798         0,
  49799         0,
  49800         2,
  49801         soc_XLPORT_FAULT_LINK_STATUS_BCM88680_A0r_fields,
  49802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49803         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49804         -1,
  49805         -1,
  49806     },
  49807 #endif /* chips */
  49808 
  49809 #if defined(BCM_2801PM_A0)
  49810     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIGr */
  49811         soc_block_list[56],
  49812         soc_portreg,
  49813         1,
  49814         0,
  49815         0x20700,
  49816         0,
  49817         0,
  49818         2,
  49819         soc_CLPORT_FLOW_CONTROL_CONFIGr_fields,
  49820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49821         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49822         -1,
  49823         -1,
  49824     },
  49825 #endif /* chips */
  49826 
  49827 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  49828     defined(BCM_56670_B0)
  49829     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM53400_A0r */
  49830         soc_block_list[16],
  49831         soc_portreg,
  49832         1,
  49833         0,
  49834         0x20700,
  49835         0,
  49836         0,
  49837         2,
  49838         soc_CLPORT_FLOW_CONTROL_CONFIGr_fields,
  49839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49840         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49841         -1,
  49842         -1,
  49843     },
  49844 #endif /* chips */
  49845 
  49846 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  49847     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM53570_A0r */
  49848         soc_block_list[16],
  49849         soc_portreg,
  49850         1,
  49851         0,
  49852         0x20700,
  49853         0,
  49854         0,
  49855         2,
  49856         soc_CLPORT_FLOW_CONTROL_CONFIGr_fields,
  49857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49858         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49859         -1,
  49860         -1,
  49861     },
  49862 #endif /* chips */
  49863 
  49864 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  49865     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM56160_A0r */
  49866         soc_block_list[16],
  49867         soc_portreg,
  49868         1,
  49869         0,
  49870         0x20700,
  49871         0,
  49872         0,
  49873         2,
  49874         soc_CLPORT_FLOW_CONTROL_CONFIGr_fields,
  49875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49876         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49877         -1,
  49878         -1,
  49879     },
  49880 #endif /* chips */
  49881 
  49882 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  49883     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM56260_A0r */
  49884         soc_block_list[16],
  49885         soc_portreg,
  49886         1,
  49887         0,
  49888         0x20700,
  49889         0,
  49890         0,
  49891         2,
  49892         soc_CLPORT_FLOW_CONTROL_CONFIGr_fields,
  49893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49894         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49895         -1,
  49896         -1,
  49897     },
  49898 #endif /* chips */
  49899 
  49900 #if defined(BCM_56370_A0)
  49901     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM56370_A0r */
  49902         soc_block_list[16],
  49903         soc_portreg,
  49904         1,
  49905         0,
  49906         0x20700,
  49907         0,
  49908         0,
  49909         2,
  49910         soc_CLPORT_FLOW_CONTROL_CONFIGr_fields,
  49911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49912         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49913         -1,
  49914         -1,
  49915         3,
  49916     },
  49917 #endif /* chips */
  49918 
  49919 #if defined(BCM_56560_A0)
  49920     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM56560_A0r */
  49921         soc_block_list[217],
  49922         soc_portreg,
  49923         1,
  49924         0,
  49925         0x20700,
  49926         0,
  49927         0,
  49928         2,
  49929         soc_CLPORT_FLOW_CONTROL_CONFIGr_fields,
  49930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49931         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49932         -1,
  49933         -1,
  49934     },
  49935 #endif /* chips */
  49936 
  49937 #if defined(BCM_56560_B0)
  49938     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM56560_B0r */
  49939         soc_block_list[16],
  49940         soc_portreg,
  49941         1,
  49942         0,
  49943         0x20700,
  49944         0,
  49945         0,
  49946         2,
  49947         soc_CLPORT_FLOW_CONTROL_CONFIGr_fields,
  49948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49949         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49950         -1,
  49951         -1,
  49952     },
  49953 #endif /* chips */
  49954 
  49955 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  49956     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  49957     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  49958     defined(BCM_56980_B0)
  49959     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM56960_A0r */
  49960         soc_block_list[16],
  49961         soc_portreg,
  49962         1,
  49963         0,
  49964         0x20700,
  49965         0,
  49966         0,
  49967         2,
  49968         soc_CLPORT_FLOW_CONTROL_CONFIGr_fields,
  49969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49970         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49971         -1,
  49972         -1,
  49973         3,
  49974     },
  49975 #endif /* chips */
  49976 
  49977 #if defined(BCM_88270_A0)
  49978     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM88270_A0r */
  49979         soc_block_list[56],
  49980         soc_portreg,
  49981         1,
  49982         0,
  49983         0x20700,
  49984         0,
  49985         0,
  49986         2,
  49987         soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88270_A0r_fields,
  49988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49989         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49990         -1,
  49991         -1,
  49992     },
  49993 #endif /* chips */
  49994 
  49995 #if defined(BCM_88375_A0)
  49996     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM88375_A0r */
  49997         soc_block_list[56],
  49998         soc_portreg,
  49999         1,
  50000         0,
  50001         0x20700,
  50002         0,
  50003         0,
  50004         2,
  50005         soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88375_A0r_fields,
  50006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50007         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50008         -1,
  50009         -1,
  50010     },
  50011 #endif /* chips */
  50012 
  50013 #if defined(BCM_88375_B0)
  50014     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM88375_B0r */
  50015         soc_block_list[56],
  50016         soc_portreg,
  50017         1,
  50018         0,
  50019         0x20700,
  50020         0,
  50021         0,
  50022         2,
  50023         soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88375_B0r_fields,
  50024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50025         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50026         -1,
  50027         -1,
  50028     },
  50029 #endif /* chips */
  50030 
  50031 #if defined(BCM_88470_A0)
  50032     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM88470_A0r */
  50033         soc_block_list[56],
  50034         soc_portreg,
  50035         1,
  50036         0,
  50037         0x20700,
  50038         0,
  50039         0,
  50040         2,
  50041         soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88470_A0r_fields,
  50042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50043         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50044         -1,
  50045         -1,
  50046     },
  50047 #endif /* chips */
  50048 
  50049 #if defined(BCM_88470_B0)
  50050     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM88470_B0r */
  50051         soc_block_list[56],
  50052         soc_portreg,
  50053         1,
  50054         0,
  50055         0x20700,
  50056         0,
  50057         0,
  50058         2,
  50059         soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88470_B0r_fields,
  50060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50061         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50062         -1,
  50063         -1,
  50064     },
  50065 #endif /* chips */
  50066 
  50067 #if defined(BCM_88675_A0)
  50068     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM88675_A0r */
  50069         soc_block_list[56],
  50070         soc_portreg,
  50071         1,
  50072         0,
  50073         0x20700,
  50074         0,
  50075         0,
  50076         2,
  50077         soc_XLPORT_FLOW_CONTROL_CONFIGr_fields,
  50078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50079         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50080         -1,
  50081         -1,
  50082     },
  50083 #endif /* chips */
  50084 
  50085 #if defined(BCM_88675_B0)
  50086     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM88675_B0r */
  50087         soc_block_list[56],
  50088         soc_portreg,
  50089         1,
  50090         0,
  50091         0x20700,
  50092         0,
  50093         0,
  50094         2,
  50095         soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88675_B0r_fields,
  50096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50097         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50098         -1,
  50099         -1,
  50100     },
  50101 #endif /* chips */
  50102 
  50103 #if defined(BCM_88680_A0)
  50104     { /* SOC_REG_INT_XLPORT_FLOW_CONTROL_CONFIG_BCM88680_A0r */
  50105         soc_block_list[56],
  50106         soc_portreg,
  50107         1,
  50108         0,
  50109         0x20700,
  50110         0,
  50111         0,
  50112         2,
  50113         soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88680_A0r_fields,
  50114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50115         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50116         -1,
  50117         -1,
  50118     },
  50119 #endif /* chips */
  50120 
  50121 #if defined(BCM_56840_A0)
  50122     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERRORr */
  50123         soc_block_list[16],
  50124         soc_genreg,
  50125         1,
  50126         0,
  50127         0x80243,
  50128         0,
  50129         0,
  50130         10,
  50131         soc_XLPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  50132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50133         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50134         -1,
  50135         -1,
  50136     },
  50137 #endif /* chips */
  50138 
  50139 #if defined(BCM_2801PM_A0)
  50140     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM2801PM_A0r */
  50141         soc_block_list[56],
  50142         soc_genreg,
  50143         1,
  50144         0,
  50145         0x2021b00,
  50146         0,
  50147         0,
  50148         4,
  50149         soc_CLPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  50150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50151         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50152         -1,
  50153         -1,
  50154     },
  50155 #endif /* chips */
  50156 
  50157 #if defined(BCM_53400_A0)
  50158     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r */
  50159         soc_block_list[16],
  50160         soc_genreg,
  50161         1,
  50162         0,
  50163         0x2021b00,
  50164         0,
  50165         0,
  50166         4,
  50167         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50169         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50170         -1,
  50171         -1,
  50172     },
  50173 #endif /* chips */
  50174 
  50175 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  50176     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53570_A0r */
  50177         soc_block_list[16],
  50178         soc_genreg,
  50179         1,
  50180         0,
  50181         0x2021b00,
  50182         0,
  50183         0,
  50184         9,
  50185         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53570_A0r_fields,
  50186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50187         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50188         -1,
  50189         -1,
  50190     },
  50191 #endif /* chips */
  50192 
  50193 #if defined(BCM_56150_A0)
  50194     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM56150_A0r */
  50195         soc_block_list[16],
  50196         soc_genreg,
  50197         1,
  50198         0,
  50199         0x2021b00,
  50200         0,
  50201         0,
  50202         4,
  50203         soc_PGW_FORCE_DOUBLE_BIT_ERRORr_fields,
  50204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50205         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50206         -1,
  50207         -1,
  50208     },
  50209 #endif /* chips */
  50210 
  50211 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  50212     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM56160_A0r */
  50213         soc_block_list[16],
  50214         soc_genreg,
  50215         1,
  50216         0,
  50217         0x2021b00,
  50218         0,
  50219         0,
  50220         4,
  50221         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50223         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50224         -1,
  50225         -1,
  50226     },
  50227 #endif /* chips */
  50228 
  50229 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  50230     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM56260_A0r */
  50231         soc_block_list[16],
  50232         soc_genreg,
  50233         1,
  50234         0,
  50235         0x2021b00,
  50236         0,
  50237         0,
  50238         4,
  50239         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50241         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50242         -1,
  50243         -1,
  50244     },
  50245 #endif /* chips */
  50246 
  50247 #if defined(BCM_56370_A0)
  50248     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM56370_A0r */
  50249         soc_block_list[16],
  50250         soc_genreg,
  50251         1,
  50252         0,
  50253         0x2021b00,
  50254         0,
  50255         0,
  50256         4,
  50257         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50259         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50260         -1,
  50261         -1,
  50262         3,
  50263     },
  50264 #endif /* chips */
  50265 
  50266 #if defined(BCM_56560_A0)
  50267     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM56560_A0r */
  50268         soc_block_list[217],
  50269         soc_genreg,
  50270         1,
  50271         0,
  50272         0x2021b00,
  50273         0,
  50274         0,
  50275         4,
  50276         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50278         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50279         -1,
  50280         -1,
  50281     },
  50282 #endif /* chips */
  50283 
  50284 #if defined(BCM_56560_B0)
  50285     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM56560_B0r */
  50286         soc_block_list[16],
  50287         soc_genreg,
  50288         1,
  50289         0,
  50290         0x2021b00,
  50291         0,
  50292         0,
  50293         4,
  50294         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50296         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50297         -1,
  50298         -1,
  50299     },
  50300 #endif /* chips */
  50301 
  50302 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  50303     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM56670_A0r */
  50304         soc_block_list[16],
  50305         soc_genreg,
  50306         1,
  50307         0,
  50308         0x2021b00,
  50309         0,
  50310         0,
  50311         9,
  50312         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53570_A0r_fields,
  50313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50314         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50315         -1,
  50316         -1,
  50317     },
  50318 #endif /* chips */
  50319 
  50320 #if defined(BCM_56840_B0)
  50321     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM56840_B0r */
  50322         soc_block_list[16],
  50323         soc_genreg,
  50324         1,
  50325         0,
  50326         0x80243,
  50327         0,
  50328         0,
  50329         10,
  50330         soc_XLPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  50331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50332         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50333         -1,
  50334         -1,
  50335     },
  50336 #endif /* chips */
  50337 
  50338 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  50339     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  50340     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  50341     defined(BCM_56980_B0)
  50342     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM56960_A0r */
  50343         soc_block_list[16],
  50344         soc_genreg,
  50345         1,
  50346         0,
  50347         0x2021b00,
  50348         0,
  50349         0,
  50350         4,
  50351         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50353         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50354         -1,
  50355         -1,
  50356         3,
  50357     },
  50358 #endif /* chips */
  50359 
  50360 #if defined(BCM_88270_A0)
  50361     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88270_A0r */
  50362         soc_block_list[56],
  50363         soc_genreg,
  50364         1,
  50365         0,
  50366         0x2021b00,
  50367         0,
  50368         0,
  50369         4,
  50370         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88270_A0r_fields,
  50371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50372         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50373         -1,
  50374         -1,
  50375     },
  50376 #endif /* chips */
  50377 
  50378 #if defined(BCM_88375_A0)
  50379     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88375_A0r */
  50380         soc_block_list[56],
  50381         soc_genreg,
  50382         1,
  50383         0,
  50384         0x2021b00,
  50385         0,
  50386         0,
  50387         4,
  50388         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88375_A0r_fields,
  50389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50390         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50391         -1,
  50392         -1,
  50393     },
  50394 #endif /* chips */
  50395 
  50396 #if defined(BCM_88375_B0)
  50397     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88375_B0r */
  50398         soc_block_list[56],
  50399         soc_genreg,
  50400         1,
  50401         0,
  50402         0x2021b00,
  50403         0,
  50404         0,
  50405         4,
  50406         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88375_B0r_fields,
  50407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50408         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50409         -1,
  50410         -1,
  50411     },
  50412 #endif /* chips */
  50413 
  50414 #if defined(BCM_88470_A0)
  50415     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88470_A0r */
  50416         soc_block_list[56],
  50417         soc_genreg,
  50418         1,
  50419         0,
  50420         0x2021b00,
  50421         0,
  50422         0,
  50423         4,
  50424         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88470_A0r_fields,
  50425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50426         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50427         -1,
  50428         -1,
  50429     },
  50430 #endif /* chips */
  50431 
  50432 #if defined(BCM_88470_B0)
  50433     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88470_B0r */
  50434         soc_block_list[56],
  50435         soc_genreg,
  50436         1,
  50437         0,
  50438         0x2021b00,
  50439         0,
  50440         0,
  50441         4,
  50442         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88470_B0r_fields,
  50443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50444         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50445         -1,
  50446         -1,
  50447     },
  50448 #endif /* chips */
  50449 
  50450 #if defined(BCM_88675_A0)
  50451     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88675_A0r */
  50452         soc_block_list[56],
  50453         soc_genreg,
  50454         1,
  50455         0,
  50456         0x2021b00,
  50457         0,
  50458         0,
  50459         4,
  50460         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88675_A0r_fields,
  50461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50462         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50463         -1,
  50464         -1,
  50465     },
  50466 #endif /* chips */
  50467 
  50468 #if defined(BCM_88675_B0)
  50469     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88675_B0r */
  50470         soc_block_list[56],
  50471         soc_genreg,
  50472         1,
  50473         0,
  50474         0x2021b00,
  50475         0,
  50476         0,
  50477         4,
  50478         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88675_B0r_fields,
  50479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50480         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50481         -1,
  50482         -1,
  50483     },
  50484 #endif /* chips */
  50485 
  50486 #if defined(BCM_88680_A0)
  50487     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88680_A0r */
  50488         soc_block_list[56],
  50489         soc_genreg,
  50490         1,
  50491         0,
  50492         0x2021b00,
  50493         0,
  50494         0,
  50495         4,
  50496         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88680_A0r_fields,
  50497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50498         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50499         -1,
  50500         -1,
  50501     },
  50502 #endif /* chips */
  50503 
  50504 #if defined(BCM_88732_A0)
  50505     { /* SOC_REG_INT_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88732_A0r */
  50506         soc_block_list[16],
  50507         soc_genreg,
  50508         1,
  50509         0,
  50510         0x80243,
  50511         0,
  50512         0,
  50513         10,
  50514         soc_XLPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  50515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50516         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50517         -1,
  50518         -1,
  50519     },
  50520 #endif /* chips */
  50521 
  50522 #if defined(BCM_56840_A0)
  50523     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERRORr */
  50524         soc_block_list[16],
  50525         soc_genreg,
  50526         1,
  50527         0,
  50528         0x80244,
  50529         0,
  50530         0,
  50531         10,
  50532         soc_XLPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  50533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50534         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50535         -1,
  50536         -1,
  50537     },
  50538 #endif /* chips */
  50539 
  50540 #if defined(BCM_2801PM_A0)
  50541     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM2801PM_A0r */
  50542         soc_block_list[56],
  50543         soc_genreg,
  50544         1,
  50545         0,
  50546         0x2021c00,
  50547         0,
  50548         0,
  50549         4,
  50550         soc_CLPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  50551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50552         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50553         -1,
  50554         -1,
  50555     },
  50556 #endif /* chips */
  50557 
  50558 #if defined(BCM_53400_A0)
  50559     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM53400_A0r */
  50560         soc_block_list[16],
  50561         soc_genreg,
  50562         1,
  50563         0,
  50564         0x2021c00,
  50565         0,
  50566         0,
  50567         4,
  50568         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50570         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50571         -1,
  50572         -1,
  50573     },
  50574 #endif /* chips */
  50575 
  50576 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  50577     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM53570_A0r */
  50578         soc_block_list[16],
  50579         soc_genreg,
  50580         1,
  50581         0,
  50582         0x2021c00,
  50583         0,
  50584         0,
  50585         9,
  50586         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53570_A0r_fields,
  50587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50588         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50589         -1,
  50590         -1,
  50591     },
  50592 #endif /* chips */
  50593 
  50594 #if defined(BCM_56150_A0)
  50595     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM56150_A0r */
  50596         soc_block_list[16],
  50597         soc_genreg,
  50598         1,
  50599         0,
  50600         0x2021c00,
  50601         0,
  50602         0,
  50603         4,
  50604         soc_PGW_FORCE_DOUBLE_BIT_ERRORr_fields,
  50605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50606         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50607         -1,
  50608         -1,
  50609     },
  50610 #endif /* chips */
  50611 
  50612 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  50613     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM56160_A0r */
  50614         soc_block_list[16],
  50615         soc_genreg,
  50616         1,
  50617         0,
  50618         0x2021c00,
  50619         0,
  50620         0,
  50621         4,
  50622         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50624         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50625         -1,
  50626         -1,
  50627     },
  50628 #endif /* chips */
  50629 
  50630 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  50631     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM56260_A0r */
  50632         soc_block_list[16],
  50633         soc_genreg,
  50634         1,
  50635         0,
  50636         0x2021c00,
  50637         0,
  50638         0,
  50639         4,
  50640         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50642         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50643         -1,
  50644         -1,
  50645     },
  50646 #endif /* chips */
  50647 
  50648 #if defined(BCM_56370_A0)
  50649     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM56370_A0r */
  50650         soc_block_list[16],
  50651         soc_genreg,
  50652         1,
  50653         0,
  50654         0x2021c00,
  50655         0,
  50656         0,
  50657         4,
  50658         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50660         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50661         -1,
  50662         -1,
  50663         3,
  50664     },
  50665 #endif /* chips */
  50666 
  50667 #if defined(BCM_56560_A0)
  50668     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM56560_A0r */
  50669         soc_block_list[217],
  50670         soc_genreg,
  50671         1,
  50672         0,
  50673         0x2021c00,
  50674         0,
  50675         0,
  50676         4,
  50677         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50679         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50680         -1,
  50681         -1,
  50682     },
  50683 #endif /* chips */
  50684 
  50685 #if defined(BCM_56560_B0)
  50686     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM56560_B0r */
  50687         soc_block_list[16],
  50688         soc_genreg,
  50689         1,
  50690         0,
  50691         0x2021c00,
  50692         0,
  50693         0,
  50694         4,
  50695         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50697         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50698         -1,
  50699         -1,
  50700     },
  50701 #endif /* chips */
  50702 
  50703 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  50704     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM56670_A0r */
  50705         soc_block_list[16],
  50706         soc_genreg,
  50707         1,
  50708         0,
  50709         0x2021c00,
  50710         0,
  50711         0,
  50712         9,
  50713         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53570_A0r_fields,
  50714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50715         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50716         -1,
  50717         -1,
  50718     },
  50719 #endif /* chips */
  50720 
  50721 #if defined(BCM_56840_B0)
  50722     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM56840_B0r */
  50723         soc_block_list[16],
  50724         soc_genreg,
  50725         1,
  50726         0,
  50727         0x80244,
  50728         0,
  50729         0,
  50730         10,
  50731         soc_XLPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  50732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50733         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50734         -1,
  50735         -1,
  50736     },
  50737 #endif /* chips */
  50738 
  50739 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  50740     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  50741     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  50742     defined(BCM_56980_B0)
  50743     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM56960_A0r */
  50744         soc_block_list[16],
  50745         soc_genreg,
  50746         1,
  50747         0,
  50748         0x2021c00,
  50749         0,
  50750         0,
  50751         4,
  50752         soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields,
  50753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50754         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50755         -1,
  50756         -1,
  50757         3,
  50758     },
  50759 #endif /* chips */
  50760 
  50761 #if defined(BCM_88270_A0)
  50762     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88270_A0r */
  50763         soc_block_list[56],
  50764         soc_genreg,
  50765         1,
  50766         0,
  50767         0x2021c00,
  50768         0,
  50769         0,
  50770         4,
  50771         soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88270_A0r_fields,
  50772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50773         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50774         -1,
  50775         -1,
  50776     },
  50777 #endif /* chips */
  50778 
  50779 #if defined(BCM_88375_A0)
  50780     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88375_A0r */
  50781         soc_block_list[56],
  50782         soc_genreg,
  50783         1,
  50784         0,
  50785         0x2021c00,
  50786         0,
  50787         0,
  50788         4,
  50789         soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88375_A0r_fields,
  50790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50791         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50792         -1,
  50793         -1,
  50794     },
  50795 #endif /* chips */
  50796 
  50797 #if defined(BCM_88375_B0)
  50798     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88375_B0r */
  50799         soc_block_list[56],
  50800         soc_genreg,
  50801         1,
  50802         0,
  50803         0x2021c00,
  50804         0,
  50805         0,
  50806         4,
  50807         soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88375_B0r_fields,
  50808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50809         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50810         -1,
  50811         -1,
  50812     },
  50813 #endif /* chips */
  50814 
  50815 #if defined(BCM_88470_A0)
  50816     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88470_A0r */
  50817         soc_block_list[56],
  50818         soc_genreg,
  50819         1,
  50820         0,
  50821         0x2021c00,
  50822         0,
  50823         0,
  50824         4,
  50825         soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88470_A0r_fields,
  50826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50827         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50828         -1,
  50829         -1,
  50830     },
  50831 #endif /* chips */
  50832 
  50833 #if defined(BCM_88470_B0)
  50834     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88470_B0r */
  50835         soc_block_list[56],
  50836         soc_genreg,
  50837         1,
  50838         0,
  50839         0x2021c00,
  50840         0,
  50841         0,
  50842         4,
  50843         soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88470_B0r_fields,
  50844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50845         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50846         -1,
  50847         -1,
  50848     },
  50849 #endif /* chips */
  50850 
  50851 #if defined(BCM_88675_A0)
  50852     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88675_A0r */
  50853         soc_block_list[56],
  50854         soc_genreg,
  50855         1,
  50856         0,
  50857         0x2021c00,
  50858         0,
  50859         0,
  50860         4,
  50861         soc_XLPORT_FORCE_SINGLE_BIT_ERRORr_fields,
  50862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50863         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50864         -1,
  50865         -1,
  50866     },
  50867 #endif /* chips */
  50868 
  50869 #if defined(BCM_88675_B0)
  50870     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88675_B0r */
  50871         soc_block_list[56],
  50872         soc_genreg,
  50873         1,
  50874         0,
  50875         0x2021c00,
  50876         0,
  50877         0,
  50878         4,
  50879         soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88675_B0r_fields,
  50880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50881         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50882         -1,
  50883         -1,
  50884     },
  50885 #endif /* chips */
  50886 
  50887 #if defined(BCM_88680_A0)
  50888     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88680_A0r */
  50889         soc_block_list[56],
  50890         soc_genreg,
  50891         1,
  50892         0,
  50893         0x2021c00,
  50894         0,
  50895         0,
  50896         4,
  50897         soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88680_A0r_fields,
  50898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50899         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50900         -1,
  50901         -1,
  50902     },
  50903 #endif /* chips */
  50904 
  50905 #if defined(BCM_88732_A0)
  50906     { /* SOC_REG_INT_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88732_A0r */
  50907         soc_block_list[16],
  50908         soc_genreg,
  50909         1,
  50910         0,
  50911         0x80244,
  50912         0,
  50913         0,
  50914         10,
  50915         soc_XLPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  50916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50917         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50918         -1,
  50919         -1,
  50920     },
  50921 #endif /* chips */
  50922 
  50923 #if defined(BCM_56860_A0)
  50924     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE0r */
  50925         soc_block_list[16],
  50926         soc_genreg,
  50927         1,
  50928         0,
  50929         0x2020900,
  50930         0,
  50931         0,
  50932         1,
  50933         soc_XLPORT_GENERAL_SPARE0r_fields,
  50934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50935         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50936         -1,
  50937         -1,
  50938     },
  50939 #endif /* chips */
  50940 
  50941 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  50942     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  50943     defined(BCM_56980_B0)
  50944     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE1_REGr */
  50945         soc_block_list[16],
  50946         soc_genreg,
  50947         1,
  50948         0,
  50949         0x2022e00,
  50950         0,
  50951         0,
  50952         1,
  50953         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  50954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50955         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50956         -1,
  50957         -1,
  50958         3,
  50959     },
  50960 #endif /* chips */
  50961 
  50962 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  50963     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE1_REG_BCM53570_A0r */
  50964         soc_block_list[16],
  50965         soc_genreg,
  50966         1,
  50967         0,
  50968         0x2022e00,
  50969         0,
  50970         0,
  50971         1,
  50972         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  50973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50974         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50975         -1,
  50976         -1,
  50977     },
  50978 #endif /* chips */
  50979 
  50980 #if defined(BCM_56370_A0)
  50981     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE1_REG_BCM56370_A0r */
  50982         soc_block_list[16],
  50983         soc_genreg,
  50984         1,
  50985         0,
  50986         0x2022e00,
  50987         0,
  50988         0,
  50989         1,
  50990         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  50991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50992         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50993         -1,
  50994         -1,
  50995         3,
  50996     },
  50997 #endif /* chips */
  50998 
  50999 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  51000     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE1_REG_BCM56670_A0r */
  51001         soc_block_list[16],
  51002         soc_genreg,
  51003         1,
  51004         0,
  51005         0x2022e00,
  51006         0,
  51007         0,
  51008         1,
  51009         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51012         -1,
  51013         -1,
  51014     },
  51015 #endif /* chips */
  51016 
  51017 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  51018     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  51019     defined(BCM_56980_B0)
  51020     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE2_REGr */
  51021         soc_block_list[16],
  51022         soc_genreg,
  51023         1,
  51024         0,
  51025         0x2022f00,
  51026         0,
  51027         0,
  51028         1,
  51029         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51032         -1,
  51033         -1,
  51034         3,
  51035     },
  51036 #endif /* chips */
  51037 
  51038 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  51039     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE2_REG_BCM53570_A0r */
  51040         soc_block_list[16],
  51041         soc_genreg,
  51042         1,
  51043         0,
  51044         0x2022f00,
  51045         0,
  51046         0,
  51047         1,
  51048         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51050         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51051         -1,
  51052         -1,
  51053     },
  51054 #endif /* chips */
  51055 
  51056 #if defined(BCM_56370_A0)
  51057     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE2_REG_BCM56370_A0r */
  51058         soc_block_list[16],
  51059         soc_genreg,
  51060         1,
  51061         0,
  51062         0x2022f00,
  51063         0,
  51064         0,
  51065         1,
  51066         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51068         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51069         -1,
  51070         -1,
  51071         3,
  51072     },
  51073 #endif /* chips */
  51074 
  51075 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  51076     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE2_REG_BCM56670_A0r */
  51077         soc_block_list[16],
  51078         soc_genreg,
  51079         1,
  51080         0,
  51081         0x2022f00,
  51082         0,
  51083         0,
  51084         1,
  51085         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51088         -1,
  51089         -1,
  51090     },
  51091 #endif /* chips */
  51092 
  51093 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  51094     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  51095     defined(BCM_56980_B0)
  51096     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE3_REGr */
  51097         soc_block_list[16],
  51098         soc_genreg,
  51099         1,
  51100         0,
  51101         0x2023000,
  51102         0,
  51103         0,
  51104         1,
  51105         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51107         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51108         -1,
  51109         -1,
  51110         3,
  51111     },
  51112 #endif /* chips */
  51113 
  51114 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  51115     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE3_REG_BCM53570_A0r */
  51116         soc_block_list[16],
  51117         soc_genreg,
  51118         1,
  51119         0,
  51120         0x2023000,
  51121         0,
  51122         0,
  51123         1,
  51124         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51126         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51127         -1,
  51128         -1,
  51129     },
  51130 #endif /* chips */
  51131 
  51132 #if defined(BCM_56370_A0)
  51133     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE3_REG_BCM56370_A0r */
  51134         soc_block_list[16],
  51135         soc_genreg,
  51136         1,
  51137         0,
  51138         0x2023000,
  51139         0,
  51140         0,
  51141         1,
  51142         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51144         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51145         -1,
  51146         -1,
  51147         3,
  51148     },
  51149 #endif /* chips */
  51150 
  51151 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  51152     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE3_REG_BCM56670_A0r */
  51153         soc_block_list[16],
  51154         soc_genreg,
  51155         1,
  51156         0,
  51157         0x2023000,
  51158         0,
  51159         0,
  51160         1,
  51161         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51163         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51164         -1,
  51165         -1,
  51166     },
  51167 #endif /* chips */
  51168 
  51169 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  51170     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE4_REGr */
  51171         soc_block_list[16],
  51172         soc_genreg,
  51173         1,
  51174         0,
  51175         0x2024c00,
  51176         0,
  51177         0,
  51178         1,
  51179         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51182         -1,
  51183         -1,
  51184     },
  51185 #endif /* chips */
  51186 
  51187 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  51188     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE4_REG_BCM56670_A0r */
  51189         soc_block_list[16],
  51190         soc_genreg,
  51191         1,
  51192         0,
  51193         0x2024d00,
  51194         0,
  51195         0,
  51196         1,
  51197         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51200         -1,
  51201         -1,
  51202     },
  51203 #endif /* chips */
  51204 
  51205 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  51206     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE5_REGr */
  51207         soc_block_list[16],
  51208         soc_genreg,
  51209         1,
  51210         0,
  51211         0x2024d00,
  51212         0,
  51213         0,
  51214         1,
  51215         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51217         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51218         -1,
  51219         -1,
  51220     },
  51221 #endif /* chips */
  51222 
  51223 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  51224     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE5_REG_BCM56670_A0r */
  51225         soc_block_list[16],
  51226         soc_genreg,
  51227         1,
  51228         0,
  51229         0x2024e00,
  51230         0,
  51231         0,
  51232         1,
  51233         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51235         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51236         -1,
  51237         -1,
  51238     },
  51239 #endif /* chips */
  51240 
  51241 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  51242     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE6_REGr */
  51243         soc_block_list[16],
  51244         soc_genreg,
  51245         1,
  51246         0,
  51247         0x2024e00,
  51248         0,
  51249         0,
  51250         1,
  51251         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51253         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51254         -1,
  51255         -1,
  51256     },
  51257 #endif /* chips */
  51258 
  51259 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  51260     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE6_REG_BCM56670_A0r */
  51261         soc_block_list[16],
  51262         soc_genreg,
  51263         1,
  51264         0,
  51265         0x2024f00,
  51266         0,
  51267         0,
  51268         1,
  51269         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51271         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51272         -1,
  51273         -1,
  51274     },
  51275 #endif /* chips */
  51276 
  51277 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  51278     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE7_REGr */
  51279         soc_block_list[16],
  51280         soc_genreg,
  51281         1,
  51282         0,
  51283         0x2024f00,
  51284         0,
  51285         0,
  51286         1,
  51287         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51289         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51290         -1,
  51291         -1,
  51292     },
  51293 #endif /* chips */
  51294 
  51295 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  51296     { /* SOC_REG_INT_XLPORT_GENERAL_SPARE7_REG_BCM56670_A0r */
  51297         soc_block_list[16],
  51298         soc_genreg,
  51299         1,
  51300         0,
  51301         0x2025000,
  51302         0,
  51303         0,
  51304         1,
  51305         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  51306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  51308         -1,
  51309         -1,
  51310     },
  51311 #endif /* chips */
  51312 
  51313 #if defined(BCM_56840_A0)
  51314     { /* SOC_REG_INT_XLPORT_INTR_ENABLEr */
  51315         soc_block_list[16],
  51316         soc_genreg,
  51317         1,
  51318         0,
  51319         0x80253,
  51320         0,
  51321         0,
  51322         10,
  51323         soc_XLPORT_INTR_ENABLEr_fields,
  51324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51325         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  51326         -1,
  51327         -1,
  51328     },
  51329 #endif /* chips */
  51330 
  51331 #if defined(BCM_2801PM_A0)
  51332     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM2801PM_A0r */
  51333         soc_block_list[56],
  51334         soc_genreg,
  51335         1,
  51336         0,
  51337         0x2022a00,
  51338         0,
  51339         0,
  51340         6,
  51341         soc_XLPORT_INTR_ENABLE_BCM2801PM_A0r_fields,
  51342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51343         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51344         -1,
  51345         -1,
  51346     },
  51347 #endif /* chips */
  51348 
  51349 #if defined(BCM_53400_A0)
  51350     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM53400_A0r */
  51351         soc_block_list[16],
  51352         soc_genreg,
  51353         1,
  51354         0,
  51355         0x2022a00,
  51356         0,
  51357         0,
  51358         6,
  51359         soc_XLPORT_INTR_ENABLE_BCM53400_A0r_fields,
  51360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51361         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51362         -1,
  51363         -1,
  51364     },
  51365 #endif /* chips */
  51366 
  51367 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  51368     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM53570_A0r */
  51369         soc_block_list[16],
  51370         soc_genreg,
  51371         1,
  51372         0,
  51373         0x2022a00,
  51374         0,
  51375         0,
  51376         8,
  51377         soc_XLPORT_INTR_ENABLE_BCM56970_A0r_fields,
  51378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51379         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  51380         -1,
  51381         -1,
  51382     },
  51383 #endif /* chips */
  51384 
  51385 #if defined(BCM_56150_A0)
  51386     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56150_A0r */
  51387         soc_block_list[16],
  51388         soc_genreg,
  51389         1,
  51390         0,
  51391         0x2023000,
  51392         0,
  51393         0,
  51394         9,
  51395         soc_XLPORT_INTR_ENABLE_BCM56150_A0r_fields,
  51396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51397         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51398         -1,
  51399         -1,
  51400     },
  51401 #endif /* chips */
  51402 
  51403 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  51404     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56160_A0r */
  51405         soc_block_list[16],
  51406         soc_genreg,
  51407         1,
  51408         0,
  51409         0x2022a00,
  51410         0,
  51411         0,
  51412         6,
  51413         soc_XLPORT_INTR_ENABLE_BCM56160_A0r_fields,
  51414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51415         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51416         -1,
  51417         -1,
  51418     },
  51419 #endif /* chips */
  51420 
  51421 #if defined(BCM_56260_A0)
  51422     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56260_A0r */
  51423         soc_block_list[16],
  51424         soc_genreg,
  51425         1,
  51426         0,
  51427         0x2022a00,
  51428         0,
  51429         0,
  51430         6,
  51431         soc_XLPORT_INTR_ENABLE_BCM53400_A0r_fields,
  51432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51433         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51434         -1,
  51435         -1,
  51436     },
  51437 #endif /* chips */
  51438 
  51439 #if defined(BCM_56260_B0)
  51440     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56260_B0r */
  51441         soc_block_list[16],
  51442         soc_genreg,
  51443         1,
  51444         0,
  51445         0x2022a00,
  51446         0,
  51447         0,
  51448         6,
  51449         soc_XLPORT_INTR_ENABLE_BCM56960_A0r_fields,
  51450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51451         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51452         -1,
  51453         -1,
  51454     },
  51455 #endif /* chips */
  51456 
  51457 #if defined(BCM_56370_A0)
  51458     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56370_A0r */
  51459         soc_block_list[16],
  51460         soc_genreg,
  51461         1,
  51462         0,
  51463         0x2022a00,
  51464         0,
  51465         0,
  51466         8,
  51467         soc_XLPORT_INTR_ENABLE_BCM56970_A0r_fields,
  51468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51469         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  51470         -1,
  51471         -1,
  51472         3,
  51473     },
  51474 #endif /* chips */
  51475 
  51476 #if defined(BCM_56560_A0)
  51477     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56560_A0r */
  51478         soc_block_list[217],
  51479         soc_genreg,
  51480         1,
  51481         0,
  51482         0x2022a00,
  51483         0,
  51484         0,
  51485         6,
  51486         soc_XLPORT_INTR_ENABLE_BCM56960_A0r_fields,
  51487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51488         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51489         -1,
  51490         -1,
  51491     },
  51492 #endif /* chips */
  51493 
  51494 #if defined(BCM_56560_B0)
  51495     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56560_B0r */
  51496         soc_block_list[16],
  51497         soc_genreg,
  51498         1,
  51499         0,
  51500         0x2022a00,
  51501         0,
  51502         0,
  51503         6,
  51504         soc_XLPORT_INTR_ENABLE_BCM56960_A0r_fields,
  51505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51506         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51507         -1,
  51508         -1,
  51509     },
  51510 #endif /* chips */
  51511 
  51512 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  51513     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56670_A0r */
  51514         soc_block_list[16],
  51515         soc_genreg,
  51516         1,
  51517         0,
  51518         0x2022a00,
  51519         0,
  51520         0,
  51521         8,
  51522         soc_XLPORT_INTR_ENABLE_BCM56970_A0r_fields,
  51523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51524         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  51525         -1,
  51526         -1,
  51527     },
  51528 #endif /* chips */
  51529 
  51530 #if defined(BCM_56840_B0)
  51531     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56840_B0r */
  51532         soc_block_list[16],
  51533         soc_genreg,
  51534         1,
  51535         0,
  51536         0x80253,
  51537         0,
  51538         0,
  51539         10,
  51540         soc_XLPORT_INTR_ENABLEr_fields,
  51541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51542         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  51543         -1,
  51544         -1,
  51545     },
  51546 #endif /* chips */
  51547 
  51548 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  51549     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56850_A0r */
  51550         soc_block_list[16],
  51551         soc_genreg,
  51552         1,
  51553         0,
  51554         0x2021900,
  51555         0,
  51556         0,
  51557         2,
  51558         soc_XLPORT_INTR_ENABLE_BCM56850_A0r_fields,
  51559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51560         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  51561         -1,
  51562         -1,
  51563     },
  51564 #endif /* chips */
  51565 
  51566 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  51567     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56960_A0r */
  51568         soc_block_list[16],
  51569         soc_genreg,
  51570         1,
  51571         0,
  51572         0x2022a00,
  51573         0,
  51574         0,
  51575         6,
  51576         soc_XLPORT_INTR_ENABLE_BCM56960_A0r_fields,
  51577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51578         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51579         -1,
  51580         -1,
  51581         3,
  51582     },
  51583 #endif /* chips */
  51584 
  51585 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  51586     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  51587     defined(BCM_56980_B0)
  51588     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM56970_A0r */
  51589         soc_block_list[16],
  51590         soc_genreg,
  51591         1,
  51592         0,
  51593         0x2022a00,
  51594         0,
  51595         0,
  51596         8,
  51597         soc_XLPORT_INTR_ENABLE_BCM56970_A0r_fields,
  51598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51599         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  51600         -1,
  51601         -1,
  51602         3,
  51603     },
  51604 #endif /* chips */
  51605 
  51606 #if defined(BCM_88270_A0)
  51607     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM88270_A0r */
  51608         soc_block_list[56],
  51609         soc_genreg,
  51610         1,
  51611         0,
  51612         0x2022a00,
  51613         0,
  51614         0,
  51615         6,
  51616         soc_XLPORT_INTR_ENABLE_BCM88270_A0r_fields,
  51617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51618         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51619         -1,
  51620         -1,
  51621     },
  51622 #endif /* chips */
  51623 
  51624 #if defined(BCM_88375_A0)
  51625     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM88375_A0r */
  51626         soc_block_list[56],
  51627         soc_genreg,
  51628         1,
  51629         0,
  51630         0x2022a00,
  51631         0,
  51632         0,
  51633         6,
  51634         soc_XLPORT_INTR_ENABLE_BCM88375_A0r_fields,
  51635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51636         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51637         -1,
  51638         -1,
  51639     },
  51640 #endif /* chips */
  51641 
  51642 #if defined(BCM_88375_B0)
  51643     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM88375_B0r */
  51644         soc_block_list[56],
  51645         soc_genreg,
  51646         1,
  51647         0,
  51648         0x2022a00,
  51649         0,
  51650         0,
  51651         6,
  51652         soc_XLPORT_INTR_ENABLE_BCM88375_B0r_fields,
  51653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51654         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51655         -1,
  51656         -1,
  51657     },
  51658 #endif /* chips */
  51659 
  51660 #if defined(BCM_88470_A0)
  51661     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM88470_A0r */
  51662         soc_block_list[56],
  51663         soc_genreg,
  51664         1,
  51665         0,
  51666         0x2022a00,
  51667         0,
  51668         0,
  51669         6,
  51670         soc_XLPORT_INTR_ENABLE_BCM88470_A0r_fields,
  51671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51672         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51673         -1,
  51674         -1,
  51675     },
  51676 #endif /* chips */
  51677 
  51678 #if defined(BCM_88470_B0)
  51679     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM88470_B0r */
  51680         soc_block_list[56],
  51681         soc_genreg,
  51682         1,
  51683         0,
  51684         0x2022a00,
  51685         0,
  51686         0,
  51687         6,
  51688         soc_XLPORT_INTR_ENABLE_BCM88470_B0r_fields,
  51689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51690         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51691         -1,
  51692         -1,
  51693     },
  51694 #endif /* chips */
  51695 
  51696 #if defined(BCM_88675_A0)
  51697     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM88675_A0r */
  51698         soc_block_list[56],
  51699         soc_genreg,
  51700         1,
  51701         0,
  51702         0x2022a00,
  51703         0,
  51704         0,
  51705         6,
  51706         soc_XLPORT_INTR_ENABLE_BCM88675_A0r_fields,
  51707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51708         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51709         -1,
  51710         -1,
  51711     },
  51712 #endif /* chips */
  51713 
  51714 #if defined(BCM_88675_B0)
  51715     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM88675_B0r */
  51716         soc_block_list[56],
  51717         soc_genreg,
  51718         1,
  51719         0,
  51720         0x2022a00,
  51721         0,
  51722         0,
  51723         6,
  51724         soc_XLPORT_INTR_ENABLE_BCM88675_B0r_fields,
  51725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51726         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51727         -1,
  51728         -1,
  51729     },
  51730 #endif /* chips */
  51731 
  51732 #if defined(BCM_88680_A0)
  51733     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM88680_A0r */
  51734         soc_block_list[56],
  51735         soc_genreg,
  51736         1,
  51737         0,
  51738         0x2022a00,
  51739         0,
  51740         0,
  51741         6,
  51742         soc_XLPORT_INTR_ENABLE_BCM88680_A0r_fields,
  51743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51744         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51745         -1,
  51746         -1,
  51747     },
  51748 #endif /* chips */
  51749 
  51750 #if defined(BCM_88732_A0)
  51751     { /* SOC_REG_INT_XLPORT_INTR_ENABLE_BCM88732_A0r */
  51752         soc_block_list[16],
  51753         soc_genreg,
  51754         1,
  51755         0,
  51756         0x80253,
  51757         0,
  51758         0,
  51759         10,
  51760         soc_XLPORT_INTR_ENABLEr_fields,
  51761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51762         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  51763         -1,
  51764         -1,
  51765     },
  51766 #endif /* chips */
  51767 
  51768 #if defined(BCM_56840_A0)
  51769     { /* SOC_REG_INT_XLPORT_INTR_STATUSr */
  51770         soc_block_list[16],
  51771         soc_genreg,
  51772         1,
  51773         0,
  51774         0x80252,
  51775         SOC_REG_FLAG_RO,
  51776         0,
  51777         10,
  51778         soc_XLPORT_INTR_STATUSr_fields,
  51779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51780         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  51781         -1,
  51782         -1,
  51783     },
  51784 #endif /* chips */
  51785 
  51786 #if defined(BCM_2801PM_A0)
  51787     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM2801PM_A0r */
  51788         soc_block_list[56],
  51789         soc_genreg,
  51790         1,
  51791         0,
  51792         0x2022900,
  51793         SOC_REG_FLAG_RO |
  51794                           SOC_REG_FLAG_SIGNAL,
  51795         0,
  51796         6,
  51797         soc_XLPORT_INTR_STATUS_BCM2801PM_A0r_fields,
  51798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51799         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51800         -1,
  51801         -1,
  51802     },
  51803 #endif /* chips */
  51804 
  51805 #if defined(BCM_53400_A0)
  51806     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM53400_A0r */
  51807         soc_block_list[16],
  51808         soc_genreg,
  51809         1,
  51810         0,
  51811         0x2022900,
  51812         SOC_REG_FLAG_RO,
  51813         0,
  51814         6,
  51815         soc_XLPORT_INTR_STATUS_BCM53400_A0r_fields,
  51816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51817         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51818         -1,
  51819         -1,
  51820     },
  51821 #endif /* chips */
  51822 
  51823 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  51824     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM53570_A0r */
  51825         soc_block_list[16],
  51826         soc_genreg,
  51827         1,
  51828         0,
  51829         0x2022900,
  51830         SOC_REG_FLAG_RO,
  51831         0,
  51832         8,
  51833         soc_XLPORT_INTR_STATUS_BCM56970_A0r_fields,
  51834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51835         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  51836         -1,
  51837         -1,
  51838     },
  51839 #endif /* chips */
  51840 
  51841 #if defined(BCM_56150_A0)
  51842     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM56150_A0r */
  51843         soc_block_list[16],
  51844         soc_genreg,
  51845         1,
  51846         0,
  51847         0x2022f00,
  51848         SOC_REG_FLAG_RO,
  51849         0,
  51850         9,
  51851         soc_XLPORT_INTR_STATUS_BCM56150_A0r_fields,
  51852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51853         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51854         -1,
  51855         -1,
  51856     },
  51857 #endif /* chips */
  51858 
  51859 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  51860     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM56160_A0r */
  51861         soc_block_list[16],
  51862         soc_genreg,
  51863         1,
  51864         0,
  51865         0x2022900,
  51866         SOC_REG_FLAG_RO,
  51867         0,
  51868         6,
  51869         soc_XLPORT_INTR_STATUS_BCM56160_A0r_fields,
  51870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51871         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51872         -1,
  51873         -1,
  51874     },
  51875 #endif /* chips */
  51876 
  51877 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  51878     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM56260_A0r */
  51879         soc_block_list[16],
  51880         soc_genreg,
  51881         1,
  51882         0,
  51883         0x2022900,
  51884         SOC_REG_FLAG_RO,
  51885         0,
  51886         6,
  51887         soc_XLPORT_INTR_STATUS_BCM53400_A0r_fields,
  51888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51889         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51890         -1,
  51891         -1,
  51892     },
  51893 #endif /* chips */
  51894 
  51895 #if defined(BCM_56370_A0)
  51896     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM56370_A0r */
  51897         soc_block_list[16],
  51898         soc_genreg,
  51899         1,
  51900         0,
  51901         0x2022900,
  51902         SOC_REG_FLAG_RO,
  51903         0,
  51904         8,
  51905         soc_XLPORT_INTR_STATUS_BCM56970_A0r_fields,
  51906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51907         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  51908         -1,
  51909         -1,
  51910         3,
  51911     },
  51912 #endif /* chips */
  51913 
  51914 #if defined(BCM_56560_A0)
  51915     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM56560_A0r */
  51916         soc_block_list[217],
  51917         soc_genreg,
  51918         1,
  51919         0,
  51920         0x2022900,
  51921         SOC_REG_FLAG_RO,
  51922         0,
  51923         6,
  51924         soc_XLPORT_INTR_STATUS_BCM53400_A0r_fields,
  51925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51926         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51927         -1,
  51928         -1,
  51929     },
  51930 #endif /* chips */
  51931 
  51932 #if defined(BCM_56560_B0)
  51933     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM56560_B0r */
  51934         soc_block_list[16],
  51935         soc_genreg,
  51936         1,
  51937         0,
  51938         0x2022900,
  51939         SOC_REG_FLAG_RO,
  51940         0,
  51941         6,
  51942         soc_XLPORT_INTR_STATUS_BCM53400_A0r_fields,
  51943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51944         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51945         -1,
  51946         -1,
  51947     },
  51948 #endif /* chips */
  51949 
  51950 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  51951     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM56670_A0r */
  51952         soc_block_list[16],
  51953         soc_genreg,
  51954         1,
  51955         0,
  51956         0x2022900,
  51957         SOC_REG_FLAG_RO,
  51958         0,
  51959         8,
  51960         soc_XLPORT_INTR_STATUS_BCM56970_A0r_fields,
  51961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51962         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  51963         -1,
  51964         -1,
  51965     },
  51966 #endif /* chips */
  51967 
  51968 #if defined(BCM_56840_B0)
  51969     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM56840_B0r */
  51970         soc_block_list[16],
  51971         soc_genreg,
  51972         1,
  51973         0,
  51974         0x80252,
  51975         SOC_REG_FLAG_RO,
  51976         0,
  51977         10,
  51978         soc_XLPORT_INTR_STATUSr_fields,
  51979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51980         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  51981         -1,
  51982         -1,
  51983     },
  51984 #endif /* chips */
  51985 
  51986 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  51987     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM56850_A0r */
  51988         soc_block_list[16],
  51989         soc_genreg,
  51990         1,
  51991         0,
  51992         0x2021800,
  51993         SOC_REG_FLAG_RO,
  51994         0,
  51995         2,
  51996         soc_XLPORT_INTR_STATUS_BCM56850_A0r_fields,
  51997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51998         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  51999         -1,
  52000         -1,
  52001     },
  52002 #endif /* chips */
  52003 
  52004 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  52005     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM56960_A0r */
  52006         soc_block_list[16],
  52007         soc_genreg,
  52008         1,
  52009         0,
  52010         0x2022900,
  52011         SOC_REG_FLAG_RO,
  52012         0,
  52013         6,
  52014         soc_XLPORT_INTR_STATUS_BCM53400_A0r_fields,
  52015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52016         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52017         -1,
  52018         -1,
  52019         3,
  52020     },
  52021 #endif /* chips */
  52022 
  52023 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  52024     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  52025     defined(BCM_56980_B0)
  52026     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM56970_A0r */
  52027         soc_block_list[16],
  52028         soc_genreg,
  52029         1,
  52030         0,
  52031         0x2022900,
  52032         SOC_REG_FLAG_RO,
  52033         0,
  52034         8,
  52035         soc_XLPORT_INTR_STATUS_BCM56970_A0r_fields,
  52036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52037         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  52038         -1,
  52039         -1,
  52040         3,
  52041     },
  52042 #endif /* chips */
  52043 
  52044 #if defined(BCM_88270_A0)
  52045     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM88270_A0r */
  52046         soc_block_list[56],
  52047         soc_genreg,
  52048         1,
  52049         0,
  52050         0x2022900,
  52051         SOC_REG_FLAG_RO |
  52052                           SOC_REG_FLAG_SIGNAL,
  52053         0,
  52054         6,
  52055         soc_XLPORT_INTR_STATUS_BCM88270_A0r_fields,
  52056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52057         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52058         -1,
  52059         -1,
  52060     },
  52061 #endif /* chips */
  52062 
  52063 #if defined(BCM_88375_A0)
  52064     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM88375_A0r */
  52065         soc_block_list[56],
  52066         soc_genreg,
  52067         1,
  52068         0,
  52069         0x2022900,
  52070         SOC_REG_FLAG_RO |
  52071                           SOC_REG_FLAG_SIGNAL,
  52072         0,
  52073         6,
  52074         soc_XLPORT_INTR_STATUS_BCM88375_A0r_fields,
  52075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52076         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52077         -1,
  52078         -1,
  52079     },
  52080 #endif /* chips */
  52081 
  52082 #if defined(BCM_88375_B0)
  52083     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM88375_B0r */
  52084         soc_block_list[56],
  52085         soc_genreg,
  52086         1,
  52087         0,
  52088         0x2022900,
  52089         SOC_REG_FLAG_RO |
  52090                           SOC_REG_FLAG_SIGNAL,
  52091         0,
  52092         6,
  52093         soc_XLPORT_INTR_STATUS_BCM88375_B0r_fields,
  52094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52095         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52096         -1,
  52097         -1,
  52098     },
  52099 #endif /* chips */
  52100 
  52101 #if defined(BCM_88470_A0)
  52102     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM88470_A0r */
  52103         soc_block_list[56],
  52104         soc_genreg,
  52105         1,
  52106         0,
  52107         0x2022900,
  52108         SOC_REG_FLAG_RO |
  52109                           SOC_REG_FLAG_SIGNAL,
  52110         0,
  52111         6,
  52112         soc_XLPORT_INTR_STATUS_BCM88470_A0r_fields,
  52113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52114         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52115         -1,
  52116         -1,
  52117     },
  52118 #endif /* chips */
  52119 
  52120 #if defined(BCM_88470_B0)
  52121     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM88470_B0r */
  52122         soc_block_list[56],
  52123         soc_genreg,
  52124         1,
  52125         0,
  52126         0x2022900,
  52127         SOC_REG_FLAG_RO |
  52128                           SOC_REG_FLAG_SIGNAL,
  52129         0,
  52130         6,
  52131         soc_XLPORT_INTR_STATUS_BCM88470_B0r_fields,
  52132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52133         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52134         -1,
  52135         -1,
  52136     },
  52137 #endif /* chips */
  52138 
  52139 #if defined(BCM_88675_A0)
  52140     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM88675_A0r */
  52141         soc_block_list[56],
  52142         soc_genreg,
  52143         1,
  52144         0,
  52145         0x2022900,
  52146         SOC_REG_FLAG_RO |
  52147                           SOC_REG_FLAG_SIGNAL,
  52148         0,
  52149         6,
  52150         soc_XLPORT_INTR_STATUS_BCM88675_A0r_fields,
  52151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52152         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52153         -1,
  52154         -1,
  52155     },
  52156 #endif /* chips */
  52157 
  52158 #if defined(BCM_88675_B0)
  52159     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM88675_B0r */
  52160         soc_block_list[56],
  52161         soc_genreg,
  52162         1,
  52163         0,
  52164         0x2022900,
  52165         SOC_REG_FLAG_RO |
  52166                           SOC_REG_FLAG_SIGNAL,
  52167         0,
  52168         6,
  52169         soc_XLPORT_INTR_STATUS_BCM88675_B0r_fields,
  52170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52171         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52172         -1,
  52173         -1,
  52174     },
  52175 #endif /* chips */
  52176 
  52177 #if defined(BCM_88680_A0)
  52178     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM88680_A0r */
  52179         soc_block_list[56],
  52180         soc_genreg,
  52181         1,
  52182         0,
  52183         0x2022900,
  52184         SOC_REG_FLAG_RO |
  52185                           SOC_REG_FLAG_SIGNAL,
  52186         0,
  52187         6,
  52188         soc_XLPORT_INTR_STATUS_BCM88680_A0r_fields,
  52189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52190         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  52191         -1,
  52192         -1,
  52193     },
  52194 #endif /* chips */
  52195 
  52196 #if defined(BCM_88732_A0)
  52197     { /* SOC_REG_INT_XLPORT_INTR_STATUS_BCM88732_A0r */
  52198         soc_block_list[16],
  52199         soc_genreg,
  52200         1,
  52201         0,
  52202         0x80252,
  52203         SOC_REG_FLAG_RO,
  52204         0,
  52205         10,
  52206         soc_XLPORT_INTR_STATUSr_fields,
  52207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52208         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  52209         -1,
  52210         -1,
  52211     },
  52212 #endif /* chips */
  52213 
  52214 #if defined(BCM_2801PM_A0)
  52215     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIGr */
  52216         soc_block_list[56],
  52217         soc_portreg,
  52218         1,
  52219         0,
  52220         0x20200,
  52221         0,
  52222         0,
  52223         1,
  52224         soc_CLPORT_LAG_FAILOVER_CONFIGr_fields,
  52225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52226         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52227         -1,
  52228         -1,
  52229     },
  52230 #endif /* chips */
  52231 
  52232 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  52233     defined(BCM_56670_B0)
  52234     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM53400_A0r */
  52235         soc_block_list[16],
  52236         soc_portreg,
  52237         1,
  52238         0,
  52239         0x20200,
  52240         0,
  52241         0,
  52242         1,
  52243         soc_CLPORT_LAG_FAILOVER_CONFIGr_fields,
  52244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52245         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52246         -1,
  52247         -1,
  52248     },
  52249 #endif /* chips */
  52250 
  52251 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  52252     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM53570_A0r */
  52253         soc_block_list[16],
  52254         soc_portreg,
  52255         1,
  52256         0,
  52257         0x20200,
  52258         0,
  52259         0,
  52260         1,
  52261         soc_CLPORT_LAG_FAILOVER_CONFIGr_fields,
  52262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52263         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52264         -1,
  52265         -1,
  52266     },
  52267 #endif /* chips */
  52268 
  52269 #if defined(BCM_56150_A0)
  52270     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM56150_A0r */
  52271         soc_block_list[16],
  52272         soc_portreg,
  52273         1,
  52274         0,
  52275         0x20200,
  52276         0,
  52277         0,
  52278         1,
  52279         soc_CPORT_LAG_FAILOVER_CONFIGr_fields,
  52280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52281         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52282         -1,
  52283         -1,
  52284     },
  52285 #endif /* chips */
  52286 
  52287 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  52288     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM56160_A0r */
  52289         soc_block_list[16],
  52290         soc_portreg,
  52291         1,
  52292         0,
  52293         0x20200,
  52294         0,
  52295         0,
  52296         1,
  52297         soc_CLPORT_LAG_FAILOVER_CONFIGr_fields,
  52298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52299         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52300         -1,
  52301         -1,
  52302     },
  52303 #endif /* chips */
  52304 
  52305 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52306     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM56260_A0r */
  52307         soc_block_list[16],
  52308         soc_portreg,
  52309         1,
  52310         0,
  52311         0x20200,
  52312         0,
  52313         0,
  52314         1,
  52315         soc_CLPORT_LAG_FAILOVER_CONFIGr_fields,
  52316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52317         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52318         -1,
  52319         -1,
  52320     },
  52321 #endif /* chips */
  52322 
  52323 #if defined(BCM_56370_A0)
  52324     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM56370_A0r */
  52325         soc_block_list[16],
  52326         soc_portreg,
  52327         1,
  52328         0,
  52329         0x20200,
  52330         0,
  52331         0,
  52332         1,
  52333         soc_CLPORT_LAG_FAILOVER_CONFIGr_fields,
  52334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52335         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52336         -1,
  52337         -1,
  52338         3,
  52339     },
  52340 #endif /* chips */
  52341 
  52342 #if defined(BCM_56560_A0)
  52343     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM56560_A0r */
  52344         soc_block_list[217],
  52345         soc_portreg,
  52346         1,
  52347         0,
  52348         0x20200,
  52349         0,
  52350         0,
  52351         1,
  52352         soc_CLPORT_LAG_FAILOVER_CONFIGr_fields,
  52353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52354         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52355         -1,
  52356         -1,
  52357     },
  52358 #endif /* chips */
  52359 
  52360 #if defined(BCM_56560_B0)
  52361     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM56560_B0r */
  52362         soc_block_list[16],
  52363         soc_portreg,
  52364         1,
  52365         0,
  52366         0x20200,
  52367         0,
  52368         0,
  52369         1,
  52370         soc_CLPORT_LAG_FAILOVER_CONFIGr_fields,
  52371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52372         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52373         -1,
  52374         -1,
  52375     },
  52376 #endif /* chips */
  52377 
  52378 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  52379     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM56850_A0r */
  52380         soc_block_list[16],
  52381         soc_portreg,
  52382         1,
  52383         0,
  52384         0x20100,
  52385         0,
  52386         0,
  52387         1,
  52388         soc_CPORT_LAG_FAILOVER_CONFIGr_fields,
  52389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52390         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52391         -1,
  52392         -1,
  52393     },
  52394 #endif /* chips */
  52395 
  52396 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  52397     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  52398     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  52399     defined(BCM_56980_B0)
  52400     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM56960_A0r */
  52401         soc_block_list[16],
  52402         soc_portreg,
  52403         1,
  52404         0,
  52405         0x20200,
  52406         0,
  52407         0,
  52408         1,
  52409         soc_CLPORT_LAG_FAILOVER_CONFIGr_fields,
  52410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52411         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52412         -1,
  52413         -1,
  52414         3,
  52415     },
  52416 #endif /* chips */
  52417 
  52418 #if defined(BCM_88270_A0)
  52419     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM88270_A0r */
  52420         soc_block_list[56],
  52421         soc_portreg,
  52422         1,
  52423         0,
  52424         0x20200,
  52425         0,
  52426         0,
  52427         1,
  52428         soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88270_A0r_fields,
  52429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52430         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52431         -1,
  52432         -1,
  52433     },
  52434 #endif /* chips */
  52435 
  52436 #if defined(BCM_88375_A0)
  52437     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM88375_A0r */
  52438         soc_block_list[56],
  52439         soc_portreg,
  52440         1,
  52441         0,
  52442         0x20200,
  52443         0,
  52444         0,
  52445         1,
  52446         soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88375_A0r_fields,
  52447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52448         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52449         -1,
  52450         -1,
  52451     },
  52452 #endif /* chips */
  52453 
  52454 #if defined(BCM_88375_B0)
  52455     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM88375_B0r */
  52456         soc_block_list[56],
  52457         soc_portreg,
  52458         1,
  52459         0,
  52460         0x20200,
  52461         0,
  52462         0,
  52463         1,
  52464         soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88375_B0r_fields,
  52465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52466         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52467         -1,
  52468         -1,
  52469     },
  52470 #endif /* chips */
  52471 
  52472 #if defined(BCM_88470_A0)
  52473     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM88470_A0r */
  52474         soc_block_list[56],
  52475         soc_portreg,
  52476         1,
  52477         0,
  52478         0x20200,
  52479         0,
  52480         0,
  52481         1,
  52482         soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88470_A0r_fields,
  52483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52484         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52485         -1,
  52486         -1,
  52487     },
  52488 #endif /* chips */
  52489 
  52490 #if defined(BCM_88470_B0)
  52491     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM88470_B0r */
  52492         soc_block_list[56],
  52493         soc_portreg,
  52494         1,
  52495         0,
  52496         0x20200,
  52497         0,
  52498         0,
  52499         1,
  52500         soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88470_B0r_fields,
  52501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52502         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52503         -1,
  52504         -1,
  52505     },
  52506 #endif /* chips */
  52507 
  52508 #if defined(BCM_88675_A0)
  52509     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM88675_A0r */
  52510         soc_block_list[56],
  52511         soc_portreg,
  52512         1,
  52513         0,
  52514         0x20200,
  52515         0,
  52516         0,
  52517         1,
  52518         soc_XLPORT_LAG_FAILOVER_CONFIGr_fields,
  52519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52520         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52521         -1,
  52522         -1,
  52523     },
  52524 #endif /* chips */
  52525 
  52526 #if defined(BCM_88675_B0)
  52527     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM88675_B0r */
  52528         soc_block_list[56],
  52529         soc_portreg,
  52530         1,
  52531         0,
  52532         0x20200,
  52533         0,
  52534         0,
  52535         1,
  52536         soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88675_B0r_fields,
  52537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52538         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52539         -1,
  52540         -1,
  52541     },
  52542 #endif /* chips */
  52543 
  52544 #if defined(BCM_88680_A0)
  52545     { /* SOC_REG_INT_XLPORT_LAG_FAILOVER_CONFIG_BCM88680_A0r */
  52546         soc_block_list[56],
  52547         soc_portreg,
  52548         1,
  52549         0,
  52550         0x20200,
  52551         0,
  52552         0,
  52553         1,
  52554         soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88680_A0r_fields,
  52555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52556         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  52557         -1,
  52558         -1,
  52559     },
  52560 #endif /* chips */
  52561 
  52562 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  52563     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIGr */
  52564         soc_block_list[16],
  52565         soc_genreg,
  52566         1,
  52567         0,
  52568         0x2021700,
  52569         0,
  52570         0,
  52571         1,
  52572         soc_CPORT_LED_CHAIN_CONFIGr_fields,
  52573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52574         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52575         -1,
  52576         -1,
  52577     },
  52578 #endif /* chips */
  52579 
  52580 #if defined(BCM_53400_A0)
  52581     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM53400_A0r */
  52582         soc_block_list[16],
  52583         soc_genreg,
  52584         1,
  52585         0,
  52586         0x2022300,
  52587         0,
  52588         0,
  52589         1,
  52590         soc_PGW_GX_BYPASS_LED_CHAIN_CONFIGr_fields,
  52591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52592         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52593         -1,
  52594         -1,
  52595     },
  52596 #endif /* chips */
  52597 
  52598 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  52599     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM53570_A0r */
  52600         soc_block_list[16],
  52601         soc_genreg,
  52602         1,
  52603         0,
  52604         0x2022300,
  52605         0,
  52606         0,
  52607         1,
  52608         soc_CXX_CXXPORT_LED_CHAIN_CONFIGr_fields,
  52609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52610         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52611         -1,
  52612         -1,
  52613     },
  52614 #endif /* chips */
  52615 
  52616 #if defined(BCM_56150_A0)
  52617     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM56150_A0r */
  52618         soc_block_list[16],
  52619         soc_genreg,
  52620         1,
  52621         0,
  52622         0x2022b00,
  52623         0,
  52624         0,
  52625         1,
  52626         soc_CPORT_LED_CHAIN_CONFIGr_fields,
  52627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52628         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52629         -1,
  52630         -1,
  52631     },
  52632 #endif /* chips */
  52633 
  52634 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  52635     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM56160_A0r */
  52636         soc_block_list[16],
  52637         soc_genreg,
  52638         1,
  52639         0,
  52640         0x2022300,
  52641         0,
  52642         0,
  52643         1,
  52644         soc_CXX_CXXPORT_LED_CHAIN_CONFIGr_fields,
  52645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52646         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52647         -1,
  52648         -1,
  52649     },
  52650 #endif /* chips */
  52651 
  52652 #if defined(BCM_56260_A0)
  52653     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM56260_A0r */
  52654         soc_block_list[16],
  52655         soc_genreg,
  52656         1,
  52657         0,
  52658         0x2022300,
  52659         0,
  52660         0,
  52661         1,
  52662         soc_PGW_GX_BYPASS_LED_CHAIN_CONFIGr_fields,
  52663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52664         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52665         -1,
  52666         -1,
  52667     },
  52668 #endif /* chips */
  52669 
  52670 #if defined(BCM_56260_B0)
  52671     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM56260_B0r */
  52672         soc_block_list[16],
  52673         soc_genreg,
  52674         1,
  52675         0,
  52676         0x2022300,
  52677         0,
  52678         0,
  52679         1,
  52680         soc_CXX_CXXPORT_LED_CHAIN_CONFIGr_fields,
  52681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52682         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52683         -1,
  52684         -1,
  52685     },
  52686 #endif /* chips */
  52687 
  52688 #if defined(BCM_56370_A0)
  52689     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM56370_A0r */
  52690         soc_block_list[16],
  52691         soc_genreg,
  52692         1,
  52693         0,
  52694         0x2022300,
  52695         0,
  52696         0,
  52697         1,
  52698         soc_CLPORT_LED_CHAIN_CONFIGr_fields,
  52699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52700         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52701         -1,
  52702         -1,
  52703         3,
  52704     },
  52705 #endif /* chips */
  52706 
  52707 #if defined(BCM_56560_A0)
  52708     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM56560_A0r */
  52709         soc_block_list[217],
  52710         soc_genreg,
  52711         1,
  52712         0,
  52713         0x2022300,
  52714         0,
  52715         0,
  52716         1,
  52717         soc_CXX_CXXPORT_LED_CHAIN_CONFIGr_fields,
  52718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52719         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52720         -1,
  52721         -1,
  52722     },
  52723 #endif /* chips */
  52724 
  52725 #if defined(BCM_56560_B0)
  52726     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM56560_B0r */
  52727         soc_block_list[16],
  52728         soc_genreg,
  52729         1,
  52730         0,
  52731         0x2022300,
  52732         0,
  52733         0,
  52734         1,
  52735         soc_CXX_CXXPORT_LED_CHAIN_CONFIGr_fields,
  52736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52737         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52738         -1,
  52739         -1,
  52740     },
  52741 #endif /* chips */
  52742 
  52743 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  52744     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM56670_A0r */
  52745         soc_block_list[16],
  52746         soc_genreg,
  52747         1,
  52748         0,
  52749         0x2022300,
  52750         0,
  52751         0,
  52752         1,
  52753         soc_CXX_CXXPORT_LED_CHAIN_CONFIGr_fields,
  52754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52755         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52756         -1,
  52757         -1,
  52758     },
  52759 #endif /* chips */
  52760 
  52761 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  52762     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  52763     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  52764     defined(BCM_56980_B0)
  52765     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM56960_A0r */
  52766         soc_block_list[16],
  52767         soc_genreg,
  52768         1,
  52769         0,
  52770         0x2022300,
  52771         0,
  52772         0,
  52773         1,
  52774         soc_CLPORT_LED_CHAIN_CONFIGr_fields,
  52775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52776         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  52777         -1,
  52778         -1,
  52779         3,
  52780     },
  52781 #endif /* chips */
  52782 
  52783 #if defined(BCM_88270_A0)
  52784     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM88270_A0r */
  52785         soc_block_list[56],
  52786         soc_genreg,
  52787         1,
  52788         0,
  52789         0x2022300,
  52790         0,
  52791         0,
  52792         1,
  52793         soc_XLPORT_LED_CHAIN_CONFIG_BCM88270_A0r_fields,
  52794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52795         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52796         -1,
  52797         -1,
  52798     },
  52799 #endif /* chips */
  52800 
  52801 #if defined(BCM_88375_B0)
  52802     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM88375_B0r */
  52803         soc_block_list[56],
  52804         soc_genreg,
  52805         1,
  52806         0,
  52807         0x2022300,
  52808         0,
  52809         0,
  52810         1,
  52811         soc_XLPORT_LED_CHAIN_CONFIG_BCM88375_B0r_fields,
  52812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52813         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52814         -1,
  52815         -1,
  52816     },
  52817 #endif /* chips */
  52818 
  52819 #if defined(BCM_88470_B0)
  52820     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM88470_B0r */
  52821         soc_block_list[56],
  52822         soc_genreg,
  52823         1,
  52824         0,
  52825         0x2022300,
  52826         0,
  52827         0,
  52828         1,
  52829         soc_XLPORT_LED_CHAIN_CONFIGr_fields,
  52830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52831         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52832         -1,
  52833         -1,
  52834     },
  52835 #endif /* chips */
  52836 
  52837 #if defined(BCM_88675_B0)
  52838     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM88675_B0r */
  52839         soc_block_list[56],
  52840         soc_genreg,
  52841         1,
  52842         0,
  52843         0x2022300,
  52844         0,
  52845         0,
  52846         1,
  52847         soc_XLPORT_LED_CHAIN_CONFIG_BCM88675_B0r_fields,
  52848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52849         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52850         -1,
  52851         -1,
  52852     },
  52853 #endif /* chips */
  52854 
  52855 #if defined(BCM_88680_A0)
  52856     { /* SOC_REG_INT_XLPORT_LED_CHAIN_CONFIG_BCM88680_A0r */
  52857         soc_block_list[56],
  52858         soc_genreg,
  52859         1,
  52860         0,
  52861         0x2022300,
  52862         0,
  52863         0,
  52864         1,
  52865         soc_XLPORT_LED_CHAIN_CONFIG_BCM88680_A0r_fields,
  52866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52867         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52868         -1,
  52869         -1,
  52870     },
  52871 #endif /* chips */
  52872 
  52873 #if defined(BCM_56840_B0)
  52874     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWNr */
  52875         soc_block_list[16],
  52876         soc_genreg,
  52877         1,
  52878         0,
  52879         0x80254,
  52880         SOC_REG_FLAG_RO,
  52881         0,
  52882         4,
  52883         soc_XLPORT_LINKSTATUS_DOWNr_fields,
  52884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52885         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52886         -1,
  52887         -1,
  52888     },
  52889 #endif /* chips */
  52890 
  52891 #if defined(BCM_2801PM_A0)
  52892     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM2801PM_A0r */
  52893         soc_block_list[56],
  52894         soc_genreg,
  52895         1,
  52896         0,
  52897         0x2022700,
  52898         SOC_REG_FLAG_RO |
  52899                           SOC_REG_FLAG_SIGNAL,
  52900         0,
  52901         4,
  52902         soc_CLPORT_LINKSTATUS_DOWNr_fields,
  52903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52904         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52905         -1,
  52906         -1,
  52907     },
  52908 #endif /* chips */
  52909 
  52910 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  52911     defined(BCM_56670_B0)
  52912     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM53400_A0r */
  52913         soc_block_list[16],
  52914         soc_genreg,
  52915         1,
  52916         0,
  52917         0x2022700,
  52918         SOC_REG_FLAG_RO,
  52919         0,
  52920         4,
  52921         soc_XLPORT_LINKSTATUS_DOWN_BCM53400_A0r_fields,
  52922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52923         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52924         -1,
  52925         -1,
  52926     },
  52927 #endif /* chips */
  52928 
  52929 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  52930     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM53570_A0r */
  52931         soc_block_list[16],
  52932         soc_genreg,
  52933         1,
  52934         0,
  52935         0x2022700,
  52936         SOC_REG_FLAG_RO,
  52937         0,
  52938         4,
  52939         soc_XLPORT_LINKSTATUS_DOWN_BCM53400_A0r_fields,
  52940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52941         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52942         -1,
  52943         -1,
  52944     },
  52945 #endif /* chips */
  52946 
  52947 #if defined(BCM_56150_A0)
  52948     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM56150_A0r */
  52949         soc_block_list[16],
  52950         soc_genreg,
  52951         1,
  52952         0,
  52953         0x2022900,
  52954         SOC_REG_FLAG_RO,
  52955         0,
  52956         4,
  52957         soc_XLPORT_LINKSTATUS_DOWN_BCM56850_A0r_fields,
  52958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52959         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52960         -1,
  52961         -1,
  52962     },
  52963 #endif /* chips */
  52964 
  52965 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  52966     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM56160_A0r */
  52967         soc_block_list[16],
  52968         soc_genreg,
  52969         1,
  52970         0,
  52971         0x2022700,
  52972         SOC_REG_FLAG_RO,
  52973         0,
  52974         4,
  52975         soc_XLPORT_LINKSTATUS_DOWN_BCM53400_A0r_fields,
  52976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52977         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52978         -1,
  52979         -1,
  52980     },
  52981 #endif /* chips */
  52982 
  52983 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  52984     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM56260_A0r */
  52985         soc_block_list[16],
  52986         soc_genreg,
  52987         1,
  52988         0,
  52989         0x2022700,
  52990         SOC_REG_FLAG_RO,
  52991         0,
  52992         4,
  52993         soc_XLPORT_LINKSTATUS_DOWN_BCM53400_A0r_fields,
  52994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52995         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  52996         -1,
  52997         -1,
  52998     },
  52999 #endif /* chips */
  53000 
  53001 #if defined(BCM_56370_A0)
  53002     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM56370_A0r */
  53003         soc_block_list[16],
  53004         soc_genreg,
  53005         1,
  53006         0,
  53007         0x2022700,
  53008         SOC_REG_FLAG_RO,
  53009         0,
  53010         4,
  53011         soc_XLPORT_LINKSTATUS_DOWN_BCM53400_A0r_fields,
  53012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53013         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53014         -1,
  53015         -1,
  53016         3,
  53017     },
  53018 #endif /* chips */
  53019 
  53020 #if defined(BCM_56560_A0)
  53021     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM56560_A0r */
  53022         soc_block_list[217],
  53023         soc_genreg,
  53024         1,
  53025         0,
  53026         0x2022700,
  53027         SOC_REG_FLAG_RO,
  53028         0,
  53029         4,
  53030         soc_XLPORT_LINKSTATUS_DOWN_BCM53400_A0r_fields,
  53031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53032         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53033         -1,
  53034         -1,
  53035     },
  53036 #endif /* chips */
  53037 
  53038 #if defined(BCM_56560_B0)
  53039     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM56560_B0r */
  53040         soc_block_list[16],
  53041         soc_genreg,
  53042         1,
  53043         0,
  53044         0x2022700,
  53045         SOC_REG_FLAG_RO,
  53046         0,
  53047         4,
  53048         soc_XLPORT_LINKSTATUS_DOWN_BCM53400_A0r_fields,
  53049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53050         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53051         -1,
  53052         -1,
  53053     },
  53054 #endif /* chips */
  53055 
  53056 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  53057     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM56850_A0r */
  53058         soc_block_list[16],
  53059         soc_genreg,
  53060         1,
  53061         0,
  53062         0x2021500,
  53063         SOC_REG_FLAG_RO,
  53064         0,
  53065         4,
  53066         soc_XLPORT_LINKSTATUS_DOWN_BCM56850_A0r_fields,
  53067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53068         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53069         -1,
  53070         -1,
  53071     },
  53072 #endif /* chips */
  53073 
  53074 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  53075     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  53076     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  53077     defined(BCM_56980_B0)
  53078     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM56960_A0r */
  53079         soc_block_list[16],
  53080         soc_genreg,
  53081         1,
  53082         0,
  53083         0x2022700,
  53084         SOC_REG_FLAG_RO,
  53085         0,
  53086         4,
  53087         soc_XLPORT_LINKSTATUS_DOWN_BCM53400_A0r_fields,
  53088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53089         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53090         -1,
  53091         -1,
  53092         3,
  53093     },
  53094 #endif /* chips */
  53095 
  53096 #if defined(BCM_88270_A0)
  53097     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM88270_A0r */
  53098         soc_block_list[56],
  53099         soc_genreg,
  53100         1,
  53101         0,
  53102         0x2022700,
  53103         SOC_REG_FLAG_RO |
  53104                           SOC_REG_FLAG_SIGNAL,
  53105         0,
  53106         4,
  53107         soc_XLPORT_LINKSTATUS_DOWN_BCM88270_A0r_fields,
  53108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53109         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53110         -1,
  53111         -1,
  53112     },
  53113 #endif /* chips */
  53114 
  53115 #if defined(BCM_88375_A0)
  53116     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM88375_A0r */
  53117         soc_block_list[56],
  53118         soc_genreg,
  53119         1,
  53120         0,
  53121         0x2022700,
  53122         SOC_REG_FLAG_RO |
  53123                           SOC_REG_FLAG_SIGNAL,
  53124         0,
  53125         4,
  53126         soc_XLPORT_LINKSTATUS_DOWN_BCM88375_A0r_fields,
  53127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53128         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53129         -1,
  53130         -1,
  53131     },
  53132 #endif /* chips */
  53133 
  53134 #if defined(BCM_88375_B0)
  53135     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM88375_B0r */
  53136         soc_block_list[56],
  53137         soc_genreg,
  53138         1,
  53139         0,
  53140         0x2022700,
  53141         SOC_REG_FLAG_RO |
  53142                           SOC_REG_FLAG_SIGNAL,
  53143         0,
  53144         4,
  53145         soc_XLPORT_LINKSTATUS_DOWN_BCM88375_B0r_fields,
  53146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53147         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53148         -1,
  53149         -1,
  53150     },
  53151 #endif /* chips */
  53152 
  53153 #if defined(BCM_88470_A0)
  53154     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM88470_A0r */
  53155         soc_block_list[56],
  53156         soc_genreg,
  53157         1,
  53158         0,
  53159         0x2022700,
  53160         SOC_REG_FLAG_RO |
  53161                           SOC_REG_FLAG_SIGNAL,
  53162         0,
  53163         4,
  53164         soc_XLPORT_LINKSTATUS_DOWN_BCM88470_A0r_fields,
  53165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53166         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53167         -1,
  53168         -1,
  53169     },
  53170 #endif /* chips */
  53171 
  53172 #if defined(BCM_88470_B0)
  53173     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM88470_B0r */
  53174         soc_block_list[56],
  53175         soc_genreg,
  53176         1,
  53177         0,
  53178         0x2022700,
  53179         SOC_REG_FLAG_RO |
  53180                           SOC_REG_FLAG_SIGNAL,
  53181         0,
  53182         4,
  53183         soc_XLPORT_LINKSTATUS_DOWN_BCM88470_B0r_fields,
  53184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53185         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53186         -1,
  53187         -1,
  53188     },
  53189 #endif /* chips */
  53190 
  53191 #if defined(BCM_88675_A0)
  53192     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM88675_A0r */
  53193         soc_block_list[56],
  53194         soc_genreg,
  53195         1,
  53196         0,
  53197         0x2022700,
  53198         SOC_REG_FLAG_RO |
  53199                           SOC_REG_FLAG_SIGNAL,
  53200         0,
  53201         4,
  53202         soc_XLPORT_LINKSTATUS_DOWN_BCM88675_A0r_fields,
  53203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53204         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53205         -1,
  53206         -1,
  53207     },
  53208 #endif /* chips */
  53209 
  53210 #if defined(BCM_88675_B0)
  53211     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM88675_B0r */
  53212         soc_block_list[56],
  53213         soc_genreg,
  53214         1,
  53215         0,
  53216         0x2022700,
  53217         SOC_REG_FLAG_RO |
  53218                           SOC_REG_FLAG_SIGNAL,
  53219         0,
  53220         4,
  53221         soc_XLPORT_LINKSTATUS_DOWN_BCM88675_B0r_fields,
  53222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53223         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53224         -1,
  53225         -1,
  53226     },
  53227 #endif /* chips */
  53228 
  53229 #if defined(BCM_88680_A0)
  53230     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_BCM88680_A0r */
  53231         soc_block_list[56],
  53232         soc_genreg,
  53233         1,
  53234         0,
  53235         0x2022700,
  53236         SOC_REG_FLAG_RO |
  53237                           SOC_REG_FLAG_SIGNAL,
  53238         0,
  53239         4,
  53240         soc_XLPORT_LINKSTATUS_DOWN_BCM88680_A0r_fields,
  53241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53242         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53243         -1,
  53244         -1,
  53245     },
  53246 #endif /* chips */
  53247 
  53248 #if defined(BCM_56840_B0)
  53249     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEARr */
  53250         soc_block_list[16],
  53251         soc_genreg,
  53252         1,
  53253         0,
  53254         0x80255,
  53255         0,
  53256         0,
  53257         4,
  53258         soc_XLPORT_LINKSTATUS_DOWN_CLEARr_fields,
  53259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53260         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53261         -1,
  53262         -1,
  53263     },
  53264 #endif /* chips */
  53265 
  53266 #if defined(BCM_2801PM_A0)
  53267     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM2801PM_A0r */
  53268         soc_block_list[56],
  53269         soc_genreg,
  53270         1,
  53271         0,
  53272         0x2022800,
  53273         0,
  53274         0,
  53275         4,
  53276         soc_CLPORT_LINKSTATUS_DOWN_CLEARr_fields,
  53277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53278         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53279         -1,
  53280         -1,
  53281     },
  53282 #endif /* chips */
  53283 
  53284 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  53285     defined(BCM_56670_B0)
  53286     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM53400_A0r */
  53287         soc_block_list[16],
  53288         soc_genreg,
  53289         1,
  53290         0,
  53291         0x2022800,
  53292         0,
  53293         0,
  53294         4,
  53295         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM53400_A0r_fields,
  53296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53297         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53298         -1,
  53299         -1,
  53300     },
  53301 #endif /* chips */
  53302 
  53303 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  53304     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM53570_A0r */
  53305         soc_block_list[16],
  53306         soc_genreg,
  53307         1,
  53308         0,
  53309         0x2022800,
  53310         0,
  53311         0,
  53312         4,
  53313         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM53400_A0r_fields,
  53314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53315         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53316         -1,
  53317         -1,
  53318     },
  53319 #endif /* chips */
  53320 
  53321 #if defined(BCM_56150_A0)
  53322     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56150_A0r */
  53323         soc_block_list[16],
  53324         soc_genreg,
  53325         1,
  53326         0,
  53327         0x2022a00,
  53328         0,
  53329         0,
  53330         4,
  53331         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56850_A0r_fields,
  53332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53333         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53334         -1,
  53335         -1,
  53336     },
  53337 #endif /* chips */
  53338 
  53339 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  53340     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56160_A0r */
  53341         soc_block_list[16],
  53342         soc_genreg,
  53343         1,
  53344         0,
  53345         0x2022800,
  53346         0,
  53347         0,
  53348         4,
  53349         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM53400_A0r_fields,
  53350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53351         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53352         -1,
  53353         -1,
  53354     },
  53355 #endif /* chips */
  53356 
  53357 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  53358     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56260_A0r */
  53359         soc_block_list[16],
  53360         soc_genreg,
  53361         1,
  53362         0,
  53363         0x2022800,
  53364         0,
  53365         0,
  53366         4,
  53367         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM53400_A0r_fields,
  53368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53369         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53370         -1,
  53371         -1,
  53372     },
  53373 #endif /* chips */
  53374 
  53375 #if defined(BCM_56370_A0)
  53376     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56370_A0r */
  53377         soc_block_list[16],
  53378         soc_genreg,
  53379         1,
  53380         0,
  53381         0x2022800,
  53382         0,
  53383         0,
  53384         4,
  53385         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM53400_A0r_fields,
  53386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53387         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53388         -1,
  53389         -1,
  53390         3,
  53391     },
  53392 #endif /* chips */
  53393 
  53394 #if defined(BCM_56560_A0)
  53395     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56560_A0r */
  53396         soc_block_list[217],
  53397         soc_genreg,
  53398         1,
  53399         0,
  53400         0x2022800,
  53401         0,
  53402         0,
  53403         4,
  53404         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM53400_A0r_fields,
  53405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53406         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53407         -1,
  53408         -1,
  53409     },
  53410 #endif /* chips */
  53411 
  53412 #if defined(BCM_56560_B0)
  53413     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56560_B0r */
  53414         soc_block_list[16],
  53415         soc_genreg,
  53416         1,
  53417         0,
  53418         0x2022800,
  53419         0,
  53420         0,
  53421         4,
  53422         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM53400_A0r_fields,
  53423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53424         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53425         -1,
  53426         -1,
  53427     },
  53428 #endif /* chips */
  53429 
  53430 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  53431     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56850_A0r */
  53432         soc_block_list[16],
  53433         soc_genreg,
  53434         1,
  53435         0,
  53436         0x2021600,
  53437         0,
  53438         0,
  53439         4,
  53440         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56850_A0r_fields,
  53441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53442         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53443         -1,
  53444         -1,
  53445     },
  53446 #endif /* chips */
  53447 
  53448 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  53449     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  53450     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  53451     defined(BCM_56980_B0)
  53452     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56960_A0r */
  53453         soc_block_list[16],
  53454         soc_genreg,
  53455         1,
  53456         0,
  53457         0x2022800,
  53458         0,
  53459         0,
  53460         4,
  53461         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM53400_A0r_fields,
  53462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53463         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53464         -1,
  53465         -1,
  53466         3,
  53467     },
  53468 #endif /* chips */
  53469 
  53470 #if defined(BCM_88270_A0)
  53471     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88270_A0r */
  53472         soc_block_list[56],
  53473         soc_genreg,
  53474         1,
  53475         0,
  53476         0x2022800,
  53477         0,
  53478         0,
  53479         4,
  53480         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88270_A0r_fields,
  53481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53482         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53483         -1,
  53484         -1,
  53485     },
  53486 #endif /* chips */
  53487 
  53488 #if defined(BCM_88375_A0)
  53489     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88375_A0r */
  53490         soc_block_list[56],
  53491         soc_genreg,
  53492         1,
  53493         0,
  53494         0x2022800,
  53495         0,
  53496         0,
  53497         4,
  53498         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88375_A0r_fields,
  53499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53500         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53501         -1,
  53502         -1,
  53503     },
  53504 #endif /* chips */
  53505 
  53506 #if defined(BCM_88375_B0)
  53507     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88375_B0r */
  53508         soc_block_list[56],
  53509         soc_genreg,
  53510         1,
  53511         0,
  53512         0x2022800,
  53513         0,
  53514         0,
  53515         4,
  53516         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88375_B0r_fields,
  53517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53518         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53519         -1,
  53520         -1,
  53521     },
  53522 #endif /* chips */
  53523 
  53524 #if defined(BCM_88470_A0)
  53525     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88470_A0r */
  53526         soc_block_list[56],
  53527         soc_genreg,
  53528         1,
  53529         0,
  53530         0x2022800,
  53531         0,
  53532         0,
  53533         4,
  53534         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88470_A0r_fields,
  53535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53536         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53537         -1,
  53538         -1,
  53539     },
  53540 #endif /* chips */
  53541 
  53542 #if defined(BCM_88470_B0)
  53543     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88470_B0r */
  53544         soc_block_list[56],
  53545         soc_genreg,
  53546         1,
  53547         0,
  53548         0x2022800,
  53549         0,
  53550         0,
  53551         4,
  53552         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88470_B0r_fields,
  53553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53554         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53555         -1,
  53556         -1,
  53557     },
  53558 #endif /* chips */
  53559 
  53560 #if defined(BCM_88675_A0)
  53561     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88675_A0r */
  53562         soc_block_list[56],
  53563         soc_genreg,
  53564         1,
  53565         0,
  53566         0x2022800,
  53567         0,
  53568         0,
  53569         4,
  53570         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88675_A0r_fields,
  53571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53572         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53573         -1,
  53574         -1,
  53575     },
  53576 #endif /* chips */
  53577 
  53578 #if defined(BCM_88675_B0)
  53579     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88675_B0r */
  53580         soc_block_list[56],
  53581         soc_genreg,
  53582         1,
  53583         0,
  53584         0x2022800,
  53585         0,
  53586         0,
  53587         4,
  53588         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88675_B0r_fields,
  53589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53590         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53591         -1,
  53592         -1,
  53593     },
  53594 #endif /* chips */
  53595 
  53596 #if defined(BCM_88680_A0)
  53597     { /* SOC_REG_INT_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88680_A0r */
  53598         soc_block_list[56],
  53599         soc_genreg,
  53600         1,
  53601         0,
  53602         0x2022800,
  53603         0,
  53604         0,
  53605         4,
  53606         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88680_A0r_fields,
  53607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53608         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  53609         -1,
  53610         -1,
  53611     },
  53612 #endif /* chips */
  53613 
  53614 #if defined(BCM_2801PM_A0)
  53615     { /* SOC_REG_INT_XLPORT_MAC_CONTROLr */
  53616         soc_block_list[56],
  53617         soc_genreg,
  53618         1,
  53619         0,
  53620         0x2021000,
  53621         0,
  53622         0,
  53623         3,
  53624         soc_XLPORT_MAC_CONTROLr_fields,
  53625         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  53626         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  53627         -1,
  53628         -1,
  53629     },
  53630 #endif /* chips */
  53631 
  53632 #if defined(BCM_53400_A0)
  53633     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM53400_A0r */
  53634         soc_block_list[16],
  53635         soc_genreg,
  53636         1,
  53637         0,
  53638         0x2021000,
  53639         0,
  53640         0,
  53641         3,
  53642         soc_XLPORT_MAC_CONTROL_BCM53400_A0r_fields,
  53643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53644         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53645         -1,
  53646         -1,
  53647     },
  53648 #endif /* chips */
  53649 
  53650 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  53651     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM53570_A0r */
  53652         soc_block_list[16],
  53653         soc_genreg,
  53654         1,
  53655         0,
  53656         0x2021000,
  53657         0,
  53658         0,
  53659         7,
  53660         soc_XLPORT_MAC_CONTROL_BCM53570_A0r_fields,
  53661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53662         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53663         -1,
  53664         -1,
  53665     },
  53666 #endif /* chips */
  53667 
  53668 #if defined(BCM_56150_A0)
  53669     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM56150_A0r */
  53670         soc_block_list[16],
  53671         soc_genreg,
  53672         1,
  53673         0,
  53674         0x2021000,
  53675         0,
  53676         0,
  53677         2,
  53678         soc_XLPORT_MAC_CONTROL_BCM56850_A0r_fields,
  53679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53680         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53681         -1,
  53682         -1,
  53683     },
  53684 #endif /* chips */
  53685 
  53686 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  53687     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM56160_A0r */
  53688         soc_block_list[16],
  53689         soc_genreg,
  53690         1,
  53691         0,
  53692         0x2021000,
  53693         0,
  53694         0,
  53695         3,
  53696         soc_XLPORT_MAC_CONTROL_BCM53400_A0r_fields,
  53697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53698         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53699         -1,
  53700         -1,
  53701     },
  53702 #endif /* chips */
  53703 
  53704 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  53705     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM56260_A0r */
  53706         soc_block_list[16],
  53707         soc_genreg,
  53708         1,
  53709         0,
  53710         0x2021000,
  53711         0,
  53712         0,
  53713         3,
  53714         soc_XLPORT_MAC_CONTROL_BCM53400_A0r_fields,
  53715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53716         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53717         -1,
  53718         -1,
  53719     },
  53720 #endif /* chips */
  53721 
  53722 #if defined(BCM_56370_A0)
  53723     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM56370_A0r */
  53724         soc_block_list[16],
  53725         soc_genreg,
  53726         1,
  53727         0,
  53728         0x2021000,
  53729         0,
  53730         0,
  53731         6,
  53732         soc_XLPORT_MAC_CONTROL_BCM56970_A0r_fields,
  53733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53734         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53735         -1,
  53736         -1,
  53737         3,
  53738     },
  53739 #endif /* chips */
  53740 
  53741 #if defined(BCM_56560_A0)
  53742     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM56560_A0r */
  53743         soc_block_list[217],
  53744         soc_genreg,
  53745         1,
  53746         0,
  53747         0x2021000,
  53748         0,
  53749         0,
  53750         3,
  53751         soc_XLPORT_MAC_CONTROL_BCM53400_A0r_fields,
  53752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53754         -1,
  53755         -1,
  53756     },
  53757 #endif /* chips */
  53758 
  53759 #if defined(BCM_56560_B0)
  53760     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM56560_B0r */
  53761         soc_block_list[16],
  53762         soc_genreg,
  53763         1,
  53764         0,
  53765         0x2021000,
  53766         0,
  53767         0,
  53768         3,
  53769         soc_XLPORT_MAC_CONTROL_BCM53400_A0r_fields,
  53770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53772         -1,
  53773         -1,
  53774     },
  53775 #endif /* chips */
  53776 
  53777 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  53778     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM56670_A0r */
  53779         soc_block_list[16],
  53780         soc_genreg,
  53781         1,
  53782         0,
  53783         0x2021000,
  53784         0,
  53785         0,
  53786         7,
  53787         soc_XLPORT_MAC_CONTROL_BCM53570_A0r_fields,
  53788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53790         -1,
  53791         -1,
  53792     },
  53793 #endif /* chips */
  53794 
  53795 #if defined(BCM_56850_A0)
  53796     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM56850_A0r */
  53797         soc_block_list[16],
  53798         soc_genreg,
  53799         1,
  53800         0,
  53801         0x2020c00,
  53802         0,
  53803         0,
  53804         2,
  53805         soc_XLPORT_MAC_CONTROL_BCM56850_A0r_fields,
  53806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53807         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53808         -1,
  53809         -1,
  53810     },
  53811 #endif /* chips */
  53812 
  53813 #if defined(BCM_56860_A0)
  53814     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM56860_A0r */
  53815         soc_block_list[16],
  53816         soc_genreg,
  53817         1,
  53818         0,
  53819         0x2020d00,
  53820         0,
  53821         0,
  53822         2,
  53823         soc_XLPORT_MAC_CONTROL_BCM56850_A0r_fields,
  53824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53825         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53826         -1,
  53827         -1,
  53828     },
  53829 #endif /* chips */
  53830 
  53831 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  53832     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM56960_A0r */
  53833         soc_block_list[16],
  53834         soc_genreg,
  53835         1,
  53836         0,
  53837         0x2021000,
  53838         0,
  53839         0,
  53840         3,
  53841         soc_XLPORT_MAC_CONTROL_BCM53400_A0r_fields,
  53842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53843         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53844         -1,
  53845         -1,
  53846         3,
  53847     },
  53848 #endif /* chips */
  53849 
  53850 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  53851     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  53852     defined(BCM_56980_B0)
  53853     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM56970_A0r */
  53854         soc_block_list[16],
  53855         soc_genreg,
  53856         1,
  53857         0,
  53858         0x2021000,
  53859         0,
  53860         0,
  53861         6,
  53862         soc_XLPORT_MAC_CONTROL_BCM56970_A0r_fields,
  53863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53864         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  53865         -1,
  53866         -1,
  53867         3,
  53868     },
  53869 #endif /* chips */
  53870 
  53871 #if defined(BCM_88270_A0)
  53872     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM88270_A0r */
  53873         soc_block_list[56],
  53874         soc_genreg,
  53875         1,
  53876         0,
  53877         0x2021000,
  53878         0,
  53879         0,
  53880         3,
  53881         soc_XLPORT_MAC_CONTROL_BCM88270_A0r_fields,
  53882         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  53883         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  53884         -1,
  53885         -1,
  53886     },
  53887 #endif /* chips */
  53888 
  53889 #if defined(BCM_88375_A0)
  53890     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM88375_A0r */
  53891         soc_block_list[56],
  53892         soc_genreg,
  53893         1,
  53894         0,
  53895         0x2021000,
  53896         SOC_REG_FLAG_IGNORE_DEFAULT,
  53897         0,
  53898         3,
  53899         soc_XLPORT_MAC_CONTROL_BCM88375_A0r_fields,
  53900         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  53901         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  53902         -1,
  53903         -1,
  53904     },
  53905 #endif /* chips */
  53906 
  53907 #if defined(BCM_88375_B0)
  53908     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM88375_B0r */
  53909         soc_block_list[56],
  53910         soc_genreg,
  53911         1,
  53912         0,
  53913         0x2021000,
  53914         SOC_REG_FLAG_IGNORE_DEFAULT,
  53915         0,
  53916         3,
  53917         soc_XLPORT_MAC_CONTROL_BCM88375_B0r_fields,
  53918         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  53919         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  53920         -1,
  53921         -1,
  53922     },
  53923 #endif /* chips */
  53924 
  53925 #if defined(BCM_88470_A0)
  53926     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM88470_A0r */
  53927         soc_block_list[56],
  53928         soc_genreg,
  53929         1,
  53930         0,
  53931         0x2021000,
  53932         0,
  53933         0,
  53934         3,
  53935         soc_XLPORT_MAC_CONTROL_BCM88470_A0r_fields,
  53936         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  53937         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  53938         -1,
  53939         -1,
  53940     },
  53941 #endif /* chips */
  53942 
  53943 #if defined(BCM_88470_B0)
  53944     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM88470_B0r */
  53945         soc_block_list[56],
  53946         soc_genreg,
  53947         1,
  53948         0,
  53949         0x2021000,
  53950         0,
  53951         0,
  53952         3,
  53953         soc_XLPORT_MAC_CONTROL_BCM88470_B0r_fields,
  53954         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  53955         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  53956         -1,
  53957         -1,
  53958     },
  53959 #endif /* chips */
  53960 
  53961 #if defined(BCM_88675_A0)
  53962     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM88675_A0r */
  53963         soc_block_list[56],
  53964         soc_genreg,
  53965         1,
  53966         0,
  53967         0x2021000,
  53968         SOC_REG_FLAG_IGNORE_DEFAULT,
  53969         0,
  53970         3,
  53971         soc_XLPORT_MAC_CONTROL_BCM88675_A0r_fields,
  53972         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  53973         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  53974         -1,
  53975         -1,
  53976     },
  53977 #endif /* chips */
  53978 
  53979 #if defined(BCM_88675_B0)
  53980     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM88675_B0r */
  53981         soc_block_list[56],
  53982         soc_genreg,
  53983         1,
  53984         0,
  53985         0x2021000,
  53986         SOC_REG_FLAG_IGNORE_DEFAULT,
  53987         0,
  53988         3,
  53989         soc_XLPORT_MAC_CONTROL_BCM88675_B0r_fields,
  53990         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  53991         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  53992         -1,
  53993         -1,
  53994     },
  53995 #endif /* chips */
  53996 
  53997 #if defined(BCM_88680_A0)
  53998     { /* SOC_REG_INT_XLPORT_MAC_CONTROL_BCM88680_A0r */
  53999         soc_block_list[56],
  54000         soc_genreg,
  54001         1,
  54002         0,
  54003         0x2021000,
  54004         0,
  54005         0,
  54006         3,
  54007         soc_XLPORT_MAC_CONTROL_BCM88680_A0r_fields,
  54008         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  54009         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  54010         -1,
  54011         -1,
  54012     },
  54013 #endif /* chips */
  54014 
  54015 #if defined(BCM_2801PM_A0)
  54016     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASKr */
  54017         soc_block_list[56],
  54018         soc_portreg,
  54019         1,
  54020         0,
  54021         0x20800,
  54022         0,
  54023         0,
  54024         1,
  54025         soc_CLPORT_MAC_RSV_MASKr_fields,
  54026         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54028         -1,
  54029         -1,
  54030     },
  54031 #endif /* chips */
  54032 
  54033 #if defined(BCM_53400_A0)
  54034     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM53400_A0r */
  54035         soc_block_list[16],
  54036         soc_portreg,
  54037         1,
  54038         0,
  54039         0x20800,
  54040         0,
  54041         0,
  54042         1,
  54043         soc_CLPORT_MAC_RSV_MASKr_fields,
  54044         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54045         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54046         -1,
  54047         -1,
  54048     },
  54049 #endif /* chips */
  54050 
  54051 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  54052     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM53570_A0r */
  54053         soc_block_list[16],
  54054         soc_portreg,
  54055         1,
  54056         0,
  54057         0x20800,
  54058         0,
  54059         0,
  54060         1,
  54061         soc_XLPORT_MAC_RSV_MASK_BCM53570_A0r_fields,
  54062         SOC_RESET_VAL_DEC(0x6c000078, 0x00000000)
  54063         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54064         -1,
  54065         -1,
  54066     },
  54067 #endif /* chips */
  54068 
  54069 #if defined(BCM_56150_A0)
  54070     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM56150_A0r */
  54071         soc_block_list[16],
  54072         soc_portreg,
  54073         1,
  54074         0,
  54075         0x20800,
  54076         0,
  54077         0,
  54078         1,
  54079         soc_PGW_MAC_RSV_MASKr_fields,
  54080         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54081         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54082         -1,
  54083         -1,
  54084     },
  54085 #endif /* chips */
  54086 
  54087 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  54088     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM56160_A0r */
  54089         soc_block_list[16],
  54090         soc_portreg,
  54091         1,
  54092         0,
  54093         0x20800,
  54094         0,
  54095         0,
  54096         1,
  54097         soc_CLPORT_MAC_RSV_MASKr_fields,
  54098         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54099         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54100         -1,
  54101         -1,
  54102     },
  54103 #endif /* chips */
  54104 
  54105 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  54106     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM56260_A0r */
  54107         soc_block_list[16],
  54108         soc_portreg,
  54109         1,
  54110         0,
  54111         0x20800,
  54112         0,
  54113         0,
  54114         1,
  54115         soc_CLPORT_MAC_RSV_MASKr_fields,
  54116         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54117         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54118         -1,
  54119         -1,
  54120     },
  54121 #endif /* chips */
  54122 
  54123 #if defined(BCM_56370_A0)
  54124     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM56370_A0r */
  54125         soc_block_list[16],
  54126         soc_portreg,
  54127         1,
  54128         0,
  54129         0x20800,
  54130         0,
  54131         0,
  54132         1,
  54133         soc_CLPORT_MAC_RSV_MASKr_fields,
  54134         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54135         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54136         -1,
  54137         -1,
  54138         3,
  54139     },
  54140 #endif /* chips */
  54141 
  54142 #if defined(BCM_56560_A0)
  54143     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM56560_A0r */
  54144         soc_block_list[217],
  54145         soc_portreg,
  54146         1,
  54147         0,
  54148         0x20800,
  54149         0,
  54150         0,
  54151         1,
  54152         soc_CLPORT_MAC_RSV_MASKr_fields,
  54153         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54154         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54155         -1,
  54156         -1,
  54157     },
  54158 #endif /* chips */
  54159 
  54160 #if defined(BCM_56560_B0)
  54161     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM56560_B0r */
  54162         soc_block_list[16],
  54163         soc_portreg,
  54164         1,
  54165         0,
  54166         0x20800,
  54167         0,
  54168         0,
  54169         1,
  54170         soc_CLPORT_MAC_RSV_MASKr_fields,
  54171         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54172         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54173         -1,
  54174         -1,
  54175     },
  54176 #endif /* chips */
  54177 
  54178 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  54179     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM56670_A0r */
  54180         soc_block_list[16],
  54181         soc_portreg,
  54182         1,
  54183         0,
  54184         0x20800,
  54185         0,
  54186         0,
  54187         1,
  54188         soc_XLPORT_MAC_RSV_MASK_BCM53570_A0r_fields,
  54189         SOC_RESET_VAL_DEC(0x6c000078, 0x00000000)
  54190         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54191         -1,
  54192         -1,
  54193     },
  54194 #endif /* chips */
  54195 
  54196 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  54197     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  54198     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  54199     defined(BCM_56980_B0)
  54200     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM56960_A0r */
  54201         soc_block_list[16],
  54202         soc_portreg,
  54203         1,
  54204         0,
  54205         0x20800,
  54206         0,
  54207         0,
  54208         1,
  54209         soc_CLPORT_MAC_RSV_MASKr_fields,
  54210         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54211         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54212         -1,
  54213         -1,
  54214         3,
  54215     },
  54216 #endif /* chips */
  54217 
  54218 #if defined(BCM_88270_A0)
  54219     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM88270_A0r */
  54220         soc_block_list[56],
  54221         soc_portreg,
  54222         1,
  54223         0,
  54224         0x20800,
  54225         0,
  54226         0,
  54227         1,
  54228         soc_XLPORT_MAC_RSV_MASK_BCM88270_A0r_fields,
  54229         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54230         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54231         -1,
  54232         -1,
  54233     },
  54234 #endif /* chips */
  54235 
  54236 #if defined(BCM_88375_A0)
  54237     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM88375_A0r */
  54238         soc_block_list[56],
  54239         soc_portreg,
  54240         1,
  54241         0,
  54242         0x20800,
  54243         0,
  54244         0,
  54245         1,
  54246         soc_XLPORT_MAC_RSV_MASK_BCM88375_A0r_fields,
  54247         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54248         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54249         -1,
  54250         -1,
  54251     },
  54252 #endif /* chips */
  54253 
  54254 #if defined(BCM_88375_B0)
  54255     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM88375_B0r */
  54256         soc_block_list[56],
  54257         soc_portreg,
  54258         1,
  54259         0,
  54260         0x20800,
  54261         0,
  54262         0,
  54263         1,
  54264         soc_XLPORT_MAC_RSV_MASK_BCM88375_B0r_fields,
  54265         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54266         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54267         -1,
  54268         -1,
  54269     },
  54270 #endif /* chips */
  54271 
  54272 #if defined(BCM_88470_A0)
  54273     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM88470_A0r */
  54274         soc_block_list[56],
  54275         soc_portreg,
  54276         1,
  54277         0,
  54278         0x20800,
  54279         0,
  54280         0,
  54281         1,
  54282         soc_XLPORT_MAC_RSV_MASK_BCM88470_A0r_fields,
  54283         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54284         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54285         -1,
  54286         -1,
  54287     },
  54288 #endif /* chips */
  54289 
  54290 #if defined(BCM_88470_B0)
  54291     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM88470_B0r */
  54292         soc_block_list[56],
  54293         soc_portreg,
  54294         1,
  54295         0,
  54296         0x20800,
  54297         0,
  54298         0,
  54299         1,
  54300         soc_XLPORT_MAC_RSV_MASK_BCM88470_B0r_fields,
  54301         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54302         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54303         -1,
  54304         -1,
  54305     },
  54306 #endif /* chips */
  54307 
  54308 #if defined(BCM_88675_A0)
  54309     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM88675_A0r */
  54310         soc_block_list[56],
  54311         soc_portreg,
  54312         1,
  54313         0,
  54314         0x20800,
  54315         0,
  54316         0,
  54317         1,
  54318         soc_XLPORT_MAC_RSV_MASKr_fields,
  54319         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54320         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54321         -1,
  54322         -1,
  54323     },
  54324 #endif /* chips */
  54325 
  54326 #if defined(BCM_88675_B0)
  54327     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM88675_B0r */
  54328         soc_block_list[56],
  54329         soc_portreg,
  54330         1,
  54331         0,
  54332         0x20800,
  54333         0,
  54334         0,
  54335         1,
  54336         soc_XLPORT_MAC_RSV_MASK_BCM88675_B0r_fields,
  54337         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54338         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54339         -1,
  54340         -1,
  54341     },
  54342 #endif /* chips */
  54343 
  54344 #if defined(BCM_88680_A0)
  54345     { /* SOC_REG_INT_XLPORT_MAC_RSV_MASK_BCM88680_A0r */
  54346         soc_block_list[56],
  54347         soc_portreg,
  54348         1,
  54349         0,
  54350         0x20800,
  54351         0,
  54352         0,
  54353         1,
  54354         soc_XLPORT_MAC_RSV_MASK_BCM88680_A0r_fields,
  54355         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  54356         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54357         -1,
  54358         -1,
  54359     },
  54360 #endif /* chips */
  54361 
  54362 #if defined(BCM_56840_A0)
  54363     { /* SOC_REG_INT_XLPORT_MEMORY_CONTROL0r */
  54364         soc_block_list[16],
  54365         soc_genreg,
  54366         1,
  54367         0,
  54368         0x8024f,
  54369         0,
  54370         0,
  54371         2,
  54372         soc_XLPORT_MEMORY_CONTROL0r_fields,
  54373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54374         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54375         -1,
  54376         -1,
  54377     },
  54378 #endif /* chips */
  54379 
  54380 #if defined(BCM_56840_A0)
  54381     { /* SOC_REG_INT_XLPORT_MEMORY_CONTROL1r */
  54382         soc_block_list[16],
  54383         soc_genreg,
  54384         1,
  54385         0,
  54386         0x80250,
  54387         0,
  54388         0,
  54389         3,
  54390         soc_XLPORT_MEMORY_CONTROL1r_fields,
  54391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54392         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  54393         -1,
  54394         -1,
  54395     },
  54396 #endif /* chips */
  54397 
  54398 #if defined(BCM_56840_A0)
  54399     { /* SOC_REG_INT_XLPORT_MEMORY_CONTROL2r */
  54400         soc_block_list[16],
  54401         soc_genreg,
  54402         1,
  54403         0,
  54404         0x80251,
  54405         0,
  54406         0,
  54407         3,
  54408         soc_XLPORT_MEMORY_CONTROL2r_fields,
  54409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54410         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  54411         -1,
  54412         -1,
  54413     },
  54414 #endif /* chips */
  54415 
  54416 #if defined(BCM_56840_B0)
  54417     { /* SOC_REG_INT_XLPORT_MEMORY_CONTROL0_BCM56840_B0r */
  54418         soc_block_list[16],
  54419         soc_genreg,
  54420         1,
  54421         0,
  54422         0x8024f,
  54423         0,
  54424         0,
  54425         2,
  54426         soc_XLPORT_MEMORY_CONTROL0r_fields,
  54427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54429         -1,
  54430         -1,
  54431     },
  54432 #endif /* chips */
  54433 
  54434 #if defined(BCM_88732_A0)
  54435     { /* SOC_REG_INT_XLPORT_MEMORY_CONTROL0_BCM88732_A0r */
  54436         soc_block_list[16],
  54437         soc_genreg,
  54438         1,
  54439         0,
  54440         0x8024f,
  54441         0,
  54442         0,
  54443         2,
  54444         soc_XLPORT_MEMORY_CONTROL0r_fields,
  54445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54446         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  54447         -1,
  54448         -1,
  54449     },
  54450 #endif /* chips */
  54451 
  54452 #if defined(BCM_56840_B0)
  54453     { /* SOC_REG_INT_XLPORT_MEMORY_CONTROL1_BCM56840_B0r */
  54454         soc_block_list[16],
  54455         soc_genreg,
  54456         1,
  54457         0,
  54458         0x80250,
  54459         0,
  54460         0,
  54461         3,
  54462         soc_XLPORT_MEMORY_CONTROL1r_fields,
  54463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54464         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  54465         -1,
  54466         -1,
  54467     },
  54468 #endif /* chips */
  54469 
  54470 #if defined(BCM_88732_A0)
  54471     { /* SOC_REG_INT_XLPORT_MEMORY_CONTROL1_BCM88732_A0r */
  54472         soc_block_list[16],
  54473         soc_genreg,
  54474         1,
  54475         0,
  54476         0x80250,
  54477         0,
  54478         0,
  54479         3,
  54480         soc_XLPORT_MEMORY_CONTROL1r_fields,
  54481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54482         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  54483         -1,
  54484         -1,
  54485     },
  54486 #endif /* chips */
  54487 
  54488 #if defined(BCM_56840_B0)
  54489     { /* SOC_REG_INT_XLPORT_MEMORY_CONTROL2_BCM56840_B0r */
  54490         soc_block_list[16],
  54491         soc_genreg,
  54492         1,
  54493         0,
  54494         0x80251,
  54495         0,
  54496         0,
  54497         3,
  54498         soc_XLPORT_MEMORY_CONTROL2r_fields,
  54499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54500         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  54501         -1,
  54502         -1,
  54503     },
  54504 #endif /* chips */
  54505 
  54506 #if defined(BCM_88732_A0)
  54507     { /* SOC_REG_INT_XLPORT_MEMORY_CONTROL2_BCM88732_A0r */
  54508         soc_block_list[16],
  54509         soc_genreg,
  54510         1,
  54511         0,
  54512         0x80251,
  54513         0,
  54514         0,
  54515         3,
  54516         soc_XLPORT_MEMORY_CONTROL2r_fields,
  54517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54518         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  54519         -1,
  54520         -1,
  54521     },
  54522 #endif /* chips */
  54523 
  54524 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  54525     { /* SOC_REG_INT_XLPORT_MIB_MIN_FRAG_SIZEr */
  54526         soc_block_list[16],
  54527         soc_portreg,
  54528         1,
  54529         0,
  54530         0x23500,
  54531         0,
  54532         0,
  54533         3,
  54534         soc_XLPORT_MIB_MIN_FRAG_SIZEr_fields,
  54535         SOC_RESET_VAL_DEC(0x00000808, 0x00000000)
  54536         SOC_RESET_MASK_DEC(0x00007f7f, 0x00000000)
  54537         -1,
  54538         -1,
  54539     },
  54540 #endif /* chips */
  54541 
  54542 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  54543     { /* SOC_REG_INT_XLPORT_MIB_MIN_FRAG_SIZE_BCM56670_A0r */
  54544         soc_block_list[16],
  54545         soc_portreg,
  54546         1,
  54547         0,
  54548         0x23500,
  54549         0,
  54550         0,
  54551         3,
  54552         soc_XLPORT_MIB_MIN_FRAG_SIZEr_fields,
  54553         SOC_RESET_VAL_DEC(0x00000808, 0x00000000)
  54554         SOC_RESET_MASK_DEC(0x00007f7f, 0x00000000)
  54555         -1,
  54556         -1,
  54557     },
  54558 #endif /* chips */
  54559 
  54560 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  54561     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  54562     defined(BCM_56980_B0)
  54563     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR0_CONFIGr */
  54564         soc_block_list[16],
  54565         soc_portreg,
  54566         1,
  54567         0,
  54568         0x23100,
  54569         0,
  54570         0,
  54571         2,
  54572         soc_CLPORT_MIB_PROG_RANGE_CNTR0_CONFIGr_fields,
  54573         SOC_RESET_VAL_DEC(0x004f0040, 0x00000000)
  54574         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54575         -1,
  54576         -1,
  54577         3,
  54578     },
  54579 #endif /* chips */
  54580 
  54581 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  54582     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR0_CONFIG_BCM53570_A0r */
  54583         soc_block_list[16],
  54584         soc_portreg,
  54585         1,
  54586         0,
  54587         0x23100,
  54588         0,
  54589         0,
  54590         2,
  54591         soc_CLPORT_MIB_PROG_RANGE_CNTR0_CONFIGr_fields,
  54592         SOC_RESET_VAL_DEC(0x004f0040, 0x00000000)
  54593         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54594         -1,
  54595         -1,
  54596     },
  54597 #endif /* chips */
  54598 
  54599 #if defined(BCM_56370_A0)
  54600     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR0_CONFIG_BCM56370_A0r */
  54601         soc_block_list[16],
  54602         soc_portreg,
  54603         1,
  54604         0,
  54605         0x23100,
  54606         0,
  54607         0,
  54608         2,
  54609         soc_CLPORT_MIB_PROG_RANGE_CNTR0_CONFIGr_fields,
  54610         SOC_RESET_VAL_DEC(0x004f0040, 0x00000000)
  54611         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54612         -1,
  54613         -1,
  54614         3,
  54615     },
  54616 #endif /* chips */
  54617 
  54618 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  54619     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR0_CONFIG_BCM56670_A0r */
  54620         soc_block_list[16],
  54621         soc_portreg,
  54622         1,
  54623         0,
  54624         0x23100,
  54625         0,
  54626         0,
  54627         2,
  54628         soc_CLPORT_MIB_PROG_RANGE_CNTR0_CONFIGr_fields,
  54629         SOC_RESET_VAL_DEC(0x004f0040, 0x00000000)
  54630         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54631         -1,
  54632         -1,
  54633     },
  54634 #endif /* chips */
  54635 
  54636 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  54637     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  54638     defined(BCM_56980_B0)
  54639     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR1_CONFIGr */
  54640         soc_block_list[16],
  54641         soc_portreg,
  54642         1,
  54643         0,
  54644         0x23200,
  54645         0,
  54646         0,
  54647         2,
  54648         soc_CLPORT_MIB_PROG_RANGE_CNTR1_CONFIGr_fields,
  54649         SOC_RESET_VAL_DEC(0x005f0050, 0x00000000)
  54650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54651         -1,
  54652         -1,
  54653         3,
  54654     },
  54655 #endif /* chips */
  54656 
  54657 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  54658     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR1_CONFIG_BCM53570_A0r */
  54659         soc_block_list[16],
  54660         soc_portreg,
  54661         1,
  54662         0,
  54663         0x23200,
  54664         0,
  54665         0,
  54666         2,
  54667         soc_CLPORT_MIB_PROG_RANGE_CNTR1_CONFIGr_fields,
  54668         SOC_RESET_VAL_DEC(0x005f0050, 0x00000000)
  54669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54670         -1,
  54671         -1,
  54672     },
  54673 #endif /* chips */
  54674 
  54675 #if defined(BCM_56370_A0)
  54676     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR1_CONFIG_BCM56370_A0r */
  54677         soc_block_list[16],
  54678         soc_portreg,
  54679         1,
  54680         0,
  54681         0x23200,
  54682         0,
  54683         0,
  54684         2,
  54685         soc_CLPORT_MIB_PROG_RANGE_CNTR1_CONFIGr_fields,
  54686         SOC_RESET_VAL_DEC(0x005f0050, 0x00000000)
  54687         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54688         -1,
  54689         -1,
  54690         3,
  54691     },
  54692 #endif /* chips */
  54693 
  54694 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  54695     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR1_CONFIG_BCM56670_A0r */
  54696         soc_block_list[16],
  54697         soc_portreg,
  54698         1,
  54699         0,
  54700         0x23200,
  54701         0,
  54702         0,
  54703         2,
  54704         soc_CLPORT_MIB_PROG_RANGE_CNTR1_CONFIGr_fields,
  54705         SOC_RESET_VAL_DEC(0x005f0050, 0x00000000)
  54706         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54707         -1,
  54708         -1,
  54709     },
  54710 #endif /* chips */
  54711 
  54712 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  54713     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  54714     defined(BCM_56980_B0)
  54715     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR2_CONFIGr */
  54716         soc_block_list[16],
  54717         soc_portreg,
  54718         1,
  54719         0,
  54720         0x23300,
  54721         0,
  54722         0,
  54723         2,
  54724         soc_CLPORT_MIB_PROG_RANGE_CNTR2_CONFIGr_fields,
  54725         SOC_RESET_VAL_DEC(0x006f0060, 0x00000000)
  54726         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54727         -1,
  54728         -1,
  54729         3,
  54730     },
  54731 #endif /* chips */
  54732 
  54733 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  54734     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR2_CONFIG_BCM53570_A0r */
  54735         soc_block_list[16],
  54736         soc_portreg,
  54737         1,
  54738         0,
  54739         0x23300,
  54740         0,
  54741         0,
  54742         2,
  54743         soc_CLPORT_MIB_PROG_RANGE_CNTR2_CONFIGr_fields,
  54744         SOC_RESET_VAL_DEC(0x006f0060, 0x00000000)
  54745         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54746         -1,
  54747         -1,
  54748     },
  54749 #endif /* chips */
  54750 
  54751 #if defined(BCM_56370_A0)
  54752     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR2_CONFIG_BCM56370_A0r */
  54753         soc_block_list[16],
  54754         soc_portreg,
  54755         1,
  54756         0,
  54757         0x23300,
  54758         0,
  54759         0,
  54760         2,
  54761         soc_CLPORT_MIB_PROG_RANGE_CNTR2_CONFIGr_fields,
  54762         SOC_RESET_VAL_DEC(0x006f0060, 0x00000000)
  54763         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54764         -1,
  54765         -1,
  54766         3,
  54767     },
  54768 #endif /* chips */
  54769 
  54770 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  54771     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR2_CONFIG_BCM56670_A0r */
  54772         soc_block_list[16],
  54773         soc_portreg,
  54774         1,
  54775         0,
  54776         0x23300,
  54777         0,
  54778         0,
  54779         2,
  54780         soc_CLPORT_MIB_PROG_RANGE_CNTR2_CONFIGr_fields,
  54781         SOC_RESET_VAL_DEC(0x006f0060, 0x00000000)
  54782         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54783         -1,
  54784         -1,
  54785     },
  54786 #endif /* chips */
  54787 
  54788 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  54789     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  54790     defined(BCM_56980_B0)
  54791     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR3_CONFIGr */
  54792         soc_block_list[16],
  54793         soc_portreg,
  54794         1,
  54795         0,
  54796         0x23400,
  54797         0,
  54798         0,
  54799         2,
  54800         soc_CLPORT_MIB_PROG_RANGE_CNTR3_CONFIGr_fields,
  54801         SOC_RESET_VAL_DEC(0x007f0070, 0x00000000)
  54802         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54803         -1,
  54804         -1,
  54805         3,
  54806     },
  54807 #endif /* chips */
  54808 
  54809 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  54810     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR3_CONFIG_BCM53570_A0r */
  54811         soc_block_list[16],
  54812         soc_portreg,
  54813         1,
  54814         0,
  54815         0x23400,
  54816         0,
  54817         0,
  54818         2,
  54819         soc_CLPORT_MIB_PROG_RANGE_CNTR3_CONFIGr_fields,
  54820         SOC_RESET_VAL_DEC(0x007f0070, 0x00000000)
  54821         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54822         -1,
  54823         -1,
  54824     },
  54825 #endif /* chips */
  54826 
  54827 #if defined(BCM_56370_A0)
  54828     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR3_CONFIG_BCM56370_A0r */
  54829         soc_block_list[16],
  54830         soc_portreg,
  54831         1,
  54832         0,
  54833         0x23400,
  54834         0,
  54835         0,
  54836         2,
  54837         soc_CLPORT_MIB_PROG_RANGE_CNTR3_CONFIGr_fields,
  54838         SOC_RESET_VAL_DEC(0x007f0070, 0x00000000)
  54839         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54840         -1,
  54841         -1,
  54842         3,
  54843     },
  54844 #endif /* chips */
  54845 
  54846 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  54847     { /* SOC_REG_INT_XLPORT_MIB_PROG_RANGE_CNTR3_CONFIG_BCM56670_A0r */
  54848         soc_block_list[16],
  54849         soc_portreg,
  54850         1,
  54851         0,
  54852         0x23400,
  54853         0,
  54854         0,
  54855         2,
  54856         soc_CLPORT_MIB_PROG_RANGE_CNTR3_CONFIGr_fields,
  54857         SOC_RESET_VAL_DEC(0x007f0070, 0x00000000)
  54858         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  54859         -1,
  54860         -1,
  54861     },
  54862 #endif /* chips */
  54863 
  54864 #if defined(BCM_56840_A0)
  54865     { /* SOC_REG_INT_XLPORT_MIB_RESETr */
  54866         soc_block_list[16],
  54867         soc_genreg,
  54868         1,
  54869         0,
  54870         0x8022c,
  54871         0,
  54872         0,
  54873         1,
  54874         soc_XLPORT_MIB_RESETr_fields,
  54875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54876         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54877         -1,
  54878         -1,
  54879     },
  54880 #endif /* chips */
  54881 
  54882 #if defined(BCM_2801PM_A0)
  54883     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM2801PM_A0r */
  54884         soc_block_list[56],
  54885         soc_genreg,
  54886         1,
  54887         0,
  54888         0x2022400,
  54889         0,
  54890         0,
  54891         1,
  54892         soc_CLPORT_MIB_RESETr_fields,
  54893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54894         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54895         -1,
  54896         -1,
  54897     },
  54898 #endif /* chips */
  54899 
  54900 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  54901     defined(BCM_56670_B0)
  54902     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM53400_A0r */
  54903         soc_block_list[16],
  54904         soc_genreg,
  54905         1,
  54906         0,
  54907         0x2022400,
  54908         0,
  54909         0,
  54910         1,
  54911         soc_XLPORT_MIB_RESET_BCM53400_A0r_fields,
  54912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54913         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54914         -1,
  54915         -1,
  54916     },
  54917 #endif /* chips */
  54918 
  54919 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  54920     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM53570_A0r */
  54921         soc_block_list[16],
  54922         soc_genreg,
  54923         1,
  54924         0,
  54925         0x2022400,
  54926         0,
  54927         0,
  54928         1,
  54929         soc_XLPORT_MIB_RESET_BCM53400_A0r_fields,
  54930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54931         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54932         -1,
  54933         -1,
  54934     },
  54935 #endif /* chips */
  54936 
  54937 #if defined(BCM_56150_A0)
  54938     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM56150_A0r */
  54939         soc_block_list[16],
  54940         soc_genreg,
  54941         1,
  54942         0,
  54943         0x2022c00,
  54944         0,
  54945         0,
  54946         1,
  54947         soc_XLPORT_MIB_RESET_BCM56150_A0r_fields,
  54948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54949         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54950         -1,
  54951         -1,
  54952     },
  54953 #endif /* chips */
  54954 
  54955 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  54956     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM56160_A0r */
  54957         soc_block_list[16],
  54958         soc_genreg,
  54959         1,
  54960         0,
  54961         0x2022400,
  54962         0,
  54963         0,
  54964         1,
  54965         soc_XLPORT_MIB_RESET_BCM53400_A0r_fields,
  54966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54967         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54968         -1,
  54969         -1,
  54970     },
  54971 #endif /* chips */
  54972 
  54973 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  54974     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM56260_A0r */
  54975         soc_block_list[16],
  54976         soc_genreg,
  54977         1,
  54978         0,
  54979         0x2022400,
  54980         0,
  54981         0,
  54982         1,
  54983         soc_XLPORT_MIB_RESET_BCM53400_A0r_fields,
  54984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54985         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54986         -1,
  54987         -1,
  54988     },
  54989 #endif /* chips */
  54990 
  54991 #if defined(BCM_56370_A0)
  54992     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM56370_A0r */
  54993         soc_block_list[16],
  54994         soc_genreg,
  54995         1,
  54996         0,
  54997         0x2022400,
  54998         0,
  54999         0,
  55000         1,
  55001         soc_XLPORT_MIB_RESET_BCM53400_A0r_fields,
  55002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55003         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55004         -1,
  55005         -1,
  55006         3,
  55007     },
  55008 #endif /* chips */
  55009 
  55010 #if defined(BCM_56560_A0)
  55011     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM56560_A0r */
  55012         soc_block_list[217],
  55013         soc_genreg,
  55014         1,
  55015         0,
  55016         0x2022400,
  55017         0,
  55018         0,
  55019         1,
  55020         soc_XLPORT_MIB_RESET_BCM53400_A0r_fields,
  55021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55022         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55023         -1,
  55024         -1,
  55025     },
  55026 #endif /* chips */
  55027 
  55028 #if defined(BCM_56560_B0)
  55029     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM56560_B0r */
  55030         soc_block_list[16],
  55031         soc_genreg,
  55032         1,
  55033         0,
  55034         0x2022400,
  55035         0,
  55036         0,
  55037         1,
  55038         soc_XLPORT_MIB_RESET_BCM53400_A0r_fields,
  55039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55040         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55041         -1,
  55042         -1,
  55043     },
  55044 #endif /* chips */
  55045 
  55046 #if defined(BCM_56840_B0)
  55047     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM56840_B0r */
  55048         soc_block_list[16],
  55049         soc_genreg,
  55050         1,
  55051         0,
  55052         0x8022c,
  55053         0,
  55054         0,
  55055         1,
  55056         soc_XLPORT_MIB_RESETr_fields,
  55057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55058         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55059         -1,
  55060         -1,
  55061     },
  55062 #endif /* chips */
  55063 
  55064 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  55065     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  55066     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  55067     defined(BCM_56980_B0)
  55068     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM56960_A0r */
  55069         soc_block_list[16],
  55070         soc_genreg,
  55071         1,
  55072         0,
  55073         0x2022400,
  55074         0,
  55075         0,
  55076         1,
  55077         soc_XLPORT_MIB_RESET_BCM53400_A0r_fields,
  55078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55079         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55080         -1,
  55081         -1,
  55082         3,
  55083     },
  55084 #endif /* chips */
  55085 
  55086 #if defined(BCM_88270_A0)
  55087     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM88270_A0r */
  55088         soc_block_list[56],
  55089         soc_genreg,
  55090         1,
  55091         0,
  55092         0x2022400,
  55093         0,
  55094         0,
  55095         1,
  55096         soc_XLPORT_MIB_RESET_BCM88270_A0r_fields,
  55097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55098         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55099         -1,
  55100         -1,
  55101     },
  55102 #endif /* chips */
  55103 
  55104 #if defined(BCM_88375_A0)
  55105     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM88375_A0r */
  55106         soc_block_list[56],
  55107         soc_genreg,
  55108         1,
  55109         0,
  55110         0x2022400,
  55111         0,
  55112         0,
  55113         1,
  55114         soc_XLPORT_MIB_RESET_BCM88375_A0r_fields,
  55115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55116         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55117         -1,
  55118         -1,
  55119     },
  55120 #endif /* chips */
  55121 
  55122 #if defined(BCM_88375_B0)
  55123     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM88375_B0r */
  55124         soc_block_list[56],
  55125         soc_genreg,
  55126         1,
  55127         0,
  55128         0x2022400,
  55129         0,
  55130         0,
  55131         1,
  55132         soc_XLPORT_MIB_RESET_BCM88375_B0r_fields,
  55133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55134         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55135         -1,
  55136         -1,
  55137     },
  55138 #endif /* chips */
  55139 
  55140 #if defined(BCM_88470_A0)
  55141     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM88470_A0r */
  55142         soc_block_list[56],
  55143         soc_genreg,
  55144         1,
  55145         0,
  55146         0x2022400,
  55147         0,
  55148         0,
  55149         1,
  55150         soc_XLPORT_MIB_RESET_BCM88470_A0r_fields,
  55151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55152         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55153         -1,
  55154         -1,
  55155     },
  55156 #endif /* chips */
  55157 
  55158 #if defined(BCM_88470_B0)
  55159     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM88470_B0r */
  55160         soc_block_list[56],
  55161         soc_genreg,
  55162         1,
  55163         0,
  55164         0x2022400,
  55165         0,
  55166         0,
  55167         1,
  55168         soc_XLPORT_MIB_RESET_BCM88470_B0r_fields,
  55169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55170         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55171         -1,
  55172         -1,
  55173     },
  55174 #endif /* chips */
  55175 
  55176 #if defined(BCM_88675_A0)
  55177     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM88675_A0r */
  55178         soc_block_list[56],
  55179         soc_genreg,
  55180         1,
  55181         0,
  55182         0x2022400,
  55183         0,
  55184         0,
  55185         1,
  55186         soc_XLPORT_MIB_RESET_BCM88675_A0r_fields,
  55187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55188         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55189         -1,
  55190         -1,
  55191     },
  55192 #endif /* chips */
  55193 
  55194 #if defined(BCM_88675_B0)
  55195     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM88675_B0r */
  55196         soc_block_list[56],
  55197         soc_genreg,
  55198         1,
  55199         0,
  55200         0x2022400,
  55201         0,
  55202         0,
  55203         1,
  55204         soc_XLPORT_MIB_RESET_BCM88675_B0r_fields,
  55205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55206         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55207         -1,
  55208         -1,
  55209     },
  55210 #endif /* chips */
  55211 
  55212 #if defined(BCM_88680_A0)
  55213     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM88680_A0r */
  55214         soc_block_list[56],
  55215         soc_genreg,
  55216         1,
  55217         0,
  55218         0x2022400,
  55219         0,
  55220         0,
  55221         1,
  55222         soc_XLPORT_MIB_RESET_BCM88680_A0r_fields,
  55223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55224         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55225         -1,
  55226         -1,
  55227     },
  55228 #endif /* chips */
  55229 
  55230 #if defined(BCM_88732_A0)
  55231     { /* SOC_REG_INT_XLPORT_MIB_RESET_BCM88732_A0r */
  55232         soc_block_list[16],
  55233         soc_genreg,
  55234         1,
  55235         0,
  55236         0x8022c,
  55237         0,
  55238         0,
  55239         1,
  55240         soc_XLPORT_MIB_RESETr_fields,
  55241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55242         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55243         -1,
  55244         -1,
  55245     },
  55246 #endif /* chips */
  55247 
  55248 #if defined(BCM_2801PM_A0)
  55249     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUSr */
  55250         soc_block_list[56],
  55251         soc_genreg,
  55252         1,
  55253         0,
  55254         0x2021d00,
  55255         0,
  55256         0,
  55257         4,
  55258         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55260         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55261         -1,
  55262         -1,
  55263     },
  55264 #endif /* chips */
  55265 
  55266 #if defined(BCM_53400_A0)
  55267     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM53400_A0r */
  55268         soc_block_list[16],
  55269         soc_genreg,
  55270         1,
  55271         0,
  55272         0x2021d00,
  55273         0,
  55274         0,
  55275         4,
  55276         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55278         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55279         -1,
  55280         -1,
  55281     },
  55282 #endif /* chips */
  55283 
  55284 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  55285     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM53570_A0r */
  55286         soc_block_list[16],
  55287         soc_genreg,
  55288         1,
  55289         0,
  55290         0x2021d00,
  55291         0,
  55292         0,
  55293         9,
  55294         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM53570_A0r_fields,
  55295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55296         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  55297         -1,
  55298         -1,
  55299     },
  55300 #endif /* chips */
  55301 
  55302 #if defined(BCM_56150_A0)
  55303     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM56150_A0r */
  55304         soc_block_list[16],
  55305         soc_genreg,
  55306         1,
  55307         0,
  55308         0x2021d00,
  55309         0,
  55310         0,
  55311         4,
  55312         soc_PGW_MIB_RSC0_ECC_STATUSr_fields,
  55313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55314         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55315         -1,
  55316         -1,
  55317     },
  55318 #endif /* chips */
  55319 
  55320 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  55321     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM56160_A0r */
  55322         soc_block_list[16],
  55323         soc_genreg,
  55324         1,
  55325         0,
  55326         0x2021d00,
  55327         0,
  55328         0,
  55329         4,
  55330         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55332         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55333         -1,
  55334         -1,
  55335     },
  55336 #endif /* chips */
  55337 
  55338 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  55339     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM56260_A0r */
  55340         soc_block_list[16],
  55341         soc_genreg,
  55342         1,
  55343         0,
  55344         0x2021d00,
  55345         0,
  55346         0,
  55347         4,
  55348         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55350         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55351         -1,
  55352         -1,
  55353     },
  55354 #endif /* chips */
  55355 
  55356 #if defined(BCM_56370_A0)
  55357     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM56370_A0r */
  55358         soc_block_list[16],
  55359         soc_genreg,
  55360         1,
  55361         0,
  55362         0x2021d00,
  55363         0,
  55364         0,
  55365         4,
  55366         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55368         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55369         -1,
  55370         -1,
  55371         3,
  55372     },
  55373 #endif /* chips */
  55374 
  55375 #if defined(BCM_56560_A0)
  55376     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM56560_A0r */
  55377         soc_block_list[217],
  55378         soc_genreg,
  55379         1,
  55380         0,
  55381         0x2021d00,
  55382         0,
  55383         0,
  55384         4,
  55385         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55387         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55388         -1,
  55389         -1,
  55390     },
  55391 #endif /* chips */
  55392 
  55393 #if defined(BCM_56560_B0)
  55394     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM56560_B0r */
  55395         soc_block_list[16],
  55396         soc_genreg,
  55397         1,
  55398         0,
  55399         0x2021d00,
  55400         0,
  55401         0,
  55402         4,
  55403         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55405         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55406         -1,
  55407         -1,
  55408     },
  55409 #endif /* chips */
  55410 
  55411 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  55412     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM56670_A0r */
  55413         soc_block_list[16],
  55414         soc_genreg,
  55415         1,
  55416         0,
  55417         0x2021d00,
  55418         0,
  55419         0,
  55420         9,
  55421         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM53570_A0r_fields,
  55422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55423         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  55424         -1,
  55425         -1,
  55426     },
  55427 #endif /* chips */
  55428 
  55429 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  55430     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  55431     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  55432     defined(BCM_56980_B0)
  55433     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM56960_A0r */
  55434         soc_block_list[16],
  55435         soc_genreg,
  55436         1,
  55437         0,
  55438         0x2021d00,
  55439         0,
  55440         0,
  55441         4,
  55442         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55444         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55445         -1,
  55446         -1,
  55447         3,
  55448     },
  55449 #endif /* chips */
  55450 
  55451 #if defined(BCM_88270_A0)
  55452     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM88270_A0r */
  55453         soc_block_list[56],
  55454         soc_genreg,
  55455         1,
  55456         0,
  55457         0x2021d00,
  55458         0,
  55459         0,
  55460         4,
  55461         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88270_A0r_fields,
  55462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55463         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55464         -1,
  55465         -1,
  55466     },
  55467 #endif /* chips */
  55468 
  55469 #if defined(BCM_88375_A0)
  55470     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM88375_A0r */
  55471         soc_block_list[56],
  55472         soc_genreg,
  55473         1,
  55474         0,
  55475         0x2021d00,
  55476         0,
  55477         0,
  55478         4,
  55479         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88375_A0r_fields,
  55480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55481         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55482         -1,
  55483         -1,
  55484     },
  55485 #endif /* chips */
  55486 
  55487 #if defined(BCM_88375_B0)
  55488     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM88375_B0r */
  55489         soc_block_list[56],
  55490         soc_genreg,
  55491         1,
  55492         0,
  55493         0x2021d00,
  55494         0,
  55495         0,
  55496         4,
  55497         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88375_B0r_fields,
  55498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55499         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55500         -1,
  55501         -1,
  55502     },
  55503 #endif /* chips */
  55504 
  55505 #if defined(BCM_88470_A0)
  55506     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM88470_A0r */
  55507         soc_block_list[56],
  55508         soc_genreg,
  55509         1,
  55510         0,
  55511         0x2021d00,
  55512         0,
  55513         0,
  55514         4,
  55515         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88470_A0r_fields,
  55516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55517         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55518         -1,
  55519         -1,
  55520     },
  55521 #endif /* chips */
  55522 
  55523 #if defined(BCM_88470_B0)
  55524     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM88470_B0r */
  55525         soc_block_list[56],
  55526         soc_genreg,
  55527         1,
  55528         0,
  55529         0x2021d00,
  55530         0,
  55531         0,
  55532         4,
  55533         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88470_B0r_fields,
  55534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55535         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55536         -1,
  55537         -1,
  55538     },
  55539 #endif /* chips */
  55540 
  55541 #if defined(BCM_88675_A0)
  55542     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM88675_A0r */
  55543         soc_block_list[56],
  55544         soc_genreg,
  55545         1,
  55546         0,
  55547         0x2021d00,
  55548         0,
  55549         0,
  55550         4,
  55551         soc_XLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55553         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55554         -1,
  55555         -1,
  55556     },
  55557 #endif /* chips */
  55558 
  55559 #if defined(BCM_88675_B0)
  55560     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM88675_B0r */
  55561         soc_block_list[56],
  55562         soc_genreg,
  55563         1,
  55564         0,
  55565         0x2021d00,
  55566         0,
  55567         0,
  55568         4,
  55569         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88675_B0r_fields,
  55570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55571         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55572         -1,
  55573         -1,
  55574     },
  55575 #endif /* chips */
  55576 
  55577 #if defined(BCM_88680_A0)
  55578     { /* SOC_REG_INT_XLPORT_MIB_RSC0_ECC_STATUS_BCM88680_A0r */
  55579         soc_block_list[56],
  55580         soc_genreg,
  55581         1,
  55582         0,
  55583         0x2021d00,
  55584         0,
  55585         0,
  55586         4,
  55587         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88680_A0r_fields,
  55588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55589         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55590         -1,
  55591         -1,
  55592     },
  55593 #endif /* chips */
  55594 
  55595 #if defined(BCM_2801PM_A0)
  55596     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUSr */
  55597         soc_block_list[56],
  55598         soc_genreg,
  55599         1,
  55600         0,
  55601         0x2021e00,
  55602         0,
  55603         0,
  55604         4,
  55605         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55607         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55608         -1,
  55609         -1,
  55610     },
  55611 #endif /* chips */
  55612 
  55613 #if defined(BCM_53400_A0)
  55614     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM53400_A0r */
  55615         soc_block_list[16],
  55616         soc_genreg,
  55617         1,
  55618         0,
  55619         0x2021e00,
  55620         0,
  55621         0,
  55622         4,
  55623         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55625         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55626         -1,
  55627         -1,
  55628     },
  55629 #endif /* chips */
  55630 
  55631 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  55632     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM53570_A0r */
  55633         soc_block_list[16],
  55634         soc_genreg,
  55635         1,
  55636         0,
  55637         0x2021e00,
  55638         0,
  55639         0,
  55640         9,
  55641         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM53570_A0r_fields,
  55642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55643         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  55644         -1,
  55645         -1,
  55646     },
  55647 #endif /* chips */
  55648 
  55649 #if defined(BCM_56150_A0)
  55650     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM56150_A0r */
  55651         soc_block_list[16],
  55652         soc_genreg,
  55653         1,
  55654         0,
  55655         0x2021e00,
  55656         0,
  55657         0,
  55658         4,
  55659         soc_PGW_MIB_RSC0_ECC_STATUSr_fields,
  55660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55661         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55662         -1,
  55663         -1,
  55664     },
  55665 #endif /* chips */
  55666 
  55667 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  55668     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM56160_A0r */
  55669         soc_block_list[16],
  55670         soc_genreg,
  55671         1,
  55672         0,
  55673         0x2021e00,
  55674         0,
  55675         0,
  55676         4,
  55677         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55679         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55680         -1,
  55681         -1,
  55682     },
  55683 #endif /* chips */
  55684 
  55685 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  55686     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM56260_A0r */
  55687         soc_block_list[16],
  55688         soc_genreg,
  55689         1,
  55690         0,
  55691         0x2021e00,
  55692         0,
  55693         0,
  55694         4,
  55695         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55697         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55698         -1,
  55699         -1,
  55700     },
  55701 #endif /* chips */
  55702 
  55703 #if defined(BCM_56370_A0)
  55704     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM56370_A0r */
  55705         soc_block_list[16],
  55706         soc_genreg,
  55707         1,
  55708         0,
  55709         0x2021e00,
  55710         0,
  55711         0,
  55712         4,
  55713         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55715         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55716         -1,
  55717         -1,
  55718         3,
  55719     },
  55720 #endif /* chips */
  55721 
  55722 #if defined(BCM_56560_A0)
  55723     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM56560_A0r */
  55724         soc_block_list[217],
  55725         soc_genreg,
  55726         1,
  55727         0,
  55728         0x2021e00,
  55729         0,
  55730         0,
  55731         4,
  55732         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55734         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55735         -1,
  55736         -1,
  55737     },
  55738 #endif /* chips */
  55739 
  55740 #if defined(BCM_56560_B0)
  55741     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM56560_B0r */
  55742         soc_block_list[16],
  55743         soc_genreg,
  55744         1,
  55745         0,
  55746         0x2021e00,
  55747         0,
  55748         0,
  55749         4,
  55750         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55752         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55753         -1,
  55754         -1,
  55755     },
  55756 #endif /* chips */
  55757 
  55758 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  55759     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM56670_A0r */
  55760         soc_block_list[16],
  55761         soc_genreg,
  55762         1,
  55763         0,
  55764         0x2021e00,
  55765         0,
  55766         0,
  55767         9,
  55768         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM53570_A0r_fields,
  55769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55770         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  55771         -1,
  55772         -1,
  55773     },
  55774 #endif /* chips */
  55775 
  55776 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  55777     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  55778     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  55779     defined(BCM_56980_B0)
  55780     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM56960_A0r */
  55781         soc_block_list[16],
  55782         soc_genreg,
  55783         1,
  55784         0,
  55785         0x2021e00,
  55786         0,
  55787         0,
  55788         4,
  55789         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  55790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55791         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55792         -1,
  55793         -1,
  55794         3,
  55795     },
  55796 #endif /* chips */
  55797 
  55798 #if defined(BCM_88270_A0)
  55799     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM88270_A0r */
  55800         soc_block_list[56],
  55801         soc_genreg,
  55802         1,
  55803         0,
  55804         0x2021e00,
  55805         0,
  55806         0,
  55807         4,
  55808         soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88270_A0r_fields,
  55809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55810         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55811         -1,
  55812         -1,
  55813     },
  55814 #endif /* chips */
  55815 
  55816 #if defined(BCM_88375_A0)
  55817     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM88375_A0r */
  55818         soc_block_list[56],
  55819         soc_genreg,
  55820         1,
  55821         0,
  55822         0x2021e00,
  55823         0,
  55824         0,
  55825         4,
  55826         soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88375_A0r_fields,
  55827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55828         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55829         -1,
  55830         -1,
  55831     },
  55832 #endif /* chips */
  55833 
  55834 #if defined(BCM_88375_B0)
  55835     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM88375_B0r */
  55836         soc_block_list[56],
  55837         soc_genreg,
  55838         1,
  55839         0,
  55840         0x2021e00,
  55841         0,
  55842         0,
  55843         4,
  55844         soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88375_B0r_fields,
  55845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55846         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55847         -1,
  55848         -1,
  55849     },
  55850 #endif /* chips */
  55851 
  55852 #if defined(BCM_88470_A0)
  55853     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM88470_A0r */
  55854         soc_block_list[56],
  55855         soc_genreg,
  55856         1,
  55857         0,
  55858         0x2021e00,
  55859         0,
  55860         0,
  55861         4,
  55862         soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88470_A0r_fields,
  55863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55864         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55865         -1,
  55866         -1,
  55867     },
  55868 #endif /* chips */
  55869 
  55870 #if defined(BCM_88470_B0)
  55871     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM88470_B0r */
  55872         soc_block_list[56],
  55873         soc_genreg,
  55874         1,
  55875         0,
  55876         0x2021e00,
  55877         0,
  55878         0,
  55879         4,
  55880         soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88470_B0r_fields,
  55881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55882         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55883         -1,
  55884         -1,
  55885     },
  55886 #endif /* chips */
  55887 
  55888 #if defined(BCM_88675_A0)
  55889     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM88675_A0r */
  55890         soc_block_list[56],
  55891         soc_genreg,
  55892         1,
  55893         0,
  55894         0x2021e00,
  55895         0,
  55896         0,
  55897         4,
  55898         soc_XLPORT_MIB_RSC1_ECC_STATUSr_fields,
  55899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55900         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55901         -1,
  55902         -1,
  55903     },
  55904 #endif /* chips */
  55905 
  55906 #if defined(BCM_88675_B0)
  55907     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM88675_B0r */
  55908         soc_block_list[56],
  55909         soc_genreg,
  55910         1,
  55911         0,
  55912         0x2021e00,
  55913         0,
  55914         0,
  55915         4,
  55916         soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88675_B0r_fields,
  55917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55918         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55919         -1,
  55920         -1,
  55921     },
  55922 #endif /* chips */
  55923 
  55924 #if defined(BCM_88680_A0)
  55925     { /* SOC_REG_INT_XLPORT_MIB_RSC1_ECC_STATUS_BCM88680_A0r */
  55926         soc_block_list[56],
  55927         soc_genreg,
  55928         1,
  55929         0,
  55930         0x2021e00,
  55931         0,
  55932         0,
  55933         4,
  55934         soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88680_A0r_fields,
  55935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55936         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  55937         -1,
  55938         -1,
  55939     },
  55940 #endif /* chips */
  55941 
  55942 #if defined(BCM_56840_A0)
  55943     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM0_ECC_STATUSr */
  55944         soc_block_list[16],
  55945         soc_genreg,
  55946         1,
  55947         0,
  55948         0x80249,
  55949         0,
  55950         0,
  55951         4,
  55952         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  55953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55954         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  55955         -1,
  55956         -1,
  55957     },
  55958 #endif /* chips */
  55959 
  55960 #if defined(BCM_56840_B0)
  55961     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM0_ECC_STATUS_BCM56840_B0r */
  55962         soc_block_list[16],
  55963         soc_genreg,
  55964         1,
  55965         0,
  55966         0x80249,
  55967         0,
  55968         0,
  55969         4,
  55970         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  55971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55972         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  55973         -1,
  55974         -1,
  55975     },
  55976 #endif /* chips */
  55977 
  55978 #if defined(BCM_88732_A0)
  55979     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM0_ECC_STATUS_BCM88732_A0r */
  55980         soc_block_list[16],
  55981         soc_genreg,
  55982         1,
  55983         0,
  55984         0x80249,
  55985         0,
  55986         0,
  55987         4,
  55988         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  55989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55990         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  55991         -1,
  55992         -1,
  55993     },
  55994 #endif /* chips */
  55995 
  55996 #if defined(BCM_56840_A0)
  55997     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM1_ECC_STATUSr */
  55998         soc_block_list[16],
  55999         soc_genreg,
  56000         1,
  56001         0,
  56002         0x80248,
  56003         0,
  56004         0,
  56005         4,
  56006         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56008         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56009         -1,
  56010         -1,
  56011     },
  56012 #endif /* chips */
  56013 
  56014 #if defined(BCM_56840_B0)
  56015     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM1_ECC_STATUS_BCM56840_B0r */
  56016         soc_block_list[16],
  56017         soc_genreg,
  56018         1,
  56019         0,
  56020         0x80248,
  56021         0,
  56022         0,
  56023         4,
  56024         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56026         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56027         -1,
  56028         -1,
  56029     },
  56030 #endif /* chips */
  56031 
  56032 #if defined(BCM_88732_A0)
  56033     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM1_ECC_STATUS_BCM88732_A0r */
  56034         soc_block_list[16],
  56035         soc_genreg,
  56036         1,
  56037         0,
  56038         0x80248,
  56039         0,
  56040         0,
  56041         4,
  56042         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56044         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56045         -1,
  56046         -1,
  56047     },
  56048 #endif /* chips */
  56049 
  56050 #if defined(BCM_56840_A0)
  56051     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM2_ECC_STATUSr */
  56052         soc_block_list[16],
  56053         soc_genreg,
  56054         1,
  56055         0,
  56056         0x80247,
  56057         0,
  56058         0,
  56059         4,
  56060         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56062         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56063         -1,
  56064         -1,
  56065     },
  56066 #endif /* chips */
  56067 
  56068 #if defined(BCM_56840_B0)
  56069     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM2_ECC_STATUS_BCM56840_B0r */
  56070         soc_block_list[16],
  56071         soc_genreg,
  56072         1,
  56073         0,
  56074         0x80247,
  56075         0,
  56076         0,
  56077         4,
  56078         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56080         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56081         -1,
  56082         -1,
  56083     },
  56084 #endif /* chips */
  56085 
  56086 #if defined(BCM_88732_A0)
  56087     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM2_ECC_STATUS_BCM88732_A0r */
  56088         soc_block_list[16],
  56089         soc_genreg,
  56090         1,
  56091         0,
  56092         0x80247,
  56093         0,
  56094         0,
  56095         4,
  56096         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56098         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56099         -1,
  56100         -1,
  56101     },
  56102 #endif /* chips */
  56103 
  56104 #if defined(BCM_56840_A0)
  56105     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM3_ECC_STATUSr */
  56106         soc_block_list[16],
  56107         soc_genreg,
  56108         1,
  56109         0,
  56110         0x80246,
  56111         0,
  56112         0,
  56113         4,
  56114         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56116         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56117         -1,
  56118         -1,
  56119     },
  56120 #endif /* chips */
  56121 
  56122 #if defined(BCM_56840_B0)
  56123     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM3_ECC_STATUS_BCM56840_B0r */
  56124         soc_block_list[16],
  56125         soc_genreg,
  56126         1,
  56127         0,
  56128         0x80246,
  56129         0,
  56130         0,
  56131         4,
  56132         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56134         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56135         -1,
  56136         -1,
  56137     },
  56138 #endif /* chips */
  56139 
  56140 #if defined(BCM_88732_A0)
  56141     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM3_ECC_STATUS_BCM88732_A0r */
  56142         soc_block_list[16],
  56143         soc_genreg,
  56144         1,
  56145         0,
  56146         0x80246,
  56147         0,
  56148         0,
  56149         4,
  56150         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56152         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56153         -1,
  56154         -1,
  56155     },
  56156 #endif /* chips */
  56157 
  56158 #if defined(BCM_56840_A0)
  56159     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM4_ECC_STATUSr */
  56160         soc_block_list[16],
  56161         soc_genreg,
  56162         1,
  56163         0,
  56164         0x80245,
  56165         0,
  56166         0,
  56167         4,
  56168         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56170         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56171         -1,
  56172         -1,
  56173     },
  56174 #endif /* chips */
  56175 
  56176 #if defined(BCM_56840_B0)
  56177     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM4_ECC_STATUS_BCM56840_B0r */
  56178         soc_block_list[16],
  56179         soc_genreg,
  56180         1,
  56181         0,
  56182         0x80245,
  56183         0,
  56184         0,
  56185         4,
  56186         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56188         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56189         -1,
  56190         -1,
  56191     },
  56192 #endif /* chips */
  56193 
  56194 #if defined(BCM_88732_A0)
  56195     { /* SOC_REG_INT_XLPORT_MIB_RSC_MEM4_ECC_STATUS_BCM88732_A0r */
  56196         soc_block_list[16],
  56197         soc_genreg,
  56198         1,
  56199         0,
  56200         0x80245,
  56201         0,
  56202         0,
  56203         4,
  56204         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  56205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56206         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  56207         -1,
  56208         -1,
  56209     },
  56210 #endif /* chips */
  56211 
  56212 #if defined(BCM_2801PM_A0)
  56213     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROLr */
  56214         soc_block_list[56],
  56215         soc_genreg,
  56216         1,
  56217         0,
  56218         0x2022200,
  56219         0,
  56220         0,
  56221         4,
  56222         soc_CLPORT_MIB_RSC_RAM_CONTROLr_fields,
  56223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56224         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56225         -1,
  56226         -1,
  56227     },
  56228 #endif /* chips */
  56229 
  56230 #if defined(BCM_53400_A0)
  56231     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM53400_A0r */
  56232         soc_block_list[16],
  56233         soc_genreg,
  56234         1,
  56235         0,
  56236         0x2022200,
  56237         0,
  56238         0,
  56239         4,
  56240         soc_CLPORT_MIB_RSC_RAM_CONTROLr_fields,
  56241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56242         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56243         -1,
  56244         -1,
  56245     },
  56246 #endif /* chips */
  56247 
  56248 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  56249     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM53570_A0r */
  56250         soc_block_list[16],
  56251         soc_genreg,
  56252         1,
  56253         0,
  56254         0x2022200,
  56255         0,
  56256         0,
  56257         4,
  56258         soc_CLPORT_MIB_RSC_RAM_CONTROL_BCM56965_A0r_fields,
  56259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56260         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56261         -1,
  56262         -1,
  56263     },
  56264 #endif /* chips */
  56265 
  56266 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  56267     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM56160_A0r */
  56268         soc_block_list[16],
  56269         soc_genreg,
  56270         1,
  56271         0,
  56272         0x2022200,
  56273         0,
  56274         0,
  56275         4,
  56276         soc_CLPORT_MIB_RSC_RAM_CONTROLr_fields,
  56277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56278         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56279         -1,
  56280         -1,
  56281     },
  56282 #endif /* chips */
  56283 
  56284 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56285     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM56260_A0r */
  56286         soc_block_list[16],
  56287         soc_genreg,
  56288         1,
  56289         0,
  56290         0x2022200,
  56291         0,
  56292         0,
  56293         4,
  56294         soc_CLPORT_MIB_RSC_RAM_CONTROLr_fields,
  56295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56296         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56297         -1,
  56298         -1,
  56299     },
  56300 #endif /* chips */
  56301 
  56302 #if defined(BCM_56370_A0)
  56303     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM56370_A0r */
  56304         soc_block_list[16],
  56305         soc_genreg,
  56306         1,
  56307         0,
  56308         0x2022200,
  56309         0,
  56310         0,
  56311         4,
  56312         soc_CLPORT_MIB_RSC_RAM_CONTROL_BCM56965_A0r_fields,
  56313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56314         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56315         -1,
  56316         -1,
  56317         3,
  56318     },
  56319 #endif /* chips */
  56320 
  56321 #if defined(BCM_56560_A0)
  56322     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM56560_A0r */
  56323         soc_block_list[217],
  56324         soc_genreg,
  56325         1,
  56326         0,
  56327         0x2022200,
  56328         0,
  56329         0,
  56330         4,
  56331         soc_CLPORT_MIB_RSC_RAM_CONTROLr_fields,
  56332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56333         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56334         -1,
  56335         -1,
  56336     },
  56337 #endif /* chips */
  56338 
  56339 #if defined(BCM_56560_B0)
  56340     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM56560_B0r */
  56341         soc_block_list[16],
  56342         soc_genreg,
  56343         1,
  56344         0,
  56345         0x2022200,
  56346         0,
  56347         0,
  56348         4,
  56349         soc_CLPORT_MIB_RSC_RAM_CONTROLr_fields,
  56350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56351         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56352         -1,
  56353         -1,
  56354     },
  56355 #endif /* chips */
  56356 
  56357 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  56358     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM56670_A0r */
  56359         soc_block_list[16],
  56360         soc_genreg,
  56361         1,
  56362         0,
  56363         0x2022200,
  56364         0,
  56365         0,
  56366         4,
  56367         soc_CLPORT_MIB_RSC_RAM_CONTROL_BCM56965_A0r_fields,
  56368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56369         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56370         -1,
  56371         -1,
  56372     },
  56373 #endif /* chips */
  56374 
  56375 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  56376     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM56960_A0r */
  56377         soc_block_list[16],
  56378         soc_genreg,
  56379         1,
  56380         0,
  56381         0x2022200,
  56382         0,
  56383         0,
  56384         4,
  56385         soc_CLPORT_MIB_RSC_RAM_CONTROLr_fields,
  56386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56387         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56388         -1,
  56389         -1,
  56390         3,
  56391     },
  56392 #endif /* chips */
  56393 
  56394 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  56395     defined(BCM_56970_A0)
  56396     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM56970_A0r */
  56397         soc_block_list[16],
  56398         soc_genreg,
  56399         1,
  56400         0,
  56401         0x2022200,
  56402         0,
  56403         0,
  56404         4,
  56405         soc_CLPORT_MIB_RSC_RAM_CONTROL_BCM56560_B0r_fields,
  56406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56407         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56408         -1,
  56409         -1,
  56410         3,
  56411     },
  56412 #endif /* chips */
  56413 
  56414 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  56415     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM56980_A0r */
  56416         soc_block_list[16],
  56417         soc_genreg,
  56418         1,
  56419         0,
  56420         0x2022200,
  56421         0,
  56422         0,
  56423         4,
  56424         soc_CLPORT_MIB_RSC_RAM_CONTROL_BCM56965_A0r_fields,
  56425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56426         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  56427         -1,
  56428         -1,
  56429         3,
  56430     },
  56431 #endif /* chips */
  56432 
  56433 #if defined(BCM_88270_A0)
  56434     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM88270_A0r */
  56435         soc_block_list[56],
  56436         soc_genreg,
  56437         1,
  56438         0,
  56439         0x2022200,
  56440         0,
  56441         0,
  56442         4,
  56443         soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88270_A0r_fields,
  56444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56445         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56446         -1,
  56447         -1,
  56448     },
  56449 #endif /* chips */
  56450 
  56451 #if defined(BCM_88375_A0)
  56452     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM88375_A0r */
  56453         soc_block_list[56],
  56454         soc_genreg,
  56455         1,
  56456         0,
  56457         0x2022200,
  56458         0,
  56459         0,
  56460         4,
  56461         soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88375_A0r_fields,
  56462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56463         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56464         -1,
  56465         -1,
  56466     },
  56467 #endif /* chips */
  56468 
  56469 #if defined(BCM_88375_B0)
  56470     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM88375_B0r */
  56471         soc_block_list[56],
  56472         soc_genreg,
  56473         1,
  56474         0,
  56475         0x2022200,
  56476         0,
  56477         0,
  56478         4,
  56479         soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88375_B0r_fields,
  56480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56481         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56482         -1,
  56483         -1,
  56484     },
  56485 #endif /* chips */
  56486 
  56487 #if defined(BCM_88470_A0)
  56488     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM88470_A0r */
  56489         soc_block_list[56],
  56490         soc_genreg,
  56491         1,
  56492         0,
  56493         0x2022200,
  56494         0,
  56495         0,
  56496         4,
  56497         soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88470_A0r_fields,
  56498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56499         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56500         -1,
  56501         -1,
  56502     },
  56503 #endif /* chips */
  56504 
  56505 #if defined(BCM_88470_B0)
  56506     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM88470_B0r */
  56507         soc_block_list[56],
  56508         soc_genreg,
  56509         1,
  56510         0,
  56511         0x2022200,
  56512         0,
  56513         0,
  56514         4,
  56515         soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88470_B0r_fields,
  56516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56517         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56518         -1,
  56519         -1,
  56520     },
  56521 #endif /* chips */
  56522 
  56523 #if defined(BCM_88675_A0)
  56524     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM88675_A0r */
  56525         soc_block_list[56],
  56526         soc_genreg,
  56527         1,
  56528         0,
  56529         0x2022200,
  56530         0,
  56531         0,
  56532         4,
  56533         soc_XLPORT_MIB_RSC_RAM_CONTROLr_fields,
  56534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56535         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56536         -1,
  56537         -1,
  56538     },
  56539 #endif /* chips */
  56540 
  56541 #if defined(BCM_88675_B0)
  56542     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM88675_B0r */
  56543         soc_block_list[56],
  56544         soc_genreg,
  56545         1,
  56546         0,
  56547         0x2022200,
  56548         0,
  56549         0,
  56550         4,
  56551         soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88675_B0r_fields,
  56552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56553         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56554         -1,
  56555         -1,
  56556     },
  56557 #endif /* chips */
  56558 
  56559 #if defined(BCM_88680_A0)
  56560     { /* SOC_REG_INT_XLPORT_MIB_RSC_RAM_CONTROL_BCM88680_A0r */
  56561         soc_block_list[56],
  56562         soc_genreg,
  56563         1,
  56564         0,
  56565         0x2022200,
  56566         0,
  56567         0,
  56568         4,
  56569         soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88680_A0r_fields,
  56570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56571         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  56572         -1,
  56573         -1,
  56574     },
  56575 #endif /* chips */
  56576 
  56577 #if defined(BCM_2801PM_A0)
  56578     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUSr */
  56579         soc_block_list[56],
  56580         soc_genreg,
  56581         1,
  56582         0,
  56583         0x2021f00,
  56584         0,
  56585         0,
  56586         4,
  56587         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  56588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56589         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56590         -1,
  56591         -1,
  56592     },
  56593 #endif /* chips */
  56594 
  56595 #if defined(BCM_53400_A0)
  56596     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM53400_A0r */
  56597         soc_block_list[16],
  56598         soc_genreg,
  56599         1,
  56600         0,
  56601         0x2021f00,
  56602         0,
  56603         0,
  56604         4,
  56605         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  56606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56607         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56608         -1,
  56609         -1,
  56610     },
  56611 #endif /* chips */
  56612 
  56613 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  56614     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM53570_A0r */
  56615         soc_block_list[16],
  56616         soc_genreg,
  56617         1,
  56618         0,
  56619         0x2021f00,
  56620         0,
  56621         0,
  56622         9,
  56623         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM53570_A0r_fields,
  56624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56625         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  56626         -1,
  56627         -1,
  56628     },
  56629 #endif /* chips */
  56630 
  56631 #if defined(BCM_56150_A0)
  56632     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM56150_A0r */
  56633         soc_block_list[16],
  56634         soc_genreg,
  56635         1,
  56636         0,
  56637         0x2021f00,
  56638         0,
  56639         0,
  56640         4,
  56641         soc_PGW_MIB_RSC0_ECC_STATUSr_fields,
  56642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56643         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56644         -1,
  56645         -1,
  56646     },
  56647 #endif /* chips */
  56648 
  56649 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  56650     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM56160_A0r */
  56651         soc_block_list[16],
  56652         soc_genreg,
  56653         1,
  56654         0,
  56655         0x2021f00,
  56656         0,
  56657         0,
  56658         4,
  56659         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  56660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56661         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56662         -1,
  56663         -1,
  56664     },
  56665 #endif /* chips */
  56666 
  56667 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  56668     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM56260_A0r */
  56669         soc_block_list[16],
  56670         soc_genreg,
  56671         1,
  56672         0,
  56673         0x2021f00,
  56674         0,
  56675         0,
  56676         4,
  56677         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  56678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56679         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56680         -1,
  56681         -1,
  56682     },
  56683 #endif /* chips */
  56684 
  56685 #if defined(BCM_56370_A0)
  56686     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM56370_A0r */
  56687         soc_block_list[16],
  56688         soc_genreg,
  56689         1,
  56690         0,
  56691         0x2021f00,
  56692         0,
  56693         0,
  56694         4,
  56695         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  56696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56697         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56698         -1,
  56699         -1,
  56700         3,
  56701     },
  56702 #endif /* chips */
  56703 
  56704 #if defined(BCM_56560_A0)
  56705     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM56560_A0r */
  56706         soc_block_list[217],
  56707         soc_genreg,
  56708         1,
  56709         0,
  56710         0x2021f00,
  56711         0,
  56712         0,
  56713         4,
  56714         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  56715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56716         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56717         -1,
  56718         -1,
  56719     },
  56720 #endif /* chips */
  56721 
  56722 #if defined(BCM_56560_B0)
  56723     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM56560_B0r */
  56724         soc_block_list[16],
  56725         soc_genreg,
  56726         1,
  56727         0,
  56728         0x2021f00,
  56729         0,
  56730         0,
  56731         4,
  56732         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  56733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56734         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56735         -1,
  56736         -1,
  56737     },
  56738 #endif /* chips */
  56739 
  56740 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  56741     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM56670_A0r */
  56742         soc_block_list[16],
  56743         soc_genreg,
  56744         1,
  56745         0,
  56746         0x2021f00,
  56747         0,
  56748         0,
  56749         9,
  56750         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM53570_A0r_fields,
  56751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56752         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  56753         -1,
  56754         -1,
  56755     },
  56756 #endif /* chips */
  56757 
  56758 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  56759     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  56760     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  56761     defined(BCM_56980_B0)
  56762     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM56960_A0r */
  56763         soc_block_list[16],
  56764         soc_genreg,
  56765         1,
  56766         0,
  56767         0x2021f00,
  56768         0,
  56769         0,
  56770         4,
  56771         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  56772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56773         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56774         -1,
  56775         -1,
  56776         3,
  56777     },
  56778 #endif /* chips */
  56779 
  56780 #if defined(BCM_88270_A0)
  56781     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM88270_A0r */
  56782         soc_block_list[56],
  56783         soc_genreg,
  56784         1,
  56785         0,
  56786         0x2021f00,
  56787         0,
  56788         0,
  56789         4,
  56790         soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88270_A0r_fields,
  56791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56792         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56793         -1,
  56794         -1,
  56795     },
  56796 #endif /* chips */
  56797 
  56798 #if defined(BCM_88375_A0)
  56799     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM88375_A0r */
  56800         soc_block_list[56],
  56801         soc_genreg,
  56802         1,
  56803         0,
  56804         0x2021f00,
  56805         0,
  56806         0,
  56807         4,
  56808         soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88375_A0r_fields,
  56809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56810         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56811         -1,
  56812         -1,
  56813     },
  56814 #endif /* chips */
  56815 
  56816 #if defined(BCM_88375_B0)
  56817     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM88375_B0r */
  56818         soc_block_list[56],
  56819         soc_genreg,
  56820         1,
  56821         0,
  56822         0x2021f00,
  56823         0,
  56824         0,
  56825         4,
  56826         soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88375_B0r_fields,
  56827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56828         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56829         -1,
  56830         -1,
  56831     },
  56832 #endif /* chips */
  56833 
  56834 #if defined(BCM_88470_A0)
  56835     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM88470_A0r */
  56836         soc_block_list[56],
  56837         soc_genreg,
  56838         1,
  56839         0,
  56840         0x2021f00,
  56841         0,
  56842         0,
  56843         4,
  56844         soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88470_A0r_fields,
  56845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56846         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56847         -1,
  56848         -1,
  56849     },
  56850 #endif /* chips */
  56851 
  56852 #if defined(BCM_88470_B0)
  56853     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM88470_B0r */
  56854         soc_block_list[56],
  56855         soc_genreg,
  56856         1,
  56857         0,
  56858         0x2021f00,
  56859         0,
  56860         0,
  56861         4,
  56862         soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88470_B0r_fields,
  56863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56864         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56865         -1,
  56866         -1,
  56867     },
  56868 #endif /* chips */
  56869 
  56870 #if defined(BCM_88675_A0)
  56871     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM88675_A0r */
  56872         soc_block_list[56],
  56873         soc_genreg,
  56874         1,
  56875         0,
  56876         0x2021f00,
  56877         0,
  56878         0,
  56879         4,
  56880         soc_XLPORT_MIB_TSC0_ECC_STATUSr_fields,
  56881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56882         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56883         -1,
  56884         -1,
  56885     },
  56886 #endif /* chips */
  56887 
  56888 #if defined(BCM_88675_B0)
  56889     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM88675_B0r */
  56890         soc_block_list[56],
  56891         soc_genreg,
  56892         1,
  56893         0,
  56894         0x2021f00,
  56895         0,
  56896         0,
  56897         4,
  56898         soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88675_B0r_fields,
  56899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56900         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56901         -1,
  56902         -1,
  56903     },
  56904 #endif /* chips */
  56905 
  56906 #if defined(BCM_88680_A0)
  56907     { /* SOC_REG_INT_XLPORT_MIB_TSC0_ECC_STATUS_BCM88680_A0r */
  56908         soc_block_list[56],
  56909         soc_genreg,
  56910         1,
  56911         0,
  56912         0x2021f00,
  56913         0,
  56914         0,
  56915         4,
  56916         soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88680_A0r_fields,
  56917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56918         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56919         -1,
  56920         -1,
  56921     },
  56922 #endif /* chips */
  56923 
  56924 #if defined(BCM_2801PM_A0)
  56925     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUSr */
  56926         soc_block_list[56],
  56927         soc_genreg,
  56928         1,
  56929         0,
  56930         0x2022000,
  56931         0,
  56932         0,
  56933         4,
  56934         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  56935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56936         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56937         -1,
  56938         -1,
  56939     },
  56940 #endif /* chips */
  56941 
  56942 #if defined(BCM_53400_A0)
  56943     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM53400_A0r */
  56944         soc_block_list[16],
  56945         soc_genreg,
  56946         1,
  56947         0,
  56948         0x2022000,
  56949         0,
  56950         0,
  56951         4,
  56952         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  56953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56954         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56955         -1,
  56956         -1,
  56957     },
  56958 #endif /* chips */
  56959 
  56960 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  56961     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM53570_A0r */
  56962         soc_block_list[16],
  56963         soc_genreg,
  56964         1,
  56965         0,
  56966         0x2022000,
  56967         0,
  56968         0,
  56969         9,
  56970         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM53570_A0r_fields,
  56971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56972         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  56973         -1,
  56974         -1,
  56975     },
  56976 #endif /* chips */
  56977 
  56978 #if defined(BCM_56150_A0)
  56979     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM56150_A0r */
  56980         soc_block_list[16],
  56981         soc_genreg,
  56982         1,
  56983         0,
  56984         0x2022000,
  56985         0,
  56986         0,
  56987         4,
  56988         soc_PGW_MIB_RSC0_ECC_STATUSr_fields,
  56989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56990         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  56991         -1,
  56992         -1,
  56993     },
  56994 #endif /* chips */
  56995 
  56996 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  56997     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM56160_A0r */
  56998         soc_block_list[16],
  56999         soc_genreg,
  57000         1,
  57001         0,
  57002         0x2022000,
  57003         0,
  57004         0,
  57005         4,
  57006         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  57007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57008         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57009         -1,
  57010         -1,
  57011     },
  57012 #endif /* chips */
  57013 
  57014 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57015     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM56260_A0r */
  57016         soc_block_list[16],
  57017         soc_genreg,
  57018         1,
  57019         0,
  57020         0x2022000,
  57021         0,
  57022         0,
  57023         4,
  57024         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  57025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57026         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57027         -1,
  57028         -1,
  57029     },
  57030 #endif /* chips */
  57031 
  57032 #if defined(BCM_56370_A0)
  57033     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM56370_A0r */
  57034         soc_block_list[16],
  57035         soc_genreg,
  57036         1,
  57037         0,
  57038         0x2022000,
  57039         0,
  57040         0,
  57041         4,
  57042         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  57043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57044         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57045         -1,
  57046         -1,
  57047         3,
  57048     },
  57049 #endif /* chips */
  57050 
  57051 #if defined(BCM_56560_A0)
  57052     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM56560_A0r */
  57053         soc_block_list[217],
  57054         soc_genreg,
  57055         1,
  57056         0,
  57057         0x2022000,
  57058         0,
  57059         0,
  57060         4,
  57061         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  57062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57063         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57064         -1,
  57065         -1,
  57066     },
  57067 #endif /* chips */
  57068 
  57069 #if defined(BCM_56560_B0)
  57070     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM56560_B0r */
  57071         soc_block_list[16],
  57072         soc_genreg,
  57073         1,
  57074         0,
  57075         0x2022000,
  57076         0,
  57077         0,
  57078         4,
  57079         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  57080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57081         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57082         -1,
  57083         -1,
  57084     },
  57085 #endif /* chips */
  57086 
  57087 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  57088     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM56670_A0r */
  57089         soc_block_list[16],
  57090         soc_genreg,
  57091         1,
  57092         0,
  57093         0x2022000,
  57094         0,
  57095         0,
  57096         9,
  57097         soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM53570_A0r_fields,
  57098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57099         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  57100         -1,
  57101         -1,
  57102     },
  57103 #endif /* chips */
  57104 
  57105 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  57106     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  57107     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  57108     defined(BCM_56980_B0)
  57109     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM56960_A0r */
  57110         soc_block_list[16],
  57111         soc_genreg,
  57112         1,
  57113         0,
  57114         0x2022000,
  57115         0,
  57116         0,
  57117         4,
  57118         soc_CLPORT_MIB_RSC0_ECC_STATUSr_fields,
  57119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57120         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57121         -1,
  57122         -1,
  57123         3,
  57124     },
  57125 #endif /* chips */
  57126 
  57127 #if defined(BCM_88270_A0)
  57128     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM88270_A0r */
  57129         soc_block_list[56],
  57130         soc_genreg,
  57131         1,
  57132         0,
  57133         0x2022000,
  57134         0,
  57135         0,
  57136         4,
  57137         soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88270_A0r_fields,
  57138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57139         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57140         -1,
  57141         -1,
  57142     },
  57143 #endif /* chips */
  57144 
  57145 #if defined(BCM_88375_A0)
  57146     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM88375_A0r */
  57147         soc_block_list[56],
  57148         soc_genreg,
  57149         1,
  57150         0,
  57151         0x2022000,
  57152         0,
  57153         0,
  57154         4,
  57155         soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88375_A0r_fields,
  57156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57157         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57158         -1,
  57159         -1,
  57160     },
  57161 #endif /* chips */
  57162 
  57163 #if defined(BCM_88375_B0)
  57164     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM88375_B0r */
  57165         soc_block_list[56],
  57166         soc_genreg,
  57167         1,
  57168         0,
  57169         0x2022000,
  57170         0,
  57171         0,
  57172         4,
  57173         soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88375_B0r_fields,
  57174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57175         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57176         -1,
  57177         -1,
  57178     },
  57179 #endif /* chips */
  57180 
  57181 #if defined(BCM_88470_A0)
  57182     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM88470_A0r */
  57183         soc_block_list[56],
  57184         soc_genreg,
  57185         1,
  57186         0,
  57187         0x2022000,
  57188         0,
  57189         0,
  57190         4,
  57191         soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88470_A0r_fields,
  57192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57193         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57194         -1,
  57195         -1,
  57196     },
  57197 #endif /* chips */
  57198 
  57199 #if defined(BCM_88470_B0)
  57200     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM88470_B0r */
  57201         soc_block_list[56],
  57202         soc_genreg,
  57203         1,
  57204         0,
  57205         0x2022000,
  57206         0,
  57207         0,
  57208         4,
  57209         soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88470_B0r_fields,
  57210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57211         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57212         -1,
  57213         -1,
  57214     },
  57215 #endif /* chips */
  57216 
  57217 #if defined(BCM_88675_A0)
  57218     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM88675_A0r */
  57219         soc_block_list[56],
  57220         soc_genreg,
  57221         1,
  57222         0,
  57223         0x2022000,
  57224         0,
  57225         0,
  57226         4,
  57227         soc_XLPORT_MIB_TSC1_ECC_STATUSr_fields,
  57228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57229         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57230         -1,
  57231         -1,
  57232     },
  57233 #endif /* chips */
  57234 
  57235 #if defined(BCM_88675_B0)
  57236     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM88675_B0r */
  57237         soc_block_list[56],
  57238         soc_genreg,
  57239         1,
  57240         0,
  57241         0x2022000,
  57242         0,
  57243         0,
  57244         4,
  57245         soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88675_B0r_fields,
  57246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57247         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57248         -1,
  57249         -1,
  57250     },
  57251 #endif /* chips */
  57252 
  57253 #if defined(BCM_88680_A0)
  57254     { /* SOC_REG_INT_XLPORT_MIB_TSC1_ECC_STATUS_BCM88680_A0r */
  57255         soc_block_list[56],
  57256         soc_genreg,
  57257         1,
  57258         0,
  57259         0x2022000,
  57260         0,
  57261         0,
  57262         4,
  57263         soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88680_A0r_fields,
  57264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57265         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57266         -1,
  57267         -1,
  57268     },
  57269 #endif /* chips */
  57270 
  57271 #if defined(BCM_56840_A0)
  57272     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM0_ECC_STATUSr */
  57273         soc_block_list[16],
  57274         soc_genreg,
  57275         1,
  57276         0,
  57277         0x8024d,
  57278         0,
  57279         0,
  57280         4,
  57281         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57283         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57284         -1,
  57285         -1,
  57286     },
  57287 #endif /* chips */
  57288 
  57289 #if defined(BCM_56840_B0)
  57290     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM0_ECC_STATUS_BCM56840_B0r */
  57291         soc_block_list[16],
  57292         soc_genreg,
  57293         1,
  57294         0,
  57295         0x8024d,
  57296         0,
  57297         0,
  57298         4,
  57299         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57301         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57302         -1,
  57303         -1,
  57304     },
  57305 #endif /* chips */
  57306 
  57307 #if defined(BCM_88732_A0)
  57308     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM0_ECC_STATUS_BCM88732_A0r */
  57309         soc_block_list[16],
  57310         soc_genreg,
  57311         1,
  57312         0,
  57313         0x8024d,
  57314         0,
  57315         0,
  57316         4,
  57317         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57319         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57320         -1,
  57321         -1,
  57322     },
  57323 #endif /* chips */
  57324 
  57325 #if defined(BCM_56840_A0)
  57326     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM1_ECC_STATUSr */
  57327         soc_block_list[16],
  57328         soc_genreg,
  57329         1,
  57330         0,
  57331         0x8024c,
  57332         0,
  57333         0,
  57334         4,
  57335         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57337         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57338         -1,
  57339         -1,
  57340     },
  57341 #endif /* chips */
  57342 
  57343 #if defined(BCM_56840_B0)
  57344     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM1_ECC_STATUS_BCM56840_B0r */
  57345         soc_block_list[16],
  57346         soc_genreg,
  57347         1,
  57348         0,
  57349         0x8024c,
  57350         0,
  57351         0,
  57352         4,
  57353         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57355         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57356         -1,
  57357         -1,
  57358     },
  57359 #endif /* chips */
  57360 
  57361 #if defined(BCM_88732_A0)
  57362     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM1_ECC_STATUS_BCM88732_A0r */
  57363         soc_block_list[16],
  57364         soc_genreg,
  57365         1,
  57366         0,
  57367         0x8024c,
  57368         0,
  57369         0,
  57370         4,
  57371         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57373         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57374         -1,
  57375         -1,
  57376     },
  57377 #endif /* chips */
  57378 
  57379 #if defined(BCM_56840_A0)
  57380     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM2_ECC_STATUSr */
  57381         soc_block_list[16],
  57382         soc_genreg,
  57383         1,
  57384         0,
  57385         0x8024b,
  57386         0,
  57387         0,
  57388         4,
  57389         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57391         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57392         -1,
  57393         -1,
  57394     },
  57395 #endif /* chips */
  57396 
  57397 #if defined(BCM_56840_B0)
  57398     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM2_ECC_STATUS_BCM56840_B0r */
  57399         soc_block_list[16],
  57400         soc_genreg,
  57401         1,
  57402         0,
  57403         0x8024b,
  57404         0,
  57405         0,
  57406         4,
  57407         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57409         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57410         -1,
  57411         -1,
  57412     },
  57413 #endif /* chips */
  57414 
  57415 #if defined(BCM_88732_A0)
  57416     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM2_ECC_STATUS_BCM88732_A0r */
  57417         soc_block_list[16],
  57418         soc_genreg,
  57419         1,
  57420         0,
  57421         0x8024b,
  57422         0,
  57423         0,
  57424         4,
  57425         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57427         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57428         -1,
  57429         -1,
  57430     },
  57431 #endif /* chips */
  57432 
  57433 #if defined(BCM_56840_A0)
  57434     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM3_ECC_STATUSr */
  57435         soc_block_list[16],
  57436         soc_genreg,
  57437         1,
  57438         0,
  57439         0x8024a,
  57440         0,
  57441         0,
  57442         4,
  57443         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57445         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57446         -1,
  57447         -1,
  57448     },
  57449 #endif /* chips */
  57450 
  57451 #if defined(BCM_56840_B0)
  57452     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM3_ECC_STATUS_BCM56840_B0r */
  57453         soc_block_list[16],
  57454         soc_genreg,
  57455         1,
  57456         0,
  57457         0x8024a,
  57458         0,
  57459         0,
  57460         4,
  57461         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57463         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57464         -1,
  57465         -1,
  57466     },
  57467 #endif /* chips */
  57468 
  57469 #if defined(BCM_88732_A0)
  57470     { /* SOC_REG_INT_XLPORT_MIB_TSC_MEM3_ECC_STATUS_BCM88732_A0r */
  57471         soc_block_list[16],
  57472         soc_genreg,
  57473         1,
  57474         0,
  57475         0x8024a,
  57476         0,
  57477         0,
  57478         4,
  57479         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  57480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57481         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  57482         -1,
  57483         -1,
  57484     },
  57485 #endif /* chips */
  57486 
  57487 #if defined(BCM_2801PM_A0)
  57488     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROLr */
  57489         soc_block_list[56],
  57490         soc_genreg,
  57491         1,
  57492         0,
  57493         0x2022100,
  57494         0,
  57495         0,
  57496         4,
  57497         soc_CLPORT_MIB_TSC_RAM_CONTROLr_fields,
  57498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57499         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57500         -1,
  57501         -1,
  57502     },
  57503 #endif /* chips */
  57504 
  57505 #if defined(BCM_53400_A0)
  57506     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM53400_A0r */
  57507         soc_block_list[16],
  57508         soc_genreg,
  57509         1,
  57510         0,
  57511         0x2022100,
  57512         0,
  57513         0,
  57514         4,
  57515         soc_CLPORT_MIB_TSC_RAM_CONTROLr_fields,
  57516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57517         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57518         -1,
  57519         -1,
  57520     },
  57521 #endif /* chips */
  57522 
  57523 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  57524     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM53570_A0r */
  57525         soc_block_list[16],
  57526         soc_genreg,
  57527         1,
  57528         0,
  57529         0x2022100,
  57530         0,
  57531         0,
  57532         4,
  57533         soc_CLPORT_MIB_TSC_RAM_CONTROL_BCM56965_A0r_fields,
  57534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57535         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  57536         -1,
  57537         -1,
  57538     },
  57539 #endif /* chips */
  57540 
  57541 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  57542     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM56160_A0r */
  57543         soc_block_list[16],
  57544         soc_genreg,
  57545         1,
  57546         0,
  57547         0x2022100,
  57548         0,
  57549         0,
  57550         4,
  57551         soc_CLPORT_MIB_TSC_RAM_CONTROLr_fields,
  57552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57553         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57554         -1,
  57555         -1,
  57556     },
  57557 #endif /* chips */
  57558 
  57559 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  57560     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM56260_A0r */
  57561         soc_block_list[16],
  57562         soc_genreg,
  57563         1,
  57564         0,
  57565         0x2022100,
  57566         0,
  57567         0,
  57568         4,
  57569         soc_CLPORT_MIB_TSC_RAM_CONTROLr_fields,
  57570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57571         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57572         -1,
  57573         -1,
  57574     },
  57575 #endif /* chips */
  57576 
  57577 #if defined(BCM_56370_A0)
  57578     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM56370_A0r */
  57579         soc_block_list[16],
  57580         soc_genreg,
  57581         1,
  57582         0,
  57583         0x2022100,
  57584         0,
  57585         0,
  57586         4,
  57587         soc_CLPORT_MIB_TSC_RAM_CONTROL_BCM56965_A0r_fields,
  57588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57589         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  57590         -1,
  57591         -1,
  57592         3,
  57593     },
  57594 #endif /* chips */
  57595 
  57596 #if defined(BCM_56560_A0)
  57597     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM56560_A0r */
  57598         soc_block_list[217],
  57599         soc_genreg,
  57600         1,
  57601         0,
  57602         0x2022100,
  57603         0,
  57604         0,
  57605         4,
  57606         soc_CLPORT_MIB_TSC_RAM_CONTROLr_fields,
  57607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57608         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57609         -1,
  57610         -1,
  57611     },
  57612 #endif /* chips */
  57613 
  57614 #if defined(BCM_56560_B0)
  57615     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM56560_B0r */
  57616         soc_block_list[16],
  57617         soc_genreg,
  57618         1,
  57619         0,
  57620         0x2022100,
  57621         0,
  57622         0,
  57623         4,
  57624         soc_CLPORT_MIB_TSC_RAM_CONTROLr_fields,
  57625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57626         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57627         -1,
  57628         -1,
  57629     },
  57630 #endif /* chips */
  57631 
  57632 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  57633     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM56670_A0r */
  57634         soc_block_list[16],
  57635         soc_genreg,
  57636         1,
  57637         0,
  57638         0x2022100,
  57639         0,
  57640         0,
  57641         4,
  57642         soc_CLPORT_MIB_TSC_RAM_CONTROL_BCM56965_A0r_fields,
  57643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57644         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  57645         -1,
  57646         -1,
  57647     },
  57648 #endif /* chips */
  57649 
  57650 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  57651     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM56960_A0r */
  57652         soc_block_list[16],
  57653         soc_genreg,
  57654         1,
  57655         0,
  57656         0x2022100,
  57657         0,
  57658         0,
  57659         4,
  57660         soc_CLPORT_MIB_TSC_RAM_CONTROLr_fields,
  57661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57662         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57663         -1,
  57664         -1,
  57665         3,
  57666     },
  57667 #endif /* chips */
  57668 
  57669 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  57670     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  57671     defined(BCM_56980_B0)
  57672     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM56970_A0r */
  57673         soc_block_list[16],
  57674         soc_genreg,
  57675         1,
  57676         0,
  57677         0x2022100,
  57678         0,
  57679         0,
  57680         4,
  57681         soc_CLPORT_MIB_TSC_RAM_CONTROL_BCM56965_A0r_fields,
  57682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57683         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  57684         -1,
  57685         -1,
  57686         3,
  57687     },
  57688 #endif /* chips */
  57689 
  57690 #if defined(BCM_88270_A0)
  57691     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM88270_A0r */
  57692         soc_block_list[56],
  57693         soc_genreg,
  57694         1,
  57695         0,
  57696         0x2022100,
  57697         0,
  57698         0,
  57699         4,
  57700         soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88270_A0r_fields,
  57701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57702         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57703         -1,
  57704         -1,
  57705     },
  57706 #endif /* chips */
  57707 
  57708 #if defined(BCM_88375_A0)
  57709     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM88375_A0r */
  57710         soc_block_list[56],
  57711         soc_genreg,
  57712         1,
  57713         0,
  57714         0x2022100,
  57715         0,
  57716         0,
  57717         4,
  57718         soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88375_A0r_fields,
  57719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57720         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57721         -1,
  57722         -1,
  57723     },
  57724 #endif /* chips */
  57725 
  57726 #if defined(BCM_88375_B0)
  57727     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM88375_B0r */
  57728         soc_block_list[56],
  57729         soc_genreg,
  57730         1,
  57731         0,
  57732         0x2022100,
  57733         0,
  57734         0,
  57735         4,
  57736         soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88375_B0r_fields,
  57737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57738         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57739         -1,
  57740         -1,
  57741     },
  57742 #endif /* chips */
  57743 
  57744 #if defined(BCM_88470_A0)
  57745     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM88470_A0r */
  57746         soc_block_list[56],
  57747         soc_genreg,
  57748         1,
  57749         0,
  57750         0x2022100,
  57751         0,
  57752         0,
  57753         4,
  57754         soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88470_A0r_fields,
  57755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57756         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57757         -1,
  57758         -1,
  57759     },
  57760 #endif /* chips */
  57761 
  57762 #if defined(BCM_88470_B0)
  57763     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM88470_B0r */
  57764         soc_block_list[56],
  57765         soc_genreg,
  57766         1,
  57767         0,
  57768         0x2022100,
  57769         0,
  57770         0,
  57771         4,
  57772         soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88470_B0r_fields,
  57773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57774         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57775         -1,
  57776         -1,
  57777     },
  57778 #endif /* chips */
  57779 
  57780 #if defined(BCM_88675_A0)
  57781     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM88675_A0r */
  57782         soc_block_list[56],
  57783         soc_genreg,
  57784         1,
  57785         0,
  57786         0x2022100,
  57787         0,
  57788         0,
  57789         4,
  57790         soc_XLPORT_MIB_TSC_RAM_CONTROLr_fields,
  57791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57792         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57793         -1,
  57794         -1,
  57795     },
  57796 #endif /* chips */
  57797 
  57798 #if defined(BCM_88675_B0)
  57799     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM88675_B0r */
  57800         soc_block_list[56],
  57801         soc_genreg,
  57802         1,
  57803         0,
  57804         0x2022100,
  57805         0,
  57806         0,
  57807         4,
  57808         soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88675_B0r_fields,
  57809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57810         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57811         -1,
  57812         -1,
  57813     },
  57814 #endif /* chips */
  57815 
  57816 #if defined(BCM_88680_A0)
  57817     { /* SOC_REG_INT_XLPORT_MIB_TSC_RAM_CONTROL_BCM88680_A0r */
  57818         soc_block_list[56],
  57819         soc_genreg,
  57820         1,
  57821         0,
  57822         0x2022100,
  57823         0,
  57824         0,
  57825         4,
  57826         soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88680_A0r_fields,
  57827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57828         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  57829         -1,
  57830         -1,
  57831     },
  57832 #endif /* chips */
  57833 
  57834 #if defined(BCM_56840_A0)
  57835     { /* SOC_REG_INT_XLPORT_MODE_REGr */
  57836         soc_block_list[16],
  57837         soc_genreg,
  57838         1,
  57839         0,
  57840         0x80229,
  57841         0,
  57842         0,
  57843         6,
  57844         soc_XLPORT_MODE_REGr_fields,
  57845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57846         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57847         -1,
  57848         -1,
  57849     },
  57850 #endif /* chips */
  57851 
  57852 #if defined(BCM_2801PM_A0)
  57853     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM2801PM_A0r */
  57854         soc_block_list[56],
  57855         soc_genreg,
  57856         1,
  57857         0,
  57858         0x2020a00,
  57859         0,
  57860         0,
  57861         6,
  57862         soc_XLPORT_MODE_REG_BCM2801PM_A0r_fields,
  57863         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  57864         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57865         -1,
  57866         -1,
  57867     },
  57868 #endif /* chips */
  57869 
  57870 #if defined(BCM_53400_A0)
  57871     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM53400_A0r */
  57872         soc_block_list[16],
  57873         soc_genreg,
  57874         1,
  57875         0,
  57876         0x2020a00,
  57877         0,
  57878         0,
  57879         6,
  57880         soc_XLPORT_MODE_REG_BCM53400_A0r_fields,
  57881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57882         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57883         -1,
  57884         -1,
  57885     },
  57886 #endif /* chips */
  57887 
  57888 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  57889     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM53570_A0r */
  57890         soc_block_list[16],
  57891         soc_genreg,
  57892         1,
  57893         0,
  57894         0x2020a00,
  57895         0,
  57896         0,
  57897         6,
  57898         soc_XLPORT_MODE_REG_BCM56970_A0r_fields,
  57899         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  57900         SOC_RESET_MASK_DEC(0x000002ff, 0x00000000)
  57901         -1,
  57902         -1,
  57903     },
  57904 #endif /* chips */
  57905 
  57906 #if defined(BCM_56150_A0)
  57907     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56150_A0r */
  57908         soc_block_list[16],
  57909         soc_genreg,
  57910         1,
  57911         0,
  57912         0x2020a00,
  57913         0,
  57914         0,
  57915         5,
  57916         soc_XLPORT_MODE_REG_BCM56150_A0r_fields,
  57917         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  57918         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57919         -1,
  57920         -1,
  57921     },
  57922 #endif /* chips */
  57923 
  57924 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  57925     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56160_A0r */
  57926         soc_block_list[16],
  57927         soc_genreg,
  57928         1,
  57929         0,
  57930         0x2020a00,
  57931         0,
  57932         0,
  57933         6,
  57934         soc_XLPORT_MODE_REG_BCM56960_A0r_fields,
  57935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57936         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57937         -1,
  57938         -1,
  57939     },
  57940 #endif /* chips */
  57941 
  57942 #if defined(BCM_56260_A0)
  57943     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56260_A0r */
  57944         soc_block_list[16],
  57945         soc_genreg,
  57946         1,
  57947         0,
  57948         0x2020a00,
  57949         0,
  57950         0,
  57951         6,
  57952         soc_XLPORT_MODE_REG_BCM53400_A0r_fields,
  57953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57954         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57955         -1,
  57956         -1,
  57957     },
  57958 #endif /* chips */
  57959 
  57960 #if defined(BCM_56260_B0)
  57961     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56260_B0r */
  57962         soc_block_list[16],
  57963         soc_genreg,
  57964         1,
  57965         0,
  57966         0x2020a00,
  57967         0,
  57968         0,
  57969         6,
  57970         soc_XLPORT_MODE_REG_BCM56960_A0r_fields,
  57971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57972         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57973         -1,
  57974         -1,
  57975     },
  57976 #endif /* chips */
  57977 
  57978 #if defined(BCM_56370_A0)
  57979     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56370_A0r */
  57980         soc_block_list[16],
  57981         soc_genreg,
  57982         1,
  57983         0,
  57984         0x2020a00,
  57985         0,
  57986         0,
  57987         6,
  57988         soc_XLPORT_MODE_REG_BCM56970_A0r_fields,
  57989         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  57990         SOC_RESET_MASK_DEC(0x000002ff, 0x00000000)
  57991         -1,
  57992         -1,
  57993         3,
  57994     },
  57995 #endif /* chips */
  57996 
  57997 #if defined(BCM_56560_A0)
  57998     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56560_A0r */
  57999         soc_block_list[217],
  58000         soc_genreg,
  58001         1,
  58002         0,
  58003         0x2020a00,
  58004         0,
  58005         0,
  58006         6,
  58007         soc_XLPORT_MODE_REG_BCM56960_A0r_fields,
  58008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58009         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  58010         -1,
  58011         -1,
  58012     },
  58013 #endif /* chips */
  58014 
  58015 #if defined(BCM_56560_B0)
  58016     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56560_B0r */
  58017         soc_block_list[16],
  58018         soc_genreg,
  58019         1,
  58020         0,
  58021         0x2020a00,
  58022         0,
  58023         0,
  58024         6,
  58025         soc_XLPORT_MODE_REG_BCM56960_A0r_fields,
  58026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58027         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  58028         -1,
  58029         -1,
  58030     },
  58031 #endif /* chips */
  58032 
  58033 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  58034     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56670_A0r */
  58035         soc_block_list[16],
  58036         soc_genreg,
  58037         1,
  58038         0,
  58039         0x2020a00,
  58040         0,
  58041         0,
  58042         6,
  58043         soc_XLPORT_MODE_REG_BCM56970_A0r_fields,
  58044         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  58045         SOC_RESET_MASK_DEC(0x000002ff, 0x00000000)
  58046         -1,
  58047         -1,
  58048     },
  58049 #endif /* chips */
  58050 
  58051 #if defined(BCM_56840_B0)
  58052     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56840_B0r */
  58053         soc_block_list[16],
  58054         soc_genreg,
  58055         1,
  58056         0,
  58057         0x80229,
  58058         0,
  58059         0,
  58060         6,
  58061         soc_XLPORT_MODE_REGr_fields,
  58062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58063         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  58064         -1,
  58065         -1,
  58066     },
  58067 #endif /* chips */
  58068 
  58069 #if defined(BCM_56850_A0)
  58070     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56850_A0r */
  58071         soc_block_list[16],
  58072         soc_genreg,
  58073         1,
  58074         0,
  58075         0x2020600,
  58076         0,
  58077         0,
  58078         2,
  58079         soc_XLPORT_MODE_REG_BCM56850_A0r_fields,
  58080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58081         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58082         -1,
  58083         -1,
  58084     },
  58085 #endif /* chips */
  58086 
  58087 #if defined(BCM_56860_A0)
  58088     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56860_A0r */
  58089         soc_block_list[16],
  58090         soc_genreg,
  58091         1,
  58092         0,
  58093         0x2020600,
  58094         0,
  58095         0,
  58096         4,
  58097         soc_XLPORT_MODE_REG_BCM56860_A0r_fields,
  58098         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  58099         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  58100         -1,
  58101         -1,
  58102     },
  58103 #endif /* chips */
  58104 
  58105 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  58106     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56960_A0r */
  58107         soc_block_list[16],
  58108         soc_genreg,
  58109         1,
  58110         0,
  58111         0x2020a00,
  58112         0,
  58113         0,
  58114         6,
  58115         soc_XLPORT_MODE_REG_BCM56960_A0r_fields,
  58116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58117         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  58118         -1,
  58119         -1,
  58120         3,
  58121     },
  58122 #endif /* chips */
  58123 
  58124 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  58125     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  58126     defined(BCM_56980_B0)
  58127     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM56970_A0r */
  58128         soc_block_list[16],
  58129         soc_genreg,
  58130         1,
  58131         0,
  58132         0x2020a00,
  58133         0,
  58134         0,
  58135         6,
  58136         soc_XLPORT_MODE_REG_BCM56970_A0r_fields,
  58137         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  58138         SOC_RESET_MASK_DEC(0x000002ff, 0x00000000)
  58139         -1,
  58140         -1,
  58141         3,
  58142     },
  58143 #endif /* chips */
  58144 
  58145 #if defined(BCM_88270_A0)
  58146     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM88270_A0r */
  58147         soc_block_list[56],
  58148         soc_genreg,
  58149         1,
  58150         0,
  58151         0x2020a00,
  58152         0,
  58153         0,
  58154         6,
  58155         soc_XLPORT_MODE_REG_BCM88270_A0r_fields,
  58156         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  58157         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58158         -1,
  58159         -1,
  58160     },
  58161 #endif /* chips */
  58162 
  58163 #if defined(BCM_88375_A0)
  58164     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM88375_A0r */
  58165         soc_block_list[56],
  58166         soc_genreg,
  58167         1,
  58168         0,
  58169         0x2020a00,
  58170         0,
  58171         0,
  58172         6,
  58173         soc_XLPORT_MODE_REG_BCM88375_A0r_fields,
  58174         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  58175         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58176         -1,
  58177         -1,
  58178     },
  58179 #endif /* chips */
  58180 
  58181 #if defined(BCM_88375_B0)
  58182     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM88375_B0r */
  58183         soc_block_list[56],
  58184         soc_genreg,
  58185         1,
  58186         0,
  58187         0x2020a00,
  58188         0,
  58189         0,
  58190         6,
  58191         soc_XLPORT_MODE_REG_BCM88375_B0r_fields,
  58192         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  58193         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58194         -1,
  58195         -1,
  58196     },
  58197 #endif /* chips */
  58198 
  58199 #if defined(BCM_88470_A0)
  58200     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM88470_A0r */
  58201         soc_block_list[56],
  58202         soc_genreg,
  58203         1,
  58204         0,
  58205         0x2020a00,
  58206         0,
  58207         0,
  58208         6,
  58209         soc_XLPORT_MODE_REG_BCM88470_A0r_fields,
  58210         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  58211         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58212         -1,
  58213         -1,
  58214     },
  58215 #endif /* chips */
  58216 
  58217 #if defined(BCM_88470_B0)
  58218     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM88470_B0r */
  58219         soc_block_list[56],
  58220         soc_genreg,
  58221         1,
  58222         0,
  58223         0x2020a00,
  58224         0,
  58225         0,
  58226         6,
  58227         soc_XLPORT_MODE_REG_BCM88470_B0r_fields,
  58228         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  58229         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58230         -1,
  58231         -1,
  58232     },
  58233 #endif /* chips */
  58234 
  58235 #if defined(BCM_88675_A0)
  58236     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM88675_A0r */
  58237         soc_block_list[56],
  58238         soc_genreg,
  58239         1,
  58240         0,
  58241         0x2020a00,
  58242         0,
  58243         0,
  58244         6,
  58245         soc_XLPORT_MODE_REG_BCM88675_A0r_fields,
  58246         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  58247         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58248         -1,
  58249         -1,
  58250     },
  58251 #endif /* chips */
  58252 
  58253 #if defined(BCM_88675_B0)
  58254     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM88675_B0r */
  58255         soc_block_list[56],
  58256         soc_genreg,
  58257         1,
  58258         0,
  58259         0x2020a00,
  58260         0,
  58261         0,
  58262         6,
  58263         soc_XLPORT_MODE_REG_BCM88675_B0r_fields,
  58264         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  58265         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58266         -1,
  58267         -1,
  58268     },
  58269 #endif /* chips */
  58270 
  58271 #if defined(BCM_88680_A0)
  58272     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM88680_A0r */
  58273         soc_block_list[56],
  58274         soc_genreg,
  58275         1,
  58276         0,
  58277         0x2020a00,
  58278         0,
  58279         0,
  58280         6,
  58281         soc_XLPORT_MODE_REG_BCM88680_A0r_fields,
  58282         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  58283         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58284         -1,
  58285         -1,
  58286     },
  58287 #endif /* chips */
  58288 
  58289 #if defined(BCM_88732_A0)
  58290     { /* SOC_REG_INT_XLPORT_MODE_REG_BCM88732_A0r */
  58291         soc_block_list[16],
  58292         soc_genreg,
  58293         1,
  58294         0,
  58295         0x80229,
  58296         0,
  58297         0,
  58298         6,
  58299         soc_XLPORT_MODE_REGr_fields,
  58300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58301         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  58302         -1,
  58303         -1,
  58304     },
  58305 #endif /* chips */
  58306 
  58307 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  58308     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  58309     defined(BCM_56980_B0)
  58310     { /* SOC_REG_INT_XLPORT_PMD_PLL_CTRL_CONFIGr */
  58311         soc_block_list[16],
  58312         soc_genreg,
  58313         1,
  58314         0,
  58315         0x2022c00,
  58316         0,
  58317         0,
  58318         3,
  58319         soc_XLPORT_PMD_PLL_CTRL_CONFIGr_fields,
  58320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58321         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  58322         -1,
  58323         -1,
  58324         3,
  58325     },
  58326 #endif /* chips */
  58327 
  58328 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  58329     { /* SOC_REG_INT_XLPORT_PMD_PLL_CTRL_CONFIG_BCM53570_A0r */
  58330         soc_block_list[16],
  58331         soc_genreg,
  58332         1,
  58333         0,
  58334         0x2022c00,
  58335         0,
  58336         0,
  58337         3,
  58338         soc_XLPORT_PMD_PLL_CTRL_CONFIGr_fields,
  58339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58340         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  58341         -1,
  58342         -1,
  58343     },
  58344 #endif /* chips */
  58345 
  58346 #if defined(BCM_56370_A0)
  58347     { /* SOC_REG_INT_XLPORT_PMD_PLL_CTRL_CONFIG_BCM56370_A0r */
  58348         soc_block_list[16],
  58349         soc_genreg,
  58350         1,
  58351         0,
  58352         0x2022c00,
  58353         0,
  58354         0,
  58355         3,
  58356         soc_XLPORT_PMD_PLL_CTRL_CONFIGr_fields,
  58357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58358         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  58359         -1,
  58360         -1,
  58361         3,
  58362     },
  58363 #endif /* chips */
  58364 
  58365 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  58366     { /* SOC_REG_INT_XLPORT_PMD_PLL_CTRL_CONFIG_BCM56670_A0r */
  58367         soc_block_list[16],
  58368         soc_genreg,
  58369         1,
  58370         0,
  58371         0x2022c00,
  58372         0,
  58373         0,
  58374         3,
  58375         soc_XLPORT_PMD_PLL_CTRL_CONFIGr_fields,
  58376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58377         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  58378         -1,
  58379         -1,
  58380     },
  58381 #endif /* chips */
  58382 
  58383 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  58384     defined(BCM_56970_A0)
  58385     { /* SOC_REG_INT_XLPORT_PM_VERSION_IDr */
  58386         soc_block_list[16],
  58387         soc_genreg,
  58388         1,
  58389         0,
  58390         0x2022d00,
  58391         SOC_REG_FLAG_RO,
  58392         0,
  58393         5,
  58394         soc_XLPORT_PM_VERSION_IDr_fields,
  58395         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  58396         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  58397         -1,
  58398         -1,
  58399         3,
  58400     },
  58401 #endif /* chips */
  58402 
  58403 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  58404     { /* SOC_REG_INT_XLPORT_PM_VERSION_ID_BCM53570_A0r */
  58405         soc_block_list[16],
  58406         soc_genreg,
  58407         1,
  58408         0,
  58409         0x2022d00,
  58410         SOC_REG_FLAG_RO,
  58411         0,
  58412         5,
  58413         soc_XLPORT_PM_VERSION_ID_BCM53570_A0r_fields,
  58414         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  58415         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  58416         -1,
  58417         -1,
  58418     },
  58419 #endif /* chips */
  58420 
  58421 #if defined(BCM_56370_A0)
  58422     { /* SOC_REG_INT_XLPORT_PM_VERSION_ID_BCM56370_A0r */
  58423         soc_block_list[16],
  58424         soc_genreg,
  58425         1,
  58426         0,
  58427         0x2022d00,
  58428         SOC_REG_FLAG_RO,
  58429         0,
  58430         5,
  58431         soc_XLPORT_PM_VERSION_ID_BCM56980_A0r_fields,
  58432         SOC_RESET_VAL_DEC(0x00000410, 0x00000000)
  58433         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  58434         -1,
  58435         -1,
  58436         3,
  58437     },
  58438 #endif /* chips */
  58439 
  58440 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  58441     { /* SOC_REG_INT_XLPORT_PM_VERSION_ID_BCM56670_A0r */
  58442         soc_block_list[16],
  58443         soc_genreg,
  58444         1,
  58445         0,
  58446         0x2022d00,
  58447         SOC_REG_FLAG_RO,
  58448         0,
  58449         5,
  58450         soc_XLPORT_PM_VERSION_ID_BCM53570_A0r_fields,
  58451         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  58452         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  58453         -1,
  58454         -1,
  58455     },
  58456 #endif /* chips */
  58457 
  58458 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  58459     { /* SOC_REG_INT_XLPORT_PM_VERSION_ID_BCM56980_A0r */
  58460         soc_block_list[16],
  58461         soc_genreg,
  58462         1,
  58463         0,
  58464         0x2022d00,
  58465         SOC_REG_FLAG_RO,
  58466         0,
  58467         5,
  58468         soc_XLPORT_PM_VERSION_ID_BCM56980_A0r_fields,
  58469         SOC_RESET_VAL_DEC(0x00000410, 0x00000000)
  58470         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  58471         -1,
  58472         -1,
  58473         3,
  58474     },
  58475 #endif /* chips */
  58476 
  58477 #if defined(BCM_56840_A0)
  58478     { /* SOC_REG_INT_XLPORT_PORT_ENABLEr */
  58479         soc_block_list[16],
  58480         soc_genreg,
  58481         1,
  58482         0,
  58483         0x8022a,
  58484         0,
  58485         0,
  58486         4,
  58487         soc_XLPORT_PORT_ENABLEr_fields,
  58488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58489         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  58490         -1,
  58491         -1,
  58492     },
  58493 #endif /* chips */
  58494 
  58495 #if defined(BCM_56840_B0)
  58496     { /* SOC_REG_INT_XLPORT_PORT_ENABLE_BCM56840_B0r */
  58497         soc_block_list[16],
  58498         soc_genreg,
  58499         1,
  58500         0,
  58501         0x8022a,
  58502         0,
  58503         0,
  58504         4,
  58505         soc_XLPORT_PORT_ENABLEr_fields,
  58506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58507         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  58508         -1,
  58509         -1,
  58510     },
  58511 #endif /* chips */
  58512 
  58513 #if defined(BCM_88732_A0)
  58514     { /* SOC_REG_INT_XLPORT_PORT_ENABLE_BCM88732_A0r */
  58515         soc_block_list[16],
  58516         soc_genreg,
  58517         1,
  58518         0,
  58519         0x8022a,
  58520         0,
  58521         0,
  58522         4,
  58523         soc_XLPORT_PORT_ENABLEr_fields,
  58524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58525         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  58526         -1,
  58527         -1,
  58528     },
  58529 #endif /* chips */
  58530 
  58531 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  58532     { /* SOC_REG_INT_XLPORT_PORT_SPARE0r */
  58533         soc_block_list[16],
  58534         soc_portreg,
  58535         1,
  58536         0,
  58537         0x23600,
  58538         0,
  58539         0,
  58540         1,
  58541         soc_XLPORT_PORT_SPARE0r_fields,
  58542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58543         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58544         -1,
  58545         -1,
  58546     },
  58547 #endif /* chips */
  58548 
  58549 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  58550     { /* SOC_REG_INT_XLPORT_PORT_SPARE1r */
  58551         soc_block_list[16],
  58552         soc_portreg,
  58553         1,
  58554         0,
  58555         0x23700,
  58556         0,
  58557         0,
  58558         1,
  58559         soc_XLPORT_PORT_SPARE0r_fields,
  58560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58562         -1,
  58563         -1,
  58564     },
  58565 #endif /* chips */
  58566 
  58567 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  58568     { /* SOC_REG_INT_XLPORT_PORT_SPARE2r */
  58569         soc_block_list[16],
  58570         soc_portreg,
  58571         1,
  58572         0,
  58573         0x23800,
  58574         0,
  58575         0,
  58576         1,
  58577         soc_XLPORT_PORT_SPARE0r_fields,
  58578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58579         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58580         -1,
  58581         -1,
  58582     },
  58583 #endif /* chips */
  58584 
  58585 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  58586     { /* SOC_REG_INT_XLPORT_PORT_SPARE3r */
  58587         soc_block_list[16],
  58588         soc_portreg,
  58589         1,
  58590         0,
  58591         0x23900,
  58592         0,
  58593         0,
  58594         1,
  58595         soc_XLPORT_PORT_SPARE0r_fields,
  58596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58598         -1,
  58599         -1,
  58600     },
  58601 #endif /* chips */
  58602 
  58603 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  58604     { /* SOC_REG_INT_XLPORT_PORT_SPARE0_BCM56670_A0r */
  58605         soc_block_list[16],
  58606         soc_portreg,
  58607         1,
  58608         0,
  58609         0x23600,
  58610         0,
  58611         0,
  58612         1,
  58613         soc_XLPORT_PORT_SPARE0r_fields,
  58614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58616         -1,
  58617         -1,
  58618     },
  58619 #endif /* chips */
  58620 
  58621 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  58622     { /* SOC_REG_INT_XLPORT_PORT_SPARE1_BCM56670_A0r */
  58623         soc_block_list[16],
  58624         soc_portreg,
  58625         1,
  58626         0,
  58627         0x23700,
  58628         0,
  58629         0,
  58630         1,
  58631         soc_XLPORT_PORT_SPARE0r_fields,
  58632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58634         -1,
  58635         -1,
  58636     },
  58637 #endif /* chips */
  58638 
  58639 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  58640     { /* SOC_REG_INT_XLPORT_PORT_SPARE2_BCM56670_A0r */
  58641         soc_block_list[16],
  58642         soc_portreg,
  58643         1,
  58644         0,
  58645         0x23800,
  58646         0,
  58647         0,
  58648         1,
  58649         soc_XLPORT_PORT_SPARE0r_fields,
  58650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58652         -1,
  58653         -1,
  58654     },
  58655 #endif /* chips */
  58656 
  58657 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  58658     { /* SOC_REG_INT_XLPORT_PORT_SPARE3_BCM56670_A0r */
  58659         soc_block_list[16],
  58660         soc_portreg,
  58661         1,
  58662         0,
  58663         0x23900,
  58664         0,
  58665         0,
  58666         1,
  58667         soc_XLPORT_PORT_SPARE0r_fields,
  58668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58670         -1,
  58671         -1,
  58672     },
  58673 #endif /* chips */
  58674 
  58675 #if defined(BCM_2801PM_A0)
  58676     { /* SOC_REG_INT_XLPORT_POWER_SAVEr */
  58677         soc_block_list[56],
  58678         soc_genreg,
  58679         1,
  58680         0,
  58681         0x2020d00,
  58682         0,
  58683         0,
  58684         1,
  58685         soc_CLPORT_POWER_SAVEr_fields,
  58686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58687         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58688         -1,
  58689         -1,
  58690     },
  58691 #endif /* chips */
  58692 
  58693 #if defined(BCM_53400_A0)
  58694     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM53400_A0r */
  58695         soc_block_list[16],
  58696         soc_genreg,
  58697         1,
  58698         0,
  58699         0x2020d00,
  58700         0,
  58701         0,
  58702         1,
  58703         soc_XLPORT_POWER_SAVE_BCM53400_A0r_fields,
  58704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58706         -1,
  58707         -1,
  58708     },
  58709 #endif /* chips */
  58710 
  58711 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  58712     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM53570_A0r */
  58713         soc_block_list[16],
  58714         soc_genreg,
  58715         1,
  58716         0,
  58717         0x2020d00,
  58718         0,
  58719         0,
  58720         1,
  58721         soc_XLPORT_POWER_SAVE_BCM53400_A0r_fields,
  58722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58723         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58724         -1,
  58725         -1,
  58726     },
  58727 #endif /* chips */
  58728 
  58729 #if defined(BCM_56150_A0)
  58730     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM56150_A0r */
  58731         soc_block_list[16],
  58732         soc_genreg,
  58733         1,
  58734         0,
  58735         0x2020d00,
  58736         0,
  58737         0,
  58738         1,
  58739         soc_XLPORT_POWER_SAVE_BCM56850_A0r_fields,
  58740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58741         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58742         -1,
  58743         -1,
  58744     },
  58745 #endif /* chips */
  58746 
  58747 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  58748     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM56160_A0r */
  58749         soc_block_list[16],
  58750         soc_genreg,
  58751         1,
  58752         0,
  58753         0x2020d00,
  58754         0,
  58755         0,
  58756         1,
  58757         soc_XLPORT_POWER_SAVE_BCM53400_A0r_fields,
  58758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58760         -1,
  58761         -1,
  58762     },
  58763 #endif /* chips */
  58764 
  58765 #if defined(BCM_56260_A0)
  58766     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM56260_A0r */
  58767         soc_block_list[16],
  58768         soc_genreg,
  58769         1,
  58770         0,
  58771         0x2020d00,
  58772         0,
  58773         0,
  58774         1,
  58775         soc_XLPORT_POWER_SAVE_BCM53400_A0r_fields,
  58776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58777         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58778         -1,
  58779         -1,
  58780     },
  58781 #endif /* chips */
  58782 
  58783 #if defined(BCM_56260_B0)
  58784     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM56260_B0r */
  58785         soc_block_list[16],
  58786         soc_genreg,
  58787         1,
  58788         0,
  58789         0x2020d00,
  58790         0,
  58791         0,
  58792         1,
  58793         soc_XLPORT_POWER_SAVE_BCM53400_A0r_fields,
  58794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58795         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58796         -1,
  58797         -1,
  58798     },
  58799 #endif /* chips */
  58800 
  58801 #if defined(BCM_56370_A0)
  58802     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM56370_A0r */
  58803         soc_block_list[16],
  58804         soc_genreg,
  58805         1,
  58806         0,
  58807         0x2020d00,
  58808         0,
  58809         0,
  58810         1,
  58811         soc_XLPORT_POWER_SAVE_BCM53400_A0r_fields,
  58812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58814         -1,
  58815         -1,
  58816         3,
  58817     },
  58818 #endif /* chips */
  58819 
  58820 #if defined(BCM_56560_A0)
  58821     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM56560_A0r */
  58822         soc_block_list[217],
  58823         soc_genreg,
  58824         1,
  58825         0,
  58826         0x2020d00,
  58827         0,
  58828         0,
  58829         1,
  58830         soc_XLPORT_POWER_SAVE_BCM53400_A0r_fields,
  58831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58832         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58833         -1,
  58834         -1,
  58835     },
  58836 #endif /* chips */
  58837 
  58838 #if defined(BCM_56560_B0)
  58839     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM56560_B0r */
  58840         soc_block_list[16],
  58841         soc_genreg,
  58842         1,
  58843         0,
  58844         0x2020d00,
  58845         0,
  58846         0,
  58847         1,
  58848         soc_XLPORT_POWER_SAVE_BCM53400_A0r_fields,
  58849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58850         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58851         -1,
  58852         -1,
  58853     },
  58854 #endif /* chips */
  58855 
  58856 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  58857     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM56670_A0r */
  58858         soc_block_list[16],
  58859         soc_genreg,
  58860         1,
  58861         0,
  58862         0x2020d00,
  58863         0,
  58864         0,
  58865         1,
  58866         soc_XLPORT_POWER_SAVE_BCM53400_A0r_fields,
  58867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58868         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58869         -1,
  58870         -1,
  58871     },
  58872 #endif /* chips */
  58873 
  58874 #if defined(BCM_56850_A0)
  58875     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM56850_A0r */
  58876         soc_block_list[16],
  58877         soc_genreg,
  58878         1,
  58879         0,
  58880         0x2020900,
  58881         0,
  58882         0,
  58883         1,
  58884         soc_XLPORT_POWER_SAVE_BCM56850_A0r_fields,
  58885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58886         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58887         -1,
  58888         -1,
  58889     },
  58890 #endif /* chips */
  58891 
  58892 #if defined(BCM_56860_A0)
  58893     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM56860_A0r */
  58894         soc_block_list[16],
  58895         soc_genreg,
  58896         1,
  58897         0,
  58898         0x2020a00,
  58899         0,
  58900         0,
  58901         1,
  58902         soc_XLPORT_POWER_SAVE_BCM56850_A0r_fields,
  58903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58904         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58905         -1,
  58906         -1,
  58907     },
  58908 #endif /* chips */
  58909 
  58910 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  58911     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  58912     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  58913     defined(BCM_56980_B0)
  58914     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM56960_A0r */
  58915         soc_block_list[16],
  58916         soc_genreg,
  58917         1,
  58918         0,
  58919         0x2020d00,
  58920         0,
  58921         0,
  58922         1,
  58923         soc_XLPORT_POWER_SAVE_BCM53400_A0r_fields,
  58924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  58926         -1,
  58927         -1,
  58928         3,
  58929     },
  58930 #endif /* chips */
  58931 
  58932 #if defined(BCM_88270_A0)
  58933     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM88270_A0r */
  58934         soc_block_list[56],
  58935         soc_genreg,
  58936         1,
  58937         0,
  58938         0x2020d00,
  58939         0,
  58940         0,
  58941         1,
  58942         soc_XLPORT_POWER_SAVE_BCM88270_A0r_fields,
  58943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58944         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58945         -1,
  58946         -1,
  58947     },
  58948 #endif /* chips */
  58949 
  58950 #if defined(BCM_88375_A0)
  58951     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM88375_A0r */
  58952         soc_block_list[56],
  58953         soc_genreg,
  58954         1,
  58955         0,
  58956         0x2020d00,
  58957         0,
  58958         0,
  58959         1,
  58960         soc_XLPORT_POWER_SAVE_BCM88375_A0r_fields,
  58961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58962         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58963         -1,
  58964         -1,
  58965     },
  58966 #endif /* chips */
  58967 
  58968 #if defined(BCM_88375_B0)
  58969     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM88375_B0r */
  58970         soc_block_list[56],
  58971         soc_genreg,
  58972         1,
  58973         0,
  58974         0x2020d00,
  58975         0,
  58976         0,
  58977         1,
  58978         soc_XLPORT_POWER_SAVE_BCM88375_B0r_fields,
  58979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58980         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58981         -1,
  58982         -1,
  58983     },
  58984 #endif /* chips */
  58985 
  58986 #if defined(BCM_88470_A0)
  58987     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM88470_A0r */
  58988         soc_block_list[56],
  58989         soc_genreg,
  58990         1,
  58991         0,
  58992         0x2020d00,
  58993         0,
  58994         0,
  58995         1,
  58996         soc_XLPORT_POWER_SAVE_BCM88470_A0r_fields,
  58997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58998         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  58999         -1,
  59000         -1,
  59001     },
  59002 #endif /* chips */
  59003 
  59004 #if defined(BCM_88470_B0)
  59005     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM88470_B0r */
  59006         soc_block_list[56],
  59007         soc_genreg,
  59008         1,
  59009         0,
  59010         0x2020d00,
  59011         0,
  59012         0,
  59013         1,
  59014         soc_XLPORT_POWER_SAVE_BCM88470_B0r_fields,
  59015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59016         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59017         -1,
  59018         -1,
  59019     },
  59020 #endif /* chips */
  59021 
  59022 #if defined(BCM_88675_A0)
  59023     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM88675_A0r */
  59024         soc_block_list[56],
  59025         soc_genreg,
  59026         1,
  59027         0,
  59028         0x2020d00,
  59029         0,
  59030         0,
  59031         1,
  59032         soc_XLPORT_POWER_SAVEr_fields,
  59033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59034         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59035         -1,
  59036         -1,
  59037     },
  59038 #endif /* chips */
  59039 
  59040 #if defined(BCM_88675_B0)
  59041     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM88675_B0r */
  59042         soc_block_list[56],
  59043         soc_genreg,
  59044         1,
  59045         0,
  59046         0x2020d00,
  59047         0,
  59048         0,
  59049         1,
  59050         soc_XLPORT_POWER_SAVE_BCM88675_B0r_fields,
  59051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59052         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59053         -1,
  59054         -1,
  59055     },
  59056 #endif /* chips */
  59057 
  59058 #if defined(BCM_88680_A0)
  59059     { /* SOC_REG_INT_XLPORT_POWER_SAVE_BCM88680_A0r */
  59060         soc_block_list[56],
  59061         soc_genreg,
  59062         1,
  59063         0,
  59064         0x2020d00,
  59065         0,
  59066         0,
  59067         1,
  59068         soc_XLPORT_POWER_SAVE_BCM88680_A0r_fields,
  59069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59070         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59071         -1,
  59072         -1,
  59073     },
  59074 #endif /* chips */
  59075 
  59076 #if defined(BCM_2801PM_A0)
  59077     { /* SOC_REG_INT_XLPORT_SBUS_CONTROLr */
  59078         soc_block_list[56],
  59079         soc_genreg,
  59080         1,
  59081         0,
  59082         0x2022b00,
  59083         0,
  59084         0,
  59085         2,
  59086         soc_CLPORT_SBUS_CONTROLr_fields,
  59087         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59088         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59089         -1,
  59090         -1,
  59091     },
  59092 #endif /* chips */
  59093 
  59094 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  59095     defined(BCM_56670_B0)
  59096     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM53400_A0r */
  59097         soc_block_list[16],
  59098         soc_genreg,
  59099         1,
  59100         0,
  59101         0x2022b00,
  59102         0,
  59103         0,
  59104         2,
  59105         soc_XLPORT_SBUS_CONTROL_BCM53400_A0r_fields,
  59106         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59107         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59108         -1,
  59109         -1,
  59110     },
  59111 #endif /* chips */
  59112 
  59113 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  59114     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM53570_A0r */
  59115         soc_block_list[16],
  59116         soc_genreg,
  59117         1,
  59118         0,
  59119         0x2022b00,
  59120         0,
  59121         0,
  59122         2,
  59123         soc_XLPORT_SBUS_CONTROL_BCM53400_A0r_fields,
  59124         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59125         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59126         -1,
  59127         -1,
  59128     },
  59129 #endif /* chips */
  59130 
  59131 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  59132     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM56160_A0r */
  59133         soc_block_list[16],
  59134         soc_genreg,
  59135         1,
  59136         0,
  59137         0x2022b00,
  59138         0,
  59139         0,
  59140         2,
  59141         soc_XLPORT_SBUS_CONTROL_BCM53400_A0r_fields,
  59142         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59143         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59144         -1,
  59145         -1,
  59146     },
  59147 #endif /* chips */
  59148 
  59149 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  59150     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM56260_A0r */
  59151         soc_block_list[16],
  59152         soc_genreg,
  59153         1,
  59154         0,
  59155         0x2022b00,
  59156         0,
  59157         0,
  59158         2,
  59159         soc_XLPORT_SBUS_CONTROL_BCM53400_A0r_fields,
  59160         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59161         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59162         -1,
  59163         -1,
  59164     },
  59165 #endif /* chips */
  59166 
  59167 #if defined(BCM_56370_A0)
  59168     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM56370_A0r */
  59169         soc_block_list[16],
  59170         soc_genreg,
  59171         1,
  59172         0,
  59173         0x2022b00,
  59174         0,
  59175         0,
  59176         2,
  59177         soc_XLPORT_SBUS_CONTROL_BCM53400_A0r_fields,
  59178         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59179         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59180         -1,
  59181         -1,
  59182         3,
  59183     },
  59184 #endif /* chips */
  59185 
  59186 #if defined(BCM_56560_A0)
  59187     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM56560_A0r */
  59188         soc_block_list[217],
  59189         soc_genreg,
  59190         1,
  59191         0,
  59192         0x2022b00,
  59193         0,
  59194         0,
  59195         2,
  59196         soc_XLPORT_SBUS_CONTROL_BCM53400_A0r_fields,
  59197         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59198         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59199         -1,
  59200         -1,
  59201     },
  59202 #endif /* chips */
  59203 
  59204 #if defined(BCM_56560_B0)
  59205     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM56560_B0r */
  59206         soc_block_list[16],
  59207         soc_genreg,
  59208         1,
  59209         0,
  59210         0x2022b00,
  59211         0,
  59212         0,
  59213         2,
  59214         soc_XLPORT_SBUS_CONTROL_BCM53400_A0r_fields,
  59215         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59216         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59217         -1,
  59218         -1,
  59219     },
  59220 #endif /* chips */
  59221 
  59222 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  59223     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  59224     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  59225     defined(BCM_56980_B0)
  59226     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM56960_A0r */
  59227         soc_block_list[16],
  59228         soc_genreg,
  59229         1,
  59230         0,
  59231         0x2022b00,
  59232         0,
  59233         0,
  59234         2,
  59235         soc_XLPORT_SBUS_CONTROL_BCM53400_A0r_fields,
  59236         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59237         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59238         -1,
  59239         -1,
  59240         3,
  59241     },
  59242 #endif /* chips */
  59243 
  59244 #if defined(BCM_88270_A0)
  59245     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM88270_A0r */
  59246         soc_block_list[56],
  59247         soc_genreg,
  59248         1,
  59249         0,
  59250         0x2022b00,
  59251         0,
  59252         0,
  59253         2,
  59254         soc_XLPORT_SBUS_CONTROL_BCM88270_A0r_fields,
  59255         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59256         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59257         -1,
  59258         -1,
  59259     },
  59260 #endif /* chips */
  59261 
  59262 #if defined(BCM_88375_A0)
  59263     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM88375_A0r */
  59264         soc_block_list[56],
  59265         soc_genreg,
  59266         1,
  59267         0,
  59268         0x2022b00,
  59269         0,
  59270         0,
  59271         2,
  59272         soc_XLPORT_SBUS_CONTROL_BCM88375_A0r_fields,
  59273         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59274         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59275         -1,
  59276         -1,
  59277     },
  59278 #endif /* chips */
  59279 
  59280 #if defined(BCM_88375_B0)
  59281     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM88375_B0r */
  59282         soc_block_list[56],
  59283         soc_genreg,
  59284         1,
  59285         0,
  59286         0x2022b00,
  59287         0,
  59288         0,
  59289         2,
  59290         soc_XLPORT_SBUS_CONTROL_BCM88375_B0r_fields,
  59291         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59292         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59293         -1,
  59294         -1,
  59295     },
  59296 #endif /* chips */
  59297 
  59298 #if defined(BCM_88470_A0)
  59299     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM88470_A0r */
  59300         soc_block_list[56],
  59301         soc_genreg,
  59302         1,
  59303         0,
  59304         0x2022b00,
  59305         0,
  59306         0,
  59307         2,
  59308         soc_XLPORT_SBUS_CONTROL_BCM88470_A0r_fields,
  59309         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59310         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59311         -1,
  59312         -1,
  59313     },
  59314 #endif /* chips */
  59315 
  59316 #if defined(BCM_88470_B0)
  59317     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM88470_B0r */
  59318         soc_block_list[56],
  59319         soc_genreg,
  59320         1,
  59321         0,
  59322         0x2022b00,
  59323         0,
  59324         0,
  59325         2,
  59326         soc_XLPORT_SBUS_CONTROL_BCM88470_B0r_fields,
  59327         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59328         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59329         -1,
  59330         -1,
  59331     },
  59332 #endif /* chips */
  59333 
  59334 #if defined(BCM_88675_A0)
  59335     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM88675_A0r */
  59336         soc_block_list[56],
  59337         soc_genreg,
  59338         1,
  59339         0,
  59340         0x2022b00,
  59341         0,
  59342         0,
  59343         2,
  59344         soc_XLPORT_SBUS_CONTROLr_fields,
  59345         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59346         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59347         -1,
  59348         -1,
  59349     },
  59350 #endif /* chips */
  59351 
  59352 #if defined(BCM_88675_B0)
  59353     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM88675_B0r */
  59354         soc_block_list[56],
  59355         soc_genreg,
  59356         1,
  59357         0,
  59358         0x2022b00,
  59359         0,
  59360         0,
  59361         2,
  59362         soc_XLPORT_SBUS_CONTROL_BCM88675_B0r_fields,
  59363         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59364         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59365         -1,
  59366         -1,
  59367     },
  59368 #endif /* chips */
  59369 
  59370 #if defined(BCM_88680_A0)
  59371     { /* SOC_REG_INT_XLPORT_SBUS_CONTROL_BCM88680_A0r */
  59372         soc_block_list[56],
  59373         soc_genreg,
  59374         1,
  59375         0,
  59376         0x2022b00,
  59377         0,
  59378         0,
  59379         2,
  59380         soc_XLPORT_SBUS_CONTROL_BCM88680_A0r_fields,
  59381         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  59382         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  59383         -1,
  59384         -1,
  59385     },
  59386 #endif /* chips */
  59387 
  59388 #if defined(BCM_2801PM_A0)
  59389     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRSr */
  59390         soc_block_list[56],
  59391         soc_portreg,
  59392         1,
  59393         0,
  59394         0x20400,
  59395         0,
  59396         0,
  59397         1,
  59398         soc_CLPORT_SGNDET_EARLYCRSr_fields,
  59399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59400         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59401         -1,
  59402         -1,
  59403     },
  59404 #endif /* chips */
  59405 
  59406 #if defined(BCM_53400_A0)
  59407     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r */
  59408         soc_block_list[16],
  59409         soc_portreg,
  59410         1,
  59411         0,
  59412         0x20400,
  59413         0,
  59414         0,
  59415         1,
  59416         soc_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r_fields,
  59417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59418         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59419         -1,
  59420         -1,
  59421     },
  59422 #endif /* chips */
  59423 
  59424 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  59425     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM53570_A0r */
  59426         soc_block_list[16],
  59427         soc_portreg,
  59428         1,
  59429         0,
  59430         0x20400,
  59431         0,
  59432         0,
  59433         1,
  59434         soc_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r_fields,
  59435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59436         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59437         -1,
  59438         -1,
  59439     },
  59440 #endif /* chips */
  59441 
  59442 #if defined(BCM_56150_A0)
  59443     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM56150_A0r */
  59444         soc_block_list[16],
  59445         soc_portreg,
  59446         1,
  59447         0,
  59448         0x20500,
  59449         0,
  59450         0,
  59451         1,
  59452         soc_CPORT_SGNDET_EARLYCRSr_fields,
  59453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59454         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59455         -1,
  59456         -1,
  59457     },
  59458 #endif /* chips */
  59459 
  59460 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  59461     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM56160_A0r */
  59462         soc_block_list[16],
  59463         soc_portreg,
  59464         1,
  59465         0,
  59466         0x20400,
  59467         0,
  59468         0,
  59469         1,
  59470         soc_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r_fields,
  59471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59472         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59473         -1,
  59474         -1,
  59475     },
  59476 #endif /* chips */
  59477 
  59478 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  59479     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM56260_A0r */
  59480         soc_block_list[16],
  59481         soc_portreg,
  59482         1,
  59483         0,
  59484         0x20400,
  59485         0,
  59486         0,
  59487         1,
  59488         soc_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r_fields,
  59489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59490         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59491         -1,
  59492         -1,
  59493     },
  59494 #endif /* chips */
  59495 
  59496 #if defined(BCM_56370_A0)
  59497     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM56370_A0r */
  59498         soc_block_list[16],
  59499         soc_portreg,
  59500         1,
  59501         0,
  59502         0x20400,
  59503         0,
  59504         0,
  59505         1,
  59506         soc_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r_fields,
  59507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59508         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59509         -1,
  59510         -1,
  59511         3,
  59512     },
  59513 #endif /* chips */
  59514 
  59515 #if defined(BCM_56560_A0)
  59516     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM56560_A0r */
  59517         soc_block_list[217],
  59518         soc_portreg,
  59519         1,
  59520         0,
  59521         0x20400,
  59522         0,
  59523         0,
  59524         1,
  59525         soc_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r_fields,
  59526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59527         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59528         -1,
  59529         -1,
  59530     },
  59531 #endif /* chips */
  59532 
  59533 #if defined(BCM_56560_B0)
  59534     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM56560_B0r */
  59535         soc_block_list[16],
  59536         soc_portreg,
  59537         1,
  59538         0,
  59539         0x20400,
  59540         0,
  59541         0,
  59542         1,
  59543         soc_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r_fields,
  59544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59545         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59546         -1,
  59547         -1,
  59548     },
  59549 #endif /* chips */
  59550 
  59551 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  59552     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM56670_A0r */
  59553         soc_block_list[16],
  59554         soc_portreg,
  59555         1,
  59556         0,
  59557         0x20400,
  59558         0,
  59559         0,
  59560         1,
  59561         soc_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r_fields,
  59562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59564         -1,
  59565         -1,
  59566     },
  59567 #endif /* chips */
  59568 
  59569 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  59570     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM56850_A0r */
  59571         soc_block_list[16],
  59572         soc_portreg,
  59573         1,
  59574         0,
  59575         0x20200,
  59576         0,
  59577         0,
  59578         1,
  59579         soc_CPORT_SGNDET_EARLYCRSr_fields,
  59580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59581         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59582         -1,
  59583         -1,
  59584     },
  59585 #endif /* chips */
  59586 
  59587 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  59588     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM56960_A0r */
  59589         soc_block_list[16],
  59590         soc_portreg,
  59591         1,
  59592         0,
  59593         0x20400,
  59594         0,
  59595         0,
  59596         1,
  59597         soc_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r_fields,
  59598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59599         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59600         -1,
  59601         -1,
  59602         3,
  59603     },
  59604 #endif /* chips */
  59605 
  59606 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  59607     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  59608     defined(BCM_56980_B0)
  59609     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM56970_A0r */
  59610         soc_block_list[16],
  59611         soc_portreg,
  59612         1,
  59613         0,
  59614         0x20400,
  59615         0,
  59616         0,
  59617         1,
  59618         soc_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r_fields,
  59619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59620         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59621         -1,
  59622         -1,
  59623         3,
  59624     },
  59625 #endif /* chips */
  59626 
  59627 #if defined(BCM_88270_A0)
  59628     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM88270_A0r */
  59629         soc_block_list[56],
  59630         soc_portreg,
  59631         1,
  59632         0,
  59633         0x20400,
  59634         0,
  59635         0,
  59636         1,
  59637         soc_XLPORT_SGNDET_EARLYCRS_BCM88270_A0r_fields,
  59638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59639         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59640         -1,
  59641         -1,
  59642     },
  59643 #endif /* chips */
  59644 
  59645 #if defined(BCM_88375_A0)
  59646     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM88375_A0r */
  59647         soc_block_list[56],
  59648         soc_portreg,
  59649         1,
  59650         0,
  59651         0x20400,
  59652         0,
  59653         0,
  59654         1,
  59655         soc_XLPORT_SGNDET_EARLYCRS_BCM88375_A0r_fields,
  59656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59657         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59658         -1,
  59659         -1,
  59660     },
  59661 #endif /* chips */
  59662 
  59663 #if defined(BCM_88375_B0)
  59664     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM88375_B0r */
  59665         soc_block_list[56],
  59666         soc_portreg,
  59667         1,
  59668         0,
  59669         0x20400,
  59670         0,
  59671         0,
  59672         1,
  59673         soc_XLPORT_SGNDET_EARLYCRS_BCM88375_B0r_fields,
  59674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59675         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59676         -1,
  59677         -1,
  59678     },
  59679 #endif /* chips */
  59680 
  59681 #if defined(BCM_88470_A0)
  59682     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM88470_A0r */
  59683         soc_block_list[56],
  59684         soc_portreg,
  59685         1,
  59686         0,
  59687         0x20400,
  59688         0,
  59689         0,
  59690         1,
  59691         soc_XLPORT_SGNDET_EARLYCRS_BCM88470_A0r_fields,
  59692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59693         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59694         -1,
  59695         -1,
  59696     },
  59697 #endif /* chips */
  59698 
  59699 #if defined(BCM_88470_B0)
  59700     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM88470_B0r */
  59701         soc_block_list[56],
  59702         soc_portreg,
  59703         1,
  59704         0,
  59705         0x20400,
  59706         0,
  59707         0,
  59708         1,
  59709         soc_XLPORT_SGNDET_EARLYCRS_BCM88470_B0r_fields,
  59710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59711         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59712         -1,
  59713         -1,
  59714     },
  59715 #endif /* chips */
  59716 
  59717 #if defined(BCM_88675_A0)
  59718     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM88675_A0r */
  59719         soc_block_list[56],
  59720         soc_portreg,
  59721         1,
  59722         0,
  59723         0x20400,
  59724         0,
  59725         0,
  59726         1,
  59727         soc_XLPORT_SGNDET_EARLYCRSr_fields,
  59728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59729         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59730         -1,
  59731         -1,
  59732     },
  59733 #endif /* chips */
  59734 
  59735 #if defined(BCM_88675_B0)
  59736     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM88675_B0r */
  59737         soc_block_list[56],
  59738         soc_portreg,
  59739         1,
  59740         0,
  59741         0x20400,
  59742         0,
  59743         0,
  59744         1,
  59745         soc_XLPORT_SGNDET_EARLYCRS_BCM88675_B0r_fields,
  59746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59747         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59748         -1,
  59749         -1,
  59750     },
  59751 #endif /* chips */
  59752 
  59753 #if defined(BCM_88680_A0)
  59754     { /* SOC_REG_INT_XLPORT_SGNDET_EARLYCRS_BCM88680_A0r */
  59755         soc_block_list[56],
  59756         soc_portreg,
  59757         1,
  59758         0,
  59759         0x20400,
  59760         0,
  59761         0,
  59762         1,
  59763         soc_XLPORT_SGNDET_EARLYCRS_BCM88680_A0r_fields,
  59764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59765         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  59766         -1,
  59767         -1,
  59768     },
  59769 #endif /* chips */
  59770 
  59771 #if defined(BCM_2801PM_A0)
  59772     { /* SOC_REG_INT_XLPORT_SOFT_RESETr */
  59773         soc_block_list[56],
  59774         soc_genreg,
  59775         1,
  59776         0,
  59777         0x2020c00,
  59778         0,
  59779         0,
  59780         5,
  59781         soc_CLPORT_SOFT_RESETr_fields,
  59782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59783         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  59784         -1,
  59785         -1,
  59786     },
  59787 #endif /* chips */
  59788 
  59789 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  59790     defined(BCM_56670_B0)
  59791     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM53400_A0r */
  59792         soc_block_list[16],
  59793         soc_genreg,
  59794         1,
  59795         0,
  59796         0x2020c00,
  59797         0,
  59798         0,
  59799         5,
  59800         soc_PGW_XL_RXFIFO_SOFT_RESETr_fields,
  59801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59802         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59803         -1,
  59804         -1,
  59805     },
  59806 #endif /* chips */
  59807 
  59808 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  59809     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM53570_A0r */
  59810         soc_block_list[16],
  59811         soc_genreg,
  59812         1,
  59813         0,
  59814         0x2020c00,
  59815         0,
  59816         0,
  59817         5,
  59818         soc_PGW_XL_RXFIFO_SOFT_RESETr_fields,
  59819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59820         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59821         -1,
  59822         -1,
  59823     },
  59824 #endif /* chips */
  59825 
  59826 #if defined(BCM_56150_A0)
  59827     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM56150_A0r */
  59828         soc_block_list[16],
  59829         soc_genreg,
  59830         1,
  59831         0,
  59832         0x2020c00,
  59833         0,
  59834         0,
  59835         5,
  59836         soc_XLPORT_SOFT_RESET_BCM56850_A0r_fields,
  59837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59838         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59839         -1,
  59840         -1,
  59841     },
  59842 #endif /* chips */
  59843 
  59844 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  59845     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM56160_A0r */
  59846         soc_block_list[16],
  59847         soc_genreg,
  59848         1,
  59849         0,
  59850         0x2020c00,
  59851         0,
  59852         0,
  59853         5,
  59854         soc_PGW_XL_RXFIFO_SOFT_RESETr_fields,
  59855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59856         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59857         -1,
  59858         -1,
  59859     },
  59860 #endif /* chips */
  59861 
  59862 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  59863     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM56260_A0r */
  59864         soc_block_list[16],
  59865         soc_genreg,
  59866         1,
  59867         0,
  59868         0x2020c00,
  59869         0,
  59870         0,
  59871         5,
  59872         soc_PGW_XL_RXFIFO_SOFT_RESETr_fields,
  59873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59874         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59875         -1,
  59876         -1,
  59877     },
  59878 #endif /* chips */
  59879 
  59880 #if defined(BCM_56370_A0)
  59881     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM56370_A0r */
  59882         soc_block_list[16],
  59883         soc_genreg,
  59884         1,
  59885         0,
  59886         0x2020c00,
  59887         0,
  59888         0,
  59889         5,
  59890         soc_PGW_XL_RXFIFO_SOFT_RESETr_fields,
  59891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59892         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59893         -1,
  59894         -1,
  59895         3,
  59896     },
  59897 #endif /* chips */
  59898 
  59899 #if defined(BCM_56560_A0)
  59900     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM56560_A0r */
  59901         soc_block_list[217],
  59902         soc_genreg,
  59903         1,
  59904         0,
  59905         0x2020c00,
  59906         0,
  59907         0,
  59908         5,
  59909         soc_PGW_XL_RXFIFO_SOFT_RESETr_fields,
  59910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59912         -1,
  59913         -1,
  59914     },
  59915 #endif /* chips */
  59916 
  59917 #if defined(BCM_56560_B0)
  59918     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM56560_B0r */
  59919         soc_block_list[16],
  59920         soc_genreg,
  59921         1,
  59922         0,
  59923         0x2020c00,
  59924         0,
  59925         0,
  59926         5,
  59927         soc_PGW_XL_RXFIFO_SOFT_RESETr_fields,
  59928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59929         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59930         -1,
  59931         -1,
  59932     },
  59933 #endif /* chips */
  59934 
  59935 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  59936     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM56850_A0r */
  59937         soc_block_list[16],
  59938         soc_genreg,
  59939         1,
  59940         0,
  59941         0x2020800,
  59942         0,
  59943         0,
  59944         5,
  59945         soc_XLPORT_SOFT_RESET_BCM56850_A0r_fields,
  59946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59947         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59948         -1,
  59949         -1,
  59950     },
  59951 #endif /* chips */
  59952 
  59953 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  59954     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  59955     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  59956     defined(BCM_56980_B0)
  59957     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM56960_A0r */
  59958         soc_block_list[16],
  59959         soc_genreg,
  59960         1,
  59961         0,
  59962         0x2020c00,
  59963         0,
  59964         0,
  59965         5,
  59966         soc_PGW_XL_RXFIFO_SOFT_RESETr_fields,
  59967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59968         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59969         -1,
  59970         -1,
  59971         3,
  59972     },
  59973 #endif /* chips */
  59974 
  59975 #if defined(BCM_88270_A0)
  59976     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM88270_A0r */
  59977         soc_block_list[56],
  59978         soc_genreg,
  59979         1,
  59980         0,
  59981         0x2020c00,
  59982         0,
  59983         0,
  59984         5,
  59985         soc_XLPORT_SOFT_RESET_BCM88270_A0r_fields,
  59986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59987         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  59988         -1,
  59989         -1,
  59990     },
  59991 #endif /* chips */
  59992 
  59993 #if defined(BCM_88375_A0)
  59994     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM88375_A0r */
  59995         soc_block_list[56],
  59996         soc_genreg,
  59997         1,
  59998         0,
  59999         0x2020c00,
  60000         0,
  60001         0,
  60002         5,
  60003         soc_XLPORT_SOFT_RESET_BCM88375_A0r_fields,
  60004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60005         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  60006         -1,
  60007         -1,
  60008     },
  60009 #endif /* chips */
  60010 
  60011 #if defined(BCM_88375_B0)
  60012     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM88375_B0r */
  60013         soc_block_list[56],
  60014         soc_genreg,
  60015         1,
  60016         0,
  60017         0x2020c00,
  60018         0,
  60019         0,
  60020         5,
  60021         soc_XLPORT_SOFT_RESET_BCM88375_B0r_fields,
  60022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60023         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  60024         -1,
  60025         -1,
  60026     },
  60027 #endif /* chips */
  60028 
  60029 #if defined(BCM_88470_A0)
  60030     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM88470_A0r */
  60031         soc_block_list[56],
  60032         soc_genreg,
  60033         1,
  60034         0,
  60035         0x2020c00,
  60036         0,
  60037         0,
  60038         5,
  60039         soc_XLPORT_SOFT_RESET_BCM88470_A0r_fields,
  60040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60041         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  60042         -1,
  60043         -1,
  60044     },
  60045 #endif /* chips */
  60046 
  60047 #if defined(BCM_88470_B0)
  60048     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM88470_B0r */
  60049         soc_block_list[56],
  60050         soc_genreg,
  60051         1,
  60052         0,
  60053         0x2020c00,
  60054         0,
  60055         0,
  60056         5,
  60057         soc_XLPORT_SOFT_RESET_BCM88470_B0r_fields,
  60058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60059         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  60060         -1,
  60061         -1,
  60062     },
  60063 #endif /* chips */
  60064 
  60065 #if defined(BCM_88675_A0)
  60066     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM88675_A0r */
  60067         soc_block_list[56],
  60068         soc_genreg,
  60069         1,
  60070         0,
  60071         0x2020c00,
  60072         0,
  60073         0,
  60074         5,
  60075         soc_XLPORT_SOFT_RESETr_fields,
  60076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60077         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  60078         -1,
  60079         -1,
  60080     },
  60081 #endif /* chips */
  60082 
  60083 #if defined(BCM_88675_B0)
  60084     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM88675_B0r */
  60085         soc_block_list[56],
  60086         soc_genreg,
  60087         1,
  60088         0,
  60089         0x2020c00,
  60090         0,
  60091         0,
  60092         5,
  60093         soc_XLPORT_SOFT_RESET_BCM88675_B0r_fields,
  60094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60095         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  60096         -1,
  60097         -1,
  60098     },
  60099 #endif /* chips */
  60100 
  60101 #if defined(BCM_88680_A0)
  60102     { /* SOC_REG_INT_XLPORT_SOFT_RESET_BCM88680_A0r */
  60103         soc_block_list[56],
  60104         soc_genreg,
  60105         1,
  60106         0,
  60107         0x2020c00,
  60108         0,
  60109         0,
  60110         5,
  60111         soc_XLPORT_SOFT_RESET_BCM88680_A0r_fields,
  60112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60113         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  60114         -1,
  60115         -1,
  60116     },
  60117 #endif /* chips */
  60118 
  60119 #if defined(BCM_2801PM_A0)
  60120     { /* SOC_REG_INT_XLPORT_SPARE0_REGr */
  60121         soc_block_list[56],
  60122         soc_portreg,
  60123         1,
  60124         0,
  60125         0x20900,
  60126         0,
  60127         0,
  60128         1,
  60129         soc_CLPORT_SPARE0_REGr_fields,
  60130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60132         -1,
  60133         -1,
  60134     },
  60135 #endif /* chips */
  60136 
  60137 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  60138     defined(BCM_56670_B0)
  60139     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM53400_A0r */
  60140         soc_block_list[16],
  60141         soc_portreg,
  60142         1,
  60143         0,
  60144         0x20900,
  60145         0,
  60146         0,
  60147         1,
  60148         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  60149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60150         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60151         -1,
  60152         -1,
  60153     },
  60154 #endif /* chips */
  60155 
  60156 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  60157     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM53570_A0r */
  60158         soc_block_list[16],
  60159         soc_portreg,
  60160         1,
  60161         0,
  60162         0x20900,
  60163         0,
  60164         0,
  60165         1,
  60166         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  60167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60169         -1,
  60170         -1,
  60171     },
  60172 #endif /* chips */
  60173 
  60174 #if defined(BCM_56150_A0)
  60175     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM56150_A0r */
  60176         soc_block_list[16],
  60177         soc_portreg,
  60178         1,
  60179         0,
  60180         0x20900,
  60181         0,
  60182         0,
  60183         1,
  60184         soc_PORT_SPARE0_REGr_fields,
  60185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60187         -1,
  60188         -1,
  60189     },
  60190 #endif /* chips */
  60191 
  60192 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  60193     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM56160_A0r */
  60194         soc_block_list[16],
  60195         soc_portreg,
  60196         1,
  60197         0,
  60198         0x20900,
  60199         0,
  60200         0,
  60201         1,
  60202         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  60203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60204         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60205         -1,
  60206         -1,
  60207     },
  60208 #endif /* chips */
  60209 
  60210 #if defined(BCM_56260_A0)
  60211     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM56260_A0r */
  60212         soc_block_list[16],
  60213         soc_portreg,
  60214         1,
  60215         0,
  60216         0x20900,
  60217         0,
  60218         0,
  60219         1,
  60220         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  60221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60222         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60223         -1,
  60224         -1,
  60225     },
  60226 #endif /* chips */
  60227 
  60228 #if defined(BCM_56260_B0)
  60229     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM56260_B0r */
  60230         soc_block_list[16],
  60231         soc_portreg,
  60232         1,
  60233         0,
  60234         0x20900,
  60235         0,
  60236         0,
  60237         1,
  60238         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  60239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60240         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60241         -1,
  60242         -1,
  60243     },
  60244 #endif /* chips */
  60245 
  60246 #if defined(BCM_56370_A0)
  60247     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM56370_A0r */
  60248         soc_block_list[16],
  60249         soc_portreg,
  60250         1,
  60251         0,
  60252         0x20900,
  60253         0,
  60254         0,
  60255         1,
  60256         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  60257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60258         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60259         -1,
  60260         -1,
  60261         3,
  60262     },
  60263 #endif /* chips */
  60264 
  60265 #if defined(BCM_56560_A0)
  60266     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM56560_A0r */
  60267         soc_block_list[217],
  60268         soc_portreg,
  60269         1,
  60270         0,
  60271         0x20900,
  60272         0,
  60273         0,
  60274         1,
  60275         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  60276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60277         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60278         -1,
  60279         -1,
  60280     },
  60281 #endif /* chips */
  60282 
  60283 #if defined(BCM_56560_B0)
  60284     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM56560_B0r */
  60285         soc_block_list[16],
  60286         soc_portreg,
  60287         1,
  60288         0,
  60289         0x20900,
  60290         0,
  60291         0,
  60292         1,
  60293         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  60294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60295         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60296         -1,
  60297         -1,
  60298     },
  60299 #endif /* chips */
  60300 
  60301 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  60302     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM56850_A0r */
  60303         soc_block_list[16],
  60304         soc_portreg,
  60305         1,
  60306         0,
  60307         0x20500,
  60308         0,
  60309         0,
  60310         1,
  60311         soc_PORT_SPARE0_REGr_fields,
  60312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60313         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60314         -1,
  60315         -1,
  60316     },
  60317 #endif /* chips */
  60318 
  60319 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  60320     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM56960_A0r */
  60321         soc_block_list[16],
  60322         soc_portreg,
  60323         1,
  60324         0,
  60325         0x20900,
  60326         0,
  60327         0,
  60328         1,
  60329         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  60330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60331         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60332         -1,
  60333         -1,
  60334         3,
  60335     },
  60336 #endif /* chips */
  60337 
  60338 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  60339     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  60340     defined(BCM_56980_B0)
  60341     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM56970_A0r */
  60342         soc_block_list[16],
  60343         soc_portreg,
  60344         1,
  60345         0,
  60346         0x20900,
  60347         0,
  60348         0,
  60349         1,
  60350         soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields,
  60351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60352         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60353         -1,
  60354         -1,
  60355         3,
  60356     },
  60357 #endif /* chips */
  60358 
  60359 #if defined(BCM_88270_A0)
  60360     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM88270_A0r */
  60361         soc_block_list[56],
  60362         soc_portreg,
  60363         1,
  60364         0,
  60365         0x20900,
  60366         0,
  60367         0,
  60368         1,
  60369         soc_XLPORT_SPARE0_REG_BCM88270_A0r_fields,
  60370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60371         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60372         -1,
  60373         -1,
  60374     },
  60375 #endif /* chips */
  60376 
  60377 #if defined(BCM_88375_A0)
  60378     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM88375_A0r */
  60379         soc_block_list[56],
  60380         soc_portreg,
  60381         1,
  60382         0,
  60383         0x20900,
  60384         0,
  60385         0,
  60386         1,
  60387         soc_XLPORT_SPARE0_REG_BCM88375_A0r_fields,
  60388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60389         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60390         -1,
  60391         -1,
  60392     },
  60393 #endif /* chips */
  60394 
  60395 #if defined(BCM_88375_B0)
  60396     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM88375_B0r */
  60397         soc_block_list[56],
  60398         soc_portreg,
  60399         1,
  60400         0,
  60401         0x20900,
  60402         0,
  60403         0,
  60404         1,
  60405         soc_XLPORT_SPARE0_REG_BCM88375_B0r_fields,
  60406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60407         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60408         -1,
  60409         -1,
  60410     },
  60411 #endif /* chips */
  60412 
  60413 #if defined(BCM_88470_A0)
  60414     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM88470_A0r */
  60415         soc_block_list[56],
  60416         soc_portreg,
  60417         1,
  60418         0,
  60419         0x20900,
  60420         0,
  60421         0,
  60422         1,
  60423         soc_XLPORT_SPARE0_REG_BCM88470_A0r_fields,
  60424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60425         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60426         -1,
  60427         -1,
  60428     },
  60429 #endif /* chips */
  60430 
  60431 #if defined(BCM_88470_B0)
  60432     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM88470_B0r */
  60433         soc_block_list[56],
  60434         soc_portreg,
  60435         1,
  60436         0,
  60437         0x20900,
  60438         0,
  60439         0,
  60440         1,
  60441         soc_XLPORT_SPARE0_REG_BCM88470_B0r_fields,
  60442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60444         -1,
  60445         -1,
  60446     },
  60447 #endif /* chips */
  60448 
  60449 #if defined(BCM_88675_A0)
  60450     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM88675_A0r */
  60451         soc_block_list[56],
  60452         soc_portreg,
  60453         1,
  60454         0,
  60455         0x20900,
  60456         0,
  60457         0,
  60458         1,
  60459         soc_XLPORT_SPARE0_REGr_fields,
  60460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60462         -1,
  60463         -1,
  60464     },
  60465 #endif /* chips */
  60466 
  60467 #if defined(BCM_88675_B0)
  60468     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM88675_B0r */
  60469         soc_block_list[56],
  60470         soc_portreg,
  60471         1,
  60472         0,
  60473         0x20900,
  60474         0,
  60475         0,
  60476         1,
  60477         soc_XLPORT_SPARE0_REG_BCM88675_B0r_fields,
  60478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60479         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60480         -1,
  60481         -1,
  60482     },
  60483 #endif /* chips */
  60484 
  60485 #if defined(BCM_88680_A0)
  60486     { /* SOC_REG_INT_XLPORT_SPARE0_REG_BCM88680_A0r */
  60487         soc_block_list[56],
  60488         soc_portreg,
  60489         1,
  60490         0,
  60491         0x20900,
  60492         0,
  60493         0,
  60494         1,
  60495         soc_XLPORT_SPARE0_REG_BCM88680_A0r_fields,
  60496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60498         -1,
  60499         -1,
  60500     },
  60501 #endif /* chips */
  60502 
  60503 #if defined(BCM_2801PM_A0)
  60504     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROLr */
  60505         soc_block_list[56],
  60506         soc_portreg,
  60507         1,
  60508         0,
  60509         0x20600,
  60510         0,
  60511         0,
  60512         2,
  60513         soc_CLPORT_SW_FLOW_CONTROLr_fields,
  60514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60515         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60516         -1,
  60517         -1,
  60518     },
  60519 #endif /* chips */
  60520 
  60521 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  60522     defined(BCM_56670_B0)
  60523     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM53400_A0r */
  60524         soc_block_list[16],
  60525         soc_portreg,
  60526         1,
  60527         0,
  60528         0x20600,
  60529         0,
  60530         0,
  60531         2,
  60532         soc_CLPORT_SW_FLOW_CONTROLr_fields,
  60533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60534         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60535         -1,
  60536         -1,
  60537     },
  60538 #endif /* chips */
  60539 
  60540 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  60541     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM53570_A0r */
  60542         soc_block_list[16],
  60543         soc_portreg,
  60544         1,
  60545         0,
  60546         0x20600,
  60547         0,
  60548         0,
  60549         2,
  60550         soc_CLPORT_SW_FLOW_CONTROLr_fields,
  60551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60552         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60553         -1,
  60554         -1,
  60555     },
  60556 #endif /* chips */
  60557 
  60558 #if defined(BCM_56150_A0)
  60559     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM56150_A0r */
  60560         soc_block_list[16],
  60561         soc_portreg,
  60562         1,
  60563         0,
  60564         0x20700,
  60565         0,
  60566         0,
  60567         2,
  60568         soc_XLPORT_SW_FLOW_CONTROL_BCM56850_A0r_fields,
  60569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60570         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60571         -1,
  60572         -1,
  60573     },
  60574 #endif /* chips */
  60575 
  60576 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  60577     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM56160_A0r */
  60578         soc_block_list[16],
  60579         soc_portreg,
  60580         1,
  60581         0,
  60582         0x20600,
  60583         0,
  60584         0,
  60585         2,
  60586         soc_CLPORT_SW_FLOW_CONTROLr_fields,
  60587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60588         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60589         -1,
  60590         -1,
  60591     },
  60592 #endif /* chips */
  60593 
  60594 #if defined(BCM_56260_A0)
  60595     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM56260_A0r */
  60596         soc_block_list[16],
  60597         soc_portreg,
  60598         1,
  60599         0,
  60600         0x20600,
  60601         0,
  60602         0,
  60603         2,
  60604         soc_CLPORT_SW_FLOW_CONTROLr_fields,
  60605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60606         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60607         -1,
  60608         -1,
  60609     },
  60610 #endif /* chips */
  60611 
  60612 #if defined(BCM_56260_B0)
  60613     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM56260_B0r */
  60614         soc_block_list[16],
  60615         soc_portreg,
  60616         1,
  60617         0,
  60618         0x20600,
  60619         0,
  60620         0,
  60621         2,
  60622         soc_CLPORT_SW_FLOW_CONTROLr_fields,
  60623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60624         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60625         -1,
  60626         -1,
  60627     },
  60628 #endif /* chips */
  60629 
  60630 #if defined(BCM_56370_A0)
  60631     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM56370_A0r */
  60632         soc_block_list[16],
  60633         soc_portreg,
  60634         1,
  60635         0,
  60636         0x20600,
  60637         0,
  60638         0,
  60639         2,
  60640         soc_CLPORT_SW_FLOW_CONTROLr_fields,
  60641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60642         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60643         -1,
  60644         -1,
  60645         3,
  60646     },
  60647 #endif /* chips */
  60648 
  60649 #if defined(BCM_56560_A0)
  60650     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM56560_A0r */
  60651         soc_block_list[217],
  60652         soc_portreg,
  60653         1,
  60654         0,
  60655         0x20600,
  60656         0,
  60657         0,
  60658         2,
  60659         soc_CLPORT_SW_FLOW_CONTROLr_fields,
  60660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60661         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60662         -1,
  60663         -1,
  60664     },
  60665 #endif /* chips */
  60666 
  60667 #if defined(BCM_56560_B0)
  60668     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM56560_B0r */
  60669         soc_block_list[16],
  60670         soc_portreg,
  60671         1,
  60672         0,
  60673         0x20600,
  60674         0,
  60675         0,
  60676         2,
  60677         soc_CLPORT_SW_FLOW_CONTROLr_fields,
  60678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60679         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60680         -1,
  60681         -1,
  60682     },
  60683 #endif /* chips */
  60684 
  60685 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  60686     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM56850_A0r */
  60687         soc_block_list[16],
  60688         soc_portreg,
  60689         1,
  60690         0,
  60691         0x20400,
  60692         0,
  60693         0,
  60694         2,
  60695         soc_XLPORT_SW_FLOW_CONTROL_BCM56850_A0r_fields,
  60696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60697         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60698         -1,
  60699         -1,
  60700     },
  60701 #endif /* chips */
  60702 
  60703 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  60704     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM56960_A0r */
  60705         soc_block_list[16],
  60706         soc_portreg,
  60707         1,
  60708         0,
  60709         0x20600,
  60710         0,
  60711         0,
  60712         2,
  60713         soc_CLPORT_SW_FLOW_CONTROLr_fields,
  60714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60715         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60716         -1,
  60717         -1,
  60718         3,
  60719     },
  60720 #endif /* chips */
  60721 
  60722 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  60723     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  60724     defined(BCM_56980_B0)
  60725     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM56970_A0r */
  60726         soc_block_list[16],
  60727         soc_portreg,
  60728         1,
  60729         0,
  60730         0x20600,
  60731         0,
  60732         0,
  60733         2,
  60734         soc_CLPORT_SW_FLOW_CONTROLr_fields,
  60735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60736         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60737         -1,
  60738         -1,
  60739         3,
  60740     },
  60741 #endif /* chips */
  60742 
  60743 #if defined(BCM_88270_A0)
  60744     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM88270_A0r */
  60745         soc_block_list[56],
  60746         soc_portreg,
  60747         1,
  60748         0,
  60749         0x20600,
  60750         0,
  60751         0,
  60752         2,
  60753         soc_XLPORT_SW_FLOW_CONTROL_BCM88270_A0r_fields,
  60754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60755         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60756         -1,
  60757         -1,
  60758     },
  60759 #endif /* chips */
  60760 
  60761 #if defined(BCM_88375_A0)
  60762     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM88375_A0r */
  60763         soc_block_list[56],
  60764         soc_portreg,
  60765         1,
  60766         0,
  60767         0x20600,
  60768         0,
  60769         0,
  60770         2,
  60771         soc_XLPORT_SW_FLOW_CONTROL_BCM88375_A0r_fields,
  60772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60773         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60774         -1,
  60775         -1,
  60776     },
  60777 #endif /* chips */
  60778 
  60779 #if defined(BCM_88375_B0)
  60780     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM88375_B0r */
  60781         soc_block_list[56],
  60782         soc_portreg,
  60783         1,
  60784         0,
  60785         0x20600,
  60786         0,
  60787         0,
  60788         2,
  60789         soc_XLPORT_SW_FLOW_CONTROL_BCM88375_B0r_fields,
  60790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60791         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60792         -1,
  60793         -1,
  60794     },
  60795 #endif /* chips */
  60796 
  60797 #if defined(BCM_88470_A0)
  60798     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM88470_A0r */
  60799         soc_block_list[56],
  60800         soc_portreg,
  60801         1,
  60802         0,
  60803         0x20600,
  60804         0,
  60805         0,
  60806         2,
  60807         soc_XLPORT_SW_FLOW_CONTROL_BCM88470_A0r_fields,
  60808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60809         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60810         -1,
  60811         -1,
  60812     },
  60813 #endif /* chips */
  60814 
  60815 #if defined(BCM_88470_B0)
  60816     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM88470_B0r */
  60817         soc_block_list[56],
  60818         soc_portreg,
  60819         1,
  60820         0,
  60821         0x20600,
  60822         0,
  60823         0,
  60824         2,
  60825         soc_XLPORT_SW_FLOW_CONTROL_BCM88470_B0r_fields,
  60826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60827         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60828         -1,
  60829         -1,
  60830     },
  60831 #endif /* chips */
  60832 
  60833 #if defined(BCM_88675_A0)
  60834     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM88675_A0r */
  60835         soc_block_list[56],
  60836         soc_portreg,
  60837         1,
  60838         0,
  60839         0x20600,
  60840         0,
  60841         0,
  60842         2,
  60843         soc_XLPORT_SW_FLOW_CONTROLr_fields,
  60844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60845         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60846         -1,
  60847         -1,
  60848     },
  60849 #endif /* chips */
  60850 
  60851 #if defined(BCM_88675_B0)
  60852     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM88675_B0r */
  60853         soc_block_list[56],
  60854         soc_portreg,
  60855         1,
  60856         0,
  60857         0x20600,
  60858         0,
  60859         0,
  60860         2,
  60861         soc_XLPORT_SW_FLOW_CONTROL_BCM88675_B0r_fields,
  60862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60863         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60864         -1,
  60865         -1,
  60866     },
  60867 #endif /* chips */
  60868 
  60869 #if defined(BCM_88680_A0)
  60870     { /* SOC_REG_INT_XLPORT_SW_FLOW_CONTROL_BCM88680_A0r */
  60871         soc_block_list[56],
  60872         soc_portreg,
  60873         1,
  60874         0,
  60875         0x20600,
  60876         0,
  60877         0,
  60878         2,
  60879         soc_XLPORT_SW_FLOW_CONTROL_BCM88680_A0r_fields,
  60880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60881         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60882         -1,
  60883         -1,
  60884     },
  60885 #endif /* chips */
  60886 
  60887 #if defined(BCM_56150_A0)
  60888     { /* SOC_REG_INT_XLPORT_TM_CONTROLr */
  60889         soc_block_list[16],
  60890         soc_genreg,
  60891         1,
  60892         0,
  60893         0x2022800,
  60894         0,
  60895         0,
  60896         13,
  60897         soc_XLPORT_TM_CONTROLr_fields,
  60898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60899         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  60900         -1,
  60901         -1,
  60902     },
  60903 #endif /* chips */
  60904 
  60905 #if defined(BCM_2801PM_A0)
  60906     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUSr */
  60907         soc_block_list[56],
  60908         soc_genreg,
  60909         1,
  60910         0,
  60911         0x2021300,
  60912         0,
  60913         0,
  60914         2,
  60915         soc_CLPORT_TSC_PLL_LOCK_STATUSr_fields,
  60916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60917         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60918         -1,
  60919         -1,
  60920     },
  60921 #endif /* chips */
  60922 
  60923 #if defined(BCM_53400_A0)
  60924     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM53400_A0r */
  60925         soc_block_list[16],
  60926         soc_genreg,
  60927         1,
  60928         0,
  60929         0x2021300,
  60930         0,
  60931         0,
  60932         2,
  60933         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM53400_A0r_fields,
  60934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60935         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60936         -1,
  60937         -1,
  60938     },
  60939 #endif /* chips */
  60940 
  60941 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  60942     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM53570_A0r */
  60943         soc_block_list[16],
  60944         soc_genreg,
  60945         1,
  60946         0,
  60947         0x2021300,
  60948         0,
  60949         0,
  60950         4,
  60951         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM53570_A0r_fields,
  60952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60953         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  60954         -1,
  60955         -1,
  60956     },
  60957 #endif /* chips */
  60958 
  60959 #if defined(BCM_56150_A0)
  60960     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM56150_A0r */
  60961         soc_block_list[16],
  60962         soc_genreg,
  60963         1,
  60964         0,
  60965         0x2021300,
  60966         0,
  60967         0,
  60968         2,
  60969         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM56850_A0r_fields,
  60970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60971         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60972         -1,
  60973         -1,
  60974     },
  60975 #endif /* chips */
  60976 
  60977 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  60978     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM56160_A0r */
  60979         soc_block_list[16],
  60980         soc_genreg,
  60981         1,
  60982         0,
  60983         0x2021300,
  60984         0,
  60985         0,
  60986         2,
  60987         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM53400_A0r_fields,
  60988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60989         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60990         -1,
  60991         -1,
  60992     },
  60993 #endif /* chips */
  60994 
  60995 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  60996     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM56260_A0r */
  60997         soc_block_list[16],
  60998         soc_genreg,
  60999         1,
  61000         0,
  61001         0x2021300,
  61002         0,
  61003         0,
  61004         2,
  61005         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM53400_A0r_fields,
  61006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61007         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61008         -1,
  61009         -1,
  61010     },
  61011 #endif /* chips */
  61012 
  61013 #if defined(BCM_56370_A0)
  61014     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM56370_A0r */
  61015         soc_block_list[16],
  61016         soc_genreg,
  61017         1,
  61018         0,
  61019         0x2021300,
  61020         0,
  61021         0,
  61022         2,
  61023         soc_CLPORT_TSC_PLL_LOCK_STATUS_BCM56960_A0r_fields,
  61024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61025         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61026         -1,
  61027         -1,
  61028         3,
  61029     },
  61030 #endif /* chips */
  61031 
  61032 #if defined(BCM_56560_A0)
  61033     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM56560_A0r */
  61034         soc_block_list[217],
  61035         soc_genreg,
  61036         1,
  61037         0,
  61038         0x2021300,
  61039         0,
  61040         0,
  61041         2,
  61042         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM53400_A0r_fields,
  61043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61044         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61045         -1,
  61046         -1,
  61047     },
  61048 #endif /* chips */
  61049 
  61050 #if defined(BCM_56560_B0)
  61051     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM56560_B0r */
  61052         soc_block_list[16],
  61053         soc_genreg,
  61054         1,
  61055         0,
  61056         0x2021300,
  61057         0,
  61058         0,
  61059         2,
  61060         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM53400_A0r_fields,
  61061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61062         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61063         -1,
  61064         -1,
  61065     },
  61066 #endif /* chips */
  61067 
  61068 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  61069     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM56670_A0r */
  61070         soc_block_list[16],
  61071         soc_genreg,
  61072         1,
  61073         0,
  61074         0x2021300,
  61075         0,
  61076         0,
  61077         4,
  61078         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM53570_A0r_fields,
  61079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61080         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  61081         -1,
  61082         -1,
  61083     },
  61084 #endif /* chips */
  61085 
  61086 #if defined(BCM_56850_A0)
  61087     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM56850_A0r */
  61088         soc_block_list[16],
  61089         soc_genreg,
  61090         1,
  61091         0,
  61092         0x2020e00,
  61093         0,
  61094         0,
  61095         2,
  61096         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM56850_A0r_fields,
  61097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61098         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61099         -1,
  61100         -1,
  61101     },
  61102 #endif /* chips */
  61103 
  61104 #if defined(BCM_56860_A0)
  61105     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM56860_A0r */
  61106         soc_block_list[16],
  61107         soc_genreg,
  61108         1,
  61109         0,
  61110         0x2020f00,
  61111         0,
  61112         0,
  61113         2,
  61114         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM56860_A0r_fields,
  61115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61116         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61117         -1,
  61118         -1,
  61119     },
  61120 #endif /* chips */
  61121 
  61122 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  61123     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  61124     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  61125     defined(BCM_56980_B0)
  61126     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM56960_A0r */
  61127         soc_block_list[16],
  61128         soc_genreg,
  61129         1,
  61130         0,
  61131         0x2021300,
  61132         0,
  61133         0,
  61134         2,
  61135         soc_CLPORT_TSC_PLL_LOCK_STATUS_BCM56960_A0r_fields,
  61136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61137         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61138         -1,
  61139         -1,
  61140         3,
  61141     },
  61142 #endif /* chips */
  61143 
  61144 #if defined(BCM_88270_A0)
  61145     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM88270_A0r */
  61146         soc_block_list[56],
  61147         soc_genreg,
  61148         1,
  61149         0,
  61150         0x2021300,
  61151         0,
  61152         0,
  61153         2,
  61154         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88270_A0r_fields,
  61155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61156         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61157         -1,
  61158         -1,
  61159     },
  61160 #endif /* chips */
  61161 
  61162 #if defined(BCM_88375_A0)
  61163     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM88375_A0r */
  61164         soc_block_list[56],
  61165         soc_genreg,
  61166         1,
  61167         0,
  61168         0x2021300,
  61169         0,
  61170         0,
  61171         2,
  61172         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88375_A0r_fields,
  61173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61174         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61175         -1,
  61176         -1,
  61177     },
  61178 #endif /* chips */
  61179 
  61180 #if defined(BCM_88375_B0)
  61181     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM88375_B0r */
  61182         soc_block_list[56],
  61183         soc_genreg,
  61184         1,
  61185         0,
  61186         0x2021300,
  61187         0,
  61188         0,
  61189         2,
  61190         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88375_B0r_fields,
  61191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61192         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61193         -1,
  61194         -1,
  61195     },
  61196 #endif /* chips */
  61197 
  61198 #if defined(BCM_88470_A0)
  61199     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM88470_A0r */
  61200         soc_block_list[56],
  61201         soc_genreg,
  61202         1,
  61203         0,
  61204         0x2021300,
  61205         0,
  61206         0,
  61207         2,
  61208         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88470_A0r_fields,
  61209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61210         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61211         -1,
  61212         -1,
  61213     },
  61214 #endif /* chips */
  61215 
  61216 #if defined(BCM_88470_B0)
  61217     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM88470_B0r */
  61218         soc_block_list[56],
  61219         soc_genreg,
  61220         1,
  61221         0,
  61222         0x2021300,
  61223         0,
  61224         0,
  61225         2,
  61226         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88470_B0r_fields,
  61227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61228         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61229         -1,
  61230         -1,
  61231     },
  61232 #endif /* chips */
  61233 
  61234 #if defined(BCM_88675_A0)
  61235     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM88675_A0r */
  61236         soc_block_list[56],
  61237         soc_genreg,
  61238         1,
  61239         0,
  61240         0x2021300,
  61241         0,
  61242         0,
  61243         2,
  61244         soc_XLPORT_TSC_PLL_LOCK_STATUSr_fields,
  61245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61246         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61247         -1,
  61248         -1,
  61249     },
  61250 #endif /* chips */
  61251 
  61252 #if defined(BCM_88675_B0)
  61253     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM88675_B0r */
  61254         soc_block_list[56],
  61255         soc_genreg,
  61256         1,
  61257         0,
  61258         0x2021300,
  61259         0,
  61260         0,
  61261         2,
  61262         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88675_B0r_fields,
  61263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61264         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61265         -1,
  61266         -1,
  61267     },
  61268 #endif /* chips */
  61269 
  61270 #if defined(BCM_88680_A0)
  61271     { /* SOC_REG_INT_XLPORT_TSC_PLL_LOCK_STATUS_BCM88680_A0r */
  61272         soc_block_list[56],
  61273         soc_genreg,
  61274         1,
  61275         0,
  61276         0x2021300,
  61277         0,
  61278         0,
  61279         2,
  61280         soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88680_A0r_fields,
  61281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61282         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61283         -1,
  61284         -1,
  61285     },
  61286 #endif /* chips */
  61287 
  61288 #if defined(BCM_2801PM_A0)
  61289     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REGr */
  61290         soc_block_list[56],
  61291         soc_genreg,
  61292         1,
  61293         0,
  61294         0x2022600,
  61295         0,
  61296         0,
  61297         1,
  61298         soc_CLPORT_TS_TIMER_31_0_REGr_fields,
  61299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61300         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61301         -1,
  61302         -1,
  61303     },
  61304 #endif /* chips */
  61305 
  61306 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  61307     defined(BCM_56670_B0)
  61308     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM53400_A0r */
  61309         soc_block_list[16],
  61310         soc_genreg,
  61311         1,
  61312         0,
  61313         0x2022600,
  61314         0,
  61315         0,
  61316         1,
  61317         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  61318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61319         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61320         -1,
  61321         -1,
  61322     },
  61323 #endif /* chips */
  61324 
  61325 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  61326     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM53570_A0r */
  61327         soc_block_list[16],
  61328         soc_genreg,
  61329         1,
  61330         0,
  61331         0x2022600,
  61332         0,
  61333         0,
  61334         1,
  61335         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  61336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61337         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61338         -1,
  61339         -1,
  61340     },
  61341 #endif /* chips */
  61342 
  61343 #if defined(BCM_56150_A0)
  61344     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM56150_A0r */
  61345         soc_block_list[16],
  61346         soc_genreg,
  61347         1,
  61348         0,
  61349         0x2022e00,
  61350         0,
  61351         0,
  61352         1,
  61353         soc_GPORT_TS_TIMER_31_0_REG_BCM56150_A0r_fields,
  61354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61355         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61356         -1,
  61357         -1,
  61358     },
  61359 #endif /* chips */
  61360 
  61361 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  61362     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM56160_A0r */
  61363         soc_block_list[16],
  61364         soc_genreg,
  61365         1,
  61366         0,
  61367         0x2022600,
  61368         0,
  61369         0,
  61370         1,
  61371         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  61372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61373         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61374         -1,
  61375         -1,
  61376     },
  61377 #endif /* chips */
  61378 
  61379 #if defined(BCM_56260_A0)
  61380     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM56260_A0r */
  61381         soc_block_list[16],
  61382         soc_genreg,
  61383         1,
  61384         0,
  61385         0x2022600,
  61386         0,
  61387         0,
  61388         1,
  61389         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  61390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61391         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61392         -1,
  61393         -1,
  61394     },
  61395 #endif /* chips */
  61396 
  61397 #if defined(BCM_56260_B0)
  61398     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM56260_B0r */
  61399         soc_block_list[16],
  61400         soc_genreg,
  61401         1,
  61402         0,
  61403         0x2022600,
  61404         0,
  61405         0,
  61406         1,
  61407         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  61408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61409         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61410         -1,
  61411         -1,
  61412     },
  61413 #endif /* chips */
  61414 
  61415 #if defined(BCM_56370_A0)
  61416     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM56370_A0r */
  61417         soc_block_list[16],
  61418         soc_genreg,
  61419         1,
  61420         0,
  61421         0x2022600,
  61422         0,
  61423         0,
  61424         1,
  61425         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  61426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61427         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61428         -1,
  61429         -1,
  61430         3,
  61431     },
  61432 #endif /* chips */
  61433 
  61434 #if defined(BCM_56560_A0)
  61435     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM56560_A0r */
  61436         soc_block_list[217],
  61437         soc_genreg,
  61438         1,
  61439         0,
  61440         0x2022600,
  61441         0,
  61442         0,
  61443         1,
  61444         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  61445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61446         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61447         -1,
  61448         -1,
  61449     },
  61450 #endif /* chips */
  61451 
  61452 #if defined(BCM_56560_B0)
  61453     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM56560_B0r */
  61454         soc_block_list[16],
  61455         soc_genreg,
  61456         1,
  61457         0,
  61458         0x2022600,
  61459         0,
  61460         0,
  61461         1,
  61462         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  61463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61464         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61465         -1,
  61466         -1,
  61467     },
  61468 #endif /* chips */
  61469 
  61470 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  61471     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM56960_A0r */
  61472         soc_block_list[16],
  61473         soc_genreg,
  61474         1,
  61475         0,
  61476         0x2022600,
  61477         0,
  61478         0,
  61479         1,
  61480         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  61481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61482         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61483         -1,
  61484         -1,
  61485         3,
  61486     },
  61487 #endif /* chips */
  61488 
  61489 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  61490     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  61491     defined(BCM_56980_B0)
  61492     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM56970_A0r */
  61493         soc_block_list[16],
  61494         soc_genreg,
  61495         1,
  61496         0,
  61497         0x2022600,
  61498         0,
  61499         0,
  61500         1,
  61501         soc_GPORT_TS_TIMER_31_0_REG_BCM53400_A0r_fields,
  61502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61503         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61504         -1,
  61505         -1,
  61506         3,
  61507     },
  61508 #endif /* chips */
  61509 
  61510 #if defined(BCM_88270_A0)
  61511     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM88270_A0r */
  61512         soc_block_list[56],
  61513         soc_genreg,
  61514         1,
  61515         0,
  61516         0x2022600,
  61517         0,
  61518         0,
  61519         1,
  61520         soc_XLPORT_TS_TIMER_31_0_REG_BCM88270_A0r_fields,
  61521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61522         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61523         -1,
  61524         -1,
  61525     },
  61526 #endif /* chips */
  61527 
  61528 #if defined(BCM_88375_A0)
  61529     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM88375_A0r */
  61530         soc_block_list[56],
  61531         soc_genreg,
  61532         1,
  61533         0,
  61534         0x2022600,
  61535         0,
  61536         0,
  61537         1,
  61538         soc_XLPORT_TS_TIMER_31_0_REG_BCM88375_A0r_fields,
  61539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61540         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61541         -1,
  61542         -1,
  61543     },
  61544 #endif /* chips */
  61545 
  61546 #if defined(BCM_88375_B0)
  61547     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM88375_B0r */
  61548         soc_block_list[56],
  61549         soc_genreg,
  61550         1,
  61551         0,
  61552         0x2022600,
  61553         0,
  61554         0,
  61555         1,
  61556         soc_XLPORT_TS_TIMER_31_0_REG_BCM88375_B0r_fields,
  61557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61558         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61559         -1,
  61560         -1,
  61561     },
  61562 #endif /* chips */
  61563 
  61564 #if defined(BCM_88470_A0)
  61565     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM88470_A0r */
  61566         soc_block_list[56],
  61567         soc_genreg,
  61568         1,
  61569         0,
  61570         0x2022600,
  61571         0,
  61572         0,
  61573         1,
  61574         soc_XLPORT_TS_TIMER_31_0_REG_BCM88470_A0r_fields,
  61575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61576         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61577         -1,
  61578         -1,
  61579     },
  61580 #endif /* chips */
  61581 
  61582 #if defined(BCM_88470_B0)
  61583     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM88470_B0r */
  61584         soc_block_list[56],
  61585         soc_genreg,
  61586         1,
  61587         0,
  61588         0x2022600,
  61589         0,
  61590         0,
  61591         1,
  61592         soc_XLPORT_TS_TIMER_31_0_REG_BCM88470_B0r_fields,
  61593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61594         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61595         -1,
  61596         -1,
  61597     },
  61598 #endif /* chips */
  61599 
  61600 #if defined(BCM_88675_A0)
  61601     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM88675_A0r */
  61602         soc_block_list[56],
  61603         soc_genreg,
  61604         1,
  61605         0,
  61606         0x2022600,
  61607         0,
  61608         0,
  61609         1,
  61610         soc_XLPORT_TS_TIMER_31_0_REGr_fields,
  61611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61612         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61613         -1,
  61614         -1,
  61615     },
  61616 #endif /* chips */
  61617 
  61618 #if defined(BCM_88675_B0)
  61619     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM88675_B0r */
  61620         soc_block_list[56],
  61621         soc_genreg,
  61622         1,
  61623         0,
  61624         0x2022600,
  61625         0,
  61626         0,
  61627         1,
  61628         soc_XLPORT_TS_TIMER_31_0_REG_BCM88675_B0r_fields,
  61629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61630         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61631         -1,
  61632         -1,
  61633     },
  61634 #endif /* chips */
  61635 
  61636 #if defined(BCM_88680_A0)
  61637     { /* SOC_REG_INT_XLPORT_TS_TIMER_31_0_REG_BCM88680_A0r */
  61638         soc_block_list[56],
  61639         soc_genreg,
  61640         1,
  61641         0,
  61642         0x2022600,
  61643         0,
  61644         0,
  61645         1,
  61646         soc_XLPORT_TS_TIMER_31_0_REG_BCM88680_A0r_fields,
  61647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61648         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61649         -1,
  61650         -1,
  61651     },
  61652 #endif /* chips */
  61653 
  61654 #if defined(BCM_2801PM_A0)
  61655     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REGr */
  61656         soc_block_list[56],
  61657         soc_genreg,
  61658         1,
  61659         0,
  61660         0x2022500,
  61661         0,
  61662         0,
  61663         1,
  61664         soc_CLPORT_TS_TIMER_47_32_REGr_fields,
  61665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61666         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61667         -1,
  61668         -1,
  61669     },
  61670 #endif /* chips */
  61671 
  61672 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  61673     defined(BCM_56670_B0)
  61674     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM53400_A0r */
  61675         soc_block_list[16],
  61676         soc_genreg,
  61677         1,
  61678         0,
  61679         0x2022500,
  61680         0,
  61681         0,
  61682         1,
  61683         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  61684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61685         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61686         -1,
  61687         -1,
  61688     },
  61689 #endif /* chips */
  61690 
  61691 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  61692     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM53570_A0r */
  61693         soc_block_list[16],
  61694         soc_genreg,
  61695         1,
  61696         0,
  61697         0x2022500,
  61698         0,
  61699         0,
  61700         1,
  61701         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  61702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61703         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61704         -1,
  61705         -1,
  61706     },
  61707 #endif /* chips */
  61708 
  61709 #if defined(BCM_56150_A0)
  61710     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM56150_A0r */
  61711         soc_block_list[16],
  61712         soc_genreg,
  61713         1,
  61714         0,
  61715         0x2022d00,
  61716         0,
  61717         0,
  61718         1,
  61719         soc_GPORT_TS_TIMER_47_32_REG_BCM56150_A0r_fields,
  61720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61721         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61722         -1,
  61723         -1,
  61724     },
  61725 #endif /* chips */
  61726 
  61727 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  61728     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM56160_A0r */
  61729         soc_block_list[16],
  61730         soc_genreg,
  61731         1,
  61732         0,
  61733         0x2022500,
  61734         0,
  61735         0,
  61736         1,
  61737         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  61738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61739         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61740         -1,
  61741         -1,
  61742     },
  61743 #endif /* chips */
  61744 
  61745 #if defined(BCM_56260_A0)
  61746     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM56260_A0r */
  61747         soc_block_list[16],
  61748         soc_genreg,
  61749         1,
  61750         0,
  61751         0x2022500,
  61752         0,
  61753         0,
  61754         1,
  61755         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  61756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61757         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61758         -1,
  61759         -1,
  61760     },
  61761 #endif /* chips */
  61762 
  61763 #if defined(BCM_56260_B0)
  61764     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM56260_B0r */
  61765         soc_block_list[16],
  61766         soc_genreg,
  61767         1,
  61768         0,
  61769         0x2022500,
  61770         0,
  61771         0,
  61772         1,
  61773         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  61774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61775         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61776         -1,
  61777         -1,
  61778     },
  61779 #endif /* chips */
  61780 
  61781 #if defined(BCM_56370_A0)
  61782     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM56370_A0r */
  61783         soc_block_list[16],
  61784         soc_genreg,
  61785         1,
  61786         0,
  61787         0x2022500,
  61788         0,
  61789         0,
  61790         1,
  61791         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  61792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61793         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61794         -1,
  61795         -1,
  61796         3,
  61797     },
  61798 #endif /* chips */
  61799 
  61800 #if defined(BCM_56560_A0)
  61801     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM56560_A0r */
  61802         soc_block_list[217],
  61803         soc_genreg,
  61804         1,
  61805         0,
  61806         0x2022500,
  61807         0,
  61808         0,
  61809         1,
  61810         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  61811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61812         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61813         -1,
  61814         -1,
  61815     },
  61816 #endif /* chips */
  61817 
  61818 #if defined(BCM_56560_B0)
  61819     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM56560_B0r */
  61820         soc_block_list[16],
  61821         soc_genreg,
  61822         1,
  61823         0,
  61824         0x2022500,
  61825         0,
  61826         0,
  61827         1,
  61828         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  61829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61830         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61831         -1,
  61832         -1,
  61833     },
  61834 #endif /* chips */
  61835 
  61836 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  61837     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM56960_A0r */
  61838         soc_block_list[16],
  61839         soc_genreg,
  61840         1,
  61841         0,
  61842         0x2022500,
  61843         0,
  61844         0,
  61845         1,
  61846         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  61847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61848         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61849         -1,
  61850         -1,
  61851         3,
  61852     },
  61853 #endif /* chips */
  61854 
  61855 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  61856     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  61857     defined(BCM_56980_B0)
  61858     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM56970_A0r */
  61859         soc_block_list[16],
  61860         soc_genreg,
  61861         1,
  61862         0,
  61863         0x2022500,
  61864         0,
  61865         0,
  61866         1,
  61867         soc_GPORT_TS_TIMER_47_32_REG_BCM53400_A0r_fields,
  61868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61869         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  61870         -1,
  61871         -1,
  61872         3,
  61873     },
  61874 #endif /* chips */
  61875 
  61876 #if defined(BCM_88270_A0)
  61877     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM88270_A0r */
  61878         soc_block_list[56],
  61879         soc_genreg,
  61880         1,
  61881         0,
  61882         0x2022500,
  61883         0,
  61884         0,
  61885         1,
  61886         soc_XLPORT_TS_TIMER_47_32_REG_BCM88270_A0r_fields,
  61887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61888         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61889         -1,
  61890         -1,
  61891     },
  61892 #endif /* chips */
  61893 
  61894 #if defined(BCM_88375_A0)
  61895     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM88375_A0r */
  61896         soc_block_list[56],
  61897         soc_genreg,
  61898         1,
  61899         0,
  61900         0x2022500,
  61901         0,
  61902         0,
  61903         1,
  61904         soc_XLPORT_TS_TIMER_47_32_REG_BCM88375_A0r_fields,
  61905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61906         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61907         -1,
  61908         -1,
  61909     },
  61910 #endif /* chips */
  61911 
  61912 #if defined(BCM_88375_B0)
  61913     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM88375_B0r */
  61914         soc_block_list[56],
  61915         soc_genreg,
  61916         1,
  61917         0,
  61918         0x2022500,
  61919         0,
  61920         0,
  61921         1,
  61922         soc_XLPORT_TS_TIMER_47_32_REG_BCM88375_B0r_fields,
  61923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61924         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61925         -1,
  61926         -1,
  61927     },
  61928 #endif /* chips */
  61929 
  61930 #if defined(BCM_88470_A0)
  61931     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM88470_A0r */
  61932         soc_block_list[56],
  61933         soc_genreg,
  61934         1,
  61935         0,
  61936         0x2022500,
  61937         0,
  61938         0,
  61939         1,
  61940         soc_XLPORT_TS_TIMER_47_32_REG_BCM88470_A0r_fields,
  61941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61942         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61943         -1,
  61944         -1,
  61945     },
  61946 #endif /* chips */
  61947 
  61948 #if defined(BCM_88470_B0)
  61949     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM88470_B0r */
  61950         soc_block_list[56],
  61951         soc_genreg,
  61952         1,
  61953         0,
  61954         0x2022500,
  61955         0,
  61956         0,
  61957         1,
  61958         soc_XLPORT_TS_TIMER_47_32_REG_BCM88470_B0r_fields,
  61959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61960         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61961         -1,
  61962         -1,
  61963     },
  61964 #endif /* chips */
  61965 
  61966 #if defined(BCM_88675_A0)
  61967     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM88675_A0r */
  61968         soc_block_list[56],
  61969         soc_genreg,
  61970         1,
  61971         0,
  61972         0x2022500,
  61973         0,
  61974         0,
  61975         1,
  61976         soc_XLPORT_TS_TIMER_47_32_REGr_fields,
  61977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61978         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61979         -1,
  61980         -1,
  61981     },
  61982 #endif /* chips */
  61983 
  61984 #if defined(BCM_88675_B0)
  61985     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM88675_B0r */
  61986         soc_block_list[56],
  61987         soc_genreg,
  61988         1,
  61989         0,
  61990         0x2022500,
  61991         0,
  61992         0,
  61993         1,
  61994         soc_XLPORT_TS_TIMER_47_32_REG_BCM88675_B0r_fields,
  61995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61996         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  61997         -1,
  61998         -1,
  61999     },
  62000 #endif /* chips */
  62001 
  62002 #if defined(BCM_88680_A0)
  62003     { /* SOC_REG_INT_XLPORT_TS_TIMER_47_32_REG_BCM88680_A0r */
  62004         soc_block_list[56],
  62005         soc_genreg,
  62006         1,
  62007         0,
  62008         0x2022500,
  62009         0,
  62010         0,
  62011         1,
  62012         soc_XLPORT_TS_TIMER_47_32_REG_BCM88680_A0r_fields,
  62013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62014         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62015         -1,
  62016         -1,
  62017     },
  62018 #endif /* chips */
  62019 
  62020 #if defined(BCM_56150_A0)
  62021     { /* SOC_REG_INT_XLPORT_TXFIFO0_ECC_STATUSr */
  62022         soc_block_list[16],
  62023         soc_genreg,
  62024         1,
  62025         0,
  62026         0x2022200,
  62027         0,
  62028         0,
  62029         4,
  62030         soc_XLPORT_TXFIFO0_ECC_STATUSr_fields,
  62031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62032         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62033         -1,
  62034         -1,
  62035     },
  62036 #endif /* chips */
  62037 
  62038 #if defined(BCM_56150_A0)
  62039     { /* SOC_REG_INT_XLPORT_TXFIFO1_ECC_STATUSr */
  62040         soc_block_list[16],
  62041         soc_genreg,
  62042         1,
  62043         0,
  62044         0x2022300,
  62045         0,
  62046         0,
  62047         4,
  62048         soc_XLPORT_TXFIFO0_ECC_STATUSr_fields,
  62049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62050         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62051         -1,
  62052         -1,
  62053     },
  62054 #endif /* chips */
  62055 
  62056 #if defined(BCM_56150_A0)
  62057     { /* SOC_REG_INT_XLPORT_TXFIFO2_ECC_STATUSr */
  62058         soc_block_list[16],
  62059         soc_genreg,
  62060         1,
  62061         0,
  62062         0x2022400,
  62063         0,
  62064         0,
  62065         4,
  62066         soc_XLPORT_TXFIFO0_ECC_STATUSr_fields,
  62067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62068         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62069         -1,
  62070         -1,
  62071     },
  62072 #endif /* chips */
  62073 
  62074 #if defined(BCM_56150_A0)
  62075     { /* SOC_REG_INT_XLPORT_TXFIFO3_ECC_STATUSr */
  62076         soc_block_list[16],
  62077         soc_genreg,
  62078         1,
  62079         0,
  62080         0x2022500,
  62081         0,
  62082         0,
  62083         4,
  62084         soc_XLPORT_TXFIFO0_ECC_STATUSr_fields,
  62085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62086         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62087         -1,
  62088         -1,
  62089     },
  62090 #endif /* chips */
  62091 
  62092 #if defined(BCM_56150_A0)
  62093     { /* SOC_REG_INT_XLPORT_TXFIFO_CTRLr */
  62094         soc_block_list[16],
  62095         soc_portreg,
  62096         1,
  62097         0,
  62098         0x20300,
  62099         0,
  62100         0,
  62101         3,
  62102         soc_XLPORT_TXFIFO_CTRLr_fields,
  62103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  62105         -1,
  62106         -1,
  62107     },
  62108 #endif /* chips */
  62109 
  62110 #if defined(BCM_56840_A0)
  62111     { /* SOC_REG_INT_XLPORT_TXFIFO_MEM_ECC_STATUSr */
  62112         soc_block_list[16],
  62113         soc_genreg,
  62114         1,
  62115         0,
  62116         0x8024e,
  62117         0,
  62118         0,
  62119         4,
  62120         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  62121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62122         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62123         -1,
  62124         -1,
  62125     },
  62126 #endif /* chips */
  62127 
  62128 #if defined(BCM_56840_B0)
  62129     { /* SOC_REG_INT_XLPORT_TXFIFO_MEM_ECC_STATUS_BCM56840_B0r */
  62130         soc_block_list[16],
  62131         soc_genreg,
  62132         1,
  62133         0,
  62134         0x8024e,
  62135         0,
  62136         0,
  62137         4,
  62138         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  62139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62140         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62141         -1,
  62142         -1,
  62143     },
  62144 #endif /* chips */
  62145 
  62146 #if defined(BCM_88732_A0)
  62147     { /* SOC_REG_INT_XLPORT_TXFIFO_MEM_ECC_STATUS_BCM88732_A0r */
  62148         soc_block_list[16],
  62149         soc_genreg,
  62150         1,
  62151         0,
  62152         0x8024e,
  62153         0,
  62154         0,
  62155         4,
  62156         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  62157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62158         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  62159         -1,
  62160         -1,
  62161     },
  62162 #endif /* chips */
  62163 
  62164 #if defined(BCM_56150_A0)
  62165     { /* SOC_REG_INT_XLPORT_TXFIFO_OVERFLOWr */
  62166         soc_block_list[16],
  62167         soc_genreg,
  62168         1,
  62169         0,
  62170         0x2022600,
  62171         SOC_REG_FLAG_RO,
  62172         0,
  62173         4,
  62174         soc_XLPORT_TXFIFO_OVERFLOWr_fields,
  62175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62176         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  62177         -1,
  62178         -1,
  62179     },
  62180 #endif /* chips */
  62181 
  62182 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62183     { /* SOC_REG_INT_XLPORT_TXPI_CSR_CTRL1r */
  62184         soc_block_list[16],
  62185         soc_genreg,
  62186         1,
  62187         0,
  62188         0x2024c00,
  62189         0,
  62190         0,
  62191         2,
  62192         soc_XLPORT_TXPI_CSR_CTRL1r_fields,
  62193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62194         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62195         -1,
  62196         -1,
  62197     },
  62198 #endif /* chips */
  62199 
  62200 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62201     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_ENr */
  62202         soc_block_list[16],
  62203         soc_genreg,
  62204         1,
  62205         0,
  62206         0x2023a00,
  62207         0,
  62208         0,
  62209         4,
  62210         soc_XLPORT_TXPI_CSR_OVER_ENr_fields,
  62211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62212         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  62213         -1,
  62214         -1,
  62215     },
  62216 #endif /* chips */
  62217 
  62218 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62219     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_EN_BCM56670_A0r */
  62220         soc_block_list[16],
  62221         soc_genreg,
  62222         1,
  62223         0,
  62224         0x2023a00,
  62225         0,
  62226         0,
  62227         4,
  62228         soc_XLPORT_TXPI_CSR_OVER_ENr_fields,
  62229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62230         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  62231         -1,
  62232         -1,
  62233     },
  62234 #endif /* chips */
  62235 
  62236 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62237     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_0_HIGHr */
  62238         soc_block_list[16],
  62239         soc_genreg,
  62240         1,
  62241         0,
  62242         0x2023c00,
  62243         0,
  62244         0,
  62245         1,
  62246         soc_XLPORT_TXPI_CSR_OVER_VAL_0_HIGHr_fields,
  62247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62248         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62249         -1,
  62250         -1,
  62251     },
  62252 #endif /* chips */
  62253 
  62254 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62255     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_0_HIGH_BCM56670_A0r */
  62256         soc_block_list[16],
  62257         soc_genreg,
  62258         1,
  62259         0,
  62260         0x2023c00,
  62261         0,
  62262         0,
  62263         1,
  62264         soc_XLPORT_TXPI_CSR_OVER_VAL_0_HIGHr_fields,
  62265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62266         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62267         -1,
  62268         -1,
  62269     },
  62270 #endif /* chips */
  62271 
  62272 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62273     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_0_LOWr */
  62274         soc_block_list[16],
  62275         soc_genreg,
  62276         1,
  62277         0,
  62278         0x2023b00,
  62279         0,
  62280         0,
  62281         1,
  62282         soc_XLPORT_TXPI_CSR_OVER_VAL_0_LOWr_fields,
  62283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62284         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62285         -1,
  62286         -1,
  62287     },
  62288 #endif /* chips */
  62289 
  62290 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62291     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_0_LOW_BCM56670_A0r */
  62292         soc_block_list[16],
  62293         soc_genreg,
  62294         1,
  62295         0,
  62296         0x2023b00,
  62297         0,
  62298         0,
  62299         1,
  62300         soc_XLPORT_TXPI_CSR_OVER_VAL_0_LOWr_fields,
  62301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62302         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62303         -1,
  62304         -1,
  62305     },
  62306 #endif /* chips */
  62307 
  62308 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62309     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_1_HIGHr */
  62310         soc_block_list[16],
  62311         soc_genreg,
  62312         1,
  62313         0,
  62314         0x2023e00,
  62315         0,
  62316         0,
  62317         1,
  62318         soc_XLPORT_TXPI_CSR_OVER_VAL_1_HIGHr_fields,
  62319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62320         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62321         -1,
  62322         -1,
  62323     },
  62324 #endif /* chips */
  62325 
  62326 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62327     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_1_HIGH_BCM56670_A0r */
  62328         soc_block_list[16],
  62329         soc_genreg,
  62330         1,
  62331         0,
  62332         0x2023e00,
  62333         0,
  62334         0,
  62335         1,
  62336         soc_XLPORT_TXPI_CSR_OVER_VAL_1_HIGHr_fields,
  62337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62338         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62339         -1,
  62340         -1,
  62341     },
  62342 #endif /* chips */
  62343 
  62344 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62345     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_1_LOWr */
  62346         soc_block_list[16],
  62347         soc_genreg,
  62348         1,
  62349         0,
  62350         0x2023d00,
  62351         0,
  62352         0,
  62353         1,
  62354         soc_XLPORT_TXPI_CSR_OVER_VAL_1_LOWr_fields,
  62355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62356         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62357         -1,
  62358         -1,
  62359     },
  62360 #endif /* chips */
  62361 
  62362 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62363     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_1_LOW_BCM56670_A0r */
  62364         soc_block_list[16],
  62365         soc_genreg,
  62366         1,
  62367         0,
  62368         0x2023d00,
  62369         0,
  62370         0,
  62371         1,
  62372         soc_XLPORT_TXPI_CSR_OVER_VAL_1_LOWr_fields,
  62373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62374         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62375         -1,
  62376         -1,
  62377     },
  62378 #endif /* chips */
  62379 
  62380 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62381     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_2_HIGHr */
  62382         soc_block_list[16],
  62383         soc_genreg,
  62384         1,
  62385         0,
  62386         0x2024000,
  62387         0,
  62388         0,
  62389         1,
  62390         soc_XLPORT_TXPI_CSR_OVER_VAL_2_HIGHr_fields,
  62391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62392         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62393         -1,
  62394         -1,
  62395     },
  62396 #endif /* chips */
  62397 
  62398 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62399     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_2_HIGH_BCM56670_A0r */
  62400         soc_block_list[16],
  62401         soc_genreg,
  62402         1,
  62403         0,
  62404         0x2024000,
  62405         0,
  62406         0,
  62407         1,
  62408         soc_XLPORT_TXPI_CSR_OVER_VAL_2_HIGHr_fields,
  62409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62410         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62411         -1,
  62412         -1,
  62413     },
  62414 #endif /* chips */
  62415 
  62416 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62417     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_2_LOWr */
  62418         soc_block_list[16],
  62419         soc_genreg,
  62420         1,
  62421         0,
  62422         0x2023f00,
  62423         0,
  62424         0,
  62425         1,
  62426         soc_XLPORT_TXPI_CSR_OVER_VAL_2_LOWr_fields,
  62427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62428         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62429         -1,
  62430         -1,
  62431     },
  62432 #endif /* chips */
  62433 
  62434 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62435     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_2_LOW_BCM56670_A0r */
  62436         soc_block_list[16],
  62437         soc_genreg,
  62438         1,
  62439         0,
  62440         0x2023f00,
  62441         0,
  62442         0,
  62443         1,
  62444         soc_XLPORT_TXPI_CSR_OVER_VAL_2_LOWr_fields,
  62445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62446         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62447         -1,
  62448         -1,
  62449     },
  62450 #endif /* chips */
  62451 
  62452 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62453     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_3_HIGHr */
  62454         soc_block_list[16],
  62455         soc_genreg,
  62456         1,
  62457         0,
  62458         0x2024200,
  62459         0,
  62460         0,
  62461         1,
  62462         soc_XLPORT_TXPI_CSR_OVER_VAL_3_HIGHr_fields,
  62463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62464         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62465         -1,
  62466         -1,
  62467     },
  62468 #endif /* chips */
  62469 
  62470 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62471     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_3_HIGH_BCM56670_A0r */
  62472         soc_block_list[16],
  62473         soc_genreg,
  62474         1,
  62475         0,
  62476         0x2024200,
  62477         0,
  62478         0,
  62479         1,
  62480         soc_XLPORT_TXPI_CSR_OVER_VAL_3_HIGHr_fields,
  62481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62482         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62483         -1,
  62484         -1,
  62485     },
  62486 #endif /* chips */
  62487 
  62488 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62489     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_3_LOWr */
  62490         soc_block_list[16],
  62491         soc_genreg,
  62492         1,
  62493         0,
  62494         0x2024100,
  62495         0,
  62496         0,
  62497         1,
  62498         soc_XLPORT_TXPI_CSR_OVER_VAL_3_LOWr_fields,
  62499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62500         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62501         -1,
  62502         -1,
  62503     },
  62504 #endif /* chips */
  62505 
  62506 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62507     { /* SOC_REG_INT_XLPORT_TXPI_CSR_OVER_VAL_3_LOW_BCM56670_A0r */
  62508         soc_block_list[16],
  62509         soc_genreg,
  62510         1,
  62511         0,
  62512         0x2024100,
  62513         0,
  62514         0,
  62515         1,
  62516         soc_XLPORT_TXPI_CSR_OVER_VAL_3_LOWr_fields,
  62517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62518         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62519         -1,
  62520         -1,
  62521     },
  62522 #endif /* chips */
  62523 
  62524 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62525     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_0_HIGHr */
  62526         soc_block_list[16],
  62527         soc_genreg,
  62528         1,
  62529         0,
  62530         0x2024400,
  62531         SOC_REG_FLAG_RO,
  62532         0,
  62533         1,
  62534         soc_XLPORT_TXPI_DATA_OUT_STS_0_HIGHr_fields,
  62535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62536         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62537         -1,
  62538         -1,
  62539     },
  62540 #endif /* chips */
  62541 
  62542 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62543     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_0_HIGH_BCM56670_A0r */
  62544         soc_block_list[16],
  62545         soc_genreg,
  62546         1,
  62547         0,
  62548         0x2024400,
  62549         SOC_REG_FLAG_RO,
  62550         0,
  62551         1,
  62552         soc_XLPORT_TXPI_DATA_OUT_STS_0_HIGHr_fields,
  62553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62554         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62555         -1,
  62556         -1,
  62557     },
  62558 #endif /* chips */
  62559 
  62560 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62561     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_0_LOWr */
  62562         soc_block_list[16],
  62563         soc_genreg,
  62564         1,
  62565         0,
  62566         0x2024300,
  62567         SOC_REG_FLAG_RO,
  62568         0,
  62569         1,
  62570         soc_XLPORT_TXPI_DATA_OUT_STS_0_LOWr_fields,
  62571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62572         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62573         -1,
  62574         -1,
  62575     },
  62576 #endif /* chips */
  62577 
  62578 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62579     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_0_LOW_BCM56670_A0r */
  62580         soc_block_list[16],
  62581         soc_genreg,
  62582         1,
  62583         0,
  62584         0x2024300,
  62585         SOC_REG_FLAG_RO,
  62586         0,
  62587         1,
  62588         soc_XLPORT_TXPI_DATA_OUT_STS_0_LOWr_fields,
  62589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62590         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62591         -1,
  62592         -1,
  62593     },
  62594 #endif /* chips */
  62595 
  62596 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62597     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_1_HIGHr */
  62598         soc_block_list[16],
  62599         soc_genreg,
  62600         1,
  62601         0,
  62602         0x2024600,
  62603         SOC_REG_FLAG_RO,
  62604         0,
  62605         1,
  62606         soc_XLPORT_TXPI_DATA_OUT_STS_1_HIGHr_fields,
  62607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62608         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62609         -1,
  62610         -1,
  62611     },
  62612 #endif /* chips */
  62613 
  62614 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62615     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_1_HIGH_BCM56670_A0r */
  62616         soc_block_list[16],
  62617         soc_genreg,
  62618         1,
  62619         0,
  62620         0x2024600,
  62621         SOC_REG_FLAG_RO,
  62622         0,
  62623         1,
  62624         soc_XLPORT_TXPI_DATA_OUT_STS_1_HIGHr_fields,
  62625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62626         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62627         -1,
  62628         -1,
  62629     },
  62630 #endif /* chips */
  62631 
  62632 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62633     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_1_LOWr */
  62634         soc_block_list[16],
  62635         soc_genreg,
  62636         1,
  62637         0,
  62638         0x2024500,
  62639         SOC_REG_FLAG_RO,
  62640         0,
  62641         1,
  62642         soc_XLPORT_TXPI_DATA_OUT_STS_1_LOWr_fields,
  62643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62644         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62645         -1,
  62646         -1,
  62647     },
  62648 #endif /* chips */
  62649 
  62650 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62651     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_1_LOW_BCM56670_A0r */
  62652         soc_block_list[16],
  62653         soc_genreg,
  62654         1,
  62655         0,
  62656         0x2024500,
  62657         SOC_REG_FLAG_RO,
  62658         0,
  62659         1,
  62660         soc_XLPORT_TXPI_DATA_OUT_STS_1_LOWr_fields,
  62661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62662         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62663         -1,
  62664         -1,
  62665     },
  62666 #endif /* chips */
  62667 
  62668 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62669     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_2_HIGHr */
  62670         soc_block_list[16],
  62671         soc_genreg,
  62672         1,
  62673         0,
  62674         0x2024800,
  62675         SOC_REG_FLAG_RO,
  62676         0,
  62677         1,
  62678         soc_XLPORT_TXPI_DATA_OUT_STS_2_HIGHr_fields,
  62679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62680         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62681         -1,
  62682         -1,
  62683     },
  62684 #endif /* chips */
  62685 
  62686 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62687     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_2_HIGH_BCM56670_A0r */
  62688         soc_block_list[16],
  62689         soc_genreg,
  62690         1,
  62691         0,
  62692         0x2024800,
  62693         SOC_REG_FLAG_RO,
  62694         0,
  62695         1,
  62696         soc_XLPORT_TXPI_DATA_OUT_STS_2_HIGHr_fields,
  62697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62698         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62699         -1,
  62700         -1,
  62701     },
  62702 #endif /* chips */
  62703 
  62704 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62705     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_2_LOWr */
  62706         soc_block_list[16],
  62707         soc_genreg,
  62708         1,
  62709         0,
  62710         0x2024700,
  62711         SOC_REG_FLAG_RO,
  62712         0,
  62713         1,
  62714         soc_XLPORT_TXPI_DATA_OUT_STS_2_LOWr_fields,
  62715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62716         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62717         -1,
  62718         -1,
  62719     },
  62720 #endif /* chips */
  62721 
  62722 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62723     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_2_LOW_BCM56670_A0r */
  62724         soc_block_list[16],
  62725         soc_genreg,
  62726         1,
  62727         0,
  62728         0x2024700,
  62729         SOC_REG_FLAG_RO,
  62730         0,
  62731         1,
  62732         soc_XLPORT_TXPI_DATA_OUT_STS_2_LOWr_fields,
  62733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62734         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62735         -1,
  62736         -1,
  62737     },
  62738 #endif /* chips */
  62739 
  62740 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62741     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_3_HIGHr */
  62742         soc_block_list[16],
  62743         soc_genreg,
  62744         1,
  62745         0,
  62746         0x2024a00,
  62747         SOC_REG_FLAG_RO,
  62748         0,
  62749         1,
  62750         soc_XLPORT_TXPI_DATA_OUT_STS_3_HIGHr_fields,
  62751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62752         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62753         -1,
  62754         -1,
  62755     },
  62756 #endif /* chips */
  62757 
  62758 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62759     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_3_HIGH_BCM56670_A0r */
  62760         soc_block_list[16],
  62761         soc_genreg,
  62762         1,
  62763         0,
  62764         0x2024a00,
  62765         SOC_REG_FLAG_RO,
  62766         0,
  62767         1,
  62768         soc_XLPORT_TXPI_DATA_OUT_STS_3_HIGHr_fields,
  62769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62770         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  62771         -1,
  62772         -1,
  62773     },
  62774 #endif /* chips */
  62775 
  62776 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62777     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_3_LOWr */
  62778         soc_block_list[16],
  62779         soc_genreg,
  62780         1,
  62781         0,
  62782         0x2024900,
  62783         SOC_REG_FLAG_RO,
  62784         0,
  62785         1,
  62786         soc_XLPORT_TXPI_DATA_OUT_STS_3_LOWr_fields,
  62787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62788         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62789         -1,
  62790         -1,
  62791     },
  62792 #endif /* chips */
  62793 
  62794 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62795     { /* SOC_REG_INT_XLPORT_TXPI_DATA_OUT_STS_3_LOW_BCM56670_A0r */
  62796         soc_block_list[16],
  62797         soc_genreg,
  62798         1,
  62799         0,
  62800         0x2024900,
  62801         SOC_REG_FLAG_RO,
  62802         0,
  62803         1,
  62804         soc_XLPORT_TXPI_DATA_OUT_STS_3_LOWr_fields,
  62805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62806         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  62807         -1,
  62808         -1,
  62809     },
  62810 #endif /* chips */
  62811 
  62812 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62813     { /* SOC_REG_INT_XLPORT_TXPI_LANE_SELECTIONr */
  62814         soc_block_list[16],
  62815         soc_genreg,
  62816         1,
  62817         0,
  62818         0x2024b00,
  62819         0,
  62820         0,
  62821         4,
  62822         soc_XLPORT_TXPI_LANE_SELECTIONr_fields,
  62823         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
  62824         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  62825         -1,
  62826         -1,
  62827     },
  62828 #endif /* chips */
  62829 
  62830 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  62831     { /* SOC_REG_INT_XLPORT_TXPI_LANE_SELECTION_BCM56670_A0r */
  62832         soc_block_list[16],
  62833         soc_genreg,
  62834         1,
  62835         0,
  62836         0x2024b00,
  62837         0,
  62838         0,
  62839         4,
  62840         soc_XLPORT_TXPI_LANE_SELECTIONr_fields,
  62841         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
  62842         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  62843         -1,
  62844         -1,
  62845     },
  62846 #endif /* chips */
  62847 
  62848 #if defined(BCM_56840_A0)
  62849     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRLr */
  62850         soc_block_list[16],
  62851         soc_genreg,
  62852         1,
  62853         0,
  62854         0x80241,
  62855         0,
  62856         0,
  62857         7,
  62858         soc_XLPORT_WC_UCMEM_CTRLr_fields,
  62859         SOC_RESET_VAL_DEC(0x0002a900, 0x00000000)
  62860         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  62861         -1,
  62862         -1,
  62863     },
  62864 #endif /* chips */
  62865 
  62866 #if defined(BCM_2801PM_A0)
  62867     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM2801PM_A0r */
  62868         soc_block_list[56],
  62869         soc_genreg,
  62870         1,
  62871         0,
  62872         0x2021900,
  62873         0,
  62874         0,
  62875         2,
  62876         soc_CLPORT_WC_UCMEM_CTRLr_fields,
  62877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62878         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  62879         -1,
  62880         -1,
  62881     },
  62882 #endif /* chips */
  62883 
  62884 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  62885     defined(BCM_56670_B0)
  62886     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r */
  62887         soc_block_list[16],
  62888         soc_genreg,
  62889         1,
  62890         0,
  62891         0x2021900,
  62892         0,
  62893         0,
  62894         2,
  62895         soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields,
  62896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62897         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  62898         -1,
  62899         -1,
  62900     },
  62901 #endif /* chips */
  62902 
  62903 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  62904     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM53570_A0r */
  62905         soc_block_list[16],
  62906         soc_genreg,
  62907         1,
  62908         0,
  62909         0x2021900,
  62910         0,
  62911         0,
  62912         2,
  62913         soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields,
  62914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62915         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  62916         -1,
  62917         -1,
  62918     },
  62919 #endif /* chips */
  62920 
  62921 #if defined(BCM_56150_A0)
  62922     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM56150_A0r */
  62923         soc_block_list[16],
  62924         soc_genreg,
  62925         1,
  62926         0,
  62927         0x2021900,
  62928         0,
  62929         0,
  62930         2,
  62931         soc_XLPORT_WC_UCMEM_CTRL_BCM56850_A0r_fields,
  62932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62933         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  62934         -1,
  62935         -1,
  62936     },
  62937 #endif /* chips */
  62938 
  62939 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  62940     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM56160_A0r */
  62941         soc_block_list[16],
  62942         soc_genreg,
  62943         1,
  62944         0,
  62945         0x2021900,
  62946         0,
  62947         0,
  62948         2,
  62949         soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields,
  62950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62951         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  62952         -1,
  62953         -1,
  62954     },
  62955 #endif /* chips */
  62956 
  62957 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  62958     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM56260_A0r */
  62959         soc_block_list[16],
  62960         soc_genreg,
  62961         1,
  62962         0,
  62963         0x2021900,
  62964         0,
  62965         0,
  62966         2,
  62967         soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields,
  62968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62969         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  62970         -1,
  62971         -1,
  62972     },
  62973 #endif /* chips */
  62974 
  62975 #if defined(BCM_56370_A0)
  62976     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM56370_A0r */
  62977         soc_block_list[16],
  62978         soc_genreg,
  62979         1,
  62980         0,
  62981         0x2021900,
  62982         0,
  62983         0,
  62984         2,
  62985         soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields,
  62986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62987         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  62988         -1,
  62989         -1,
  62990         3,
  62991     },
  62992 #endif /* chips */
  62993 
  62994 #if defined(BCM_56560_A0)
  62995     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM56560_A0r */
  62996         soc_block_list[217],
  62997         soc_genreg,
  62998         1,
  62999         0,
  63000         0x2021900,
  63001         0,
  63002         0,
  63003         2,
  63004         soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields,
  63005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63006         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63007         -1,
  63008         -1,
  63009     },
  63010 #endif /* chips */
  63011 
  63012 #if defined(BCM_56560_B0)
  63013     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM56560_B0r */
  63014         soc_block_list[16],
  63015         soc_genreg,
  63016         1,
  63017         0,
  63018         0x2021900,
  63019         0,
  63020         0,
  63021         2,
  63022         soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields,
  63023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63024         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63025         -1,
  63026         -1,
  63027     },
  63028 #endif /* chips */
  63029 
  63030 #if defined(BCM_56840_B0)
  63031     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM56840_B0r */
  63032         soc_block_list[16],
  63033         soc_genreg,
  63034         1,
  63035         0,
  63036         0x80241,
  63037         0,
  63038         0,
  63039         7,
  63040         soc_XLPORT_WC_UCMEM_CTRLr_fields,
  63041         SOC_RESET_VAL_DEC(0x0002a900, 0x00000000)
  63042         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  63043         -1,
  63044         -1,
  63045     },
  63046 #endif /* chips */
  63047 
  63048 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  63049     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM56850_A0r */
  63050         soc_block_list[16],
  63051         soc_genreg,
  63052         1,
  63053         0,
  63054         0x2021400,
  63055         0,
  63056         0,
  63057         2,
  63058         soc_XLPORT_WC_UCMEM_CTRL_BCM56850_A0r_fields,
  63059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63060         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63061         -1,
  63062         -1,
  63063     },
  63064 #endif /* chips */
  63065 
  63066 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  63067     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  63068     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  63069     defined(BCM_56980_B0)
  63070     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM56960_A0r */
  63071         soc_block_list[16],
  63072         soc_genreg,
  63073         1,
  63074         0,
  63075         0x2021900,
  63076         0,
  63077         0,
  63078         2,
  63079         soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields,
  63080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63081         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63082         -1,
  63083         -1,
  63084         3,
  63085     },
  63086 #endif /* chips */
  63087 
  63088 #if defined(BCM_88270_A0)
  63089     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM88270_A0r */
  63090         soc_block_list[56],
  63091         soc_genreg,
  63092         1,
  63093         0,
  63094         0x2021900,
  63095         0,
  63096         0,
  63097         2,
  63098         soc_XLPORT_WC_UCMEM_CTRL_BCM88270_A0r_fields,
  63099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63100         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63101         -1,
  63102         -1,
  63103     },
  63104 #endif /* chips */
  63105 
  63106 #if defined(BCM_88375_A0)
  63107     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM88375_A0r */
  63108         soc_block_list[56],
  63109         soc_genreg,
  63110         1,
  63111         0,
  63112         0x2021900,
  63113         0,
  63114         0,
  63115         2,
  63116         soc_XLPORT_WC_UCMEM_CTRL_BCM88375_A0r_fields,
  63117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63118         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63119         -1,
  63120         -1,
  63121     },
  63122 #endif /* chips */
  63123 
  63124 #if defined(BCM_88375_B0)
  63125     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM88375_B0r */
  63126         soc_block_list[56],
  63127         soc_genreg,
  63128         1,
  63129         0,
  63130         0x2021900,
  63131         0,
  63132         0,
  63133         2,
  63134         soc_XLPORT_WC_UCMEM_CTRL_BCM88375_B0r_fields,
  63135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63136         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63137         -1,
  63138         -1,
  63139     },
  63140 #endif /* chips */
  63141 
  63142 #if defined(BCM_88470_A0)
  63143     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM88470_A0r */
  63144         soc_block_list[56],
  63145         soc_genreg,
  63146         1,
  63147         0,
  63148         0x2021900,
  63149         0,
  63150         0,
  63151         2,
  63152         soc_XLPORT_WC_UCMEM_CTRL_BCM88470_A0r_fields,
  63153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63154         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63155         -1,
  63156         -1,
  63157     },
  63158 #endif /* chips */
  63159 
  63160 #if defined(BCM_88470_B0)
  63161     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM88470_B0r */
  63162         soc_block_list[56],
  63163         soc_genreg,
  63164         1,
  63165         0,
  63166         0x2021900,
  63167         0,
  63168         0,
  63169         2,
  63170         soc_XLPORT_WC_UCMEM_CTRL_BCM88470_B0r_fields,
  63171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63172         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63173         -1,
  63174         -1,
  63175     },
  63176 #endif /* chips */
  63177 
  63178 #if defined(BCM_88675_A0)
  63179     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM88675_A0r */
  63180         soc_block_list[56],
  63181         soc_genreg,
  63182         1,
  63183         0,
  63184         0x2021900,
  63185         0,
  63186         0,
  63187         2,
  63188         soc_XLPORT_WC_UCMEM_CTRL_BCM88675_A0r_fields,
  63189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63190         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63191         -1,
  63192         -1,
  63193     },
  63194 #endif /* chips */
  63195 
  63196 #if defined(BCM_88675_B0)
  63197     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM88675_B0r */
  63198         soc_block_list[56],
  63199         soc_genreg,
  63200         1,
  63201         0,
  63202         0x2021900,
  63203         0,
  63204         0,
  63205         2,
  63206         soc_XLPORT_WC_UCMEM_CTRL_BCM88675_B0r_fields,
  63207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63208         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63209         -1,
  63210         -1,
  63211     },
  63212 #endif /* chips */
  63213 
  63214 #if defined(BCM_88680_A0)
  63215     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM88680_A0r */
  63216         soc_block_list[56],
  63217         soc_genreg,
  63218         1,
  63219         0,
  63220         0x2021900,
  63221         0,
  63222         0,
  63223         2,
  63224         soc_XLPORT_WC_UCMEM_CTRL_BCM88680_A0r_fields,
  63225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63226         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63227         -1,
  63228         -1,
  63229     },
  63230 #endif /* chips */
  63231 
  63232 #if defined(BCM_88732_A0)
  63233     { /* SOC_REG_INT_XLPORT_WC_UCMEM_CTRL_BCM88732_A0r */
  63234         soc_block_list[16],
  63235         soc_genreg,
  63236         1,
  63237         0,
  63238         0x80241,
  63239         0,
  63240         0,
  63241         7,
  63242         soc_XLPORT_WC_UCMEM_CTRLr_fields,
  63243         SOC_RESET_VAL_DEC(0x0002a900, 0x00000000)
  63244         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  63245         -1,
  63246         -1,
  63247     },
  63248 #endif /* chips */
  63249 
  63250 #if defined(BCM_2801PM_A0)
  63251     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REGr */
  63252         soc_block_list[56],
  63253         soc_genreg,
  63254         1,
  63255         0,
  63256         0x2021400,
  63257         0,
  63258         0,
  63259         5,
  63260         soc_CLPORT_XGXS0_CTRL_REGr_fields,
  63261         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  63262         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63263         -1,
  63264         -1,
  63265     },
  63266 #endif /* chips */
  63267 
  63268 #if defined(BCM_53400_A0)
  63269     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM53400_A0r */
  63270         soc_block_list[16],
  63271         soc_genreg,
  63272         1,
  63273         0,
  63274         0x2021400,
  63275         0,
  63276         0,
  63277         5,
  63278         soc_XLPORT_XGXS0_CTRL_REG_BCM53400_A0r_fields,
  63279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63280         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63281         -1,
  63282         -1,
  63283     },
  63284 #endif /* chips */
  63285 
  63286 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  63287     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM53570_A0r */
  63288         soc_block_list[16],
  63289         soc_genreg,
  63290         1,
  63291         0,
  63292         0x2021400,
  63293         0,
  63294         0,
  63295         15,
  63296         soc_XLPORT_XGXS0_CTRL_REG_BCM53570_A0r_fields,
  63297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63298         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63299         -1,
  63300         -1,
  63301     },
  63302 #endif /* chips */
  63303 
  63304 #if defined(BCM_56150_A0)
  63305     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM56150_A0r */
  63306         soc_block_list[16],
  63307         soc_genreg,
  63308         1,
  63309         0,
  63310         0x2021400,
  63311         0,
  63312         0,
  63313         9,
  63314         soc_XLPORT_XGXS0_CTRL_REG_BCM56850_A0r_fields,
  63315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63316         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63317         -1,
  63318         -1,
  63319     },
  63320 #endif /* chips */
  63321 
  63322 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  63323     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM56160_A0r */
  63324         soc_block_list[16],
  63325         soc_genreg,
  63326         1,
  63327         0,
  63328         0x2021400,
  63329         0,
  63330         0,
  63331         5,
  63332         soc_XLPORT_XGXS0_CTRL_REG_BCM53400_A0r_fields,
  63333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63334         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63335         -1,
  63336         -1,
  63337     },
  63338 #endif /* chips */
  63339 
  63340 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  63341     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM56260_A0r */
  63342         soc_block_list[16],
  63343         soc_genreg,
  63344         1,
  63345         0,
  63346         0x2021400,
  63347         0,
  63348         0,
  63349         5,
  63350         soc_XLPORT_XGXS0_CTRL_REG_BCM53400_A0r_fields,
  63351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63352         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63353         -1,
  63354         -1,
  63355     },
  63356 #endif /* chips */
  63357 
  63358 #if defined(BCM_56370_A0)
  63359     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM56370_A0r */
  63360         soc_block_list[16],
  63361         soc_genreg,
  63362         1,
  63363         0,
  63364         0x2021400,
  63365         0,
  63366         0,
  63367         9,
  63368         soc_XLPORT_XGXS0_CTRL_REG_BCM56980_A0r_fields,
  63369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63370         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63371         -1,
  63372         -1,
  63373         3,
  63374     },
  63375 #endif /* chips */
  63376 
  63377 #if defined(BCM_56560_A0)
  63378     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM56560_A0r */
  63379         soc_block_list[217],
  63380         soc_genreg,
  63381         1,
  63382         0,
  63383         0x2021400,
  63384         0,
  63385         0,
  63386         5,
  63387         soc_XLPORT_XGXS0_CTRL_REG_BCM53400_A0r_fields,
  63388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63389         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63390         -1,
  63391         -1,
  63392     },
  63393 #endif /* chips */
  63394 
  63395 #if defined(BCM_56560_B0)
  63396     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM56560_B0r */
  63397         soc_block_list[16],
  63398         soc_genreg,
  63399         1,
  63400         0,
  63401         0x2021400,
  63402         0,
  63403         0,
  63404         5,
  63405         soc_XLPORT_XGXS0_CTRL_REG_BCM53400_A0r_fields,
  63406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63408         -1,
  63409         -1,
  63410     },
  63411 #endif /* chips */
  63412 
  63413 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  63414     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM56670_A0r */
  63415         soc_block_list[16],
  63416         soc_genreg,
  63417         1,
  63418         0,
  63419         0x2021400,
  63420         0,
  63421         0,
  63422         15,
  63423         soc_XLPORT_XGXS0_CTRL_REG_BCM53570_A0r_fields,
  63424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63425         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63426         -1,
  63427         -1,
  63428     },
  63429 #endif /* chips */
  63430 
  63431 #if defined(BCM_56850_A0)
  63432     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM56850_A0r */
  63433         soc_block_list[16],
  63434         soc_genreg,
  63435         1,
  63436         0,
  63437         0x2020f00,
  63438         0,
  63439         0,
  63440         9,
  63441         soc_XLPORT_XGXS0_CTRL_REG_BCM56850_A0r_fields,
  63442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63443         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63444         -1,
  63445         -1,
  63446     },
  63447 #endif /* chips */
  63448 
  63449 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  63450     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM56960_A0r */
  63451         soc_block_list[16],
  63452         soc_genreg,
  63453         1,
  63454         0,
  63455         0x2021400,
  63456         0,
  63457         0,
  63458         5,
  63459         soc_XLPORT_XGXS0_CTRL_REG_BCM53400_A0r_fields,
  63460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63461         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63462         -1,
  63463         -1,
  63464         3,
  63465     },
  63466 #endif /* chips */
  63467 
  63468 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  63469     defined(BCM_56970_A0)
  63470     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM56970_A0r */
  63471         soc_block_list[16],
  63472         soc_genreg,
  63473         1,
  63474         0,
  63475         0x2021400,
  63476         0,
  63477         0,
  63478         9,
  63479         soc_XLPORT_XGXS0_CTRL_REG_BCM56970_A0r_fields,
  63480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63481         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63482         -1,
  63483         -1,
  63484         3,
  63485     },
  63486 #endif /* chips */
  63487 
  63488 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  63489     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM56980_A0r */
  63490         soc_block_list[16],
  63491         soc_genreg,
  63492         1,
  63493         0,
  63494         0x2021400,
  63495         0,
  63496         0,
  63497         9,
  63498         soc_XLPORT_XGXS0_CTRL_REG_BCM56980_A0r_fields,
  63499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63500         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63501         -1,
  63502         -1,
  63503         3,
  63504     },
  63505 #endif /* chips */
  63506 
  63507 #if defined(BCM_88270_A0)
  63508     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM88270_A0r */
  63509         soc_block_list[56],
  63510         soc_genreg,
  63511         1,
  63512         0,
  63513         0x2021400,
  63514         0,
  63515         0,
  63516         5,
  63517         soc_XLPORT_XGXS0_CTRL_REG_BCM88270_A0r_fields,
  63518         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  63519         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63520         -1,
  63521         -1,
  63522     },
  63523 #endif /* chips */
  63524 
  63525 #if defined(BCM_88375_A0)
  63526     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM88375_A0r */
  63527         soc_block_list[56],
  63528         soc_genreg,
  63529         1,
  63530         0,
  63531         0x2021400,
  63532         0,
  63533         0,
  63534         5,
  63535         soc_XLPORT_XGXS0_CTRL_REG_BCM88375_A0r_fields,
  63536         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  63537         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63538         -1,
  63539         -1,
  63540     },
  63541 #endif /* chips */
  63542 
  63543 #if defined(BCM_88375_B0)
  63544     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM88375_B0r */
  63545         soc_block_list[56],
  63546         soc_genreg,
  63547         1,
  63548         0,
  63549         0x2021400,
  63550         0,
  63551         0,
  63552         5,
  63553         soc_XLPORT_XGXS0_CTRL_REG_BCM88375_B0r_fields,
  63554         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  63555         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63556         -1,
  63557         -1,
  63558     },
  63559 #endif /* chips */
  63560 
  63561 #if defined(BCM_88470_A0)
  63562     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM88470_A0r */
  63563         soc_block_list[56],
  63564         soc_genreg,
  63565         1,
  63566         0,
  63567         0x2021400,
  63568         0,
  63569         0,
  63570         5,
  63571         soc_XLPORT_XGXS0_CTRL_REG_BCM88470_A0r_fields,
  63572         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  63573         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63574         -1,
  63575         -1,
  63576     },
  63577 #endif /* chips */
  63578 
  63579 #if defined(BCM_88470_B0)
  63580     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM88470_B0r */
  63581         soc_block_list[56],
  63582         soc_genreg,
  63583         1,
  63584         0,
  63585         0x2021400,
  63586         0,
  63587         0,
  63588         5,
  63589         soc_XLPORT_XGXS0_CTRL_REG_BCM88470_B0r_fields,
  63590         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  63591         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63592         -1,
  63593         -1,
  63594     },
  63595 #endif /* chips */
  63596 
  63597 #if defined(BCM_88675_A0)
  63598     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM88675_A0r */
  63599         soc_block_list[56],
  63600         soc_genreg,
  63601         1,
  63602         0,
  63603         0x2021400,
  63604         0,
  63605         0,
  63606         5,
  63607         soc_XLPORT_XGXS0_CTRL_REGr_fields,
  63608         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  63609         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63610         -1,
  63611         -1,
  63612     },
  63613 #endif /* chips */
  63614 
  63615 #if defined(BCM_88675_B0)
  63616     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM88675_B0r */
  63617         soc_block_list[56],
  63618         soc_genreg,
  63619         1,
  63620         0,
  63621         0x2021400,
  63622         0,
  63623         0,
  63624         5,
  63625         soc_XLPORT_XGXS0_CTRL_REG_BCM88675_B0r_fields,
  63626         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  63627         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63628         -1,
  63629         -1,
  63630     },
  63631 #endif /* chips */
  63632 
  63633 #if defined(BCM_88680_A0)
  63634     { /* SOC_REG_INT_XLPORT_XGXS0_CTRL_REG_BCM88680_A0r */
  63635         soc_block_list[56],
  63636         soc_genreg,
  63637         1,
  63638         0,
  63639         0x2021400,
  63640         0,
  63641         0,
  63642         5,
  63643         soc_XLPORT_XGXS0_CTRL_REG_BCM88680_A0r_fields,
  63644         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  63645         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  63646         -1,
  63647         -1,
  63648     },
  63649 #endif /* chips */
  63650 
  63651 #if defined(BCM_2801PM_A0)
  63652     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REGr */
  63653         soc_block_list[56],
  63654         soc_genreg,
  63655         1,
  63656         0,
  63657         0x2021500,
  63658         SOC_REG_FLAG_RO,
  63659         0,
  63660         3,
  63661         soc_CLPORT_XGXS0_LN0_STATUS0_REGr_fields,
  63662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63663         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63664         -1,
  63665         -1,
  63666     },
  63667 #endif /* chips */
  63668 
  63669 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  63670     defined(BCM_56670_B0)
  63671     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r */
  63672         soc_block_list[16],
  63673         soc_genreg,
  63674         1,
  63675         0,
  63676         0x2021500,
  63677         SOC_REG_FLAG_RO,
  63678         0,
  63679         3,
  63680         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  63681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63682         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63683         -1,
  63684         -1,
  63685     },
  63686 #endif /* chips */
  63687 
  63688 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  63689     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53570_A0r */
  63690         soc_block_list[16],
  63691         soc_genreg,
  63692         1,
  63693         0,
  63694         0x2021500,
  63695         SOC_REG_FLAG_RO,
  63696         0,
  63697         3,
  63698         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  63699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63700         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63701         -1,
  63702         -1,
  63703     },
  63704 #endif /* chips */
  63705 
  63706 #if defined(BCM_56150_A0)
  63707     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56150_A0r */
  63708         soc_block_list[16],
  63709         soc_genreg,
  63710         1,
  63711         0,
  63712         0x2021500,
  63713         SOC_REG_FLAG_RO,
  63714         0,
  63715         3,
  63716         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56850_A0r_fields,
  63717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63718         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63719         -1,
  63720         -1,
  63721     },
  63722 #endif /* chips */
  63723 
  63724 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  63725     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56160_A0r */
  63726         soc_block_list[16],
  63727         soc_genreg,
  63728         1,
  63729         0,
  63730         0x2021500,
  63731         SOC_REG_FLAG_RO,
  63732         0,
  63733         3,
  63734         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  63735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63736         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63737         -1,
  63738         -1,
  63739     },
  63740 #endif /* chips */
  63741 
  63742 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  63743     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56260_A0r */
  63744         soc_block_list[16],
  63745         soc_genreg,
  63746         1,
  63747         0,
  63748         0x2021500,
  63749         SOC_REG_FLAG_RO,
  63750         0,
  63751         3,
  63752         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  63753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63754         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63755         -1,
  63756         -1,
  63757     },
  63758 #endif /* chips */
  63759 
  63760 #if defined(BCM_56370_A0)
  63761     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56370_A0r */
  63762         soc_block_list[16],
  63763         soc_genreg,
  63764         1,
  63765         0,
  63766         0x2021500,
  63767         SOC_REG_FLAG_RO,
  63768         0,
  63769         3,
  63770         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  63771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63772         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63773         -1,
  63774         -1,
  63775         3,
  63776     },
  63777 #endif /* chips */
  63778 
  63779 #if defined(BCM_56560_A0)
  63780     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56560_A0r */
  63781         soc_block_list[217],
  63782         soc_genreg,
  63783         1,
  63784         0,
  63785         0x2021500,
  63786         SOC_REG_FLAG_RO,
  63787         0,
  63788         3,
  63789         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  63790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63791         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63792         -1,
  63793         -1,
  63794     },
  63795 #endif /* chips */
  63796 
  63797 #if defined(BCM_56560_B0)
  63798     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56560_B0r */
  63799         soc_block_list[16],
  63800         soc_genreg,
  63801         1,
  63802         0,
  63803         0x2021500,
  63804         SOC_REG_FLAG_RO,
  63805         0,
  63806         3,
  63807         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  63808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63809         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63810         -1,
  63811         -1,
  63812     },
  63813 #endif /* chips */
  63814 
  63815 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  63816     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56850_A0r */
  63817         soc_block_list[16],
  63818         soc_genreg,
  63819         1,
  63820         0,
  63821         0x2021000,
  63822         SOC_REG_FLAG_RO,
  63823         0,
  63824         3,
  63825         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56850_A0r_fields,
  63826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63827         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63828         -1,
  63829         -1,
  63830     },
  63831 #endif /* chips */
  63832 
  63833 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  63834     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  63835     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  63836     defined(BCM_56980_B0)
  63837     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56960_A0r */
  63838         soc_block_list[16],
  63839         soc_genreg,
  63840         1,
  63841         0,
  63842         0x2021500,
  63843         SOC_REG_FLAG_RO,
  63844         0,
  63845         3,
  63846         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  63847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63848         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  63849         -1,
  63850         -1,
  63851         3,
  63852     },
  63853 #endif /* chips */
  63854 
  63855 #if defined(BCM_88270_A0)
  63856     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88270_A0r */
  63857         soc_block_list[56],
  63858         soc_genreg,
  63859         1,
  63860         0,
  63861         0x2021500,
  63862         SOC_REG_FLAG_RO,
  63863         0,
  63864         3,
  63865         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88270_A0r_fields,
  63866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63867         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63868         -1,
  63869         -1,
  63870     },
  63871 #endif /* chips */
  63872 
  63873 #if defined(BCM_88375_A0)
  63874     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88375_A0r */
  63875         soc_block_list[56],
  63876         soc_genreg,
  63877         1,
  63878         0,
  63879         0x2021500,
  63880         SOC_REG_FLAG_RO,
  63881         0,
  63882         3,
  63883         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88375_A0r_fields,
  63884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63885         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63886         -1,
  63887         -1,
  63888     },
  63889 #endif /* chips */
  63890 
  63891 #if defined(BCM_88375_B0)
  63892     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88375_B0r */
  63893         soc_block_list[56],
  63894         soc_genreg,
  63895         1,
  63896         0,
  63897         0x2021500,
  63898         SOC_REG_FLAG_RO,
  63899         0,
  63900         3,
  63901         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88375_B0r_fields,
  63902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63903         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63904         -1,
  63905         -1,
  63906     },
  63907 #endif /* chips */
  63908 
  63909 #if defined(BCM_88470_A0)
  63910     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88470_A0r */
  63911         soc_block_list[56],
  63912         soc_genreg,
  63913         1,
  63914         0,
  63915         0x2021500,
  63916         SOC_REG_FLAG_RO,
  63917         0,
  63918         3,
  63919         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88470_A0r_fields,
  63920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63921         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63922         -1,
  63923         -1,
  63924     },
  63925 #endif /* chips */
  63926 
  63927 #if defined(BCM_88470_B0)
  63928     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88470_B0r */
  63929         soc_block_list[56],
  63930         soc_genreg,
  63931         1,
  63932         0,
  63933         0x2021500,
  63934         SOC_REG_FLAG_RO,
  63935         0,
  63936         3,
  63937         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88470_B0r_fields,
  63938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63939         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63940         -1,
  63941         -1,
  63942     },
  63943 #endif /* chips */
  63944 
  63945 #if defined(BCM_88675_A0)
  63946     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88675_A0r */
  63947         soc_block_list[56],
  63948         soc_genreg,
  63949         1,
  63950         0,
  63951         0x2021500,
  63952         SOC_REG_FLAG_RO,
  63953         0,
  63954         3,
  63955         soc_XLPORT_XGXS0_LN0_STATUS0_REGr_fields,
  63956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63957         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63958         -1,
  63959         -1,
  63960     },
  63961 #endif /* chips */
  63962 
  63963 #if defined(BCM_88675_B0)
  63964     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88675_B0r */
  63965         soc_block_list[56],
  63966         soc_genreg,
  63967         1,
  63968         0,
  63969         0x2021500,
  63970         SOC_REG_FLAG_RO,
  63971         0,
  63972         3,
  63973         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88675_B0r_fields,
  63974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63975         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63976         -1,
  63977         -1,
  63978     },
  63979 #endif /* chips */
  63980 
  63981 #if defined(BCM_88680_A0)
  63982     { /* SOC_REG_INT_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88680_A0r */
  63983         soc_block_list[56],
  63984         soc_genreg,
  63985         1,
  63986         0,
  63987         0x2021500,
  63988         SOC_REG_FLAG_RO,
  63989         0,
  63990         3,
  63991         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88680_A0r_fields,
  63992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63993         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63994         -1,
  63995         -1,
  63996     },
  63997 #endif /* chips */
  63998 
  63999 #if defined(BCM_2801PM_A0)
  64000     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REGr */
  64001         soc_block_list[56],
  64002         soc_genreg,
  64003         1,
  64004         0,
  64005         0x2021600,
  64006         SOC_REG_FLAG_RO |
  64007                           SOC_REG_FLAG_SIGNAL,
  64008         0,
  64009         3,
  64010         soc_CLPORT_XGXS0_LN0_STATUS0_REGr_fields,
  64011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64012         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64013         -1,
  64014         -1,
  64015     },
  64016 #endif /* chips */
  64017 
  64018 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  64019     defined(BCM_56670_B0)
  64020     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM53400_A0r */
  64021         soc_block_list[16],
  64022         soc_genreg,
  64023         1,
  64024         0,
  64025         0x2021600,
  64026         SOC_REG_FLAG_RO,
  64027         0,
  64028         3,
  64029         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64032         -1,
  64033         -1,
  64034     },
  64035 #endif /* chips */
  64036 
  64037 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  64038     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM53570_A0r */
  64039         soc_block_list[16],
  64040         soc_genreg,
  64041         1,
  64042         0,
  64043         0x2021600,
  64044         SOC_REG_FLAG_RO,
  64045         0,
  64046         3,
  64047         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64049         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64050         -1,
  64051         -1,
  64052     },
  64053 #endif /* chips */
  64054 
  64055 #if defined(BCM_56150_A0)
  64056     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM56150_A0r */
  64057         soc_block_list[16],
  64058         soc_genreg,
  64059         1,
  64060         0,
  64061         0x2021600,
  64062         SOC_REG_FLAG_RO,
  64063         0,
  64064         3,
  64065         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56850_A0r_fields,
  64066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64067         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64068         -1,
  64069         -1,
  64070     },
  64071 #endif /* chips */
  64072 
  64073 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  64074     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM56160_A0r */
  64075         soc_block_list[16],
  64076         soc_genreg,
  64077         1,
  64078         0,
  64079         0x2021600,
  64080         SOC_REG_FLAG_RO,
  64081         0,
  64082         3,
  64083         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64085         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64086         -1,
  64087         -1,
  64088     },
  64089 #endif /* chips */
  64090 
  64091 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64092     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM56260_A0r */
  64093         soc_block_list[16],
  64094         soc_genreg,
  64095         1,
  64096         0,
  64097         0x2021600,
  64098         SOC_REG_FLAG_RO,
  64099         0,
  64100         3,
  64101         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64103         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64104         -1,
  64105         -1,
  64106     },
  64107 #endif /* chips */
  64108 
  64109 #if defined(BCM_56370_A0)
  64110     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM56370_A0r */
  64111         soc_block_list[16],
  64112         soc_genreg,
  64113         1,
  64114         0,
  64115         0x2021600,
  64116         SOC_REG_FLAG_RO,
  64117         0,
  64118         3,
  64119         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64121         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64122         -1,
  64123         -1,
  64124         3,
  64125     },
  64126 #endif /* chips */
  64127 
  64128 #if defined(BCM_56560_A0)
  64129     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM56560_A0r */
  64130         soc_block_list[217],
  64131         soc_genreg,
  64132         1,
  64133         0,
  64134         0x2021600,
  64135         SOC_REG_FLAG_RO,
  64136         0,
  64137         3,
  64138         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64140         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64141         -1,
  64142         -1,
  64143     },
  64144 #endif /* chips */
  64145 
  64146 #if defined(BCM_56560_B0)
  64147     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM56560_B0r */
  64148         soc_block_list[16],
  64149         soc_genreg,
  64150         1,
  64151         0,
  64152         0x2021600,
  64153         SOC_REG_FLAG_RO,
  64154         0,
  64155         3,
  64156         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64158         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64159         -1,
  64160         -1,
  64161     },
  64162 #endif /* chips */
  64163 
  64164 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  64165     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM56850_A0r */
  64166         soc_block_list[16],
  64167         soc_genreg,
  64168         1,
  64169         0,
  64170         0x2021100,
  64171         SOC_REG_FLAG_RO,
  64172         0,
  64173         3,
  64174         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56850_A0r_fields,
  64175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64176         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64177         -1,
  64178         -1,
  64179     },
  64180 #endif /* chips */
  64181 
  64182 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  64183     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  64184     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  64185     defined(BCM_56980_B0)
  64186     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM56960_A0r */
  64187         soc_block_list[16],
  64188         soc_genreg,
  64189         1,
  64190         0,
  64191         0x2021600,
  64192         SOC_REG_FLAG_RO,
  64193         0,
  64194         3,
  64195         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64197         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64198         -1,
  64199         -1,
  64200         3,
  64201     },
  64202 #endif /* chips */
  64203 
  64204 #if defined(BCM_88270_A0)
  64205     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88270_A0r */
  64206         soc_block_list[56],
  64207         soc_genreg,
  64208         1,
  64209         0,
  64210         0x2021600,
  64211         SOC_REG_FLAG_RO |
  64212                           SOC_REG_FLAG_SIGNAL,
  64213         0,
  64214         3,
  64215         soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88270_A0r_fields,
  64216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64217         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64218         -1,
  64219         -1,
  64220     },
  64221 #endif /* chips */
  64222 
  64223 #if defined(BCM_88375_A0)
  64224     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88375_A0r */
  64225         soc_block_list[56],
  64226         soc_genreg,
  64227         1,
  64228         0,
  64229         0x2021600,
  64230         SOC_REG_FLAG_RO |
  64231                           SOC_REG_FLAG_SIGNAL,
  64232         0,
  64233         3,
  64234         soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88375_A0r_fields,
  64235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64236         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64237         -1,
  64238         -1,
  64239     },
  64240 #endif /* chips */
  64241 
  64242 #if defined(BCM_88375_B0)
  64243     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88375_B0r */
  64244         soc_block_list[56],
  64245         soc_genreg,
  64246         1,
  64247         0,
  64248         0x2021600,
  64249         SOC_REG_FLAG_RO |
  64250                           SOC_REG_FLAG_SIGNAL,
  64251         0,
  64252         3,
  64253         soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88375_B0r_fields,
  64254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64255         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64256         -1,
  64257         -1,
  64258     },
  64259 #endif /* chips */
  64260 
  64261 #if defined(BCM_88470_A0)
  64262     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88470_A0r */
  64263         soc_block_list[56],
  64264         soc_genreg,
  64265         1,
  64266         0,
  64267         0x2021600,
  64268         SOC_REG_FLAG_RO |
  64269                           SOC_REG_FLAG_SIGNAL,
  64270         0,
  64271         3,
  64272         soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88470_A0r_fields,
  64273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64274         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64275         -1,
  64276         -1,
  64277     },
  64278 #endif /* chips */
  64279 
  64280 #if defined(BCM_88470_B0)
  64281     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88470_B0r */
  64282         soc_block_list[56],
  64283         soc_genreg,
  64284         1,
  64285         0,
  64286         0x2021600,
  64287         SOC_REG_FLAG_RO |
  64288                           SOC_REG_FLAG_SIGNAL,
  64289         0,
  64290         3,
  64291         soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88470_B0r_fields,
  64292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64293         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64294         -1,
  64295         -1,
  64296     },
  64297 #endif /* chips */
  64298 
  64299 #if defined(BCM_88675_A0)
  64300     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88675_A0r */
  64301         soc_block_list[56],
  64302         soc_genreg,
  64303         1,
  64304         0,
  64305         0x2021600,
  64306         SOC_REG_FLAG_RO |
  64307                           SOC_REG_FLAG_SIGNAL,
  64308         0,
  64309         3,
  64310         soc_XLPORT_XGXS0_LN1_STATUS0_REGr_fields,
  64311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64312         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64313         -1,
  64314         -1,
  64315     },
  64316 #endif /* chips */
  64317 
  64318 #if defined(BCM_88675_B0)
  64319     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88675_B0r */
  64320         soc_block_list[56],
  64321         soc_genreg,
  64322         1,
  64323         0,
  64324         0x2021600,
  64325         SOC_REG_FLAG_RO |
  64326                           SOC_REG_FLAG_SIGNAL,
  64327         0,
  64328         3,
  64329         soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88675_B0r_fields,
  64330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64331         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64332         -1,
  64333         -1,
  64334     },
  64335 #endif /* chips */
  64336 
  64337 #if defined(BCM_88680_A0)
  64338     { /* SOC_REG_INT_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88680_A0r */
  64339         soc_block_list[56],
  64340         soc_genreg,
  64341         1,
  64342         0,
  64343         0x2021600,
  64344         SOC_REG_FLAG_RO |
  64345                           SOC_REG_FLAG_SIGNAL,
  64346         0,
  64347         3,
  64348         soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88680_A0r_fields,
  64349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64350         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64351         -1,
  64352         -1,
  64353     },
  64354 #endif /* chips */
  64355 
  64356 #if defined(BCM_2801PM_A0)
  64357     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REGr */
  64358         soc_block_list[56],
  64359         soc_genreg,
  64360         1,
  64361         0,
  64362         0x2021700,
  64363         SOC_REG_FLAG_RO |
  64364                           SOC_REG_FLAG_SIGNAL,
  64365         0,
  64366         3,
  64367         soc_CLPORT_XGXS0_LN0_STATUS0_REGr_fields,
  64368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64369         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64370         -1,
  64371         -1,
  64372     },
  64373 #endif /* chips */
  64374 
  64375 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  64376     defined(BCM_56670_B0)
  64377     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM53400_A0r */
  64378         soc_block_list[16],
  64379         soc_genreg,
  64380         1,
  64381         0,
  64382         0x2021700,
  64383         SOC_REG_FLAG_RO,
  64384         0,
  64385         3,
  64386         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64388         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64389         -1,
  64390         -1,
  64391     },
  64392 #endif /* chips */
  64393 
  64394 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  64395     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM53570_A0r */
  64396         soc_block_list[16],
  64397         soc_genreg,
  64398         1,
  64399         0,
  64400         0x2021700,
  64401         SOC_REG_FLAG_RO,
  64402         0,
  64403         3,
  64404         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64406         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64407         -1,
  64408         -1,
  64409     },
  64410 #endif /* chips */
  64411 
  64412 #if defined(BCM_56150_A0)
  64413     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM56150_A0r */
  64414         soc_block_list[16],
  64415         soc_genreg,
  64416         1,
  64417         0,
  64418         0x2021700,
  64419         SOC_REG_FLAG_RO,
  64420         0,
  64421         3,
  64422         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56850_A0r_fields,
  64423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64424         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64425         -1,
  64426         -1,
  64427     },
  64428 #endif /* chips */
  64429 
  64430 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  64431     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM56160_A0r */
  64432         soc_block_list[16],
  64433         soc_genreg,
  64434         1,
  64435         0,
  64436         0x2021700,
  64437         SOC_REG_FLAG_RO,
  64438         0,
  64439         3,
  64440         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64442         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64443         -1,
  64444         -1,
  64445     },
  64446 #endif /* chips */
  64447 
  64448 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64449     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM56260_A0r */
  64450         soc_block_list[16],
  64451         soc_genreg,
  64452         1,
  64453         0,
  64454         0x2021700,
  64455         SOC_REG_FLAG_RO,
  64456         0,
  64457         3,
  64458         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64460         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64461         -1,
  64462         -1,
  64463     },
  64464 #endif /* chips */
  64465 
  64466 #if defined(BCM_56370_A0)
  64467     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM56370_A0r */
  64468         soc_block_list[16],
  64469         soc_genreg,
  64470         1,
  64471         0,
  64472         0x2021700,
  64473         SOC_REG_FLAG_RO,
  64474         0,
  64475         3,
  64476         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64478         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64479         -1,
  64480         -1,
  64481         3,
  64482     },
  64483 #endif /* chips */
  64484 
  64485 #if defined(BCM_56560_A0)
  64486     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM56560_A0r */
  64487         soc_block_list[217],
  64488         soc_genreg,
  64489         1,
  64490         0,
  64491         0x2021700,
  64492         SOC_REG_FLAG_RO,
  64493         0,
  64494         3,
  64495         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64497         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64498         -1,
  64499         -1,
  64500     },
  64501 #endif /* chips */
  64502 
  64503 #if defined(BCM_56560_B0)
  64504     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM56560_B0r */
  64505         soc_block_list[16],
  64506         soc_genreg,
  64507         1,
  64508         0,
  64509         0x2021700,
  64510         SOC_REG_FLAG_RO,
  64511         0,
  64512         3,
  64513         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64515         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64516         -1,
  64517         -1,
  64518     },
  64519 #endif /* chips */
  64520 
  64521 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  64522     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM56850_A0r */
  64523         soc_block_list[16],
  64524         soc_genreg,
  64525         1,
  64526         0,
  64527         0x2021200,
  64528         SOC_REG_FLAG_RO,
  64529         0,
  64530         3,
  64531         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56850_A0r_fields,
  64532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64533         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64534         -1,
  64535         -1,
  64536     },
  64537 #endif /* chips */
  64538 
  64539 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  64540     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  64541     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  64542     defined(BCM_56980_B0)
  64543     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM56960_A0r */
  64544         soc_block_list[16],
  64545         soc_genreg,
  64546         1,
  64547         0,
  64548         0x2021700,
  64549         SOC_REG_FLAG_RO,
  64550         0,
  64551         3,
  64552         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64554         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64555         -1,
  64556         -1,
  64557         3,
  64558     },
  64559 #endif /* chips */
  64560 
  64561 #if defined(BCM_88270_A0)
  64562     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88270_A0r */
  64563         soc_block_list[56],
  64564         soc_genreg,
  64565         1,
  64566         0,
  64567         0x2021700,
  64568         SOC_REG_FLAG_RO |
  64569                           SOC_REG_FLAG_SIGNAL,
  64570         0,
  64571         3,
  64572         soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88270_A0r_fields,
  64573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64574         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64575         -1,
  64576         -1,
  64577     },
  64578 #endif /* chips */
  64579 
  64580 #if defined(BCM_88375_A0)
  64581     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88375_A0r */
  64582         soc_block_list[56],
  64583         soc_genreg,
  64584         1,
  64585         0,
  64586         0x2021700,
  64587         SOC_REG_FLAG_RO |
  64588                           SOC_REG_FLAG_SIGNAL,
  64589         0,
  64590         3,
  64591         soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88375_A0r_fields,
  64592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64593         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64594         -1,
  64595         -1,
  64596     },
  64597 #endif /* chips */
  64598 
  64599 #if defined(BCM_88375_B0)
  64600     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88375_B0r */
  64601         soc_block_list[56],
  64602         soc_genreg,
  64603         1,
  64604         0,
  64605         0x2021700,
  64606         SOC_REG_FLAG_RO |
  64607                           SOC_REG_FLAG_SIGNAL,
  64608         0,
  64609         3,
  64610         soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88375_B0r_fields,
  64611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64612         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64613         -1,
  64614         -1,
  64615     },
  64616 #endif /* chips */
  64617 
  64618 #if defined(BCM_88470_A0)
  64619     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88470_A0r */
  64620         soc_block_list[56],
  64621         soc_genreg,
  64622         1,
  64623         0,
  64624         0x2021700,
  64625         SOC_REG_FLAG_RO |
  64626                           SOC_REG_FLAG_SIGNAL,
  64627         0,
  64628         3,
  64629         soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88470_A0r_fields,
  64630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64631         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64632         -1,
  64633         -1,
  64634     },
  64635 #endif /* chips */
  64636 
  64637 #if defined(BCM_88470_B0)
  64638     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88470_B0r */
  64639         soc_block_list[56],
  64640         soc_genreg,
  64641         1,
  64642         0,
  64643         0x2021700,
  64644         SOC_REG_FLAG_RO |
  64645                           SOC_REG_FLAG_SIGNAL,
  64646         0,
  64647         3,
  64648         soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88470_B0r_fields,
  64649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64650         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64651         -1,
  64652         -1,
  64653     },
  64654 #endif /* chips */
  64655 
  64656 #if defined(BCM_88675_A0)
  64657     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88675_A0r */
  64658         soc_block_list[56],
  64659         soc_genreg,
  64660         1,
  64661         0,
  64662         0x2021700,
  64663         SOC_REG_FLAG_RO |
  64664                           SOC_REG_FLAG_SIGNAL,
  64665         0,
  64666         3,
  64667         soc_XLPORT_XGXS0_LN2_STATUS0_REGr_fields,
  64668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64669         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64670         -1,
  64671         -1,
  64672     },
  64673 #endif /* chips */
  64674 
  64675 #if defined(BCM_88675_B0)
  64676     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88675_B0r */
  64677         soc_block_list[56],
  64678         soc_genreg,
  64679         1,
  64680         0,
  64681         0x2021700,
  64682         SOC_REG_FLAG_RO |
  64683                           SOC_REG_FLAG_SIGNAL,
  64684         0,
  64685         3,
  64686         soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88675_B0r_fields,
  64687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64688         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64689         -1,
  64690         -1,
  64691     },
  64692 #endif /* chips */
  64693 
  64694 #if defined(BCM_88680_A0)
  64695     { /* SOC_REG_INT_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88680_A0r */
  64696         soc_block_list[56],
  64697         soc_genreg,
  64698         1,
  64699         0,
  64700         0x2021700,
  64701         SOC_REG_FLAG_RO |
  64702                           SOC_REG_FLAG_SIGNAL,
  64703         0,
  64704         3,
  64705         soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88680_A0r_fields,
  64706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64707         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64708         -1,
  64709         -1,
  64710     },
  64711 #endif /* chips */
  64712 
  64713 #if defined(BCM_2801PM_A0)
  64714     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REGr */
  64715         soc_block_list[56],
  64716         soc_genreg,
  64717         1,
  64718         0,
  64719         0x2021800,
  64720         SOC_REG_FLAG_RO |
  64721                           SOC_REG_FLAG_SIGNAL,
  64722         0,
  64723         3,
  64724         soc_CLPORT_XGXS0_LN0_STATUS0_REGr_fields,
  64725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64726         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64727         -1,
  64728         -1,
  64729     },
  64730 #endif /* chips */
  64731 
  64732 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  64733     defined(BCM_56670_B0)
  64734     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM53400_A0r */
  64735         soc_block_list[16],
  64736         soc_genreg,
  64737         1,
  64738         0,
  64739         0x2021800,
  64740         SOC_REG_FLAG_RO,
  64741         0,
  64742         3,
  64743         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64745         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64746         -1,
  64747         -1,
  64748     },
  64749 #endif /* chips */
  64750 
  64751 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  64752     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM53570_A0r */
  64753         soc_block_list[16],
  64754         soc_genreg,
  64755         1,
  64756         0,
  64757         0x2021800,
  64758         SOC_REG_FLAG_RO,
  64759         0,
  64760         3,
  64761         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64763         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64764         -1,
  64765         -1,
  64766     },
  64767 #endif /* chips */
  64768 
  64769 #if defined(BCM_56150_A0)
  64770     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM56150_A0r */
  64771         soc_block_list[16],
  64772         soc_genreg,
  64773         1,
  64774         0,
  64775         0x2021800,
  64776         SOC_REG_FLAG_RO,
  64777         0,
  64778         3,
  64779         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56850_A0r_fields,
  64780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64782         -1,
  64783         -1,
  64784     },
  64785 #endif /* chips */
  64786 
  64787 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  64788     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM56160_A0r */
  64789         soc_block_list[16],
  64790         soc_genreg,
  64791         1,
  64792         0,
  64793         0x2021800,
  64794         SOC_REG_FLAG_RO,
  64795         0,
  64796         3,
  64797         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64799         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64800         -1,
  64801         -1,
  64802     },
  64803 #endif /* chips */
  64804 
  64805 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  64806     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM56260_A0r */
  64807         soc_block_list[16],
  64808         soc_genreg,
  64809         1,
  64810         0,
  64811         0x2021800,
  64812         SOC_REG_FLAG_RO,
  64813         0,
  64814         3,
  64815         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64817         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64818         -1,
  64819         -1,
  64820     },
  64821 #endif /* chips */
  64822 
  64823 #if defined(BCM_56370_A0)
  64824     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM56370_A0r */
  64825         soc_block_list[16],
  64826         soc_genreg,
  64827         1,
  64828         0,
  64829         0x2021800,
  64830         SOC_REG_FLAG_RO,
  64831         0,
  64832         3,
  64833         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64835         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64836         -1,
  64837         -1,
  64838         3,
  64839     },
  64840 #endif /* chips */
  64841 
  64842 #if defined(BCM_56560_A0)
  64843     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM56560_A0r */
  64844         soc_block_list[217],
  64845         soc_genreg,
  64846         1,
  64847         0,
  64848         0x2021800,
  64849         SOC_REG_FLAG_RO,
  64850         0,
  64851         3,
  64852         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64854         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64855         -1,
  64856         -1,
  64857     },
  64858 #endif /* chips */
  64859 
  64860 #if defined(BCM_56560_B0)
  64861     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM56560_B0r */
  64862         soc_block_list[16],
  64863         soc_genreg,
  64864         1,
  64865         0,
  64866         0x2021800,
  64867         SOC_REG_FLAG_RO,
  64868         0,
  64869         3,
  64870         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64872         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64873         -1,
  64874         -1,
  64875     },
  64876 #endif /* chips */
  64877 
  64878 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  64879     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM56850_A0r */
  64880         soc_block_list[16],
  64881         soc_genreg,
  64882         1,
  64883         0,
  64884         0x2021300,
  64885         SOC_REG_FLAG_RO,
  64886         0,
  64887         3,
  64888         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56850_A0r_fields,
  64889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64890         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64891         -1,
  64892         -1,
  64893     },
  64894 #endif /* chips */
  64895 
  64896 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  64897     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  64898     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  64899     defined(BCM_56980_B0)
  64900     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM56960_A0r */
  64901         soc_block_list[16],
  64902         soc_genreg,
  64903         1,
  64904         0,
  64905         0x2021800,
  64906         SOC_REG_FLAG_RO,
  64907         0,
  64908         3,
  64909         soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields,
  64910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  64912         -1,
  64913         -1,
  64914         3,
  64915     },
  64916 #endif /* chips */
  64917 
  64918 #if defined(BCM_88270_A0)
  64919     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88270_A0r */
  64920         soc_block_list[56],
  64921         soc_genreg,
  64922         1,
  64923         0,
  64924         0x2021800,
  64925         SOC_REG_FLAG_RO |
  64926                           SOC_REG_FLAG_SIGNAL,
  64927         0,
  64928         3,
  64929         soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88270_A0r_fields,
  64930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64931         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64932         -1,
  64933         -1,
  64934     },
  64935 #endif /* chips */
  64936 
  64937 #if defined(BCM_88375_A0)
  64938     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88375_A0r */
  64939         soc_block_list[56],
  64940         soc_genreg,
  64941         1,
  64942         0,
  64943         0x2021800,
  64944         SOC_REG_FLAG_RO |
  64945                           SOC_REG_FLAG_SIGNAL,
  64946         0,
  64947         3,
  64948         soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88375_A0r_fields,
  64949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64950         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64951         -1,
  64952         -1,
  64953     },
  64954 #endif /* chips */
  64955 
  64956 #if defined(BCM_88375_B0)
  64957     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88375_B0r */
  64958         soc_block_list[56],
  64959         soc_genreg,
  64960         1,
  64961         0,
  64962         0x2021800,
  64963         SOC_REG_FLAG_RO |
  64964                           SOC_REG_FLAG_SIGNAL,
  64965         0,
  64966         3,
  64967         soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88375_B0r_fields,
  64968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64969         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64970         -1,
  64971         -1,
  64972     },
  64973 #endif /* chips */
  64974 
  64975 #if defined(BCM_88470_A0)
  64976     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88470_A0r */
  64977         soc_block_list[56],
  64978         soc_genreg,
  64979         1,
  64980         0,
  64981         0x2021800,
  64982         SOC_REG_FLAG_RO |
  64983                           SOC_REG_FLAG_SIGNAL,
  64984         0,
  64985         3,
  64986         soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88470_A0r_fields,
  64987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64988         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64989         -1,
  64990         -1,
  64991     },
  64992 #endif /* chips */
  64993 
  64994 #if defined(BCM_88470_B0)
  64995     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88470_B0r */
  64996         soc_block_list[56],
  64997         soc_genreg,
  64998         1,
  64999         0,
  65000         0x2021800,
  65001         SOC_REG_FLAG_RO |
  65002                           SOC_REG_FLAG_SIGNAL,
  65003         0,
  65004         3,
  65005         soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88470_B0r_fields,
  65006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65007         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  65008         -1,
  65009         -1,
  65010     },
  65011 #endif /* chips */
  65012 
  65013 #if defined(BCM_88675_A0)
  65014     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88675_A0r */
  65015         soc_block_list[56],
  65016         soc_genreg,
  65017         1,
  65018         0,
  65019         0x2021800,
  65020         SOC_REG_FLAG_RO |
  65021                           SOC_REG_FLAG_SIGNAL,
  65022         0,
  65023         3,
  65024         soc_XLPORT_XGXS0_LN3_STATUS0_REGr_fields,
  65025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65026         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  65027         -1,
  65028         -1,
  65029     },
  65030 #endif /* chips */
  65031 
  65032 #if defined(BCM_88675_B0)
  65033     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88675_B0r */
  65034         soc_block_list[56],
  65035         soc_genreg,
  65036         1,
  65037         0,
  65038         0x2021800,
  65039         SOC_REG_FLAG_RO |
  65040                           SOC_REG_FLAG_SIGNAL,
  65041         0,
  65042         3,
  65043         soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88675_B0r_fields,
  65044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65045         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  65046         -1,
  65047         -1,
  65048     },
  65049 #endif /* chips */
  65050 
  65051 #if defined(BCM_88680_A0)
  65052     { /* SOC_REG_INT_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88680_A0r */
  65053         soc_block_list[56],
  65054         soc_genreg,
  65055         1,
  65056         0,
  65057         0x2021800,
  65058         SOC_REG_FLAG_RO |
  65059                           SOC_REG_FLAG_SIGNAL,
  65060         0,
  65061         3,
  65062         soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88680_A0r_fields,
  65063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65064         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  65065         -1,
  65066         -1,
  65067     },
  65068 #endif /* chips */
  65069 
  65070 #if defined(BCM_56840_A0)
  65071     { /* SOC_REG_INT_XLPORT_XGXS0_STATUS0_REGr */
  65072         soc_block_list[16],
  65073         soc_genreg,
  65074         1,
  65075         0,
  65076         0x80239,
  65077         SOC_REG_FLAG_RO,
  65078         0,
  65079         19,
  65080         soc_XLPORT_XGXS0_STATUS0_REGr_fields,
  65081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65082         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65083         -1,
  65084         -1,
  65085     },
  65086 #endif /* chips */
  65087 
  65088 #if defined(BCM_56840_B0)
  65089     { /* SOC_REG_INT_XLPORT_XGXS0_STATUS0_REG_BCM56840_B0r */
  65090         soc_block_list[16],
  65091         soc_genreg,
  65092         1,
  65093         0,
  65094         0x80239,
  65095         SOC_REG_FLAG_RO,
  65096         0,
  65097         30,
  65098         soc_XLPORT_XGXS0_STATUS0_REG_BCM56840_B0r_fields,
  65099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65100         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65101         -1,
  65102         -1,
  65103     },
  65104 #endif /* chips */
  65105 
  65106 #if defined(BCM_88732_A0)
  65107     { /* SOC_REG_INT_XLPORT_XGXS0_STATUS0_REG_BCM88732_A0r */
  65108         soc_block_list[16],
  65109         soc_genreg,
  65110         1,
  65111         0,
  65112         0x80239,
  65113         SOC_REG_FLAG_RO,
  65114         0,
  65115         19,
  65116         soc_XLPORT_XGXS0_STATUS0_REGr_fields,
  65117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65118         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65119         -1,
  65120         -1,
  65121     },
  65122 #endif /* chips */
  65123 
  65124 #if defined(BCM_56840_A0)
  65125     { /* SOC_REG_INT_XLPORT_XGXS0_STATUS1_REGr */
  65126         soc_block_list[16],
  65127         soc_genreg,
  65128         1,
  65129         0,
  65130         0x8023a,
  65131         SOC_REG_FLAG_RO,
  65132         0,
  65133         30,
  65134         soc_XLPORT_XGXS0_STATUS1_REGr_fields,
  65135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65136         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65137         -1,
  65138         -1,
  65139     },
  65140 #endif /* chips */
  65141 
  65142 #if defined(BCM_56840_B0)
  65143     { /* SOC_REG_INT_XLPORT_XGXS0_STATUS1_REG_BCM56840_B0r */
  65144         soc_block_list[16],
  65145         soc_genreg,
  65146         1,
  65147         0,
  65148         0x8023a,
  65149         SOC_REG_FLAG_RO,
  65150         0,
  65151         30,
  65152         soc_XLPORT_XGXS0_STATUS1_REGr_fields,
  65153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65154         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65155         -1,
  65156         -1,
  65157     },
  65158 #endif /* chips */
  65159 
  65160 #if defined(BCM_88732_A0)
  65161     { /* SOC_REG_INT_XLPORT_XGXS0_STATUS1_REG_BCM88732_A0r */
  65162         soc_block_list[16],
  65163         soc_genreg,
  65164         1,
  65165         0,
  65166         0x8023a,
  65167         SOC_REG_FLAG_RO,
  65168         0,
  65169         30,
  65170         soc_XLPORT_XGXS0_STATUS1_REGr_fields,
  65171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65172         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65173         -1,
  65174         -1,
  65175     },
  65176 #endif /* chips */
  65177 
  65178 #if defined(BCM_56840_A0)
  65179     { /* SOC_REG_INT_XLPORT_XGXS1_STATUS0_REGr */
  65180         soc_block_list[16],
  65181         soc_genreg,
  65182         1,
  65183         0,
  65184         0x8023b,
  65185         SOC_REG_FLAG_RO,
  65186         0,
  65187         19,
  65188         soc_XLPORT_XGXS1_STATUS0_REGr_fields,
  65189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65190         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65191         -1,
  65192         -1,
  65193     },
  65194 #endif /* chips */
  65195 
  65196 #if defined(BCM_56840_B0)
  65197     { /* SOC_REG_INT_XLPORT_XGXS1_STATUS0_REG_BCM56840_B0r */
  65198         soc_block_list[16],
  65199         soc_genreg,
  65200         1,
  65201         0,
  65202         0x8023b,
  65203         SOC_REG_FLAG_RO,
  65204         0,
  65205         30,
  65206         soc_XLPORT_XGXS1_STATUS0_REG_BCM56840_B0r_fields,
  65207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65208         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65209         -1,
  65210         -1,
  65211     },
  65212 #endif /* chips */
  65213 
  65214 #if defined(BCM_88732_A0)
  65215     { /* SOC_REG_INT_XLPORT_XGXS1_STATUS0_REG_BCM88732_A0r */
  65216         soc_block_list[16],
  65217         soc_genreg,
  65218         1,
  65219         0,
  65220         0x8023b,
  65221         SOC_REG_FLAG_RO,
  65222         0,
  65223         19,
  65224         soc_XLPORT_XGXS1_STATUS0_REGr_fields,
  65225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65226         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65227         -1,
  65228         -1,
  65229     },
  65230 #endif /* chips */
  65231 
  65232 #if defined(BCM_56840_A0)
  65233     { /* SOC_REG_INT_XLPORT_XGXS1_STATUS1_REGr */
  65234         soc_block_list[16],
  65235         soc_genreg,
  65236         1,
  65237         0,
  65238         0x8023c,
  65239         SOC_REG_FLAG_RO,
  65240         0,
  65241         30,
  65242         soc_XLPORT_XGXS1_STATUS1_REGr_fields,
  65243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65244         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65245         -1,
  65246         -1,
  65247     },
  65248 #endif /* chips */
  65249 
  65250 #if defined(BCM_56840_B0)
  65251     { /* SOC_REG_INT_XLPORT_XGXS1_STATUS1_REG_BCM56840_B0r */
  65252         soc_block_list[16],
  65253         soc_genreg,
  65254         1,
  65255         0,
  65256         0x8023c,
  65257         SOC_REG_FLAG_RO,
  65258         0,
  65259         30,
  65260         soc_XLPORT_XGXS1_STATUS1_REGr_fields,
  65261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65262         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65263         -1,
  65264         -1,
  65265     },
  65266 #endif /* chips */
  65267 
  65268 #if defined(BCM_88732_A0)
  65269     { /* SOC_REG_INT_XLPORT_XGXS1_STATUS1_REG_BCM88732_A0r */
  65270         soc_block_list[16],
  65271         soc_genreg,
  65272         1,
  65273         0,
  65274         0x8023c,
  65275         SOC_REG_FLAG_RO,
  65276         0,
  65277         30,
  65278         soc_XLPORT_XGXS1_STATUS1_REGr_fields,
  65279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65280         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65281         -1,
  65282         -1,
  65283     },
  65284 #endif /* chips */
  65285 
  65286 #if defined(BCM_56840_A0)
  65287     { /* SOC_REG_INT_XLPORT_XGXS2_STATUS0_REGr */
  65288         soc_block_list[16],
  65289         soc_genreg,
  65290         1,
  65291         0,
  65292         0x8023d,
  65293         SOC_REG_FLAG_RO,
  65294         0,
  65295         19,
  65296         soc_XLPORT_XGXS2_STATUS0_REGr_fields,
  65297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65298         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65299         -1,
  65300         -1,
  65301     },
  65302 #endif /* chips */
  65303 
  65304 #if defined(BCM_56840_B0)
  65305     { /* SOC_REG_INT_XLPORT_XGXS2_STATUS0_REG_BCM56840_B0r */
  65306         soc_block_list[16],
  65307         soc_genreg,
  65308         1,
  65309         0,
  65310         0x8023d,
  65311         SOC_REG_FLAG_RO,
  65312         0,
  65313         30,
  65314         soc_XLPORT_XGXS2_STATUS0_REG_BCM56840_B0r_fields,
  65315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65316         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65317         -1,
  65318         -1,
  65319     },
  65320 #endif /* chips */
  65321 
  65322 #if defined(BCM_88732_A0)
  65323     { /* SOC_REG_INT_XLPORT_XGXS2_STATUS0_REG_BCM88732_A0r */
  65324         soc_block_list[16],
  65325         soc_genreg,
  65326         1,
  65327         0,
  65328         0x8023d,
  65329         SOC_REG_FLAG_RO,
  65330         0,
  65331         19,
  65332         soc_XLPORT_XGXS2_STATUS0_REGr_fields,
  65333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65334         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65335         -1,
  65336         -1,
  65337     },
  65338 #endif /* chips */
  65339 
  65340 #if defined(BCM_56840_A0)
  65341     { /* SOC_REG_INT_XLPORT_XGXS2_STATUS1_REGr */
  65342         soc_block_list[16],
  65343         soc_genreg,
  65344         1,
  65345         0,
  65346         0x8023e,
  65347         SOC_REG_FLAG_RO,
  65348         0,
  65349         30,
  65350         soc_XLPORT_XGXS2_STATUS1_REGr_fields,
  65351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65352         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65353         -1,
  65354         -1,
  65355     },
  65356 #endif /* chips */
  65357 
  65358 #if defined(BCM_56840_B0)
  65359     { /* SOC_REG_INT_XLPORT_XGXS2_STATUS1_REG_BCM56840_B0r */
  65360         soc_block_list[16],
  65361         soc_genreg,
  65362         1,
  65363         0,
  65364         0x8023e,
  65365         SOC_REG_FLAG_RO,
  65366         0,
  65367         30,
  65368         soc_XLPORT_XGXS2_STATUS1_REGr_fields,
  65369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65370         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65371         -1,
  65372         -1,
  65373     },
  65374 #endif /* chips */
  65375 
  65376 #if defined(BCM_88732_A0)
  65377     { /* SOC_REG_INT_XLPORT_XGXS2_STATUS1_REG_BCM88732_A0r */
  65378         soc_block_list[16],
  65379         soc_genreg,
  65380         1,
  65381         0,
  65382         0x8023e,
  65383         SOC_REG_FLAG_RO,
  65384         0,
  65385         30,
  65386         soc_XLPORT_XGXS2_STATUS1_REGr_fields,
  65387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65388         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65389         -1,
  65390         -1,
  65391     },
  65392 #endif /* chips */
  65393 
  65394 #if defined(BCM_56840_A0)
  65395     { /* SOC_REG_INT_XLPORT_XGXS3_STATUS0_REGr */
  65396         soc_block_list[16],
  65397         soc_genreg,
  65398         1,
  65399         0,
  65400         0x8023f,
  65401         SOC_REG_FLAG_RO,
  65402         0,
  65403         19,
  65404         soc_XLPORT_XGXS3_STATUS0_REGr_fields,
  65405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65406         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65407         -1,
  65408         -1,
  65409     },
  65410 #endif /* chips */
  65411 
  65412 #if defined(BCM_56840_B0)
  65413     { /* SOC_REG_INT_XLPORT_XGXS3_STATUS0_REG_BCM56840_B0r */
  65414         soc_block_list[16],
  65415         soc_genreg,
  65416         1,
  65417         0,
  65418         0x8023f,
  65419         SOC_REG_FLAG_RO,
  65420         0,
  65421         30,
  65422         soc_XLPORT_XGXS3_STATUS0_REG_BCM56840_B0r_fields,
  65423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65424         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65425         -1,
  65426         -1,
  65427     },
  65428 #endif /* chips */
  65429 
  65430 #if defined(BCM_88732_A0)
  65431     { /* SOC_REG_INT_XLPORT_XGXS3_STATUS0_REG_BCM88732_A0r */
  65432         soc_block_list[16],
  65433         soc_genreg,
  65434         1,
  65435         0,
  65436         0x8023f,
  65437         SOC_REG_FLAG_RO,
  65438         0,
  65439         19,
  65440         soc_XLPORT_XGXS3_STATUS0_REGr_fields,
  65441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65442         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65443         -1,
  65444         -1,
  65445     },
  65446 #endif /* chips */
  65447 
  65448 #if defined(BCM_56840_A0)
  65449     { /* SOC_REG_INT_XLPORT_XGXS3_STATUS1_REGr */
  65450         soc_block_list[16],
  65451         soc_genreg,
  65452         1,
  65453         0,
  65454         0x80240,
  65455         SOC_REG_FLAG_RO,
  65456         0,
  65457         30,
  65458         soc_XLPORT_XGXS3_STATUS1_REGr_fields,
  65459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65460         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65461         -1,
  65462         -1,
  65463     },
  65464 #endif /* chips */
  65465 
  65466 #if defined(BCM_56840_B0)
  65467     { /* SOC_REG_INT_XLPORT_XGXS3_STATUS1_REG_BCM56840_B0r */
  65468         soc_block_list[16],
  65469         soc_genreg,
  65470         1,
  65471         0,
  65472         0x80240,
  65473         SOC_REG_FLAG_RO,
  65474         0,
  65475         30,
  65476         soc_XLPORT_XGXS3_STATUS1_REGr_fields,
  65477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65478         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65479         -1,
  65480         -1,
  65481     },
  65482 #endif /* chips */
  65483 
  65484 #if defined(BCM_88732_A0)
  65485     { /* SOC_REG_INT_XLPORT_XGXS3_STATUS1_REG_BCM88732_A0r */
  65486         soc_block_list[16],
  65487         soc_genreg,
  65488         1,
  65489         0,
  65490         0x80240,
  65491         SOC_REG_FLAG_RO,
  65492         0,
  65493         30,
  65494         soc_XLPORT_XGXS3_STATUS1_REGr_fields,
  65495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65496         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65497         -1,
  65498         -1,
  65499     },
  65500 #endif /* chips */
  65501 
  65502 #if defined(BCM_56840_A0)
  65503     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODEr */
  65504         soc_block_list[16],
  65505         soc_genreg,
  65506         1,
  65507         0,
  65508         0x8022d,
  65509         0,
  65510         0,
  65511         1,
  65512         soc_XLPORT_XGXS_COUNTER_MODEr_fields,
  65513         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65514         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65515         -1,
  65516         -1,
  65517     },
  65518 #endif /* chips */
  65519 
  65520 #if defined(BCM_2801PM_A0)
  65521     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM2801PM_A0r */
  65522         soc_block_list[56],
  65523         soc_genreg,
  65524         1,
  65525         0,
  65526         0x2021100,
  65527         0,
  65528         0,
  65529         1,
  65530         soc_CLPORT_XGXS_COUNTER_MODEr_fields,
  65531         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65532         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65533         -1,
  65534         -1,
  65535     },
  65536 #endif /* chips */
  65537 
  65538 #if defined(BCM_53400_A0) || defined(BCM_56670_A0) || \
  65539     defined(BCM_56670_B0)
  65540     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM53400_A0r */
  65541         soc_block_list[16],
  65542         soc_genreg,
  65543         1,
  65544         0,
  65545         0x2021100,
  65546         0,
  65547         0,
  65548         1,
  65549         soc_XLPORT_XGXS_COUNTER_MODE_BCM53400_A0r_fields,
  65550         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65551         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65552         -1,
  65553         -1,
  65554     },
  65555 #endif /* chips */
  65556 
  65557 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  65558     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM53570_A0r */
  65559         soc_block_list[16],
  65560         soc_genreg,
  65561         1,
  65562         0,
  65563         0x2021100,
  65564         0,
  65565         0,
  65566         1,
  65567         soc_XLPORT_XGXS_COUNTER_MODE_BCM53400_A0r_fields,
  65568         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65569         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65570         -1,
  65571         -1,
  65572     },
  65573 #endif /* chips */
  65574 
  65575 #if defined(BCM_56150_A0)
  65576     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM56150_A0r */
  65577         soc_block_list[16],
  65578         soc_genreg,
  65579         1,
  65580         0,
  65581         0x2021100,
  65582         0,
  65583         0,
  65584         1,
  65585         soc_PORT_XGXS_COUNTER_MODE_BCM56640_A0r_fields,
  65586         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65587         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65588         -1,
  65589         -1,
  65590     },
  65591 #endif /* chips */
  65592 
  65593 #if defined(BCM_56160_A0) || defined(BCM_56270_A0)
  65594     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM56160_A0r */
  65595         soc_block_list[16],
  65596         soc_genreg,
  65597         1,
  65598         0,
  65599         0x2021100,
  65600         0,
  65601         0,
  65602         1,
  65603         soc_XLPORT_XGXS_COUNTER_MODE_BCM53400_A0r_fields,
  65604         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65605         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65606         -1,
  65607         -1,
  65608     },
  65609 #endif /* chips */
  65610 
  65611 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  65612     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM56260_A0r */
  65613         soc_block_list[16],
  65614         soc_genreg,
  65615         1,
  65616         0,
  65617         0x2021100,
  65618         0,
  65619         0,
  65620         1,
  65621         soc_XLPORT_XGXS_COUNTER_MODE_BCM53400_A0r_fields,
  65622         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65623         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65624         -1,
  65625         -1,
  65626     },
  65627 #endif /* chips */
  65628 
  65629 #if defined(BCM_56370_A0)
  65630     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM56370_A0r */
  65631         soc_block_list[16],
  65632         soc_genreg,
  65633         1,
  65634         0,
  65635         0x2021100,
  65636         0,
  65637         0,
  65638         1,
  65639         soc_XLPORT_XGXS_COUNTER_MODE_BCM53400_A0r_fields,
  65640         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65641         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65642         -1,
  65643         -1,
  65644         3,
  65645     },
  65646 #endif /* chips */
  65647 
  65648 #if defined(BCM_56560_A0)
  65649     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM56560_A0r */
  65650         soc_block_list[217],
  65651         soc_genreg,
  65652         1,
  65653         0,
  65654         0x2021100,
  65655         0,
  65656         0,
  65657         1,
  65658         soc_XLPORT_XGXS_COUNTER_MODE_BCM53400_A0r_fields,
  65659         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65660         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65661         -1,
  65662         -1,
  65663     },
  65664 #endif /* chips */
  65665 
  65666 #if defined(BCM_56560_B0)
  65667     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM56560_B0r */
  65668         soc_block_list[16],
  65669         soc_genreg,
  65670         1,
  65671         0,
  65672         0x2021100,
  65673         0,
  65674         0,
  65675         1,
  65676         soc_XLPORT_XGXS_COUNTER_MODE_BCM53400_A0r_fields,
  65677         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65678         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65679         -1,
  65680         -1,
  65681     },
  65682 #endif /* chips */
  65683 
  65684 #if defined(BCM_56840_B0)
  65685     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM56840_B0r */
  65686         soc_block_list[16],
  65687         soc_genreg,
  65688         1,
  65689         0,
  65690         0x8022d,
  65691         0,
  65692         0,
  65693         1,
  65694         soc_XLPORT_XGXS_COUNTER_MODEr_fields,
  65695         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65696         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65697         -1,
  65698         -1,
  65699     },
  65700 #endif /* chips */
  65701 
  65702 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  65703     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  65704     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  65705     defined(BCM_56980_B0)
  65706     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM56960_A0r */
  65707         soc_block_list[16],
  65708         soc_genreg,
  65709         1,
  65710         0,
  65711         0x2021100,
  65712         0,
  65713         0,
  65714         1,
  65715         soc_XLPORT_XGXS_COUNTER_MODE_BCM53400_A0r_fields,
  65716         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65717         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65718         -1,
  65719         -1,
  65720         3,
  65721     },
  65722 #endif /* chips */
  65723 
  65724 #if defined(BCM_88270_A0)
  65725     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM88270_A0r */
  65726         soc_block_list[56],
  65727         soc_genreg,
  65728         1,
  65729         0,
  65730         0x2021100,
  65731         0,
  65732         0,
  65733         1,
  65734         soc_XLPORT_XGXS_COUNTER_MODE_BCM88270_A0r_fields,
  65735         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65736         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65737         -1,
  65738         -1,
  65739     },
  65740 #endif /* chips */
  65741 
  65742 #if defined(BCM_88375_A0)
  65743     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM88375_A0r */
  65744         soc_block_list[56],
  65745         soc_genreg,
  65746         1,
  65747         0,
  65748         0x2021100,
  65749         0,
  65750         0,
  65751         1,
  65752         soc_XLPORT_XGXS_COUNTER_MODE_BCM88375_A0r_fields,
  65753         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65754         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65755         -1,
  65756         -1,
  65757     },
  65758 #endif /* chips */
  65759 
  65760 #if defined(BCM_88375_B0)
  65761     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM88375_B0r */
  65762         soc_block_list[56],
  65763         soc_genreg,
  65764         1,
  65765         0,
  65766         0x2021100,
  65767         0,
  65768         0,
  65769         1,
  65770         soc_XLPORT_XGXS_COUNTER_MODE_BCM88375_B0r_fields,
  65771         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65772         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65773         -1,
  65774         -1,
  65775     },
  65776 #endif /* chips */
  65777 
  65778 #if defined(BCM_88470_A0)
  65779     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM88470_A0r */
  65780         soc_block_list[56],
  65781         soc_genreg,
  65782         1,
  65783         0,
  65784         0x2021100,
  65785         0,
  65786         0,
  65787         1,
  65788         soc_XLPORT_XGXS_COUNTER_MODE_BCM88470_A0r_fields,
  65789         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65790         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65791         -1,
  65792         -1,
  65793     },
  65794 #endif /* chips */
  65795 
  65796 #if defined(BCM_88470_B0)
  65797     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM88470_B0r */
  65798         soc_block_list[56],
  65799         soc_genreg,
  65800         1,
  65801         0,
  65802         0x2021100,
  65803         0,
  65804         0,
  65805         1,
  65806         soc_XLPORT_XGXS_COUNTER_MODE_BCM88470_B0r_fields,
  65807         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65808         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65809         -1,
  65810         -1,
  65811     },
  65812 #endif /* chips */
  65813 
  65814 #if defined(BCM_88675_A0)
  65815     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM88675_A0r */
  65816         soc_block_list[56],
  65817         soc_genreg,
  65818         1,
  65819         0,
  65820         0x2021100,
  65821         0,
  65822         0,
  65823         1,
  65824         soc_XLPORT_XGXS_COUNTER_MODE_BCM88675_A0r_fields,
  65825         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65826         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65827         -1,
  65828         -1,
  65829     },
  65830 #endif /* chips */
  65831 
  65832 #if defined(BCM_88675_B0)
  65833     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM88675_B0r */
  65834         soc_block_list[56],
  65835         soc_genreg,
  65836         1,
  65837         0,
  65838         0x2021100,
  65839         0,
  65840         0,
  65841         1,
  65842         soc_XLPORT_XGXS_COUNTER_MODE_BCM88675_B0r_fields,
  65843         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65844         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65845         -1,
  65846         -1,
  65847     },
  65848 #endif /* chips */
  65849 
  65850 #if defined(BCM_88680_A0)
  65851     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM88680_A0r */
  65852         soc_block_list[56],
  65853         soc_genreg,
  65854         1,
  65855         0,
  65856         0x2021100,
  65857         0,
  65858         0,
  65859         1,
  65860         soc_XLPORT_XGXS_COUNTER_MODE_BCM88680_A0r_fields,
  65861         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65862         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65863         -1,
  65864         -1,
  65865     },
  65866 #endif /* chips */
  65867 
  65868 #if defined(BCM_88732_A0)
  65869     { /* SOC_REG_INT_XLPORT_XGXS_COUNTER_MODE_BCM88732_A0r */
  65870         soc_block_list[16],
  65871         soc_genreg,
  65872         1,
  65873         0,
  65874         0x8022d,
  65875         0,
  65876         0,
  65877         1,
  65878         soc_XLPORT_XGXS_COUNTER_MODEr_fields,
  65879         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  65880         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65881         -1,
  65882         -1,
  65883     },
  65884 #endif /* chips */
  65885 
  65886 #if defined(BCM_56840_A0)
  65887     { /* SOC_REG_INT_XLPORT_XGXS_CTRL_REGr */
  65888         soc_block_list[16],
  65889         soc_genreg,
  65890         1,
  65891         0,
  65892         0x80237,
  65893         0,
  65894         0,
  65895         12,
  65896         soc_XLPORT_XGXS_CTRL_REGr_fields,
  65897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65898         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65899         -1,
  65900         -1,
  65901     },
  65902 #endif /* chips */
  65903 
  65904 #if defined(BCM_56840_B0)
  65905     { /* SOC_REG_INT_XLPORT_XGXS_CTRL_REG_BCM56840_B0r */
  65906         soc_block_list[16],
  65907         soc_genreg,
  65908         1,
  65909         0,
  65910         0x80237,
  65911         0,
  65912         0,
  65913         12,
  65914         soc_XLPORT_XGXS_CTRL_REGr_fields,
  65915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65916         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65917         -1,
  65918         -1,
  65919     },
  65920 #endif /* chips */
  65921 
  65922 #if defined(BCM_88732_A0)
  65923     { /* SOC_REG_INT_XLPORT_XGXS_CTRL_REG_BCM88732_A0r */
  65924         soc_block_list[16],
  65925         soc_genreg,
  65926         1,
  65927         0,
  65928         0x80237,
  65929         0,
  65930         0,
  65931         12,
  65932         soc_XLPORT_XGXS_CTRL_REGr_fields,
  65933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65934         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65935         -1,
  65936         -1,
  65937     },
  65938 #endif /* chips */
  65939 
  65940 #if defined(BCM_56840_A0)
  65941     { /* SOC_REG_INT_XLPORT_XGXS_STATUS_GEN_REGr */
  65942         soc_block_list[16],
  65943         soc_genreg,
  65944         1,
  65945         0,
  65946         0x80238,
  65947         SOC_REG_FLAG_RO,
  65948         0,
  65949         1,
  65950         soc_XLPORT_XGXS_STATUS_GEN_REGr_fields,
  65951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65952         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65953         -1,
  65954         -1,
  65955     },
  65956 #endif /* chips */
  65957 
  65958 #if defined(BCM_56840_B0)
  65959     { /* SOC_REG_INT_XLPORT_XGXS_STATUS_GEN_REG_BCM56840_B0r */
  65960         soc_block_list[16],
  65961         soc_genreg,
  65962         1,
  65963         0,
  65964         0x80238,
  65965         SOC_REG_FLAG_RO,
  65966         0,
  65967         1,
  65968         soc_XLPORT_XGXS_STATUS_GEN_REGr_fields,
  65969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65970         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65971         -1,
  65972         -1,
  65973     },
  65974 #endif /* chips */
  65975 
  65976 #if defined(BCM_88732_A0)
  65977     { /* SOC_REG_INT_XLPORT_XGXS_STATUS_GEN_REG_BCM88732_A0r */
  65978         soc_block_list[16],
  65979         soc_genreg,
  65980         1,
  65981         0,
  65982         0x80238,
  65983         SOC_REG_FLAG_RO,
  65984         0,
  65985         1,
  65986         soc_XLPORT_XGXS_STATUS_GEN_REGr_fields,
  65987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65988         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65989         -1,
  65990         -1,
  65991     },
  65992 #endif /* chips */
  65993 
  65994 #if defined(BCM_56840_A0)
  65995     { /* SOC_REG_INT_XLPORT_XMAC_CONTROLr */
  65996         soc_block_list[16],
  65997         soc_genreg,
  65998         1,
  65999         0,
  66000         0x8022b,
  66001         0,
  66002         0,
  66003         1,
  66004         soc_XLPORT_XMAC_CONTROLr_fields,
  66005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66006         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  66007         -1,
  66008         -1,
  66009     },
  66010 #endif /* chips */
  66011 
  66012 #if defined(BCM_56840_B0)
  66013     { /* SOC_REG_INT_XLPORT_XMAC_CONTROL_BCM56840_B0r */
  66014         soc_block_list[16],
  66015         soc_genreg,
  66016         1,
  66017         0,
  66018         0x8022b,
  66019         0,
  66020         0,
  66021         1,
  66022         soc_XLPORT_XMAC_CONTROLr_fields,
  66023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66024         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  66025         -1,
  66026         -1,
  66027     },
  66028 #endif /* chips */
  66029 
  66030 #if defined(BCM_88732_A0)
  66031     { /* SOC_REG_INT_XLPORT_XMAC_CONTROL_BCM88732_A0r */
  66032         soc_block_list[16],
  66033         soc_genreg,
  66034         1,
  66035         0,
  66036         0x8022b,
  66037         0,
  66038         0,
  66039         1,
  66040         soc_XLPORT_XMAC_CONTROLr_fields,
  66041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66042         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  66043         -1,
  66044         -1,
  66045     },
  66046 #endif /* chips */
  66047 
  66048 #if defined(BCM_56840_A0)
  66049     { /* SOC_REG_INT_XLP_EEE_COUNTER_MODEr */
  66050         soc_block_list[16],
  66051         soc_portreg,
  66052         1,
  66053         0,
  66054         0x223,
  66055         0,
  66056         0,
  66057         1,
  66058         soc_XLP_EEE_COUNTER_MODEr_fields,
  66059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66060         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66061         -1,
  66062         -1,
  66063     },
  66064 #endif /* chips */
  66065 
  66066 #if defined(BCM_56840_B0)
  66067     { /* SOC_REG_INT_XLP_EEE_COUNTER_MODE_BCM56840_B0r */
  66068         soc_block_list[16],
  66069         soc_portreg,
  66070         1,
  66071         0,
  66072         0x223,
  66073         0,
  66074         0,
  66075         1,
  66076         soc_XLP_EEE_COUNTER_MODEr_fields,
  66077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66078         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66079         -1,
  66080         -1,
  66081     },
  66082 #endif /* chips */
  66083 
  66084 #if defined(BCM_88732_A0)
  66085     { /* SOC_REG_INT_XLP_EEE_COUNTER_MODE_BCM88732_A0r */
  66086         soc_block_list[16],
  66087         soc_portreg,
  66088         1,
  66089         0,
  66090         0x223,
  66091         0,
  66092         0,
  66093         1,
  66094         soc_XLP_EEE_COUNTER_MODEr_fields,
  66095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66096         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66097         -1,
  66098         -1,
  66099     },
  66100 #endif /* chips */
  66101 
  66102 #if defined(BCM_88650_A0)
  66103     { /* SOC_REG_INT_XLP_REG_060200r */
  66104         soc_block_list[56],
  66105         soc_portreg,
  66106         1,
  66107         0,
  66108         0x60200,
  66109         0,
  66110         0,
  66111         1,
  66112         soc_XLP_REG_060200r_fields,
  66113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66114         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66115         -1,
  66116         -1,
  66117     },
  66118 #endif /* chips */
  66119 
  66120 #if defined(BCM_88650_A0)
  66121     { /* SOC_REG_INT_XLP_REG_060300r */
  66122         soc_block_list[56],
  66123         soc_portreg,
  66124         1,
  66125         0,
  66126         0x60300,
  66127         0,
  66128         0,
  66129         1,
  66130         soc_XLP_REG_060300r_fields,
  66131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66132         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66133         -1,
  66134         -1,
  66135     },
  66136 #endif /* chips */
  66137 
  66138 #if defined(BCM_88650_A0)
  66139     { /* SOC_REG_INT_XLP_REG_061500r */
  66140         soc_block_list[56],
  66141         soc_portreg,
  66142         1,
  66143         0,
  66144         0x61500,
  66145         SOC_REG_FLAG_SIGNAL,
  66146         0,
  66147         7,
  66148         soc_XLP_REG_061500r_fields,
  66149         SOC_RESET_VAL_DEC(0x00030b80, 0x00000000)
  66150         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  66151         -1,
  66152         -1,
  66153     },
  66154 #endif /* chips */
  66155 
  66156 #if defined(BCM_88650_A0)
  66157     { /* SOC_REG_INT_XLP_REG_062000r */
  66158         soc_block_list[56],
  66159         soc_portreg,
  66160         1,
  66161         0,
  66162         0x62000,
  66163         SOC_REG_FLAG_64_BITS,
  66164         0,
  66165         3,
  66166         soc_XLP_REG_062000r_fields,
  66167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66168         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  66169         -1,
  66170         -1,
  66171     },
  66172 #endif /* chips */
  66173 
  66174 #if defined(BCM_88650_A0)
  66175     { /* SOC_REG_INT_XLP_REG_062200r */
  66176         soc_block_list[56],
  66177         soc_portreg,
  66178         1,
  66179         0,
  66180         0x62200,
  66181         SOC_REG_FLAG_SIGNAL,
  66182         0,
  66183         6,
  66184         soc_XLP_REG_062200r_fields,
  66185         SOC_RESET_VAL_DEC(0x000fb808, 0x00000000)
  66186         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  66187         -1,
  66188         -1,
  66189     },
  66190 #endif /* chips */
  66191 
  66192 #if defined(BCM_88650_A0)
  66193     { /* SOC_REG_INT_XLP_REG_062500r */
  66194         soc_block_list[56],
  66195         soc_portreg,
  66196         1,
  66197         0,
  66198         0x62500,
  66199         SOC_REG_FLAG_64_BITS |
  66200                           SOC_REG_FLAG_SIGNAL,
  66201         0,
  66202         6,
  66203         soc_XLP_REG_062500r_fields,
  66204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66205         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  66206         -1,
  66207         -1,
  66208     },
  66209 #endif /* chips */
  66210 
  66211 #if defined(BCM_2801PM_A0)
  66212     { /* SOC_REG_INT_XLP_REG_2022300r */
  66213         soc_block_list[56],
  66214         soc_genreg,
  66215         1,
  66216         0,
  66217         0x2022300,
  66218         0,
  66219         0,
  66220         1,
  66221         soc_CLP_REG_2022300r_fields,
  66222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66223         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66224         -1,
  66225         -1,
  66226     },
  66227 #endif /* chips */
  66228 
  66229 #if defined(BCM_88650_B0)
  66230     { /* SOC_REG_INT_XLP_REG_060200_BCM88650_B0r */
  66231         soc_block_list[56],
  66232         soc_portreg,
  66233         1,
  66234         0,
  66235         0x60200,
  66236         0,
  66237         0,
  66238         1,
  66239         soc_XLP_REG_060200_BCM88650_B0r_fields,
  66240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66241         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66242         -1,
  66243         -1,
  66244     },
  66245 #endif /* chips */
  66246 
  66247 #if defined(BCM_88660_A0)
  66248     { /* SOC_REG_INT_XLP_REG_060200_BCM88660_A0r */
  66249         soc_block_list[56],
  66250         soc_portreg,
  66251         1,
  66252         0,
  66253         0x60200,
  66254         0,
  66255         0,
  66256         1,
  66257         soc_XLP_REG_060200_BCM88660_A0r_fields,
  66258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66259         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66260         -1,
  66261         -1,
  66262     },
  66263 #endif /* chips */
  66264 
  66265 #if defined(BCM_88650_B0)
  66266     { /* SOC_REG_INT_XLP_REG_060300_BCM88650_B0r */
  66267         soc_block_list[56],
  66268         soc_portreg,
  66269         1,
  66270         0,
  66271         0x60300,
  66272         0,
  66273         0,
  66274         1,
  66275         soc_XLP_REG_060300_BCM88650_B0r_fields,
  66276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66277         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66278         -1,
  66279         -1,
  66280     },
  66281 #endif /* chips */
  66282 
  66283 #if defined(BCM_88660_A0)
  66284     { /* SOC_REG_INT_XLP_REG_060300_BCM88660_A0r */
  66285         soc_block_list[56],
  66286         soc_portreg,
  66287         1,
  66288         0,
  66289         0x60300,
  66290         0,
  66291         0,
  66292         1,
  66293         soc_XLP_REG_060300_BCM88660_A0r_fields,
  66294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66295         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66296         -1,
  66297         -1,
  66298     },
  66299 #endif /* chips */
  66300 
  66301 #if defined(BCM_88650_B0)
  66302     { /* SOC_REG_INT_XLP_REG_061500_BCM88650_B0r */
  66303         soc_block_list[56],
  66304         soc_portreg,
  66305         1,
  66306         0,
  66307         0x61500,
  66308         SOC_REG_FLAG_SIGNAL,
  66309         0,
  66310         7,
  66311         soc_XLP_REG_061500_BCM88650_B0r_fields,
  66312         SOC_RESET_VAL_DEC(0x00030b80, 0x00000000)
  66313         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  66314         -1,
  66315         -1,
  66316     },
  66317 #endif /* chips */
  66318 
  66319 #if defined(BCM_88660_A0)
  66320     { /* SOC_REG_INT_XLP_REG_061500_BCM88660_A0r */
  66321         soc_block_list[56],
  66322         soc_portreg,
  66323         1,
  66324         0,
  66325         0x61500,
  66326         SOC_REG_FLAG_SIGNAL,
  66327         0,
  66328         7,
  66329         soc_XLP_REG_061500_BCM88660_A0r_fields,
  66330         SOC_RESET_VAL_DEC(0x00030b80, 0x00000000)
  66331         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  66332         -1,
  66333         -1,
  66334     },
  66335 #endif /* chips */
  66336 
  66337 #if defined(BCM_88650_A0)
  66338     { /* SOC_REG_INT_XLP_REG_061E00r */
  66339         soc_block_list[56],
  66340         soc_portreg,
  66341         1,
  66342         0,
  66343         0x61e00,
  66344         SOC_REG_FLAG_64_BITS,
  66345         0,
  66346         3,
  66347         soc_XLP_REG_061E00r_fields,
  66348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66349         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  66350         -1,
  66351         -1,
  66352     },
  66353 #endif /* chips */
  66354 
  66355 #if defined(BCM_88650_B0)
  66356     { /* SOC_REG_INT_XLP_REG_061E00_BCM88650_B0r */
  66357         soc_block_list[56],
  66358         soc_portreg,
  66359         1,
  66360         0,
  66361         0x61e00,
  66362         SOC_REG_FLAG_64_BITS,
  66363         0,
  66364         3,
  66365         soc_XLP_REG_061E00_BCM88650_B0r_fields,
  66366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66367         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  66368         -1,
  66369         -1,
  66370     },
  66371 #endif /* chips */
  66372 
  66373 #if defined(BCM_88660_A0)
  66374     { /* SOC_REG_INT_XLP_REG_061E00_BCM88660_A0r */
  66375         soc_block_list[56],
  66376         soc_portreg,
  66377         1,
  66378         0,
  66379         0x61e00,
  66380         SOC_REG_FLAG_64_BITS,
  66381         0,
  66382         3,
  66383         soc_XLP_REG_061E00_BCM88660_A0r_fields,
  66384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66385         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  66386         -1,
  66387         -1,
  66388     },
  66389 #endif /* chips */
  66390 
  66391 #if defined(BCM_88650_A0)
  66392     { /* SOC_REG_INT_XLP_REG_061F00r */
  66393         soc_block_list[56],
  66394         soc_portreg,
  66395         1,
  66396         0,
  66397         0x61f00,
  66398         SOC_REG_FLAG_64_BITS,
  66399         0,
  66400         3,
  66401         soc_XLP_REG_061F00r_fields,
  66402         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66403         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  66404         -1,
  66405         -1,
  66406     },
  66407 #endif /* chips */
  66408 
  66409 #if defined(BCM_88650_B0)
  66410     { /* SOC_REG_INT_XLP_REG_061F00_BCM88650_B0r */
  66411         soc_block_list[56],
  66412         soc_portreg,
  66413         1,
  66414         0,
  66415         0x61f00,
  66416         SOC_REG_FLAG_64_BITS,
  66417         0,
  66418         3,
  66419         soc_XLP_REG_061F00_BCM88650_B0r_fields,
  66420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66421         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  66422         -1,
  66423         -1,
  66424     },
  66425 #endif /* chips */
  66426 
  66427 #if defined(BCM_88660_A0)
  66428     { /* SOC_REG_INT_XLP_REG_061F00_BCM88660_A0r */
  66429         soc_block_list[56],
  66430         soc_portreg,
  66431         1,
  66432         0,
  66433         0x61f00,
  66434         SOC_REG_FLAG_64_BITS,
  66435         0,
  66436         3,
  66437         soc_XLP_REG_061F00_BCM88660_A0r_fields,
  66438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66439         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  66440         -1,
  66441         -1,
  66442     },
  66443 #endif /* chips */
  66444 
  66445 #if defined(BCM_88650_B0)
  66446     { /* SOC_REG_INT_XLP_REG_062000_BCM88650_B0r */
  66447         soc_block_list[56],
  66448         soc_portreg,
  66449         1,
  66450         0,
  66451         0x62000,
  66452         SOC_REG_FLAG_64_BITS,
  66453         0,
  66454         3,
  66455         soc_XLP_REG_062000_BCM88650_B0r_fields,
  66456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66457         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  66458         -1,
  66459         -1,
  66460     },
  66461 #endif /* chips */
  66462 
  66463 #if defined(BCM_88660_A0)
  66464     { /* SOC_REG_INT_XLP_REG_062000_BCM88660_A0r */
  66465         soc_block_list[56],
  66466         soc_portreg,
  66467         1,
  66468         0,
  66469         0x62000,
  66470         SOC_REG_FLAG_64_BITS,
  66471         0,
  66472         3,
  66473         soc_XLP_REG_062000_BCM88660_A0r_fields,
  66474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66475         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  66476         -1,
  66477         -1,
  66478     },
  66479 #endif /* chips */
  66480 
  66481 #if defined(BCM_88650_B0)
  66482     { /* SOC_REG_INT_XLP_REG_062200_BCM88650_B0r */
  66483         soc_block_list[56],
  66484         soc_portreg,
  66485         1,
  66486         0,
  66487         0x62200,
  66488         SOC_REG_FLAG_SIGNAL,
  66489         0,
  66490         6,
  66491         soc_XLP_REG_062200_BCM88650_B0r_fields,
  66492         SOC_RESET_VAL_DEC(0x000fb808, 0x00000000)
  66493         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  66494         -1,
  66495         -1,
  66496     },
  66497 #endif /* chips */
  66498 
  66499 #if defined(BCM_88660_A0)
  66500     { /* SOC_REG_INT_XLP_REG_062200_BCM88660_A0r */
  66501         soc_block_list[56],
  66502         soc_portreg,
  66503         1,
  66504         0,
  66505         0x62200,
  66506         SOC_REG_FLAG_SIGNAL,
  66507         0,
  66508         6,
  66509         soc_XLP_REG_062200_BCM88660_A0r_fields,
  66510         SOC_RESET_VAL_DEC(0x000fb808, 0x00000000)
  66511         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  66512         -1,
  66513         -1,
  66514     },
  66515 #endif /* chips */
  66516 
  66517 #if defined(BCM_88650_B0)
  66518     { /* SOC_REG_INT_XLP_REG_062500_BCM88650_B0r */
  66519         soc_block_list[56],
  66520         soc_portreg,
  66521         1,
  66522         0,
  66523         0x62500,
  66524         SOC_REG_FLAG_64_BITS |
  66525                           SOC_REG_FLAG_SIGNAL,
  66526         0,
  66527         6,
  66528         soc_XLP_REG_062500_BCM88650_B0r_fields,
  66529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66530         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  66531         -1,
  66532         -1,
  66533     },
  66534 #endif /* chips */
  66535 
  66536 #if defined(BCM_88660_A0)
  66537     { /* SOC_REG_INT_XLP_REG_062500_BCM88660_A0r */
  66538         soc_block_list[56],
  66539         soc_portreg,
  66540         1,
  66541         0,
  66542         0x62500,
  66543         SOC_REG_FLAG_64_BITS |
  66544                           SOC_REG_FLAG_SIGNAL,
  66545         0,
  66546         6,
  66547         soc_XLP_REG_062500_BCM88660_A0r_fields,
  66548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66549         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  66550         -1,
  66551         -1,
  66552     },
  66553 #endif /* chips */
  66554 
  66555 #if defined(BCM_88375_A0)
  66556     { /* SOC_REG_INT_XLP_REG_2022300_BCM88375_A0r */
  66557         soc_block_list[56],
  66558         soc_genreg,
  66559         1,
  66560         0,
  66561         0x2022300,
  66562         0,
  66563         0,
  66564         1,
  66565         soc_XLP_REG_2022300_BCM88375_A0r_fields,
  66566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66567         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66568         -1,
  66569         -1,
  66570     },
  66571 #endif /* chips */
  66572 
  66573 #if defined(BCM_88470_A0)
  66574     { /* SOC_REG_INT_XLP_REG_2022300_BCM88470_A0r */
  66575         soc_block_list[56],
  66576         soc_genreg,
  66577         1,
  66578         0,
  66579         0x2022300,
  66580         0,
  66581         0,
  66582         1,
  66583         soc_XLP_REG_2022300_BCM88470_A0r_fields,
  66584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66585         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66586         -1,
  66587         -1,
  66588     },
  66589 #endif /* chips */
  66590 
  66591 #if defined(BCM_88675_A0)
  66592     { /* SOC_REG_INT_XLP_REG_2022300_BCM88675_A0r */
  66593         soc_block_list[56],
  66594         soc_genreg,
  66595         1,
  66596         0,
  66597         0x2022300,
  66598         SOC_REG_FLAG_IGNORE_DEFAULT,
  66599         0,
  66600         1,
  66601         soc_XLP_REG_2022300r_fields,
  66602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66603         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66604         -1,
  66605         -1,
  66606     },
  66607 #endif /* chips */
  66608 
  66609 #if defined(BCM_88732_A0)
  66610     { /* SOC_REG_INT_XLP_TO_MMU_BKP_STATUSr */
  66611         soc_block_list[4],
  66612         soc_portreg,
  66613         1,
  66614         0,
  66615         0xb000063,
  66616         0,
  66617         0,
  66618         2,
  66619         soc_XLP_TO_MMU_BKP_STATUSr_fields,
  66620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66621         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66622         -1,
  66623         50,
  66624     },
  66625 #endif /* chips */
  66626 
  66627 #if defined(BCM_56840_A0)
  66628     { /* SOC_REG_INT_XLP_TXFIFO_CELL_CNTr */
  66629         soc_block_list[16],
  66630         soc_portreg,
  66631         1,
  66632         0,
  66633         0x219,
  66634         SOC_REG_FLAG_RO,
  66635         0,
  66636         1,
  66637         soc_XLP_TXFIFO_CELL_CNTr_fields,
  66638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66639         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  66640         -1,
  66641         -1,
  66642     },
  66643 #endif /* chips */
  66644 
  66645 #if defined(BCM_56840_B0)
  66646     { /* SOC_REG_INT_XLP_TXFIFO_CELL_CNT_BCM56840_B0r */
  66647         soc_block_list[16],
  66648         soc_portreg,
  66649         1,
  66650         0,
  66651         0x219,
  66652         SOC_REG_FLAG_RO,
  66653         0,
  66654         1,
  66655         soc_XLP_TXFIFO_CELL_CNTr_fields,
  66656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66657         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  66658         -1,
  66659         -1,
  66660     },
  66661 #endif /* chips */
  66662 
  66663 #if defined(BCM_88732_A0)
  66664     { /* SOC_REG_INT_XLP_TXFIFO_CELL_CNT_BCM88732_A0r */
  66665         soc_block_list[16],
  66666         soc_portreg,
  66667         1,
  66668         0,
  66669         0x219,
  66670         SOC_REG_FLAG_RO,
  66671         0,
  66672         1,
  66673         soc_XLP_TXFIFO_CELL_CNTr_fields,
  66674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66675         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  66676         -1,
  66677         -1,
  66678     },
  66679 #endif /* chips */
  66680 
  66681 #if defined(BCM_56840_A0)
  66682     { /* SOC_REG_INT_XLP_TXFIFO_CELL_REQ_CNTr */
  66683         soc_block_list[16],
  66684         soc_portreg,
  66685         1,
  66686         0,
  66687         0x21a,
  66688         SOC_REG_FLAG_RO,
  66689         0,
  66690         1,
  66691         soc_XLP_TXFIFO_CELL_REQ_CNTr_fields,
  66692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66693         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  66694         -1,
  66695         -1,
  66696     },
  66697 #endif /* chips */
  66698 
  66699 #if defined(BCM_56840_B0)
  66700     { /* SOC_REG_INT_XLP_TXFIFO_CELL_REQ_CNT_BCM56840_B0r */
  66701         soc_block_list[16],
  66702         soc_portreg,
  66703         1,
  66704         0,
  66705         0x21a,
  66706         SOC_REG_FLAG_RO,
  66707         0,
  66708         1,
  66709         soc_XLP_TXFIFO_CELL_REQ_CNTr_fields,
  66710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66711         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  66712         -1,
  66713         -1,
  66714     },
  66715 #endif /* chips */
  66716 
  66717 #if defined(BCM_88732_A0)
  66718     { /* SOC_REG_INT_XLP_TXFIFO_CELL_REQ_CNT_BCM88732_A0r */
  66719         soc_block_list[16],
  66720         soc_portreg,
  66721         1,
  66722         0,
  66723         0x21a,
  66724         SOC_REG_FLAG_RO,
  66725         0,
  66726         1,
  66727         soc_XLP_TXFIFO_CELL_REQ_CNTr_fields,
  66728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66729         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  66730         -1,
  66731         -1,
  66732     },
  66733 #endif /* chips */
  66734 
  66735 #if defined(BCM_56840_A0)
  66736     { /* SOC_REG_INT_XLP_TXFIFO_OVRFLWr */
  66737         soc_block_list[16],
  66738         soc_portreg,
  66739         1,
  66740         0,
  66741         0x21b,
  66742         SOC_REG_FLAG_RO,
  66743         0,
  66744         1,
  66745         soc_GE0_GBOD_OVRFLWr_fields,
  66746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66747         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66748         -1,
  66749         -1,
  66750     },
  66751 #endif /* chips */
  66752 
  66753 #if defined(BCM_56840_B0)
  66754     { /* SOC_REG_INT_XLP_TXFIFO_OVRFLW_BCM56840_B0r */
  66755         soc_block_list[16],
  66756         soc_portreg,
  66757         1,
  66758         0,
  66759         0x21b,
  66760         SOC_REG_FLAG_RO,
  66761         0,
  66762         1,
  66763         soc_GE0_GBOD_OVRFLWr_fields,
  66764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66765         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66766         -1,
  66767         -1,
  66768     },
  66769 #endif /* chips */
  66770 
  66771 #if defined(BCM_88732_A0)
  66772     { /* SOC_REG_INT_XLP_TXFIFO_OVRFLW_BCM88732_A0r */
  66773         soc_block_list[16],
  66774         soc_portreg,
  66775         1,
  66776         0,
  66777         0x21b,
  66778         SOC_REG_FLAG_RO,
  66779         0,
  66780         1,
  66781         soc_GE0_GBOD_OVRFLWr_fields,
  66782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66783         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66784         -1,
  66785         -1,
  66786     },
  66787 #endif /* chips */
  66788 
  66789 #if defined(BCM_56840_A0)
  66790     { /* SOC_REG_INT_XLP_TXFIFO_PKT_DROP_CTLr */
  66791         soc_block_list[16],
  66792         soc_portreg,
  66793         1,
  66794         0,
  66795         0x218,
  66796         0,
  66797         0,
  66798         1,
  66799         soc_XLP_TXFIFO_PKT_DROP_CTLr_fields,
  66800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66801         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66802         -1,
  66803         -1,
  66804     },
  66805 #endif /* chips */
  66806 
  66807 #if defined(BCM_56840_B0)
  66808     { /* SOC_REG_INT_XLP_TXFIFO_PKT_DROP_CTL_BCM56840_B0r */
  66809         soc_block_list[16],
  66810         soc_portreg,
  66811         1,
  66812         0,
  66813         0x218,
  66814         0,
  66815         0,
  66816         1,
  66817         soc_XLP_TXFIFO_PKT_DROP_CTLr_fields,
  66818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66819         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66820         -1,
  66821         -1,
  66822     },
  66823 #endif /* chips */
  66824 
  66825 #if defined(BCM_88732_A0)
  66826     { /* SOC_REG_INT_XLP_TXFIFO_PKT_DROP_CTL_BCM88732_A0r */
  66827         soc_block_list[16],
  66828         soc_portreg,
  66829         1,
  66830         0,
  66831         0x218,
  66832         0,
  66833         0,
  66834         1,
  66835         soc_XLP_TXFIFO_PKT_DROP_CTLr_fields,
  66836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66837         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  66838         -1,
  66839         -1,
  66840     },
  66841 #endif /* chips */
  66842 
  66843 #if defined(BCM_88650_A0)
  66844     { /* SOC_REG_INT_XLP_XMAC_CLEAR_FIFO_STATUSr */
  66845         soc_block_list[56],
  66846         soc_portreg,
  66847         1,
  66848         0,
  66849         0x61900,
  66850         SOC_REG_FLAG_RO,
  66851         0,
  66852         7,
  66853         soc_XLP_XMAC_CLEAR_FIFO_STATUSr_fields,
  66854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66855         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  66856         -1,
  66857         -1,
  66858     },
  66859 #endif /* chips */
  66860 
  66861 #if defined(BCM_88650_B0)
  66862     { /* SOC_REG_INT_XLP_XMAC_CLEAR_FIFO_STATUS_BCM88650_B0r */
  66863         soc_block_list[56],
  66864         soc_portreg,
  66865         1,
  66866         0,
  66867         0x61900,
  66868         SOC_REG_FLAG_RO,
  66869         0,
  66870         7,
  66871         soc_XLP_XMAC_CLEAR_FIFO_STATUS_BCM88650_B0r_fields,
  66872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66873         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  66874         -1,
  66875         -1,
  66876     },
  66877 #endif /* chips */
  66878 
  66879 #if defined(BCM_88660_A0)
  66880     { /* SOC_REG_INT_XLP_XMAC_CLEAR_FIFO_STATUS_BCM88660_A0r */
  66881         soc_block_list[56],
  66882         soc_portreg,
  66883         1,
  66884         0,
  66885         0x61900,
  66886         SOC_REG_FLAG_RO,
  66887         0,
  66888         7,
  66889         soc_XLP_XMAC_CLEAR_FIFO_STATUS_BCM88660_A0r_fields,
  66890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66891         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  66892         -1,
  66893         -1,
  66894     },
  66895 #endif /* chips */
  66896 
  66897 #if defined(BCM_88650_A0)
  66898     { /* SOC_REG_INT_XLP_XMAC_CLEAR_RX_LSS_STATUSr */
  66899         soc_block_list[56],
  66900         soc_portreg,
  66901         1,
  66902         0,
  66903         0x60c00,
  66904         0,
  66905         0,
  66906         3,
  66907         soc_XLP_XMAC_CLEAR_RX_LSS_STATUSr_fields,
  66908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66909         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  66910         -1,
  66911         -1,
  66912     },
  66913 #endif /* chips */
  66914 
  66915 #if defined(BCM_88650_B0)
  66916     { /* SOC_REG_INT_XLP_XMAC_CLEAR_RX_LSS_STATUS_BCM88650_B0r */
  66917         soc_block_list[56],
  66918         soc_portreg,
  66919         1,
  66920         0,
  66921         0x60c00,
  66922         0,
  66923         0,
  66924         3,
  66925         soc_XLP_XMAC_CLEAR_RX_LSS_STATUS_BCM88650_B0r_fields,
  66926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66927         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  66928         -1,
  66929         -1,
  66930     },
  66931 #endif /* chips */
  66932 
  66933 #if defined(BCM_88660_A0)
  66934     { /* SOC_REG_INT_XLP_XMAC_CLEAR_RX_LSS_STATUS_BCM88660_A0r */
  66935         soc_block_list[56],
  66936         soc_portreg,
  66937         1,
  66938         0,
  66939         0x60c00,
  66940         0,
  66941         0,
  66942         3,
  66943         soc_XLP_XMAC_CLEAR_RX_LSS_STATUS_BCM88660_A0r_fields,
  66944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66945         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  66946         -1,
  66947         -1,
  66948     },
  66949 #endif /* chips */
  66950 
  66951 #if defined(BCM_88650_A0)
  66952     { /* SOC_REG_INT_XLP_XMAC_CTRLr */
  66953         soc_block_list[56],
  66954         soc_portreg,
  66955         1,
  66956         0,
  66957         0x60000,
  66958         SOC_REG_FLAG_SIGNAL,
  66959         0,
  66960         14,
  66961         soc_XLP_XMAC_CTRLr_fields,
  66962         SOC_RESET_VAL_DEC(0x00001040, 0x00000000)
  66963         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  66964         -1,
  66965         -1,
  66966     },
  66967 #endif /* chips */
  66968 
  66969 #if defined(BCM_88650_B0)
  66970     { /* SOC_REG_INT_XLP_XMAC_CTRL_BCM88650_B0r */
  66971         soc_block_list[56],
  66972         soc_portreg,
  66973         1,
  66974         0,
  66975         0x60000,
  66976         SOC_REG_FLAG_SIGNAL,
  66977         0,
  66978         14,
  66979         soc_XLP_XMAC_CTRL_BCM88650_B0r_fields,
  66980         SOC_RESET_VAL_DEC(0x00001040, 0x00000000)
  66981         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  66982         -1,
  66983         -1,
  66984     },
  66985 #endif /* chips */
  66986 
  66987 #if defined(BCM_88660_A0)
  66988     { /* SOC_REG_INT_XLP_XMAC_CTRL_BCM88660_A0r */
  66989         soc_block_list[56],
  66990         soc_portreg,
  66991         1,
  66992         0,
  66993         0x60000,
  66994         SOC_REG_FLAG_SIGNAL,
  66995         0,
  66996         14,
  66997         soc_XLP_XMAC_CTRL_BCM88660_A0r_fields,
  66998         SOC_RESET_VAL_DEC(0x00001040, 0x00000000)
  66999         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  67000         -1,
  67001         -1,
  67002     },
  67003 #endif /* chips */
  67004 
  67005 #if defined(BCM_88650_A0)
  67006     { /* SOC_REG_INT_XLP_XMAC_EEE_1_SEC_LINK_STATUS_TIMERr */
  67007         soc_block_list[56],
  67008         soc_portreg,
  67009         1,
  67010         0,
  67011         0x61d00,
  67012         0,
  67013         0,
  67014         1,
  67015         soc_XLP_XMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  67016         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  67017         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  67018         -1,
  67019         -1,
  67020     },
  67021 #endif /* chips */
  67022 
  67023 #if defined(BCM_88650_B0)
  67024     { /* SOC_REG_INT_XLP_XMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88650_B0r */
  67025         soc_block_list[56],
  67026         soc_portreg,
  67027         1,
  67028         0,
  67029         0x61d00,
  67030         0,
  67031         0,
  67032         1,
  67033         soc_XLP_XMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88650_B0r_fields,
  67034         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  67035         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  67036         -1,
  67037         -1,
  67038     },
  67039 #endif /* chips */
  67040 
  67041 #if defined(BCM_88660_A0)
  67042     { /* SOC_REG_INT_XLP_XMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88660_A0r */
  67043         soc_block_list[56],
  67044         soc_portreg,
  67045         1,
  67046         0,
  67047         0x61d00,
  67048         0,
  67049         0,
  67050         1,
  67051         soc_XLP_XMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88660_A0r_fields,
  67052         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  67053         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  67054         -1,
  67055         -1,
  67056     },
  67057 #endif /* chips */
  67058 
  67059 #if defined(BCM_88650_A0)
  67060     { /* SOC_REG_INT_XLP_XMAC_EEE_CTRLr */
  67061         soc_block_list[56],
  67062         soc_portreg,
  67063         1,
  67064         0,
  67065         0x61b00,
  67066         SOC_REG_FLAG_SIGNAL,
  67067         0,
  67068         4,
  67069         soc_XLP_XMAC_EEE_CTRLr_fields,
  67070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67071         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  67072         -1,
  67073         -1,
  67074     },
  67075 #endif /* chips */
  67076 
  67077 #if defined(BCM_88650_B0)
  67078     { /* SOC_REG_INT_XLP_XMAC_EEE_CTRL_BCM88650_B0r */
  67079         soc_block_list[56],
  67080         soc_portreg,
  67081         1,
  67082         0,
  67083         0x61b00,
  67084         SOC_REG_FLAG_SIGNAL,
  67085         0,
  67086         4,
  67087         soc_XLP_XMAC_EEE_CTRL_BCM88650_B0r_fields,
  67088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67089         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  67090         -1,
  67091         -1,
  67092     },
  67093 #endif /* chips */
  67094 
  67095 #if defined(BCM_88660_A0)
  67096     { /* SOC_REG_INT_XLP_XMAC_EEE_CTRL_BCM88660_A0r */
  67097         soc_block_list[56],
  67098         soc_portreg,
  67099         1,
  67100         0,
  67101         0x61b00,
  67102         SOC_REG_FLAG_SIGNAL,
  67103         0,
  67104         4,
  67105         soc_XLP_XMAC_EEE_CTRL_BCM88660_A0r_fields,
  67106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67107         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  67108         -1,
  67109         -1,
  67110     },
  67111 #endif /* chips */
  67112 
  67113 #if defined(BCM_88650_A0)
  67114     { /* SOC_REG_INT_XLP_XMAC_EEE_TIMERSr */
  67115         soc_block_list[56],
  67116         soc_portreg,
  67117         1,
  67118         0,
  67119         0x61c00,
  67120         SOC_REG_FLAG_64_BITS,
  67121         0,
  67122         5,
  67123         soc_XLP_XMAC_EEE_TIMERSr_fields,
  67124         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  67125         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67126         -1,
  67127         -1,
  67128     },
  67129 #endif /* chips */
  67130 
  67131 #if defined(BCM_88650_B0)
  67132     { /* SOC_REG_INT_XLP_XMAC_EEE_TIMERS_BCM88650_B0r */
  67133         soc_block_list[56],
  67134         soc_portreg,
  67135         1,
  67136         0,
  67137         0x61c00,
  67138         SOC_REG_FLAG_64_BITS,
  67139         0,
  67140         5,
  67141         soc_XLP_XMAC_EEE_TIMERS_BCM88650_B0r_fields,
  67142         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  67143         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67144         -1,
  67145         -1,
  67146     },
  67147 #endif /* chips */
  67148 
  67149 #if defined(BCM_88660_A0)
  67150     { /* SOC_REG_INT_XLP_XMAC_EEE_TIMERS_BCM88660_A0r */
  67151         soc_block_list[56],
  67152         soc_portreg,
  67153         1,
  67154         0,
  67155         0x61c00,
  67156         SOC_REG_FLAG_64_BITS,
  67157         0,
  67158         5,
  67159         soc_XLP_XMAC_EEE_TIMERS_BCM88660_A0r_fields,
  67160         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  67161         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67162         -1,
  67163         -1,
  67164     },
  67165 #endif /* chips */
  67166 
  67167 #if defined(BCM_88650_A0)
  67168     { /* SOC_REG_INT_XLP_XMAC_FIFO_STATUSr */
  67169         soc_block_list[56],
  67170         soc_portreg,
  67171         1,
  67172         0,
  67173         0x61800,
  67174         SOC_REG_FLAG_RO,
  67175         0,
  67176         8,
  67177         soc_XLP_XMAC_FIFO_STATUSr_fields,
  67178         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  67179         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  67180         -1,
  67181         -1,
  67182     },
  67183 #endif /* chips */
  67184 
  67185 #if defined(BCM_88650_B0)
  67186     { /* SOC_REG_INT_XLP_XMAC_FIFO_STATUS_BCM88650_B0r */
  67187         soc_block_list[56],
  67188         soc_portreg,
  67189         1,
  67190         0,
  67191         0x61800,
  67192         SOC_REG_FLAG_RO,
  67193         0,
  67194         8,
  67195         soc_XLP_XMAC_FIFO_STATUS_BCM88650_B0r_fields,
  67196         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  67197         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  67198         -1,
  67199         -1,
  67200     },
  67201 #endif /* chips */
  67202 
  67203 #if defined(BCM_88660_A0)
  67204     { /* SOC_REG_INT_XLP_XMAC_FIFO_STATUS_BCM88660_A0r */
  67205         soc_block_list[56],
  67206         soc_portreg,
  67207         1,
  67208         0,
  67209         0x61800,
  67210         SOC_REG_FLAG_RO,
  67211         0,
  67212         8,
  67213         soc_XLP_XMAC_FIFO_STATUS_BCM88660_A0r_fields,
  67214         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  67215         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  67216         -1,
  67217         -1,
  67218     },
  67219 #endif /* chips */
  67220 
  67221 #if defined(BCM_88650_A0)
  67222     { /* SOC_REG_INT_XLP_XMAC_GMII_EEE_CTRLr */
  67223         soc_block_list[56],
  67224         soc_portreg,
  67225         1,
  67226         0,
  67227         0x62300,
  67228         SOC_REG_FLAG_SIGNAL,
  67229         0,
  67230         3,
  67231         soc_XLP_XMAC_GMII_EEE_CTRLr_fields,
  67232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67233         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  67234         -1,
  67235         -1,
  67236     },
  67237 #endif /* chips */
  67238 
  67239 #if defined(BCM_88650_B0)
  67240     { /* SOC_REG_INT_XLP_XMAC_GMII_EEE_CTRL_BCM88650_B0r */
  67241         soc_block_list[56],
  67242         soc_portreg,
  67243         1,
  67244         0,
  67245         0x62300,
  67246         SOC_REG_FLAG_SIGNAL,
  67247         0,
  67248         3,
  67249         soc_XLP_XMAC_GMII_EEE_CTRL_BCM88650_B0r_fields,
  67250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67251         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  67252         -1,
  67253         -1,
  67254     },
  67255 #endif /* chips */
  67256 
  67257 #if defined(BCM_88660_A0)
  67258     { /* SOC_REG_INT_XLP_XMAC_GMII_EEE_CTRL_BCM88660_A0r */
  67259         soc_block_list[56],
  67260         soc_portreg,
  67261         1,
  67262         0,
  67263         0x62300,
  67264         SOC_REG_FLAG_SIGNAL,
  67265         0,
  67266         3,
  67267         soc_XLP_XMAC_GMII_EEE_CTRL_BCM88660_A0r_fields,
  67268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67269         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  67270         -1,
  67271         -1,
  67272     },
  67273 #endif /* chips */
  67274 
  67275 #if defined(BCM_88650_A0)
  67276     { /* SOC_REG_INT_XLP_XMAC_LH_HDR_3r */
  67277         soc_block_list[56],
  67278         soc_portreg,
  67279         1,
  67280         0,
  67281         0x62100,
  67282         SOC_REG_FLAG_64_BITS,
  67283         0,
  67284         3,
  67285         soc_XLP_XMAC_LH_HDR_3r_fields,
  67286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67287         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67288         -1,
  67289         -1,
  67290     },
  67291 #endif /* chips */
  67292 
  67293 #if defined(BCM_88650_B0)
  67294     { /* SOC_REG_INT_XLP_XMAC_LH_HDR_3_BCM88650_B0r */
  67295         soc_block_list[56],
  67296         soc_portreg,
  67297         1,
  67298         0,
  67299         0x62100,
  67300         SOC_REG_FLAG_64_BITS,
  67301         0,
  67302         3,
  67303         soc_XLP_XMAC_LH_HDR_3_BCM88650_B0r_fields,
  67304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67305         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67306         -1,
  67307         -1,
  67308     },
  67309 #endif /* chips */
  67310 
  67311 #if defined(BCM_88660_A0)
  67312     { /* SOC_REG_INT_XLP_XMAC_LH_HDR_3_BCM88660_A0r */
  67313         soc_block_list[56],
  67314         soc_portreg,
  67315         1,
  67316         0,
  67317         0x62100,
  67318         SOC_REG_FLAG_64_BITS,
  67319         0,
  67320         3,
  67321         soc_XLP_XMAC_LH_HDR_3_BCM88660_A0r_fields,
  67322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67323         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  67324         -1,
  67325         -1,
  67326     },
  67327 #endif /* chips */
  67328 
  67329 #if defined(BCM_88650_A0)
  67330     { /* SOC_REG_INT_XLP_XMAC_LLFC_CTRLr */
  67331         soc_block_list[56],
  67332         soc_portreg,
  67333         1,
  67334         0,
  67335         0x61200,
  67336         SOC_REG_FLAG_SIGNAL,
  67337         0,
  67338         7,
  67339         soc_XLP_XMAC_LLFC_CTRLr_fields,
  67340         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  67341         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  67342         -1,
  67343         -1,
  67344     },
  67345 #endif /* chips */
  67346 
  67347 #if defined(BCM_88650_B0)
  67348     { /* SOC_REG_INT_XLP_XMAC_LLFC_CTRL_BCM88650_B0r */
  67349         soc_block_list[56],
  67350         soc_portreg,
  67351         1,
  67352         0,
  67353         0x61200,
  67354         SOC_REG_FLAG_SIGNAL,
  67355         0,
  67356         7,
  67357         soc_XLP_XMAC_LLFC_CTRL_BCM88650_B0r_fields,
  67358         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  67359         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  67360         -1,
  67361         -1,
  67362     },
  67363 #endif /* chips */
  67364 
  67365 #if defined(BCM_88660_A0)
  67366     { /* SOC_REG_INT_XLP_XMAC_LLFC_CTRL_BCM88660_A0r */
  67367         soc_block_list[56],
  67368         soc_portreg,
  67369         1,
  67370         0,
  67371         0x61200,
  67372         SOC_REG_FLAG_SIGNAL,
  67373         0,
  67374         7,
  67375         soc_XLP_XMAC_LLFC_CTRL_BCM88660_A0r_fields,
  67376         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  67377         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  67378         -1,
  67379         -1,
  67380     },
  67381 #endif /* chips */
  67382 
  67383 #if defined(BCM_88650_A0)
  67384     { /* SOC_REG_INT_XLP_XMAC_MODEr */
  67385         soc_block_list[56],
  67386         soc_portreg,
  67387         1,
  67388         0,
  67389         0x60100,
  67390         0,
  67391         0,
  67392         3,
  67393         soc_XLP_XMAC_MODEr_fields,
  67394         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  67395         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  67396         -1,
  67397         -1,
  67398     },
  67399 #endif /* chips */
  67400 
  67401 #if defined(BCM_88650_B0)
  67402     { /* SOC_REG_INT_XLP_XMAC_MODE_BCM88650_B0r */
  67403         soc_block_list[56],
  67404         soc_portreg,
  67405         1,
  67406         0,
  67407         0x60100,
  67408         0,
  67409         0,
  67410         3,
  67411         soc_XLP_XMAC_MODE_BCM88650_B0r_fields,
  67412         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  67413         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  67414         -1,
  67415         -1,
  67416     },
  67417 #endif /* chips */
  67418 
  67419 #if defined(BCM_88660_A0)
  67420     { /* SOC_REG_INT_XLP_XMAC_MODE_BCM88660_A0r */
  67421         soc_block_list[56],
  67422         soc_portreg,
  67423         1,
  67424         0,
  67425         0x60100,
  67426         0,
  67427         0,
  67428         3,
  67429         soc_XLP_XMAC_MODE_BCM88660_A0r_fields,
  67430         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  67431         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  67432         -1,
  67433         -1,
  67434     },
  67435 #endif /* chips */
  67436 
  67437 #if defined(BCM_88650_A0)
  67438     { /* SOC_REG_INT_XLP_XMAC_OSTS_TIMESTAMP_ADJUSTr */
  67439         soc_block_list[56],
  67440         soc_portreg,
  67441         1,
  67442         0,
  67443         0x62400,
  67444         SOC_REG_FLAG_64_BITS,
  67445         0,
  67446         7,
  67447         soc_XLP_XMAC_OSTS_TIMESTAMP_ADJUSTr_fields,
  67448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67449         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  67450         -1,
  67451         -1,
  67452     },
  67453 #endif /* chips */
  67454 
  67455 #if defined(BCM_88650_B0)
  67456     { /* SOC_REG_INT_XLP_XMAC_OSTS_TIMESTAMP_ADJUST_BCM88650_B0r */
  67457         soc_block_list[56],
  67458         soc_portreg,
  67459         1,
  67460         0,
  67461         0x62400,
  67462         SOC_REG_FLAG_64_BITS,
  67463         0,
  67464         7,
  67465         soc_XLP_XMAC_OSTS_TIMESTAMP_ADJUST_BCM88650_B0r_fields,
  67466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67467         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  67468         -1,
  67469         -1,
  67470     },
  67471 #endif /* chips */
  67472 
  67473 #if defined(BCM_88660_A0)
  67474     { /* SOC_REG_INT_XLP_XMAC_OSTS_TIMESTAMP_ADJUST_BCM88660_A0r */
  67475         soc_block_list[56],
  67476         soc_portreg,
  67477         1,
  67478         0,
  67479         0x62400,
  67480         SOC_REG_FLAG_64_BITS,
  67481         0,
  67482         8,
  67483         soc_XLP_XMAC_OSTS_TIMESTAMP_ADJUST_BCM88660_A0r_fields,
  67484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67485         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  67486         -1,
  67487         -1,
  67488     },
  67489 #endif /* chips */
  67490 
  67491 #if defined(BCM_88650_A0)
  67492     { /* SOC_REG_INT_XLP_XMAC_PAUSE_CTRLr */
  67493         soc_block_list[56],
  67494         soc_portreg,
  67495         1,
  67496         0,
  67497         0x60d00,
  67498         SOC_REG_FLAG_64_BITS |
  67499                           SOC_REG_FLAG_SIGNAL,
  67500         0,
  67501         9,
  67502         soc_XLP_XMAC_PAUSE_CTRLr_fields,
  67503         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  67504         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  67505         -1,
  67506         -1,
  67507     },
  67508 #endif /* chips */
  67509 
  67510 #if defined(BCM_88650_B0)
  67511     { /* SOC_REG_INT_XLP_XMAC_PAUSE_CTRL_BCM88650_B0r */
  67512         soc_block_list[56],
  67513         soc_portreg,
  67514         1,
  67515         0,
  67516         0x60d00,
  67517         SOC_REG_FLAG_64_BITS |
  67518                           SOC_REG_FLAG_SIGNAL,
  67519         0,
  67520         9,
  67521         soc_XLP_XMAC_PAUSE_CTRL_BCM88650_B0r_fields,
  67522         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  67523         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  67524         -1,
  67525         -1,
  67526     },
  67527 #endif /* chips */
  67528 
  67529 #if defined(BCM_88660_A0)
  67530     { /* SOC_REG_INT_XLP_XMAC_PAUSE_CTRL_BCM88660_A0r */
  67531         soc_block_list[56],
  67532         soc_portreg,
  67533         1,
  67534         0,
  67535         0x60d00,
  67536         SOC_REG_FLAG_64_BITS |
  67537                           SOC_REG_FLAG_SIGNAL,
  67538         0,
  67539         9,
  67540         soc_XLP_XMAC_PAUSE_CTRL_BCM88660_A0r_fields,
  67541         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  67542         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  67543         -1,
  67544         -1,
  67545     },
  67546 #endif /* chips */
  67547 
  67548 #if defined(BCM_88650_A0)
  67549     { /* SOC_REG_INT_XLP_XMAC_PFC_CTRLr */
  67550         soc_block_list[56],
  67551         soc_portreg,
  67552         1,
  67553         0,
  67554         0x60e00,
  67555         SOC_REG_FLAG_64_BITS |
  67556                           SOC_REG_FLAG_SIGNAL,
  67557         0,
  67558         8,
  67559         soc_XLP_XMAC_PFC_CTRLr_fields,
  67560         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  67561         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  67562         -1,
  67563         -1,
  67564     },
  67565 #endif /* chips */
  67566 
  67567 #if defined(BCM_88650_B0)
  67568     { /* SOC_REG_INT_XLP_XMAC_PFC_CTRL_BCM88650_B0r */
  67569         soc_block_list[56],
  67570         soc_portreg,
  67571         1,
  67572         0,
  67573         0x60e00,
  67574         SOC_REG_FLAG_64_BITS |
  67575                           SOC_REG_FLAG_SIGNAL,
  67576         0,
  67577         8,
  67578         soc_XLP_XMAC_PFC_CTRL_BCM88650_B0r_fields,
  67579         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  67580         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  67581         -1,
  67582         -1,
  67583     },
  67584 #endif /* chips */
  67585 
  67586 #if defined(BCM_88660_A0)
  67587     { /* SOC_REG_INT_XLP_XMAC_PFC_CTRL_BCM88660_A0r */
  67588         soc_block_list[56],
  67589         soc_portreg,
  67590         1,
  67591         0,
  67592         0x60e00,
  67593         SOC_REG_FLAG_64_BITS |
  67594                           SOC_REG_FLAG_SIGNAL,
  67595         0,
  67596         8,
  67597         soc_XLP_XMAC_PFC_CTRL_BCM88660_A0r_fields,
  67598         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  67599         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  67600         -1,
  67601         -1,
  67602     },
  67603 #endif /* chips */
  67604 
  67605 #if defined(BCM_88650_A0)
  67606     { /* SOC_REG_INT_XLP_XMAC_PFC_DAr */
  67607         soc_block_list[56],
  67608         soc_portreg,
  67609         1,
  67610         0,
  67611         0x61100,
  67612         SOC_REG_FLAG_64_BITS,
  67613         0,
  67614         3,
  67615         soc_XLP_XMAC_PFC_DAr_fields,
  67616         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  67617         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  67618         -1,
  67619         -1,
  67620     },
  67621 #endif /* chips */
  67622 
  67623 #if defined(BCM_88650_B0)
  67624     { /* SOC_REG_INT_XLP_XMAC_PFC_DA_BCM88650_B0r */
  67625         soc_block_list[56],
  67626         soc_portreg,
  67627         1,
  67628         0,
  67629         0x61100,
  67630         SOC_REG_FLAG_64_BITS,
  67631         0,
  67632         3,
  67633         soc_XLP_XMAC_PFC_DA_BCM88650_B0r_fields,
  67634         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  67635         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  67636         -1,
  67637         -1,
  67638     },
  67639 #endif /* chips */
  67640 
  67641 #if defined(BCM_88660_A0)
  67642     { /* SOC_REG_INT_XLP_XMAC_PFC_DA_BCM88660_A0r */
  67643         soc_block_list[56],
  67644         soc_portreg,
  67645         1,
  67646         0,
  67647         0x61100,
  67648         SOC_REG_FLAG_64_BITS,
  67649         0,
  67650         3,
  67651         soc_XLP_XMAC_PFC_DA_BCM88660_A0r_fields,
  67652         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  67653         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  67654         -1,
  67655         -1,
  67656     },
  67657 #endif /* chips */
  67658 
  67659 #if defined(BCM_88650_A0)
  67660     { /* SOC_REG_INT_XLP_XMAC_PFC_OPCODEr */
  67661         soc_block_list[56],
  67662         soc_portreg,
  67663         1,
  67664         0,
  67665         0x61000,
  67666         0,
  67667         0,
  67668         1,
  67669         soc_XLP_XMAC_PFC_OPCODEr_fields,
  67670         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  67671         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  67672         -1,
  67673         -1,
  67674     },
  67675 #endif /* chips */
  67676 
  67677 #if defined(BCM_88650_B0)
  67678     { /* SOC_REG_INT_XLP_XMAC_PFC_OPCODE_BCM88650_B0r */
  67679         soc_block_list[56],
  67680         soc_portreg,
  67681         1,
  67682         0,
  67683         0x61000,
  67684         0,
  67685         0,
  67686         1,
  67687         soc_XLP_XMAC_PFC_OPCODE_BCM88650_B0r_fields,
  67688         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  67689         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  67690         -1,
  67691         -1,
  67692     },
  67693 #endif /* chips */
  67694 
  67695 #if defined(BCM_88660_A0)
  67696     { /* SOC_REG_INT_XLP_XMAC_PFC_OPCODE_BCM88660_A0r */
  67697         soc_block_list[56],
  67698         soc_portreg,
  67699         1,
  67700         0,
  67701         0x61000,
  67702         0,
  67703         0,
  67704         1,
  67705         soc_XLP_XMAC_PFC_OPCODE_BCM88660_A0r_fields,
  67706         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  67707         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  67708         -1,
  67709         -1,
  67710     },
  67711 #endif /* chips */
  67712 
  67713 #if defined(BCM_88650_A0)
  67714     { /* SOC_REG_INT_XLP_XMAC_PFC_TYPEr */
  67715         soc_block_list[56],
  67716         soc_portreg,
  67717         1,
  67718         0,
  67719         0x60f00,
  67720         0,
  67721         0,
  67722         1,
  67723         soc_XLP_XMAC_PFC_TYPEr_fields,
  67724         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  67725         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  67726         -1,
  67727         -1,
  67728     },
  67729 #endif /* chips */
  67730 
  67731 #if defined(BCM_88650_B0)
  67732     { /* SOC_REG_INT_XLP_XMAC_PFC_TYPE_BCM88650_B0r */
  67733         soc_block_list[56],
  67734         soc_portreg,
  67735         1,
  67736         0,
  67737         0x60f00,
  67738         0,
  67739         0,
  67740         1,
  67741         soc_XLP_XMAC_PFC_TYPE_BCM88650_B0r_fields,
  67742         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  67743         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  67744         -1,
  67745         -1,
  67746     },
  67747 #endif /* chips */
  67748 
  67749 #if defined(BCM_88660_A0)
  67750     { /* SOC_REG_INT_XLP_XMAC_PFC_TYPE_BCM88660_A0r */
  67751         soc_block_list[56],
  67752         soc_portreg,
  67753         1,
  67754         0,
  67755         0x60f00,
  67756         0,
  67757         0,
  67758         1,
  67759         soc_XLP_XMAC_PFC_TYPE_BCM88660_A0r_fields,
  67760         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  67761         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  67762         -1,
  67763         -1,
  67764     },
  67765 #endif /* chips */
  67766 
  67767 #if defined(BCM_88650_A0)
  67768     { /* SOC_REG_INT_XLP_XMAC_RX_CTRLr */
  67769         soc_block_list[56],
  67770         soc_portreg,
  67771         1,
  67772         0,
  67773         0x60600,
  67774         SOC_REG_FLAG_SIGNAL,
  67775         0,
  67776         7,
  67777         soc_XLP_XMAC_RX_CTRLr_fields,
  67778         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  67779         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67780         -1,
  67781         -1,
  67782     },
  67783 #endif /* chips */
  67784 
  67785 #if defined(BCM_88650_B0)
  67786     { /* SOC_REG_INT_XLP_XMAC_RX_CTRL_BCM88650_B0r */
  67787         soc_block_list[56],
  67788         soc_portreg,
  67789         1,
  67790         0,
  67791         0x60600,
  67792         SOC_REG_FLAG_SIGNAL,
  67793         0,
  67794         7,
  67795         soc_XLP_XMAC_RX_CTRL_BCM88650_B0r_fields,
  67796         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  67797         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67798         -1,
  67799         -1,
  67800     },
  67801 #endif /* chips */
  67802 
  67803 #if defined(BCM_88660_A0)
  67804     { /* SOC_REG_INT_XLP_XMAC_RX_CTRL_BCM88660_A0r */
  67805         soc_block_list[56],
  67806         soc_portreg,
  67807         1,
  67808         0,
  67809         0x60600,
  67810         SOC_REG_FLAG_SIGNAL,
  67811         0,
  67812         7,
  67813         soc_XLP_XMAC_RX_CTRL_BCM88660_A0r_fields,
  67814         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  67815         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67816         -1,
  67817         -1,
  67818     },
  67819 #endif /* chips */
  67820 
  67821 #if defined(BCM_88650_A0)
  67822     { /* SOC_REG_INT_XLP_XMAC_RX_LLFC_MSG_FIELDSr */
  67823         soc_block_list[56],
  67824         soc_portreg,
  67825         1,
  67826         0,
  67827         0x61400,
  67828         0,
  67829         0,
  67830         4,
  67831         soc_XLP_XMAC_RX_LLFC_MSG_FIELDSr_fields,
  67832         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  67833         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  67834         -1,
  67835         -1,
  67836     },
  67837 #endif /* chips */
  67838 
  67839 #if defined(BCM_88650_B0)
  67840     { /* SOC_REG_INT_XLP_XMAC_RX_LLFC_MSG_FIELDS_BCM88650_B0r */
  67841         soc_block_list[56],
  67842         soc_portreg,
  67843         1,
  67844         0,
  67845         0x61400,
  67846         0,
  67847         0,
  67848         4,
  67849         soc_XLP_XMAC_RX_LLFC_MSG_FIELDS_BCM88650_B0r_fields,
  67850         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  67851         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  67852         -1,
  67853         -1,
  67854     },
  67855 #endif /* chips */
  67856 
  67857 #if defined(BCM_88660_A0)
  67858     { /* SOC_REG_INT_XLP_XMAC_RX_LLFC_MSG_FIELDS_BCM88660_A0r */
  67859         soc_block_list[56],
  67860         soc_portreg,
  67861         1,
  67862         0,
  67863         0x61400,
  67864         0,
  67865         0,
  67866         4,
  67867         soc_XLP_XMAC_RX_LLFC_MSG_FIELDS_BCM88660_A0r_fields,
  67868         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  67869         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  67870         -1,
  67871         -1,
  67872     },
  67873 #endif /* chips */
  67874 
  67875 #if defined(BCM_88650_A0)
  67876     { /* SOC_REG_INT_XLP_XMAC_RX_LSS_CTRLr */
  67877         soc_block_list[56],
  67878         soc_portreg,
  67879         1,
  67880         0,
  67881         0x60a00,
  67882         SOC_REG_FLAG_SIGNAL,
  67883         0,
  67884         8,
  67885         soc_XLP_XMAC_RX_LSS_CTRLr_fields,
  67886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67887         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  67888         -1,
  67889         -1,
  67890     },
  67891 #endif /* chips */
  67892 
  67893 #if defined(BCM_88650_B0)
  67894     { /* SOC_REG_INT_XLP_XMAC_RX_LSS_CTRL_BCM88650_B0r */
  67895         soc_block_list[56],
  67896         soc_portreg,
  67897         1,
  67898         0,
  67899         0x60a00,
  67900         SOC_REG_FLAG_SIGNAL,
  67901         0,
  67902         8,
  67903         soc_XLP_XMAC_RX_LSS_CTRL_BCM88650_B0r_fields,
  67904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67905         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  67906         -1,
  67907         -1,
  67908     },
  67909 #endif /* chips */
  67910 
  67911 #if defined(BCM_88660_A0)
  67912     { /* SOC_REG_INT_XLP_XMAC_RX_LSS_CTRL_BCM88660_A0r */
  67913         soc_block_list[56],
  67914         soc_portreg,
  67915         1,
  67916         0,
  67917         0x60a00,
  67918         SOC_REG_FLAG_SIGNAL,
  67919         0,
  67920         8,
  67921         soc_XLP_XMAC_RX_LSS_CTRL_BCM88660_A0r_fields,
  67922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67923         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  67924         -1,
  67925         -1,
  67926     },
  67927 #endif /* chips */
  67928 
  67929 #if defined(BCM_88650_A0)
  67930     { /* SOC_REG_INT_XLP_XMAC_RX_LSS_STATUSr */
  67931         soc_block_list[56],
  67932         soc_portreg,
  67933         1,
  67934         0,
  67935         0x60b00,
  67936         SOC_REG_FLAG_RO,
  67937         0,
  67938         3,
  67939         soc_XLP_XMAC_RX_LSS_STATUSr_fields,
  67940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67941         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  67942         -1,
  67943         -1,
  67944     },
  67945 #endif /* chips */
  67946 
  67947 #if defined(BCM_88650_B0)
  67948     { /* SOC_REG_INT_XLP_XMAC_RX_LSS_STATUS_BCM88650_B0r */
  67949         soc_block_list[56],
  67950         soc_portreg,
  67951         1,
  67952         0,
  67953         0x60b00,
  67954         SOC_REG_FLAG_RO,
  67955         0,
  67956         3,
  67957         soc_XLP_XMAC_RX_LSS_STATUS_BCM88650_B0r_fields,
  67958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67959         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  67960         -1,
  67961         -1,
  67962     },
  67963 #endif /* chips */
  67964 
  67965 #if defined(BCM_88660_A0)
  67966     { /* SOC_REG_INT_XLP_XMAC_RX_LSS_STATUS_BCM88660_A0r */
  67967         soc_block_list[56],
  67968         soc_portreg,
  67969         1,
  67970         0,
  67971         0x60b00,
  67972         SOC_REG_FLAG_RO,
  67973         0,
  67974         3,
  67975         soc_XLP_XMAC_RX_LSS_STATUS_BCM88660_A0r_fields,
  67976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67977         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  67978         -1,
  67979         -1,
  67980     },
  67981 #endif /* chips */
  67982 
  67983 #if defined(BCM_88650_A0)
  67984     { /* SOC_REG_INT_XLP_XMAC_RX_MAC_SAr */
  67985         soc_block_list[56],
  67986         soc_portreg,
  67987         1,
  67988         0,
  67989         0x60700,
  67990         SOC_REG_FLAG_64_BITS,
  67991         0,
  67992         3,
  67993         soc_XLP_XMAC_RX_MAC_SAr_fields,
  67994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67995         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  67996         -1,
  67997         -1,
  67998     },
  67999 #endif /* chips */
  68000 
  68001 #if defined(BCM_88650_B0)
  68002     { /* SOC_REG_INT_XLP_XMAC_RX_MAC_SA_BCM88650_B0r */
  68003         soc_block_list[56],
  68004         soc_portreg,
  68005         1,
  68006         0,
  68007         0x60700,
  68008         SOC_REG_FLAG_64_BITS,
  68009         0,
  68010         3,
  68011         soc_XLP_XMAC_RX_MAC_SA_BCM88650_B0r_fields,
  68012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68013         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  68014         -1,
  68015         -1,
  68016     },
  68017 #endif /* chips */
  68018 
  68019 #if defined(BCM_88660_A0)
  68020     { /* SOC_REG_INT_XLP_XMAC_RX_MAC_SA_BCM88660_A0r */
  68021         soc_block_list[56],
  68022         soc_portreg,
  68023         1,
  68024         0,
  68025         0x60700,
  68026         SOC_REG_FLAG_64_BITS,
  68027         0,
  68028         3,
  68029         soc_XLP_XMAC_RX_MAC_SA_BCM88660_A0r_fields,
  68030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68031         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  68032         -1,
  68033         -1,
  68034     },
  68035 #endif /* chips */
  68036 
  68037 #if defined(BCM_88650_A0)
  68038     { /* SOC_REG_INT_XLP_XMAC_RX_MAX_SIZEr */
  68039         soc_block_list[56],
  68040         soc_portreg,
  68041         1,
  68042         0,
  68043         0x60800,
  68044         0,
  68045         0,
  68046         1,
  68047         soc_XLP_XMAC_RX_MAX_SIZEr_fields,
  68048         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  68049         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  68050         -1,
  68051         -1,
  68052     },
  68053 #endif /* chips */
  68054 
  68055 #if defined(BCM_88650_B0)
  68056     { /* SOC_REG_INT_XLP_XMAC_RX_MAX_SIZE_BCM88650_B0r */
  68057         soc_block_list[56],
  68058         soc_portreg,
  68059         1,
  68060         0,
  68061         0x60800,
  68062         0,
  68063         0,
  68064         1,
  68065         soc_XLP_XMAC_RX_MAX_SIZE_BCM88650_B0r_fields,
  68066         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  68067         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  68068         -1,
  68069         -1,
  68070     },
  68071 #endif /* chips */
  68072 
  68073 #if defined(BCM_88660_A0)
  68074     { /* SOC_REG_INT_XLP_XMAC_RX_MAX_SIZE_BCM88660_A0r */
  68075         soc_block_list[56],
  68076         soc_portreg,
  68077         1,
  68078         0,
  68079         0x60800,
  68080         0,
  68081         0,
  68082         1,
  68083         soc_XLP_XMAC_RX_MAX_SIZE_BCM88660_A0r_fields,
  68084         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  68085         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  68086         -1,
  68087         -1,
  68088     },
  68089 #endif /* chips */
  68090 
  68091 #if defined(BCM_88650_A0)
  68092     { /* SOC_REG_INT_XLP_XMAC_RX_VLAN_TAGr */
  68093         soc_block_list[56],
  68094         soc_portreg,
  68095         1,
  68096         0,
  68097         0x60900,
  68098         SOC_REG_FLAG_64_BITS,
  68099         0,
  68100         4,
  68101         soc_XLP_XMAC_RX_VLAN_TAGr_fields,
  68102         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  68103         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  68104         -1,
  68105         -1,
  68106     },
  68107 #endif /* chips */
  68108 
  68109 #if defined(BCM_88650_B0)
  68110     { /* SOC_REG_INT_XLP_XMAC_RX_VLAN_TAG_BCM88650_B0r */
  68111         soc_block_list[56],
  68112         soc_portreg,
  68113         1,
  68114         0,
  68115         0x60900,
  68116         SOC_REG_FLAG_64_BITS,
  68117         0,
  68118         4,
  68119         soc_XLP_XMAC_RX_VLAN_TAG_BCM88650_B0r_fields,
  68120         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  68121         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  68122         -1,
  68123         -1,
  68124     },
  68125 #endif /* chips */
  68126 
  68127 #if defined(BCM_88660_A0)
  68128     { /* SOC_REG_INT_XLP_XMAC_RX_VLAN_TAG_BCM88660_A0r */
  68129         soc_block_list[56],
  68130         soc_portreg,
  68131         1,
  68132         0,
  68133         0x60900,
  68134         SOC_REG_FLAG_64_BITS,
  68135         0,
  68136         4,
  68137         soc_XLP_XMAC_RX_VLAN_TAG_BCM88660_A0r_fields,
  68138         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  68139         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  68140         -1,
  68141         -1,
  68142     },
  68143 #endif /* chips */
  68144 
  68145 #if defined(BCM_88650_A0)
  68146     { /* SOC_REG_INT_XLP_XMAC_TX_CTRLr */
  68147         soc_block_list[56],
  68148         soc_portreg,
  68149         1,
  68150         0,
  68151         0x60400,
  68152         SOC_REG_FLAG_64_BITS |
  68153                           SOC_REG_FLAG_SIGNAL,
  68154         0,
  68155         12,
  68156         soc_XLP_XMAC_TX_CTRLr_fields,
  68157         SOC_RESET_VAL_DEC(0x0000c802, 0x00000010)
  68158         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  68159         -1,
  68160         -1,
  68161     },
  68162 #endif /* chips */
  68163 
  68164 #if defined(BCM_88650_B0)
  68165     { /* SOC_REG_INT_XLP_XMAC_TX_CTRL_BCM88650_B0r */
  68166         soc_block_list[56],
  68167         soc_portreg,
  68168         1,
  68169         0,
  68170         0x60400,
  68171         SOC_REG_FLAG_64_BITS |
  68172                           SOC_REG_FLAG_SIGNAL,
  68173         0,
  68174         12,
  68175         soc_XLP_XMAC_TX_CTRL_BCM88650_B0r_fields,
  68176         SOC_RESET_VAL_DEC(0x0000c802, 0x00000010)
  68177         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  68178         -1,
  68179         -1,
  68180     },
  68181 #endif /* chips */
  68182 
  68183 #if defined(BCM_88660_A0)
  68184     { /* SOC_REG_INT_XLP_XMAC_TX_CTRL_BCM88660_A0r */
  68185         soc_block_list[56],
  68186         soc_portreg,
  68187         1,
  68188         0,
  68189         0x60400,
  68190         SOC_REG_FLAG_64_BITS |
  68191                           SOC_REG_FLAG_SIGNAL,
  68192         0,
  68193         12,
  68194         soc_XLP_XMAC_TX_CTRL_BCM88660_A0r_fields,
  68195         SOC_RESET_VAL_DEC(0x0000c802, 0x00000010)
  68196         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  68197         -1,
  68198         -1,
  68199     },
  68200 #endif /* chips */
  68201 
  68202 #if defined(BCM_88650_A0)
  68203     { /* SOC_REG_INT_XLP_XMAC_TX_FIFO_CREDITSr */
  68204         soc_block_list[56],
  68205         soc_portreg,
  68206         1,
  68207         0,
  68208         0x61a00,
  68209         0,
  68210         0,
  68211         3,
  68212         soc_XLP_XMAC_TX_FIFO_CREDITSr_fields,
  68213         SOC_RESET_VAL_DEC(0x00010308, 0x00000000)
  68214         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  68215         -1,
  68216         -1,
  68217     },
  68218 #endif /* chips */
  68219 
  68220 #if defined(BCM_88650_B0)
  68221     { /* SOC_REG_INT_XLP_XMAC_TX_FIFO_CREDITS_BCM88650_B0r */
  68222         soc_block_list[56],
  68223         soc_portreg,
  68224         1,
  68225         0,
  68226         0x61a00,
  68227         0,
  68228         0,
  68229         3,
  68230         soc_XLP_XMAC_TX_FIFO_CREDITS_BCM88650_B0r_fields,
  68231         SOC_RESET_VAL_DEC(0x00010308, 0x00000000)
  68232         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  68233         -1,
  68234         -1,
  68235     },
  68236 #endif /* chips */
  68237 
  68238 #if defined(BCM_88660_A0)
  68239     { /* SOC_REG_INT_XLP_XMAC_TX_FIFO_CREDITS_BCM88660_A0r */
  68240         soc_block_list[56],
  68241         soc_portreg,
  68242         1,
  68243         0,
  68244         0x61a00,
  68245         0,
  68246         0,
  68247         3,
  68248         soc_XLP_XMAC_TX_FIFO_CREDITS_BCM88660_A0r_fields,
  68249         SOC_RESET_VAL_DEC(0x00010308, 0x00000000)
  68250         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  68251         -1,
  68252         -1,
  68253     },
  68254 #endif /* chips */
  68255 
  68256 #if defined(BCM_88650_A0)
  68257     { /* SOC_REG_INT_XLP_XMAC_TX_LLFC_MSG_FIELDSr */
  68258         soc_block_list[56],
  68259         soc_portreg,
  68260         1,
  68261         0,
  68262         0x61300,
  68263         0,
  68264         0,
  68265         3,
  68266         soc_XLP_XMAC_TX_LLFC_MSG_FIELDSr_fields,
  68267         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  68268         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  68269         -1,
  68270         -1,
  68271     },
  68272 #endif /* chips */
  68273 
  68274 #if defined(BCM_88650_B0)
  68275     { /* SOC_REG_INT_XLP_XMAC_TX_LLFC_MSG_FIELDS_BCM88650_B0r */
  68276         soc_block_list[56],
  68277         soc_portreg,
  68278         1,
  68279         0,
  68280         0x61300,
  68281         0,
  68282         0,
  68283         3,
  68284         soc_XLP_XMAC_TX_LLFC_MSG_FIELDS_BCM88650_B0r_fields,
  68285         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  68286         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  68287         -1,
  68288         -1,
  68289     },
  68290 #endif /* chips */
  68291 
  68292 #if defined(BCM_88660_A0)
  68293     { /* SOC_REG_INT_XLP_XMAC_TX_LLFC_MSG_FIELDS_BCM88660_A0r */
  68294         soc_block_list[56],
  68295         soc_portreg,
  68296         1,
  68297         0,
  68298         0x61300,
  68299         0,
  68300         0,
  68301         3,
  68302         soc_XLP_XMAC_TX_LLFC_MSG_FIELDS_BCM88660_A0r_fields,
  68303         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  68304         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  68305         -1,
  68306         -1,
  68307     },
  68308 #endif /* chips */
  68309 
  68310 #if defined(BCM_88650_A0)
  68311     { /* SOC_REG_INT_XLP_XMAC_TX_MAC_SAr */
  68312         soc_block_list[56],
  68313         soc_portreg,
  68314         1,
  68315         0,
  68316         0x60500,
  68317         SOC_REG_FLAG_64_BITS,
  68318         0,
  68319         3,
  68320         soc_XLP_XMAC_TX_MAC_SAr_fields,
  68321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68322         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  68323         -1,
  68324         -1,
  68325     },
  68326 #endif /* chips */
  68327 
  68328 #if defined(BCM_88650_B0)
  68329     { /* SOC_REG_INT_XLP_XMAC_TX_MAC_SA_BCM88650_B0r */
  68330         soc_block_list[56],
  68331         soc_portreg,
  68332         1,
  68333         0,
  68334         0x60500,
  68335         SOC_REG_FLAG_64_BITS,
  68336         0,
  68337         3,
  68338         soc_XLP_XMAC_TX_MAC_SA_BCM88650_B0r_fields,
  68339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68340         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  68341         -1,
  68342         -1,
  68343     },
  68344 #endif /* chips */
  68345 
  68346 #if defined(BCM_88660_A0)
  68347     { /* SOC_REG_INT_XLP_XMAC_TX_MAC_SA_BCM88660_A0r */
  68348         soc_block_list[56],
  68349         soc_portreg,
  68350         1,
  68351         0,
  68352         0x60500,
  68353         SOC_REG_FLAG_64_BITS,
  68354         0,
  68355         3,
  68356         soc_XLP_XMAC_TX_MAC_SA_BCM88660_A0r_fields,
  68357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68358         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  68359         -1,
  68360         -1,
  68361     },
  68362 #endif /* chips */
  68363 
  68364 #if defined(BCM_88650_A0)
  68365     { /* SOC_REG_INT_XLP_XMAC_TX_TIMESTAMP_FIFO_DATAr */
  68366         soc_block_list[56],
  68367         soc_portreg,
  68368         1,
  68369         0,
  68370         0x61600,
  68371         SOC_REG_FLAG_64_BITS |
  68372                           SOC_REG_FLAG_RO,
  68373         0,
  68374         3,
  68375         soc_XLP_XMAC_TX_TIMESTAMP_FIFO_DATAr_fields,
  68376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68377         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  68378         -1,
  68379         -1,
  68380     },
  68381 #endif /* chips */
  68382 
  68383 #if defined(BCM_88650_B0)
  68384     { /* SOC_REG_INT_XLP_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM88650_B0r */
  68385         soc_block_list[56],
  68386         soc_portreg,
  68387         1,
  68388         0,
  68389         0x61600,
  68390         SOC_REG_FLAG_64_BITS |
  68391                           SOC_REG_FLAG_RO,
  68392         0,
  68393         3,
  68394         soc_XLP_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM88650_B0r_fields,
  68395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68396         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  68397         -1,
  68398         -1,
  68399     },
  68400 #endif /* chips */
  68401 
  68402 #if defined(BCM_88660_A0)
  68403     { /* SOC_REG_INT_XLP_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM88660_A0r */
  68404         soc_block_list[56],
  68405         soc_portreg,
  68406         1,
  68407         0,
  68408         0x61600,
  68409         SOC_REG_FLAG_64_BITS |
  68410                           SOC_REG_FLAG_RO,
  68411         0,
  68412         3,
  68413         soc_XLP_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM88660_A0r_fields,
  68414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68415         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  68416         -1,
  68417         -1,
  68418     },
  68419 #endif /* chips */
  68420 
  68421 #if defined(BCM_88650_A0)
  68422     { /* SOC_REG_INT_XLP_XMAC_TX_TIMESTAMP_FIFO_STATUSr */
  68423         soc_block_list[56],
  68424         soc_portreg,
  68425         1,
  68426         0,
  68427         0x61700,
  68428         SOC_REG_FLAG_RO,
  68429         0,
  68430         1,
  68431         soc_XLP_XMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  68432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68433         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  68434         -1,
  68435         -1,
  68436     },
  68437 #endif /* chips */
  68438 
  68439 #if defined(BCM_88650_B0)
  68440     { /* SOC_REG_INT_XLP_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88650_B0r */
  68441         soc_block_list[56],
  68442         soc_portreg,
  68443         1,
  68444         0,
  68445         0x61700,
  68446         SOC_REG_FLAG_RO,
  68447         0,
  68448         1,
  68449         soc_XLP_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88650_B0r_fields,
  68450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68451         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  68452         -1,
  68453         -1,
  68454     },
  68455 #endif /* chips */
  68456 
  68457 #if defined(BCM_88660_A0)
  68458     { /* SOC_REG_INT_XLP_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88660_A0r */
  68459         soc_block_list[56],
  68460         soc_portreg,
  68461         1,
  68462         0,
  68463         0x61700,
  68464         SOC_REG_FLAG_RO,
  68465         0,
  68466         1,
  68467         soc_XLP_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88660_A0r_fields,
  68468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68469         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  68470         -1,
  68471         -1,
  68472     },
  68473 #endif /* chips */
  68474 
  68475 #if defined(BCM_88650_A0)
  68476     { /* SOC_REG_INT_XLP_XMAC_VERSION_IDr */
  68477         soc_block_list[56],
  68478         soc_portreg,
  68479         1,
  68480         0,
  68481         0x62600,
  68482         SOC_REG_FLAG_RO,
  68483         0,
  68484         1,
  68485         soc_XLP_XMAC_VERSION_IDr_fields,
  68486         SOC_RESET_VAL_DEC(0x0000b017, 0x00000000)
  68487         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  68488         -1,
  68489         -1,
  68490     },
  68491 #endif /* chips */
  68492 
  68493 #if defined(BCM_88650_B0)
  68494     { /* SOC_REG_INT_XLP_XMAC_VERSION_ID_BCM88650_B0r */
  68495         soc_block_list[56],
  68496         soc_portreg,
  68497         1,
  68498         0,
  68499         0x62600,
  68500         SOC_REG_FLAG_RO,
  68501         0,
  68502         1,
  68503         soc_XLP_XMAC_VERSION_ID_BCM88650_B0r_fields,
  68504         SOC_RESET_VAL_DEC(0x0000b017, 0x00000000)
  68505         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  68506         -1,
  68507         -1,
  68508     },
  68509 #endif /* chips */
  68510 
  68511 #if defined(BCM_88660_A0)
  68512     { /* SOC_REG_INT_XLP_XMAC_VERSION_ID_BCM88660_A0r */
  68513         soc_block_list[56],
  68514         soc_portreg,
  68515         1,
  68516         0,
  68517         0x62600,
  68518         SOC_REG_FLAG_RO,
  68519         0,
  68520         1,
  68521         soc_XLP_XMAC_VERSION_ID_BCM88660_A0r_fields,
  68522         SOC_RESET_VAL_DEC(0x0000b020, 0x00000000)
  68523         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  68524         -1,
  68525         -1,
  68526     },
  68527 #endif /* chips */
  68528 
  68529 #if defined(BCM_56840_A0)
  68530     { /* SOC_REG_INT_XMAC_CLEAR_FIFO_STATUSr */
  68531         soc_block_list[16],
  68532         soc_portreg,
  68533         1,
  68534         0,
  68535         0x619,
  68536         SOC_REG_FLAG_64_BITS |
  68537                           SOC_REG_FLAG_RO,
  68538         0,
  68539         7,
  68540         soc_XMAC_CLEAR_FIFO_STATUSr_fields,
  68541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68542         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  68543         -1,
  68544         -1,
  68545     },
  68546 #endif /* chips */
  68547 
  68548 #if defined(BCM_56340_A0)
  68549     { /* SOC_REG_INT_XMAC_CLEAR_FIFO_STATUS_BCM56340_A0r */
  68550         soc_block_list[214],
  68551         soc_portreg,
  68552         1,
  68553         0,
  68554         0x61900,
  68555         SOC_REG_FLAG_64_BITS |
  68556                           SOC_REG_FLAG_RO,
  68557         0,
  68558         7,
  68559         soc_XMAC_CLEAR_FIFO_STATUS_BCM56640_A0r_fields,
  68560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68561         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  68562         -1,
  68563         -1,
  68564     },
  68565 #endif /* chips */
  68566 
  68567 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  68568     { /* SOC_REG_INT_XMAC_CLEAR_FIFO_STATUS_BCM56440_A0r */
  68569         soc_block_list[83],
  68570         soc_portreg,
  68571         1,
  68572         0,
  68573         0x619,
  68574         SOC_REG_FLAG_64_BITS |
  68575                           SOC_REG_FLAG_RO,
  68576         0,
  68577         7,
  68578         soc_XMAC_CLEAR_FIFO_STATUSr_fields,
  68579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68580         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  68581         -1,
  68582         -1,
  68583     },
  68584 #endif /* chips */
  68585 
  68586 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  68587     defined(BCM_56450_B1)
  68588     { /* SOC_REG_INT_XMAC_CLEAR_FIFO_STATUS_BCM56450_A0r */
  68589         soc_block_list[83],
  68590         soc_portreg,
  68591         1,
  68592         0,
  68593         0x41900,
  68594         SOC_REG_FLAG_64_BITS |
  68595                           SOC_REG_FLAG_RO,
  68596         0,
  68597         7,
  68598         soc_XMAC_CLEAR_FIFO_STATUS_BCM56640_A0r_fields,
  68599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68600         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  68601         -1,
  68602         -1,
  68603     },
  68604 #endif /* chips */
  68605 
  68606 #if defined(BCM_56640_A0)
  68607     { /* SOC_REG_INT_XMAC_CLEAR_FIFO_STATUS_BCM56640_A0r */
  68608         soc_block_list[212],
  68609         soc_portreg,
  68610         1,
  68611         0,
  68612         0x61900,
  68613         SOC_REG_FLAG_64_BITS |
  68614                           SOC_REG_FLAG_RO,
  68615         0,
  68616         7,
  68617         soc_XMAC_CLEAR_FIFO_STATUS_BCM56640_A0r_fields,
  68618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68619         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  68620         -1,
  68621         -1,
  68622     },
  68623 #endif /* chips */
  68624 
  68625 #if defined(BCM_56840_B0)
  68626     { /* SOC_REG_INT_XMAC_CLEAR_FIFO_STATUS_BCM56840_B0r */
  68627         soc_block_list[16],
  68628         soc_portreg,
  68629         1,
  68630         0,
  68631         0x619,
  68632         SOC_REG_FLAG_64_BITS |
  68633                           SOC_REG_FLAG_RO,
  68634         0,
  68635         7,
  68636         soc_XMAC_CLEAR_FIFO_STATUSr_fields,
  68637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68638         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  68639         -1,
  68640         -1,
  68641     },
  68642 #endif /* chips */
  68643 
  68644 #if defined(BCM_88732_A0)
  68645     { /* SOC_REG_INT_XMAC_CLEAR_FIFO_STATUS_BCM88732_A0r */
  68646         soc_block_list[16],
  68647         soc_portreg,
  68648         1,
  68649         0,
  68650         0x619,
  68651         SOC_REG_FLAG_64_BITS |
  68652                           SOC_REG_FLAG_RO,
  68653         0,
  68654         7,
  68655         soc_XMAC_CLEAR_FIFO_STATUSr_fields,
  68656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68657         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  68658         -1,
  68659         -1,
  68660     },
  68661 #endif /* chips */
  68662 
  68663 #if defined(BCM_56840_A0)
  68664     { /* SOC_REG_INT_XMAC_CLEAR_RX_LSS_STATUSr */
  68665         soc_block_list[16],
  68666         soc_portreg,
  68667         1,
  68668         0,
  68669         0x60c,
  68670         SOC_REG_FLAG_64_BITS,
  68671         0,
  68672         2,
  68673         soc_XMAC_CLEAR_RX_LSS_STATUSr_fields,
  68674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68675         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  68676         -1,
  68677         -1,
  68678     },
  68679 #endif /* chips */
  68680 
  68681 #if defined(BCM_56340_A0)
  68682     { /* SOC_REG_INT_XMAC_CLEAR_RX_LSS_STATUS_BCM56340_A0r */
  68683         soc_block_list[214],
  68684         soc_portreg,
  68685         1,
  68686         0,
  68687         0x60c00,
  68688         SOC_REG_FLAG_64_BITS,
  68689         0,
  68690         3,
  68691         soc_XMAC_CLEAR_RX_LSS_STATUS_BCM56640_A0r_fields,
  68692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68693         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  68694         -1,
  68695         -1,
  68696     },
  68697 #endif /* chips */
  68698 
  68699 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  68700     { /* SOC_REG_INT_XMAC_CLEAR_RX_LSS_STATUS_BCM56440_A0r */
  68701         soc_block_list[83],
  68702         soc_portreg,
  68703         1,
  68704         0,
  68705         0x60c,
  68706         SOC_REG_FLAG_64_BITS,
  68707         0,
  68708         2,
  68709         soc_XMAC_CLEAR_RX_LSS_STATUSr_fields,
  68710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68711         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  68712         -1,
  68713         -1,
  68714     },
  68715 #endif /* chips */
  68716 
  68717 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  68718     defined(BCM_56450_B1)
  68719     { /* SOC_REG_INT_XMAC_CLEAR_RX_LSS_STATUS_BCM56450_A0r */
  68720         soc_block_list[83],
  68721         soc_portreg,
  68722         1,
  68723         0,
  68724         0x40c00,
  68725         SOC_REG_FLAG_64_BITS,
  68726         0,
  68727         3,
  68728         soc_XMAC_CLEAR_RX_LSS_STATUS_BCM56640_A0r_fields,
  68729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68730         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  68731         -1,
  68732         -1,
  68733     },
  68734 #endif /* chips */
  68735 
  68736 #if defined(BCM_56640_A0)
  68737     { /* SOC_REG_INT_XMAC_CLEAR_RX_LSS_STATUS_BCM56640_A0r */
  68738         soc_block_list[212],
  68739         soc_portreg,
  68740         1,
  68741         0,
  68742         0x60c00,
  68743         SOC_REG_FLAG_64_BITS,
  68744         0,
  68745         3,
  68746         soc_XMAC_CLEAR_RX_LSS_STATUS_BCM56640_A0r_fields,
  68747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68748         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  68749         -1,
  68750         -1,
  68751     },
  68752 #endif /* chips */
  68753 
  68754 #if defined(BCM_56840_B0)
  68755     { /* SOC_REG_INT_XMAC_CLEAR_RX_LSS_STATUS_BCM56840_B0r */
  68756         soc_block_list[16],
  68757         soc_portreg,
  68758         1,
  68759         0,
  68760         0x60c,
  68761         SOC_REG_FLAG_64_BITS,
  68762         0,
  68763         2,
  68764         soc_XMAC_CLEAR_RX_LSS_STATUSr_fields,
  68765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68766         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  68767         -1,
  68768         -1,
  68769     },
  68770 #endif /* chips */
  68771 
  68772 #if defined(BCM_88732_A0)
  68773     { /* SOC_REG_INT_XMAC_CLEAR_RX_LSS_STATUS_BCM88732_A0r */
  68774         soc_block_list[16],
  68775         soc_portreg,
  68776         1,
  68777         0,
  68778         0x60c,
  68779         SOC_REG_FLAG_64_BITS,
  68780         0,
  68781         2,
  68782         soc_XMAC_CLEAR_RX_LSS_STATUSr_fields,
  68783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68784         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  68785         -1,
  68786         -1,
  68787     },
  68788 #endif /* chips */
  68789 
  68790 #if defined(BCM_56840_A0)
  68791     { /* SOC_REG_INT_XMAC_CTRLr */
  68792         soc_block_list[16],
  68793         soc_portreg,
  68794         1,
  68795         0,
  68796         0x600,
  68797         SOC_REG_FLAG_64_BITS,
  68798         0,
  68799         11,
  68800         soc_XMAC_CTRLr_fields,
  68801         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  68802         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  68803         -1,
  68804         -1,
  68805     },
  68806 #endif /* chips */
  68807 
  68808 #if defined(BCM_56340_A0)
  68809     { /* SOC_REG_INT_XMAC_CTRL_BCM56340_A0r */
  68810         soc_block_list[214],
  68811         soc_portreg,
  68812         1,
  68813         0,
  68814         0x60000,
  68815         SOC_REG_FLAG_64_BITS,
  68816         0,
  68817         14,
  68818         soc_CMAC_CTRLr_fields,
  68819         SOC_RESET_VAL_DEC(0x00001040, 0x00000000)
  68820         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  68821         -1,
  68822         -1,
  68823     },
  68824 #endif /* chips */
  68825 
  68826 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  68827     { /* SOC_REG_INT_XMAC_CTRL_BCM56440_A0r */
  68828         soc_block_list[83],
  68829         soc_portreg,
  68830         1,
  68831         0,
  68832         0x600,
  68833         SOC_REG_FLAG_64_BITS,
  68834         0,
  68835         12,
  68836         soc_XMAC_CTRL_BCM56840_B0r_fields,
  68837         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  68838         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  68839         -1,
  68840         -1,
  68841     },
  68842 #endif /* chips */
  68843 
  68844 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  68845     defined(BCM_56450_B1)
  68846     { /* SOC_REG_INT_XMAC_CTRL_BCM56450_A0r */
  68847         soc_block_list[83],
  68848         soc_portreg,
  68849         1,
  68850         0,
  68851         0x40000,
  68852         SOC_REG_FLAG_64_BITS,
  68853         0,
  68854         14,
  68855         soc_CMAC_CTRLr_fields,
  68856         SOC_RESET_VAL_DEC(0x00001040, 0x00000000)
  68857         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  68858         -1,
  68859         -1,
  68860     },
  68861 #endif /* chips */
  68862 
  68863 #if defined(BCM_56640_A0)
  68864     { /* SOC_REG_INT_XMAC_CTRL_BCM56640_A0r */
  68865         soc_block_list[212],
  68866         soc_portreg,
  68867         1,
  68868         0,
  68869         0x60000,
  68870         SOC_REG_FLAG_64_BITS,
  68871         0,
  68872         14,
  68873         soc_CMAC_CTRLr_fields,
  68874         SOC_RESET_VAL_DEC(0x00001040, 0x00000000)
  68875         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  68876         -1,
  68877         -1,
  68878     },
  68879 #endif /* chips */
  68880 
  68881 #if defined(BCM_56840_B0)
  68882     { /* SOC_REG_INT_XMAC_CTRL_BCM56840_B0r */
  68883         soc_block_list[16],
  68884         soc_portreg,
  68885         1,
  68886         0,
  68887         0x600,
  68888         SOC_REG_FLAG_64_BITS,
  68889         0,
  68890         12,
  68891         soc_XMAC_CTRL_BCM56840_B0r_fields,
  68892         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  68893         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  68894         -1,
  68895         -1,
  68896     },
  68897 #endif /* chips */
  68898 
  68899 #if defined(BCM_88732_A0)
  68900     { /* SOC_REG_INT_XMAC_CTRL_BCM88732_A0r */
  68901         soc_block_list[16],
  68902         soc_portreg,
  68903         1,
  68904         0,
  68905         0x600,
  68906         SOC_REG_FLAG_64_BITS,
  68907         0,
  68908         11,
  68909         soc_XMAC_CTRLr_fields,
  68910         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  68911         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  68912         -1,
  68913         -1,
  68914     },
  68915 #endif /* chips */
  68916 
  68917 #if defined(BCM_56640_A0)
  68918     { /* SOC_REG_INT_XMAC_EEE_1_SEC_LINK_STATUS_TIMERr */
  68919         soc_block_list[212],
  68920         soc_portreg,
  68921         1,
  68922         0,
  68923         0x61d00,
  68924         SOC_REG_FLAG_64_BITS,
  68925         0,
  68926         1,
  68927         soc_CMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  68928         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  68929         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68930         -1,
  68931         -1,
  68932     },
  68933 #endif /* chips */
  68934 
  68935 #if defined(BCM_56340_A0)
  68936     { /* SOC_REG_INT_XMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56340_A0r */
  68937         soc_block_list[214],
  68938         soc_portreg,
  68939         1,
  68940         0,
  68941         0x61d00,
  68942         SOC_REG_FLAG_64_BITS,
  68943         0,
  68944         1,
  68945         soc_CMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  68946         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  68947         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68948         -1,
  68949         -1,
  68950     },
  68951 #endif /* chips */
  68952 
  68953 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  68954     defined(BCM_56450_B1)
  68955     { /* SOC_REG_INT_XMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM56450_A0r */
  68956         soc_block_list[83],
  68957         soc_portreg,
  68958         1,
  68959         0,
  68960         0x41d00,
  68961         SOC_REG_FLAG_64_BITS,
  68962         0,
  68963         1,
  68964         soc_CMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields,
  68965         SOC_RESET_VAL_DEC(0x000f4240, 0x00000000)
  68966         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  68967         -1,
  68968         -1,
  68969     },
  68970 #endif /* chips */
  68971 
  68972 #if defined(BCM_56840_A0)
  68973     { /* SOC_REG_INT_XMAC_EEE_CTRLr */
  68974         soc_block_list[16],
  68975         soc_portreg,
  68976         1,
  68977         0,
  68978         0x61b,
  68979         SOC_REG_FLAG_64_BITS,
  68980         0,
  68981         4,
  68982         soc_XMAC_EEE_CTRLr_fields,
  68983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68984         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  68985         -1,
  68986         -1,
  68987     },
  68988 #endif /* chips */
  68989 
  68990 #if defined(BCM_56340_A0)
  68991     { /* SOC_REG_INT_XMAC_EEE_CTRL_BCM56340_A0r */
  68992         soc_block_list[214],
  68993         soc_portreg,
  68994         1,
  68995         0,
  68996         0x61b00,
  68997         SOC_REG_FLAG_64_BITS,
  68998         0,
  68999         4,
  69000         soc_CMAC_EEE_CTRLr_fields,
  69001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69002         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69003         -1,
  69004         -1,
  69005     },
  69006 #endif /* chips */
  69007 
  69008 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69009     { /* SOC_REG_INT_XMAC_EEE_CTRL_BCM56440_A0r */
  69010         soc_block_list[83],
  69011         soc_portreg,
  69012         1,
  69013         0,
  69014         0x61b,
  69015         SOC_REG_FLAG_64_BITS,
  69016         0,
  69017         4,
  69018         soc_XMAC_EEE_CTRLr_fields,
  69019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69020         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69021         -1,
  69022         -1,
  69023     },
  69024 #endif /* chips */
  69025 
  69026 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69027     defined(BCM_56450_B1)
  69028     { /* SOC_REG_INT_XMAC_EEE_CTRL_BCM56450_A0r */
  69029         soc_block_list[83],
  69030         soc_portreg,
  69031         1,
  69032         0,
  69033         0x41b00,
  69034         SOC_REG_FLAG_64_BITS,
  69035         0,
  69036         4,
  69037         soc_CMAC_EEE_CTRLr_fields,
  69038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69039         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69040         -1,
  69041         -1,
  69042     },
  69043 #endif /* chips */
  69044 
  69045 #if defined(BCM_56640_A0)
  69046     { /* SOC_REG_INT_XMAC_EEE_CTRL_BCM56640_A0r */
  69047         soc_block_list[212],
  69048         soc_portreg,
  69049         1,
  69050         0,
  69051         0x61b00,
  69052         SOC_REG_FLAG_64_BITS,
  69053         0,
  69054         4,
  69055         soc_CMAC_EEE_CTRLr_fields,
  69056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69057         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69058         -1,
  69059         -1,
  69060     },
  69061 #endif /* chips */
  69062 
  69063 #if defined(BCM_56840_B0)
  69064     { /* SOC_REG_INT_XMAC_EEE_CTRL_BCM56840_B0r */
  69065         soc_block_list[16],
  69066         soc_portreg,
  69067         1,
  69068         0,
  69069         0x61b,
  69070         SOC_REG_FLAG_64_BITS,
  69071         0,
  69072         4,
  69073         soc_XMAC_EEE_CTRLr_fields,
  69074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69075         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69076         -1,
  69077         -1,
  69078     },
  69079 #endif /* chips */
  69080 
  69081 #if defined(BCM_88732_A0)
  69082     { /* SOC_REG_INT_XMAC_EEE_CTRL_BCM88732_A0r */
  69083         soc_block_list[16],
  69084         soc_portreg,
  69085         1,
  69086         0,
  69087         0x61b,
  69088         SOC_REG_FLAG_64_BITS,
  69089         0,
  69090         4,
  69091         soc_XMAC_EEE_CTRLr_fields,
  69092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69093         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69094         -1,
  69095         -1,
  69096     },
  69097 #endif /* chips */
  69098 
  69099 #if defined(BCM_56840_A0)
  69100     { /* SOC_REG_INT_XMAC_EEE_TIMERSr */
  69101         soc_block_list[16],
  69102         soc_portreg,
  69103         1,
  69104         0,
  69105         0x61c,
  69106         SOC_REG_FLAG_64_BITS,
  69107         0,
  69108         4,
  69109         soc_XMAC_EEE_TIMERSr_fields,
  69110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69111         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  69112         -1,
  69113         -1,
  69114     },
  69115 #endif /* chips */
  69116 
  69117 #if defined(BCM_56340_A0)
  69118     { /* SOC_REG_INT_XMAC_EEE_TIMERS_BCM56340_A0r */
  69119         soc_block_list[214],
  69120         soc_portreg,
  69121         1,
  69122         0,
  69123         0x61c00,
  69124         SOC_REG_FLAG_64_BITS,
  69125         0,
  69126         5,
  69127         soc_XMAC_EEE_TIMERS_BCM56640_A0r_fields,
  69128         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  69129         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  69130         -1,
  69131         -1,
  69132     },
  69133 #endif /* chips */
  69134 
  69135 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69136     { /* SOC_REG_INT_XMAC_EEE_TIMERS_BCM56440_A0r */
  69137         soc_block_list[83],
  69138         soc_portreg,
  69139         1,
  69140         0,
  69141         0x61c,
  69142         SOC_REG_FLAG_64_BITS,
  69143         0,
  69144         5,
  69145         soc_XMAC_EEE_TIMERS_BCM56440_A0r_fields,
  69146         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  69147         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  69148         -1,
  69149         -1,
  69150     },
  69151 #endif /* chips */
  69152 
  69153 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69154     defined(BCM_56450_B1)
  69155     { /* SOC_REG_INT_XMAC_EEE_TIMERS_BCM56450_A0r */
  69156         soc_block_list[83],
  69157         soc_portreg,
  69158         1,
  69159         0,
  69160         0x41c00,
  69161         SOC_REG_FLAG_64_BITS,
  69162         0,
  69163         5,
  69164         soc_XMAC_EEE_TIMERS_BCM56640_A0r_fields,
  69165         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  69166         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  69167         -1,
  69168         -1,
  69169     },
  69170 #endif /* chips */
  69171 
  69172 #if defined(BCM_56640_A0)
  69173     { /* SOC_REG_INT_XMAC_EEE_TIMERS_BCM56640_A0r */
  69174         soc_block_list[212],
  69175         soc_portreg,
  69176         1,
  69177         0,
  69178         0x61c00,
  69179         SOC_REG_FLAG_64_BITS,
  69180         0,
  69181         5,
  69182         soc_XMAC_EEE_TIMERS_BCM56640_A0r_fields,
  69183         SOC_RESET_VAL_DEC(0x00000000, 0x01380000)
  69184         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  69185         -1,
  69186         -1,
  69187     },
  69188 #endif /* chips */
  69189 
  69190 #if defined(BCM_56840_B0)
  69191     { /* SOC_REG_INT_XMAC_EEE_TIMERS_BCM56840_B0r */
  69192         soc_block_list[16],
  69193         soc_portreg,
  69194         1,
  69195         0,
  69196         0x61c,
  69197         SOC_REG_FLAG_64_BITS,
  69198         0,
  69199         4,
  69200         soc_XMAC_EEE_TIMERSr_fields,
  69201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69202         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  69203         -1,
  69204         -1,
  69205     },
  69206 #endif /* chips */
  69207 
  69208 #if defined(BCM_88732_A0)
  69209     { /* SOC_REG_INT_XMAC_EEE_TIMERS_BCM88732_A0r */
  69210         soc_block_list[16],
  69211         soc_portreg,
  69212         1,
  69213         0,
  69214         0x61c,
  69215         SOC_REG_FLAG_64_BITS,
  69216         0,
  69217         4,
  69218         soc_XMAC_EEE_TIMERSr_fields,
  69219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69220         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  69221         -1,
  69222         -1,
  69223     },
  69224 #endif /* chips */
  69225 
  69226 #if defined(BCM_56840_A0)
  69227     { /* SOC_REG_INT_XMAC_FIFO_STATUSr */
  69228         soc_block_list[16],
  69229         soc_portreg,
  69230         1,
  69231         0,
  69232         0x618,
  69233         SOC_REG_FLAG_64_BITS |
  69234                           SOC_REG_FLAG_RO,
  69235         0,
  69236         7,
  69237         soc_XMAC_FIFO_STATUSr_fields,
  69238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69239         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  69240         -1,
  69241         -1,
  69242     },
  69243 #endif /* chips */
  69244 
  69245 #if defined(BCM_56340_A0)
  69246     { /* SOC_REG_INT_XMAC_FIFO_STATUS_BCM56340_A0r */
  69247         soc_block_list[214],
  69248         soc_portreg,
  69249         1,
  69250         0,
  69251         0x61800,
  69252         SOC_REG_FLAG_64_BITS |
  69253                           SOC_REG_FLAG_RO,
  69254         0,
  69255         8,
  69256         soc_XMAC_FIFO_STATUS_BCM56640_A0r_fields,
  69257         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  69258         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69259         -1,
  69260         -1,
  69261     },
  69262 #endif /* chips */
  69263 
  69264 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69265     { /* SOC_REG_INT_XMAC_FIFO_STATUS_BCM56440_A0r */
  69266         soc_block_list[83],
  69267         soc_portreg,
  69268         1,
  69269         0,
  69270         0x618,
  69271         SOC_REG_FLAG_64_BITS |
  69272                           SOC_REG_FLAG_RO,
  69273         0,
  69274         7,
  69275         soc_XMAC_FIFO_STATUSr_fields,
  69276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69277         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  69278         -1,
  69279         -1,
  69280     },
  69281 #endif /* chips */
  69282 
  69283 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69284     defined(BCM_56450_B1)
  69285     { /* SOC_REG_INT_XMAC_FIFO_STATUS_BCM56450_A0r */
  69286         soc_block_list[83],
  69287         soc_portreg,
  69288         1,
  69289         0,
  69290         0x41800,
  69291         SOC_REG_FLAG_64_BITS |
  69292                           SOC_REG_FLAG_RO,
  69293         0,
  69294         8,
  69295         soc_XMAC_FIFO_STATUS_BCM56640_A0r_fields,
  69296         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  69297         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69298         -1,
  69299         -1,
  69300     },
  69301 #endif /* chips */
  69302 
  69303 #if defined(BCM_56640_A0)
  69304     { /* SOC_REG_INT_XMAC_FIFO_STATUS_BCM56640_A0r */
  69305         soc_block_list[212],
  69306         soc_portreg,
  69307         1,
  69308         0,
  69309         0x61800,
  69310         SOC_REG_FLAG_64_BITS |
  69311                           SOC_REG_FLAG_RO,
  69312         0,
  69313         8,
  69314         soc_XMAC_FIFO_STATUS_BCM56640_A0r_fields,
  69315         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  69316         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  69317         -1,
  69318         -1,
  69319     },
  69320 #endif /* chips */
  69321 
  69322 #if defined(BCM_56840_B0)
  69323     { /* SOC_REG_INT_XMAC_FIFO_STATUS_BCM56840_B0r */
  69324         soc_block_list[16],
  69325         soc_portreg,
  69326         1,
  69327         0,
  69328         0x618,
  69329         SOC_REG_FLAG_64_BITS |
  69330                           SOC_REG_FLAG_RO,
  69331         0,
  69332         7,
  69333         soc_XMAC_FIFO_STATUSr_fields,
  69334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69335         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  69336         -1,
  69337         -1,
  69338     },
  69339 #endif /* chips */
  69340 
  69341 #if defined(BCM_88732_A0)
  69342     { /* SOC_REG_INT_XMAC_FIFO_STATUS_BCM88732_A0r */
  69343         soc_block_list[16],
  69344         soc_portreg,
  69345         1,
  69346         0,
  69347         0x618,
  69348         SOC_REG_FLAG_64_BITS |
  69349                           SOC_REG_FLAG_RO,
  69350         0,
  69351         7,
  69352         soc_XMAC_FIFO_STATUSr_fields,
  69353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69354         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  69355         -1,
  69356         -1,
  69357     },
  69358 #endif /* chips */
  69359 
  69360 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69361     { /* SOC_REG_INT_XMAC_GMII_EEE_CTRLr */
  69362         soc_block_list[83],
  69363         soc_portreg,
  69364         1,
  69365         0,
  69366         0x622,
  69367         SOC_REG_FLAG_64_BITS,
  69368         0,
  69369         3,
  69370         soc_XMAC_GMII_EEE_CTRLr_fields,
  69371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69372         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  69373         -1,
  69374         -1,
  69375     },
  69376 #endif /* chips */
  69377 
  69378 #if defined(BCM_56340_A0)
  69379     { /* SOC_REG_INT_XMAC_GMII_EEE_CTRL_BCM56340_A0r */
  69380         soc_block_list[214],
  69381         soc_portreg,
  69382         1,
  69383         0,
  69384         0x62300,
  69385         SOC_REG_FLAG_64_BITS,
  69386         0,
  69387         3,
  69388         soc_XMAC_GMII_EEE_CTRL_BCM56640_A0r_fields,
  69389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69390         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  69391         -1,
  69392         -1,
  69393     },
  69394 #endif /* chips */
  69395 
  69396 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69397     defined(BCM_56450_B1)
  69398     { /* SOC_REG_INT_XMAC_GMII_EEE_CTRL_BCM56450_A0r */
  69399         soc_block_list[83],
  69400         soc_portreg,
  69401         1,
  69402         0,
  69403         0x42300,
  69404         SOC_REG_FLAG_64_BITS,
  69405         0,
  69406         3,
  69407         soc_XMAC_GMII_EEE_CTRL_BCM56640_A0r_fields,
  69408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69409         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  69410         -1,
  69411         -1,
  69412     },
  69413 #endif /* chips */
  69414 
  69415 #if defined(BCM_56640_A0)
  69416     { /* SOC_REG_INT_XMAC_GMII_EEE_CTRL_BCM56640_A0r */
  69417         soc_block_list[212],
  69418         soc_portreg,
  69419         1,
  69420         0,
  69421         0x62300,
  69422         SOC_REG_FLAG_64_BITS,
  69423         0,
  69424         3,
  69425         soc_XMAC_GMII_EEE_CTRL_BCM56640_A0r_fields,
  69426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69427         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  69428         -1,
  69429         -1,
  69430     },
  69431 #endif /* chips */
  69432 
  69433 #if defined(BCM_56840_A0)
  69434     { /* SOC_REG_INT_XMAC_HCFC_CTRLr */
  69435         soc_block_list[16],
  69436         soc_portreg,
  69437         1,
  69438         0,
  69439         0x615,
  69440         SOC_REG_FLAG_64_BITS,
  69441         0,
  69442         7,
  69443         soc_XMAC_HCFC_CTRLr_fields,
  69444         SOC_RESET_VAL_DEC(0x00030b80, 0x00000000)
  69445         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  69446         -1,
  69447         -1,
  69448     },
  69449 #endif /* chips */
  69450 
  69451 #if defined(BCM_56340_A0)
  69452     { /* SOC_REG_INT_XMAC_HCFC_CTRL_BCM56340_A0r */
  69453         soc_block_list[214],
  69454         soc_portreg,
  69455         1,
  69456         0,
  69457         0x61500,
  69458         SOC_REG_FLAG_64_BITS,
  69459         0,
  69460         7,
  69461         soc_CMAC_HCFC_CTRLr_fields,
  69462         SOC_RESET_VAL_DEC(0x00030b80, 0x00000000)
  69463         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  69464         -1,
  69465         -1,
  69466     },
  69467 #endif /* chips */
  69468 
  69469 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69470     { /* SOC_REG_INT_XMAC_HCFC_CTRL_BCM56440_A0r */
  69471         soc_block_list[83],
  69472         soc_portreg,
  69473         1,
  69474         0,
  69475         0x615,
  69476         SOC_REG_FLAG_64_BITS,
  69477         0,
  69478         7,
  69479         soc_XMAC_HCFC_CTRLr_fields,
  69480         SOC_RESET_VAL_DEC(0x00030b80, 0x00000000)
  69481         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  69482         -1,
  69483         -1,
  69484     },
  69485 #endif /* chips */
  69486 
  69487 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69488     defined(BCM_56450_B1)
  69489     { /* SOC_REG_INT_XMAC_HCFC_CTRL_BCM56450_A0r */
  69490         soc_block_list[83],
  69491         soc_portreg,
  69492         1,
  69493         0,
  69494         0x41500,
  69495         SOC_REG_FLAG_64_BITS,
  69496         0,
  69497         7,
  69498         soc_CMAC_HCFC_CTRLr_fields,
  69499         SOC_RESET_VAL_DEC(0x00030b80, 0x00000000)
  69500         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  69501         -1,
  69502         -1,
  69503     },
  69504 #endif /* chips */
  69505 
  69506 #if defined(BCM_56640_A0)
  69507     { /* SOC_REG_INT_XMAC_HCFC_CTRL_BCM56640_A0r */
  69508         soc_block_list[212],
  69509         soc_portreg,
  69510         1,
  69511         0,
  69512         0x61500,
  69513         SOC_REG_FLAG_64_BITS,
  69514         0,
  69515         7,
  69516         soc_CMAC_HCFC_CTRLr_fields,
  69517         SOC_RESET_VAL_DEC(0x00030b80, 0x00000000)
  69518         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  69519         -1,
  69520         -1,
  69521     },
  69522 #endif /* chips */
  69523 
  69524 #if defined(BCM_56840_B0)
  69525     { /* SOC_REG_INT_XMAC_HCFC_CTRL_BCM56840_B0r */
  69526         soc_block_list[16],
  69527         soc_portreg,
  69528         1,
  69529         0,
  69530         0x615,
  69531         SOC_REG_FLAG_64_BITS,
  69532         0,
  69533         7,
  69534         soc_XMAC_HCFC_CTRLr_fields,
  69535         SOC_RESET_VAL_DEC(0x00030b80, 0x00000000)
  69536         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  69537         -1,
  69538         -1,
  69539     },
  69540 #endif /* chips */
  69541 
  69542 #if defined(BCM_88732_A0)
  69543     { /* SOC_REG_INT_XMAC_HCFC_CTRL_BCM88732_A0r */
  69544         soc_block_list[16],
  69545         soc_portreg,
  69546         1,
  69547         0,
  69548         0x615,
  69549         SOC_REG_FLAG_64_BITS,
  69550         0,
  69551         7,
  69552         soc_XMAC_HCFC_CTRLr_fields,
  69553         SOC_RESET_VAL_DEC(0x00030b80, 0x00000000)
  69554         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  69555         -1,
  69556         -1,
  69557     },
  69558 #endif /* chips */
  69559 
  69560 #if defined(BCM_56840_A0)
  69561     { /* SOC_REG_INT_XMAC_LLFC_CTRLr */
  69562         soc_block_list[16],
  69563         soc_portreg,
  69564         1,
  69565         0,
  69566         0x612,
  69567         SOC_REG_FLAG_64_BITS,
  69568         0,
  69569         7,
  69570         soc_XMAC_LLFC_CTRLr_fields,
  69571         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  69572         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  69573         -1,
  69574         -1,
  69575     },
  69576 #endif /* chips */
  69577 
  69578 #if defined(BCM_56340_A0)
  69579     { /* SOC_REG_INT_XMAC_LLFC_CTRL_BCM56340_A0r */
  69580         soc_block_list[214],
  69581         soc_portreg,
  69582         1,
  69583         0,
  69584         0x61200,
  69585         SOC_REG_FLAG_64_BITS,
  69586         0,
  69587         7,
  69588         soc_CMAC_LLFC_CTRLr_fields,
  69589         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  69590         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  69591         -1,
  69592         -1,
  69593     },
  69594 #endif /* chips */
  69595 
  69596 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69597     { /* SOC_REG_INT_XMAC_LLFC_CTRL_BCM56440_A0r */
  69598         soc_block_list[83],
  69599         soc_portreg,
  69600         1,
  69601         0,
  69602         0x612,
  69603         SOC_REG_FLAG_64_BITS,
  69604         0,
  69605         7,
  69606         soc_XMAC_LLFC_CTRLr_fields,
  69607         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  69608         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  69609         -1,
  69610         -1,
  69611     },
  69612 #endif /* chips */
  69613 
  69614 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69615     defined(BCM_56450_B1)
  69616     { /* SOC_REG_INT_XMAC_LLFC_CTRL_BCM56450_A0r */
  69617         soc_block_list[83],
  69618         soc_portreg,
  69619         1,
  69620         0,
  69621         0x41200,
  69622         SOC_REG_FLAG_64_BITS,
  69623         0,
  69624         7,
  69625         soc_CMAC_LLFC_CTRLr_fields,
  69626         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  69627         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  69628         -1,
  69629         -1,
  69630     },
  69631 #endif /* chips */
  69632 
  69633 #if defined(BCM_56640_A0)
  69634     { /* SOC_REG_INT_XMAC_LLFC_CTRL_BCM56640_A0r */
  69635         soc_block_list[212],
  69636         soc_portreg,
  69637         1,
  69638         0,
  69639         0x61200,
  69640         SOC_REG_FLAG_64_BITS,
  69641         0,
  69642         7,
  69643         soc_CMAC_LLFC_CTRLr_fields,
  69644         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  69645         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  69646         -1,
  69647         -1,
  69648     },
  69649 #endif /* chips */
  69650 
  69651 #if defined(BCM_56840_B0)
  69652     { /* SOC_REG_INT_XMAC_LLFC_CTRL_BCM56840_B0r */
  69653         soc_block_list[16],
  69654         soc_portreg,
  69655         1,
  69656         0,
  69657         0x612,
  69658         SOC_REG_FLAG_64_BITS,
  69659         0,
  69660         7,
  69661         soc_XMAC_LLFC_CTRLr_fields,
  69662         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  69663         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  69664         -1,
  69665         -1,
  69666     },
  69667 #endif /* chips */
  69668 
  69669 #if defined(BCM_88732_A0)
  69670     { /* SOC_REG_INT_XMAC_LLFC_CTRL_BCM88732_A0r */
  69671         soc_block_list[16],
  69672         soc_portreg,
  69673         1,
  69674         0,
  69675         0x612,
  69676         SOC_REG_FLAG_64_BITS,
  69677         0,
  69678         7,
  69679         soc_XMAC_LLFC_CTRLr_fields,
  69680         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  69681         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  69682         -1,
  69683         -1,
  69684     },
  69685 #endif /* chips */
  69686 
  69687 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69688     { /* SOC_REG_INT_XMAC_MACSEC_CTRLr */
  69689         soc_block_list[83],
  69690         soc_portreg,
  69691         1,
  69692         0,
  69693         0x624,
  69694         SOC_REG_FLAG_64_BITS,
  69695         0,
  69696         6,
  69697         soc_XMAC_MACSEC_CTRLr_fields,
  69698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69699         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  69700         -1,
  69701         -1,
  69702     },
  69703 #endif /* chips */
  69704 
  69705 #if defined(BCM_56340_A0)
  69706     { /* SOC_REG_INT_XMAC_MACSEC_CTRL_BCM56340_A0r */
  69707         soc_block_list[214],
  69708         soc_portreg,
  69709         1,
  69710         0,
  69711         0x62500,
  69712         SOC_REG_FLAG_64_BITS,
  69713         0,
  69714         6,
  69715         soc_XMAC_MACSEC_CTRL_BCM56640_A0r_fields,
  69716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  69718         -1,
  69719         -1,
  69720     },
  69721 #endif /* chips */
  69722 
  69723 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69724     defined(BCM_56450_B1)
  69725     { /* SOC_REG_INT_XMAC_MACSEC_CTRL_BCM56450_A0r */
  69726         soc_block_list[83],
  69727         soc_portreg,
  69728         1,
  69729         0,
  69730         0x42500,
  69731         SOC_REG_FLAG_64_BITS,
  69732         0,
  69733         6,
  69734         soc_XMAC_MACSEC_CTRL_BCM56640_A0r_fields,
  69735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69736         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  69737         -1,
  69738         -1,
  69739     },
  69740 #endif /* chips */
  69741 
  69742 #if defined(BCM_56640_A0)
  69743     { /* SOC_REG_INT_XMAC_MACSEC_CTRL_BCM56640_A0r */
  69744         soc_block_list[212],
  69745         soc_portreg,
  69746         1,
  69747         0,
  69748         0x62500,
  69749         SOC_REG_FLAG_64_BITS,
  69750         0,
  69751         6,
  69752         soc_XMAC_MACSEC_CTRL_BCM56640_A0r_fields,
  69753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69754         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  69755         -1,
  69756         -1,
  69757     },
  69758 #endif /* chips */
  69759 
  69760 #if defined(BCM_56840_A0)
  69761     { /* SOC_REG_INT_XMAC_MODEr */
  69762         soc_block_list[16],
  69763         soc_portreg,
  69764         1,
  69765         0,
  69766         0x601,
  69767         SOC_REG_FLAG_64_BITS,
  69768         0,
  69769         2,
  69770         soc_XMAC_MODEr_fields,
  69771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69772         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69773         -1,
  69774         -1,
  69775     },
  69776 #endif /* chips */
  69777 
  69778 #if defined(BCM_56340_A0)
  69779     { /* SOC_REG_INT_XMAC_MODE_BCM56340_A0r */
  69780         soc_block_list[214],
  69781         soc_portreg,
  69782         1,
  69783         0,
  69784         0x60100,
  69785         SOC_REG_FLAG_64_BITS,
  69786         0,
  69787         3,
  69788         soc_CMAC_MODEr_fields,
  69789         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  69790         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  69791         -1,
  69792         -1,
  69793     },
  69794 #endif /* chips */
  69795 
  69796 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69797     { /* SOC_REG_INT_XMAC_MODE_BCM56440_A0r */
  69798         soc_block_list[83],
  69799         soc_portreg,
  69800         1,
  69801         0,
  69802         0x601,
  69803         SOC_REG_FLAG_64_BITS,
  69804         0,
  69805         3,
  69806         soc_XMAC_MODE_BCM56440_A0r_fields,
  69807         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  69808         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  69809         -1,
  69810         -1,
  69811     },
  69812 #endif /* chips */
  69813 
  69814 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69815     defined(BCM_56450_B1)
  69816     { /* SOC_REG_INT_XMAC_MODE_BCM56450_A0r */
  69817         soc_block_list[83],
  69818         soc_portreg,
  69819         1,
  69820         0,
  69821         0x40100,
  69822         SOC_REG_FLAG_64_BITS,
  69823         0,
  69824         3,
  69825         soc_CMAC_MODEr_fields,
  69826         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  69827         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  69828         -1,
  69829         -1,
  69830     },
  69831 #endif /* chips */
  69832 
  69833 #if defined(BCM_56640_A0)
  69834     { /* SOC_REG_INT_XMAC_MODE_BCM56640_A0r */
  69835         soc_block_list[212],
  69836         soc_portreg,
  69837         1,
  69838         0,
  69839         0x60100,
  69840         SOC_REG_FLAG_64_BITS,
  69841         0,
  69842         3,
  69843         soc_CMAC_MODEr_fields,
  69844         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  69845         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  69846         -1,
  69847         -1,
  69848     },
  69849 #endif /* chips */
  69850 
  69851 #if defined(BCM_56840_B0)
  69852     { /* SOC_REG_INT_XMAC_MODE_BCM56840_B0r */
  69853         soc_block_list[16],
  69854         soc_portreg,
  69855         1,
  69856         0,
  69857         0x601,
  69858         SOC_REG_FLAG_64_BITS,
  69859         0,
  69860         2,
  69861         soc_XMAC_MODEr_fields,
  69862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69863         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69864         -1,
  69865         -1,
  69866     },
  69867 #endif /* chips */
  69868 
  69869 #if defined(BCM_88732_A0)
  69870     { /* SOC_REG_INT_XMAC_MODE_BCM88732_A0r */
  69871         soc_block_list[16],
  69872         soc_portreg,
  69873         1,
  69874         0,
  69875         0x601,
  69876         SOC_REG_FLAG_64_BITS,
  69877         0,
  69878         2,
  69879         soc_XMAC_MODEr_fields,
  69880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69881         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  69882         -1,
  69883         -1,
  69884     },
  69885 #endif /* chips */
  69886 
  69887 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69888     { /* SOC_REG_INT_XMAC_OSTS_TIMESTAMP_ADJUSTr */
  69889         soc_block_list[83],
  69890         soc_portreg,
  69891         1,
  69892         0,
  69893         0x623,
  69894         SOC_REG_FLAG_64_BITS,
  69895         0,
  69896         7,
  69897         soc_XMAC_OSTS_TIMESTAMP_ADJUSTr_fields,
  69898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69899         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  69900         -1,
  69901         -1,
  69902     },
  69903 #endif /* chips */
  69904 
  69905 #if defined(BCM_56340_A0)
  69906     { /* SOC_REG_INT_XMAC_OSTS_TIMESTAMP_ADJUST_BCM56340_A0r */
  69907         soc_block_list[214],
  69908         soc_portreg,
  69909         1,
  69910         0,
  69911         0x62400,
  69912         SOC_REG_FLAG_64_BITS,
  69913         0,
  69914         8,
  69915         soc_XMAC_OSTS_TIMESTAMP_ADJUST_BCM56640_A0r_fields,
  69916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69917         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  69918         -1,
  69919         -1,
  69920     },
  69921 #endif /* chips */
  69922 
  69923 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  69924     defined(BCM_56450_B1)
  69925     { /* SOC_REG_INT_XMAC_OSTS_TIMESTAMP_ADJUST_BCM56450_A0r */
  69926         soc_block_list[83],
  69927         soc_portreg,
  69928         1,
  69929         0,
  69930         0x42400,
  69931         SOC_REG_FLAG_64_BITS,
  69932         0,
  69933         8,
  69934         soc_XMAC_OSTS_TIMESTAMP_ADJUST_BCM56640_A0r_fields,
  69935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69936         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  69937         -1,
  69938         -1,
  69939     },
  69940 #endif /* chips */
  69941 
  69942 #if defined(BCM_56640_A0)
  69943     { /* SOC_REG_INT_XMAC_OSTS_TIMESTAMP_ADJUST_BCM56640_A0r */
  69944         soc_block_list[212],
  69945         soc_portreg,
  69946         1,
  69947         0,
  69948         0x62400,
  69949         SOC_REG_FLAG_64_BITS,
  69950         0,
  69951         8,
  69952         soc_XMAC_OSTS_TIMESTAMP_ADJUST_BCM56640_A0r_fields,
  69953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69954         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  69955         -1,
  69956         -1,
  69957     },
  69958 #endif /* chips */
  69959 
  69960 #if defined(BCM_56840_A0)
  69961     { /* SOC_REG_INT_XMAC_PAUSE_CTRLr */
  69962         soc_block_list[16],
  69963         soc_portreg,
  69964         1,
  69965         0,
  69966         0x60d,
  69967         SOC_REG_FLAG_64_BITS,
  69968         0,
  69969         5,
  69970         soc_XMAC_PAUSE_CTRLr_fields,
  69971         SOC_RESET_VAL_DEC(0x0001c000, 0x00000000)
  69972         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  69973         -1,
  69974         -1,
  69975     },
  69976 #endif /* chips */
  69977 
  69978 #if defined(BCM_56340_A0)
  69979     { /* SOC_REG_INT_XMAC_PAUSE_CTRL_BCM56340_A0r */
  69980         soc_block_list[214],
  69981         soc_portreg,
  69982         1,
  69983         0,
  69984         0x60d00,
  69985         SOC_REG_FLAG_64_BITS,
  69986         0,
  69987         9,
  69988         soc_XMAC_PAUSE_CTRL_BCM56640_A0r_fields,
  69989         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  69990         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  69991         -1,
  69992         -1,
  69993     },
  69994 #endif /* chips */
  69995 
  69996 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  69997     { /* SOC_REG_INT_XMAC_PAUSE_CTRL_BCM56440_A0r */
  69998         soc_block_list[83],
  69999         soc_portreg,
  70000         1,
  70001         0,
  70002         0x60d,
  70003         SOC_REG_FLAG_64_BITS,
  70004         0,
  70005         6,
  70006         soc_XMAC_PAUSE_CTRL_BCM56440_A0r_fields,
  70007         SOC_RESET_VAL_DEC(0x0011c000, 0x00000000)
  70008         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  70009         -1,
  70010         -1,
  70011     },
  70012 #endif /* chips */
  70013 
  70014 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70015     defined(BCM_56450_B1)
  70016     { /* SOC_REG_INT_XMAC_PAUSE_CTRL_BCM56450_A0r */
  70017         soc_block_list[83],
  70018         soc_portreg,
  70019         1,
  70020         0,
  70021         0x40d00,
  70022         SOC_REG_FLAG_64_BITS,
  70023         0,
  70024         9,
  70025         soc_XMAC_PAUSE_CTRL_BCM56640_A0r_fields,
  70026         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  70027         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  70028         -1,
  70029         -1,
  70030     },
  70031 #endif /* chips */
  70032 
  70033 #if defined(BCM_56640_A0)
  70034     { /* SOC_REG_INT_XMAC_PAUSE_CTRL_BCM56640_A0r */
  70035         soc_block_list[212],
  70036         soc_portreg,
  70037         1,
  70038         0,
  70039         0x60d00,
  70040         SOC_REG_FLAG_64_BITS,
  70041         0,
  70042         9,
  70043         soc_XMAC_PAUSE_CTRL_BCM56640_A0r_fields,
  70044         SOC_RESET_VAL_DEC(0xfff1c000, 0x0000001f)
  70045         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  70046         -1,
  70047         -1,
  70048     },
  70049 #endif /* chips */
  70050 
  70051 #if defined(BCM_56840_B0)
  70052     { /* SOC_REG_INT_XMAC_PAUSE_CTRL_BCM56840_B0r */
  70053         soc_block_list[16],
  70054         soc_portreg,
  70055         1,
  70056         0,
  70057         0x60d,
  70058         SOC_REG_FLAG_64_BITS,
  70059         0,
  70060         5,
  70061         soc_XMAC_PAUSE_CTRLr_fields,
  70062         SOC_RESET_VAL_DEC(0x0001c000, 0x00000000)
  70063         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  70064         -1,
  70065         -1,
  70066     },
  70067 #endif /* chips */
  70068 
  70069 #if defined(BCM_88732_A0)
  70070     { /* SOC_REG_INT_XMAC_PAUSE_CTRL_BCM88732_A0r */
  70071         soc_block_list[16],
  70072         soc_portreg,
  70073         1,
  70074         0,
  70075         0x60d,
  70076         SOC_REG_FLAG_64_BITS,
  70077         0,
  70078         5,
  70079         soc_XMAC_PAUSE_CTRLr_fields,
  70080         SOC_RESET_VAL_DEC(0x0001c000, 0x00000000)
  70081         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  70082         -1,
  70083         -1,
  70084     },
  70085 #endif /* chips */
  70086 
  70087 #if defined(BCM_56840_A0)
  70088     { /* SOC_REG_INT_XMAC_PFC_CTRLr */
  70089         soc_block_list[16],
  70090         soc_portreg,
  70091         1,
  70092         0,
  70093         0x60e,
  70094         SOC_REG_FLAG_64_BITS,
  70095         0,
  70096         8,
  70097         soc_XMAC_PFC_CTRLr_fields,
  70098         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  70099         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  70100         -1,
  70101         -1,
  70102     },
  70103 #endif /* chips */
  70104 
  70105 #if defined(BCM_56340_A0)
  70106     { /* SOC_REG_INT_XMAC_PFC_CTRL_BCM56340_A0r */
  70107         soc_block_list[214],
  70108         soc_portreg,
  70109         1,
  70110         0,
  70111         0x60e00,
  70112         SOC_REG_FLAG_64_BITS,
  70113         0,
  70114         8,
  70115         soc_CMAC_PFC_CTRLr_fields,
  70116         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  70117         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  70118         -1,
  70119         -1,
  70120     },
  70121 #endif /* chips */
  70122 
  70123 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70124     { /* SOC_REG_INT_XMAC_PFC_CTRL_BCM56440_A0r */
  70125         soc_block_list[83],
  70126         soc_portreg,
  70127         1,
  70128         0,
  70129         0x60e,
  70130         SOC_REG_FLAG_64_BITS,
  70131         0,
  70132         8,
  70133         soc_XMAC_PFC_CTRLr_fields,
  70134         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  70135         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  70136         -1,
  70137         -1,
  70138     },
  70139 #endif /* chips */
  70140 
  70141 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70142     defined(BCM_56450_B1)
  70143     { /* SOC_REG_INT_XMAC_PFC_CTRL_BCM56450_A0r */
  70144         soc_block_list[83],
  70145         soc_portreg,
  70146         1,
  70147         0,
  70148         0x40e00,
  70149         SOC_REG_FLAG_64_BITS,
  70150         0,
  70151         8,
  70152         soc_CMAC_PFC_CTRLr_fields,
  70153         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  70154         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  70155         -1,
  70156         -1,
  70157     },
  70158 #endif /* chips */
  70159 
  70160 #if defined(BCM_56640_A0)
  70161     { /* SOC_REG_INT_XMAC_PFC_CTRL_BCM56640_A0r */
  70162         soc_block_list[212],
  70163         soc_portreg,
  70164         1,
  70165         0,
  70166         0x60e00,
  70167         SOC_REG_FLAG_64_BITS,
  70168         0,
  70169         8,
  70170         soc_CMAC_PFC_CTRLr_fields,
  70171         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  70172         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  70173         -1,
  70174         -1,
  70175     },
  70176 #endif /* chips */
  70177 
  70178 #if defined(BCM_56840_B0)
  70179     { /* SOC_REG_INT_XMAC_PFC_CTRL_BCM56840_B0r */
  70180         soc_block_list[16],
  70181         soc_portreg,
  70182         1,
  70183         0,
  70184         0x60e,
  70185         SOC_REG_FLAG_64_BITS,
  70186         0,
  70187         8,
  70188         soc_XMAC_PFC_CTRLr_fields,
  70189         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  70190         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  70191         -1,
  70192         -1,
  70193     },
  70194 #endif /* chips */
  70195 
  70196 #if defined(BCM_88732_A0)
  70197     { /* SOC_REG_INT_XMAC_PFC_CTRL_BCM88732_A0r */
  70198         soc_block_list[16],
  70199         soc_portreg,
  70200         1,
  70201         0,
  70202         0x60e,
  70203         SOC_REG_FLAG_64_BITS,
  70204         0,
  70205         8,
  70206         soc_XMAC_PFC_CTRLr_fields,
  70207         SOC_RESET_VAL_DEC(0xffffc000, 0x00000000)
  70208         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  70209         -1,
  70210         -1,
  70211     },
  70212 #endif /* chips */
  70213 
  70214 #if defined(BCM_56840_A0)
  70215     { /* SOC_REG_INT_XMAC_PFC_DAr */
  70216         soc_block_list[16],
  70217         soc_portreg,
  70218         1,
  70219         0,
  70220         0x611,
  70221         SOC_REG_FLAG_64_BITS,
  70222         0,
  70223         3,
  70224         soc_XMAC_PFC_DAr_fields,
  70225         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  70226         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  70227         -1,
  70228         -1,
  70229     },
  70230 #endif /* chips */
  70231 
  70232 #if defined(BCM_56340_A0)
  70233     { /* SOC_REG_INT_XMAC_PFC_DA_BCM56340_A0r */
  70234         soc_block_list[214],
  70235         soc_portreg,
  70236         1,
  70237         0,
  70238         0x61100,
  70239         SOC_REG_FLAG_64_BITS,
  70240         0,
  70241         3,
  70242         soc_CMAC_PFC_DAr_fields,
  70243         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  70244         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  70245         -1,
  70246         -1,
  70247     },
  70248 #endif /* chips */
  70249 
  70250 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70251     { /* SOC_REG_INT_XMAC_PFC_DA_BCM56440_A0r */
  70252         soc_block_list[83],
  70253         soc_portreg,
  70254         1,
  70255         0,
  70256         0x611,
  70257         SOC_REG_FLAG_64_BITS,
  70258         0,
  70259         3,
  70260         soc_XMAC_PFC_DAr_fields,
  70261         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  70262         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  70263         -1,
  70264         -1,
  70265     },
  70266 #endif /* chips */
  70267 
  70268 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70269     defined(BCM_56450_B1)
  70270     { /* SOC_REG_INT_XMAC_PFC_DA_BCM56450_A0r */
  70271         soc_block_list[83],
  70272         soc_portreg,
  70273         1,
  70274         0,
  70275         0x41100,
  70276         SOC_REG_FLAG_64_BITS,
  70277         0,
  70278         3,
  70279         soc_CMAC_PFC_DAr_fields,
  70280         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  70281         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  70282         -1,
  70283         -1,
  70284     },
  70285 #endif /* chips */
  70286 
  70287 #if defined(BCM_56640_A0)
  70288     { /* SOC_REG_INT_XMAC_PFC_DA_BCM56640_A0r */
  70289         soc_block_list[212],
  70290         soc_portreg,
  70291         1,
  70292         0,
  70293         0x61100,
  70294         SOC_REG_FLAG_64_BITS,
  70295         0,
  70296         3,
  70297         soc_CMAC_PFC_DAr_fields,
  70298         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  70299         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  70300         -1,
  70301         -1,
  70302     },
  70303 #endif /* chips */
  70304 
  70305 #if defined(BCM_56840_B0)
  70306     { /* SOC_REG_INT_XMAC_PFC_DA_BCM56840_B0r */
  70307         soc_block_list[16],
  70308         soc_portreg,
  70309         1,
  70310         0,
  70311         0x611,
  70312         SOC_REG_FLAG_64_BITS,
  70313         0,
  70314         3,
  70315         soc_XMAC_PFC_DAr_fields,
  70316         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  70317         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  70318         -1,
  70319         -1,
  70320     },
  70321 #endif /* chips */
  70322 
  70323 #if defined(BCM_88732_A0)
  70324     { /* SOC_REG_INT_XMAC_PFC_DA_BCM88732_A0r */
  70325         soc_block_list[16],
  70326         soc_portreg,
  70327         1,
  70328         0,
  70329         0x611,
  70330         SOC_REG_FLAG_64_BITS,
  70331         0,
  70332         3,
  70333         soc_XMAC_PFC_DAr_fields,
  70334         SOC_RESET_VAL_DEC(0xc2000001, 0x00000180)
  70335         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  70336         -1,
  70337         -1,
  70338     },
  70339 #endif /* chips */
  70340 
  70341 #if defined(BCM_56840_A0)
  70342     { /* SOC_REG_INT_XMAC_PFC_OPCODEr */
  70343         soc_block_list[16],
  70344         soc_portreg,
  70345         1,
  70346         0,
  70347         0x610,
  70348         SOC_REG_FLAG_64_BITS,
  70349         0,
  70350         1,
  70351         soc_BMAC_PFC_OPCODEr_fields,
  70352         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  70353         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70354         -1,
  70355         -1,
  70356     },
  70357 #endif /* chips */
  70358 
  70359 #if defined(BCM_56340_A0)
  70360     { /* SOC_REG_INT_XMAC_PFC_OPCODE_BCM56340_A0r */
  70361         soc_block_list[214],
  70362         soc_portreg,
  70363         1,
  70364         0,
  70365         0x61000,
  70366         SOC_REG_FLAG_64_BITS,
  70367         0,
  70368         1,
  70369         soc_CMAC_PFC_OPCODEr_fields,
  70370         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  70371         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70372         -1,
  70373         -1,
  70374     },
  70375 #endif /* chips */
  70376 
  70377 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70378     { /* SOC_REG_INT_XMAC_PFC_OPCODE_BCM56440_A0r */
  70379         soc_block_list[83],
  70380         soc_portreg,
  70381         1,
  70382         0,
  70383         0x610,
  70384         SOC_REG_FLAG_64_BITS,
  70385         0,
  70386         1,
  70387         soc_BMAC_PFC_OPCODEr_fields,
  70388         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  70389         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70390         -1,
  70391         -1,
  70392     },
  70393 #endif /* chips */
  70394 
  70395 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70396     defined(BCM_56450_B1)
  70397     { /* SOC_REG_INT_XMAC_PFC_OPCODE_BCM56450_A0r */
  70398         soc_block_list[83],
  70399         soc_portreg,
  70400         1,
  70401         0,
  70402         0x41000,
  70403         SOC_REG_FLAG_64_BITS,
  70404         0,
  70405         1,
  70406         soc_CMAC_PFC_OPCODEr_fields,
  70407         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  70408         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70409         -1,
  70410         -1,
  70411     },
  70412 #endif /* chips */
  70413 
  70414 #if defined(BCM_56640_A0)
  70415     { /* SOC_REG_INT_XMAC_PFC_OPCODE_BCM56640_A0r */
  70416         soc_block_list[212],
  70417         soc_portreg,
  70418         1,
  70419         0,
  70420         0x61000,
  70421         SOC_REG_FLAG_64_BITS,
  70422         0,
  70423         1,
  70424         soc_CMAC_PFC_OPCODEr_fields,
  70425         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  70426         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70427         -1,
  70428         -1,
  70429     },
  70430 #endif /* chips */
  70431 
  70432 #if defined(BCM_56840_B0)
  70433     { /* SOC_REG_INT_XMAC_PFC_OPCODE_BCM56840_B0r */
  70434         soc_block_list[16],
  70435         soc_portreg,
  70436         1,
  70437         0,
  70438         0x610,
  70439         SOC_REG_FLAG_64_BITS,
  70440         0,
  70441         1,
  70442         soc_BMAC_PFC_OPCODEr_fields,
  70443         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  70444         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70445         -1,
  70446         -1,
  70447     },
  70448 #endif /* chips */
  70449 
  70450 #if defined(BCM_88732_A0)
  70451     { /* SOC_REG_INT_XMAC_PFC_OPCODE_BCM88732_A0r */
  70452         soc_block_list[16],
  70453         soc_portreg,
  70454         1,
  70455         0,
  70456         0x610,
  70457         SOC_REG_FLAG_64_BITS,
  70458         0,
  70459         1,
  70460         soc_BMAC_PFC_OPCODEr_fields,
  70461         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  70462         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70463         -1,
  70464         -1,
  70465     },
  70466 #endif /* chips */
  70467 
  70468 #if defined(BCM_56840_A0)
  70469     { /* SOC_REG_INT_XMAC_PFC_TYPEr */
  70470         soc_block_list[16],
  70471         soc_portreg,
  70472         1,
  70473         0,
  70474         0x60f,
  70475         SOC_REG_FLAG_64_BITS,
  70476         0,
  70477         1,
  70478         soc_BMAC_PFC_TYPEr_fields,
  70479         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  70480         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70481         -1,
  70482         -1,
  70483     },
  70484 #endif /* chips */
  70485 
  70486 #if defined(BCM_56340_A0)
  70487     { /* SOC_REG_INT_XMAC_PFC_TYPE_BCM56340_A0r */
  70488         soc_block_list[214],
  70489         soc_portreg,
  70490         1,
  70491         0,
  70492         0x60f00,
  70493         SOC_REG_FLAG_64_BITS,
  70494         0,
  70495         1,
  70496         soc_CMAC_PFC_TYPEr_fields,
  70497         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  70498         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70499         -1,
  70500         -1,
  70501     },
  70502 #endif /* chips */
  70503 
  70504 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70505     { /* SOC_REG_INT_XMAC_PFC_TYPE_BCM56440_A0r */
  70506         soc_block_list[83],
  70507         soc_portreg,
  70508         1,
  70509         0,
  70510         0x60f,
  70511         SOC_REG_FLAG_64_BITS,
  70512         0,
  70513         1,
  70514         soc_BMAC_PFC_TYPEr_fields,
  70515         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  70516         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70517         -1,
  70518         -1,
  70519     },
  70520 #endif /* chips */
  70521 
  70522 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70523     defined(BCM_56450_B1)
  70524     { /* SOC_REG_INT_XMAC_PFC_TYPE_BCM56450_A0r */
  70525         soc_block_list[83],
  70526         soc_portreg,
  70527         1,
  70528         0,
  70529         0x40f00,
  70530         SOC_REG_FLAG_64_BITS,
  70531         0,
  70532         1,
  70533         soc_CMAC_PFC_TYPEr_fields,
  70534         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  70535         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70536         -1,
  70537         -1,
  70538     },
  70539 #endif /* chips */
  70540 
  70541 #if defined(BCM_56640_A0)
  70542     { /* SOC_REG_INT_XMAC_PFC_TYPE_BCM56640_A0r */
  70543         soc_block_list[212],
  70544         soc_portreg,
  70545         1,
  70546         0,
  70547         0x60f00,
  70548         SOC_REG_FLAG_64_BITS,
  70549         0,
  70550         1,
  70551         soc_CMAC_PFC_TYPEr_fields,
  70552         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  70553         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70554         -1,
  70555         -1,
  70556     },
  70557 #endif /* chips */
  70558 
  70559 #if defined(BCM_56840_B0)
  70560     { /* SOC_REG_INT_XMAC_PFC_TYPE_BCM56840_B0r */
  70561         soc_block_list[16],
  70562         soc_portreg,
  70563         1,
  70564         0,
  70565         0x60f,
  70566         SOC_REG_FLAG_64_BITS,
  70567         0,
  70568         1,
  70569         soc_BMAC_PFC_TYPEr_fields,
  70570         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  70571         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70572         -1,
  70573         -1,
  70574     },
  70575 #endif /* chips */
  70576 
  70577 #if defined(BCM_88732_A0)
  70578     { /* SOC_REG_INT_XMAC_PFC_TYPE_BCM88732_A0r */
  70579         soc_block_list[16],
  70580         soc_portreg,
  70581         1,
  70582         0,
  70583         0x60f,
  70584         SOC_REG_FLAG_64_BITS,
  70585         0,
  70586         1,
  70587         soc_BMAC_PFC_TYPEr_fields,
  70588         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  70589         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  70590         -1,
  70591         -1,
  70592     },
  70593 #endif /* chips */
  70594 
  70595 #if defined(BCM_56840_A0)
  70596     { /* SOC_REG_INT_XMAC_RX_CTRLr */
  70597         soc_block_list[16],
  70598         soc_portreg,
  70599         1,
  70600         0,
  70601         0x606,
  70602         SOC_REG_FLAG_64_BITS,
  70603         0,
  70604         5,
  70605         soc_XMAC_RX_CTRLr_fields,
  70606         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  70607         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70608         -1,
  70609         -1,
  70610     },
  70611 #endif /* chips */
  70612 
  70613 #if defined(BCM_56340_A0)
  70614     { /* SOC_REG_INT_XMAC_RX_CTRL_BCM56340_A0r */
  70615         soc_block_list[214],
  70616         soc_portreg,
  70617         1,
  70618         0,
  70619         0x60600,
  70620         SOC_REG_FLAG_64_BITS,
  70621         0,
  70622         7,
  70623         soc_XMAC_RX_CTRL_BCM56640_A0r_fields,
  70624         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  70625         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  70626         -1,
  70627         -1,
  70628     },
  70629 #endif /* chips */
  70630 
  70631 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70632     { /* SOC_REG_INT_XMAC_RX_CTRL_BCM56440_A0r */
  70633         soc_block_list[83],
  70634         soc_portreg,
  70635         1,
  70636         0,
  70637         0x606,
  70638         SOC_REG_FLAG_64_BITS,
  70639         0,
  70640         7,
  70641         soc_XMAC_RX_CTRL_BCM56440_A0r_fields,
  70642         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  70643         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  70644         -1,
  70645         -1,
  70646     },
  70647 #endif /* chips */
  70648 
  70649 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70650     defined(BCM_56450_B1)
  70651     { /* SOC_REG_INT_XMAC_RX_CTRL_BCM56450_A0r */
  70652         soc_block_list[83],
  70653         soc_portreg,
  70654         1,
  70655         0,
  70656         0x40600,
  70657         SOC_REG_FLAG_64_BITS,
  70658         0,
  70659         7,
  70660         soc_XMAC_RX_CTRL_BCM56640_A0r_fields,
  70661         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  70662         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  70663         -1,
  70664         -1,
  70665     },
  70666 #endif /* chips */
  70667 
  70668 #if defined(BCM_56640_A0)
  70669     { /* SOC_REG_INT_XMAC_RX_CTRL_BCM56640_A0r */
  70670         soc_block_list[212],
  70671         soc_portreg,
  70672         1,
  70673         0,
  70674         0x60600,
  70675         SOC_REG_FLAG_64_BITS,
  70676         0,
  70677         7,
  70678         soc_XMAC_RX_CTRL_BCM56640_A0r_fields,
  70679         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  70680         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  70681         -1,
  70682         -1,
  70683     },
  70684 #endif /* chips */
  70685 
  70686 #if defined(BCM_56840_B0)
  70687     { /* SOC_REG_INT_XMAC_RX_CTRL_BCM56840_B0r */
  70688         soc_block_list[16],
  70689         soc_portreg,
  70690         1,
  70691         0,
  70692         0x606,
  70693         SOC_REG_FLAG_64_BITS,
  70694         0,
  70695         5,
  70696         soc_XMAC_RX_CTRLr_fields,
  70697         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  70698         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70699         -1,
  70700         -1,
  70701     },
  70702 #endif /* chips */
  70703 
  70704 #if defined(BCM_88732_A0)
  70705     { /* SOC_REG_INT_XMAC_RX_CTRL_BCM88732_A0r */
  70706         soc_block_list[16],
  70707         soc_portreg,
  70708         1,
  70709         0,
  70710         0x606,
  70711         SOC_REG_FLAG_64_BITS,
  70712         0,
  70713         5,
  70714         soc_XMAC_RX_CTRLr_fields,
  70715         SOC_RESET_VAL_DEC(0x0000040c, 0x00000000)
  70716         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  70717         -1,
  70718         -1,
  70719     },
  70720 #endif /* chips */
  70721 
  70722 #if defined(BCM_56840_A0)
  70723     { /* SOC_REG_INT_XMAC_RX_LLFC_MSG_FIELDSr */
  70724         soc_block_list[16],
  70725         soc_portreg,
  70726         1,
  70727         0,
  70728         0x614,
  70729         SOC_REG_FLAG_64_BITS,
  70730         0,
  70731         4,
  70732         soc_XMAC_RX_LLFC_MSG_FIELDSr_fields,
  70733         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  70734         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  70735         -1,
  70736         -1,
  70737     },
  70738 #endif /* chips */
  70739 
  70740 #if defined(BCM_56340_A0)
  70741     { /* SOC_REG_INT_XMAC_RX_LLFC_MSG_FIELDS_BCM56340_A0r */
  70742         soc_block_list[214],
  70743         soc_portreg,
  70744         1,
  70745         0,
  70746         0x61400,
  70747         SOC_REG_FLAG_64_BITS,
  70748         0,
  70749         4,
  70750         soc_CMAC_RX_LLFC_MSG_FIELDSr_fields,
  70751         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  70752         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  70753         -1,
  70754         -1,
  70755     },
  70756 #endif /* chips */
  70757 
  70758 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70759     { /* SOC_REG_INT_XMAC_RX_LLFC_MSG_FIELDS_BCM56440_A0r */
  70760         soc_block_list[83],
  70761         soc_portreg,
  70762         1,
  70763         0,
  70764         0x614,
  70765         SOC_REG_FLAG_64_BITS,
  70766         0,
  70767         4,
  70768         soc_XMAC_RX_LLFC_MSG_FIELDSr_fields,
  70769         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  70770         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  70771         -1,
  70772         -1,
  70773     },
  70774 #endif /* chips */
  70775 
  70776 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70777     defined(BCM_56450_B1)
  70778     { /* SOC_REG_INT_XMAC_RX_LLFC_MSG_FIELDS_BCM56450_A0r */
  70779         soc_block_list[83],
  70780         soc_portreg,
  70781         1,
  70782         0,
  70783         0x41400,
  70784         SOC_REG_FLAG_64_BITS,
  70785         0,
  70786         4,
  70787         soc_CMAC_RX_LLFC_MSG_FIELDSr_fields,
  70788         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  70789         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  70790         -1,
  70791         -1,
  70792     },
  70793 #endif /* chips */
  70794 
  70795 #if defined(BCM_56640_A0)
  70796     { /* SOC_REG_INT_XMAC_RX_LLFC_MSG_FIELDS_BCM56640_A0r */
  70797         soc_block_list[212],
  70798         soc_portreg,
  70799         1,
  70800         0,
  70801         0x61400,
  70802         SOC_REG_FLAG_64_BITS,
  70803         0,
  70804         4,
  70805         soc_CMAC_RX_LLFC_MSG_FIELDSr_fields,
  70806         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  70807         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  70808         -1,
  70809         -1,
  70810     },
  70811 #endif /* chips */
  70812 
  70813 #if defined(BCM_56840_B0)
  70814     { /* SOC_REG_INT_XMAC_RX_LLFC_MSG_FIELDS_BCM56840_B0r */
  70815         soc_block_list[16],
  70816         soc_portreg,
  70817         1,
  70818         0,
  70819         0x614,
  70820         SOC_REG_FLAG_64_BITS,
  70821         0,
  70822         4,
  70823         soc_XMAC_RX_LLFC_MSG_FIELDSr_fields,
  70824         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  70825         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  70826         -1,
  70827         -1,
  70828     },
  70829 #endif /* chips */
  70830 
  70831 #if defined(BCM_88732_A0)
  70832     { /* SOC_REG_INT_XMAC_RX_LLFC_MSG_FIELDS_BCM88732_A0r */
  70833         soc_block_list[16],
  70834         soc_portreg,
  70835         1,
  70836         0,
  70837         0x614,
  70838         SOC_REG_FLAG_64_BITS,
  70839         0,
  70840         4,
  70841         soc_XMAC_RX_LLFC_MSG_FIELDSr_fields,
  70842         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  70843         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  70844         -1,
  70845         -1,
  70846     },
  70847 #endif /* chips */
  70848 
  70849 #if defined(BCM_56840_A0)
  70850     { /* SOC_REG_INT_XMAC_RX_LSS_CTRLr */
  70851         soc_block_list[16],
  70852         soc_portreg,
  70853         1,
  70854         0,
  70855         0x60a,
  70856         SOC_REG_FLAG_64_BITS,
  70857         0,
  70858         2,
  70859         soc_XMAC_RX_LSS_CTRLr_fields,
  70860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70861         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  70862         -1,
  70863         -1,
  70864     },
  70865 #endif /* chips */
  70866 
  70867 #if defined(BCM_56340_A0)
  70868     { /* SOC_REG_INT_XMAC_RX_LSS_CTRL_BCM56340_A0r */
  70869         soc_block_list[214],
  70870         soc_portreg,
  70871         1,
  70872         0,
  70873         0x60a00,
  70874         SOC_REG_FLAG_64_BITS,
  70875         0,
  70876         8,
  70877         soc_XMAC_RX_LSS_CTRL_BCM56640_A0r_fields,
  70878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70879         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  70880         -1,
  70881         -1,
  70882     },
  70883 #endif /* chips */
  70884 
  70885 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  70886     { /* SOC_REG_INT_XMAC_RX_LSS_CTRL_BCM56440_A0r */
  70887         soc_block_list[83],
  70888         soc_portreg,
  70889         1,
  70890         0,
  70891         0x60a,
  70892         SOC_REG_FLAG_64_BITS,
  70893         0,
  70894         3,
  70895         soc_XMAC_RX_LSS_CTRL_BCM56440_A0r_fields,
  70896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70897         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  70898         -1,
  70899         -1,
  70900     },
  70901 #endif /* chips */
  70902 
  70903 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  70904     defined(BCM_56450_B1)
  70905     { /* SOC_REG_INT_XMAC_RX_LSS_CTRL_BCM56450_A0r */
  70906         soc_block_list[83],
  70907         soc_portreg,
  70908         1,
  70909         0,
  70910         0x40a00,
  70911         SOC_REG_FLAG_64_BITS,
  70912         0,
  70913         8,
  70914         soc_XMAC_RX_LSS_CTRL_BCM56640_A0r_fields,
  70915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70916         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  70917         -1,
  70918         -1,
  70919     },
  70920 #endif /* chips */
  70921 
  70922 #if defined(BCM_56640_A0)
  70923     { /* SOC_REG_INT_XMAC_RX_LSS_CTRL_BCM56640_A0r */
  70924         soc_block_list[212],
  70925         soc_portreg,
  70926         1,
  70927         0,
  70928         0x60a00,
  70929         SOC_REG_FLAG_64_BITS,
  70930         0,
  70931         8,
  70932         soc_XMAC_RX_LSS_CTRL_BCM56640_A0r_fields,
  70933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70934         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  70935         -1,
  70936         -1,
  70937     },
  70938 #endif /* chips */
  70939 
  70940 #if defined(BCM_56840_B0)
  70941     { /* SOC_REG_INT_XMAC_RX_LSS_CTRL_BCM56840_B0r */
  70942         soc_block_list[16],
  70943         soc_portreg,
  70944         1,
  70945         0,
  70946         0x60a,
  70947         SOC_REG_FLAG_64_BITS,
  70948         0,
  70949         2,
  70950         soc_XMAC_RX_LSS_CTRLr_fields,
  70951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70952         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  70953         -1,
  70954         -1,
  70955     },
  70956 #endif /* chips */
  70957 
  70958 #if defined(BCM_88732_A0)
  70959     { /* SOC_REG_INT_XMAC_RX_LSS_CTRL_BCM88732_A0r */
  70960         soc_block_list[16],
  70961         soc_portreg,
  70962         1,
  70963         0,
  70964         0x60a,
  70965         SOC_REG_FLAG_64_BITS,
  70966         0,
  70967         2,
  70968         soc_XMAC_RX_LSS_CTRLr_fields,
  70969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70970         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  70971         -1,
  70972         -1,
  70973     },
  70974 #endif /* chips */
  70975 
  70976 #if defined(BCM_56840_A0)
  70977     { /* SOC_REG_INT_XMAC_RX_LSS_STATUSr */
  70978         soc_block_list[16],
  70979         soc_portreg,
  70980         1,
  70981         0,
  70982         0x60b,
  70983         SOC_REG_FLAG_64_BITS |
  70984                           SOC_REG_FLAG_RO,
  70985         0,
  70986         2,
  70987         soc_XMAC_RX_LSS_STATUSr_fields,
  70988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  70990         -1,
  70991         -1,
  70992     },
  70993 #endif /* chips */
  70994 
  70995 #if defined(BCM_56340_A0)
  70996     { /* SOC_REG_INT_XMAC_RX_LSS_STATUS_BCM56340_A0r */
  70997         soc_block_list[214],
  70998         soc_portreg,
  70999         1,
  71000         0,
  71001         0x60b00,
  71002         SOC_REG_FLAG_64_BITS |
  71003                           SOC_REG_FLAG_RO,
  71004         0,
  71005         3,
  71006         soc_XMAC_RX_LSS_STATUS_BCM56640_A0r_fields,
  71007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71008         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  71009         -1,
  71010         -1,
  71011     },
  71012 #endif /* chips */
  71013 
  71014 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71015     { /* SOC_REG_INT_XMAC_RX_LSS_STATUS_BCM56440_A0r */
  71016         soc_block_list[83],
  71017         soc_portreg,
  71018         1,
  71019         0,
  71020         0x60b,
  71021         SOC_REG_FLAG_64_BITS |
  71022                           SOC_REG_FLAG_RO,
  71023         0,
  71024         2,
  71025         soc_XMAC_RX_LSS_STATUS_BCM56440_A0r_fields,
  71026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71027         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  71028         -1,
  71029         -1,
  71030     },
  71031 #endif /* chips */
  71032 
  71033 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71034     defined(BCM_56450_B1)
  71035     { /* SOC_REG_INT_XMAC_RX_LSS_STATUS_BCM56450_A0r */
  71036         soc_block_list[83],
  71037         soc_portreg,
  71038         1,
  71039         0,
  71040         0x40b00,
  71041         SOC_REG_FLAG_64_BITS |
  71042                           SOC_REG_FLAG_RO,
  71043         0,
  71044         3,
  71045         soc_XMAC_RX_LSS_STATUS_BCM56640_A0r_fields,
  71046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71047         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  71048         -1,
  71049         -1,
  71050     },
  71051 #endif /* chips */
  71052 
  71053 #if defined(BCM_56640_A0)
  71054     { /* SOC_REG_INT_XMAC_RX_LSS_STATUS_BCM56640_A0r */
  71055         soc_block_list[212],
  71056         soc_portreg,
  71057         1,
  71058         0,
  71059         0x60b00,
  71060         SOC_REG_FLAG_64_BITS |
  71061                           SOC_REG_FLAG_RO,
  71062         0,
  71063         3,
  71064         soc_XMAC_RX_LSS_STATUS_BCM56640_A0r_fields,
  71065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71066         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  71067         -1,
  71068         -1,
  71069     },
  71070 #endif /* chips */
  71071 
  71072 #if defined(BCM_56840_B0)
  71073     { /* SOC_REG_INT_XMAC_RX_LSS_STATUS_BCM56840_B0r */
  71074         soc_block_list[16],
  71075         soc_portreg,
  71076         1,
  71077         0,
  71078         0x60b,
  71079         SOC_REG_FLAG_64_BITS |
  71080                           SOC_REG_FLAG_RO,
  71081         0,
  71082         2,
  71083         soc_XMAC_RX_LSS_STATUSr_fields,
  71084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71085         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  71086         -1,
  71087         -1,
  71088     },
  71089 #endif /* chips */
  71090 
  71091 #if defined(BCM_88732_A0)
  71092     { /* SOC_REG_INT_XMAC_RX_LSS_STATUS_BCM88732_A0r */
  71093         soc_block_list[16],
  71094         soc_portreg,
  71095         1,
  71096         0,
  71097         0x60b,
  71098         SOC_REG_FLAG_64_BITS |
  71099                           SOC_REG_FLAG_RO,
  71100         0,
  71101         2,
  71102         soc_XMAC_RX_LSS_STATUSr_fields,
  71103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  71105         -1,
  71106         -1,
  71107     },
  71108 #endif /* chips */
  71109 
  71110 #if defined(BCM_56840_A0)
  71111     { /* SOC_REG_INT_XMAC_RX_MAC_SAr */
  71112         soc_block_list[16],
  71113         soc_portreg,
  71114         1,
  71115         0,
  71116         0x607,
  71117         SOC_REG_FLAG_64_BITS,
  71118         0,
  71119         3,
  71120         soc_XMAC_RX_MAC_SAr_fields,
  71121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71122         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  71123         -1,
  71124         -1,
  71125     },
  71126 #endif /* chips */
  71127 
  71128 #if defined(BCM_56340_A0)
  71129     { /* SOC_REG_INT_XMAC_RX_MAC_SA_BCM56340_A0r */
  71130         soc_block_list[214],
  71131         soc_portreg,
  71132         1,
  71133         0,
  71134         0x60700,
  71135         SOC_REG_FLAG_64_BITS,
  71136         0,
  71137         3,
  71138         soc_CMAC_RX_MAC_SAr_fields,
  71139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71140         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  71141         -1,
  71142         -1,
  71143     },
  71144 #endif /* chips */
  71145 
  71146 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71147     { /* SOC_REG_INT_XMAC_RX_MAC_SA_BCM56440_A0r */
  71148         soc_block_list[83],
  71149         soc_portreg,
  71150         1,
  71151         0,
  71152         0x607,
  71153         SOC_REG_FLAG_64_BITS,
  71154         0,
  71155         3,
  71156         soc_XMAC_RX_MAC_SAr_fields,
  71157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71158         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  71159         -1,
  71160         -1,
  71161     },
  71162 #endif /* chips */
  71163 
  71164 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71165     defined(BCM_56450_B1)
  71166     { /* SOC_REG_INT_XMAC_RX_MAC_SA_BCM56450_A0r */
  71167         soc_block_list[83],
  71168         soc_portreg,
  71169         1,
  71170         0,
  71171         0x40700,
  71172         SOC_REG_FLAG_64_BITS,
  71173         0,
  71174         3,
  71175         soc_CMAC_RX_MAC_SAr_fields,
  71176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71177         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  71178         -1,
  71179         -1,
  71180     },
  71181 #endif /* chips */
  71182 
  71183 #if defined(BCM_56640_A0)
  71184     { /* SOC_REG_INT_XMAC_RX_MAC_SA_BCM56640_A0r */
  71185         soc_block_list[212],
  71186         soc_portreg,
  71187         1,
  71188         0,
  71189         0x60700,
  71190         SOC_REG_FLAG_64_BITS,
  71191         0,
  71192         3,
  71193         soc_CMAC_RX_MAC_SAr_fields,
  71194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71195         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  71196         -1,
  71197         -1,
  71198     },
  71199 #endif /* chips */
  71200 
  71201 #if defined(BCM_56840_B0)
  71202     { /* SOC_REG_INT_XMAC_RX_MAC_SA_BCM56840_B0r */
  71203         soc_block_list[16],
  71204         soc_portreg,
  71205         1,
  71206         0,
  71207         0x607,
  71208         SOC_REG_FLAG_64_BITS,
  71209         0,
  71210         3,
  71211         soc_XMAC_RX_MAC_SAr_fields,
  71212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71213         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  71214         -1,
  71215         -1,
  71216     },
  71217 #endif /* chips */
  71218 
  71219 #if defined(BCM_88732_A0)
  71220     { /* SOC_REG_INT_XMAC_RX_MAC_SA_BCM88732_A0r */
  71221         soc_block_list[16],
  71222         soc_portreg,
  71223         1,
  71224         0,
  71225         0x607,
  71226         SOC_REG_FLAG_64_BITS,
  71227         0,
  71228         3,
  71229         soc_XMAC_RX_MAC_SAr_fields,
  71230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71231         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  71232         -1,
  71233         -1,
  71234     },
  71235 #endif /* chips */
  71236 
  71237 #if defined(BCM_56840_A0)
  71238     { /* SOC_REG_INT_XMAC_RX_MAX_SIZEr */
  71239         soc_block_list[16],
  71240         soc_portreg,
  71241         1,
  71242         0,
  71243         0x608,
  71244         SOC_REG_FLAG_64_BITS,
  71245         0,
  71246         1,
  71247         soc_XMAC_RX_MAX_SIZEr_fields,
  71248         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  71249         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  71250         -1,
  71251         -1,
  71252     },
  71253 #endif /* chips */
  71254 
  71255 #if defined(BCM_56340_A0)
  71256     { /* SOC_REG_INT_XMAC_RX_MAX_SIZE_BCM56340_A0r */
  71257         soc_block_list[214],
  71258         soc_portreg,
  71259         1,
  71260         0,
  71261         0x60800,
  71262         SOC_REG_FLAG_64_BITS,
  71263         0,
  71264         1,
  71265         soc_CMAC_RX_MAX_SIZEr_fields,
  71266         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  71267         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  71268         -1,
  71269         -1,
  71270     },
  71271 #endif /* chips */
  71272 
  71273 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71274     { /* SOC_REG_INT_XMAC_RX_MAX_SIZE_BCM56440_A0r */
  71275         soc_block_list[83],
  71276         soc_portreg,
  71277         1,
  71278         0,
  71279         0x608,
  71280         SOC_REG_FLAG_64_BITS,
  71281         0,
  71282         1,
  71283         soc_XMAC_RX_MAX_SIZEr_fields,
  71284         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  71285         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  71286         -1,
  71287         -1,
  71288     },
  71289 #endif /* chips */
  71290 
  71291 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71292     defined(BCM_56450_B1)
  71293     { /* SOC_REG_INT_XMAC_RX_MAX_SIZE_BCM56450_A0r */
  71294         soc_block_list[83],
  71295         soc_portreg,
  71296         1,
  71297         0,
  71298         0x40800,
  71299         SOC_REG_FLAG_64_BITS,
  71300         0,
  71301         1,
  71302         soc_CMAC_RX_MAX_SIZEr_fields,
  71303         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  71304         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  71305         -1,
  71306         -1,
  71307     },
  71308 #endif /* chips */
  71309 
  71310 #if defined(BCM_56640_A0)
  71311     { /* SOC_REG_INT_XMAC_RX_MAX_SIZE_BCM56640_A0r */
  71312         soc_block_list[212],
  71313         soc_portreg,
  71314         1,
  71315         0,
  71316         0x60800,
  71317         SOC_REG_FLAG_64_BITS,
  71318         0,
  71319         1,
  71320         soc_CMAC_RX_MAX_SIZEr_fields,
  71321         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  71322         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  71323         -1,
  71324         -1,
  71325     },
  71326 #endif /* chips */
  71327 
  71328 #if defined(BCM_56840_B0)
  71329     { /* SOC_REG_INT_XMAC_RX_MAX_SIZE_BCM56840_B0r */
  71330         soc_block_list[16],
  71331         soc_portreg,
  71332         1,
  71333         0,
  71334         0x608,
  71335         SOC_REG_FLAG_64_BITS,
  71336         0,
  71337         1,
  71338         soc_XMAC_RX_MAX_SIZEr_fields,
  71339         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  71340         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  71341         -1,
  71342         -1,
  71343     },
  71344 #endif /* chips */
  71345 
  71346 #if defined(BCM_88732_A0)
  71347     { /* SOC_REG_INT_XMAC_RX_MAX_SIZE_BCM88732_A0r */
  71348         soc_block_list[16],
  71349         soc_portreg,
  71350         1,
  71351         0,
  71352         0x608,
  71353         SOC_REG_FLAG_64_BITS,
  71354         0,
  71355         1,
  71356         soc_XMAC_RX_MAX_SIZEr_fields,
  71357         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  71358         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  71359         -1,
  71360         -1,
  71361     },
  71362 #endif /* chips */
  71363 
  71364 #if defined(BCM_56840_A0)
  71365     { /* SOC_REG_INT_XMAC_RX_VLAN_TAGr */
  71366         soc_block_list[16],
  71367         soc_portreg,
  71368         1,
  71369         0,
  71370         0x609,
  71371         SOC_REG_FLAG_64_BITS,
  71372         0,
  71373         4,
  71374         soc_XMAC_RX_VLAN_TAGr_fields,
  71375         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  71376         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  71377         -1,
  71378         -1,
  71379     },
  71380 #endif /* chips */
  71381 
  71382 #if defined(BCM_56340_A0)
  71383     { /* SOC_REG_INT_XMAC_RX_VLAN_TAG_BCM56340_A0r */
  71384         soc_block_list[214],
  71385         soc_portreg,
  71386         1,
  71387         0,
  71388         0x60900,
  71389         SOC_REG_FLAG_64_BITS,
  71390         0,
  71391         4,
  71392         soc_CMAC_RX_VLAN_TAGr_fields,
  71393         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  71394         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  71395         -1,
  71396         -1,
  71397     },
  71398 #endif /* chips */
  71399 
  71400 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71401     { /* SOC_REG_INT_XMAC_RX_VLAN_TAG_BCM56440_A0r */
  71402         soc_block_list[83],
  71403         soc_portreg,
  71404         1,
  71405         0,
  71406         0x609,
  71407         SOC_REG_FLAG_64_BITS,
  71408         0,
  71409         4,
  71410         soc_XMAC_RX_VLAN_TAGr_fields,
  71411         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  71412         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  71413         -1,
  71414         -1,
  71415     },
  71416 #endif /* chips */
  71417 
  71418 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71419     defined(BCM_56450_B1)
  71420     { /* SOC_REG_INT_XMAC_RX_VLAN_TAG_BCM56450_A0r */
  71421         soc_block_list[83],
  71422         soc_portreg,
  71423         1,
  71424         0,
  71425         0x40900,
  71426         SOC_REG_FLAG_64_BITS,
  71427         0,
  71428         4,
  71429         soc_CMAC_RX_VLAN_TAGr_fields,
  71430         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  71431         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  71432         -1,
  71433         -1,
  71434     },
  71435 #endif /* chips */
  71436 
  71437 #if defined(BCM_56640_A0)
  71438     { /* SOC_REG_INT_XMAC_RX_VLAN_TAG_BCM56640_A0r */
  71439         soc_block_list[212],
  71440         soc_portreg,
  71441         1,
  71442         0,
  71443         0x60900,
  71444         SOC_REG_FLAG_64_BITS,
  71445         0,
  71446         4,
  71447         soc_CMAC_RX_VLAN_TAGr_fields,
  71448         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  71449         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  71450         -1,
  71451         -1,
  71452     },
  71453 #endif /* chips */
  71454 
  71455 #if defined(BCM_56840_B0)
  71456     { /* SOC_REG_INT_XMAC_RX_VLAN_TAG_BCM56840_B0r */
  71457         soc_block_list[16],
  71458         soc_portreg,
  71459         1,
  71460         0,
  71461         0x609,
  71462         SOC_REG_FLAG_64_BITS,
  71463         0,
  71464         4,
  71465         soc_XMAC_RX_VLAN_TAGr_fields,
  71466         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  71467         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  71468         -1,
  71469         -1,
  71470     },
  71471 #endif /* chips */
  71472 
  71473 #if defined(BCM_88732_A0)
  71474     { /* SOC_REG_INT_XMAC_RX_VLAN_TAG_BCM88732_A0r */
  71475         soc_block_list[16],
  71476         soc_portreg,
  71477         1,
  71478         0,
  71479         0x609,
  71480         SOC_REG_FLAG_64_BITS,
  71481         0,
  71482         4,
  71483         soc_XMAC_RX_VLAN_TAGr_fields,
  71484         SOC_RESET_VAL_DEC(0x81008100, 0x00000003)
  71485         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  71486         -1,
  71487         -1,
  71488     },
  71489 #endif /* chips */
  71490 
  71491 #if defined(BCM_56840_A0)
  71492     { /* SOC_REG_INT_XMAC_SPARE0r */
  71493         soc_block_list[16],
  71494         soc_portreg,
  71495         1,
  71496         0,
  71497         0x602,
  71498         SOC_REG_FLAG_64_BITS,
  71499         0,
  71500         1,
  71501         soc_MAC_CORESPARE0r_fields,
  71502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71503         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71504         -1,
  71505         -1,
  71506     },
  71507 #endif /* chips */
  71508 
  71509 #if defined(BCM_56840_A0)
  71510     { /* SOC_REG_INT_XMAC_SPARE1r */
  71511         soc_block_list[16],
  71512         soc_portreg,
  71513         1,
  71514         0,
  71515         0x603,
  71516         SOC_REG_FLAG_64_BITS,
  71517         0,
  71518         1,
  71519         soc_XMAC_SPARE1r_fields,
  71520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71521         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  71522         -1,
  71523         -1,
  71524     },
  71525 #endif /* chips */
  71526 
  71527 #if defined(BCM_56340_A0)
  71528     { /* SOC_REG_INT_XMAC_SPARE0_BCM56340_A0r */
  71529         soc_block_list[214],
  71530         soc_portreg,
  71531         1,
  71532         0,
  71533         0x60200,
  71534         SOC_REG_FLAG_64_BITS,
  71535         0,
  71536         1,
  71537         soc_CMAC_SPARE0r_fields,
  71538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71539         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71540         -1,
  71541         -1,
  71542     },
  71543 #endif /* chips */
  71544 
  71545 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71546     { /* SOC_REG_INT_XMAC_SPARE0_BCM56440_A0r */
  71547         soc_block_list[83],
  71548         soc_portreg,
  71549         1,
  71550         0,
  71551         0x602,
  71552         SOC_REG_FLAG_64_BITS,
  71553         0,
  71554         1,
  71555         soc_MAC_CORESPARE0r_fields,
  71556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71557         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71558         -1,
  71559         -1,
  71560     },
  71561 #endif /* chips */
  71562 
  71563 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71564     defined(BCM_56450_B1)
  71565     { /* SOC_REG_INT_XMAC_SPARE0_BCM56450_A0r */
  71566         soc_block_list[83],
  71567         soc_portreg,
  71568         1,
  71569         0,
  71570         0x40200,
  71571         SOC_REG_FLAG_64_BITS,
  71572         0,
  71573         1,
  71574         soc_CMAC_SPARE0r_fields,
  71575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71576         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71577         -1,
  71578         -1,
  71579     },
  71580 #endif /* chips */
  71581 
  71582 #if defined(BCM_56640_A0)
  71583     { /* SOC_REG_INT_XMAC_SPARE0_BCM56640_A0r */
  71584         soc_block_list[212],
  71585         soc_portreg,
  71586         1,
  71587         0,
  71588         0x60200,
  71589         SOC_REG_FLAG_64_BITS,
  71590         0,
  71591         1,
  71592         soc_CMAC_SPARE0r_fields,
  71593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71594         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71595         -1,
  71596         -1,
  71597     },
  71598 #endif /* chips */
  71599 
  71600 #if defined(BCM_56840_B0)
  71601     { /* SOC_REG_INT_XMAC_SPARE0_BCM56840_B0r */
  71602         soc_block_list[16],
  71603         soc_portreg,
  71604         1,
  71605         0,
  71606         0x602,
  71607         SOC_REG_FLAG_64_BITS,
  71608         0,
  71609         1,
  71610         soc_MAC_CORESPARE0r_fields,
  71611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71612         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71613         -1,
  71614         -1,
  71615     },
  71616 #endif /* chips */
  71617 
  71618 #if defined(BCM_88732_A0)
  71619     { /* SOC_REG_INT_XMAC_SPARE0_BCM88732_A0r */
  71620         soc_block_list[16],
  71621         soc_portreg,
  71622         1,
  71623         0,
  71624         0x602,
  71625         SOC_REG_FLAG_64_BITS,
  71626         0,
  71627         1,
  71628         soc_MAC_CORESPARE0r_fields,
  71629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71630         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71631         -1,
  71632         -1,
  71633     },
  71634 #endif /* chips */
  71635 
  71636 #if defined(BCM_56340_A0)
  71637     { /* SOC_REG_INT_XMAC_SPARE1_BCM56340_A0r */
  71638         soc_block_list[214],
  71639         soc_portreg,
  71640         1,
  71641         0,
  71642         0x60300,
  71643         SOC_REG_FLAG_64_BITS,
  71644         0,
  71645         1,
  71646         soc_CMAC_SPARE1r_fields,
  71647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71648         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  71649         -1,
  71650         -1,
  71651     },
  71652 #endif /* chips */
  71653 
  71654 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71655     { /* SOC_REG_INT_XMAC_SPARE1_BCM56440_A0r */
  71656         soc_block_list[83],
  71657         soc_portreg,
  71658         1,
  71659         0,
  71660         0x603,
  71661         SOC_REG_FLAG_64_BITS,
  71662         0,
  71663         1,
  71664         soc_XMAC_SPARE1r_fields,
  71665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71666         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  71667         -1,
  71668         -1,
  71669     },
  71670 #endif /* chips */
  71671 
  71672 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71673     defined(BCM_56450_B1)
  71674     { /* SOC_REG_INT_XMAC_SPARE1_BCM56450_A0r */
  71675         soc_block_list[83],
  71676         soc_portreg,
  71677         1,
  71678         0,
  71679         0x40300,
  71680         SOC_REG_FLAG_64_BITS,
  71681         0,
  71682         1,
  71683         soc_CMAC_SPARE1r_fields,
  71684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71685         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  71686         -1,
  71687         -1,
  71688     },
  71689 #endif /* chips */
  71690 
  71691 #if defined(BCM_56640_A0)
  71692     { /* SOC_REG_INT_XMAC_SPARE1_BCM56640_A0r */
  71693         soc_block_list[212],
  71694         soc_portreg,
  71695         1,
  71696         0,
  71697         0x60300,
  71698         SOC_REG_FLAG_64_BITS,
  71699         0,
  71700         1,
  71701         soc_CMAC_SPARE1r_fields,
  71702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71703         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  71704         -1,
  71705         -1,
  71706     },
  71707 #endif /* chips */
  71708 
  71709 #if defined(BCM_56840_B0)
  71710     { /* SOC_REG_INT_XMAC_SPARE1_BCM56840_B0r */
  71711         soc_block_list[16],
  71712         soc_portreg,
  71713         1,
  71714         0,
  71715         0x603,
  71716         SOC_REG_FLAG_64_BITS,
  71717         0,
  71718         1,
  71719         soc_XMAC_SPARE1r_fields,
  71720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71721         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  71722         -1,
  71723         -1,
  71724     },
  71725 #endif /* chips */
  71726 
  71727 #if defined(BCM_88732_A0)
  71728     { /* SOC_REG_INT_XMAC_SPARE1_BCM88732_A0r */
  71729         soc_block_list[16],
  71730         soc_portreg,
  71731         1,
  71732         0,
  71733         0x603,
  71734         SOC_REG_FLAG_64_BITS,
  71735         0,
  71736         1,
  71737         soc_XMAC_SPARE1r_fields,
  71738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71739         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  71740         -1,
  71741         -1,
  71742     },
  71743 #endif /* chips */
  71744 
  71745 #if defined(BCM_56840_A0)
  71746     { /* SOC_REG_INT_XMAC_TX_CTRLr */
  71747         soc_block_list[16],
  71748         soc_portreg,
  71749         1,
  71750         0,
  71751         0x604,
  71752         SOC_REG_FLAG_64_BITS,
  71753         0,
  71754         8,
  71755         soc_XMAC_TX_CTRLr_fields,
  71756         SOC_RESET_VAL_DEC(0x0000c802, 0x00000000)
  71757         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  71758         -1,
  71759         -1,
  71760     },
  71761 #endif /* chips */
  71762 
  71763 #if defined(BCM_56340_A0)
  71764     { /* SOC_REG_INT_XMAC_TX_CTRL_BCM56340_A0r */
  71765         soc_block_list[214],
  71766         soc_portreg,
  71767         1,
  71768         0,
  71769         0x60400,
  71770         SOC_REG_FLAG_64_BITS,
  71771         0,
  71772         12,
  71773         soc_XMAC_TX_CTRL_BCM56640_A0r_fields,
  71774         SOC_RESET_VAL_DEC(0x0000c802, 0x00000010)
  71775         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  71776         -1,
  71777         -1,
  71778     },
  71779 #endif /* chips */
  71780 
  71781 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71782     { /* SOC_REG_INT_XMAC_TX_CTRL_BCM56440_A0r */
  71783         soc_block_list[83],
  71784         soc_portreg,
  71785         1,
  71786         0,
  71787         0x604,
  71788         SOC_REG_FLAG_64_BITS,
  71789         0,
  71790         12,
  71791         soc_XMAC_TX_CTRL_BCM56440_A0r_fields,
  71792         SOC_RESET_VAL_DEC(0x0000c802, 0x00000010)
  71793         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  71794         -1,
  71795         -1,
  71796     },
  71797 #endif /* chips */
  71798 
  71799 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71800     defined(BCM_56450_B1)
  71801     { /* SOC_REG_INT_XMAC_TX_CTRL_BCM56450_A0r */
  71802         soc_block_list[83],
  71803         soc_portreg,
  71804         1,
  71805         0,
  71806         0x40400,
  71807         SOC_REG_FLAG_64_BITS,
  71808         0,
  71809         12,
  71810         soc_XMAC_TX_CTRL_BCM56640_A0r_fields,
  71811         SOC_RESET_VAL_DEC(0x0000c802, 0x00000010)
  71812         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  71813         -1,
  71814         -1,
  71815     },
  71816 #endif /* chips */
  71817 
  71818 #if defined(BCM_56640_A0)
  71819     { /* SOC_REG_INT_XMAC_TX_CTRL_BCM56640_A0r */
  71820         soc_block_list[212],
  71821         soc_portreg,
  71822         1,
  71823         0,
  71824         0x60400,
  71825         SOC_REG_FLAG_64_BITS,
  71826         0,
  71827         12,
  71828         soc_XMAC_TX_CTRL_BCM56640_A0r_fields,
  71829         SOC_RESET_VAL_DEC(0x0000c802, 0x00000010)
  71830         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
  71831         -1,
  71832         -1,
  71833     },
  71834 #endif /* chips */
  71835 
  71836 #if defined(BCM_56840_B0)
  71837     { /* SOC_REG_INT_XMAC_TX_CTRL_BCM56840_B0r */
  71838         soc_block_list[16],
  71839         soc_portreg,
  71840         1,
  71841         0,
  71842         0x604,
  71843         SOC_REG_FLAG_64_BITS,
  71844         0,
  71845         8,
  71846         soc_XMAC_TX_CTRLr_fields,
  71847         SOC_RESET_VAL_DEC(0x0000c802, 0x00000000)
  71848         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  71849         -1,
  71850         -1,
  71851     },
  71852 #endif /* chips */
  71853 
  71854 #if defined(BCM_88732_A0)
  71855     { /* SOC_REG_INT_XMAC_TX_CTRL_BCM88732_A0r */
  71856         soc_block_list[16],
  71857         soc_portreg,
  71858         1,
  71859         0,
  71860         0x604,
  71861         SOC_REG_FLAG_64_BITS,
  71862         0,
  71863         8,
  71864         soc_XMAC_TX_CTRLr_fields,
  71865         SOC_RESET_VAL_DEC(0x0000c802, 0x00000000)
  71866         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  71867         -1,
  71868         -1,
  71869     },
  71870 #endif /* chips */
  71871 
  71872 #if defined(BCM_56840_A0)
  71873     { /* SOC_REG_INT_XMAC_TX_FIFO_CREDITSr */
  71874         soc_block_list[16],
  71875         soc_portreg,
  71876         1,
  71877         0,
  71878         0x61a,
  71879         SOC_REG_FLAG_64_BITS,
  71880         0,
  71881         3,
  71882         soc_XMAC_TX_FIFO_CREDITSr_fields,
  71883         SOC_RESET_VAL_DEC(0x00010308, 0x00000000)
  71884         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  71885         -1,
  71886         -1,
  71887     },
  71888 #endif /* chips */
  71889 
  71890 #if defined(BCM_56340_A0)
  71891     { /* SOC_REG_INT_XMAC_TX_FIFO_CREDITS_BCM56340_A0r */
  71892         soc_block_list[214],
  71893         soc_portreg,
  71894         1,
  71895         0,
  71896         0x61a00,
  71897         SOC_REG_FLAG_64_BITS,
  71898         0,
  71899         3,
  71900         soc_XMAC_TX_FIFO_CREDITS_BCM56640_A0r_fields,
  71901         SOC_RESET_VAL_DEC(0x00010308, 0x00000000)
  71902         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  71903         -1,
  71904         -1,
  71905     },
  71906 #endif /* chips */
  71907 
  71908 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  71909     { /* SOC_REG_INT_XMAC_TX_FIFO_CREDITS_BCM56440_A0r */
  71910         soc_block_list[83],
  71911         soc_portreg,
  71912         1,
  71913         0,
  71914         0x61a,
  71915         SOC_REG_FLAG_64_BITS,
  71916         0,
  71917         3,
  71918         soc_XMAC_TX_FIFO_CREDITSr_fields,
  71919         SOC_RESET_VAL_DEC(0x00010308, 0x00000000)
  71920         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  71921         -1,
  71922         -1,
  71923     },
  71924 #endif /* chips */
  71925 
  71926 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  71927     defined(BCM_56450_B1)
  71928     { /* SOC_REG_INT_XMAC_TX_FIFO_CREDITS_BCM56450_A0r */
  71929         soc_block_list[83],
  71930         soc_portreg,
  71931         1,
  71932         0,
  71933         0x41a00,
  71934         SOC_REG_FLAG_64_BITS,
  71935         0,
  71936         3,
  71937         soc_XMAC_TX_FIFO_CREDITS_BCM56640_A0r_fields,
  71938         SOC_RESET_VAL_DEC(0x00010308, 0x00000000)
  71939         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  71940         -1,
  71941         -1,
  71942     },
  71943 #endif /* chips */
  71944 
  71945 #if defined(BCM_56640_A0)
  71946     { /* SOC_REG_INT_XMAC_TX_FIFO_CREDITS_BCM56640_A0r */
  71947         soc_block_list[212],
  71948         soc_portreg,
  71949         1,
  71950         0,
  71951         0x61a00,
  71952         SOC_REG_FLAG_64_BITS,
  71953         0,
  71954         3,
  71955         soc_XMAC_TX_FIFO_CREDITS_BCM56640_A0r_fields,
  71956         SOC_RESET_VAL_DEC(0x00010308, 0x00000000)
  71957         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  71958         -1,
  71959         -1,
  71960     },
  71961 #endif /* chips */
  71962 
  71963 #if defined(BCM_56840_B0)
  71964     { /* SOC_REG_INT_XMAC_TX_FIFO_CREDITS_BCM56840_B0r */
  71965         soc_block_list[16],
  71966         soc_portreg,
  71967         1,
  71968         0,
  71969         0x61a,
  71970         SOC_REG_FLAG_64_BITS,
  71971         0,
  71972         3,
  71973         soc_XMAC_TX_FIFO_CREDITSr_fields,
  71974         SOC_RESET_VAL_DEC(0x00010308, 0x00000000)
  71975         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  71976         -1,
  71977         -1,
  71978     },
  71979 #endif /* chips */
  71980 
  71981 #if defined(BCM_88732_A0)
  71982     { /* SOC_REG_INT_XMAC_TX_FIFO_CREDITS_BCM88732_A0r */
  71983         soc_block_list[16],
  71984         soc_portreg,
  71985         1,
  71986         0,
  71987         0x61a,
  71988         SOC_REG_FLAG_64_BITS,
  71989         0,
  71990         3,
  71991         soc_XMAC_TX_FIFO_CREDITSr_fields,
  71992         SOC_RESET_VAL_DEC(0x00010308, 0x00000000)
  71993         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  71994         -1,
  71995         -1,
  71996     },
  71997 #endif /* chips */
  71998 
  71999 #if defined(BCM_56840_A0)
  72000     { /* SOC_REG_INT_XMAC_TX_LLFC_MSG_FIELDSr */
  72001         soc_block_list[16],
  72002         soc_portreg,
  72003         1,
  72004         0,
  72005         0x613,
  72006         SOC_REG_FLAG_64_BITS,
  72007         0,
  72008         3,
  72009         soc_XMAC_TX_LLFC_MSG_FIELDSr_fields,
  72010         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  72011         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  72012         -1,
  72013         -1,
  72014     },
  72015 #endif /* chips */
  72016 
  72017 #if defined(BCM_56340_A0)
  72018     { /* SOC_REG_INT_XMAC_TX_LLFC_MSG_FIELDS_BCM56340_A0r */
  72019         soc_block_list[214],
  72020         soc_portreg,
  72021         1,
  72022         0,
  72023         0x61300,
  72024         SOC_REG_FLAG_64_BITS,
  72025         0,
  72026         3,
  72027         soc_CMAC_TX_LLFC_MSG_FIELDSr_fields,
  72028         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  72029         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  72030         -1,
  72031         -1,
  72032     },
  72033 #endif /* chips */
  72034 
  72035 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72036     { /* SOC_REG_INT_XMAC_TX_LLFC_MSG_FIELDS_BCM56440_A0r */
  72037         soc_block_list[83],
  72038         soc_portreg,
  72039         1,
  72040         0,
  72041         0x613,
  72042         SOC_REG_FLAG_64_BITS,
  72043         0,
  72044         3,
  72045         soc_XMAC_TX_LLFC_MSG_FIELDSr_fields,
  72046         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  72047         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  72048         -1,
  72049         -1,
  72050     },
  72051 #endif /* chips */
  72052 
  72053 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72054     defined(BCM_56450_B1)
  72055     { /* SOC_REG_INT_XMAC_TX_LLFC_MSG_FIELDS_BCM56450_A0r */
  72056         soc_block_list[83],
  72057         soc_portreg,
  72058         1,
  72059         0,
  72060         0x41300,
  72061         SOC_REG_FLAG_64_BITS,
  72062         0,
  72063         3,
  72064         soc_CMAC_TX_LLFC_MSG_FIELDSr_fields,
  72065         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  72066         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  72067         -1,
  72068         -1,
  72069     },
  72070 #endif /* chips */
  72071 
  72072 #if defined(BCM_56640_A0)
  72073     { /* SOC_REG_INT_XMAC_TX_LLFC_MSG_FIELDS_BCM56640_A0r */
  72074         soc_block_list[212],
  72075         soc_portreg,
  72076         1,
  72077         0,
  72078         0x61300,
  72079         SOC_REG_FLAG_64_BITS,
  72080         0,
  72081         3,
  72082         soc_CMAC_TX_LLFC_MSG_FIELDSr_fields,
  72083         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  72084         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  72085         -1,
  72086         -1,
  72087     },
  72088 #endif /* chips */
  72089 
  72090 #if defined(BCM_56840_B0)
  72091     { /* SOC_REG_INT_XMAC_TX_LLFC_MSG_FIELDS_BCM56840_B0r */
  72092         soc_block_list[16],
  72093         soc_portreg,
  72094         1,
  72095         0,
  72096         0x613,
  72097         SOC_REG_FLAG_64_BITS,
  72098         0,
  72099         3,
  72100         soc_XMAC_TX_LLFC_MSG_FIELDSr_fields,
  72101         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  72102         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  72103         -1,
  72104         -1,
  72105     },
  72106 #endif /* chips */
  72107 
  72108 #if defined(BCM_88732_A0)
  72109     { /* SOC_REG_INT_XMAC_TX_LLFC_MSG_FIELDS_BCM88732_A0r */
  72110         soc_block_list[16],
  72111         soc_portreg,
  72112         1,
  72113         0,
  72114         0x613,
  72115         SOC_REG_FLAG_64_BITS,
  72116         0,
  72117         3,
  72118         soc_XMAC_TX_LLFC_MSG_FIELDSr_fields,
  72119         SOC_RESET_VAL_DEC(0x0ffff200, 0x00000000)
  72120         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  72121         -1,
  72122         -1,
  72123     },
  72124 #endif /* chips */
  72125 
  72126 #if defined(BCM_56840_A0)
  72127     { /* SOC_REG_INT_XMAC_TX_MAC_SAr */
  72128         soc_block_list[16],
  72129         soc_portreg,
  72130         1,
  72131         0,
  72132         0x605,
  72133         SOC_REG_FLAG_64_BITS,
  72134         0,
  72135         3,
  72136         soc_XMAC_TX_MAC_SAr_fields,
  72137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72138         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  72139         -1,
  72140         -1,
  72141     },
  72142 #endif /* chips */
  72143 
  72144 #if defined(BCM_56340_A0)
  72145     { /* SOC_REG_INT_XMAC_TX_MAC_SA_BCM56340_A0r */
  72146         soc_block_list[214],
  72147         soc_portreg,
  72148         1,
  72149         0,
  72150         0x60500,
  72151         SOC_REG_FLAG_64_BITS,
  72152         0,
  72153         3,
  72154         soc_CMAC_TX_MAC_SAr_fields,
  72155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72156         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  72157         -1,
  72158         -1,
  72159     },
  72160 #endif /* chips */
  72161 
  72162 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72163     { /* SOC_REG_INT_XMAC_TX_MAC_SA_BCM56440_A0r */
  72164         soc_block_list[83],
  72165         soc_portreg,
  72166         1,
  72167         0,
  72168         0x605,
  72169         SOC_REG_FLAG_64_BITS,
  72170         0,
  72171         3,
  72172         soc_XMAC_TX_MAC_SAr_fields,
  72173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72174         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  72175         -1,
  72176         -1,
  72177     },
  72178 #endif /* chips */
  72179 
  72180 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72181     defined(BCM_56450_B1)
  72182     { /* SOC_REG_INT_XMAC_TX_MAC_SA_BCM56450_A0r */
  72183         soc_block_list[83],
  72184         soc_portreg,
  72185         1,
  72186         0,
  72187         0x40500,
  72188         SOC_REG_FLAG_64_BITS,
  72189         0,
  72190         3,
  72191         soc_CMAC_TX_MAC_SAr_fields,
  72192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72193         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  72194         -1,
  72195         -1,
  72196     },
  72197 #endif /* chips */
  72198 
  72199 #if defined(BCM_56640_A0)
  72200     { /* SOC_REG_INT_XMAC_TX_MAC_SA_BCM56640_A0r */
  72201         soc_block_list[212],
  72202         soc_portreg,
  72203         1,
  72204         0,
  72205         0x60500,
  72206         SOC_REG_FLAG_64_BITS,
  72207         0,
  72208         3,
  72209         soc_CMAC_TX_MAC_SAr_fields,
  72210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72211         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  72212         -1,
  72213         -1,
  72214     },
  72215 #endif /* chips */
  72216 
  72217 #if defined(BCM_56840_B0)
  72218     { /* SOC_REG_INT_XMAC_TX_MAC_SA_BCM56840_B0r */
  72219         soc_block_list[16],
  72220         soc_portreg,
  72221         1,
  72222         0,
  72223         0x605,
  72224         SOC_REG_FLAG_64_BITS,
  72225         0,
  72226         3,
  72227         soc_XMAC_TX_MAC_SAr_fields,
  72228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72229         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  72230         -1,
  72231         -1,
  72232     },
  72233 #endif /* chips */
  72234 
  72235 #if defined(BCM_88732_A0)
  72236     { /* SOC_REG_INT_XMAC_TX_MAC_SA_BCM88732_A0r */
  72237         soc_block_list[16],
  72238         soc_portreg,
  72239         1,
  72240         0,
  72241         0x605,
  72242         SOC_REG_FLAG_64_BITS,
  72243         0,
  72244         3,
  72245         soc_XMAC_TX_MAC_SAr_fields,
  72246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72247         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  72248         -1,
  72249         -1,
  72250     },
  72251 #endif /* chips */
  72252 
  72253 #if defined(BCM_56840_A0)
  72254     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_DATAr */
  72255         soc_block_list[16],
  72256         soc_portreg,
  72257         1,
  72258         0,
  72259         0x616,
  72260         SOC_REG_FLAG_64_BITS |
  72261                           SOC_REG_FLAG_RO,
  72262         0,
  72263         1,
  72264         soc_XMAC_TX_TIMESTAMP_FIFO_DATAr_fields,
  72265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72266         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72267         -1,
  72268         -1,
  72269     },
  72270 #endif /* chips */
  72271 
  72272 #if defined(BCM_56340_A0)
  72273     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM56340_A0r */
  72274         soc_block_list[214],
  72275         soc_portreg,
  72276         1,
  72277         0,
  72278         0x61600,
  72279         SOC_REG_FLAG_64_BITS |
  72280                           SOC_REG_FLAG_RO,
  72281         0,
  72282         3,
  72283         soc_CMAC_TX_TIMESTAMP_FIFO_DATAr_fields,
  72284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72285         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  72286         -1,
  72287         -1,
  72288     },
  72289 #endif /* chips */
  72290 
  72291 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72292     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM56440_A0r */
  72293         soc_block_list[83],
  72294         soc_portreg,
  72295         1,
  72296         0,
  72297         0x616,
  72298         SOC_REG_FLAG_64_BITS |
  72299                           SOC_REG_FLAG_RO,
  72300         0,
  72301         3,
  72302         soc_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM56440_A0r_fields,
  72303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72304         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  72305         -1,
  72306         -1,
  72307     },
  72308 #endif /* chips */
  72309 
  72310 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72311     defined(BCM_56450_B1)
  72312     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM56450_A0r */
  72313         soc_block_list[83],
  72314         soc_portreg,
  72315         1,
  72316         0,
  72317         0x41600,
  72318         SOC_REG_FLAG_64_BITS |
  72319                           SOC_REG_FLAG_RO,
  72320         0,
  72321         3,
  72322         soc_CMAC_TX_TIMESTAMP_FIFO_DATAr_fields,
  72323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72324         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  72325         -1,
  72326         -1,
  72327     },
  72328 #endif /* chips */
  72329 
  72330 #if defined(BCM_56640_A0)
  72331     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM56640_A0r */
  72332         soc_block_list[212],
  72333         soc_portreg,
  72334         1,
  72335         0,
  72336         0x61600,
  72337         SOC_REG_FLAG_64_BITS |
  72338                           SOC_REG_FLAG_RO,
  72339         0,
  72340         3,
  72341         soc_CMAC_TX_TIMESTAMP_FIFO_DATAr_fields,
  72342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72343         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
  72344         -1,
  72345         -1,
  72346     },
  72347 #endif /* chips */
  72348 
  72349 #if defined(BCM_56840_B0)
  72350     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM56840_B0r */
  72351         soc_block_list[16],
  72352         soc_portreg,
  72353         1,
  72354         0,
  72355         0x616,
  72356         SOC_REG_FLAG_64_BITS |
  72357                           SOC_REG_FLAG_RO,
  72358         0,
  72359         1,
  72360         soc_XMAC_TX_TIMESTAMP_FIFO_DATAr_fields,
  72361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72362         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72363         -1,
  72364         -1,
  72365     },
  72366 #endif /* chips */
  72367 
  72368 #if defined(BCM_88732_A0)
  72369     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM88732_A0r */
  72370         soc_block_list[16],
  72371         soc_portreg,
  72372         1,
  72373         0,
  72374         0x616,
  72375         SOC_REG_FLAG_64_BITS |
  72376                           SOC_REG_FLAG_RO,
  72377         0,
  72378         1,
  72379         soc_XMAC_TX_TIMESTAMP_FIFO_DATAr_fields,
  72380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72382         -1,
  72383         -1,
  72384     },
  72385 #endif /* chips */
  72386 
  72387 #if defined(BCM_56840_A0)
  72388     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_STATUSr */
  72389         soc_block_list[16],
  72390         soc_portreg,
  72391         1,
  72392         0,
  72393         0x617,
  72394         SOC_REG_FLAG_64_BITS |
  72395                           SOC_REG_FLAG_RO,
  72396         0,
  72397         1,
  72398         soc_XMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  72399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72400         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  72401         -1,
  72402         -1,
  72403     },
  72404 #endif /* chips */
  72405 
  72406 #if defined(BCM_56340_A0)
  72407     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56340_A0r */
  72408         soc_block_list[214],
  72409         soc_portreg,
  72410         1,
  72411         0,
  72412         0x61700,
  72413         SOC_REG_FLAG_64_BITS |
  72414                           SOC_REG_FLAG_RO,
  72415         0,
  72416         1,
  72417         soc_CMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  72418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72419         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  72420         -1,
  72421         -1,
  72422     },
  72423 #endif /* chips */
  72424 
  72425 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72426     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56440_A0r */
  72427         soc_block_list[83],
  72428         soc_portreg,
  72429         1,
  72430         0,
  72431         0x617,
  72432         SOC_REG_FLAG_64_BITS |
  72433                           SOC_REG_FLAG_RO,
  72434         0,
  72435         1,
  72436         soc_XMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  72437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72438         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  72439         -1,
  72440         -1,
  72441     },
  72442 #endif /* chips */
  72443 
  72444 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72445     defined(BCM_56450_B1)
  72446     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56450_A0r */
  72447         soc_block_list[83],
  72448         soc_portreg,
  72449         1,
  72450         0,
  72451         0x41700,
  72452         SOC_REG_FLAG_64_BITS |
  72453                           SOC_REG_FLAG_RO,
  72454         0,
  72455         1,
  72456         soc_CMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  72457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72458         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  72459         -1,
  72460         -1,
  72461     },
  72462 #endif /* chips */
  72463 
  72464 #if defined(BCM_56640_A0)
  72465     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56640_A0r */
  72466         soc_block_list[212],
  72467         soc_portreg,
  72468         1,
  72469         0,
  72470         0x61700,
  72471         SOC_REG_FLAG_64_BITS |
  72472                           SOC_REG_FLAG_RO,
  72473         0,
  72474         1,
  72475         soc_CMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  72476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72477         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  72478         -1,
  72479         -1,
  72480     },
  72481 #endif /* chips */
  72482 
  72483 #if defined(BCM_56840_B0)
  72484     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM56840_B0r */
  72485         soc_block_list[16],
  72486         soc_portreg,
  72487         1,
  72488         0,
  72489         0x617,
  72490         SOC_REG_FLAG_64_BITS |
  72491                           SOC_REG_FLAG_RO,
  72492         0,
  72493         1,
  72494         soc_XMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  72495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72496         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  72497         -1,
  72498         -1,
  72499     },
  72500 #endif /* chips */
  72501 
  72502 #if defined(BCM_88732_A0)
  72503     { /* SOC_REG_INT_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88732_A0r */
  72504         soc_block_list[16],
  72505         soc_portreg,
  72506         1,
  72507         0,
  72508         0x617,
  72509         SOC_REG_FLAG_64_BITS |
  72510                           SOC_REG_FLAG_RO,
  72511         0,
  72512         1,
  72513         soc_XMAC_TX_TIMESTAMP_FIFO_STATUSr_fields,
  72514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72515         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  72516         -1,
  72517         -1,
  72518     },
  72519 #endif /* chips */
  72520 
  72521 #if defined(BCM_56640_A0)
  72522     { /* SOC_REG_INT_XMAC_VERSION_IDr */
  72523         soc_block_list[212],
  72524         soc_portreg,
  72525         1,
  72526         0,
  72527         0x62600,
  72528         SOC_REG_FLAG_64_BITS |
  72529                           SOC_REG_FLAG_RO,
  72530         0,
  72531         1,
  72532         soc_XMAC_VERSION_IDr_fields,
  72533         SOC_RESET_VAL_DEC(0x0000b019, 0x00000000)
  72534         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72535         -1,
  72536         -1,
  72537     },
  72538 #endif /* chips */
  72539 
  72540 #if defined(BCM_56340_A0)
  72541     { /* SOC_REG_INT_XMAC_VERSION_ID_BCM56340_A0r */
  72542         soc_block_list[214],
  72543         soc_portreg,
  72544         1,
  72545         0,
  72546         0x62600,
  72547         SOC_REG_FLAG_64_BITS |
  72548                           SOC_REG_FLAG_RO,
  72549         0,
  72550         1,
  72551         soc_XMAC_VERSION_ID_BCM56340_A0r_fields,
  72552         SOC_RESET_VAL_DEC(0x0000b020, 0x00000000)
  72553         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72554         -1,
  72555         -1,
  72556     },
  72557 #endif /* chips */
  72558 
  72559 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72560     defined(BCM_56450_B1)
  72561     { /* SOC_REG_INT_XMAC_VERSION_ID_BCM56450_A0r */
  72562         soc_block_list[83],
  72563         soc_portreg,
  72564         1,
  72565         0,
  72566         0x42600,
  72567         SOC_REG_FLAG_64_BITS |
  72568                           SOC_REG_FLAG_RO,
  72569         0,
  72570         1,
  72571         soc_XMAC_VERSION_ID_BCM56450_A0r_fields,
  72572         SOC_RESET_VAL_DEC(0x0000b021, 0x00000000)
  72573         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  72574         -1,
  72575         -1,
  72576     },
  72577 #endif /* chips */
  72578 
  72579 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  72580     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  72581     { /* SOC_REG_INT_XMODIDr */
  72582         soc_block_list[204],
  72583         soc_portreg,
  72584         1,
  72585         0,
  72586         0x827,
  72587         0,
  72588         0,
  72589         4,
  72590         soc_XMODIDr_fields,
  72591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72592         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72593         -1,
  72594         -1,
  72595     },
  72596 #endif /* chips */
  72597 
  72598 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  72599     defined(BCM_56334_B0)
  72600     { /* SOC_REG_INT_XMODID_BCM56334_A0r */
  72601         soc_block_list[14],
  72602         soc_portreg,
  72603         1,
  72604         0,
  72605         0x827,
  72606         0,
  72607         0,
  72608         4,
  72609         soc_XMODIDr_fields,
  72610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72611         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72612         -1,
  72613         -1,
  72614     },
  72615 #endif /* chips */
  72616 
  72617 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72618     { /* SOC_REG_INT_XMODID_BCM56440_A0r */
  72619         soc_block_list[83],
  72620         soc_genreg,
  72621         1,
  72622         0,
  72623         0x80235,
  72624         0,
  72625         0,
  72626         4,
  72627         soc_XMODIDr_fields,
  72628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72629         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72630         -1,
  72631         -1,
  72632     },
  72633 #endif /* chips */
  72634 
  72635 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72636     defined(BCM_56450_B1)
  72637     { /* SOC_REG_INT_XMODID_BCM56450_A0r */
  72638         soc_block_list[83],
  72639         soc_genreg,
  72640         1,
  72641         0,
  72642         0x2023500,
  72643         0,
  72644         0,
  72645         4,
  72646         soc_XMODID_BCM56450_A0r_fields,
  72647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72648         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72649         -1,
  72650         -1,
  72651     },
  72652 #endif /* chips */
  72653 
  72654 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  72655     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  72656     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  72657     { /* SOC_REG_INT_XMODID_BCM56634_A0r */
  72658         soc_block_list[208],
  72659         soc_portreg,
  72660         1,
  72661         0,
  72662         0x827,
  72663         0,
  72664         0,
  72665         4,
  72666         soc_XMODIDr_fields,
  72667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72668         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72669         -1,
  72670         -1,
  72671     },
  72672 #endif /* chips */
  72673 
  72674 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  72675     { /* SOC_REG_INT_XMODID_BCM56820_A0r */
  72676         soc_block_list[9],
  72677         soc_portreg,
  72678         1,
  72679         0,
  72680         0x827,
  72681         0,
  72682         0,
  72683         4,
  72684         soc_XMODIDr_fields,
  72685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72686         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72687         -1,
  72688         -1,
  72689     },
  72690 #endif /* chips */
  72691 
  72692 #if defined(BCM_56840_A0)
  72693     { /* SOC_REG_INT_XMODID_BCM56840_A0r */
  72694         soc_block_list[16],
  72695         soc_portreg,
  72696         1,
  72697         0,
  72698         0x21e,
  72699         0,
  72700         0,
  72701         4,
  72702         soc_XMODID_BCM56840_A0r_fields,
  72703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72704         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72705         -1,
  72706         -1,
  72707     },
  72708 #endif /* chips */
  72709 
  72710 #if defined(BCM_56840_B0)
  72711     { /* SOC_REG_INT_XMODID_BCM56840_B0r */
  72712         soc_block_list[16],
  72713         soc_portreg,
  72714         1,
  72715         0,
  72716         0x21e,
  72717         0,
  72718         0,
  72719         4,
  72720         soc_XMODID_BCM56840_A0r_fields,
  72721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72722         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72723         -1,
  72724         -1,
  72725     },
  72726 #endif /* chips */
  72727 
  72728 #if defined(BCM_88732_A0)
  72729     { /* SOC_REG_INT_XMODID_BCM88732_A0r */
  72730         soc_block_list[16],
  72731         soc_portreg,
  72732         1,
  72733         0,
  72734         0x21e,
  72735         0,
  72736         0,
  72737         4,
  72738         soc_XMODID_BCM56840_A0r_fields,
  72739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72740         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72741         -1,
  72742         -1,
  72743     },
  72744 #endif /* chips */
  72745 
  72746 #if defined(BCM_56840_A0)
  72747     { /* SOC_REG_INT_XMODID_DUAL_ENr */
  72748         soc_block_list[16],
  72749         soc_portreg,
  72750         1,
  72751         0,
  72752         0x220,
  72753         0,
  72754         0,
  72755         1,
  72756         soc_E2EFC_CONFIGr_fields,
  72757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72758         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  72759         -1,
  72760         -1,
  72761     },
  72762 #endif /* chips */
  72763 
  72764 #if defined(BCM_56340_A0)
  72765     { /* SOC_REG_INT_XMODID_DUAL_EN_BCM56340_A0r */
  72766         soc_block_list[214],
  72767         soc_portreg,
  72768         1,
  72769         0,
  72770         0x22b00,
  72771         0,
  72772         0,
  72773         1,
  72774         soc_E2EFC_CONFIG_BCM56640_A0r_fields,
  72775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72776         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  72777         -1,
  72778         -1,
  72779     },
  72780 #endif /* chips */
  72781 
  72782 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72783     { /* SOC_REG_INT_XMODID_DUAL_EN_BCM56440_A0r */
  72784         soc_block_list[83],
  72785         soc_genreg,
  72786         1,
  72787         0,
  72788         0x80237,
  72789         0,
  72790         0,
  72791         1,
  72792         soc_E2EFC_CONFIGr_fields,
  72793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72794         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  72795         -1,
  72796         -1,
  72797     },
  72798 #endif /* chips */
  72799 
  72800 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72801     defined(BCM_56450_B1)
  72802     { /* SOC_REG_INT_XMODID_DUAL_EN_BCM56450_A0r */
  72803         soc_block_list[83],
  72804         soc_genreg,
  72805         1,
  72806         0,
  72807         0x2023700,
  72808         0,
  72809         0,
  72810         1,
  72811         soc_E2EFC_CONFIG_BCM56640_A0r_fields,
  72812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72813         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  72814         -1,
  72815         -1,
  72816     },
  72817 #endif /* chips */
  72818 
  72819 #if defined(BCM_56640_A0)
  72820     { /* SOC_REG_INT_XMODID_DUAL_EN_BCM56640_A0r */
  72821         soc_block_list[212],
  72822         soc_portreg,
  72823         1,
  72824         0,
  72825         0x22b00,
  72826         0,
  72827         0,
  72828         1,
  72829         soc_E2EFC_CONFIG_BCM56640_A0r_fields,
  72830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72831         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  72832         -1,
  72833         -1,
  72834     },
  72835 #endif /* chips */
  72836 
  72837 #if defined(BCM_56840_B0)
  72838     { /* SOC_REG_INT_XMODID_DUAL_EN_BCM56840_B0r */
  72839         soc_block_list[16],
  72840         soc_portreg,
  72841         1,
  72842         0,
  72843         0x220,
  72844         0,
  72845         0,
  72846         1,
  72847         soc_E2EFC_CONFIGr_fields,
  72848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72849         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  72850         -1,
  72851         -1,
  72852     },
  72853 #endif /* chips */
  72854 
  72855 #if defined(BCM_88732_A0)
  72856     { /* SOC_REG_INT_XMODID_DUAL_EN_BCM88732_A0r */
  72857         soc_block_list[16],
  72858         soc_portreg,
  72859         1,
  72860         0,
  72861         0x220,
  72862         0,
  72863         0,
  72864         1,
  72865         soc_E2EFC_CONFIGr_fields,
  72866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72867         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  72868         -1,
  72869         -1,
  72870     },
  72871 #endif /* chips */
  72872 
  72873 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  72874     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  72875     { /* SOC_REG_INT_XMODID_ENr */
  72876         soc_block_list[204],
  72877         soc_portreg,
  72878         1,
  72879         0,
  72880         0x828,
  72881         0,
  72882         0,
  72883         5,
  72884         soc_XMODID_ENr_fields,
  72885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72886         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  72887         -1,
  72888         -1,
  72889     },
  72890 #endif /* chips */
  72891 
  72892 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  72893     defined(BCM_56334_B0)
  72894     { /* SOC_REG_INT_XMODID_EN_BCM56334_A0r */
  72895         soc_block_list[14],
  72896         soc_portreg,
  72897         1,
  72898         0,
  72899         0x828,
  72900         0,
  72901         0,
  72902         5,
  72903         soc_XMODID_ENr_fields,
  72904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72905         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  72906         -1,
  72907         -1,
  72908     },
  72909 #endif /* chips */
  72910 
  72911 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  72912     { /* SOC_REG_INT_XMODID_EN_BCM56440_A0r */
  72913         soc_block_list[83],
  72914         soc_genreg,
  72915         1,
  72916         0,
  72917         0x80236,
  72918         0,
  72919         0,
  72920         4,
  72921         soc_XMODID_EN_BCM56440_A0r_fields,
  72922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72923         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  72924         -1,
  72925         -1,
  72926     },
  72927 #endif /* chips */
  72928 
  72929 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  72930     defined(BCM_56450_B1)
  72931     { /* SOC_REG_INT_XMODID_EN_BCM56450_A0r */
  72932         soc_block_list[83],
  72933         soc_genreg,
  72934         1,
  72935         0,
  72936         0x2023600,
  72937         0,
  72938         0,
  72939         4,
  72940         soc_XMODID_EN_BCM56450_A0r_fields,
  72941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72942         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  72943         -1,
  72944         -1,
  72945     },
  72946 #endif /* chips */
  72947 
  72948 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  72949     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  72950     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  72951     { /* SOC_REG_INT_XMODID_EN_BCM56634_A0r */
  72952         soc_block_list[208],
  72953         soc_portreg,
  72954         1,
  72955         0,
  72956         0x828,
  72957         0,
  72958         0,
  72959         5,
  72960         soc_XMODID_ENr_fields,
  72961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72962         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  72963         -1,
  72964         -1,
  72965     },
  72966 #endif /* chips */
  72967 
  72968 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  72969     { /* SOC_REG_INT_XMODID_EN_BCM56820_A0r */
  72970         soc_block_list[9],
  72971         soc_portreg,
  72972         1,
  72973         0,
  72974         0x828,
  72975         0,
  72976         0,
  72977         5,
  72978         soc_XMODID_ENr_fields,
  72979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72980         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  72981         -1,
  72982         -1,
  72983     },
  72984 #endif /* chips */
  72985 
  72986 #if defined(BCM_56840_A0)
  72987     { /* SOC_REG_INT_XMODID_EN_BCM56840_A0r */
  72988         soc_block_list[16],
  72989         soc_portreg,
  72990         1,
  72991         0,
  72992         0x21f,
  72993         0,
  72994         0,
  72995         4,
  72996         soc_XMODID_EN_BCM56840_A0r_fields,
  72997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72998         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  72999         -1,
  73000         -1,
  73001     },
  73002 #endif /* chips */
  73003 
  73004 #if defined(BCM_56840_B0)
  73005     { /* SOC_REG_INT_XMODID_EN_BCM56840_B0r */
  73006         soc_block_list[16],
  73007         soc_portreg,
  73008         1,
  73009         0,
  73010         0x21f,
  73011         0,
  73012         0,
  73013         4,
  73014         soc_XMODID_EN_BCM56840_A0r_fields,
  73015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73016         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  73017         -1,
  73018         -1,
  73019     },
  73020 #endif /* chips */
  73021 
  73022 #if defined(BCM_88732_A0)
  73023     { /* SOC_REG_INT_XMODID_EN_BCM88732_A0r */
  73024         soc_block_list[16],
  73025         soc_portreg,
  73026         1,
  73027         0,
  73028         0x21f,
  73029         0,
  73030         0,
  73031         4,
  73032         soc_XMODID_EN_BCM56840_A0r_fields,
  73033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73034         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  73035         -1,
  73036         -1,
  73037     },
  73038 #endif /* chips */
  73039 
  73040 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  73041     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  73042     { /* SOC_REG_INT_XPAUSE_D0r */
  73043         soc_block_list[0],
  73044         soc_genreg,
  73045         1,
  73046         0,
  73047         0x80007,
  73048         0,
  73049         0,
  73050         1,
  73051         soc_XPAUSE_D0r_fields,
  73052         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73053         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73054         -1,
  73055         -1,
  73056     },
  73057 #endif /* chips */
  73058 
  73059 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  73060     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  73061     { /* SOC_REG_INT_XPAUSE_D1r */
  73062         soc_block_list[0],
  73063         soc_genreg,
  73064         1,
  73065         0,
  73066         0x80008,
  73067         0,
  73068         0,
  73069         1,
  73070         soc_XPAUSE_D1r_fields,
  73071         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73072         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73073         -1,
  73074         -1,
  73075     },
  73076 #endif /* chips */
  73077 
  73078 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  73079     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  73080     { /* SOC_REG_INT_XPAUSE_D2r */
  73081         soc_block_list[0],
  73082         soc_genreg,
  73083         1,
  73084         0,
  73085         0x80009,
  73086         0,
  73087         0,
  73088         1,
  73089         soc_XPAUSE_D2r_fields,
  73090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73091         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73092         -1,
  73093         -1,
  73094     },
  73095 #endif /* chips */
  73096 
  73097 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  73098     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  73099     { /* SOC_REG_INT_XPAUSE_D3r */
  73100         soc_block_list[0],
  73101         soc_genreg,
  73102         1,
  73103         0,
  73104         0x8000a,
  73105         0,
  73106         0,
  73107         1,
  73108         soc_XPAUSE_D3r_fields,
  73109         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73110         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73111         -1,
  73112         -1,
  73113     },
  73114 #endif /* chips */
  73115 
  73116 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  73117     defined(BCM_56334_B0)
  73118     { /* SOC_REG_INT_XPAUSE_D0_BCM56334_A0r */
  73119         soc_block_list[14],
  73120         soc_portreg,
  73121         1,
  73122         0,
  73123         0x808,
  73124         0,
  73125         0,
  73126         1,
  73127         soc_XPAUSE_D0r_fields,
  73128         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73129         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73130         -1,
  73131         -1,
  73132     },
  73133 #endif /* chips */
  73134 
  73135 #if defined(BCM_56340_A0)
  73136     { /* SOC_REG_INT_XPAUSE_D0_BCM56340_A0r */
  73137         soc_block_list[214],
  73138         soc_portreg,
  73139         1,
  73140         0,
  73141         0x20800,
  73142         0,
  73143         0,
  73144         1,
  73145         soc_XPAUSE_D0_BCM56640_A0r_fields,
  73146         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73147         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73148         -1,
  73149         -1,
  73150     },
  73151 #endif /* chips */
  73152 
  73153 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  73154     { /* SOC_REG_INT_XPAUSE_D0_BCM56440_A0r */
  73155         soc_block_list[83],
  73156         soc_portreg,
  73157         1,
  73158         0,
  73159         0x208,
  73160         0,
  73161         0,
  73162         1,
  73163         soc_XPAUSE_D0r_fields,
  73164         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73165         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73166         -1,
  73167         -1,
  73168     },
  73169 #endif /* chips */
  73170 
  73171 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73172     defined(BCM_56450_B1)
  73173     { /* SOC_REG_INT_XPAUSE_D0_BCM56450_A0r */
  73174         soc_block_list[83],
  73175         soc_portreg,
  73176         1,
  73177         0,
  73178         0x20800,
  73179         0,
  73180         0,
  73181         1,
  73182         soc_XPAUSE_D0_BCM56640_A0r_fields,
  73183         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73184         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73185         -1,
  73186         -1,
  73187     },
  73188 #endif /* chips */
  73189 
  73190 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  73191     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  73192     { /* SOC_REG_INT_XPAUSE_D0_BCM56624_A0r */
  73193         soc_block_list[204],
  73194         soc_portreg,
  73195         1,
  73196         0,
  73197         0x808,
  73198         0,
  73199         0,
  73200         1,
  73201         soc_XPAUSE_D0r_fields,
  73202         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73203         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73204         -1,
  73205         -1,
  73206     },
  73207 #endif /* chips */
  73208 
  73209 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  73210     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  73211     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  73212     { /* SOC_REG_INT_XPAUSE_D0_BCM56634_A0r */
  73213         soc_block_list[208],
  73214         soc_portreg,
  73215         1,
  73216         0,
  73217         0x808,
  73218         0,
  73219         0,
  73220         1,
  73221         soc_XPAUSE_D0r_fields,
  73222         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73223         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73224         -1,
  73225         -1,
  73226     },
  73227 #endif /* chips */
  73228 
  73229 #if defined(BCM_56640_A0)
  73230     { /* SOC_REG_INT_XPAUSE_D0_BCM56640_A0r */
  73231         soc_block_list[212],
  73232         soc_portreg,
  73233         1,
  73234         0,
  73235         0x20800,
  73236         0,
  73237         0,
  73238         1,
  73239         soc_XPAUSE_D0_BCM56640_A0r_fields,
  73240         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73241         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73242         -1,
  73243         -1,
  73244     },
  73245 #endif /* chips */
  73246 
  73247 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  73248     defined(BCM_56820_A0)
  73249     { /* SOC_REG_INT_XPAUSE_D0_BCM56800_A0r */
  73250         soc_block_list[9],
  73251         soc_portreg,
  73252         1,
  73253         0,
  73254         0x808,
  73255         0,
  73256         0,
  73257         1,
  73258         soc_XPAUSE_D0r_fields,
  73259         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73260         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73261         -1,
  73262         -1,
  73263     },
  73264 #endif /* chips */
  73265 
  73266 #if defined(BCM_56840_A0)
  73267     { /* SOC_REG_INT_XPAUSE_D0_BCM56840_A0r */
  73268         soc_block_list[16],
  73269         soc_portreg,
  73270         1,
  73271         0,
  73272         0x208,
  73273         0,
  73274         0,
  73275         1,
  73276         soc_XPAUSE_D0r_fields,
  73277         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73278         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73279         -1,
  73280         -1,
  73281     },
  73282 #endif /* chips */
  73283 
  73284 #if defined(BCM_56840_B0)
  73285     { /* SOC_REG_INT_XPAUSE_D0_BCM56840_B0r */
  73286         soc_block_list[16],
  73287         soc_portreg,
  73288         1,
  73289         0,
  73290         0x208,
  73291         0,
  73292         0,
  73293         1,
  73294         soc_XPAUSE_D0r_fields,
  73295         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73296         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73297         -1,
  73298         -1,
  73299     },
  73300 #endif /* chips */
  73301 
  73302 #if defined(BCM_88732_A0)
  73303     { /* SOC_REG_INT_XPAUSE_D0_BCM88732_A0r */
  73304         soc_block_list[16],
  73305         soc_portreg,
  73306         1,
  73307         0,
  73308         0x208,
  73309         0,
  73310         0,
  73311         1,
  73312         soc_XPAUSE_D0r_fields,
  73313         SOC_RESET_VAL_DEC(0x0180c200, 0x00000000)
  73314         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73315         -1,
  73316         -1,
  73317     },
  73318 #endif /* chips */
  73319 
  73320 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  73321     defined(BCM_56334_B0)
  73322     { /* SOC_REG_INT_XPAUSE_D1_BCM56334_A0r */
  73323         soc_block_list[14],
  73324         soc_portreg,
  73325         1,
  73326         0,
  73327         0x809,
  73328         0,
  73329         0,
  73330         1,
  73331         soc_XPAUSE_D1r_fields,
  73332         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73333         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73334         -1,
  73335         -1,
  73336     },
  73337 #endif /* chips */
  73338 
  73339 #if defined(BCM_56340_A0)
  73340     { /* SOC_REG_INT_XPAUSE_D1_BCM56340_A0r */
  73341         soc_block_list[214],
  73342         soc_portreg,
  73343         1,
  73344         0,
  73345         0x20900,
  73346         0,
  73347         0,
  73348         1,
  73349         soc_XPAUSE_D1_BCM56640_A0r_fields,
  73350         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73351         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73352         -1,
  73353         -1,
  73354     },
  73355 #endif /* chips */
  73356 
  73357 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  73358     { /* SOC_REG_INT_XPAUSE_D1_BCM56440_A0r */
  73359         soc_block_list[83],
  73360         soc_portreg,
  73361         1,
  73362         0,
  73363         0x209,
  73364         0,
  73365         0,
  73366         1,
  73367         soc_XPAUSE_D1r_fields,
  73368         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73369         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73370         -1,
  73371         -1,
  73372     },
  73373 #endif /* chips */
  73374 
  73375 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73376     defined(BCM_56450_B1)
  73377     { /* SOC_REG_INT_XPAUSE_D1_BCM56450_A0r */
  73378         soc_block_list[83],
  73379         soc_portreg,
  73380         1,
  73381         0,
  73382         0x20900,
  73383         0,
  73384         0,
  73385         1,
  73386         soc_XPAUSE_D1_BCM56640_A0r_fields,
  73387         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73388         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73389         -1,
  73390         -1,
  73391     },
  73392 #endif /* chips */
  73393 
  73394 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  73395     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  73396     { /* SOC_REG_INT_XPAUSE_D1_BCM56624_A0r */
  73397         soc_block_list[204],
  73398         soc_portreg,
  73399         1,
  73400         0,
  73401         0x809,
  73402         0,
  73403         0,
  73404         1,
  73405         soc_XPAUSE_D1r_fields,
  73406         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73407         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73408         -1,
  73409         -1,
  73410     },
  73411 #endif /* chips */
  73412 
  73413 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  73414     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  73415     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  73416     { /* SOC_REG_INT_XPAUSE_D1_BCM56634_A0r */
  73417         soc_block_list[208],
  73418         soc_portreg,
  73419         1,
  73420         0,
  73421         0x809,
  73422         0,
  73423         0,
  73424         1,
  73425         soc_XPAUSE_D1r_fields,
  73426         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73428         -1,
  73429         -1,
  73430     },
  73431 #endif /* chips */
  73432 
  73433 #if defined(BCM_56640_A0)
  73434     { /* SOC_REG_INT_XPAUSE_D1_BCM56640_A0r */
  73435         soc_block_list[212],
  73436         soc_portreg,
  73437         1,
  73438         0,
  73439         0x20900,
  73440         0,
  73441         0,
  73442         1,
  73443         soc_XPAUSE_D1_BCM56640_A0r_fields,
  73444         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73446         -1,
  73447         -1,
  73448     },
  73449 #endif /* chips */
  73450 
  73451 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  73452     defined(BCM_56820_A0)
  73453     { /* SOC_REG_INT_XPAUSE_D1_BCM56800_A0r */
  73454         soc_block_list[9],
  73455         soc_portreg,
  73456         1,
  73457         0,
  73458         0x809,
  73459         0,
  73460         0,
  73461         1,
  73462         soc_XPAUSE_D1r_fields,
  73463         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73464         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73465         -1,
  73466         -1,
  73467     },
  73468 #endif /* chips */
  73469 
  73470 #if defined(BCM_56840_A0)
  73471     { /* SOC_REG_INT_XPAUSE_D1_BCM56840_A0r */
  73472         soc_block_list[16],
  73473         soc_portreg,
  73474         1,
  73475         0,
  73476         0x209,
  73477         0,
  73478         0,
  73479         1,
  73480         soc_XPAUSE_D1r_fields,
  73481         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73482         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73483         -1,
  73484         -1,
  73485     },
  73486 #endif /* chips */
  73487 
  73488 #if defined(BCM_56840_B0)
  73489     { /* SOC_REG_INT_XPAUSE_D1_BCM56840_B0r */
  73490         soc_block_list[16],
  73491         soc_portreg,
  73492         1,
  73493         0,
  73494         0x209,
  73495         0,
  73496         0,
  73497         1,
  73498         soc_XPAUSE_D1r_fields,
  73499         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73500         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73501         -1,
  73502         -1,
  73503     },
  73504 #endif /* chips */
  73505 
  73506 #if defined(BCM_88732_A0)
  73507     { /* SOC_REG_INT_XPAUSE_D1_BCM88732_A0r */
  73508         soc_block_list[16],
  73509         soc_portreg,
  73510         1,
  73511         0,
  73512         0x209,
  73513         0,
  73514         0,
  73515         1,
  73516         soc_XPAUSE_D1r_fields,
  73517         SOC_RESET_VAL_DEC(0x00010000, 0x00000000)
  73518         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73519         -1,
  73520         -1,
  73521     },
  73522 #endif /* chips */
  73523 
  73524 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  73525     defined(BCM_56334_B0)
  73526     { /* SOC_REG_INT_XPAUSE_D2_BCM56334_A0r */
  73527         soc_block_list[14],
  73528         soc_portreg,
  73529         1,
  73530         0,
  73531         0x80a,
  73532         0,
  73533         0,
  73534         1,
  73535         soc_XPAUSE_D2r_fields,
  73536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73537         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73538         -1,
  73539         -1,
  73540     },
  73541 #endif /* chips */
  73542 
  73543 #if defined(BCM_56340_A0)
  73544     { /* SOC_REG_INT_XPAUSE_D2_BCM56340_A0r */
  73545         soc_block_list[214],
  73546         soc_portreg,
  73547         1,
  73548         0,
  73549         0x20a00,
  73550         0,
  73551         0,
  73552         1,
  73553         soc_XPAUSE_D2_BCM56640_A0r_fields,
  73554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73555         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73556         -1,
  73557         -1,
  73558     },
  73559 #endif /* chips */
  73560 
  73561 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  73562     { /* SOC_REG_INT_XPAUSE_D2_BCM56440_A0r */
  73563         soc_block_list[83],
  73564         soc_portreg,
  73565         1,
  73566         0,
  73567         0x20a,
  73568         0,
  73569         0,
  73570         1,
  73571         soc_XPAUSE_D2r_fields,
  73572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73573         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73574         -1,
  73575         -1,
  73576     },
  73577 #endif /* chips */
  73578 
  73579 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73580     defined(BCM_56450_B1)
  73581     { /* SOC_REG_INT_XPAUSE_D2_BCM56450_A0r */
  73582         soc_block_list[83],
  73583         soc_portreg,
  73584         1,
  73585         0,
  73586         0x20a00,
  73587         0,
  73588         0,
  73589         1,
  73590         soc_XPAUSE_D2_BCM56640_A0r_fields,
  73591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73592         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73593         -1,
  73594         -1,
  73595     },
  73596 #endif /* chips */
  73597 
  73598 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  73599     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  73600     { /* SOC_REG_INT_XPAUSE_D2_BCM56624_A0r */
  73601         soc_block_list[204],
  73602         soc_portreg,
  73603         1,
  73604         0,
  73605         0x80a,
  73606         0,
  73607         0,
  73608         1,
  73609         soc_XPAUSE_D2r_fields,
  73610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73611         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73612         -1,
  73613         -1,
  73614     },
  73615 #endif /* chips */
  73616 
  73617 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  73618     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  73619     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  73620     { /* SOC_REG_INT_XPAUSE_D2_BCM56634_A0r */
  73621         soc_block_list[208],
  73622         soc_portreg,
  73623         1,
  73624         0,
  73625         0x80a,
  73626         0,
  73627         0,
  73628         1,
  73629         soc_XPAUSE_D2r_fields,
  73630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73631         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73632         -1,
  73633         -1,
  73634     },
  73635 #endif /* chips */
  73636 
  73637 #if defined(BCM_56640_A0)
  73638     { /* SOC_REG_INT_XPAUSE_D2_BCM56640_A0r */
  73639         soc_block_list[212],
  73640         soc_portreg,
  73641         1,
  73642         0,
  73643         0x20a00,
  73644         0,
  73645         0,
  73646         1,
  73647         soc_XPAUSE_D2_BCM56640_A0r_fields,
  73648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73649         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73650         -1,
  73651         -1,
  73652     },
  73653 #endif /* chips */
  73654 
  73655 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  73656     defined(BCM_56820_A0)
  73657     { /* SOC_REG_INT_XPAUSE_D2_BCM56800_A0r */
  73658         soc_block_list[9],
  73659         soc_portreg,
  73660         1,
  73661         0,
  73662         0x80a,
  73663         0,
  73664         0,
  73665         1,
  73666         soc_XPAUSE_D2r_fields,
  73667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73668         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73669         -1,
  73670         -1,
  73671     },
  73672 #endif /* chips */
  73673 
  73674 #if defined(BCM_56840_A0)
  73675     { /* SOC_REG_INT_XPAUSE_D2_BCM56840_A0r */
  73676         soc_block_list[16],
  73677         soc_portreg,
  73678         1,
  73679         0,
  73680         0x20a,
  73681         0,
  73682         0,
  73683         1,
  73684         soc_XPAUSE_D2r_fields,
  73685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73686         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73687         -1,
  73688         -1,
  73689     },
  73690 #endif /* chips */
  73691 
  73692 #if defined(BCM_56840_B0)
  73693     { /* SOC_REG_INT_XPAUSE_D2_BCM56840_B0r */
  73694         soc_block_list[16],
  73695         soc_portreg,
  73696         1,
  73697         0,
  73698         0x20a,
  73699         0,
  73700         0,
  73701         1,
  73702         soc_XPAUSE_D2r_fields,
  73703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73704         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73705         -1,
  73706         -1,
  73707     },
  73708 #endif /* chips */
  73709 
  73710 #if defined(BCM_88732_A0)
  73711     { /* SOC_REG_INT_XPAUSE_D2_BCM88732_A0r */
  73712         soc_block_list[16],
  73713         soc_portreg,
  73714         1,
  73715         0,
  73716         0x20a,
  73717         0,
  73718         0,
  73719         1,
  73720         soc_XPAUSE_D2r_fields,
  73721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73722         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73723         -1,
  73724         -1,
  73725     },
  73726 #endif /* chips */
  73727 
  73728 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  73729     defined(BCM_56334_B0)
  73730     { /* SOC_REG_INT_XPAUSE_D3_BCM56334_A0r */
  73731         soc_block_list[14],
  73732         soc_portreg,
  73733         1,
  73734         0,
  73735         0x80b,
  73736         0,
  73737         0,
  73738         1,
  73739         soc_XPAUSE_D3r_fields,
  73740         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73741         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73742         -1,
  73743         -1,
  73744     },
  73745 #endif /* chips */
  73746 
  73747 #if defined(BCM_56340_A0)
  73748     { /* SOC_REG_INT_XPAUSE_D3_BCM56340_A0r */
  73749         soc_block_list[214],
  73750         soc_portreg,
  73751         1,
  73752         0,
  73753         0x20b00,
  73754         0,
  73755         0,
  73756         1,
  73757         soc_XPAUSE_D3_BCM56640_A0r_fields,
  73758         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73760         -1,
  73761         -1,
  73762     },
  73763 #endif /* chips */
  73764 
  73765 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  73766     { /* SOC_REG_INT_XPAUSE_D3_BCM56440_A0r */
  73767         soc_block_list[83],
  73768         soc_portreg,
  73769         1,
  73770         0,
  73771         0x20b,
  73772         0,
  73773         0,
  73774         1,
  73775         soc_XPAUSE_D3r_fields,
  73776         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73778         -1,
  73779         -1,
  73780     },
  73781 #endif /* chips */
  73782 
  73783 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  73784     defined(BCM_56450_B1)
  73785     { /* SOC_REG_INT_XPAUSE_D3_BCM56450_A0r */
  73786         soc_block_list[83],
  73787         soc_portreg,
  73788         1,
  73789         0,
  73790         0x20b00,
  73791         0,
  73792         0,
  73793         1,
  73794         soc_XPAUSE_D3_BCM56640_A0r_fields,
  73795         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73796         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73797         -1,
  73798         -1,
  73799     },
  73800 #endif /* chips */
  73801 
  73802 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  73803     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  73804     { /* SOC_REG_INT_XPAUSE_D3_BCM56624_A0r */
  73805         soc_block_list[204],
  73806         soc_portreg,
  73807         1,
  73808         0,
  73809         0x80b,
  73810         0,
  73811         0,
  73812         1,
  73813         soc_XPAUSE_D3r_fields,
  73814         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73815         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73816         -1,
  73817         -1,
  73818     },
  73819 #endif /* chips */
  73820 
  73821 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  73822     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  73823     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  73824     { /* SOC_REG_INT_XPAUSE_D3_BCM56634_A0r */
  73825         soc_block_list[208],
  73826         soc_portreg,
  73827         1,
  73828         0,
  73829         0x80b,
  73830         0,
  73831         0,
  73832         1,
  73833         soc_XPAUSE_D3r_fields,
  73834         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73835         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73836         -1,
  73837         -1,
  73838     },
  73839 #endif /* chips */
  73840 
  73841 #if defined(BCM_56640_A0)
  73842     { /* SOC_REG_INT_XPAUSE_D3_BCM56640_A0r */
  73843         soc_block_list[212],
  73844         soc_portreg,
  73845         1,
  73846         0,
  73847         0x20b00,
  73848         0,
  73849         0,
  73850         1,
  73851         soc_XPAUSE_D3_BCM56640_A0r_fields,
  73852         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73853         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73854         -1,
  73855         -1,
  73856     },
  73857 #endif /* chips */
  73858 
  73859 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  73860     defined(BCM_56820_A0)
  73861     { /* SOC_REG_INT_XPAUSE_D3_BCM56800_A0r */
  73862         soc_block_list[9],
  73863         soc_portreg,
  73864         1,
  73865         0,
  73866         0x80b,
  73867         0,
  73868         0,
  73869         1,
  73870         soc_XPAUSE_D3r_fields,
  73871         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73872         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73873         -1,
  73874         -1,
  73875     },
  73876 #endif /* chips */
  73877 
  73878 #if defined(BCM_56840_A0)
  73879     { /* SOC_REG_INT_XPAUSE_D3_BCM56840_A0r */
  73880         soc_block_list[16],
  73881         soc_portreg,
  73882         1,
  73883         0,
  73884         0x20b,
  73885         0,
  73886         0,
  73887         1,
  73888         soc_XPAUSE_D3r_fields,
  73889         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73890         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73891         -1,
  73892         -1,
  73893     },
  73894 #endif /* chips */
  73895 
  73896 #if defined(BCM_56840_B0)
  73897     { /* SOC_REG_INT_XPAUSE_D3_BCM56840_B0r */
  73898         soc_block_list[16],
  73899         soc_portreg,
  73900         1,
  73901         0,
  73902         0x20b,
  73903         0,
  73904         0,
  73905         1,
  73906         soc_XPAUSE_D3r_fields,
  73907         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73908         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73909         -1,
  73910         -1,
  73911     },
  73912 #endif /* chips */
  73913 
  73914 #if defined(BCM_88732_A0)
  73915     { /* SOC_REG_INT_XPAUSE_D3_BCM88732_A0r */
  73916         soc_block_list[16],
  73917         soc_portreg,
  73918         1,
  73919         0,
  73920         0x20b,
  73921         0,
  73922         0,
  73923         1,
  73924         soc_XPAUSE_D3r_fields,
  73925         SOC_RESET_VAL_DEC(0x88080001, 0x00000000)
  73926         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73927         -1,
  73928         -1,
  73929     },
  73930 #endif /* chips */
  73931 
  73932 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  73933     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  73934     { /* SOC_REG_INT_XPAUSE_MH0r */
  73935         soc_block_list[0],
  73936         soc_genreg,
  73937         1,
  73938         0,
  73939         0x80004,
  73940         0,
  73941         0,
  73942         1,
  73943         soc_XPAUSE_MH0r_fields,
  73944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73946         -1,
  73947         -1,
  73948     },
  73949 #endif /* chips */
  73950 
  73951 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  73952     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  73953     { /* SOC_REG_INT_XPAUSE_MH1r */
  73954         soc_block_list[0],
  73955         soc_genreg,
  73956         1,
  73957         0,
  73958         0x80005,
  73959         0,
  73960         0,
  73961         1,
  73962         soc_XPAUSE_MH1r_fields,
  73963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73964         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73965         -1,
  73966         -1,
  73967     },
  73968 #endif /* chips */
  73969 
  73970 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  73971     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  73972     { /* SOC_REG_INT_XPAUSE_MH2r */
  73973         soc_block_list[0],
  73974         soc_genreg,
  73975         1,
  73976         0,
  73977         0x80006,
  73978         0,
  73979         0,
  73980         1,
  73981         soc_XHOL_MH2r_fields,
  73982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73983         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73984         -1,
  73985         -1,
  73986     },
  73987 #endif /* chips */
  73988 
  73989 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  73990     defined(BCM_56820_A0)
  73991     { /* SOC_REG_INT_XPAUSE_MH3r */
  73992         soc_block_list[9],
  73993         soc_portreg,
  73994         1,
  73995         0,
  73996         0x807,
  73997         0,
  73998         0,
  73999         1,
  74000         soc_XHOL_MH3r_fields,
  74001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74002         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74003         -1,
  74004         -1,
  74005     },
  74006 #endif /* chips */
  74007 
  74008 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  74009     defined(BCM_56334_B0)
  74010     { /* SOC_REG_INT_XPAUSE_MH0_BCM56334_A0r */
  74011         soc_block_list[14],
  74012         soc_portreg,
  74013         1,
  74014         0,
  74015         0x804,
  74016         0,
  74017         0,
  74018         1,
  74019         soc_XPAUSE_MH0r_fields,
  74020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74021         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74022         -1,
  74023         -1,
  74024     },
  74025 #endif /* chips */
  74026 
  74027 #if defined(BCM_56340_A0)
  74028     { /* SOC_REG_INT_XPAUSE_MH0_BCM56340_A0r */
  74029         soc_block_list[214],
  74030         soc_portreg,
  74031         1,
  74032         0,
  74033         0x20400,
  74034         0,
  74035         0,
  74036         1,
  74037         soc_XPAUSE_MH0_BCM56640_A0r_fields,
  74038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74039         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74040         -1,
  74041         -1,
  74042     },
  74043 #endif /* chips */
  74044 
  74045 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  74046     { /* SOC_REG_INT_XPAUSE_MH0_BCM56440_A0r */
  74047         soc_block_list[83],
  74048         soc_portreg,
  74049         1,
  74050         0,
  74051         0x204,
  74052         0,
  74053         0,
  74054         1,
  74055         soc_XPAUSE_MH0r_fields,
  74056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74057         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74058         -1,
  74059         -1,
  74060     },
  74061 #endif /* chips */
  74062 
  74063 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  74064     defined(BCM_56450_B1)
  74065     { /* SOC_REG_INT_XPAUSE_MH0_BCM56450_A0r */
  74066         soc_block_list[83],
  74067         soc_portreg,
  74068         1,
  74069         0,
  74070         0x20400,
  74071         0,
  74072         0,
  74073         1,
  74074         soc_XPAUSE_MH0_BCM56640_A0r_fields,
  74075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74076         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74077         -1,
  74078         -1,
  74079     },
  74080 #endif /* chips */
  74081 
  74082 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74083     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  74084     { /* SOC_REG_INT_XPAUSE_MH0_BCM56624_A0r */
  74085         soc_block_list[204],
  74086         soc_portreg,
  74087         1,
  74088         0,
  74089         0x804,
  74090         0,
  74091         0,
  74092         1,
  74093         soc_XPAUSE_MH0r_fields,
  74094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74096         -1,
  74097         -1,
  74098     },
  74099 #endif /* chips */
  74100 
  74101 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74102     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74103     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74104     { /* SOC_REG_INT_XPAUSE_MH0_BCM56634_A0r */
  74105         soc_block_list[208],
  74106         soc_portreg,
  74107         1,
  74108         0,
  74109         0x804,
  74110         0,
  74111         0,
  74112         1,
  74113         soc_XPAUSE_MH0r_fields,
  74114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74116         -1,
  74117         -1,
  74118     },
  74119 #endif /* chips */
  74120 
  74121 #if defined(BCM_56640_A0)
  74122     { /* SOC_REG_INT_XPAUSE_MH0_BCM56640_A0r */
  74123         soc_block_list[212],
  74124         soc_portreg,
  74125         1,
  74126         0,
  74127         0x20400,
  74128         0,
  74129         0,
  74130         1,
  74131         soc_XPAUSE_MH0_BCM56640_A0r_fields,
  74132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74133         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74134         -1,
  74135         -1,
  74136     },
  74137 #endif /* chips */
  74138 
  74139 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  74140     defined(BCM_56820_A0)
  74141     { /* SOC_REG_INT_XPAUSE_MH0_BCM56800_A0r */
  74142         soc_block_list[9],
  74143         soc_portreg,
  74144         1,
  74145         0,
  74146         0x804,
  74147         0,
  74148         0,
  74149         1,
  74150         soc_XPAUSE_MH0r_fields,
  74151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74152         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74153         -1,
  74154         -1,
  74155     },
  74156 #endif /* chips */
  74157 
  74158 #if defined(BCM_56840_A0)
  74159     { /* SOC_REG_INT_XPAUSE_MH0_BCM56840_A0r */
  74160         soc_block_list[16],
  74161         soc_portreg,
  74162         1,
  74163         0,
  74164         0x204,
  74165         0,
  74166         0,
  74167         1,
  74168         soc_XPAUSE_MH0r_fields,
  74169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74170         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74171         -1,
  74172         -1,
  74173     },
  74174 #endif /* chips */
  74175 
  74176 #if defined(BCM_56840_B0)
  74177     { /* SOC_REG_INT_XPAUSE_MH0_BCM56840_B0r */
  74178         soc_block_list[16],
  74179         soc_portreg,
  74180         1,
  74181         0,
  74182         0x204,
  74183         0,
  74184         0,
  74185         1,
  74186         soc_XPAUSE_MH0r_fields,
  74187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74188         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74189         -1,
  74190         -1,
  74191     },
  74192 #endif /* chips */
  74193 
  74194 #if defined(BCM_88732_A0)
  74195     { /* SOC_REG_INT_XPAUSE_MH0_BCM88732_A0r */
  74196         soc_block_list[16],
  74197         soc_portreg,
  74198         1,
  74199         0,
  74200         0x204,
  74201         0,
  74202         0,
  74203         1,
  74204         soc_XPAUSE_MH0r_fields,
  74205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74206         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74207         -1,
  74208         -1,
  74209     },
  74210 #endif /* chips */
  74211 
  74212 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  74213     defined(BCM_56334_B0)
  74214     { /* SOC_REG_INT_XPAUSE_MH1_BCM56334_A0r */
  74215         soc_block_list[14],
  74216         soc_portreg,
  74217         1,
  74218         0,
  74219         0x805,
  74220         0,
  74221         0,
  74222         1,
  74223         soc_XPAUSE_MH1r_fields,
  74224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74225         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74226         -1,
  74227         -1,
  74228     },
  74229 #endif /* chips */
  74230 
  74231 #if defined(BCM_56340_A0)
  74232     { /* SOC_REG_INT_XPAUSE_MH1_BCM56340_A0r */
  74233         soc_block_list[214],
  74234         soc_portreg,
  74235         1,
  74236         0,
  74237         0x20500,
  74238         0,
  74239         0,
  74240         1,
  74241         soc_XPAUSE_MH1_BCM56640_A0r_fields,
  74242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74243         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74244         -1,
  74245         -1,
  74246     },
  74247 #endif /* chips */
  74248 
  74249 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  74250     { /* SOC_REG_INT_XPAUSE_MH1_BCM56440_A0r */
  74251         soc_block_list[83],
  74252         soc_portreg,
  74253         1,
  74254         0,
  74255         0x205,
  74256         0,
  74257         0,
  74258         1,
  74259         soc_XPAUSE_MH1r_fields,
  74260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74261         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74262         -1,
  74263         -1,
  74264     },
  74265 #endif /* chips */
  74266 
  74267 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  74268     defined(BCM_56450_B1)
  74269     { /* SOC_REG_INT_XPAUSE_MH1_BCM56450_A0r */
  74270         soc_block_list[83],
  74271         soc_portreg,
  74272         1,
  74273         0,
  74274         0x20500,
  74275         0,
  74276         0,
  74277         1,
  74278         soc_XPAUSE_MH1_BCM56640_A0r_fields,
  74279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74280         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74281         -1,
  74282         -1,
  74283     },
  74284 #endif /* chips */
  74285 
  74286 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74287     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  74288     { /* SOC_REG_INT_XPAUSE_MH1_BCM56624_A0r */
  74289         soc_block_list[204],
  74290         soc_portreg,
  74291         1,
  74292         0,
  74293         0x805,
  74294         0,
  74295         0,
  74296         1,
  74297         soc_XPAUSE_MH1r_fields,
  74298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74300         -1,
  74301         -1,
  74302     },
  74303 #endif /* chips */
  74304 
  74305 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74306     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74307     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74308     { /* SOC_REG_INT_XPAUSE_MH1_BCM56634_A0r */
  74309         soc_block_list[208],
  74310         soc_portreg,
  74311         1,
  74312         0,
  74313         0x805,
  74314         0,
  74315         0,
  74316         1,
  74317         soc_XPAUSE_MH1r_fields,
  74318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74319         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74320         -1,
  74321         -1,
  74322     },
  74323 #endif /* chips */
  74324 
  74325 #if defined(BCM_56640_A0)
  74326     { /* SOC_REG_INT_XPAUSE_MH1_BCM56640_A0r */
  74327         soc_block_list[212],
  74328         soc_portreg,
  74329         1,
  74330         0,
  74331         0x20500,
  74332         0,
  74333         0,
  74334         1,
  74335         soc_XPAUSE_MH1_BCM56640_A0r_fields,
  74336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74337         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74338         -1,
  74339         -1,
  74340     },
  74341 #endif /* chips */
  74342 
  74343 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  74344     defined(BCM_56820_A0)
  74345     { /* SOC_REG_INT_XPAUSE_MH1_BCM56800_A0r */
  74346         soc_block_list[9],
  74347         soc_portreg,
  74348         1,
  74349         0,
  74350         0x805,
  74351         0,
  74352         0,
  74353         1,
  74354         soc_XPAUSE_MH1r_fields,
  74355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74356         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74357         -1,
  74358         -1,
  74359     },
  74360 #endif /* chips */
  74361 
  74362 #if defined(BCM_56840_A0)
  74363     { /* SOC_REG_INT_XPAUSE_MH1_BCM56840_A0r */
  74364         soc_block_list[16],
  74365         soc_portreg,
  74366         1,
  74367         0,
  74368         0x205,
  74369         0,
  74370         0,
  74371         1,
  74372         soc_XPAUSE_MH1r_fields,
  74373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74374         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74375         -1,
  74376         -1,
  74377     },
  74378 #endif /* chips */
  74379 
  74380 #if defined(BCM_56840_B0)
  74381     { /* SOC_REG_INT_XPAUSE_MH1_BCM56840_B0r */
  74382         soc_block_list[16],
  74383         soc_portreg,
  74384         1,
  74385         0,
  74386         0x205,
  74387         0,
  74388         0,
  74389         1,
  74390         soc_XPAUSE_MH1r_fields,
  74391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74392         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74393         -1,
  74394         -1,
  74395     },
  74396 #endif /* chips */
  74397 
  74398 #if defined(BCM_88732_A0)
  74399     { /* SOC_REG_INT_XPAUSE_MH1_BCM88732_A0r */
  74400         soc_block_list[16],
  74401         soc_portreg,
  74402         1,
  74403         0,
  74404         0x205,
  74405         0,
  74406         0,
  74407         1,
  74408         soc_XPAUSE_MH1r_fields,
  74409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74410         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74411         -1,
  74412         -1,
  74413     },
  74414 #endif /* chips */
  74415 
  74416 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  74417     defined(BCM_56334_B0)
  74418     { /* SOC_REG_INT_XPAUSE_MH2_BCM56334_A0r */
  74419         soc_block_list[14],
  74420         soc_portreg,
  74421         1,
  74422         0,
  74423         0x806,
  74424         0,
  74425         0,
  74426         1,
  74427         soc_XHOL_MH2r_fields,
  74428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74429         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74430         -1,
  74431         -1,
  74432     },
  74433 #endif /* chips */
  74434 
  74435 #if defined(BCM_56340_A0)
  74436     { /* SOC_REG_INT_XPAUSE_MH2_BCM56340_A0r */
  74437         soc_block_list[214],
  74438         soc_portreg,
  74439         1,
  74440         0,
  74441         0x20600,
  74442         0,
  74443         0,
  74444         1,
  74445         soc_XHOL_MH2_BCM56640_A0r_fields,
  74446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74447         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74448         -1,
  74449         -1,
  74450     },
  74451 #endif /* chips */
  74452 
  74453 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  74454     { /* SOC_REG_INT_XPAUSE_MH2_BCM56440_A0r */
  74455         soc_block_list[83],
  74456         soc_portreg,
  74457         1,
  74458         0,
  74459         0x206,
  74460         0,
  74461         0,
  74462         1,
  74463         soc_XHOL_MH2r_fields,
  74464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74465         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74466         -1,
  74467         -1,
  74468     },
  74469 #endif /* chips */
  74470 
  74471 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  74472     defined(BCM_56450_B1)
  74473     { /* SOC_REG_INT_XPAUSE_MH2_BCM56450_A0r */
  74474         soc_block_list[83],
  74475         soc_portreg,
  74476         1,
  74477         0,
  74478         0x20600,
  74479         0,
  74480         0,
  74481         1,
  74482         soc_XHOL_MH2_BCM56640_A0r_fields,
  74483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74484         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74485         -1,
  74486         -1,
  74487     },
  74488 #endif /* chips */
  74489 
  74490 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74491     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  74492     { /* SOC_REG_INT_XPAUSE_MH2_BCM56624_A0r */
  74493         soc_block_list[204],
  74494         soc_portreg,
  74495         1,
  74496         0,
  74497         0x806,
  74498         0,
  74499         0,
  74500         1,
  74501         soc_XHOL_MH2r_fields,
  74502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74503         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74504         -1,
  74505         -1,
  74506     },
  74507 #endif /* chips */
  74508 
  74509 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74510     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74511     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74512     { /* SOC_REG_INT_XPAUSE_MH2_BCM56634_A0r */
  74513         soc_block_list[208],
  74514         soc_portreg,
  74515         1,
  74516         0,
  74517         0x806,
  74518         0,
  74519         0,
  74520         1,
  74521         soc_XHOL_MH2r_fields,
  74522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74523         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74524         -1,
  74525         -1,
  74526     },
  74527 #endif /* chips */
  74528 
  74529 #if defined(BCM_56640_A0)
  74530     { /* SOC_REG_INT_XPAUSE_MH2_BCM56640_A0r */
  74531         soc_block_list[212],
  74532         soc_portreg,
  74533         1,
  74534         0,
  74535         0x20600,
  74536         0,
  74537         0,
  74538         1,
  74539         soc_XHOL_MH2_BCM56640_A0r_fields,
  74540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74542         -1,
  74543         -1,
  74544     },
  74545 #endif /* chips */
  74546 
  74547 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  74548     defined(BCM_56820_A0)
  74549     { /* SOC_REG_INT_XPAUSE_MH2_BCM56800_A0r */
  74550         soc_block_list[9],
  74551         soc_portreg,
  74552         1,
  74553         0,
  74554         0x806,
  74555         0,
  74556         0,
  74557         1,
  74558         soc_XHOL_MH2r_fields,
  74559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74560         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74561         -1,
  74562         -1,
  74563     },
  74564 #endif /* chips */
  74565 
  74566 #if defined(BCM_56840_A0)
  74567     { /* SOC_REG_INT_XPAUSE_MH2_BCM56840_A0r */
  74568         soc_block_list[16],
  74569         soc_portreg,
  74570         1,
  74571         0,
  74572         0x206,
  74573         0,
  74574         0,
  74575         1,
  74576         soc_XHOL_MH2r_fields,
  74577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74578         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74579         -1,
  74580         -1,
  74581     },
  74582 #endif /* chips */
  74583 
  74584 #if defined(BCM_56840_B0)
  74585     { /* SOC_REG_INT_XPAUSE_MH2_BCM56840_B0r */
  74586         soc_block_list[16],
  74587         soc_portreg,
  74588         1,
  74589         0,
  74590         0x206,
  74591         0,
  74592         0,
  74593         1,
  74594         soc_XHOL_MH2r_fields,
  74595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74596         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74597         -1,
  74598         -1,
  74599     },
  74600 #endif /* chips */
  74601 
  74602 #if defined(BCM_88732_A0)
  74603     { /* SOC_REG_INT_XPAUSE_MH2_BCM88732_A0r */
  74604         soc_block_list[16],
  74605         soc_portreg,
  74606         1,
  74607         0,
  74608         0x206,
  74609         0,
  74610         0,
  74611         1,
  74612         soc_XHOL_MH2r_fields,
  74613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74614         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74615         -1,
  74616         -1,
  74617     },
  74618 #endif /* chips */
  74619 
  74620 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  74621     defined(BCM_56334_B0)
  74622     { /* SOC_REG_INT_XPAUSE_MH3_BCM56334_A0r */
  74623         soc_block_list[14],
  74624         soc_portreg,
  74625         1,
  74626         0,
  74627         0x807,
  74628         0,
  74629         0,
  74630         1,
  74631         soc_XHOL_MH3r_fields,
  74632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74633         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74634         -1,
  74635         -1,
  74636     },
  74637 #endif /* chips */
  74638 
  74639 #if defined(BCM_56340_A0)
  74640     { /* SOC_REG_INT_XPAUSE_MH3_BCM56340_A0r */
  74641         soc_block_list[214],
  74642         soc_portreg,
  74643         1,
  74644         0,
  74645         0x20700,
  74646         0,
  74647         0,
  74648         1,
  74649         soc_XHOL_MH3_BCM56640_A0r_fields,
  74650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74651         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74652         -1,
  74653         -1,
  74654     },
  74655 #endif /* chips */
  74656 
  74657 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  74658     { /* SOC_REG_INT_XPAUSE_MH3_BCM56440_A0r */
  74659         soc_block_list[83],
  74660         soc_portreg,
  74661         1,
  74662         0,
  74663         0x207,
  74664         0,
  74665         0,
  74666         1,
  74667         soc_XHOL_MH3r_fields,
  74668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74670         -1,
  74671         -1,
  74672     },
  74673 #endif /* chips */
  74674 
  74675 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  74676     defined(BCM_56450_B1)
  74677     { /* SOC_REG_INT_XPAUSE_MH3_BCM56450_A0r */
  74678         soc_block_list[83],
  74679         soc_portreg,
  74680         1,
  74681         0,
  74682         0x20700,
  74683         0,
  74684         0,
  74685         1,
  74686         soc_XHOL_MH3_BCM56640_A0r_fields,
  74687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74689         -1,
  74690         -1,
  74691     },
  74692 #endif /* chips */
  74693 
  74694 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74695     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  74696     { /* SOC_REG_INT_XPAUSE_MH3_BCM56624_A0r */
  74697         soc_block_list[204],
  74698         soc_portreg,
  74699         1,
  74700         0,
  74701         0x807,
  74702         0,
  74703         0,
  74704         1,
  74705         soc_XHOL_MH3r_fields,
  74706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74708         -1,
  74709         -1,
  74710     },
  74711 #endif /* chips */
  74712 
  74713 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74714     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74715     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74716     { /* SOC_REG_INT_XPAUSE_MH3_BCM56634_A0r */
  74717         soc_block_list[208],
  74718         soc_portreg,
  74719         1,
  74720         0,
  74721         0x807,
  74722         0,
  74723         0,
  74724         1,
  74725         soc_XHOL_MH3r_fields,
  74726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74727         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74728         -1,
  74729         -1,
  74730     },
  74731 #endif /* chips */
  74732 
  74733 #if defined(BCM_56640_A0)
  74734     { /* SOC_REG_INT_XPAUSE_MH3_BCM56640_A0r */
  74735         soc_block_list[212],
  74736         soc_portreg,
  74737         1,
  74738         0,
  74739         0x20700,
  74740         0,
  74741         0,
  74742         1,
  74743         soc_XHOL_MH3_BCM56640_A0r_fields,
  74744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74745         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74746         -1,
  74747         -1,
  74748     },
  74749 #endif /* chips */
  74750 
  74751 #if defined(BCM_56840_A0)
  74752     { /* SOC_REG_INT_XPAUSE_MH3_BCM56840_A0r */
  74753         soc_block_list[16],
  74754         soc_portreg,
  74755         1,
  74756         0,
  74757         0x207,
  74758         0,
  74759         0,
  74760         1,
  74761         soc_XHOL_MH3r_fields,
  74762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74763         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74764         -1,
  74765         -1,
  74766     },
  74767 #endif /* chips */
  74768 
  74769 #if defined(BCM_56840_B0)
  74770     { /* SOC_REG_INT_XPAUSE_MH3_BCM56840_B0r */
  74771         soc_block_list[16],
  74772         soc_portreg,
  74773         1,
  74774         0,
  74775         0x207,
  74776         0,
  74777         0,
  74778         1,
  74779         soc_XHOL_MH3r_fields,
  74780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74781         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74782         -1,
  74783         -1,
  74784     },
  74785 #endif /* chips */
  74786 
  74787 #if defined(BCM_88732_A0)
  74788     { /* SOC_REG_INT_XPAUSE_MH3_BCM88732_A0r */
  74789         soc_block_list[16],
  74790         soc_portreg,
  74791         1,
  74792         0,
  74793         0x207,
  74794         0,
  74795         0,
  74796         1,
  74797         soc_XHOL_MH3r_fields,
  74798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74799         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74800         -1,
  74801         -1,
  74802     },
  74803 #endif /* chips */
  74804 
  74805 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  74806     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  74807     { /* SOC_REG_INT_XPAUSE_RX_DA_LSr */
  74808         soc_block_list[0],
  74809         soc_genreg,
  74810         1,
  74811         0,
  74812         0x8001a,
  74813         0,
  74814         0,
  74815         1,
  74816         soc_XPAUSE_RX_DA_LSr_fields,
  74817         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  74818         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74819         -1,
  74820         -1,
  74821     },
  74822 #endif /* chips */
  74823 
  74824 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  74825     defined(BCM_56334_B0)
  74826     { /* SOC_REG_INT_XPAUSE_RX_DA_LS_BCM56334_A0r */
  74827         soc_block_list[14],
  74828         soc_portreg,
  74829         1,
  74830         0,
  74831         0x81d,
  74832         0,
  74833         0,
  74834         1,
  74835         soc_XPAUSE_RX_DA_LSr_fields,
  74836         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  74837         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74838         -1,
  74839         -1,
  74840     },
  74841 #endif /* chips */
  74842 
  74843 #if defined(BCM_56340_A0)
  74844     { /* SOC_REG_INT_XPAUSE_RX_DA_LS_BCM56340_A0r */
  74845         soc_block_list[214],
  74846         soc_portreg,
  74847         1,
  74848         0,
  74849         0x20d00,
  74850         0,
  74851         0,
  74852         1,
  74853         soc_XPAUSE_RX_DA_LS_BCM56640_A0r_fields,
  74854         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  74855         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74856         -1,
  74857         -1,
  74858     },
  74859 #endif /* chips */
  74860 
  74861 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  74862     { /* SOC_REG_INT_XPAUSE_RX_DA_LS_BCM56440_A0r */
  74863         soc_block_list[83],
  74864         soc_portreg,
  74865         1,
  74866         0,
  74867         0x20d,
  74868         0,
  74869         0,
  74870         1,
  74871         soc_XPAUSE_RX_DA_LSr_fields,
  74872         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  74873         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74874         -1,
  74875         -1,
  74876     },
  74877 #endif /* chips */
  74878 
  74879 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  74880     defined(BCM_56450_B1)
  74881     { /* SOC_REG_INT_XPAUSE_RX_DA_LS_BCM56450_A0r */
  74882         soc_block_list[83],
  74883         soc_portreg,
  74884         1,
  74885         0,
  74886         0x20d00,
  74887         0,
  74888         0,
  74889         1,
  74890         soc_XPAUSE_RX_DA_LS_BCM56640_A0r_fields,
  74891         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  74892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74893         -1,
  74894         -1,
  74895     },
  74896 #endif /* chips */
  74897 
  74898 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  74899     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  74900     { /* SOC_REG_INT_XPAUSE_RX_DA_LS_BCM56624_A0r */
  74901         soc_block_list[204],
  74902         soc_portreg,
  74903         1,
  74904         0,
  74905         0x81d,
  74906         0,
  74907         0,
  74908         1,
  74909         soc_XPAUSE_RX_DA_LSr_fields,
  74910         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  74911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74912         -1,
  74913         -1,
  74914     },
  74915 #endif /* chips */
  74916 
  74917 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  74918     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  74919     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  74920     { /* SOC_REG_INT_XPAUSE_RX_DA_LS_BCM56634_A0r */
  74921         soc_block_list[208],
  74922         soc_portreg,
  74923         1,
  74924         0,
  74925         0x81d,
  74926         0,
  74927         0,
  74928         1,
  74929         soc_XPAUSE_RX_DA_LSr_fields,
  74930         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  74931         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74932         -1,
  74933         -1,
  74934     },
  74935 #endif /* chips */
  74936 
  74937 #if defined(BCM_56640_A0)
  74938     { /* SOC_REG_INT_XPAUSE_RX_DA_LS_BCM56640_A0r */
  74939         soc_block_list[212],
  74940         soc_portreg,
  74941         1,
  74942         0,
  74943         0x20d00,
  74944         0,
  74945         0,
  74946         1,
  74947         soc_XPAUSE_RX_DA_LS_BCM56640_A0r_fields,
  74948         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  74949         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74950         -1,
  74951         -1,
  74952     },
  74953 #endif /* chips */
  74954 
  74955 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  74956     defined(BCM_56820_A0)
  74957     { /* SOC_REG_INT_XPAUSE_RX_DA_LS_BCM56800_A0r */
  74958         soc_block_list[9],
  74959         soc_portreg,
  74960         1,
  74961         0,
  74962         0x81d,
  74963         0,
  74964         0,
  74965         1,
  74966         soc_XPAUSE_RX_DA_LSr_fields,
  74967         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  74968         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74969         -1,
  74970         -1,
  74971     },
  74972 #endif /* chips */
  74973 
  74974 #if defined(BCM_56840_A0)
  74975     { /* SOC_REG_INT_XPAUSE_RX_DA_LS_BCM56840_A0r */
  74976         soc_block_list[16],
  74977         soc_portreg,
  74978         1,
  74979         0,
  74980         0x215,
  74981         0,
  74982         0,
  74983         1,
  74984         soc_XPAUSE_RX_DA_LSr_fields,
  74985         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  74986         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  74987         -1,
  74988         -1,
  74989     },
  74990 #endif /* chips */
  74991 
  74992 #if defined(BCM_56840_B0)
  74993     { /* SOC_REG_INT_XPAUSE_RX_DA_LS_BCM56840_B0r */
  74994         soc_block_list[16],
  74995         soc_portreg,
  74996         1,
  74997         0,
  74998         0x215,
  74999         0,
  75000         0,
  75001         1,
  75002         soc_XPAUSE_RX_DA_LSr_fields,
  75003         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  75004         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  75005         -1,
  75006         -1,
  75007     },
  75008 #endif /* chips */
  75009 
  75010 #if defined(BCM_88732_A0)
  75011     { /* SOC_REG_INT_XPAUSE_RX_DA_LS_BCM88732_A0r */
  75012         soc_block_list[16],
  75013         soc_portreg,
  75014         1,
  75015         0,
  75016         0x215,
  75017         0,
  75018         0,
  75019         1,
  75020         soc_XPAUSE_RX_DA_LSr_fields,
  75021         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  75022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  75023         -1,
  75024         -1,
  75025     },
  75026 #endif /* chips */
  75027 
  75028 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  75029     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  75030     { /* SOC_REG_INT_XPAUSE_RX_DA_MSr */
  75031         soc_block_list[0],
  75032         soc_genreg,
  75033         1,
  75034         0,
  75035         0x80019,
  75036         0,
  75037         0,
  75038         1,
  75039         soc_XPAUSE_RX_DA_MSr_fields,
  75040         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75041         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75042         -1,
  75043         -1,
  75044     },
  75045 #endif /* chips */
  75046 
  75047 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  75048     defined(BCM_56334_B0)
  75049     { /* SOC_REG_INT_XPAUSE_RX_DA_MS_BCM56334_A0r */
  75050         soc_block_list[14],
  75051         soc_portreg,
  75052         1,
  75053         0,
  75054         0x81c,
  75055         0,
  75056         0,
  75057         1,
  75058         soc_XPAUSE_RX_DA_MSr_fields,
  75059         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75060         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75061         -1,
  75062         -1,
  75063     },
  75064 #endif /* chips */
  75065 
  75066 #if defined(BCM_56340_A0)
  75067     { /* SOC_REG_INT_XPAUSE_RX_DA_MS_BCM56340_A0r */
  75068         soc_block_list[214],
  75069         soc_portreg,
  75070         1,
  75071         0,
  75072         0x20c00,
  75073         0,
  75074         0,
  75075         1,
  75076         soc_XPAUSE_RX_DA_MS_BCM56640_A0r_fields,
  75077         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75078         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75079         -1,
  75080         -1,
  75081     },
  75082 #endif /* chips */
  75083 
  75084 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  75085     { /* SOC_REG_INT_XPAUSE_RX_DA_MS_BCM56440_A0r */
  75086         soc_block_list[83],
  75087         soc_portreg,
  75088         1,
  75089         0,
  75090         0x20c,
  75091         0,
  75092         0,
  75093         1,
  75094         soc_XPAUSE_RX_DA_MSr_fields,
  75095         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75096         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75097         -1,
  75098         -1,
  75099     },
  75100 #endif /* chips */
  75101 
  75102 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  75103     defined(BCM_56450_B1)
  75104     { /* SOC_REG_INT_XPAUSE_RX_DA_MS_BCM56450_A0r */
  75105         soc_block_list[83],
  75106         soc_portreg,
  75107         1,
  75108         0,
  75109         0x20c00,
  75110         0,
  75111         0,
  75112         1,
  75113         soc_XPAUSE_RX_DA_MS_BCM56640_A0r_fields,
  75114         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75115         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75116         -1,
  75117         -1,
  75118     },
  75119 #endif /* chips */
  75120 
  75121 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  75122     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  75123     { /* SOC_REG_INT_XPAUSE_RX_DA_MS_BCM56624_A0r */
  75124         soc_block_list[204],
  75125         soc_portreg,
  75126         1,
  75127         0,
  75128         0x81c,
  75129         0,
  75130         0,
  75131         1,
  75132         soc_XPAUSE_RX_DA_MSr_fields,
  75133         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75134         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75135         -1,
  75136         -1,
  75137     },
  75138 #endif /* chips */
  75139 
  75140 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75141     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75142     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75143     { /* SOC_REG_INT_XPAUSE_RX_DA_MS_BCM56634_A0r */
  75144         soc_block_list[208],
  75145         soc_portreg,
  75146         1,
  75147         0,
  75148         0x81c,
  75149         0,
  75150         0,
  75151         1,
  75152         soc_XPAUSE_RX_DA_MSr_fields,
  75153         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75154         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75155         -1,
  75156         -1,
  75157     },
  75158 #endif /* chips */
  75159 
  75160 #if defined(BCM_56640_A0)
  75161     { /* SOC_REG_INT_XPAUSE_RX_DA_MS_BCM56640_A0r */
  75162         soc_block_list[212],
  75163         soc_portreg,
  75164         1,
  75165         0,
  75166         0x20c00,
  75167         0,
  75168         0,
  75169         1,
  75170         soc_XPAUSE_RX_DA_MS_BCM56640_A0r_fields,
  75171         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75172         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75173         -1,
  75174         -1,
  75175     },
  75176 #endif /* chips */
  75177 
  75178 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  75179     defined(BCM_56820_A0)
  75180     { /* SOC_REG_INT_XPAUSE_RX_DA_MS_BCM56800_A0r */
  75181         soc_block_list[9],
  75182         soc_portreg,
  75183         1,
  75184         0,
  75185         0x81c,
  75186         0,
  75187         0,
  75188         1,
  75189         soc_XPAUSE_RX_DA_MSr_fields,
  75190         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75191         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75192         -1,
  75193         -1,
  75194     },
  75195 #endif /* chips */
  75196 
  75197 #if defined(BCM_56840_A0)
  75198     { /* SOC_REG_INT_XPAUSE_RX_DA_MS_BCM56840_A0r */
  75199         soc_block_list[16],
  75200         soc_portreg,
  75201         1,
  75202         0,
  75203         0x214,
  75204         0,
  75205         0,
  75206         1,
  75207         soc_XPAUSE_RX_DA_MSr_fields,
  75208         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75209         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75210         -1,
  75211         -1,
  75212     },
  75213 #endif /* chips */
  75214 
  75215 #if defined(BCM_56840_B0)
  75216     { /* SOC_REG_INT_XPAUSE_RX_DA_MS_BCM56840_B0r */
  75217         soc_block_list[16],
  75218         soc_portreg,
  75219         1,
  75220         0,
  75221         0x214,
  75222         0,
  75223         0,
  75224         1,
  75225         soc_XPAUSE_RX_DA_MSr_fields,
  75226         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75227         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75228         -1,
  75229         -1,
  75230     },
  75231 #endif /* chips */
  75232 
  75233 #if defined(BCM_88732_A0)
  75234     { /* SOC_REG_INT_XPAUSE_RX_DA_MS_BCM88732_A0r */
  75235         soc_block_list[16],
  75236         soc_portreg,
  75237         1,
  75238         0,
  75239         0x214,
  75240         0,
  75241         0,
  75242         1,
  75243         soc_XPAUSE_RX_DA_MSr_fields,
  75244         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  75245         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75246         -1,
  75247         -1,
  75248     },
  75249 #endif /* chips */
  75250 
  75251 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  75252     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  75253     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPEr */
  75254         soc_block_list[0],
  75255         soc_genreg,
  75256         1,
  75257         0,
  75258         0x8001b,
  75259         0,
  75260         0,
  75261         1,
  75262         soc_XPAUSE_RX_LENGTH_TYPEr_fields,
  75263         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75264         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75265         -1,
  75266         -1,
  75267     },
  75268 #endif /* chips */
  75269 
  75270 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  75271     defined(BCM_56334_B0)
  75272     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPE_BCM56334_A0r */
  75273         soc_block_list[14],
  75274         soc_portreg,
  75275         1,
  75276         0,
  75277         0x81e,
  75278         0,
  75279         0,
  75280         1,
  75281         soc_XPAUSE_RX_LENGTH_TYPEr_fields,
  75282         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75283         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75284         -1,
  75285         -1,
  75286     },
  75287 #endif /* chips */
  75288 
  75289 #if defined(BCM_56340_A0)
  75290     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPE_BCM56340_A0r */
  75291         soc_block_list[214],
  75292         soc_portreg,
  75293         1,
  75294         0,
  75295         0x20e00,
  75296         0,
  75297         0,
  75298         1,
  75299         soc_XPAUSE_RX_LENGTH_TYPE_BCM56640_A0r_fields,
  75300         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75301         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75302         -1,
  75303         -1,
  75304     },
  75305 #endif /* chips */
  75306 
  75307 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  75308     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPE_BCM56440_A0r */
  75309         soc_block_list[83],
  75310         soc_portreg,
  75311         1,
  75312         0,
  75313         0x20e,
  75314         0,
  75315         0,
  75316         1,
  75317         soc_XPAUSE_RX_LENGTH_TYPEr_fields,
  75318         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75319         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75320         -1,
  75321         -1,
  75322     },
  75323 #endif /* chips */
  75324 
  75325 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  75326     defined(BCM_56450_B1)
  75327     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPE_BCM56450_A0r */
  75328         soc_block_list[83],
  75329         soc_portreg,
  75330         1,
  75331         0,
  75332         0x20e00,
  75333         0,
  75334         0,
  75335         1,
  75336         soc_XPAUSE_RX_LENGTH_TYPE_BCM56640_A0r_fields,
  75337         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75338         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75339         -1,
  75340         -1,
  75341     },
  75342 #endif /* chips */
  75343 
  75344 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  75345     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  75346     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPE_BCM56624_A0r */
  75347         soc_block_list[204],
  75348         soc_portreg,
  75349         1,
  75350         0,
  75351         0x81e,
  75352         0,
  75353         0,
  75354         1,
  75355         soc_XPAUSE_RX_LENGTH_TYPEr_fields,
  75356         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75357         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75358         -1,
  75359         -1,
  75360     },
  75361 #endif /* chips */
  75362 
  75363 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75364     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75365     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75366     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPE_BCM56634_A0r */
  75367         soc_block_list[208],
  75368         soc_portreg,
  75369         1,
  75370         0,
  75371         0x81e,
  75372         0,
  75373         0,
  75374         1,
  75375         soc_XPAUSE_RX_LENGTH_TYPEr_fields,
  75376         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75377         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75378         -1,
  75379         -1,
  75380     },
  75381 #endif /* chips */
  75382 
  75383 #if defined(BCM_56640_A0)
  75384     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPE_BCM56640_A0r */
  75385         soc_block_list[212],
  75386         soc_portreg,
  75387         1,
  75388         0,
  75389         0x20e00,
  75390         0,
  75391         0,
  75392         1,
  75393         soc_XPAUSE_RX_LENGTH_TYPE_BCM56640_A0r_fields,
  75394         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75395         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75396         -1,
  75397         -1,
  75398     },
  75399 #endif /* chips */
  75400 
  75401 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  75402     defined(BCM_56820_A0)
  75403     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPE_BCM56800_A0r */
  75404         soc_block_list[9],
  75405         soc_portreg,
  75406         1,
  75407         0,
  75408         0x81e,
  75409         0,
  75410         0,
  75411         1,
  75412         soc_XPAUSE_RX_LENGTH_TYPEr_fields,
  75413         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75414         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75415         -1,
  75416         -1,
  75417     },
  75418 #endif /* chips */
  75419 
  75420 #if defined(BCM_56840_A0)
  75421     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPE_BCM56840_A0r */
  75422         soc_block_list[16],
  75423         soc_portreg,
  75424         1,
  75425         0,
  75426         0x216,
  75427         0,
  75428         0,
  75429         1,
  75430         soc_XPAUSE_RX_LENGTH_TYPEr_fields,
  75431         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75432         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75433         -1,
  75434         -1,
  75435     },
  75436 #endif /* chips */
  75437 
  75438 #if defined(BCM_56840_B0)
  75439     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPE_BCM56840_B0r */
  75440         soc_block_list[16],
  75441         soc_portreg,
  75442         1,
  75443         0,
  75444         0x216,
  75445         0,
  75446         0,
  75447         1,
  75448         soc_XPAUSE_RX_LENGTH_TYPEr_fields,
  75449         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75450         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75451         -1,
  75452         -1,
  75453     },
  75454 #endif /* chips */
  75455 
  75456 #if defined(BCM_88732_A0)
  75457     { /* SOC_REG_INT_XPAUSE_RX_LENGTH_TYPE_BCM88732_A0r */
  75458         soc_block_list[16],
  75459         soc_portreg,
  75460         1,
  75461         0,
  75462         0x216,
  75463         0,
  75464         0,
  75465         1,
  75466         soc_XPAUSE_RX_LENGTH_TYPEr_fields,
  75467         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  75468         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75469         -1,
  75470         -1,
  75471     },
  75472 #endif /* chips */
  75473 
  75474 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  75475     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  75476     { /* SOC_REG_INT_XPAUSE_RX_OPCODEr */
  75477         soc_block_list[0],
  75478         soc_genreg,
  75479         1,
  75480         0,
  75481         0x8001c,
  75482         0,
  75483         0,
  75484         1,
  75485         soc_XPAUSE_RX_OPCODEr_fields,
  75486         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75487         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75488         -1,
  75489         -1,
  75490     },
  75491 #endif /* chips */
  75492 
  75493 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  75494     defined(BCM_56334_B0)
  75495     { /* SOC_REG_INT_XPAUSE_RX_OPCODE_BCM56334_A0r */
  75496         soc_block_list[14],
  75497         soc_portreg,
  75498         1,
  75499         0,
  75500         0x81f,
  75501         0,
  75502         0,
  75503         1,
  75504         soc_XPAUSE_RX_OPCODEr_fields,
  75505         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75506         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75507         -1,
  75508         -1,
  75509     },
  75510 #endif /* chips */
  75511 
  75512 #if defined(BCM_56340_A0)
  75513     { /* SOC_REG_INT_XPAUSE_RX_OPCODE_BCM56340_A0r */
  75514         soc_block_list[214],
  75515         soc_portreg,
  75516         1,
  75517         0,
  75518         0x20f00,
  75519         0,
  75520         0,
  75521         1,
  75522         soc_XPAUSE_RX_OPCODE_BCM56640_A0r_fields,
  75523         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75524         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75525         -1,
  75526         -1,
  75527     },
  75528 #endif /* chips */
  75529 
  75530 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  75531     { /* SOC_REG_INT_XPAUSE_RX_OPCODE_BCM56440_A0r */
  75532         soc_block_list[83],
  75533         soc_portreg,
  75534         1,
  75535         0,
  75536         0x20f,
  75537         0,
  75538         0,
  75539         1,
  75540         soc_XPAUSE_RX_OPCODEr_fields,
  75541         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75542         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75543         -1,
  75544         -1,
  75545     },
  75546 #endif /* chips */
  75547 
  75548 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  75549     defined(BCM_56450_B1)
  75550     { /* SOC_REG_INT_XPAUSE_RX_OPCODE_BCM56450_A0r */
  75551         soc_block_list[83],
  75552         soc_portreg,
  75553         1,
  75554         0,
  75555         0x20f00,
  75556         0,
  75557         0,
  75558         1,
  75559         soc_XPAUSE_RX_OPCODE_BCM56640_A0r_fields,
  75560         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75561         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75562         -1,
  75563         -1,
  75564     },
  75565 #endif /* chips */
  75566 
  75567 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  75568     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  75569     { /* SOC_REG_INT_XPAUSE_RX_OPCODE_BCM56624_A0r */
  75570         soc_block_list[204],
  75571         soc_portreg,
  75572         1,
  75573         0,
  75574         0x81f,
  75575         0,
  75576         0,
  75577         1,
  75578         soc_XPAUSE_RX_OPCODEr_fields,
  75579         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75580         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75581         -1,
  75582         -1,
  75583     },
  75584 #endif /* chips */
  75585 
  75586 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75587     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75588     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75589     { /* SOC_REG_INT_XPAUSE_RX_OPCODE_BCM56634_A0r */
  75590         soc_block_list[208],
  75591         soc_portreg,
  75592         1,
  75593         0,
  75594         0x81f,
  75595         0,
  75596         0,
  75597         1,
  75598         soc_XPAUSE_RX_OPCODEr_fields,
  75599         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75600         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75601         -1,
  75602         -1,
  75603     },
  75604 #endif /* chips */
  75605 
  75606 #if defined(BCM_56640_A0)
  75607     { /* SOC_REG_INT_XPAUSE_RX_OPCODE_BCM56640_A0r */
  75608         soc_block_list[212],
  75609         soc_portreg,
  75610         1,
  75611         0,
  75612         0x20f00,
  75613         0,
  75614         0,
  75615         1,
  75616         soc_XPAUSE_RX_OPCODE_BCM56640_A0r_fields,
  75617         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75618         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75619         -1,
  75620         -1,
  75621     },
  75622 #endif /* chips */
  75623 
  75624 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  75625     defined(BCM_56820_A0)
  75626     { /* SOC_REG_INT_XPAUSE_RX_OPCODE_BCM56800_A0r */
  75627         soc_block_list[9],
  75628         soc_portreg,
  75629         1,
  75630         0,
  75631         0x81f,
  75632         0,
  75633         0,
  75634         1,
  75635         soc_XPAUSE_RX_OPCODEr_fields,
  75636         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75637         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75638         -1,
  75639         -1,
  75640     },
  75641 #endif /* chips */
  75642 
  75643 #if defined(BCM_56840_A0)
  75644     { /* SOC_REG_INT_XPAUSE_RX_OPCODE_BCM56840_A0r */
  75645         soc_block_list[16],
  75646         soc_portreg,
  75647         1,
  75648         0,
  75649         0x217,
  75650         0,
  75651         0,
  75652         1,
  75653         soc_XPAUSE_RX_OPCODEr_fields,
  75654         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75655         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75656         -1,
  75657         -1,
  75658     },
  75659 #endif /* chips */
  75660 
  75661 #if defined(BCM_56840_B0)
  75662     { /* SOC_REG_INT_XPAUSE_RX_OPCODE_BCM56840_B0r */
  75663         soc_block_list[16],
  75664         soc_portreg,
  75665         1,
  75666         0,
  75667         0x217,
  75668         0,
  75669         0,
  75670         1,
  75671         soc_XPAUSE_RX_OPCODEr_fields,
  75672         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75673         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75674         -1,
  75675         -1,
  75676     },
  75677 #endif /* chips */
  75678 
  75679 #if defined(BCM_88732_A0)
  75680     { /* SOC_REG_INT_XPAUSE_RX_OPCODE_BCM88732_A0r */
  75681         soc_block_list[16],
  75682         soc_portreg,
  75683         1,
  75684         0,
  75685         0x217,
  75686         0,
  75687         0,
  75688         1,
  75689         soc_XPAUSE_RX_OPCODEr_fields,
  75690         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  75691         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75692         -1,
  75693         -1,
  75694     },
  75695 #endif /* chips */
  75696 
  75697 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  75698     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  75699     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VALr */
  75700         soc_block_list[0],
  75701         soc_genreg,
  75702         1,
  75703         0,
  75704         0x80001,
  75705         0,
  75706         0,
  75707         1,
  75708         soc_XPAUSE_TX_PKT_XOFF_VALr_fields,
  75709         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75710         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75711         -1,
  75712         -1,
  75713     },
  75714 #endif /* chips */
  75715 
  75716 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  75717     defined(BCM_56334_B0)
  75718     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VAL_BCM56334_A0r */
  75719         soc_block_list[14],
  75720         soc_portreg,
  75721         1,
  75722         0,
  75723         0x801,
  75724         0,
  75725         0,
  75726         1,
  75727         soc_XPAUSE_TX_PKT_XOFF_VALr_fields,
  75728         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75729         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75730         -1,
  75731         -1,
  75732     },
  75733 #endif /* chips */
  75734 
  75735 #if defined(BCM_56340_A0)
  75736     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VAL_BCM56340_A0r */
  75737         soc_block_list[214],
  75738         soc_portreg,
  75739         1,
  75740         0,
  75741         0x20100,
  75742         0,
  75743         0,
  75744         1,
  75745         soc_XPAUSE_TX_PKT_XOFF_VAL_BCM56640_A0r_fields,
  75746         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75747         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75748         -1,
  75749         -1,
  75750     },
  75751 #endif /* chips */
  75752 
  75753 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  75754     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VAL_BCM56440_A0r */
  75755         soc_block_list[83],
  75756         soc_portreg,
  75757         1,
  75758         0,
  75759         0x201,
  75760         0,
  75761         0,
  75762         1,
  75763         soc_XPAUSE_TX_PKT_XOFF_VALr_fields,
  75764         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75765         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75766         -1,
  75767         -1,
  75768     },
  75769 #endif /* chips */
  75770 
  75771 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  75772     defined(BCM_56450_B1)
  75773     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VAL_BCM56450_A0r */
  75774         soc_block_list[83],
  75775         soc_portreg,
  75776         1,
  75777         0,
  75778         0x20100,
  75779         0,
  75780         0,
  75781         1,
  75782         soc_XPAUSE_TX_PKT_XOFF_VAL_BCM56640_A0r_fields,
  75783         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75784         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75785         -1,
  75786         -1,
  75787     },
  75788 #endif /* chips */
  75789 
  75790 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  75791     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  75792     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VAL_BCM56624_A0r */
  75793         soc_block_list[204],
  75794         soc_portreg,
  75795         1,
  75796         0,
  75797         0x801,
  75798         0,
  75799         0,
  75800         1,
  75801         soc_XPAUSE_TX_PKT_XOFF_VALr_fields,
  75802         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75803         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75804         -1,
  75805         -1,
  75806     },
  75807 #endif /* chips */
  75808 
  75809 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  75810     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  75811     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  75812     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VAL_BCM56634_A0r */
  75813         soc_block_list[208],
  75814         soc_portreg,
  75815         1,
  75816         0,
  75817         0x801,
  75818         0,
  75819         0,
  75820         1,
  75821         soc_XPAUSE_TX_PKT_XOFF_VALr_fields,
  75822         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75823         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75824         -1,
  75825         -1,
  75826     },
  75827 #endif /* chips */
  75828 
  75829 #if defined(BCM_56640_A0)
  75830     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VAL_BCM56640_A0r */
  75831         soc_block_list[212],
  75832         soc_portreg,
  75833         1,
  75834         0,
  75835         0x20100,
  75836         0,
  75837         0,
  75838         1,
  75839         soc_XPAUSE_TX_PKT_XOFF_VAL_BCM56640_A0r_fields,
  75840         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75841         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75842         -1,
  75843         -1,
  75844     },
  75845 #endif /* chips */
  75846 
  75847 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  75848     defined(BCM_56820_A0)
  75849     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VAL_BCM56800_A0r */
  75850         soc_block_list[9],
  75851         soc_portreg,
  75852         1,
  75853         0,
  75854         0x801,
  75855         0,
  75856         0,
  75857         1,
  75858         soc_XPAUSE_TX_PKT_XOFF_VALr_fields,
  75859         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75860         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75861         -1,
  75862         -1,
  75863     },
  75864 #endif /* chips */
  75865 
  75866 #if defined(BCM_56840_A0)
  75867     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VAL_BCM56840_A0r */
  75868         soc_block_list[16],
  75869         soc_portreg,
  75870         1,
  75871         0,
  75872         0x201,
  75873         0,
  75874         0,
  75875         1,
  75876         soc_XPAUSE_TX_PKT_XOFF_VALr_fields,
  75877         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75878         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75879         -1,
  75880         -1,
  75881     },
  75882 #endif /* chips */
  75883 
  75884 #if defined(BCM_56840_B0)
  75885     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VAL_BCM56840_B0r */
  75886         soc_block_list[16],
  75887         soc_portreg,
  75888         1,
  75889         0,
  75890         0x201,
  75891         0,
  75892         0,
  75893         1,
  75894         soc_XPAUSE_TX_PKT_XOFF_VALr_fields,
  75895         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75896         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75897         -1,
  75898         -1,
  75899     },
  75900 #endif /* chips */
  75901 
  75902 #if defined(BCM_88732_A0)
  75903     { /* SOC_REG_INT_XPAUSE_TX_PKT_XOFF_VAL_BCM88732_A0r */
  75904         soc_block_list[16],
  75905         soc_portreg,
  75906         1,
  75907         0,
  75908         0x201,
  75909         0,
  75910         0,
  75911         1,
  75912         soc_XPAUSE_TX_PKT_XOFF_VALr_fields,
  75913         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75914         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75915         -1,
  75916         -1,
  75917     },
  75918 #endif /* chips */
  75919 
  75920 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  75921     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  75922     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VALr */
  75923         soc_block_list[0],
  75924         soc_genreg,
  75925         1,
  75926         0,
  75927         0x80002,
  75928         0,
  75929         0,
  75930         1,
  75931         soc_XPAUSE_WATCHDOG_INIT_VALr_fields,
  75932         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75933         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75934         -1,
  75935         -1,
  75936     },
  75937 #endif /* chips */
  75938 
  75939 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  75940     defined(BCM_56334_B0)
  75941     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VAL_BCM56334_A0r */
  75942         soc_block_list[14],
  75943         soc_portreg,
  75944         1,
  75945         0,
  75946         0x802,
  75947         0,
  75948         0,
  75949         1,
  75950         soc_XPAUSE_WATCHDOG_INIT_VALr_fields,
  75951         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75952         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75953         -1,
  75954         -1,
  75955     },
  75956 #endif /* chips */
  75957 
  75958 #if defined(BCM_56340_A0)
  75959     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VAL_BCM56340_A0r */
  75960         soc_block_list[214],
  75961         soc_portreg,
  75962         1,
  75963         0,
  75964         0x20200,
  75965         0,
  75966         0,
  75967         1,
  75968         soc_XPAUSE_WATCHDOG_INIT_VAL_BCM56640_A0r_fields,
  75969         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75970         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75971         -1,
  75972         -1,
  75973     },
  75974 #endif /* chips */
  75975 
  75976 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  75977     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VAL_BCM56440_A0r */
  75978         soc_block_list[83],
  75979         soc_portreg,
  75980         1,
  75981         0,
  75982         0x202,
  75983         0,
  75984         0,
  75985         1,
  75986         soc_XPAUSE_WATCHDOG_INIT_VALr_fields,
  75987         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  75988         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75989         -1,
  75990         -1,
  75991     },
  75992 #endif /* chips */
  75993 
  75994 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  75995     defined(BCM_56450_B1)
  75996     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VAL_BCM56450_A0r */
  75997         soc_block_list[83],
  75998         soc_portreg,
  75999         1,
  76000         0,
  76001         0x20200,
  76002         0,
  76003         0,
  76004         1,
  76005         soc_XPAUSE_WATCHDOG_INIT_VAL_BCM56640_A0r_fields,
  76006         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  76007         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76008         -1,
  76009         -1,
  76010     },
  76011 #endif /* chips */
  76012 
  76013 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  76014     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  76015     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VAL_BCM56624_A0r */
  76016         soc_block_list[204],
  76017         soc_portreg,
  76018         1,
  76019         0,
  76020         0x802,
  76021         0,
  76022         0,
  76023         1,
  76024         soc_XPAUSE_WATCHDOG_INIT_VALr_fields,
  76025         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  76026         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76027         -1,
  76028         -1,
  76029     },
  76030 #endif /* chips */
  76031 
  76032 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  76033     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  76034     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  76035     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VAL_BCM56634_A0r */
  76036         soc_block_list[208],
  76037         soc_portreg,
  76038         1,
  76039         0,
  76040         0x802,
  76041         0,
  76042         0,
  76043         1,
  76044         soc_XPAUSE_WATCHDOG_INIT_VALr_fields,
  76045         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  76046         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76047         -1,
  76048         -1,
  76049     },
  76050 #endif /* chips */
  76051 
  76052 #if defined(BCM_56640_A0)
  76053     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VAL_BCM56640_A0r */
  76054         soc_block_list[212],
  76055         soc_portreg,
  76056         1,
  76057         0,
  76058         0x20200,
  76059         0,
  76060         0,
  76061         1,
  76062         soc_XPAUSE_WATCHDOG_INIT_VAL_BCM56640_A0r_fields,
  76063         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  76064         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76065         -1,
  76066         -1,
  76067     },
  76068 #endif /* chips */
  76069 
  76070 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  76071     defined(BCM_56820_A0)
  76072     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VAL_BCM56800_A0r */
  76073         soc_block_list[9],
  76074         soc_portreg,
  76075         1,
  76076         0,
  76077         0x802,
  76078         0,
  76079         0,
  76080         1,
  76081         soc_XPAUSE_WATCHDOG_INIT_VALr_fields,
  76082         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  76083         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76084         -1,
  76085         -1,
  76086     },
  76087 #endif /* chips */
  76088 
  76089 #if defined(BCM_56840_A0)
  76090     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VAL_BCM56840_A0r */
  76091         soc_block_list[16],
  76092         soc_portreg,
  76093         1,
  76094         0,
  76095         0x202,
  76096         0,
  76097         0,
  76098         1,
  76099         soc_XPAUSE_WATCHDOG_INIT_VALr_fields,
  76100         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  76101         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76102         -1,
  76103         -1,
  76104     },
  76105 #endif /* chips */
  76106 
  76107 #if defined(BCM_56840_B0)
  76108     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VAL_BCM56840_B0r */
  76109         soc_block_list[16],
  76110         soc_portreg,
  76111         1,
  76112         0,
  76113         0x202,
  76114         0,
  76115         0,
  76116         1,
  76117         soc_XPAUSE_WATCHDOG_INIT_VALr_fields,
  76118         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  76119         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76120         -1,
  76121         -1,
  76122     },
  76123 #endif /* chips */
  76124 
  76125 #if defined(BCM_88732_A0)
  76126     { /* SOC_REG_INT_XPAUSE_WATCHDOG_INIT_VAL_BCM88732_A0r */
  76127         soc_block_list[16],
  76128         soc_portreg,
  76129         1,
  76130         0,
  76131         0x202,
  76132         0,
  76133         0,
  76134         1,
  76135         soc_XPAUSE_WATCHDOG_INIT_VALr_fields,
  76136         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  76137         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76138         -1,
  76139         -1,
  76140     },
  76141 #endif /* chips */
  76142 
  76143 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  76144     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  76145     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESHr */
  76146         soc_block_list[0],
  76147         soc_genreg,
  76148         1,
  76149         0,
  76150         0x80003,
  76151         0,
  76152         0,
  76153         1,
  76154         soc_XPAUSE_WATCHDOG_THRESHr_fields,
  76155         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76156         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76157         -1,
  76158         -1,
  76159     },
  76160 #endif /* chips */
  76161 
  76162 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  76163     defined(BCM_56334_B0)
  76164     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESH_BCM56334_A0r */
  76165         soc_block_list[14],
  76166         soc_portreg,
  76167         1,
  76168         0,
  76169         0x803,
  76170         0,
  76171         0,
  76172         1,
  76173         soc_XPAUSE_WATCHDOG_THRESHr_fields,
  76174         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76175         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76176         -1,
  76177         -1,
  76178     },
  76179 #endif /* chips */
  76180 
  76181 #if defined(BCM_56340_A0)
  76182     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESH_BCM56340_A0r */
  76183         soc_block_list[214],
  76184         soc_portreg,
  76185         1,
  76186         0,
  76187         0x20300,
  76188         0,
  76189         0,
  76190         1,
  76191         soc_XPAUSE_WATCHDOG_THRESH_BCM56640_A0r_fields,
  76192         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76193         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76194         -1,
  76195         -1,
  76196     },
  76197 #endif /* chips */
  76198 
  76199 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76200     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESH_BCM56440_A0r */
  76201         soc_block_list[83],
  76202         soc_portreg,
  76203         1,
  76204         0,
  76205         0x203,
  76206         0,
  76207         0,
  76208         1,
  76209         soc_XPAUSE_WATCHDOG_THRESHr_fields,
  76210         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76211         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76212         -1,
  76213         -1,
  76214     },
  76215 #endif /* chips */
  76216 
  76217 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76218     defined(BCM_56450_B1)
  76219     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESH_BCM56450_A0r */
  76220         soc_block_list[83],
  76221         soc_portreg,
  76222         1,
  76223         0,
  76224         0x20300,
  76225         0,
  76226         0,
  76227         1,
  76228         soc_XPAUSE_WATCHDOG_THRESH_BCM56640_A0r_fields,
  76229         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76230         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76231         -1,
  76232         -1,
  76233     },
  76234 #endif /* chips */
  76235 
  76236 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  76237     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  76238     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESH_BCM56624_A0r */
  76239         soc_block_list[204],
  76240         soc_portreg,
  76241         1,
  76242         0,
  76243         0x803,
  76244         0,
  76245         0,
  76246         1,
  76247         soc_XPAUSE_WATCHDOG_THRESHr_fields,
  76248         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76249         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76250         -1,
  76251         -1,
  76252     },
  76253 #endif /* chips */
  76254 
  76255 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  76256     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  76257     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  76258     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESH_BCM56634_A0r */
  76259         soc_block_list[208],
  76260         soc_portreg,
  76261         1,
  76262         0,
  76263         0x803,
  76264         0,
  76265         0,
  76266         1,
  76267         soc_XPAUSE_WATCHDOG_THRESHr_fields,
  76268         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76269         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76270         -1,
  76271         -1,
  76272     },
  76273 #endif /* chips */
  76274 
  76275 #if defined(BCM_56640_A0)
  76276     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESH_BCM56640_A0r */
  76277         soc_block_list[212],
  76278         soc_portreg,
  76279         1,
  76280         0,
  76281         0x20300,
  76282         0,
  76283         0,
  76284         1,
  76285         soc_XPAUSE_WATCHDOG_THRESH_BCM56640_A0r_fields,
  76286         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76287         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76288         -1,
  76289         -1,
  76290     },
  76291 #endif /* chips */
  76292 
  76293 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  76294     defined(BCM_56820_A0)
  76295     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESH_BCM56800_A0r */
  76296         soc_block_list[9],
  76297         soc_portreg,
  76298         1,
  76299         0,
  76300         0x803,
  76301         0,
  76302         0,
  76303         1,
  76304         soc_XPAUSE_WATCHDOG_THRESHr_fields,
  76305         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76306         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76307         -1,
  76308         -1,
  76309     },
  76310 #endif /* chips */
  76311 
  76312 #if defined(BCM_56840_A0)
  76313     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESH_BCM56840_A0r */
  76314         soc_block_list[16],
  76315         soc_portreg,
  76316         1,
  76317         0,
  76318         0x203,
  76319         0,
  76320         0,
  76321         1,
  76322         soc_XPAUSE_WATCHDOG_THRESHr_fields,
  76323         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76324         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76325         -1,
  76326         -1,
  76327     },
  76328 #endif /* chips */
  76329 
  76330 #if defined(BCM_56840_B0)
  76331     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESH_BCM56840_B0r */
  76332         soc_block_list[16],
  76333         soc_portreg,
  76334         1,
  76335         0,
  76336         0x203,
  76337         0,
  76338         0,
  76339         1,
  76340         soc_XPAUSE_WATCHDOG_THRESHr_fields,
  76341         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76342         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76343         -1,
  76344         -1,
  76345     },
  76346 #endif /* chips */
  76347 
  76348 #if defined(BCM_88732_A0)
  76349     { /* SOC_REG_INT_XPAUSE_WATCHDOG_THRESH_BCM88732_A0r */
  76350         soc_block_list[16],
  76351         soc_portreg,
  76352         1,
  76353         0,
  76354         0x203,
  76355         0,
  76356         0,
  76357         1,
  76358         soc_XPAUSE_WATCHDOG_THRESHr_fields,
  76359         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  76360         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  76361         -1,
  76362         -1,
  76363     },
  76364 #endif /* chips */
  76365 
  76366 #if defined(BCM_56504_A0)
  76367     { /* SOC_REG_INT_XPORT_CONFIGr */
  76368         soc_block_list[0],
  76369         soc_genreg,
  76370         1,
  76371         0,
  76372         0x80000,
  76373         0,
  76374         0,
  76375         8,
  76376         soc_XPORT_CONFIGr_fields,
  76377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76378         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  76379         -1,
  76380         -1,
  76381     },
  76382 #endif /* chips */
  76383 
  76384 #if defined(BCM_56142_A0)
  76385     { /* SOC_REG_INT_XPORT_CONFIG_BCM56142_A0r */
  76386         soc_block_list[14],
  76387         soc_portreg,
  76388         1,
  76389         0,
  76390         0x800,
  76391         0,
  76392         0,
  76393         13,
  76394         soc_XPORT_CONFIG_BCM56142_A0r_fields,
  76395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76396         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  76397         -1,
  76398         -1,
  76399     },
  76400 #endif /* chips */
  76401 
  76402 #if defined(BCM_56260_A0)
  76403     { /* SOC_REG_INT_XPORT_CONFIG_BCM56260_A0r */
  76404         soc_block_list[83],
  76405         soc_portreg,
  76406         1,
  76407         0,
  76408         0x20000,
  76409         0,
  76410         0,
  76411         7,
  76412         soc_XPORT_CONFIG_BCM56260_A0r_fields,
  76413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76414         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  76415         -1,
  76416         -1,
  76417     },
  76418 #endif /* chips */
  76419 
  76420 #if defined(BCM_56260_B0)
  76421     { /* SOC_REG_INT_XPORT_CONFIG_BCM56260_B0r */
  76422         soc_block_list[83],
  76423         soc_portreg,
  76424         1,
  76425         0,
  76426         0x20000,
  76427         0,
  76428         0,
  76429         9,
  76430         soc_XPORT_CONFIG_BCM56260_B0r_fields,
  76431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76432         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  76433         -1,
  76434         -1,
  76435     },
  76436 #endif /* chips */
  76437 
  76438 #if defined(BCM_56270_A0)
  76439     { /* SOC_REG_INT_XPORT_CONFIG_BCM56270_A0r */
  76440         soc_block_list[83],
  76441         soc_portreg,
  76442         1,
  76443         0,
  76444         0x20000,
  76445         0,
  76446         0,
  76447         9,
  76448         soc_XPORT_CONFIG_BCM56260_B0r_fields,
  76449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76450         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  76451         -1,
  76452         -1,
  76453     },
  76454 #endif /* chips */
  76455 
  76456 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  76457     { /* SOC_REG_INT_XPORT_CONFIG_BCM56334_A0r */
  76458         soc_block_list[14],
  76459         soc_portreg,
  76460         1,
  76461         0,
  76462         0x800,
  76463         0,
  76464         0,
  76465         16,
  76466         soc_XPORT_CONFIG_BCM56334_A0r_fields,
  76467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76468         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  76469         -1,
  76470         -1,
  76471     },
  76472 #endif /* chips */
  76473 
  76474 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76475     { /* SOC_REG_INT_XPORT_CONFIG_BCM56440_A0r */
  76476         soc_block_list[83],
  76477         soc_portreg,
  76478         1,
  76479         0,
  76480         0x200,
  76481         0,
  76482         0,
  76483         13,
  76484         soc_XPORT_CONFIG_BCM56440_A0r_fields,
  76485         SOC_RESET_VAL_DEC(0x00080000, 0x00000000)
  76486         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  76487         -1,
  76488         -1,
  76489     },
  76490 #endif /* chips */
  76491 
  76492 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76493     defined(BCM_56450_B1)
  76494     { /* SOC_REG_INT_XPORT_CONFIG_BCM56450_A0r */
  76495         soc_block_list[83],
  76496         soc_portreg,
  76497         1,
  76498         0,
  76499         0x20000,
  76500         0,
  76501         0,
  76502         16,
  76503         soc_XPORT_CONFIG_BCM56450_A0r_fields,
  76504         SOC_RESET_VAL_DEC(0x00080000, 0x00000000)
  76505         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  76506         -1,
  76507         -1,
  76508     },
  76509 #endif /* chips */
  76510 
  76511 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  76512     defined(BCM_56514_A0)
  76513     { /* SOC_REG_INT_XPORT_CONFIG_BCM56504_B0r */
  76514         soc_block_list[0],
  76515         soc_genreg,
  76516         1,
  76517         0,
  76518         0x80000,
  76519         0,
  76520         0,
  76521         8,
  76522         soc_XPORT_CONFIG_BCM56504_B0r_fields,
  76523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76524         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  76525         -1,
  76526         -1,
  76527     },
  76528 #endif /* chips */
  76529 
  76530 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  76531     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  76532     { /* SOC_REG_INT_XPORT_CONFIG_BCM56624_A0r */
  76533         soc_block_list[204],
  76534         soc_portreg,
  76535         1,
  76536         0,
  76537         0x800,
  76538         0,
  76539         0,
  76540         15,
  76541         soc_XPORT_CONFIG_BCM56624_A0r_fields,
  76542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76543         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  76544         -1,
  76545         -1,
  76546     },
  76547 #endif /* chips */
  76548 
  76549 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \
  76550     defined(BCM_56685_A0)
  76551     { /* SOC_REG_INT_XPORT_CONFIG_BCM56634_A0r */
  76552         soc_block_list[208],
  76553         soc_portreg,
  76554         1,
  76555         0,
  76556         0x800,
  76557         0,
  76558         0,
  76559         16,
  76560         soc_XPORT_CONFIG_BCM56634_A0r_fields,
  76561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76562         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  76563         -1,
  76564         -1,
  76565     },
  76566 #endif /* chips */
  76567 
  76568 #if defined(BCM_56524_B0) || defined(BCM_56634_B0) || \
  76569     defined(BCM_56685_B0)
  76570     { /* SOC_REG_INT_XPORT_CONFIG_BCM56634_B0r */
  76571         soc_block_list[208],
  76572         soc_portreg,
  76573         1,
  76574         0,
  76575         0x800,
  76576         0,
  76577         0,
  76578         17,
  76579         soc_XPORT_CONFIG_BCM56634_B0r_fields,
  76580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76581         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  76582         -1,
  76583         -1,
  76584     },
  76585 #endif /* chips */
  76586 
  76587 #if defined(BCM_56800_A0)
  76588     { /* SOC_REG_INT_XPORT_CONFIG_BCM56800_A0r */
  76589         soc_block_list[9],
  76590         soc_portreg,
  76591         1,
  76592         0,
  76593         0x800,
  76594         0,
  76595         0,
  76596         12,
  76597         soc_XPORT_CONFIG_BCM56800_A0r_fields,
  76598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76599         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  76600         -1,
  76601         -1,
  76602     },
  76603 #endif /* chips */
  76604 
  76605 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  76606     { /* SOC_REG_INT_XPORT_CONFIG_BCM56820_A0r */
  76607         soc_block_list[9],
  76608         soc_portreg,
  76609         1,
  76610         0,
  76611         0x800,
  76612         0,
  76613         0,
  76614         15,
  76615         soc_XPORT_CONFIG_BCM56820_A0r_fields,
  76616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76617         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  76618         -1,
  76619         -1,
  76620     },
  76621 #endif /* chips */
  76622 
  76623 #if defined(BCM_88270_A0)
  76624     { /* SOC_REG_INT_XPORT_CONFIG_BCM88270_A0r */
  76625         soc_block_list[149],
  76626         soc_portreg,
  76627         1,
  76628         0,
  76629         0x20000,
  76630         0,
  76631         0,
  76632         2,
  76633         soc_XPORT_CONFIG_BCM88270_A0r_fields,
  76634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76635         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  76636         -1,
  76637         -1,
  76638     },
  76639 #endif /* chips */
  76640 
  76641 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  76642     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  76643     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  76644     { /* SOC_REG_INT_XPORT_ECC_CONTROLr */
  76645         soc_block_list[9],
  76646         soc_genreg,
  76647         1,
  76648         0,
  76649         0x80d04,
  76650         0,
  76651         0,
  76652         2,
  76653         soc_SPORT_ECC_CONTROLr_fields,
  76654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76655         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  76656         -1,
  76657         -1,
  76658     },
  76659 #endif /* chips */
  76660 
  76661 #if defined(BCM_56260_A0)
  76662     { /* SOC_REG_INT_XPORT_ECC_CONTROL_BCM56260_A0r */
  76663         soc_block_list[83],
  76664         soc_genreg,
  76665         1,
  76666         0,
  76667         0x2021700,
  76668         0,
  76669         0,
  76670         4,
  76671         soc_XPORT_ECC_CONTROL_BCM56260_A0r_fields,
  76672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76673         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  76674         -1,
  76675         -1,
  76676     },
  76677 #endif /* chips */
  76678 
  76679 #if defined(BCM_56260_B0)
  76680     { /* SOC_REG_INT_XPORT_ECC_CONTROL_BCM56260_B0r */
  76681         soc_block_list[83],
  76682         soc_genreg,
  76683         1,
  76684         0,
  76685         0x2021600,
  76686         0,
  76687         0,
  76688         4,
  76689         soc_XPORT_ECC_CONTROL_BCM56260_A0r_fields,
  76690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76691         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  76692         -1,
  76693         -1,
  76694     },
  76695 #endif /* chips */
  76696 
  76697 #if defined(BCM_56270_A0)
  76698     { /* SOC_REG_INT_XPORT_ECC_CONTROL_BCM56270_A0r */
  76699         soc_block_list[83],
  76700         soc_genreg,
  76701         1,
  76702         0,
  76703         0x2021600,
  76704         0,
  76705         0,
  76706         4,
  76707         soc_XPORT_ECC_CONTROL_BCM56260_A0r_fields,
  76708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76709         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  76710         -1,
  76711         -1,
  76712     },
  76713 #endif /* chips */
  76714 
  76715 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76716     { /* SOC_REG_INT_XPORT_ECC_CONTROL_BCM56440_A0r */
  76717         soc_block_list[83],
  76718         soc_genreg,
  76719         1,
  76720         0,
  76721         0x8023f,
  76722         0,
  76723         0,
  76724         4,
  76725         soc_XPORT_ECC_CONTROLr_fields,
  76726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76727         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  76728         -1,
  76729         -1,
  76730     },
  76731 #endif /* chips */
  76732 
  76733 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76734     defined(BCM_56450_B1)
  76735     { /* SOC_REG_INT_XPORT_ECC_CONTROL_BCM56450_A0r */
  76736         soc_block_list[83],
  76737         soc_genreg,
  76738         1,
  76739         0,
  76740         0x2024300,
  76741         0,
  76742         0,
  76743         4,
  76744         soc_XPORT_ECC_CONTROL_BCM56450_A0r_fields,
  76745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76746         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  76747         -1,
  76748         -1,
  76749     },
  76750 #endif /* chips */
  76751 
  76752 #if defined(BCM_88270_A0)
  76753     { /* SOC_REG_INT_XPORT_ECC_CONTROL_BCM88270_A0r */
  76754         soc_block_list[149],
  76755         soc_genreg,
  76756         1,
  76757         0,
  76758         0x2021000,
  76759         0,
  76760         0,
  76761         2,
  76762         soc_XPORT_ECC_CONTROL_BCM88270_A0r_fields,
  76763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76764         SOC_RESET_MASK_DEC(0x00000006, 0x00000000)
  76765         -1,
  76766         -1,
  76767     },
  76768 #endif /* chips */
  76769 
  76770 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76771     { /* SOC_REG_INT_XPORT_EEE_DURATION_TIMER_PULSEr */
  76772         soc_block_list[83],
  76773         soc_genreg,
  76774         1,
  76775         0,
  76776         0x80224,
  76777         0,
  76778         0,
  76779         1,
  76780         soc_XLPORT_EEE_DURATION_TIMER_PULSEr_fields,
  76781         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  76782         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  76783         -1,
  76784         -1,
  76785     },
  76786 #endif /* chips */
  76787 
  76788 #if defined(BCM_56260_A0)
  76789     { /* SOC_REG_INT_XPORT_EEE_DURATION_TIMER_PULSE_BCM56260_A0r */
  76790         soc_block_list[83],
  76791         soc_genreg,
  76792         1,
  76793         0,
  76794         0x2021000,
  76795         0,
  76796         0,
  76797         1,
  76798         soc_CLPORT_EEE_DURATION_TIMER_PULSEr_fields,
  76799         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  76800         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  76801         -1,
  76802         -1,
  76803     },
  76804 #endif /* chips */
  76805 
  76806 #if defined(BCM_56260_B0)
  76807     { /* SOC_REG_INT_XPORT_EEE_DURATION_TIMER_PULSE_BCM56260_B0r */
  76808         soc_block_list[83],
  76809         soc_genreg,
  76810         1,
  76811         0,
  76812         0x2020f00,
  76813         0,
  76814         0,
  76815         1,
  76816         soc_CLPORT_EEE_DURATION_TIMER_PULSEr_fields,
  76817         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  76818         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  76819         -1,
  76820         -1,
  76821     },
  76822 #endif /* chips */
  76823 
  76824 #if defined(BCM_56270_A0)
  76825     { /* SOC_REG_INT_XPORT_EEE_DURATION_TIMER_PULSE_BCM56270_A0r */
  76826         soc_block_list[83],
  76827         soc_genreg,
  76828         1,
  76829         0,
  76830         0x2020f00,
  76831         0,
  76832         0,
  76833         1,
  76834         soc_CLPORT_EEE_DURATION_TIMER_PULSEr_fields,
  76835         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  76836         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  76837         -1,
  76838         -1,
  76839     },
  76840 #endif /* chips */
  76841 
  76842 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76843     defined(BCM_56450_B1)
  76844     { /* SOC_REG_INT_XPORT_EEE_DURATION_TIMER_PULSE_BCM56450_A0r */
  76845         soc_block_list[83],
  76846         soc_genreg,
  76847         1,
  76848         0,
  76849         0x2022400,
  76850         0,
  76851         0,
  76852         1,
  76853         soc_PORT_EEE_DURATION_TIMER_PULSE_BCM56640_A0r_fields,
  76854         SOC_RESET_VAL_DEC(0x000000ec, 0x00000000)
  76855         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  76856         -1,
  76857         -1,
  76858     },
  76859 #endif /* chips */
  76860 
  76861 #if defined(BCM_88270_A0)
  76862     { /* SOC_REG_INT_XPORT_EEE_DURATION_TIMER_PULSE_BCM88270_A0r */
  76863         soc_block_list[149],
  76864         soc_genreg,
  76865         1,
  76866         0,
  76867         0x2020d00,
  76868         0,
  76869         0,
  76870         1,
  76871         soc_XPORT_EEE_DURATION_TIMER_PULSEr_fields,
  76872         SOC_RESET_VAL_DEC(0x0000061a, 0x00000000)
  76873         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  76874         -1,
  76875         -1,
  76876     },
  76877 #endif /* chips */
  76878 
  76879 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  76880     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  76881     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  76882     { /* SOC_REG_INT_XPORT_FORCE_DOUBLE_BIT_ERRORr */
  76883         soc_block_list[9],
  76884         soc_genreg,
  76885         1,
  76886         0,
  76887         0x80d05,
  76888         0,
  76889         0,
  76890         2,
  76891         soc_SPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  76892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76893         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76894         -1,
  76895         -1,
  76896     },
  76897 #endif /* chips */
  76898 
  76899 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  76900     { /* SOC_REG_INT_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56260_A0r */
  76901         soc_block_list[83],
  76902         soc_genreg,
  76903         1,
  76904         0,
  76905         0x2021800,
  76906         0,
  76907         0,
  76908         11,
  76909         soc_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56260_A0r_fields,
  76910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76912         -1,
  76913         -1,
  76914     },
  76915 #endif /* chips */
  76916 
  76917 #if defined(BCM_56260_B0)
  76918     { /* SOC_REG_INT_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56260_B0r */
  76919         soc_block_list[83],
  76920         soc_genreg,
  76921         1,
  76922         0,
  76923         0x2021700,
  76924         0,
  76925         0,
  76926         11,
  76927         soc_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56260_A0r_fields,
  76928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76929         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76930         -1,
  76931         -1,
  76932     },
  76933 #endif /* chips */
  76934 
  76935 #if defined(BCM_56270_A0)
  76936     { /* SOC_REG_INT_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56270_A0r */
  76937         soc_block_list[83],
  76938         soc_genreg,
  76939         1,
  76940         0,
  76941         0x2021700,
  76942         0,
  76943         0,
  76944         11,
  76945         soc_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56260_A0r_fields,
  76946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76947         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76948         -1,
  76949         -1,
  76950     },
  76951 #endif /* chips */
  76952 
  76953 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  76954     { /* SOC_REG_INT_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56440_A0r */
  76955         soc_block_list[83],
  76956         soc_genreg,
  76957         1,
  76958         0,
  76959         0x80240,
  76960         0,
  76961         0,
  76962         15,
  76963         soc_XPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  76964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76965         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76966         -1,
  76967         -1,
  76968     },
  76969 #endif /* chips */
  76970 
  76971 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  76972     defined(BCM_56450_B1)
  76973     { /* SOC_REG_INT_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56450_A0r */
  76974         soc_block_list[83],
  76975         soc_genreg,
  76976         1,
  76977         0,
  76978         0x2024400,
  76979         0,
  76980         0,
  76981         15,
  76982         soc_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56450_A0r_fields,
  76983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76984         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76985         -1,
  76986         -1,
  76987     },
  76988 #endif /* chips */
  76989 
  76990 #if defined(BCM_88270_A0)
  76991     { /* SOC_REG_INT_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM88270_A0r */
  76992         soc_block_list[149],
  76993         soc_genreg,
  76994         1,
  76995         0,
  76996         0x2021100,
  76997         0,
  76998         0,
  76999         9,
  77000         soc_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM88270_A0r_fields,
  77001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77002         SOC_RESET_MASK_DEC(0x000003fe, 0x00000000)
  77003         -1,
  77004         -1,
  77005     },
  77006 #endif /* chips */
  77007 
  77008 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77009     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77010     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77011     { /* SOC_REG_INT_XPORT_FORCE_SINGLE_BIT_ERRORr */
  77012         soc_block_list[9],
  77013         soc_genreg,
  77014         1,
  77015         0,
  77016         0x80d06,
  77017         0,
  77018         0,
  77019         2,
  77020         soc_SPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  77021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77022         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77023         -1,
  77024         -1,
  77025     },
  77026 #endif /* chips */
  77027 
  77028 #if defined(BCM_56260_A0)
  77029     { /* SOC_REG_INT_XPORT_FORCE_SINGLE_BIT_ERROR_BCM56260_A0r */
  77030         soc_block_list[83],
  77031         soc_genreg,
  77032         1,
  77033         0,
  77034         0x2021900,
  77035         0,
  77036         0,
  77037         11,
  77038         soc_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56260_A0r_fields,
  77039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77040         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77041         -1,
  77042         -1,
  77043     },
  77044 #endif /* chips */
  77045 
  77046 #if defined(BCM_56270_A0)
  77047     { /* SOC_REG_INT_XPORT_FORCE_SINGLE_BIT_ERROR_BCM56270_A0r */
  77048         soc_block_list[83],
  77049         soc_genreg,
  77050         1,
  77051         0,
  77052         0x2021800,
  77053         0,
  77054         0,
  77055         11,
  77056         soc_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56260_A0r_fields,
  77057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77058         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77059         -1,
  77060         -1,
  77061     },
  77062 #endif /* chips */
  77063 
  77064 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77065     { /* SOC_REG_INT_XPORT_FORCE_SINGLE_BIT_ERROR_BCM56440_A0r */
  77066         soc_block_list[83],
  77067         soc_genreg,
  77068         1,
  77069         0,
  77070         0x80241,
  77071         0,
  77072         0,
  77073         15,
  77074         soc_XPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  77075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77076         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77077         -1,
  77078         -1,
  77079     },
  77080 #endif /* chips */
  77081 
  77082 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77083     defined(BCM_56450_B1)
  77084     { /* SOC_REG_INT_XPORT_FORCE_SINGLE_BIT_ERROR_BCM56450_A0r */
  77085         soc_block_list[83],
  77086         soc_genreg,
  77087         1,
  77088         0,
  77089         0x2024500,
  77090         0,
  77091         0,
  77092         15,
  77093         soc_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56450_A0r_fields,
  77094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77095         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77096         -1,
  77097         -1,
  77098     },
  77099 #endif /* chips */
  77100 
  77101 #if defined(BCM_88270_A0)
  77102     { /* SOC_REG_INT_XPORT_FORCE_SINGLE_BIT_ERROR_BCM88270_A0r */
  77103         soc_block_list[149],
  77104         soc_genreg,
  77105         1,
  77106         0,
  77107         0x2021200,
  77108         0,
  77109         0,
  77110         9,
  77111         soc_XPORT_FORCE_SINGLE_BIT_ERRORr_fields,
  77112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77113         SOC_RESET_MASK_DEC(0x000003fe, 0x00000000)
  77114         -1,
  77115         -1,
  77116     },
  77117 #endif /* chips */
  77118 
  77119 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77120     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77121     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77122     { /* SOC_REG_INT_XPORT_INTR_ENABLEr */
  77123         soc_block_list[9],
  77124         soc_genreg,
  77125         1,
  77126         0,
  77127         0x80d0a,
  77128         0,
  77129         0,
  77130         2,
  77131         soc_SPORT_INTR_ENABLEr_fields,
  77132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77133         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  77134         -1,
  77135         -1,
  77136     },
  77137 #endif /* chips */
  77138 
  77139 #if defined(BCM_56260_A0)
  77140     { /* SOC_REG_INT_XPORT_INTR_ENABLE_BCM56260_A0r */
  77141         soc_block_list[83],
  77142         soc_genreg,
  77143         1,
  77144         0,
  77145         0x2022600,
  77146         0,
  77147         0,
  77148         11,
  77149         soc_XPORT_INTR_ENABLE_BCM56260_A0r_fields,
  77150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77151         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77152         -1,
  77153         -1,
  77154     },
  77155 #endif /* chips */
  77156 
  77157 #if defined(BCM_56260_B0)
  77158     { /* SOC_REG_INT_XPORT_INTR_ENABLE_BCM56260_B0r */
  77159         soc_block_list[83],
  77160         soc_genreg,
  77161         1,
  77162         0,
  77163         0x2022500,
  77164         0,
  77165         0,
  77166         11,
  77167         soc_XPORT_INTR_ENABLE_BCM56260_A0r_fields,
  77168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77169         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77170         -1,
  77171         -1,
  77172     },
  77173 #endif /* chips */
  77174 
  77175 #if defined(BCM_56270_A0)
  77176     { /* SOC_REG_INT_XPORT_INTR_ENABLE_BCM56270_A0r */
  77177         soc_block_list[83],
  77178         soc_genreg,
  77179         1,
  77180         0,
  77181         0x2022600,
  77182         0,
  77183         0,
  77184         11,
  77185         soc_XPORT_INTR_ENABLE_BCM56260_A0r_fields,
  77186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77187         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77188         -1,
  77189         -1,
  77190     },
  77191 #endif /* chips */
  77192 
  77193 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77194     { /* SOC_REG_INT_XPORT_INTR_ENABLE_BCM56440_A0r */
  77195         soc_block_list[83],
  77196         soc_genreg,
  77197         1,
  77198         0,
  77199         0x80252,
  77200         0,
  77201         0,
  77202         15,
  77203         soc_XPORT_INTR_ENABLEr_fields,
  77204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77205         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  77206         -1,
  77207         -1,
  77208     },
  77209 #endif /* chips */
  77210 
  77211 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77212     defined(BCM_56450_B1)
  77213     { /* SOC_REG_INT_XPORT_INTR_ENABLE_BCM56450_A0r */
  77214         soc_block_list[83],
  77215         soc_genreg,
  77216         1,
  77217         0,
  77218         0x2025600,
  77219         0,
  77220         0,
  77221         15,
  77222         soc_XPORT_INTR_ENABLE_BCM56450_A0r_fields,
  77223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77224         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  77225         -1,
  77226         -1,
  77227     },
  77228 #endif /* chips */
  77229 
  77230 #if defined(BCM_88270_A0)
  77231     { /* SOC_REG_INT_XPORT_INTR_ENABLE_BCM88270_A0r */
  77232         soc_block_list[149],
  77233         soc_genreg,
  77234         1,
  77235         0,
  77236         0x2022000,
  77237         0,
  77238         0,
  77239         11,
  77240         soc_XPORT_INTR_ENABLE_BCM88270_A0r_fields,
  77241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77242         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77243         -1,
  77244         -1,
  77245     },
  77246 #endif /* chips */
  77247 
  77248 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77249     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77250     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77251     { /* SOC_REG_INT_XPORT_INTR_STATUSr */
  77252         soc_block_list[9],
  77253         soc_genreg,
  77254         1,
  77255         0,
  77256         0x80d09,
  77257         SOC_REG_FLAG_RO,
  77258         0,
  77259         2,
  77260         soc_SPORT_INTR_STATUSr_fields,
  77261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77262         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  77263         -1,
  77264         -1,
  77265     },
  77266 #endif /* chips */
  77267 
  77268 #if defined(BCM_56260_A0)
  77269     { /* SOC_REG_INT_XPORT_INTR_STATUS_BCM56260_A0r */
  77270         soc_block_list[83],
  77271         soc_genreg,
  77272         1,
  77273         0,
  77274         0x2022700,
  77275         SOC_REG_FLAG_RO,
  77276         0,
  77277         11,
  77278         soc_XPORT_INTR_STATUS_BCM56260_A0r_fields,
  77279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77280         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77281         -1,
  77282         -1,
  77283     },
  77284 #endif /* chips */
  77285 
  77286 #if defined(BCM_56260_B0)
  77287     { /* SOC_REG_INT_XPORT_INTR_STATUS_BCM56260_B0r */
  77288         soc_block_list[83],
  77289         soc_genreg,
  77290         1,
  77291         0,
  77292         0x2022600,
  77293         SOC_REG_FLAG_RO,
  77294         0,
  77295         11,
  77296         soc_XPORT_INTR_STATUS_BCM56260_A0r_fields,
  77297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77298         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77299         -1,
  77300         -1,
  77301     },
  77302 #endif /* chips */
  77303 
  77304 #if defined(BCM_56270_A0)
  77305     { /* SOC_REG_INT_XPORT_INTR_STATUS_BCM56270_A0r */
  77306         soc_block_list[83],
  77307         soc_genreg,
  77308         1,
  77309         0,
  77310         0x2022700,
  77311         SOC_REG_FLAG_RO,
  77312         0,
  77313         11,
  77314         soc_XPORT_INTR_STATUS_BCM56260_A0r_fields,
  77315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77316         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77317         -1,
  77318         -1,
  77319     },
  77320 #endif /* chips */
  77321 
  77322 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77323     { /* SOC_REG_INT_XPORT_INTR_STATUS_BCM56440_A0r */
  77324         soc_block_list[83],
  77325         soc_genreg,
  77326         1,
  77327         0,
  77328         0x80251,
  77329         SOC_REG_FLAG_RO,
  77330         0,
  77331         15,
  77332         soc_XPORT_INTR_STATUSr_fields,
  77333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77334         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  77335         -1,
  77336         -1,
  77337     },
  77338 #endif /* chips */
  77339 
  77340 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77341     defined(BCM_56450_B1)
  77342     { /* SOC_REG_INT_XPORT_INTR_STATUS_BCM56450_A0r */
  77343         soc_block_list[83],
  77344         soc_genreg,
  77345         1,
  77346         0,
  77347         0x2025500,
  77348         SOC_REG_FLAG_RO,
  77349         0,
  77350         15,
  77351         soc_XPORT_INTR_STATUS_BCM56450_A0r_fields,
  77352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77353         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  77354         -1,
  77355         -1,
  77356     },
  77357 #endif /* chips */
  77358 
  77359 #if defined(BCM_88270_A0)
  77360     { /* SOC_REG_INT_XPORT_INTR_STATUS_BCM88270_A0r */
  77361         soc_block_list[149],
  77362         soc_genreg,
  77363         1,
  77364         0,
  77365         0x2022100,
  77366         SOC_REG_FLAG_RO |
  77367                           SOC_REG_FLAG_SIGNAL,
  77368         0,
  77369         11,
  77370         soc_XPORT_INTR_STATUS_BCM88270_A0r_fields,
  77371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77372         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77373         -1,
  77374         -1,
  77375     },
  77376 #endif /* chips */
  77377 
  77378 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77379     { /* SOC_REG_INT_XPORT_LINKSTATUS_DOWNr */
  77380         soc_block_list[83],
  77381         soc_genreg,
  77382         1,
  77383         0,
  77384         0x8024f,
  77385         SOC_REG_FLAG_RO,
  77386         0,
  77387         4,
  77388         soc_XLPORT_LINKSTATUS_DOWNr_fields,
  77389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77390         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  77391         -1,
  77392         -1,
  77393     },
  77394 #endif /* chips */
  77395 
  77396 #if defined(BCM_56260_A0)
  77397     { /* SOC_REG_INT_XPORT_LINKSTATUS_DOWN_BCM56260_A0r */
  77398         soc_block_list[83],
  77399         soc_genreg,
  77400         1,
  77401         0,
  77402         0x2022500,
  77403         0,
  77404         0,
  77405         4,
  77406         soc_XPORT_LINKSTATUS_DOWNr_fields,
  77407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77408         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  77409         -1,
  77410         -1,
  77411     },
  77412 #endif /* chips */
  77413 
  77414 #if defined(BCM_56260_B0)
  77415     { /* SOC_REG_INT_XPORT_LINKSTATUS_DOWN_BCM56260_B0r */
  77416         soc_block_list[83],
  77417         soc_genreg,
  77418         1,
  77419         0,
  77420         0x2022400,
  77421         0,
  77422         0,
  77423         4,
  77424         soc_XPORT_LINKSTATUS_DOWNr_fields,
  77425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77426         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  77427         -1,
  77428         -1,
  77429     },
  77430 #endif /* chips */
  77431 
  77432 #if defined(BCM_56270_A0)
  77433     { /* SOC_REG_INT_XPORT_LINKSTATUS_DOWN_BCM56270_A0r */
  77434         soc_block_list[83],
  77435         soc_genreg,
  77436         1,
  77437         0,
  77438         0x2022500,
  77439         0,
  77440         0,
  77441         4,
  77442         soc_XPORT_LINKSTATUS_DOWNr_fields,
  77443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77444         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  77445         -1,
  77446         -1,
  77447     },
  77448 #endif /* chips */
  77449 
  77450 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77451     defined(BCM_56450_B1)
  77452     { /* SOC_REG_INT_XPORT_LINKSTATUS_DOWN_BCM56450_A0r */
  77453         soc_block_list[83],
  77454         soc_genreg,
  77455         1,
  77456         0,
  77457         0x2025300,
  77458         SOC_REG_FLAG_RO,
  77459         0,
  77460         4,
  77461         soc_XLPORT_LINKSTATUS_DOWN_BCM56850_A0r_fields,
  77462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77463         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  77464         -1,
  77465         -1,
  77466     },
  77467 #endif /* chips */
  77468 
  77469 #if defined(BCM_88270_A0)
  77470     { /* SOC_REG_INT_XPORT_LINKSTATUS_DOWN_BCM88270_A0r */
  77471         soc_block_list[149],
  77472         soc_genreg,
  77473         1,
  77474         0,
  77475         0x2021f00,
  77476         0,
  77477         0,
  77478         4,
  77479         soc_XPORT_LINKSTATUS_DOWN_BCM88270_A0r_fields,
  77480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77481         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  77482         -1,
  77483         -1,
  77484     },
  77485 #endif /* chips */
  77486 
  77487 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77488     { /* SOC_REG_INT_XPORT_LINKSTATUS_DOWN_CLEARr */
  77489         soc_block_list[83],
  77490         soc_genreg,
  77491         1,
  77492         0,
  77493         0x80250,
  77494         0,
  77495         0,
  77496         4,
  77497         soc_XLPORT_LINKSTATUS_DOWN_CLEARr_fields,
  77498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77499         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  77500         -1,
  77501         -1,
  77502     },
  77503 #endif /* chips */
  77504 
  77505 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77506     defined(BCM_56450_B1)
  77507     { /* SOC_REG_INT_XPORT_LINKSTATUS_DOWN_CLEAR_BCM56450_A0r */
  77508         soc_block_list[83],
  77509         soc_genreg,
  77510         1,
  77511         0,
  77512         0x2025400,
  77513         0,
  77514         0,
  77515         4,
  77516         soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56850_A0r_fields,
  77517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77518         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  77519         -1,
  77520         -1,
  77521     },
  77522 #endif /* chips */
  77523 
  77524 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  77525     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  77526     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  77527     { /* SOC_REG_INT_XPORT_MEMORY_CONTROLr */
  77528         soc_block_list[9],
  77529         soc_genreg,
  77530         1,
  77531         0,
  77532         0x80d1b,
  77533         0,
  77534         0,
  77535         10,
  77536         soc_XPORT_MEMORY_CONTROLr_fields,
  77537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77538         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  77539         -1,
  77540         -1,
  77541     },
  77542 #endif /* chips */
  77543 
  77544 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77545     { /* SOC_REG_INT_XPORT_MEMORY_CONTROL0r */
  77546         soc_block_list[83],
  77547         soc_genreg,
  77548         1,
  77549         0,
  77550         0x8024c,
  77551         0,
  77552         0,
  77553         2,
  77554         soc_XLPORT_MEMORY_CONTROL0r_fields,
  77555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77556         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77557         -1,
  77558         -1,
  77559     },
  77560 #endif /* chips */
  77561 
  77562 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77563     { /* SOC_REG_INT_XPORT_MEMORY_CONTROL1r */
  77564         soc_block_list[83],
  77565         soc_genreg,
  77566         1,
  77567         0,
  77568         0x8024d,
  77569         0,
  77570         0,
  77571         3,
  77572         soc_XLPORT_MEMORY_CONTROL1r_fields,
  77573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77574         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  77575         -1,
  77576         -1,
  77577     },
  77578 #endif /* chips */
  77579 
  77580 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77581     { /* SOC_REG_INT_XPORT_MEMORY_CONTROL2r */
  77582         soc_block_list[83],
  77583         soc_genreg,
  77584         1,
  77585         0,
  77586         0x8024e,
  77587         0,
  77588         0,
  77589         3,
  77590         soc_XLPORT_MEMORY_CONTROL2r_fields,
  77591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77592         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  77593         -1,
  77594         -1,
  77595     },
  77596 #endif /* chips */
  77597 
  77598 #if defined(BCM_56260_A0)
  77599     { /* SOC_REG_INT_XPORT_MEMORY_CONTROL0_BCM56260_A0r */
  77600         soc_block_list[83],
  77601         soc_genreg,
  77602         1,
  77603         0,
  77604         0x2022400,
  77605         0,
  77606         0,
  77607         3,
  77608         soc_XPORT_MEMORY_CONTROL0_BCM56260_A0r_fields,
  77609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77610         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77611         -1,
  77612         -1,
  77613     },
  77614 #endif /* chips */
  77615 
  77616 #if defined(BCM_56260_B0)
  77617     { /* SOC_REG_INT_XPORT_MEMORY_CONTROL0_BCM56260_B0r */
  77618         soc_block_list[83],
  77619         soc_genreg,
  77620         1,
  77621         0,
  77622         0x2022300,
  77623         0,
  77624         0,
  77625         3,
  77626         soc_XPORT_MEMORY_CONTROL0_BCM56260_A0r_fields,
  77627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77628         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77629         -1,
  77630         -1,
  77631     },
  77632 #endif /* chips */
  77633 
  77634 #if defined(BCM_56270_A0)
  77635     { /* SOC_REG_INT_XPORT_MEMORY_CONTROL0_BCM56270_A0r */
  77636         soc_block_list[83],
  77637         soc_genreg,
  77638         1,
  77639         0,
  77640         0x2022300,
  77641         0,
  77642         0,
  77643         2,
  77644         soc_XPORT_MEMORY_CONTROL0_BCM56270_A0r_fields,
  77645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77646         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77647         -1,
  77648         -1,
  77649     },
  77650 #endif /* chips */
  77651 
  77652 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77653     defined(BCM_56450_B1)
  77654     { /* SOC_REG_INT_XPORT_MEMORY_CONTROL0_BCM56450_A0r */
  77655         soc_block_list[83],
  77656         soc_genreg,
  77657         1,
  77658         0,
  77659         0x2025000,
  77660         0,
  77661         0,
  77662         2,
  77663         soc_XPORT_MEMORY_CONTROL0r_fields,
  77664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77665         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77666         -1,
  77667         -1,
  77668     },
  77669 #endif /* chips */
  77670 
  77671 #if defined(BCM_88270_A0)
  77672     { /* SOC_REG_INT_XPORT_MEMORY_CONTROL0_BCM88270_A0r */
  77673         soc_block_list[149],
  77674         soc_genreg,
  77675         1,
  77676         0,
  77677         0x2021e00,
  77678         0,
  77679         0,
  77680         1,
  77681         soc_XPORT_MEMORY_CONTROL0_BCM88270_A0r_fields,
  77682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77683         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  77684         -1,
  77685         -1,
  77686     },
  77687 #endif /* chips */
  77688 
  77689 #if defined(BCM_56270_A0)
  77690     { /* SOC_REG_INT_XPORT_MEMORY_CONTROL1_BCM56270_A0r */
  77691         soc_block_list[83],
  77692         soc_genreg,
  77693         1,
  77694         0,
  77695         0x2022400,
  77696         0,
  77697         0,
  77698         1,
  77699         soc_XPORT_MEMORY_CONTROL1_BCM56270_A0r_fields,
  77700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77701         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77702         -1,
  77703         -1,
  77704     },
  77705 #endif /* chips */
  77706 
  77707 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77708     defined(BCM_56450_B1)
  77709     { /* SOC_REG_INT_XPORT_MEMORY_CONTROL1_BCM56450_A0r */
  77710         soc_block_list[83],
  77711         soc_genreg,
  77712         1,
  77713         0,
  77714         0x2025100,
  77715         0,
  77716         0,
  77717         3,
  77718         soc_XPORT_MEMORY_CONTROL1r_fields,
  77719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77720         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  77721         -1,
  77722         -1,
  77723     },
  77724 #endif /* chips */
  77725 
  77726 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77727     defined(BCM_56450_B1)
  77728     { /* SOC_REG_INT_XPORT_MEMORY_CONTROL2_BCM56450_A0r */
  77729         soc_block_list[83],
  77730         soc_genreg,
  77731         1,
  77732         0,
  77733         0x2025200,
  77734         0,
  77735         0,
  77736         3,
  77737         soc_XPORT_MEMORY_CONTROL2r_fields,
  77738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77739         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  77740         -1,
  77741         -1,
  77742     },
  77743 #endif /* chips */
  77744 
  77745 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77746     { /* SOC_REG_INT_XPORT_MIB_RESETr */
  77747         soc_block_list[83],
  77748         soc_genreg,
  77749         1,
  77750         0,
  77751         0x80222,
  77752         0,
  77753         0,
  77754         1,
  77755         soc_XPORT_MIB_RESETr_fields,
  77756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77757         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77758         -1,
  77759         -1,
  77760     },
  77761 #endif /* chips */
  77762 
  77763 #if defined(BCM_56260_A0)
  77764     { /* SOC_REG_INT_XPORT_MIB_RESET_BCM56260_A0r */
  77765         soc_block_list[83],
  77766         soc_genreg,
  77767         1,
  77768         0,
  77769         0x2020e00,
  77770         0,
  77771         0,
  77772         1,
  77773         soc_XPORT_MIB_RESET_BCM56260_A0r_fields,
  77774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77775         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77776         -1,
  77777         -1,
  77778     },
  77779 #endif /* chips */
  77780 
  77781 #if defined(BCM_56260_B0)
  77782     { /* SOC_REG_INT_XPORT_MIB_RESET_BCM56260_B0r */
  77783         soc_block_list[83],
  77784         soc_genreg,
  77785         1,
  77786         0,
  77787         0x2020d00,
  77788         0,
  77789         0,
  77790         1,
  77791         soc_XPORT_MIB_RESET_BCM56260_A0r_fields,
  77792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77793         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77794         -1,
  77795         -1,
  77796     },
  77797 #endif /* chips */
  77798 
  77799 #if defined(BCM_56270_A0)
  77800     { /* SOC_REG_INT_XPORT_MIB_RESET_BCM56270_A0r */
  77801         soc_block_list[83],
  77802         soc_genreg,
  77803         1,
  77804         0,
  77805         0x2020d00,
  77806         0,
  77807         0,
  77808         1,
  77809         soc_XPORT_MIB_RESET_BCM56260_A0r_fields,
  77810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77811         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77812         -1,
  77813         -1,
  77814     },
  77815 #endif /* chips */
  77816 
  77817 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77818     defined(BCM_56450_B1)
  77819     { /* SOC_REG_INT_XPORT_MIB_RESET_BCM56450_A0r */
  77820         soc_block_list[83],
  77821         soc_genreg,
  77822         1,
  77823         0,
  77824         0x2022200,
  77825         0,
  77826         0,
  77827         1,
  77828         soc_XPORT_MIB_RESET_BCM56450_A0r_fields,
  77829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77830         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77831         -1,
  77832         -1,
  77833     },
  77834 #endif /* chips */
  77835 
  77836 #if defined(BCM_88270_A0)
  77837     { /* SOC_REG_INT_XPORT_MIB_RESET_BCM88270_A0r */
  77838         soc_block_list[149],
  77839         soc_genreg,
  77840         1,
  77841         0,
  77842         0x2020b00,
  77843         0,
  77844         0,
  77845         1,
  77846         soc_XPORT_MIB_RESET_BCM88270_A0r_fields,
  77847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77848         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  77849         -1,
  77850         -1,
  77851     },
  77852 #endif /* chips */
  77853 
  77854 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77855     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM0_ECC_STATUSr */
  77856         soc_block_list[83],
  77857         soc_genreg,
  77858         1,
  77859         0,
  77860         0x80246,
  77861         0,
  77862         0,
  77863         4,
  77864         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  77865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77866         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  77867         -1,
  77868         -1,
  77869     },
  77870 #endif /* chips */
  77871 
  77872 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  77873     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM0_ECC_STATUS_BCM56260_A0r */
  77874         soc_block_list[83],
  77875         soc_genreg,
  77876         1,
  77877         0,
  77878         0x2021e00,
  77879         0,
  77880         0,
  77881         4,
  77882         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  77883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77884         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  77885         -1,
  77886         -1,
  77887     },
  77888 #endif /* chips */
  77889 
  77890 #if defined(BCM_56270_A0)
  77891     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM0_ECC_STATUS_BCM56270_A0r */
  77892         soc_block_list[83],
  77893         soc_genreg,
  77894         1,
  77895         0,
  77896         0x2021d00,
  77897         0,
  77898         0,
  77899         4,
  77900         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  77901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77902         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  77903         -1,
  77904         -1,
  77905     },
  77906 #endif /* chips */
  77907 
  77908 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  77909     defined(BCM_56450_B1)
  77910     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM0_ECC_STATUS_BCM56450_A0r */
  77911         soc_block_list[83],
  77912         soc_genreg,
  77913         1,
  77914         0,
  77915         0x2024a00,
  77916         0,
  77917         0,
  77918         4,
  77919         soc_PORT_EHG0_RX_DATA_ECC_STATUSr_fields,
  77920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77921         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  77922         -1,
  77923         -1,
  77924     },
  77925 #endif /* chips */
  77926 
  77927 #if defined(BCM_88270_A0)
  77928     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM0_ECC_STATUS_BCM88270_A0r */
  77929         soc_block_list[149],
  77930         soc_genreg,
  77931         1,
  77932         0,
  77933         0x2021700,
  77934         0,
  77935         0,
  77936         4,
  77937         soc_XPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  77938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77939         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  77940         -1,
  77941         -1,
  77942     },
  77943 #endif /* chips */
  77944 
  77945 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  77946     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM1_ECC_STATUSr */
  77947         soc_block_list[83],
  77948         soc_genreg,
  77949         1,
  77950         0,
  77951         0x80245,
  77952         0,
  77953         0,
  77954         4,
  77955         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  77956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77957         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  77958         -1,
  77959         -1,
  77960     },
  77961 #endif /* chips */
  77962 
  77963 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  77964     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM1_ECC_STATUS_BCM56260_A0r */
  77965         soc_block_list[83],
  77966         soc_genreg,
  77967         1,
  77968         0,
  77969         0x2021d00,
  77970         0,
  77971         0,
  77972         4,
  77973         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  77974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77975         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  77976         -1,
  77977         -1,
  77978     },
  77979 #endif /* chips */
  77980 
  77981 #if defined(BCM_56270_A0)
  77982     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM1_ECC_STATUS_BCM56270_A0r */
  77983         soc_block_list[83],
  77984         soc_genreg,
  77985         1,
  77986         0,
  77987         0x2021c00,
  77988         0,
  77989         0,
  77990         4,
  77991         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  77992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77993         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  77994         -1,
  77995         -1,
  77996     },
  77997 #endif /* chips */
  77998 
  77999 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78000     defined(BCM_56450_B1)
  78001     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM1_ECC_STATUS_BCM56450_A0r */
  78002         soc_block_list[83],
  78003         soc_genreg,
  78004         1,
  78005         0,
  78006         0x2024900,
  78007         0,
  78008         0,
  78009         4,
  78010         soc_PORT_EHG0_RX_DATA_ECC_STATUSr_fields,
  78011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78012         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78013         -1,
  78014         -1,
  78015     },
  78016 #endif /* chips */
  78017 
  78018 #if defined(BCM_88270_A0)
  78019     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM1_ECC_STATUS_BCM88270_A0r */
  78020         soc_block_list[149],
  78021         soc_genreg,
  78022         1,
  78023         0,
  78024         0x2021600,
  78025         0,
  78026         0,
  78027         4,
  78028         soc_XPORT_MIB_RSC_MEM1_ECC_STATUSr_fields,
  78029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78030         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78031         -1,
  78032         -1,
  78033     },
  78034 #endif /* chips */
  78035 
  78036 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78037     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM2_ECC_STATUSr */
  78038         soc_block_list[83],
  78039         soc_genreg,
  78040         1,
  78041         0,
  78042         0x80244,
  78043         0,
  78044         0,
  78045         4,
  78046         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  78047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78048         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78049         -1,
  78050         -1,
  78051     },
  78052 #endif /* chips */
  78053 
  78054 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78055     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM2_ECC_STATUS_BCM56260_A0r */
  78056         soc_block_list[83],
  78057         soc_genreg,
  78058         1,
  78059         0,
  78060         0x2021c00,
  78061         0,
  78062         0,
  78063         4,
  78064         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78066         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78067         -1,
  78068         -1,
  78069     },
  78070 #endif /* chips */
  78071 
  78072 #if defined(BCM_56270_A0)
  78073     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM2_ECC_STATUS_BCM56270_A0r */
  78074         soc_block_list[83],
  78075         soc_genreg,
  78076         1,
  78077         0,
  78078         0x2021b00,
  78079         0,
  78080         0,
  78081         4,
  78082         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78084         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78085         -1,
  78086         -1,
  78087     },
  78088 #endif /* chips */
  78089 
  78090 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78091     defined(BCM_56450_B1)
  78092     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM2_ECC_STATUS_BCM56450_A0r */
  78093         soc_block_list[83],
  78094         soc_genreg,
  78095         1,
  78096         0,
  78097         0x2024800,
  78098         0,
  78099         0,
  78100         4,
  78101         soc_PORT_EHG0_RX_DATA_ECC_STATUSr_fields,
  78102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78103         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78104         -1,
  78105         -1,
  78106     },
  78107 #endif /* chips */
  78108 
  78109 #if defined(BCM_88270_A0)
  78110     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM2_ECC_STATUS_BCM88270_A0r */
  78111         soc_block_list[149],
  78112         soc_genreg,
  78113         1,
  78114         0,
  78115         0x2021500,
  78116         0,
  78117         0,
  78118         4,
  78119         soc_XPORT_MIB_RSC_MEM2_ECC_STATUSr_fields,
  78120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78121         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78122         -1,
  78123         -1,
  78124     },
  78125 #endif /* chips */
  78126 
  78127 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78128     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM3_ECC_STATUSr */
  78129         soc_block_list[83],
  78130         soc_genreg,
  78131         1,
  78132         0,
  78133         0x80243,
  78134         0,
  78135         0,
  78136         4,
  78137         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  78138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78139         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78140         -1,
  78141         -1,
  78142     },
  78143 #endif /* chips */
  78144 
  78145 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78146     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM3_ECC_STATUS_BCM56260_A0r */
  78147         soc_block_list[83],
  78148         soc_genreg,
  78149         1,
  78150         0,
  78151         0x2021b00,
  78152         0,
  78153         0,
  78154         4,
  78155         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78157         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78158         -1,
  78159         -1,
  78160     },
  78161 #endif /* chips */
  78162 
  78163 #if defined(BCM_56270_A0)
  78164     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM3_ECC_STATUS_BCM56270_A0r */
  78165         soc_block_list[83],
  78166         soc_genreg,
  78167         1,
  78168         0,
  78169         0x2021a00,
  78170         0,
  78171         0,
  78172         4,
  78173         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78175         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78176         -1,
  78177         -1,
  78178     },
  78179 #endif /* chips */
  78180 
  78181 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78182     defined(BCM_56450_B1)
  78183     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM3_ECC_STATUS_BCM56450_A0r */
  78184         soc_block_list[83],
  78185         soc_genreg,
  78186         1,
  78187         0,
  78188         0x2024700,
  78189         0,
  78190         0,
  78191         4,
  78192         soc_PORT_EHG0_RX_DATA_ECC_STATUSr_fields,
  78193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78194         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78195         -1,
  78196         -1,
  78197     },
  78198 #endif /* chips */
  78199 
  78200 #if defined(BCM_88270_A0)
  78201     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM3_ECC_STATUS_BCM88270_A0r */
  78202         soc_block_list[149],
  78203         soc_genreg,
  78204         1,
  78205         0,
  78206         0x2021400,
  78207         0,
  78208         0,
  78209         4,
  78210         soc_XPORT_MIB_RSC_MEM3_ECC_STATUSr_fields,
  78211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78212         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78213         -1,
  78214         -1,
  78215     },
  78216 #endif /* chips */
  78217 
  78218 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78219     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM4_ECC_STATUSr */
  78220         soc_block_list[83],
  78221         soc_genreg,
  78222         1,
  78223         0,
  78224         0x80242,
  78225         0,
  78226         0,
  78227         4,
  78228         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  78229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78230         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78231         -1,
  78232         -1,
  78233     },
  78234 #endif /* chips */
  78235 
  78236 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78237     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM4_ECC_STATUS_BCM56260_A0r */
  78238         soc_block_list[83],
  78239         soc_genreg,
  78240         1,
  78241         0,
  78242         0x2021a00,
  78243         0,
  78244         0,
  78245         4,
  78246         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78248         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78249         -1,
  78250         -1,
  78251     },
  78252 #endif /* chips */
  78253 
  78254 #if defined(BCM_56260_B0)
  78255     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM4_ECC_STATUS_BCM56260_B0r */
  78256         soc_block_list[83],
  78257         soc_genreg,
  78258         1,
  78259         0,
  78260         0x2021900,
  78261         0,
  78262         0,
  78263         4,
  78264         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78266         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78267         -1,
  78268         -1,
  78269     },
  78270 #endif /* chips */
  78271 
  78272 #if defined(BCM_56270_A0)
  78273     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM4_ECC_STATUS_BCM56270_A0r */
  78274         soc_block_list[83],
  78275         soc_genreg,
  78276         1,
  78277         0,
  78278         0x2021900,
  78279         0,
  78280         0,
  78281         4,
  78282         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78284         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78285         -1,
  78286         -1,
  78287     },
  78288 #endif /* chips */
  78289 
  78290 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78291     defined(BCM_56450_B1)
  78292     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM4_ECC_STATUS_BCM56450_A0r */
  78293         soc_block_list[83],
  78294         soc_genreg,
  78295         1,
  78296         0,
  78297         0x2024600,
  78298         0,
  78299         0,
  78300         4,
  78301         soc_PORT_EHG0_RX_DATA_ECC_STATUSr_fields,
  78302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78303         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78304         -1,
  78305         -1,
  78306     },
  78307 #endif /* chips */
  78308 
  78309 #if defined(BCM_88270_A0)
  78310     { /* SOC_REG_INT_XPORT_MIB_RSC_MEM4_ECC_STATUS_BCM88270_A0r */
  78311         soc_block_list[149],
  78312         soc_genreg,
  78313         1,
  78314         0,
  78315         0x2021300,
  78316         0,
  78317         0,
  78318         4,
  78319         soc_XPORT_MIB_RSC_MEM4_ECC_STATUSr_fields,
  78320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78321         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78322         -1,
  78323         -1,
  78324     },
  78325 #endif /* chips */
  78326 
  78327 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78328     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM0_ECC_STATUSr */
  78329         soc_block_list[83],
  78330         soc_genreg,
  78331         1,
  78332         0,
  78333         0x8024a,
  78334         0,
  78335         0,
  78336         4,
  78337         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  78338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78339         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78340         -1,
  78341         -1,
  78342     },
  78343 #endif /* chips */
  78344 
  78345 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78346     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM0_ECC_STATUS_BCM56260_A0r */
  78347         soc_block_list[83],
  78348         soc_genreg,
  78349         1,
  78350         0,
  78351         0x2022200,
  78352         0,
  78353         0,
  78354         4,
  78355         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78357         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78358         -1,
  78359         -1,
  78360     },
  78361 #endif /* chips */
  78362 
  78363 #if defined(BCM_56270_A0)
  78364     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM0_ECC_STATUS_BCM56270_A0r */
  78365         soc_block_list[83],
  78366         soc_genreg,
  78367         1,
  78368         0,
  78369         0x2022100,
  78370         0,
  78371         0,
  78372         4,
  78373         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78375         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78376         -1,
  78377         -1,
  78378     },
  78379 #endif /* chips */
  78380 
  78381 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78382     defined(BCM_56450_B1)
  78383     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM0_ECC_STATUS_BCM56450_A0r */
  78384         soc_block_list[83],
  78385         soc_genreg,
  78386         1,
  78387         0,
  78388         0x2024e00,
  78389         0,
  78390         0,
  78391         4,
  78392         soc_PORT_EHG0_RX_DATA_ECC_STATUSr_fields,
  78393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78394         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78395         -1,
  78396         -1,
  78397     },
  78398 #endif /* chips */
  78399 
  78400 #if defined(BCM_88270_A0)
  78401     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM0_ECC_STATUS_BCM88270_A0r */
  78402         soc_block_list[149],
  78403         soc_genreg,
  78404         1,
  78405         0,
  78406         0x2021b00,
  78407         0,
  78408         0,
  78409         4,
  78410         soc_XPORT_MIB_TSC_MEM0_ECC_STATUSr_fields,
  78411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78412         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78413         -1,
  78414         -1,
  78415     },
  78416 #endif /* chips */
  78417 
  78418 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78419     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM1_ECC_STATUSr */
  78420         soc_block_list[83],
  78421         soc_genreg,
  78422         1,
  78423         0,
  78424         0x80249,
  78425         0,
  78426         0,
  78427         4,
  78428         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  78429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78430         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78431         -1,
  78432         -1,
  78433     },
  78434 #endif /* chips */
  78435 
  78436 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78437     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM1_ECC_STATUS_BCM56260_A0r */
  78438         soc_block_list[83],
  78439         soc_genreg,
  78440         1,
  78441         0,
  78442         0x2022100,
  78443         0,
  78444         0,
  78445         4,
  78446         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78448         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78449         -1,
  78450         -1,
  78451     },
  78452 #endif /* chips */
  78453 
  78454 #if defined(BCM_56270_A0)
  78455     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM1_ECC_STATUS_BCM56270_A0r */
  78456         soc_block_list[83],
  78457         soc_genreg,
  78458         1,
  78459         0,
  78460         0x2022000,
  78461         0,
  78462         0,
  78463         4,
  78464         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78466         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78467         -1,
  78468         -1,
  78469     },
  78470 #endif /* chips */
  78471 
  78472 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78473     defined(BCM_56450_B1)
  78474     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM1_ECC_STATUS_BCM56450_A0r */
  78475         soc_block_list[83],
  78476         soc_genreg,
  78477         1,
  78478         0,
  78479         0x2024d00,
  78480         0,
  78481         0,
  78482         4,
  78483         soc_PORT_EHG0_RX_DATA_ECC_STATUSr_fields,
  78484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78485         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78486         -1,
  78487         -1,
  78488     },
  78489 #endif /* chips */
  78490 
  78491 #if defined(BCM_88270_A0)
  78492     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM1_ECC_STATUS_BCM88270_A0r */
  78493         soc_block_list[149],
  78494         soc_genreg,
  78495         1,
  78496         0,
  78497         0x2021a00,
  78498         0,
  78499         0,
  78500         4,
  78501         soc_XPORT_MIB_TSC_MEM1_ECC_STATUSr_fields,
  78502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78503         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78504         -1,
  78505         -1,
  78506     },
  78507 #endif /* chips */
  78508 
  78509 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78510     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM2_ECC_STATUSr */
  78511         soc_block_list[83],
  78512         soc_genreg,
  78513         1,
  78514         0,
  78515         0x80248,
  78516         0,
  78517         0,
  78518         4,
  78519         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  78520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78521         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78522         -1,
  78523         -1,
  78524     },
  78525 #endif /* chips */
  78526 
  78527 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78528     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM2_ECC_STATUS_BCM56260_A0r */
  78529         soc_block_list[83],
  78530         soc_genreg,
  78531         1,
  78532         0,
  78533         0x2022000,
  78534         0,
  78535         0,
  78536         4,
  78537         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78539         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78540         -1,
  78541         -1,
  78542     },
  78543 #endif /* chips */
  78544 
  78545 #if defined(BCM_56270_A0)
  78546     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM2_ECC_STATUS_BCM56270_A0r */
  78547         soc_block_list[83],
  78548         soc_genreg,
  78549         1,
  78550         0,
  78551         0x2021f00,
  78552         0,
  78553         0,
  78554         4,
  78555         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78557         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78558         -1,
  78559         -1,
  78560     },
  78561 #endif /* chips */
  78562 
  78563 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78564     defined(BCM_56450_B1)
  78565     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM2_ECC_STATUS_BCM56450_A0r */
  78566         soc_block_list[83],
  78567         soc_genreg,
  78568         1,
  78569         0,
  78570         0x2024c00,
  78571         0,
  78572         0,
  78573         4,
  78574         soc_PORT_EHG0_RX_DATA_ECC_STATUSr_fields,
  78575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78576         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78577         -1,
  78578         -1,
  78579     },
  78580 #endif /* chips */
  78581 
  78582 #if defined(BCM_88270_A0)
  78583     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM2_ECC_STATUS_BCM88270_A0r */
  78584         soc_block_list[149],
  78585         soc_genreg,
  78586         1,
  78587         0,
  78588         0x2021900,
  78589         0,
  78590         0,
  78591         4,
  78592         soc_XPORT_MIB_TSC_MEM2_ECC_STATUSr_fields,
  78593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78594         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78595         -1,
  78596         -1,
  78597     },
  78598 #endif /* chips */
  78599 
  78600 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78601     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM3_ECC_STATUSr */
  78602         soc_block_list[83],
  78603         soc_genreg,
  78604         1,
  78605         0,
  78606         0x80247,
  78607         0,
  78608         0,
  78609         4,
  78610         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  78611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78612         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78613         -1,
  78614         -1,
  78615     },
  78616 #endif /* chips */
  78617 
  78618 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  78619     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM3_ECC_STATUS_BCM56260_A0r */
  78620         soc_block_list[83],
  78621         soc_genreg,
  78622         1,
  78623         0,
  78624         0x2021f00,
  78625         0,
  78626         0,
  78627         4,
  78628         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78630         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78631         -1,
  78632         -1,
  78633     },
  78634 #endif /* chips */
  78635 
  78636 #if defined(BCM_56270_A0)
  78637     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM3_ECC_STATUS_BCM56270_A0r */
  78638         soc_block_list[83],
  78639         soc_genreg,
  78640         1,
  78641         0,
  78642         0x2021e00,
  78643         0,
  78644         0,
  78645         4,
  78646         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  78647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78648         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78649         -1,
  78650         -1,
  78651     },
  78652 #endif /* chips */
  78653 
  78654 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78655     defined(BCM_56450_B1)
  78656     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM3_ECC_STATUS_BCM56450_A0r */
  78657         soc_block_list[83],
  78658         soc_genreg,
  78659         1,
  78660         0,
  78661         0x2024b00,
  78662         0,
  78663         0,
  78664         4,
  78665         soc_PORT_EHG0_RX_DATA_ECC_STATUSr_fields,
  78666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78667         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78668         -1,
  78669         -1,
  78670     },
  78671 #endif /* chips */
  78672 
  78673 #if defined(BCM_88270_A0)
  78674     { /* SOC_REG_INT_XPORT_MIB_TSC_MEM3_ECC_STATUS_BCM88270_A0r */
  78675         soc_block_list[149],
  78676         soc_genreg,
  78677         1,
  78678         0,
  78679         0x2021800,
  78680         0,
  78681         0,
  78682         4,
  78683         soc_XPORT_MIB_TSC_MEM3_ECC_STATUSr_fields,
  78684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78685         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78686         -1,
  78687         -1,
  78688     },
  78689 #endif /* chips */
  78690 
  78691 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  78692     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  78693     { /* SOC_REG_INT_XPORT_MODE_REGr */
  78694         soc_block_list[9],
  78695         soc_genreg,
  78696         1,
  78697         0,
  78698         0x80e05,
  78699         0,
  78700         0,
  78701         1,
  78702         soc_XPORT_MODE_REGr_fields,
  78703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78704         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78705         -1,
  78706         -1,
  78707     },
  78708 #endif /* chips */
  78709 
  78710 #if defined(BCM_56260_A0)
  78711     { /* SOC_REG_INT_XPORT_MODE_REG_BCM56260_A0r */
  78712         soc_block_list[83],
  78713         soc_genreg,
  78714         1,
  78715         0,
  78716         0x2020b00,
  78717         0,
  78718         0,
  78719         2,
  78720         soc_XPORT_MODE_REG_BCM56260_A0r_fields,
  78721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78722         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  78723         -1,
  78724         -1,
  78725     },
  78726 #endif /* chips */
  78727 
  78728 #if defined(BCM_56260_B0)
  78729     { /* SOC_REG_INT_XPORT_MODE_REG_BCM56260_B0r */
  78730         soc_block_list[83],
  78731         soc_genreg,
  78732         1,
  78733         0,
  78734         0x2020a00,
  78735         0,
  78736         0,
  78737         3,
  78738         soc_XPORT_MODE_REG_BCM56260_B0r_fields,
  78739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78740         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  78741         -1,
  78742         -1,
  78743     },
  78744 #endif /* chips */
  78745 
  78746 #if defined(BCM_56270_A0)
  78747     { /* SOC_REG_INT_XPORT_MODE_REG_BCM56270_A0r */
  78748         soc_block_list[83],
  78749         soc_genreg,
  78750         1,
  78751         0,
  78752         0x2020a00,
  78753         0,
  78754         0,
  78755         3,
  78756         soc_XPORT_MODE_REG_BCM56260_B0r_fields,
  78757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78758         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  78759         -1,
  78760         -1,
  78761     },
  78762 #endif /* chips */
  78763 
  78764 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78765     { /* SOC_REG_INT_XPORT_MODE_REG_BCM56440_A0r */
  78766         soc_block_list[83],
  78767         soc_genreg,
  78768         1,
  78769         0,
  78770         0x8021f,
  78771         0,
  78772         0,
  78773         5,
  78774         soc_XPORT_MODE_REG_BCM56440_A0r_fields,
  78775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78776         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  78777         -1,
  78778         -1,
  78779     },
  78780 #endif /* chips */
  78781 
  78782 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  78783     defined(BCM_56450_B1)
  78784     { /* SOC_REG_INT_XPORT_MODE_REG_BCM56450_A0r */
  78785         soc_block_list[83],
  78786         soc_genreg,
  78787         1,
  78788         0,
  78789         0x2021f00,
  78790         0,
  78791         0,
  78792         9,
  78793         soc_XPORT_MODE_REG_BCM56450_A0r_fields,
  78794         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  78795         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  78796         -1,
  78797         -1,
  78798     },
  78799 #endif /* chips */
  78800 
  78801 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  78802     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  78803     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  78804     { /* SOC_REG_INT_XPORT_MODE_REG_BCM56634_A0r */
  78805         soc_block_list[9],
  78806         soc_genreg,
  78807         1,
  78808         0,
  78809         0x80d03,
  78810         0,
  78811         0,
  78812         3,
  78813         soc_XPORT_MODE_REG_BCM56634_A0r_fields,
  78814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78815         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  78816         -1,
  78817         -1,
  78818     },
  78819 #endif /* chips */
  78820 
  78821 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  78822     { /* SOC_REG_INT_XPORT_MODE_REG_BCM56820_A0r */
  78823         soc_block_list[9],
  78824         soc_portreg,
  78825         1,
  78826         0,
  78827         0xc05,
  78828         0,
  78829         0,
  78830         1,
  78831         soc_XPORT_MODE_REG_BCM56820_A0r_fields,
  78832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78833         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  78834         -1,
  78835         -1,
  78836     },
  78837 #endif /* chips */
  78838 
  78839 #if defined(BCM_88270_A0)
  78840     { /* SOC_REG_INT_XPORT_MODE_REG_BCM88270_A0r */
  78841         soc_block_list[149],
  78842         soc_genreg,
  78843         1,
  78844         0,
  78845         0x2020800,
  78846         0,
  78847         0,
  78848         3,
  78849         soc_XPORT_MODE_REG_BCM88270_A0r_fields,
  78850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78851         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  78852         -1,
  78853         -1,
  78854     },
  78855 #endif /* chips */
  78856 
  78857 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  78858     { /* SOC_REG_INT_XPORT_PFC_STATEr */
  78859         soc_block_list[125],
  78860         soc_slicereg,
  78861         68,
  78862         0,
  78863         0x2b006000,
  78864         SOC_REG_FLAG_ARRAY |
  78865                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  78866         0,
  78867         1,
  78868         soc_XPORT_PFC_STATEr_fields,
  78869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78870         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  78871         -1,
  78872         -1,
  78873         3,
  78874     },
  78875 #endif /* chips */
  78876 
  78877 #if defined(BCM_56370_A0)
  78878     { /* SOC_REG_INT_XPORT_PFC_STATE_BCM56370_A0r */
  78879         soc_block_list[194],
  78880         soc_slicereg,
  78881         79,
  78882         0,
  78883         0x1b006000,
  78884         SOC_REG_FLAG_ARRAY |
  78885                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  78886         0,
  78887         1,
  78888         soc_XPORT_PFC_STATEr_fields,
  78889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78890         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  78891         -1,
  78892         -1,
  78893         3,
  78894     },
  78895 #endif /* chips */
  78896 
  78897 #if defined(BCM_56770_A0)
  78898     { /* SOC_REG_INT_XPORT_PFC_STATE_BCM56770_A0r */
  78899         soc_block_list[194],
  78900         soc_slicereg,
  78901         83,
  78902         0,
  78903         0x1b006000,
  78904         SOC_REG_FLAG_ARRAY |
  78905                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  78906         0,
  78907         1,
  78908         soc_XPORT_PFC_STATEr_fields,
  78909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78910         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  78911         -1,
  78912         -1,
  78913         3,
  78914     },
  78915 #endif /* chips */
  78916 
  78917 #if defined(BCM_56870_A0)
  78918     { /* SOC_REG_INT_XPORT_PFC_STATE_BCM56870_A0r */
  78919         soc_block_list[194],
  78920         soc_slicereg,
  78921         132,
  78922         0,
  78923         0x1b006000,
  78924         SOC_REG_FLAG_ARRAY |
  78925                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  78926         0,
  78927         1,
  78928         soc_XPORT_PFC_STATEr_fields,
  78929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78930         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  78931         -1,
  78932         -1,
  78933         3,
  78934     },
  78935 #endif /* chips */
  78936 
  78937 #if defined(BCM_56970_A0)
  78938     { /* SOC_REG_INT_XPORT_PFC_STATE_BCM56970_A0r */
  78939         soc_block_list[194],
  78940         soc_slicereg,
  78941         132,
  78942         0,
  78943         0x17006000,
  78944         SOC_REG_FLAG_ARRAY |
  78945                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  78946         0,
  78947         1,
  78948         soc_XPORT_PFC_STATEr_fields,
  78949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78950         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  78951         -1,
  78952         -1,
  78953         3,
  78954     },
  78955 #endif /* chips */
  78956 
  78957 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  78958     { /* SOC_REG_INT_XPORT_PORT_ENABLEr */
  78959         soc_block_list[83],
  78960         soc_genreg,
  78961         1,
  78962         0,
  78963         0x80220,
  78964         0,
  78965         0,
  78966         4,
  78967         soc_XLPORT_PORT_ENABLEr_fields,
  78968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78969         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  78970         -1,
  78971         -1,
  78972     },
  78973 #endif /* chips */
  78974 
  78975 #if defined(BCM_56260_A0)
  78976     { /* SOC_REG_INT_XPORT_PORT_ENABLE_BCM56260_A0r */
  78977         soc_block_list[83],
  78978         soc_genreg,
  78979         1,
  78980         0,
  78981         0x2020c00,
  78982         0,
  78983         0,
  78984         4,
  78985         soc_CLPORT_ENABLE_REGr_fields,
  78986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78987         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  78988         -1,
  78989         -1,
  78990     },
  78991 #endif /* chips */
  78992 
  78993 #if defined(BCM_56260_B0)
  78994     { /* SOC_REG_INT_XPORT_PORT_ENABLE_BCM56260_B0r */
  78995         soc_block_list[83],
  78996         soc_genreg,
  78997         1,
  78998         0,
  78999         0x2020b00,
  79000         0,
  79001         0,
  79002         4,
  79003         soc_CLPORT_ENABLE_REGr_fields,
  79004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79005         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  79006         -1,
  79007         -1,
  79008     },
  79009 #endif /* chips */
  79010 
  79011 #if defined(BCM_56270_A0)
  79012     { /* SOC_REG_INT_XPORT_PORT_ENABLE_BCM56270_A0r */
  79013         soc_block_list[83],
  79014         soc_genreg,
  79015         1,
  79016         0,
  79017         0x2020b00,
  79018         0,
  79019         0,
  79020         4,
  79021         soc_CLPORT_ENABLE_REGr_fields,
  79022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79023         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  79024         -1,
  79025         -1,
  79026     },
  79027 #endif /* chips */
  79028 
  79029 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79030     defined(BCM_56450_B1)
  79031     { /* SOC_REG_INT_XPORT_PORT_ENABLE_BCM56450_A0r */
  79032         soc_block_list[83],
  79033         soc_genreg,
  79034         1,
  79035         0,
  79036         0x2022000,
  79037         0,
  79038         0,
  79039         4,
  79040         soc_XLPORT_ENABLE_REG_BCM56850_A0r_fields,
  79041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79042         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  79043         -1,
  79044         -1,
  79045     },
  79046 #endif /* chips */
  79047 
  79048 #if defined(BCM_88270_A0)
  79049     { /* SOC_REG_INT_XPORT_PORT_ENABLE_BCM88270_A0r */
  79050         soc_block_list[149],
  79051         soc_genreg,
  79052         1,
  79053         0,
  79054         0x2020900,
  79055         0,
  79056         0,
  79057         4,
  79058         soc_XPORT_PORT_ENABLEr_fields,
  79059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79060         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  79061         -1,
  79062         -1,
  79063     },
  79064 #endif /* chips */
  79065 
  79066 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79067     { /* SOC_REG_INT_XPORT_RXFIFO_MEM0_ECC_STATUSr */
  79068         soc_block_list[83],
  79069         soc_genreg,
  79070         1,
  79071         0,
  79072         0x80253,
  79073         0,
  79074         0,
  79075         2,
  79076         soc_XPORT_RXFIFO_MEM0_ECC_STATUSr_fields,
  79077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79078         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79079         -1,
  79080         -1,
  79081     },
  79082 #endif /* chips */
  79083 
  79084 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79085     defined(BCM_56450_B1)
  79086     { /* SOC_REG_INT_XPORT_RXFIFO_MEM0_ECC_STATUS_BCM56450_A0r */
  79087         soc_block_list[83],
  79088         soc_genreg,
  79089         1,
  79090         0,
  79091         0x2025700,
  79092         0,
  79093         0,
  79094         2,
  79095         soc_XPORT_RXFIFO_MEM0_ECC_STATUS_BCM56450_A0r_fields,
  79096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79097         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79098         -1,
  79099         -1,
  79100     },
  79101 #endif /* chips */
  79102 
  79103 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79104     { /* SOC_REG_INT_XPORT_RXFIFO_MEM1_ECC_STATUSr */
  79105         soc_block_list[83],
  79106         soc_genreg,
  79107         1,
  79108         0,
  79109         0x80254,
  79110         0,
  79111         0,
  79112         2,
  79113         soc_XPORT_RXFIFO_MEM0_ECC_STATUSr_fields,
  79114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79115         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79116         -1,
  79117         -1,
  79118     },
  79119 #endif /* chips */
  79120 
  79121 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79122     defined(BCM_56450_B1)
  79123     { /* SOC_REG_INT_XPORT_RXFIFO_MEM1_ECC_STATUS_BCM56450_A0r */
  79124         soc_block_list[83],
  79125         soc_genreg,
  79126         1,
  79127         0,
  79128         0x2025800,
  79129         0,
  79130         0,
  79131         2,
  79132         soc_XPORT_RXFIFO_MEM0_ECC_STATUS_BCM56450_A0r_fields,
  79133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79134         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79135         -1,
  79136         -1,
  79137     },
  79138 #endif /* chips */
  79139 
  79140 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79141     { /* SOC_REG_INT_XPORT_RXFIFO_MEM2_ECC_STATUSr */
  79142         soc_block_list[83],
  79143         soc_genreg,
  79144         1,
  79145         0,
  79146         0x80255,
  79147         0,
  79148         0,
  79149         2,
  79150         soc_XPORT_RXFIFO_MEM0_ECC_STATUSr_fields,
  79151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79152         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79153         -1,
  79154         -1,
  79155     },
  79156 #endif /* chips */
  79157 
  79158 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79159     defined(BCM_56450_B1)
  79160     { /* SOC_REG_INT_XPORT_RXFIFO_MEM2_ECC_STATUS_BCM56450_A0r */
  79161         soc_block_list[83],
  79162         soc_genreg,
  79163         1,
  79164         0,
  79165         0x2025900,
  79166         0,
  79167         0,
  79168         2,
  79169         soc_XPORT_RXFIFO_MEM0_ECC_STATUS_BCM56450_A0r_fields,
  79170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79171         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79172         -1,
  79173         -1,
  79174     },
  79175 #endif /* chips */
  79176 
  79177 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79178     { /* SOC_REG_INT_XPORT_RXFIFO_MEM3_ECC_STATUSr */
  79179         soc_block_list[83],
  79180         soc_genreg,
  79181         1,
  79182         0,
  79183         0x80256,
  79184         0,
  79185         0,
  79186         2,
  79187         soc_XPORT_RXFIFO_MEM0_ECC_STATUSr_fields,
  79188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79189         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79190         -1,
  79191         -1,
  79192     },
  79193 #endif /* chips */
  79194 
  79195 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79196     defined(BCM_56450_B1)
  79197     { /* SOC_REG_INT_XPORT_RXFIFO_MEM3_ECC_STATUS_BCM56450_A0r */
  79198         soc_block_list[83],
  79199         soc_genreg,
  79200         1,
  79201         0,
  79202         0x2025a00,
  79203         0,
  79204         0,
  79205         2,
  79206         soc_XPORT_RXFIFO_MEM0_ECC_STATUS_BCM56450_A0r_fields,
  79207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79208         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79209         -1,
  79210         -1,
  79211     },
  79212 #endif /* chips */
  79213 
  79214 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79215     { /* SOC_REG_INT_XPORT_RXFIFO_MEM4_ECC_STATUSr */
  79216         soc_block_list[83],
  79217         soc_genreg,
  79218         1,
  79219         0,
  79220         0x80257,
  79221         0,
  79222         0,
  79223         2,
  79224         soc_XPORT_RXFIFO_MEM0_ECC_STATUSr_fields,
  79225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79226         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79227         -1,
  79228         -1,
  79229     },
  79230 #endif /* chips */
  79231 
  79232 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79233     defined(BCM_56450_B1)
  79234     { /* SOC_REG_INT_XPORT_RXFIFO_MEM4_ECC_STATUS_BCM56450_A0r */
  79235         soc_block_list[83],
  79236         soc_genreg,
  79237         1,
  79238         0,
  79239         0x2025b00,
  79240         0,
  79241         0,
  79242         2,
  79243         soc_XPORT_RXFIFO_MEM0_ECC_STATUS_BCM56450_A0r_fields,
  79244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79245         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79246         -1,
  79247         -1,
  79248     },
  79249 #endif /* chips */
  79250 
  79251 #if defined(BCM_56260_A0)
  79252     { /* SOC_REG_INT_XPORT_RXFIFO_MEM_ECC_STATUSr */
  79253         soc_block_list[83],
  79254         soc_genreg,
  79255         1,
  79256         0,
  79257         0x2022800,
  79258         0,
  79259         0,
  79260         2,
  79261         soc_XPORT_RXFIFO_MEM_ECC_STATUSr_fields,
  79262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79263         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79264         -1,
  79265         -1,
  79266     },
  79267 #endif /* chips */
  79268 
  79269 #if defined(BCM_56260_B0)
  79270     { /* SOC_REG_INT_XPORT_RXFIFO_MEM_ECC_STATUS_BCM56260_B0r */
  79271         soc_block_list[83],
  79272         soc_genreg,
  79273         1,
  79274         0,
  79275         0x2022700,
  79276         0,
  79277         0,
  79278         2,
  79279         soc_XPORT_RXFIFO_MEM_ECC_STATUSr_fields,
  79280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79281         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79282         -1,
  79283         -1,
  79284     },
  79285 #endif /* chips */
  79286 
  79287 #if defined(BCM_56270_A0)
  79288     { /* SOC_REG_INT_XPORT_RXFIFO_MEM_ECC_STATUS_BCM56270_A0r */
  79289         soc_block_list[83],
  79290         soc_genreg,
  79291         1,
  79292         0,
  79293         0x2022800,
  79294         0,
  79295         0,
  79296         2,
  79297         soc_XPORT_RXFIFO_MEM_ECC_STATUSr_fields,
  79298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79299         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79300         -1,
  79301         -1,
  79302     },
  79303 #endif /* chips */
  79304 
  79305 #if defined(BCM_88270_A0)
  79306     { /* SOC_REG_INT_XPORT_RXFIFO_MEM_ECC_STATUS_BCM88270_A0r */
  79307         soc_block_list[149],
  79308         soc_genreg,
  79309         1,
  79310         0,
  79311         0x2021d00,
  79312         0,
  79313         0,
  79314         2,
  79315         soc_XPORT_RXFIFO_MEM_ECC_STATUS_BCM88270_A0r_fields,
  79316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79317         SOC_RESET_MASK_DEC(0x00000005, 0x00000000)
  79318         -1,
  79319         -1,
  79320     },
  79321 #endif /* chips */
  79322 
  79323 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  79324     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  79325     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  79326     { /* SOC_REG_INT_XPORT_RX_FIFO_MEM_ECC_STATUSr */
  79327         soc_block_list[9],
  79328         soc_genreg,
  79329         1,
  79330         0,
  79331         0x80d08,
  79332         0,
  79333         0,
  79334         4,
  79335         soc_XPORT_RX_FIFO_MEM_ECC_STATUSr_fields,
  79336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79337         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  79338         -1,
  79339         -1,
  79340     },
  79341 #endif /* chips */
  79342 
  79343 #if defined(BCM_88270_A0)
  79344     { /* SOC_REG_INT_XPORT_SW_FLOW_CONTROLr */
  79345         soc_block_list[149],
  79346         soc_portreg,
  79347         1,
  79348         0,
  79349         0x20600,
  79350         0,
  79351         0,
  79352         2,
  79353         soc_XPORT_SW_FLOW_CONTROLr_fields,
  79354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79355         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  79356         -1,
  79357         -1,
  79358     },
  79359 #endif /* chips */
  79360 
  79361 #if defined(BCM_56800_A0)
  79362     { /* SOC_REG_INT_XPORT_TO_MMU_BKPr */
  79363         soc_block_list[4],
  79364         soc_portreg,
  79365         1,
  79366         0,
  79367         0xb000011,
  79368         SOC_REG_FLAG_RO,
  79369         0,
  79370         10,
  79371         soc_XPORT_TO_MMU_BKPr_fields,
  79372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79373         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  79374         -1,
  79375         -1,
  79376     },
  79377 #endif /* chips */
  79378 
  79379 #if defined(BCM_56370_A0)
  79380     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_64r */
  79381         soc_block_list[194],
  79382         soc_portreg,
  79383         1,
  79384         0,
  79385         0x18804000,
  79386         SOC_REG_FLAG_64_BITS |
  79387                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  79388         0,
  79389         2,
  79390         soc_XPORT_TO_MMU_BKP_64r_fields,
  79391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79392         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79393         -1,
  79394         111,
  79395         3,
  79396     },
  79397 #endif /* chips */
  79398 
  79399 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  79400     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56260_A0r */
  79401         soc_block_list[4],
  79402         soc_genreg,
  79403         19,
  79404         0,
  79405         0x56005d00,
  79406         SOC_REG_FLAG_ARRAY,
  79407         0,
  79408         1,
  79409         soc_XPORT_TO_MMU_BKP_BCM56260_A0r_fields,
  79410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79411         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79412         -1,
  79413         -1,
  79414     },
  79415 #endif /* chips */
  79416 
  79417 #if defined(BCM_56270_A0)
  79418     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56270_A0r */
  79419         soc_block_list[4],
  79420         soc_genreg,
  79421         12,
  79422         0,
  79423         0x56005d00,
  79424         SOC_REG_FLAG_ARRAY,
  79425         0,
  79426         1,
  79427         soc_XPORT_TO_MMU_BKP_BCM56260_A0r_fields,
  79428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79429         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79430         -1,
  79431         -1,
  79432     },
  79433 #endif /* chips */
  79434 
  79435 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79436     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56440_A0r */
  79437         soc_block_list[4],
  79438         soc_portreg,
  79439         1,
  79440         0,
  79441         0x15000060,
  79442         SOC_REG_FLAG_RO,
  79443         0,
  79444         1,
  79445         soc_XPORT_TO_MMU_BKP_BCM56440_A0r_fields,
  79446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79447         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79448         -1,
  79449         53,
  79450     },
  79451 #endif /* chips */
  79452 
  79453 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79454     defined(BCM_56450_B1)
  79455     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56450_A0r */
  79456         soc_block_list[4],
  79457         soc_genreg,
  79458         14,
  79459         0,
  79460         0x56006f00,
  79461         SOC_REG_FLAG_ARRAY,
  79462         0,
  79463         1,
  79464         soc_XPORT_TO_MMU_BKP_BCM56640_A0r_fields,
  79465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79466         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79467         -1,
  79468         -1,
  79469     },
  79470 #endif /* chips */
  79471 
  79472 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  79473     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56560_A0r */
  79474         soc_block_list[4],
  79475         soc_portreg,
  79476         1,
  79477         0,
  79478         0x54009000,
  79479         0,
  79480         0,
  79481         1,
  79482         soc_XPORT_TO_MMU_BKP_BCM56560_A0r_fields,
  79483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79484         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79485         -1,
  79486         86,
  79487     },
  79488 #endif /* chips */
  79489 
  79490 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  79491     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56640_A0r */
  79492         soc_block_list[4],
  79493         soc_portreg,
  79494         1,
  79495         0,
  79496         0x50008000,
  79497         0,
  79498         0,
  79499         1,
  79500         soc_XPORT_TO_MMU_BKP_BCM56640_A0r_fields,
  79501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79502         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79503         -1,
  79504         59,
  79505     },
  79506 #endif /* chips */
  79507 
  79508 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  79509     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56670_A0r */
  79510         soc_block_list[4],
  79511         soc_portreg,
  79512         1,
  79513         0,
  79514         0x54009000,
  79515         0,
  79516         0,
  79517         1,
  79518         soc_XPORT_TO_MMU_BKP_BCM56560_A0r_fields,
  79519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79520         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79521         -1,
  79522         109,
  79523     },
  79524 #endif /* chips */
  79525 
  79526 #if defined(BCM_56770_A0)
  79527     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56770_A0r */
  79528         soc_block_list[194],
  79529         soc_portreg,
  79530         1,
  79531         0,
  79532         0x18804000,
  79533         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  79534         0,
  79535         2,
  79536         soc_XPORT_TO_MMU_BKP_BCM56960_A0r_fields,
  79537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79539         -1,
  79540         100,
  79541         3,
  79542     },
  79543 #endif /* chips */
  79544 
  79545 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  79546     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56820_A0r */
  79547         soc_block_list[4],
  79548         soc_portreg,
  79549         1,
  79550         0,
  79551         0xb000028,
  79552         0,
  79553         0,
  79554         16,
  79555         soc_XPORT_TO_MMU_BKP_BCM56820_A0r_fields,
  79556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79557         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79558         -1,
  79559         11,
  79560     },
  79561 #endif /* chips */
  79562 
  79563 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  79564     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56840_A0r */
  79565         soc_block_list[4],
  79566         soc_portreg,
  79567         1,
  79568         0,
  79569         0x15000060,
  79570         0,
  79571         0,
  79572         1,
  79573         soc_XPORT_TO_MMU_BKP_BCM56840_A0r_fields,
  79574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79575         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79576         -1,
  79577         37,
  79578     },
  79579 #endif /* chips */
  79580 
  79581 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  79582     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56850_A0r */
  79583         soc_block_list[4],
  79584         soc_portreg,
  79585         1,
  79586         0,
  79587         0x54009000,
  79588         0,
  79589         0,
  79590         1,
  79591         soc_XPORT_TO_MMU_BKP_BCM56850_A0r_fields,
  79592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79593         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79594         -1,
  79595         72,
  79596     },
  79597 #endif /* chips */
  79598 
  79599 #if defined(BCM_56870_A0)
  79600     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56870_A0r */
  79601         soc_block_list[194],
  79602         soc_portreg,
  79603         1,
  79604         0,
  79605         0x18804000,
  79606         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  79607         0,
  79608         2,
  79609         soc_XPORT_TO_MMU_BKP_BCM56960_A0r_fields,
  79610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79612         -1,
  79613         97,
  79614         3,
  79615     },
  79616 #endif /* chips */
  79617 
  79618 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  79619     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56960_A0r */
  79620         soc_block_list[125],
  79621         soc_portreg,
  79622         1,
  79623         0,
  79624         0x28804000,
  79625         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  79626         0,
  79627         2,
  79628         soc_XPORT_TO_MMU_BKP_BCM56960_A0r_fields,
  79629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79630         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79631         -1,
  79632         82,
  79633         3,
  79634     },
  79635 #endif /* chips */
  79636 
  79637 #if defined(BCM_56970_A0)
  79638     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM56970_A0r */
  79639         soc_block_list[194],
  79640         soc_portreg,
  79641         1,
  79642         0,
  79643         0x14804000,
  79644         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  79645         0,
  79646         2,
  79647         soc_XPORT_TO_MMU_BKP_BCM56960_A0r_fields,
  79648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79649         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79650         -1,
  79651         82,
  79652         3,
  79653     },
  79654 #endif /* chips */
  79655 
  79656 #if defined(BCM_88732_A0)
  79657     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_BCM88732_A0r */
  79658         soc_block_list[4],
  79659         soc_portreg,
  79660         1,
  79661         0,
  79662         0xb000028,
  79663         0,
  79664         0,
  79665         16,
  79666         soc_XPORT_TO_MMU_BKP_BCM56820_A0r_fields,
  79667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79668         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79669         -1,
  79670         50,
  79671     },
  79672 #endif /* chips */
  79673 
  79674 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  79675     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  79676     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_HGr */
  79677         soc_block_list[4],
  79678         soc_genreg,
  79679         8,
  79680         0,
  79681         0x15080020,
  79682         SOC_REG_FLAG_ARRAY,
  79683         0,
  79684         1,
  79685         soc_XPORT_TO_MMU_BKP_HGr_fields,
  79686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79687         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79688         -1,
  79689         -1,
  79690     },
  79691 #endif /* chips */
  79692 
  79693 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  79694     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_HG_BCM56334_A0r */
  79695         soc_block_list[4],
  79696         soc_genreg,
  79697         4,
  79698         0,
  79699         0x15080018,
  79700         SOC_REG_FLAG_ARRAY,
  79701         0,
  79702         1,
  79703         soc_XPORT_TO_MMU_BKP_HGr_fields,
  79704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79705         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79706         -1,
  79707         -1,
  79708     },
  79709 #endif /* chips */
  79710 
  79711 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  79712     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  79713     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  79714     { /* SOC_REG_INT_XPORT_TO_MMU_BKP_HG_BCM56634_A0r */
  79715         soc_block_list[4],
  79716         soc_genreg,
  79717         10,
  79718         0,
  79719         0x15080020,
  79720         SOC_REG_FLAG_ARRAY,
  79721         0,
  79722         1,
  79723         soc_XPORT_TO_MMU_BKP_HGr_fields,
  79724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79725         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  79726         -1,
  79727         -1,
  79728     },
  79729 #endif /* chips */
  79730 
  79731 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  79732     { /* SOC_REG_INT_XPORT_TXFIFO_MEM_ECC_STATUSr */
  79733         soc_block_list[83],
  79734         soc_genreg,
  79735         1,
  79736         0,
  79737         0x8024b,
  79738         0,
  79739         0,
  79740         4,
  79741         soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields,
  79742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79743         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  79744         -1,
  79745         -1,
  79746     },
  79747 #endif /* chips */
  79748 
  79749 #if defined(BCM_56260_A0)
  79750     { /* SOC_REG_INT_XPORT_TXFIFO_MEM_ECC_STATUS_BCM56260_A0r */
  79751         soc_block_list[83],
  79752         soc_genreg,
  79753         1,
  79754         0,
  79755         0x2022300,
  79756         0,
  79757         0,
  79758         4,
  79759         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  79760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79761         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  79762         -1,
  79763         -1,
  79764     },
  79765 #endif /* chips */
  79766 
  79767 #if defined(BCM_56270_A0)
  79768     { /* SOC_REG_INT_XPORT_TXFIFO_MEM_ECC_STATUS_BCM56270_A0r */
  79769         soc_block_list[83],
  79770         soc_genreg,
  79771         1,
  79772         0,
  79773         0x2022200,
  79774         0,
  79775         0,
  79776         4,
  79777         soc_PGW_GX_TXFIFO0_ECC_DBE_STATUSr_fields,
  79778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79779         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  79780         -1,
  79781         -1,
  79782     },
  79783 #endif /* chips */
  79784 
  79785 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79786     defined(BCM_56450_B1)
  79787     { /* SOC_REG_INT_XPORT_TXFIFO_MEM_ECC_STATUS_BCM56450_A0r */
  79788         soc_block_list[83],
  79789         soc_genreg,
  79790         1,
  79791         0,
  79792         0x2024f00,
  79793         0,
  79794         0,
  79795         4,
  79796         soc_PORT_EHG0_RX_DATA_ECC_STATUSr_fields,
  79797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79798         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  79799         -1,
  79800         -1,
  79801     },
  79802 #endif /* chips */
  79803 
  79804 #if defined(BCM_88270_A0)
  79805     { /* SOC_REG_INT_XPORT_TXFIFO_MEM_ECC_STATUS_BCM88270_A0r */
  79806         soc_block_list[149],
  79807         soc_genreg,
  79808         1,
  79809         0,
  79810         0x2021c00,
  79811         0,
  79812         0,
  79813         2,
  79814         soc_XPORT_TXFIFO_MEM_ECC_STATUSr_fields,
  79815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79816         SOC_RESET_MASK_DEC(0x00000005, 0x00000000)
  79817         -1,
  79818         -1,
  79819     },
  79820 #endif /* chips */
  79821 
  79822 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  79823     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  79824     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  79825     { /* SOC_REG_INT_XPORT_TX_FIFO_MEM_ECC_STATUSr */
  79826         soc_block_list[9],
  79827         soc_genreg,
  79828         1,
  79829         0,
  79830         0x80d07,
  79831         0,
  79832         0,
  79833         4,
  79834         soc_XPORT_RX_FIFO_MEM_ECC_STATUSr_fields,
  79835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79836         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  79837         -1,
  79838         -1,
  79839     },
  79840 #endif /* chips */
  79841 
  79842 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79843     defined(BCM_56450_B1)
  79844     { /* SOC_REG_INT_XPORT_WC_UCMEM_CTRLr */
  79845         soc_block_list[83],
  79846         soc_genreg,
  79847         1,
  79848         0,
  79849         0x2024200,
  79850         0,
  79851         0,
  79852         7,
  79853         soc_XPORT_WC_UCMEM_CTRLr_fields,
  79854         SOC_RESET_VAL_DEC(0x0002a900, 0x00000000)
  79855         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  79856         -1,
  79857         -1,
  79858     },
  79859 #endif /* chips */
  79860 
  79861 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79862     defined(BCM_56450_B1)
  79863     { /* SOC_REG_INT_XPORT_XGXS0_STATUS0_REGr */
  79864         soc_block_list[83],
  79865         soc_genreg,
  79866         1,
  79867         0,
  79868         0x2023a00,
  79869         0,
  79870         0,
  79871         25,
  79872         soc_XPORT_XGXS0_STATUS0_REGr_fields,
  79873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79874         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79875         -1,
  79876         -1,
  79877     },
  79878 #endif /* chips */
  79879 
  79880 #if defined(BCM_56260_A0)
  79881     { /* SOC_REG_INT_XPORT_XGXS0_STATUS0_REG_BCM56260_A0r */
  79882         soc_block_list[83],
  79883         soc_genreg,
  79884         1,
  79885         0,
  79886         0x2021300,
  79887         SOC_REG_FLAG_RO,
  79888         0,
  79889         8,
  79890         soc_XPORT_XGXS0_STATUS0_REG_BCM56260_A0r_fields,
  79891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79892         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79893         -1,
  79894         -1,
  79895     },
  79896 #endif /* chips */
  79897 
  79898 #if defined(BCM_56260_B0)
  79899     { /* SOC_REG_INT_XPORT_XGXS0_STATUS0_REG_BCM56260_B0r */
  79900         soc_block_list[83],
  79901         soc_genreg,
  79902         1,
  79903         0,
  79904         0x2021200,
  79905         SOC_REG_FLAG_RO,
  79906         0,
  79907         8,
  79908         soc_XPORT_XGXS0_STATUS0_REG_BCM56260_A0r_fields,
  79909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79910         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79911         -1,
  79912         -1,
  79913     },
  79914 #endif /* chips */
  79915 
  79916 #if defined(BCM_56270_A0)
  79917     { /* SOC_REG_INT_XPORT_XGXS0_STATUS0_REG_BCM56270_A0r */
  79918         soc_block_list[83],
  79919         soc_genreg,
  79920         1,
  79921         0,
  79922         0x2021200,
  79923         SOC_REG_FLAG_RO,
  79924         0,
  79925         8,
  79926         soc_XPORT_XGXS0_STATUS0_REG_BCM56260_A0r_fields,
  79927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79928         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79929         -1,
  79930         -1,
  79931     },
  79932 #endif /* chips */
  79933 
  79934 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79935     defined(BCM_56450_B1)
  79936     { /* SOC_REG_INT_XPORT_XGXS0_STATUS1_REGr */
  79937         soc_block_list[83],
  79938         soc_genreg,
  79939         1,
  79940         0,
  79941         0x2023b00,
  79942         0,
  79943         0,
  79944         27,
  79945         soc_XPORT_XGXS0_STATUS1_REGr_fields,
  79946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79947         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79948         -1,
  79949         -1,
  79950     },
  79951 #endif /* chips */
  79952 
  79953 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  79954     defined(BCM_56450_B1)
  79955     { /* SOC_REG_INT_XPORT_XGXS1_STATUS0_REGr */
  79956         soc_block_list[83],
  79957         soc_genreg,
  79958         1,
  79959         0,
  79960         0x2023c00,
  79961         0,
  79962         0,
  79963         25,
  79964         soc_XPORT_XGXS1_STATUS0_REGr_fields,
  79965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79966         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79967         -1,
  79968         -1,
  79969     },
  79970 #endif /* chips */
  79971 
  79972 #if defined(BCM_56260_A0)
  79973     { /* SOC_REG_INT_XPORT_XGXS1_STATUS0_REG_BCM56260_A0r */
  79974         soc_block_list[83],
  79975         soc_genreg,
  79976         1,
  79977         0,
  79978         0x2021400,
  79979         SOC_REG_FLAG_RO,
  79980         0,
  79981         8,
  79982         soc_XPORT_XGXS1_STATUS0_REG_BCM56260_A0r_fields,
  79983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79984         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79985         -1,
  79986         -1,
  79987     },
  79988 #endif /* chips */
  79989 
  79990 #if defined(BCM_56260_B0)
  79991     { /* SOC_REG_INT_XPORT_XGXS1_STATUS0_REG_BCM56260_B0r */
  79992         soc_block_list[83],
  79993         soc_genreg,
  79994         1,
  79995         0,
  79996         0x2021300,
  79997         SOC_REG_FLAG_RO,
  79998         0,
  79999         8,
  80000         soc_XPORT_XGXS1_STATUS0_REG_BCM56260_A0r_fields,
  80001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80002         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80003         -1,
  80004         -1,
  80005     },
  80006 #endif /* chips */
  80007 
  80008 #if defined(BCM_56270_A0)
  80009     { /* SOC_REG_INT_XPORT_XGXS1_STATUS0_REG_BCM56270_A0r */
  80010         soc_block_list[83],
  80011         soc_genreg,
  80012         1,
  80013         0,
  80014         0x2021300,
  80015         SOC_REG_FLAG_RO,
  80016         0,
  80017         8,
  80018         soc_XPORT_XGXS1_STATUS0_REG_BCM56260_A0r_fields,
  80019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80020         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80021         -1,
  80022         -1,
  80023     },
  80024 #endif /* chips */
  80025 
  80026 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80027     defined(BCM_56450_B1)
  80028     { /* SOC_REG_INT_XPORT_XGXS1_STATUS1_REGr */
  80029         soc_block_list[83],
  80030         soc_genreg,
  80031         1,
  80032         0,
  80033         0x2023d00,
  80034         0,
  80035         0,
  80036         27,
  80037         soc_XPORT_XGXS1_STATUS1_REGr_fields,
  80038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80039         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80040         -1,
  80041         -1,
  80042     },
  80043 #endif /* chips */
  80044 
  80045 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80046     defined(BCM_56450_B1)
  80047     { /* SOC_REG_INT_XPORT_XGXS2_STATUS0_REGr */
  80048         soc_block_list[83],
  80049         soc_genreg,
  80050         1,
  80051         0,
  80052         0x2023e00,
  80053         0,
  80054         0,
  80055         25,
  80056         soc_XPORT_XGXS2_STATUS0_REGr_fields,
  80057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80058         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80059         -1,
  80060         -1,
  80061     },
  80062 #endif /* chips */
  80063 
  80064 #if defined(BCM_56260_A0)
  80065     { /* SOC_REG_INT_XPORT_XGXS2_STATUS0_REG_BCM56260_A0r */
  80066         soc_block_list[83],
  80067         soc_genreg,
  80068         1,
  80069         0,
  80070         0x2021500,
  80071         SOC_REG_FLAG_RO,
  80072         0,
  80073         8,
  80074         soc_XPORT_XGXS2_STATUS0_REG_BCM56260_A0r_fields,
  80075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80076         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80077         -1,
  80078         -1,
  80079     },
  80080 #endif /* chips */
  80081 
  80082 #if defined(BCM_56260_B0)
  80083     { /* SOC_REG_INT_XPORT_XGXS2_STATUS0_REG_BCM56260_B0r */
  80084         soc_block_list[83],
  80085         soc_genreg,
  80086         1,
  80087         0,
  80088         0x2021400,
  80089         SOC_REG_FLAG_RO,
  80090         0,
  80091         8,
  80092         soc_XPORT_XGXS2_STATUS0_REG_BCM56260_A0r_fields,
  80093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80094         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80095         -1,
  80096         -1,
  80097     },
  80098 #endif /* chips */
  80099 
  80100 #if defined(BCM_56270_A0)
  80101     { /* SOC_REG_INT_XPORT_XGXS2_STATUS0_REG_BCM56270_A0r */
  80102         soc_block_list[83],
  80103         soc_genreg,
  80104         1,
  80105         0,
  80106         0x2021400,
  80107         SOC_REG_FLAG_RO,
  80108         0,
  80109         8,
  80110         soc_XPORT_XGXS2_STATUS0_REG_BCM56260_A0r_fields,
  80111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80112         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80113         -1,
  80114         -1,
  80115     },
  80116 #endif /* chips */
  80117 
  80118 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80119     defined(BCM_56450_B1)
  80120     { /* SOC_REG_INT_XPORT_XGXS2_STATUS1_REGr */
  80121         soc_block_list[83],
  80122         soc_genreg,
  80123         1,
  80124         0,
  80125         0x2023f00,
  80126         0,
  80127         0,
  80128         27,
  80129         soc_XPORT_XGXS2_STATUS1_REGr_fields,
  80130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80131         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80132         -1,
  80133         -1,
  80134     },
  80135 #endif /* chips */
  80136 
  80137 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80138     defined(BCM_56450_B1)
  80139     { /* SOC_REG_INT_XPORT_XGXS3_STATUS0_REGr */
  80140         soc_block_list[83],
  80141         soc_genreg,
  80142         1,
  80143         0,
  80144         0x2024000,
  80145         0,
  80146         0,
  80147         25,
  80148         soc_XPORT_XGXS3_STATUS0_REGr_fields,
  80149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80150         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80151         -1,
  80152         -1,
  80153     },
  80154 #endif /* chips */
  80155 
  80156 #if defined(BCM_56260_A0)
  80157     { /* SOC_REG_INT_XPORT_XGXS3_STATUS0_REG_BCM56260_A0r */
  80158         soc_block_list[83],
  80159         soc_genreg,
  80160         1,
  80161         0,
  80162         0x2021600,
  80163         SOC_REG_FLAG_RO,
  80164         0,
  80165         8,
  80166         soc_XPORT_XGXS3_STATUS0_REG_BCM56260_A0r_fields,
  80167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80169         -1,
  80170         -1,
  80171     },
  80172 #endif /* chips */
  80173 
  80174 #if defined(BCM_56260_B0)
  80175     { /* SOC_REG_INT_XPORT_XGXS3_STATUS0_REG_BCM56260_B0r */
  80176         soc_block_list[83],
  80177         soc_genreg,
  80178         1,
  80179         0,
  80180         0x2021500,
  80181         SOC_REG_FLAG_RO,
  80182         0,
  80183         8,
  80184         soc_XPORT_XGXS3_STATUS0_REG_BCM56260_A0r_fields,
  80185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80187         -1,
  80188         -1,
  80189     },
  80190 #endif /* chips */
  80191 
  80192 #if defined(BCM_56270_A0)
  80193     { /* SOC_REG_INT_XPORT_XGXS3_STATUS0_REG_BCM56270_A0r */
  80194         soc_block_list[83],
  80195         soc_genreg,
  80196         1,
  80197         0,
  80198         0x2021500,
  80199         SOC_REG_FLAG_RO,
  80200         0,
  80201         8,
  80202         soc_XPORT_XGXS3_STATUS0_REG_BCM56260_A0r_fields,
  80203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80204         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80205         -1,
  80206         -1,
  80207     },
  80208 #endif /* chips */
  80209 
  80210 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80211     defined(BCM_56450_B1)
  80212     { /* SOC_REG_INT_XPORT_XGXS3_STATUS1_REGr */
  80213         soc_block_list[83],
  80214         soc_genreg,
  80215         1,
  80216         0,
  80217         0x2024100,
  80218         0,
  80219         0,
  80220         27,
  80221         soc_XPORT_XGXS3_STATUS1_REGr_fields,
  80222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80223         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80224         -1,
  80225         -1,
  80226     },
  80227 #endif /* chips */
  80228 
  80229 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80230     { /* SOC_REG_INT_XPORT_XGXS_COUNTER_MODEr */
  80231         soc_block_list[83],
  80232         soc_genreg,
  80233         1,
  80234         0,
  80235         0x80223,
  80236         0,
  80237         0,
  80238         1,
  80239         soc_XLPORT_XGXS_COUNTER_MODEr_fields,
  80240         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  80241         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  80242         -1,
  80243         -1,
  80244     },
  80245 #endif /* chips */
  80246 
  80247 #if defined(BCM_56260_A0)
  80248     { /* SOC_REG_INT_XPORT_XGXS_COUNTER_MODE_BCM56260_A0r */
  80249         soc_block_list[83],
  80250         soc_genreg,
  80251         1,
  80252         0,
  80253         0x2020f00,
  80254         0,
  80255         0,
  80256         1,
  80257         soc_CLPORT_XGXS_COUNTER_MODEr_fields,
  80258         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  80259         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  80260         -1,
  80261         -1,
  80262     },
  80263 #endif /* chips */
  80264 
  80265 #if defined(BCM_56260_B0)
  80266     { /* SOC_REG_INT_XPORT_XGXS_COUNTER_MODE_BCM56260_B0r */
  80267         soc_block_list[83],
  80268         soc_genreg,
  80269         1,
  80270         0,
  80271         0x2020e00,
  80272         0,
  80273         0,
  80274         1,
  80275         soc_CLPORT_XGXS_COUNTER_MODEr_fields,
  80276         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  80277         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  80278         -1,
  80279         -1,
  80280     },
  80281 #endif /* chips */
  80282 
  80283 #if defined(BCM_56270_A0)
  80284     { /* SOC_REG_INT_XPORT_XGXS_COUNTER_MODE_BCM56270_A0r */
  80285         soc_block_list[83],
  80286         soc_genreg,
  80287         1,
  80288         0,
  80289         0x2020e00,
  80290         0,
  80291         0,
  80292         1,
  80293         soc_CLPORT_XGXS_COUNTER_MODEr_fields,
  80294         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  80295         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  80296         -1,
  80297         -1,
  80298     },
  80299 #endif /* chips */
  80300 
  80301 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80302     defined(BCM_56450_B1)
  80303     { /* SOC_REG_INT_XPORT_XGXS_COUNTER_MODE_BCM56450_A0r */
  80304         soc_block_list[83],
  80305         soc_genreg,
  80306         1,
  80307         0,
  80308         0x2022300,
  80309         0,
  80310         0,
  80311         1,
  80312         soc_PORT_XGXS_COUNTER_MODE_BCM56640_A0r_fields,
  80313         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  80314         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  80315         -1,
  80316         -1,
  80317     },
  80318 #endif /* chips */
  80319 
  80320 #if defined(BCM_88270_A0)
  80321     { /* SOC_REG_INT_XPORT_XGXS_COUNTER_MODE_BCM88270_A0r */
  80322         soc_block_list[149],
  80323         soc_genreg,
  80324         1,
  80325         0,
  80326         0x2020c00,
  80327         0,
  80328         0,
  80329         2,
  80330         soc_XPORT_XGXS_COUNTER_MODEr_fields,
  80331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80332         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  80333         -1,
  80334         -1,
  80335     },
  80336 #endif /* chips */
  80337 
  80338 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80339     { /* SOC_REG_INT_XPORT_XGXS_CTRLr */
  80340         soc_block_list[83],
  80341         soc_genreg,
  80342         1,
  80343         0,
  80344         0x80238,
  80345         0,
  80346         0,
  80347         16,
  80348         soc_XPORT_XGXS_CTRLr_fields,
  80349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80350         SOC_RESET_MASK_DEC(0x00f80100, 0x00000000)
  80351         -1,
  80352         -1,
  80353     },
  80354 #endif /* chips */
  80355 
  80356 #if defined(BCM_56260_A0)
  80357     { /* SOC_REG_INT_XPORT_XGXS_CTRL_BCM56260_A0r */
  80358         soc_block_list[83],
  80359         soc_genreg,
  80360         1,
  80361         0,
  80362         0x2021100,
  80363         0,
  80364         0,
  80365         8,
  80366         soc_XPORT_XGXS_CTRL_BCM56260_A0r_fields,
  80367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80368         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80369         -1,
  80370         -1,
  80371     },
  80372 #endif /* chips */
  80373 
  80374 #if defined(BCM_56260_B0)
  80375     { /* SOC_REG_INT_XPORT_XGXS_CTRL_BCM56260_B0r */
  80376         soc_block_list[83],
  80377         soc_genreg,
  80378         1,
  80379         0,
  80380         0x2021000,
  80381         0,
  80382         0,
  80383         8,
  80384         soc_XPORT_XGXS_CTRL_BCM56260_A0r_fields,
  80385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80386         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80387         -1,
  80388         -1,
  80389     },
  80390 #endif /* chips */
  80391 
  80392 #if defined(BCM_56270_A0)
  80393     { /* SOC_REG_INT_XPORT_XGXS_CTRL_BCM56270_A0r */
  80394         soc_block_list[83],
  80395         soc_genreg,
  80396         1,
  80397         0,
  80398         0x2021000,
  80399         0,
  80400         0,
  80401         8,
  80402         soc_XPORT_XGXS_CTRL_BCM56260_A0r_fields,
  80403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80404         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80405         -1,
  80406         -1,
  80407     },
  80408 #endif /* chips */
  80409 
  80410 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80411     defined(BCM_56450_B1)
  80412     { /* SOC_REG_INT_XPORT_XGXS_CTRL_BCM56450_A0r */
  80413         soc_block_list[83],
  80414         soc_genreg,
  80415         1,
  80416         0,
  80417         0x2023800,
  80418         0,
  80419         0,
  80420         20,
  80421         soc_XPORT_XGXS_CTRL_BCM56450_A0r_fields,
  80422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80423         SOC_RESET_MASK_DEC(0x00000100, 0x00000000)
  80424         -1,
  80425         -1,
  80426     },
  80427 #endif /* chips */
  80428 
  80429 #if defined(BCM_88270_A0)
  80430     { /* SOC_REG_INT_XPORT_XGXS_CTRL_BCM88270_A0r */
  80431         soc_block_list[149],
  80432         soc_genreg,
  80433         1,
  80434         0,
  80435         0x2020e00,
  80436         0,
  80437         0,
  80438         8,
  80439         soc_XPORT_XGXS_CTRL_BCM88270_A0r_fields,
  80440         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  80441         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  80442         -1,
  80443         -1,
  80444     },
  80445 #endif /* chips */
  80446 
  80447 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  80448     defined(BCM_56450_B1)
  80449     { /* SOC_REG_INT_XPORT_XGXS_GEN_STATUS_REGr */
  80450         soc_block_list[83],
  80451         soc_genreg,
  80452         1,
  80453         0,
  80454         0x2023900,
  80455         0,
  80456         0,
  80457         8,
  80458         soc_XPORT_XGXS_GEN_STATUS_REGr_fields,
  80459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80460         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80461         -1,
  80462         -1,
  80463     },
  80464 #endif /* chips */
  80465 
  80466 #if defined(BCM_56260_A0)
  80467     { /* SOC_REG_INT_XPORT_XGXS_GEN_STATUS_REG_BCM56260_A0r */
  80468         soc_block_list[83],
  80469         soc_genreg,
  80470         1,
  80471         0,
  80472         0x2021200,
  80473         SOC_REG_FLAG_RO,
  80474         0,
  80475         2,
  80476         soc_XPORT_XGXS_GEN_STATUS_REG_BCM56260_A0r_fields,
  80477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80478         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80479         -1,
  80480         -1,
  80481     },
  80482 #endif /* chips */
  80483 
  80484 #if defined(BCM_56260_B0)
  80485     { /* SOC_REG_INT_XPORT_XGXS_GEN_STATUS_REG_BCM56260_B0r */
  80486         soc_block_list[83],
  80487         soc_genreg,
  80488         1,
  80489         0,
  80490         0x2021100,
  80491         SOC_REG_FLAG_RO,
  80492         0,
  80493         2,
  80494         soc_XPORT_XGXS_GEN_STATUS_REG_BCM56260_A0r_fields,
  80495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80496         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80497         -1,
  80498         -1,
  80499     },
  80500 #endif /* chips */
  80501 
  80502 #if defined(BCM_56270_A0)
  80503     { /* SOC_REG_INT_XPORT_XGXS_GEN_STATUS_REG_BCM56270_A0r */
  80504         soc_block_list[83],
  80505         soc_genreg,
  80506         1,
  80507         0,
  80508         0x2021100,
  80509         SOC_REG_FLAG_RO,
  80510         0,
  80511         2,
  80512         soc_XPORT_XGXS_GEN_STATUS_REG_BCM56260_A0r_fields,
  80513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80514         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80515         -1,
  80516         -1,
  80517     },
  80518 #endif /* chips */
  80519 
  80520 #if defined(BCM_88270_A0)
  80521     { /* SOC_REG_INT_XPORT_XGXS_GEN_STATUS_REG_BCM88270_A0r */
  80522         soc_block_list[149],
  80523         soc_genreg,
  80524         1,
  80525         0,
  80526         0x2020f00,
  80527         SOC_REG_FLAG_RO |
  80528                           SOC_REG_FLAG_SIGNAL,
  80529         0,
  80530         2,
  80531         soc_XPORT_XGXS_GEN_STATUS_REG_BCM88270_A0r_fields,
  80532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80533         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  80534         -1,
  80535         -1,
  80536     },
  80537 #endif /* chips */
  80538 
  80539 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  80540     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  80541     { /* SOC_REG_INT_XPORT_XGXS_NEWCTL_REGr */
  80542         soc_block_list[9],
  80543         soc_genreg,
  80544         1,
  80545         0,
  80546         0x80e00,
  80547         0,
  80548         0,
  80549         1,
  80550         soc_XGPORT_EXTRA_XGXS_NEWCTL_REGr_fields,
  80551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80552         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80553         -1,
  80554         -1,
  80555     },
  80556 #endif /* chips */
  80557 
  80558 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80559     { /* SOC_REG_INT_XPORT_XGXS_NEWCTL_REG_BCM56440_A0r */
  80560         soc_block_list[83],
  80561         soc_genreg,
  80562         1,
  80563         0,
  80564         0x80239,
  80565         0,
  80566         0,
  80567         1,
  80568         soc_XQPORT_XGXS_NEWCTL_REGr_fields,
  80569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80570         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  80571         -1,
  80572         -1,
  80573     },
  80574 #endif /* chips */
  80575 
  80576 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  80577     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  80578     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  80579     { /* SOC_REG_INT_XPORT_XGXS_NEWCTL_REG_BCM56634_A0r */
  80580         soc_block_list[9],
  80581         soc_genreg,
  80582         1,
  80583         0,
  80584         0x80d00,
  80585         0,
  80586         0,
  80587         1,
  80588         soc_XPORT_XGXS_NEWCTL_REGr_fields,
  80589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80590         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  80591         -1,
  80592         -1,
  80593     },
  80594 #endif /* chips */
  80595 
  80596 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  80597     { /* SOC_REG_INT_XPORT_XGXS_NEWCTL_REG_BCM56820_A0r */
  80598         soc_block_list[9],
  80599         soc_portreg,
  80600         1,
  80601         0,
  80602         0xc00,
  80603         0,
  80604         0,
  80605         1,
  80606         soc_XGPORT_EXTRA_XGXS_NEWCTL_REGr_fields,
  80607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80608         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80609         -1,
  80610         -1,
  80611     },
  80612 #endif /* chips */
  80613 
  80614 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  80615     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  80616     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS0_REGr */
  80617         soc_block_list[9],
  80618         soc_genreg,
  80619         1,
  80620         0,
  80621         0x80e01,
  80622         SOC_REG_FLAG_RO,
  80623         0,
  80624         8,
  80625         soc_XGPORT_EXTRA_XGXS_NEWSTATUS0_REGr_fields,
  80626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80628         -1,
  80629         -1,
  80630     },
  80631 #endif /* chips */
  80632 
  80633 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80634     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS0_REG_BCM56440_A0r */
  80635         soc_block_list[83],
  80636         soc_genreg,
  80637         1,
  80638         0,
  80639         0x8023b,
  80640         SOC_REG_FLAG_RO,
  80641         0,
  80642         8,
  80643         soc_XGPORT_EXTRA_XGXS_NEWSTATUS0_REGr_fields,
  80644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80646         -1,
  80647         -1,
  80648     },
  80649 #endif /* chips */
  80650 
  80651 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  80652     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  80653     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  80654     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS0_REG_BCM56634_A0r */
  80655         soc_block_list[9],
  80656         soc_genreg,
  80657         1,
  80658         0,
  80659         0x80d01,
  80660         SOC_REG_FLAG_RO,
  80661         0,
  80662         7,
  80663         soc_XPORT_XGXS_NEWSTATUS0_REGr_fields,
  80664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80665         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80666         -1,
  80667         -1,
  80668     },
  80669 #endif /* chips */
  80670 
  80671 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  80672     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS0_REG_BCM56820_A0r */
  80673         soc_block_list[9],
  80674         soc_portreg,
  80675         1,
  80676         0,
  80677         0xc01,
  80678         SOC_REG_FLAG_RO,
  80679         0,
  80680         8,
  80681         soc_XGPORT_EXTRA_XGXS_NEWSTATUS0_REGr_fields,
  80682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80683         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80684         -1,
  80685         -1,
  80686     },
  80687 #endif /* chips */
  80688 
  80689 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  80690     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  80691     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS1_REGr */
  80692         soc_block_list[9],
  80693         soc_genreg,
  80694         1,
  80695         0,
  80696         0x80e02,
  80697         SOC_REG_FLAG_RO,
  80698         0,
  80699         8,
  80700         soc_XGPORT_EXTRA_XGXS_NEWSTATUS1_REGr_fields,
  80701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80702         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80703         -1,
  80704         -1,
  80705     },
  80706 #endif /* chips */
  80707 
  80708 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80709     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS1_REG_BCM56440_A0r */
  80710         soc_block_list[83],
  80711         soc_genreg,
  80712         1,
  80713         0,
  80714         0x8023c,
  80715         SOC_REG_FLAG_RO,
  80716         0,
  80717         8,
  80718         soc_XGPORT_EXTRA_XGXS_NEWSTATUS1_REGr_fields,
  80719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80720         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80721         -1,
  80722         -1,
  80723     },
  80724 #endif /* chips */
  80725 
  80726 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  80727     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  80728     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  80729     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS1_REG_BCM56634_A0r */
  80730         soc_block_list[9],
  80731         soc_genreg,
  80732         1,
  80733         0,
  80734         0x80d02,
  80735         SOC_REG_FLAG_RO,
  80736         0,
  80737         26,
  80738         soc_XPORT_XGXS_NEWSTATUS1_REGr_fields,
  80739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80740         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80741         -1,
  80742         -1,
  80743     },
  80744 #endif /* chips */
  80745 
  80746 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  80747     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS1_REG_BCM56820_A0r */
  80748         soc_block_list[9],
  80749         soc_portreg,
  80750         1,
  80751         0,
  80752         0xc02,
  80753         SOC_REG_FLAG_RO,
  80754         0,
  80755         8,
  80756         soc_XGPORT_EXTRA_XGXS_NEWSTATUS1_REGr_fields,
  80757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80758         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80759         -1,
  80760         -1,
  80761     },
  80762 #endif /* chips */
  80763 
  80764 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  80765     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  80766     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS2_REGr */
  80767         soc_block_list[9],
  80768         soc_genreg,
  80769         1,
  80770         0,
  80771         0x80e03,
  80772         SOC_REG_FLAG_RO,
  80773         0,
  80774         8,
  80775         soc_XGPORT_EXTRA_XGXS_NEWSTATUS2_REGr_fields,
  80776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80777         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80778         -1,
  80779         -1,
  80780     },
  80781 #endif /* chips */
  80782 
  80783 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80784     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS2_REG_BCM56440_A0r */
  80785         soc_block_list[83],
  80786         soc_genreg,
  80787         1,
  80788         0,
  80789         0x8023d,
  80790         SOC_REG_FLAG_RO,
  80791         0,
  80792         3,
  80793         soc_XPORT_XGXS_NEWSTATUS2_REGr_fields,
  80794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80795         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80796         -1,
  80797         -1,
  80798     },
  80799 #endif /* chips */
  80800 
  80801 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  80802     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS2_REG_BCM56820_A0r */
  80803         soc_block_list[9],
  80804         soc_portreg,
  80805         1,
  80806         0,
  80807         0xc03,
  80808         SOC_REG_FLAG_RO,
  80809         0,
  80810         8,
  80811         soc_XGPORT_EXTRA_XGXS_NEWSTATUS2_REGr_fields,
  80812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80814         -1,
  80815         -1,
  80816     },
  80817 #endif /* chips */
  80818 
  80819 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  80820     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  80821     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS3_REGr */
  80822         soc_block_list[9],
  80823         soc_genreg,
  80824         1,
  80825         0,
  80826         0x80e04,
  80827         SOC_REG_FLAG_RO,
  80828         0,
  80829         2,
  80830         soc_XGPORT_EXTRA_XGXS_NEWSTATUS3_REGr_fields,
  80831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80832         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80833         -1,
  80834         -1,
  80835     },
  80836 #endif /* chips */
  80837 
  80838 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80839     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS3_REG_BCM56440_A0r */
  80840         soc_block_list[83],
  80841         soc_genreg,
  80842         1,
  80843         0,
  80844         0x8023e,
  80845         SOC_REG_FLAG_RO,
  80846         0,
  80847         2,
  80848         soc_XGPORT_EXTRA_XGXS_NEWSTATUS3_REGr_fields,
  80849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80850         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80851         -1,
  80852         -1,
  80853     },
  80854 #endif /* chips */
  80855 
  80856 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  80857     { /* SOC_REG_INT_XPORT_XGXS_NEWSTATUS3_REG_BCM56820_A0r */
  80858         soc_block_list[9],
  80859         soc_portreg,
  80860         1,
  80861         0,
  80862         0xc04,
  80863         SOC_REG_FLAG_RO,
  80864         0,
  80865         2,
  80866         soc_XGPORT_EXTRA_XGXS_NEWSTATUS3_REGr_fields,
  80867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80868         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80869         -1,
  80870         -1,
  80871     },
  80872 #endif /* chips */
  80873 
  80874 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80875     { /* SOC_REG_INT_XPORT_XGXS_STATUS_REGr */
  80876         soc_block_list[83],
  80877         soc_genreg,
  80878         1,
  80879         0,
  80880         0x8023a,
  80881         SOC_REG_FLAG_RO,
  80882         0,
  80883         24,
  80884         soc_XPORT_XGXS_STATUS_REGr_fields,
  80885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80886         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80887         -1,
  80888         -1,
  80889     },
  80890 #endif /* chips */
  80891 
  80892 #if defined(BCM_88270_A0)
  80893     { /* SOC_REG_INT_XPORT_XGXS_STATUS_REG_BCM88270_A0r */
  80894         soc_block_list[149],
  80895         soc_portreg,
  80896         1,
  80897         0,
  80898         0x20700,
  80899         SOC_REG_FLAG_RO |
  80900                           SOC_REG_FLAG_SIGNAL,
  80901         0,
  80902         8,
  80903         soc_XPORT_XGXS_STATUS_REG_BCM88270_A0r_fields,
  80904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80905         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  80906         -1,
  80907         -1,
  80908     },
  80909 #endif /* chips */
  80910 
  80911 #if defined(BCM_88270_A0)
  80912     { /* SOC_REG_INT_XPORT_XLMAC_CONTROLr */
  80913         soc_block_list[149],
  80914         soc_genreg,
  80915         1,
  80916         0,
  80917         0x2020a00,
  80918         0,
  80919         0,
  80920         3,
  80921         soc_XPORT_XLMAC_CONTROLr_fields,
  80922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80923         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  80924         -1,
  80925         -1,
  80926     },
  80927 #endif /* chips */
  80928 
  80929 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  80930     { /* SOC_REG_INT_XPORT_XMAC_CONTROLr */
  80931         soc_block_list[83],
  80932         soc_genreg,
  80933         1,
  80934         0,
  80935         0x80221,
  80936         0,
  80937         0,
  80938         1,
  80939         soc_XLPORT_XMAC_CONTROLr_fields,
  80940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80941         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80942         -1,
  80943         -1,
  80944     },
  80945 #endif /* chips */
  80946 
  80947 #if defined(BCM_56260_A0)
  80948     { /* SOC_REG_INT_XPORT_XMAC_CONTROL_BCM56260_A0r */
  80949         soc_block_list[83],
  80950         soc_genreg,
  80951         1,
  80952         0,
  80953         0x2020d00,
  80954         0,
  80955         0,
  80956         3,
  80957         soc_XPORT_XMAC_CONTROL_BCM56260_A0r_fields,
  80958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80959         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80960         -1,
  80961         -1,
  80962     },
  80963 #endif /* chips */
  80964 
  80965 #if defined(BCM_56260_B0)
  80966     { /* SOC_REG_INT_XPORT_XMAC_CONTROL_BCM56260_B0r */
  80967         soc_block_list[83],
  80968         soc_genreg,
  80969         1,
  80970         0,
  80971         0x2020c00,
  80972         0,
  80973         0,
  80974         3,
  80975         soc_XPORT_XMAC_CONTROL_BCM56260_A0r_fields,
  80976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80977         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80978         -1,
  80979         -1,
  80980     },
  80981 #endif /* chips */
  80982 
  80983 #if defined(BCM_56270_A0)
  80984     { /* SOC_REG_INT_XPORT_XMAC_CONTROL_BCM56270_A0r */
  80985         soc_block_list[83],
  80986         soc_genreg,
  80987         1,
  80988         0,
  80989         0x2020c00,
  80990         0,
  80991         0,
  80992         3,
  80993         soc_XPORT_XMAC_CONTROL_BCM56260_A0r_fields,
  80994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80995         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80996         -1,
  80997         -1,
  80998     },
  80999 #endif /* chips */
  81000 
  81001 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81002     defined(BCM_56450_B1)
  81003     { /* SOC_REG_INT_XPORT_XMAC_CONTROL_BCM56450_A0r */
  81004         soc_block_list[83],
  81005         soc_genreg,
  81006         1,
  81007         0,
  81008         0x2022100,
  81009         0,
  81010         0,
  81011         3,
  81012         soc_XPORT_XMAC_CONTROLr_fields,
  81013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81014         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  81015         -1,
  81016         -1,
  81017     },
  81018 #endif /* chips */
  81019 
  81020 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81021     { /* SOC_REG_INT_XP_EEE_COUNTER_MODEr */
  81022         soc_block_list[83],
  81023         soc_portreg,
  81024         1,
  81025         0,
  81026         0x219,
  81027         0,
  81028         0,
  81029         1,
  81030         soc_XLP_EEE_COUNTER_MODEr_fields,
  81031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81032         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81033         -1,
  81034         -1,
  81035     },
  81036 #endif /* chips */
  81037 
  81038 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81039     { /* SOC_REG_INT_XP_EEE_COUNTER_MODE_BCM56260_A0r */
  81040         soc_block_list[83],
  81041         soc_portreg,
  81042         1,
  81043         0,
  81044         0x20600,
  81045         0,
  81046         0,
  81047         1,
  81048         soc_CLPORT_EEE_COUNTER_MODEr_fields,
  81049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81050         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81051         -1,
  81052         -1,
  81053     },
  81054 #endif /* chips */
  81055 
  81056 #if defined(BCM_56270_A0)
  81057     { /* SOC_REG_INT_XP_EEE_COUNTER_MODE_BCM56270_A0r */
  81058         soc_block_list[83],
  81059         soc_portreg,
  81060         1,
  81061         0,
  81062         0x20600,
  81063         0,
  81064         0,
  81065         1,
  81066         soc_CLPORT_EEE_COUNTER_MODEr_fields,
  81067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81068         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81069         -1,
  81070         -1,
  81071     },
  81072 #endif /* chips */
  81073 
  81074 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81075     defined(BCM_56450_B1)
  81076     { /* SOC_REG_INT_XP_EEE_COUNTER_MODE_BCM56450_A0r */
  81077         soc_block_list[83],
  81078         soc_portreg,
  81079         1,
  81080         0,
  81081         0x21900,
  81082         0,
  81083         0,
  81084         1,
  81085         soc_XP_EEE_COUNTER_MODEr_fields,
  81086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81087         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81088         -1,
  81089         -1,
  81090     },
  81091 #endif /* chips */
  81092 
  81093 #if defined(BCM_88270_A0)
  81094     { /* SOC_REG_INT_XP_EEE_COUNTER_MODE_BCM88270_A0r */
  81095         soc_block_list[149],
  81096         soc_portreg,
  81097         1,
  81098         0,
  81099         0x20200,
  81100         0,
  81101         0,
  81102         1,
  81103         soc_XP_EEE_COUNTER_MODE_BCM88270_A0r_fields,
  81104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81105         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81106         -1,
  81107         -1,
  81108     },
  81109 #endif /* chips */
  81110 
  81111 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  81112     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  81113     { /* SOC_REG_INT_XP_EGR_PKT_DROP_CTLr */
  81114         soc_block_list[0],
  81115         soc_genreg,
  81116         1,
  81117         0,
  81118         0x8001d,
  81119         0,
  81120         0,
  81121         1,
  81122         soc_GE_EGR_PKT_DROP_CTLr_fields,
  81123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81124         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81125         -1,
  81126         -1,
  81127     },
  81128 #endif /* chips */
  81129 
  81130 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  81131     defined(BCM_56334_B0)
  81132     { /* SOC_REG_INT_XP_EGR_PKT_DROP_CTL_BCM56334_A0r */
  81133         soc_block_list[14],
  81134         soc_portreg,
  81135         1,
  81136         0,
  81137         0x820,
  81138         0,
  81139         0,
  81140         1,
  81141         soc_GE_EGR_PKT_DROP_CTLr_fields,
  81142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81143         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81144         -1,
  81145         -1,
  81146     },
  81147 #endif /* chips */
  81148 
  81149 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  81150     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  81151     { /* SOC_REG_INT_XP_EGR_PKT_DROP_CTL_BCM56624_A0r */
  81152         soc_block_list[204],
  81153         soc_portreg,
  81154         1,
  81155         0,
  81156         0x820,
  81157         0,
  81158         0,
  81159         1,
  81160         soc_GE_EGR_PKT_DROP_CTLr_fields,
  81161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81162         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81163         -1,
  81164         -1,
  81165     },
  81166 #endif /* chips */
  81167 
  81168 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  81169     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  81170     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  81171     { /* SOC_REG_INT_XP_EGR_PKT_DROP_CTL_BCM56634_A0r */
  81172         soc_block_list[208],
  81173         soc_portreg,
  81174         1,
  81175         0,
  81176         0x820,
  81177         0,
  81178         0,
  81179         1,
  81180         soc_GE_EGR_PKT_DROP_CTLr_fields,
  81181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81182         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81183         -1,
  81184         -1,
  81185     },
  81186 #endif /* chips */
  81187 
  81188 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  81189     defined(BCM_56820_A0)
  81190     { /* SOC_REG_INT_XP_EGR_PKT_DROP_CTL_BCM56800_A0r */
  81191         soc_block_list[9],
  81192         soc_portreg,
  81193         1,
  81194         0,
  81195         0x820,
  81196         0,
  81197         0,
  81198         1,
  81199         soc_GE_EGR_PKT_DROP_CTLr_fields,
  81200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81201         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81202         -1,
  81203         -1,
  81204     },
  81205 #endif /* chips */
  81206 
  81207 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81208     { /* SOC_REG_INT_XP_FIFO_OVERFLOW_STATUSr */
  81209         soc_block_list[83],
  81210         soc_portreg,
  81211         1,
  81212         0,
  81213         0x20400,
  81214         0,
  81215         0,
  81216         3,
  81217         soc_XP_FIFO_OVERFLOW_STATUSr_fields,
  81218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81219         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  81220         -1,
  81221         -1,
  81222     },
  81223 #endif /* chips */
  81224 
  81225 #if defined(BCM_56270_A0)
  81226     { /* SOC_REG_INT_XP_FIFO_OVERFLOW_STATUS_BCM56270_A0r */
  81227         soc_block_list[83],
  81228         soc_portreg,
  81229         1,
  81230         0,
  81231         0x20400,
  81232         0,
  81233         0,
  81234         3,
  81235         soc_XP_FIFO_OVERFLOW_STATUSr_fields,
  81236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81237         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  81238         -1,
  81239         -1,
  81240     },
  81241 #endif /* chips */
  81242 
  81243 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81244     { /* SOC_REG_INT_XP_TXFIFO_CELL_CNTr */
  81245         soc_block_list[83],
  81246         soc_portreg,
  81247         1,
  81248         0,
  81249         0x211,
  81250         SOC_REG_FLAG_RO,
  81251         0,
  81252         1,
  81253         soc_XLP_TXFIFO_CELL_CNTr_fields,
  81254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81255         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  81256         -1,
  81257         -1,
  81258     },
  81259 #endif /* chips */
  81260 
  81261 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81262     { /* SOC_REG_INT_XP_TXFIFO_CELL_CNT_BCM56260_A0r */
  81263         soc_block_list[83],
  81264         soc_portreg,
  81265         1,
  81266         0,
  81267         0x20200,
  81268         SOC_REG_FLAG_RO,
  81269         0,
  81270         1,
  81271         soc_IECELL_TXFIFO_CELL_CNTr_fields,
  81272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81273         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  81274         -1,
  81275         -1,
  81276     },
  81277 #endif /* chips */
  81278 
  81279 #if defined(BCM_56270_A0)
  81280     { /* SOC_REG_INT_XP_TXFIFO_CELL_CNT_BCM56270_A0r */
  81281         soc_block_list[83],
  81282         soc_portreg,
  81283         1,
  81284         0,
  81285         0x20200,
  81286         SOC_REG_FLAG_RO,
  81287         0,
  81288         1,
  81289         soc_IECELL_TXFIFO_CELL_CNTr_fields,
  81290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81291         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  81292         -1,
  81293         -1,
  81294     },
  81295 #endif /* chips */
  81296 
  81297 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81298     defined(BCM_56450_B1)
  81299     { /* SOC_REG_INT_XP_TXFIFO_CELL_CNT_BCM56450_A0r */
  81300         soc_block_list[83],
  81301         soc_portreg,
  81302         1,
  81303         0,
  81304         0x21100,
  81305         SOC_REG_FLAG_RO,
  81306         0,
  81307         1,
  81308         soc_PORT_CDC_RXFIFO_CELL_CNT_BCM56640_A0r_fields,
  81309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81310         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  81311         -1,
  81312         -1,
  81313     },
  81314 #endif /* chips */
  81315 
  81316 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81317     { /* SOC_REG_INT_XP_TXFIFO_CELL_REQ_CNTr */
  81318         soc_block_list[83],
  81319         soc_portreg,
  81320         1,
  81321         0,
  81322         0x212,
  81323         SOC_REG_FLAG_RO,
  81324         0,
  81325         1,
  81326         soc_XLP_TXFIFO_CELL_REQ_CNTr_fields,
  81327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81328         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  81329         -1,
  81330         -1,
  81331     },
  81332 #endif /* chips */
  81333 
  81334 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81335     { /* SOC_REG_INT_XP_TXFIFO_CELL_REQ_CNT_BCM56260_A0r */
  81336         soc_block_list[83],
  81337         soc_portreg,
  81338         1,
  81339         0,
  81340         0x20300,
  81341         SOC_REG_FLAG_RO,
  81342         0,
  81343         1,
  81344         soc_IECELL_TXFIFO_CELL_REQ_CNTr_fields,
  81345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81346         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  81347         -1,
  81348         -1,
  81349     },
  81350 #endif /* chips */
  81351 
  81352 #if defined(BCM_56270_A0)
  81353     { /* SOC_REG_INT_XP_TXFIFO_CELL_REQ_CNT_BCM56270_A0r */
  81354         soc_block_list[83],
  81355         soc_portreg,
  81356         1,
  81357         0,
  81358         0x20300,
  81359         SOC_REG_FLAG_RO,
  81360         0,
  81361         1,
  81362         soc_IECELL_TXFIFO_CELL_REQ_CNTr_fields,
  81363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81364         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  81365         -1,
  81366         -1,
  81367     },
  81368 #endif /* chips */
  81369 
  81370 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81371     defined(BCM_56450_B1)
  81372     { /* SOC_REG_INT_XP_TXFIFO_CELL_REQ_CNT_BCM56450_A0r */
  81373         soc_block_list[83],
  81374         soc_portreg,
  81375         1,
  81376         0,
  81377         0x21200,
  81378         SOC_REG_FLAG_RO,
  81379         0,
  81380         1,
  81381         soc_PORT_CDC_TXFIFO_CELL_REQ_CNT_BCM56640_A0r_fields,
  81382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81383         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  81384         -1,
  81385         -1,
  81386     },
  81387 #endif /* chips */
  81388 
  81389 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81390     { /* SOC_REG_INT_XP_TXFIFO_OVRFLWr */
  81391         soc_block_list[83],
  81392         soc_portreg,
  81393         1,
  81394         0,
  81395         0x213,
  81396         SOC_REG_FLAG_RO,
  81397         0,
  81398         1,
  81399         soc_GE0_GBOD_OVRFLWr_fields,
  81400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81401         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81402         -1,
  81403         -1,
  81404     },
  81405 #endif /* chips */
  81406 
  81407 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81408     defined(BCM_56450_B1)
  81409     { /* SOC_REG_INT_XP_TXFIFO_OVRFLW_BCM56450_A0r */
  81410         soc_block_list[83],
  81411         soc_portreg,
  81412         1,
  81413         0,
  81414         0x21300,
  81415         SOC_REG_FLAG_RO,
  81416         0,
  81417         1,
  81418         soc_PORT_CDC_RXFIFO_OVRFLW_BCM56640_A0r_fields,
  81419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81420         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81421         -1,
  81422         -1,
  81423     },
  81424 #endif /* chips */
  81425 
  81426 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  81427     { /* SOC_REG_INT_XP_TXFIFO_PKT_DROP_CTLr */
  81428         soc_block_list[83],
  81429         soc_portreg,
  81430         1,
  81431         0,
  81432         0x210,
  81433         0,
  81434         0,
  81435         1,
  81436         soc_XLP_TXFIFO_PKT_DROP_CTLr_fields,
  81437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81438         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81439         -1,
  81440         -1,
  81441     },
  81442 #endif /* chips */
  81443 
  81444 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  81445     { /* SOC_REG_INT_XP_TXFIFO_PKT_DROP_CTL_BCM56260_A0r */
  81446         soc_block_list[83],
  81447         soc_portreg,
  81448         1,
  81449         0,
  81450         0x20100,
  81451         0,
  81452         0,
  81453         1,
  81454         soc_IECELL_TXFIFO_PKT_DROP_CTLr_fields,
  81455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81456         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81457         -1,
  81458         -1,
  81459     },
  81460 #endif /* chips */
  81461 
  81462 #if defined(BCM_56270_A0)
  81463     { /* SOC_REG_INT_XP_TXFIFO_PKT_DROP_CTL_BCM56270_A0r */
  81464         soc_block_list[83],
  81465         soc_portreg,
  81466         1,
  81467         0,
  81468         0x20100,
  81469         0,
  81470         0,
  81471         1,
  81472         soc_IECELL_TXFIFO_PKT_DROP_CTLr_fields,
  81473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81474         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81475         -1,
  81476         -1,
  81477     },
  81478 #endif /* chips */
  81479 
  81480 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  81481     defined(BCM_56450_B1)
  81482     { /* SOC_REG_INT_XP_TXFIFO_PKT_DROP_CTL_BCM56450_A0r */
  81483         soc_block_list[83],
  81484         soc_portreg,
  81485         1,
  81486         0,
  81487         0x21000,
  81488         0,
  81489         0,
  81490         1,
  81491         soc_PORT_TXFIFO_PKT_DROP_CTL_BCM56640_A0r_fields,
  81492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81493         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81494         -1,
  81495         -1,
  81496     },
  81497 #endif /* chips */
  81498 
  81499 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  81500     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  81501     { /* SOC_REG_INT_XP_XBODE_CELL_CNTr */
  81502         soc_block_list[0],
  81503         soc_genreg,
  81504         1,
  81505         0,
  81506         0x8001e,
  81507         SOC_REG_FLAG_RO,
  81508         0,
  81509         1,
  81510         soc_XP_XBODE_CELL_CNTr_fields,
  81511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81512         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81513         -1,
  81514         -1,
  81515     },
  81516 #endif /* chips */
  81517 
  81518 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  81519     defined(BCM_56334_B0)
  81520     { /* SOC_REG_INT_XP_XBODE_CELL_CNT_BCM56334_A0r */
  81521         soc_block_list[14],
  81522         soc_portreg,
  81523         1,
  81524         0,
  81525         0x821,
  81526         SOC_REG_FLAG_RO,
  81527         0,
  81528         1,
  81529         soc_XP_XBODE_CELL_CNTr_fields,
  81530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81531         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81532         -1,
  81533         -1,
  81534     },
  81535 #endif /* chips */
  81536 
  81537 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  81538     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  81539     { /* SOC_REG_INT_XP_XBODE_CELL_CNT_BCM56624_A0r */
  81540         soc_block_list[204],
  81541         soc_portreg,
  81542         1,
  81543         0,
  81544         0x821,
  81545         SOC_REG_FLAG_RO,
  81546         0,
  81547         1,
  81548         soc_XP_XBODE_CELL_CNTr_fields,
  81549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81550         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81551         -1,
  81552         -1,
  81553     },
  81554 #endif /* chips */
  81555 
  81556 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  81557     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  81558     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  81559     { /* SOC_REG_INT_XP_XBODE_CELL_CNT_BCM56634_A0r */
  81560         soc_block_list[208],
  81561         soc_portreg,
  81562         1,
  81563         0,
  81564         0x821,
  81565         SOC_REG_FLAG_RO,
  81566         0,
  81567         1,
  81568         soc_XP_XBODE_CELL_CNTr_fields,
  81569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81570         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81571         -1,
  81572         -1,
  81573     },
  81574 #endif /* chips */
  81575 
  81576 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  81577     defined(BCM_56820_A0)
  81578     { /* SOC_REG_INT_XP_XBODE_CELL_CNT_BCM56800_A0r */
  81579         soc_block_list[9],
  81580         soc_portreg,
  81581         1,
  81582         0,
  81583         0x821,
  81584         SOC_REG_FLAG_RO,
  81585         0,
  81586         1,
  81587         soc_XP_XBODE_CELL_CNTr_fields,
  81588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81589         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81590         -1,
  81591         -1,
  81592     },
  81593 #endif /* chips */
  81594 
  81595 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  81596     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  81597     { /* SOC_REG_INT_XP_XBODE_CELL_REQ_CNTr */
  81598         soc_block_list[0],
  81599         soc_genreg,
  81600         1,
  81601         0,
  81602         0x8001f,
  81603         SOC_REG_FLAG_RO,
  81604         0,
  81605         1,
  81606         soc_XP_XBODE_CELL_REQ_CNTr_fields,
  81607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81608         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81609         -1,
  81610         -1,
  81611     },
  81612 #endif /* chips */
  81613 
  81614 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  81615     defined(BCM_56334_B0)
  81616     { /* SOC_REG_INT_XP_XBODE_CELL_REQ_CNT_BCM56334_A0r */
  81617         soc_block_list[14],
  81618         soc_portreg,
  81619         1,
  81620         0,
  81621         0x822,
  81622         SOC_REG_FLAG_RO,
  81623         0,
  81624         1,
  81625         soc_XP_XBODE_CELL_REQ_CNTr_fields,
  81626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81627         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81628         -1,
  81629         -1,
  81630     },
  81631 #endif /* chips */
  81632 
  81633 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  81634     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  81635     { /* SOC_REG_INT_XP_XBODE_CELL_REQ_CNT_BCM56624_A0r */
  81636         soc_block_list[204],
  81637         soc_portreg,
  81638         1,
  81639         0,
  81640         0x822,
  81641         SOC_REG_FLAG_RO,
  81642         0,
  81643         1,
  81644         soc_XP_XBODE_CELL_REQ_CNTr_fields,
  81645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81646         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81647         -1,
  81648         -1,
  81649     },
  81650 #endif /* chips */
  81651 
  81652 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  81653     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  81654     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  81655     { /* SOC_REG_INT_XP_XBODE_CELL_REQ_CNT_BCM56634_A0r */
  81656         soc_block_list[208],
  81657         soc_portreg,
  81658         1,
  81659         0,
  81660         0x822,
  81661         SOC_REG_FLAG_RO,
  81662         0,
  81663         1,
  81664         soc_XP_XBODE_CELL_REQ_CNTr_fields,
  81665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81666         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81667         -1,
  81668         -1,
  81669     },
  81670 #endif /* chips */
  81671 
  81672 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  81673     defined(BCM_56820_A0)
  81674     { /* SOC_REG_INT_XP_XBODE_CELL_REQ_CNT_BCM56800_A0r */
  81675         soc_block_list[9],
  81676         soc_portreg,
  81677         1,
  81678         0,
  81679         0x822,
  81680         SOC_REG_FLAG_RO,
  81681         0,
  81682         1,
  81683         soc_XP_XBODE_CELL_REQ_CNTr_fields,
  81684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81685         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81686         -1,
  81687         -1,
  81688     },
  81689 #endif /* chips */
  81690 
  81691 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  81692     defined(BCM_56504_B0)
  81693     { /* SOC_REG_INT_XQCOSARBSELr */
  81694         soc_block_list[4],
  81695         soc_portreg,
  81696         1,
  81697         0,
  81698         0x45,
  81699         0,
  81700         0,
  81701         1,
  81702         soc_XQCOSARBSELr_fields,
  81703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81704         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  81705         -1,
  81706         -1,
  81707     },
  81708 #endif /* chips */
  81709 
  81710 #if defined(BCM_53400_A0)
  81711     { /* SOC_REG_INT_XQCOSARBSEL_BCM53400_A0r */
  81712         soc_block_list[4],
  81713         soc_portreg,
  81714         1,
  81715         0,
  81716         0x13200,
  81717         0,
  81718         0,
  81719         2,
  81720         soc_XQCOSARBSEL_BCM53400_A0r_fields,
  81721         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  81722         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81723         -1,
  81724         79,
  81725     },
  81726 #endif /* chips */
  81727 
  81728 #if defined(BCM_53540_A0)
  81729     { /* SOC_REG_INT_XQCOSARBSEL_BCM53540_A0r */
  81730         soc_block_list[4],
  81731         soc_portreg,
  81732         1,
  81733         0,
  81734         0x1a800,
  81735         0,
  81736         0,
  81737         2,
  81738         soc_XQCOSARBSEL_BCM53400_A0r_fields,
  81739         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  81740         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81741         -1,
  81742         91,
  81743     },
  81744 #endif /* chips */
  81745 
  81746 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  81747     { /* SOC_REG_INT_XQCOSARBSEL_BCM53570_A0r */
  81748         soc_block_list[4],
  81749         soc_portreg,
  81750         1,
  81751         0,
  81752         0x1c000,
  81753         0,
  81754         0,
  81755         2,
  81756         soc_XQCOSARBSEL_BCM53400_A0r_fields,
  81757         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  81758         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81759         -1,
  81760         102,
  81761     },
  81762 #endif /* chips */
  81763 
  81764 #if defined(BCM_56142_A0)
  81765     { /* SOC_REG_INT_XQCOSARBSEL_BCM56142_A0r */
  81766         soc_block_list[4],
  81767         soc_portreg,
  81768         1,
  81769         0,
  81770         0x132,
  81771         0,
  81772         0,
  81773         2,
  81774         soc_XQCOSARBSEL_BCM56224_A0r_fields,
  81775         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  81776         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81777         -1,
  81778         -1,
  81779     },
  81780 #endif /* chips */
  81781 
  81782 #if defined(BCM_56150_A0)
  81783     { /* SOC_REG_INT_XQCOSARBSEL_BCM56150_A0r */
  81784         soc_block_list[4],
  81785         soc_portreg,
  81786         1,
  81787         0,
  81788         0x13200,
  81789         0,
  81790         0,
  81791         2,
  81792         soc_XQCOSARBSEL_BCM56150_A0r_fields,
  81793         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  81794         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81795         -1,
  81796         79,
  81797     },
  81798 #endif /* chips */
  81799 
  81800 #if defined(BCM_56160_A0)
  81801     { /* SOC_REG_INT_XQCOSARBSEL_BCM56160_A0r */
  81802         soc_block_list[4],
  81803         soc_portreg,
  81804         1,
  81805         0,
  81806         0x13200,
  81807         0,
  81808         0,
  81809         2,
  81810         soc_XQCOSARBSEL_BCM53400_A0r_fields,
  81811         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  81812         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81813         -1,
  81814         91,
  81815     },
  81816 #endif /* chips */
  81817 
  81818 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  81819     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  81820     { /* SOC_REG_INT_XQCOSARBSEL_BCM56224_A0r */
  81821         soc_block_list[4],
  81822         soc_portreg,
  81823         1,
  81824         0,
  81825         0x61,
  81826         0,
  81827         0,
  81828         2,
  81829         soc_XQCOSARBSEL_BCM56224_A0r_fields,
  81830         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  81831         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81832         -1,
  81833         -1,
  81834     },
  81835 #endif /* chips */
  81836 
  81837 #if defined(BCM_56514_A0)
  81838     { /* SOC_REG_INT_XQCOSARBSEL_BCM56514_A0r */
  81839         soc_block_list[4],
  81840         soc_portreg,
  81841         1,
  81842         0,
  81843         0x45,
  81844         0,
  81845         0,
  81846         2,
  81847         soc_XQCOSARBSEL_BCM56514_A0r_fields,
  81848         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
  81849         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  81850         -1,
  81851         -1,
  81852     },
  81853 #endif /* chips */
  81854 
  81855 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  81856     { /* SOC_REG_INT_XQCOSARBSEL_QGROUPr */
  81857         soc_block_list[4],
  81858         soc_portreg,
  81859         1,
  81860         0,
  81861         0x1e000,
  81862         0,
  81863         0,
  81864         2,
  81865         soc_XQCOSARBSEL_BCM53400_A0r_fields,
  81866         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  81867         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81868         -1,
  81869         99,
  81870     },
  81871 #endif /* chips */
  81872 
  81873 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  81874     { /* SOC_REG_INT_XQCOSARBSEL_QLAYERr */
  81875         soc_block_list[4],
  81876         soc_portreg,
  81877         8,
  81878         0,
  81879         0x1d800,
  81880         SOC_REG_FLAG_ARRAY,
  81881         0,
  81882         2,
  81883         soc_XQCOSARBSEL_BCM53400_A0r_fields,
  81884         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  81885         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  81886         -1,
  81887         99,
  81888     },
  81889 #endif /* chips */
  81890 
  81891 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  81892     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  81893     { /* SOC_REG_INT_XQCOSPTRr */
  81894         soc_block_list[4],
  81895         soc_portreg,
  81896         1,
  81897         0,
  81898         0x70,
  81899         0,
  81900         0,
  81901         3,
  81902         soc_XQCOSPTRr_fields,
  81903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81904         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  81905         -1,
  81906         -1,
  81907     },
  81908 #endif /* chips */
  81909 
  81910 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  81911     { /* SOC_REG_INT_XQCOSPTRCTLr */
  81912         soc_block_list[4],
  81913         soc_portreg,
  81914         1,
  81915         0,
  81916         0x26800,
  81917         0,
  81918         0,
  81919         1,
  81920         soc_XQCOSPTRCTLr_fields,
  81921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81922         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  81923         -1,
  81924         101,
  81925     },
  81926 #endif /* chips */
  81927 
  81928 #if defined(BCM_53400_A0)
  81929     { /* SOC_REG_INT_XQCOSPTR_BCM53400_A0r */
  81930         soc_block_list[4],
  81931         soc_portreg,
  81932         1,
  81933         0,
  81934         0x15900,
  81935         0,
  81936         0,
  81937         3,
  81938         soc_XQCOSPTR_BCM53400_A0r_fields,
  81939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81940         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  81941         -1,
  81942         79,
  81943     },
  81944 #endif /* chips */
  81945 
  81946 #if defined(BCM_53540_A0)
  81947     { /* SOC_REG_INT_XQCOSPTR_BCM53540_A0r */
  81948         soc_block_list[4],
  81949         soc_portreg,
  81950         1,
  81951         0,
  81952         0x1e000,
  81953         0,
  81954         0,
  81955         3,
  81956         soc_XQCOSPTR_BCM53540_A0r_fields,
  81957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81958         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  81959         -1,
  81960         91,
  81961     },
  81962 #endif /* chips */
  81963 
  81964 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  81965     { /* SOC_REG_INT_XQCOSPTR_BCM53570_A0r */
  81966         soc_block_list[4],
  81967         soc_portreg,
  81968         1,
  81969         0,
  81970         0x26000,
  81971         SOC_REG_FLAG_RO,
  81972         0,
  81973         2,
  81974         soc_XQCOSPTR_BCM53570_A0r_fields,
  81975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81976         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  81977         -1,
  81978         101,
  81979     },
  81980 #endif /* chips */
  81981 
  81982 #if defined(BCM_56142_A0)
  81983     { /* SOC_REG_INT_XQCOSPTR_BCM56142_A0r */
  81984         soc_block_list[4],
  81985         soc_portreg,
  81986         1,
  81987         0,
  81988         0x159,
  81989         0,
  81990         0,
  81991         3,
  81992         soc_XQCOSPTRr_fields,
  81993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81994         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  81995         -1,
  81996         -1,
  81997     },
  81998 #endif /* chips */
  81999 
  82000 #if defined(BCM_56150_A0)
  82001     { /* SOC_REG_INT_XQCOSPTR_BCM56150_A0r */
  82002         soc_block_list[4],
  82003         soc_portreg,
  82004         1,
  82005         0,
  82006         0x15900,
  82007         0,
  82008         0,
  82009         3,
  82010         soc_XQCOSPTR_BCM56150_A0r_fields,
  82011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82012         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  82013         -1,
  82014         79,
  82015     },
  82016 #endif /* chips */
  82017 
  82018 #if defined(BCM_56160_A0)
  82019     { /* SOC_REG_INT_XQCOSPTR_BCM56160_A0r */
  82020         soc_block_list[4],
  82021         soc_portreg,
  82022         1,
  82023         0,
  82024         0x15900,
  82025         0,
  82026         0,
  82027         3,
  82028         soc_XQCOSPTR_BCM56160_A0r_fields,
  82029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82030         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  82031         -1,
  82032         91,
  82033     },
  82034 #endif /* chips */
  82035 
  82036 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  82037     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  82038     { /* SOC_REG_INT_XQEMPTYr */
  82039         soc_block_list[4],
  82040         soc_portreg,
  82041         1,
  82042         0,
  82043         0x42,
  82044         SOC_REG_FLAG_RO,
  82045         0,
  82046         8,
  82047         soc_XQEMPTYr_fields,
  82048         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  82049         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  82050         -1,
  82051         -1,
  82052     },
  82053 #endif /* chips */
  82054 
  82055 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  82056     { /* SOC_REG_INT_XQEMPTY_BCM53314_A0r */
  82057         soc_block_list[4],
  82058         soc_portreg,
  82059         1,
  82060         0,
  82061         0x5e,
  82062         SOC_REG_FLAG_RO,
  82063         0,
  82064         4,
  82065         soc_XQEMPTY_BCM53314_A0r_fields,
  82066         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  82067         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  82068         -1,
  82069         -1,
  82070     },
  82071 #endif /* chips */
  82072 
  82073 #if defined(BCM_53400_A0)
  82074     { /* SOC_REG_INT_XQEMPTY_BCM53400_A0r */
  82075         soc_block_list[4],
  82076         soc_portreg,
  82077         1,
  82078         0,
  82079         0x12f00,
  82080         SOC_REG_FLAG_RO,
  82081         0,
  82082         8,
  82083         soc_XQEMPTY_BCM53400_A0r_fields,
  82084         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  82085         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  82086         -1,
  82087         79,
  82088     },
  82089 #endif /* chips */
  82090 
  82091 #if defined(BCM_53540_A0)
  82092     { /* SOC_REG_INT_XQEMPTY_BCM53540_A0r */
  82093         soc_block_list[4],
  82094         soc_portreg,
  82095         1,
  82096         0,
  82097         0x19000,
  82098         SOC_REG_FLAG_RO,
  82099         0,
  82100         8,
  82101         soc_XQEMPTY_BCM53400_A0r_fields,
  82102         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  82103         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  82104         -1,
  82105         91,
  82106     },
  82107 #endif /* chips */
  82108 
  82109 #if defined(BCM_56142_A0)
  82110     { /* SOC_REG_INT_XQEMPTY_BCM56142_A0r */
  82111         soc_block_list[4],
  82112         soc_portreg,
  82113         1,
  82114         0,
  82115         0x12f,
  82116         SOC_REG_FLAG_RO,
  82117         0,
  82118         8,
  82119         soc_XQEMPTYr_fields,
  82120         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  82121         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  82122         -1,
  82123         -1,
  82124     },
  82125 #endif /* chips */
  82126 
  82127 #if defined(BCM_56150_A0)
  82128     { /* SOC_REG_INT_XQEMPTY_BCM56150_A0r */
  82129         soc_block_list[4],
  82130         soc_portreg,
  82131         1,
  82132         0,
  82133         0x12f00,
  82134         SOC_REG_FLAG_RO,
  82135         0,
  82136         8,
  82137         soc_XQEMPTY_BCM56150_A0r_fields,
  82138         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  82139         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  82140         -1,
  82141         79,
  82142     },
  82143 #endif /* chips */
  82144 
  82145 #if defined(BCM_56160_A0)
  82146     { /* SOC_REG_INT_XQEMPTY_BCM56160_A0r */
  82147         soc_block_list[4],
  82148         soc_portreg,
  82149         1,
  82150         0,
  82151         0x12f00,
  82152         SOC_REG_FLAG_RO,
  82153         0,
  82154         8,
  82155         soc_XQEMPTY_BCM53400_A0r_fields,
  82156         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  82157         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  82158         -1,
  82159         91,
  82160     },
  82161 #endif /* chips */
  82162 
  82163 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  82164     { /* SOC_REG_INT_XQEMPTY_BCM56224_A0r */
  82165         soc_block_list[4],
  82166         soc_portreg,
  82167         1,
  82168         0,
  82169         0x5e,
  82170         SOC_REG_FLAG_RO,
  82171         0,
  82172         8,
  82173         soc_XQEMPTYr_fields,
  82174         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  82175         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  82176         -1,
  82177         -1,
  82178     },
  82179 #endif /* chips */
  82180 
  82181 #if defined(BCM_56160_A0)
  82182     { /* SOC_REG_INT_XQEMPTY_DEBUGr */
  82183         soc_block_list[4],
  82184         soc_portreg,
  82185         1,
  82186         0,
  82187         0x17fc00,
  82188         SOC_REG_FLAG_RO,
  82189         0,
  82190         1,
  82191         soc_XQEMPTY_DEBUGr_fields,
  82192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82193         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  82194         -1,
  82195         91,
  82196     },
  82197 #endif /* chips */
  82198 
  82199 #if defined(BCM_53540_A0)
  82200     { /* SOC_REG_INT_XQEMPTY_DEBUG_BCM53540_A0r */
  82201         soc_block_list[4],
  82202         soc_portreg,
  82203         1,
  82204         0,
  82205         0x96000,
  82206         SOC_REG_FLAG_RO,
  82207         0,
  82208         1,
  82209         soc_XQEMPTY_DEBUGr_fields,
  82210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82211         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  82212         -1,
  82213         91,
  82214     },
  82215 #endif /* chips */
  82216 
  82217 #if defined(BCM_56160_A0)
  82218     { /* SOC_REG_INT_XQEMPTY_DEBUG_ENr */
  82219         soc_block_list[4],
  82220         soc_genreg,
  82221         1,
  82222         0,
  82223         0x217fd00,
  82224         0,
  82225         0,
  82226         1,
  82227         soc_INTFO_FCN_ENr_fields,
  82228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82229         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  82230         -1,
  82231         -1,
  82232     },
  82233 #endif /* chips */
  82234 
  82235 #if defined(BCM_53540_A0)
  82236     { /* SOC_REG_INT_XQEMPTY_DEBUG_EN_BCM53540_A0r */
  82237         soc_block_list[4],
  82238         soc_genreg,
  82239         1,
  82240         0,
  82241         0x2096800,
  82242         0,
  82243         0,
  82244         1,
  82245         soc_INTFO_FCN_ENr_fields,
  82246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82247         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  82248         -1,
  82249         -1,
  82250     },
  82251 #endif /* chips */
  82252 
  82253 #if defined(BCM_53570_A0)
  82254     { /* SOC_REG_INT_XQEMPTY_DEBUG_EN_BCM53570_A0r */
  82255         soc_block_list[4],
  82256         soc_genreg,
  82257         1,
  82258         0,
  82259         0x210b400,
  82260         0,
  82261         0,
  82262         1,
  82263         soc_INTFO_FCN_ENr_fields,
  82264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82265         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  82266         -1,
  82267         -1,
  82268     },
  82269 #endif /* chips */
  82270 
  82271 #if defined(BCM_53570_B0)
  82272     { /* SOC_REG_INT_XQEMPTY_DEBUG_EN_BCM53570_B0r */
  82273         soc_block_list[4],
  82274         soc_genreg,
  82275         1,
  82276         0,
  82277         0x210b700,
  82278         0,
  82279         0,
  82280         1,
  82281         soc_INTFO_FCN_ENr_fields,
  82282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82283         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  82284         -1,
  82285         -1,
  82286     },
  82287 #endif /* chips */
  82288 
  82289 #if defined(BCM_53570_A0)
  82290     { /* SOC_REG_INT_XQEMPTY_DEBUG_QLAYER_QBMP0r */
  82291         soc_block_list[4],
  82292         soc_portreg,
  82293         1,
  82294         0,
  82295         0x109400,
  82296         SOC_REG_FLAG_RO,
  82297         0,
  82298         1,
  82299         soc_XQEMPTY_DEBUG_QLAYER_QBMP0r_fields,
  82300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82301         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82302         -1,
  82303         101,
  82304     },
  82305 #endif /* chips */
  82306 
  82307 #if defined(BCM_53570_A0)
  82308     { /* SOC_REG_INT_XQEMPTY_DEBUG_QLAYER_QBMP1r */
  82309         soc_block_list[4],
  82310         soc_portreg,
  82311         1,
  82312         0,
  82313         0x109c00,
  82314         SOC_REG_FLAG_RO,
  82315         0,
  82316         1,
  82317         soc_XQEMPTY_DEBUG_QLAYER_QBMP0r_fields,
  82318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82319         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82320         -1,
  82321         101,
  82322     },
  82323 #endif /* chips */
  82324 
  82325 #if defined(BCM_53570_B0)
  82326     { /* SOC_REG_INT_XQEMPTY_DEBUG_QLAYER_QBMP0_BCM53570_B0r */
  82327         soc_block_list[4],
  82328         soc_portreg,
  82329         1,
  82330         0,
  82331         0x109700,
  82332         SOC_REG_FLAG_RO,
  82333         0,
  82334         1,
  82335         soc_XQEMPTY_DEBUG_QLAYER_QBMP0r_fields,
  82336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82337         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82338         -1,
  82339         101,
  82340     },
  82341 #endif /* chips */
  82342 
  82343 #if defined(BCM_53570_B0)
  82344     { /* SOC_REG_INT_XQEMPTY_DEBUG_QLAYER_QBMP1_BCM53570_B0r */
  82345         soc_block_list[4],
  82346         soc_portreg,
  82347         1,
  82348         0,
  82349         0x109f00,
  82350         SOC_REG_FLAG_RO,
  82351         0,
  82352         1,
  82353         soc_XQEMPTY_DEBUG_QLAYER_QBMP0r_fields,
  82354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82355         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82356         -1,
  82357         101,
  82358     },
  82359 #endif /* chips */
  82360 
  82361 #if defined(BCM_53570_A0)
  82362     { /* SOC_REG_INT_XQEMPTY_QLAYER_QBMP0r */
  82363         soc_block_list[4],
  82364         soc_portreg,
  82365         1,
  82366         0,
  82367         0x10a400,
  82368         SOC_REG_FLAG_RO,
  82369         0,
  82370         1,
  82371         soc_XQEMPTY_QLAYER_QBMP0r_fields,
  82372         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  82373         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82374         -1,
  82375         101,
  82376     },
  82377 #endif /* chips */
  82378 
  82379 #if defined(BCM_53570_A0)
  82380     { /* SOC_REG_INT_XQEMPTY_QLAYER_QBMP1r */
  82381         soc_block_list[4],
  82382         soc_portreg,
  82383         1,
  82384         0,
  82385         0x10ac00,
  82386         SOC_REG_FLAG_RO,
  82387         0,
  82388         1,
  82389         soc_XQEMPTY_QLAYER_QBMP0r_fields,
  82390         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  82391         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82392         -1,
  82393         101,
  82394     },
  82395 #endif /* chips */
  82396 
  82397 #if defined(BCM_53570_B0)
  82398     { /* SOC_REG_INT_XQEMPTY_QLAYER_QBMP0_BCM53570_B0r */
  82399         soc_block_list[4],
  82400         soc_portreg,
  82401         1,
  82402         0,
  82403         0x10a700,
  82404         SOC_REG_FLAG_RO,
  82405         0,
  82406         1,
  82407         soc_XQEMPTY_QLAYER_QBMP0r_fields,
  82408         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  82409         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82410         -1,
  82411         101,
  82412     },
  82413 #endif /* chips */
  82414 
  82415 #if defined(BCM_53570_B0)
  82416     { /* SOC_REG_INT_XQEMPTY_QLAYER_QBMP1_BCM53570_B0r */
  82417         soc_block_list[4],
  82418         soc_portreg,
  82419         1,
  82420         0,
  82421         0x10af00,
  82422         SOC_REG_FLAG_RO,
  82423         0,
  82424         1,
  82425         soc_XQEMPTY_QLAYER_QBMP0r_fields,
  82426         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  82427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82428         -1,
  82429         101,
  82430     },
  82431 #endif /* chips */
  82432 
  82433 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  82434     { /* SOC_REG_INT_XQFLLMEMDEBUGr */
  82435         soc_block_list[4],
  82436         soc_genreg,
  82437         1,
  82438         0,
  82439         0x2030900,
  82440         0,
  82441         0,
  82442         1,
  82443         soc_DSCP_CONTROLr_fields,
  82444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82445         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  82446         -1,
  82447         -1,
  82448     },
  82449 #endif /* chips */
  82450 
  82451 #if defined(BCM_53540_A0)
  82452     { /* SOC_REG_INT_XQFLLMEMDEBUG_BCM53540_A0r */
  82453         soc_block_list[4],
  82454         soc_genreg,
  82455         1,
  82456         0,
  82457         0x2037800,
  82458         0,
  82459         0,
  82460         1,
  82461         soc_DSCP_CONTROLr_fields,
  82462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82463         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  82464         -1,
  82465         -1,
  82466     },
  82467 #endif /* chips */
  82468 
  82469 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  82470     { /* SOC_REG_INT_XQFLLMEMDEBUG_BCM53570_A0r */
  82471         soc_block_list[4],
  82472         soc_genreg,
  82473         1,
  82474         0,
  82475         0x2059e00,
  82476         0,
  82477         0,
  82478         1,
  82479         soc_DSCP_CONTROLr_fields,
  82480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82481         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  82482         -1,
  82483         -1,
  82484     },
  82485 #endif /* chips */
  82486 
  82487 #if defined(BCM_56142_A0)
  82488     { /* SOC_REG_INT_XQFLLPARITYERRORPTRr */
  82489         soc_block_list[4],
  82490         soc_portreg,
  82491         1,
  82492         0,
  82493         0x23d,
  82494         SOC_REG_FLAG_RO,
  82495         0,
  82496         2,
  82497         soc_XQFLLPARITYERRORPTRr_fields,
  82498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82499         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  82500         -1,
  82501         -1,
  82502     },
  82503 #endif /* chips */
  82504 
  82505 #if defined(BCM_53400_A0)
  82506     { /* SOC_REG_INT_XQFLLPARITYERRORPTR_BCM53400_A0r */
  82507         soc_block_list[4],
  82508         soc_portreg,
  82509         1,
  82510         0,
  82511         0x23d00,
  82512         SOC_REG_FLAG_RO,
  82513         0,
  82514         3,
  82515         soc_XQFLLPARITYERRORPTR_BCM53400_A0r_fields,
  82516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82517         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  82518         -1,
  82519         79,
  82520     },
  82521 #endif /* chips */
  82522 
  82523 #if defined(BCM_53540_A0)
  82524     { /* SOC_REG_INT_XQFLLPARITYERRORPTR_BCM53540_A0r */
  82525         soc_block_list[4],
  82526         soc_portreg,
  82527         1,
  82528         0,
  82529         0x22000,
  82530         SOC_REG_FLAG_RO,
  82531         0,
  82532         3,
  82533         soc_IPMC_GROUP_ERR_PTRr_fields,
  82534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82535         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  82536         -1,
  82537         91,
  82538     },
  82539 #endif /* chips */
  82540 
  82541 #if defined(BCM_53570_A0)
  82542     { /* SOC_REG_INT_XQFLLPARITYERRORPTR_BCM53570_A0r */
  82543         soc_block_list[4],
  82544         soc_portreg,
  82545         1,
  82546         0,
  82547         0x30800,
  82548         SOC_REG_FLAG_RO,
  82549         0,
  82550         4,
  82551         soc_XQFLLPARITYERRORPTR_BCM53570_A0r_fields,
  82552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82553         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  82554         -1,
  82555         101,
  82556     },
  82557 #endif /* chips */
  82558 
  82559 #if defined(BCM_53570_B0)
  82560     { /* SOC_REG_INT_XQFLLPARITYERRORPTR_BCM53570_B0r */
  82561         soc_block_list[4],
  82562         soc_portreg,
  82563         1,
  82564         0,
  82565         0x30800,
  82566         SOC_REG_FLAG_RO,
  82567         0,
  82568         5,
  82569         soc_XQFLLPARITYERRORPTR_BCM53570_B0r_fields,
  82570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82571         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  82572         -1,
  82573         101,
  82574     },
  82575 #endif /* chips */
  82576 
  82577 #if defined(BCM_56150_A0)
  82578     { /* SOC_REG_INT_XQFLLPARITYERRORPTR_BCM56150_A0r */
  82579         soc_block_list[4],
  82580         soc_portreg,
  82581         1,
  82582         0,
  82583         0x23d00,
  82584         SOC_REG_FLAG_RO,
  82585         0,
  82586         2,
  82587         soc_XQFLLPARITYERRORPTR_BCM56150_A0r_fields,
  82588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82589         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  82590         -1,
  82591         79,
  82592     },
  82593 #endif /* chips */
  82594 
  82595 #if defined(BCM_56160_A0)
  82596     { /* SOC_REG_INT_XQFLLPARITYERRORPTR_BCM56160_A0r */
  82597         soc_block_list[4],
  82598         soc_portreg,
  82599         1,
  82600         0,
  82601         0x23d00,
  82602         SOC_REG_FLAG_RO,
  82603         0,
  82604         3,
  82605         soc_XQFLLPARITYERRORPTR_BCM56160_A0r_fields,
  82606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82607         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  82608         -1,
  82609         91,
  82610     },
  82611 #endif /* chips */
  82612 
  82613 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  82614     { /* SOC_REG_INT_XQFLLPTRr */
  82615         soc_block_list[4],
  82616         soc_portreg,
  82617         1,
  82618         0,
  82619         0x27000,
  82620         SOC_REG_FLAG_RO,
  82621         0,
  82622         1,
  82623         soc_XQFLLPTRr_fields,
  82624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82625         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  82626         -1,
  82627         101,
  82628     },
  82629 #endif /* chips */
  82630 
  82631 #if defined(BCM_53400_A0)
  82632     { /* SOC_REG_INT_XQFLL_ERR_CLRr */
  82633         soc_block_list[4],
  82634         soc_genreg,
  82635         1,
  82636         0,
  82637         0x2141600,
  82638         SOC_REG_FLAG_WO,
  82639         0,
  82640         1,
  82641         soc_IPMC_GROUP_ERR_CLRr_fields,
  82642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82643         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  82644         -1,
  82645         -1,
  82646     },
  82647 #endif /* chips */
  82648 
  82649 #if defined(BCM_53570_A0)
  82650     { /* SOC_REG_INT_XQFLL_ERR_CLR_0r */
  82651         soc_block_list[4],
  82652         soc_genreg,
  82653         1,
  82654         0,
  82655         0x20d9e00,
  82656         SOC_REG_FLAG_WO,
  82657         0,
  82658         1,
  82659         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  82660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82661         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82662         -1,
  82663         -1,
  82664     },
  82665 #endif /* chips */
  82666 
  82667 #if defined(BCM_53570_A0)
  82668     { /* SOC_REG_INT_XQFLL_ERR_CLR_1r */
  82669         soc_block_list[4],
  82670         soc_genreg,
  82671         1,
  82672         0,
  82673         0x20d9f00,
  82674         SOC_REG_FLAG_WO,
  82675         0,
  82676         1,
  82677         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  82678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82680         -1,
  82681         -1,
  82682     },
  82683 #endif /* chips */
  82684 
  82685 #if defined(BCM_53570_A0)
  82686     { /* SOC_REG_INT_XQFLL_ERR_CLR_2r */
  82687         soc_block_list[4],
  82688         soc_genreg,
  82689         1,
  82690         0,
  82691         0x20da000,
  82692         SOC_REG_FLAG_WO,
  82693         0,
  82694         1,
  82695         soc_IPMC_GROUP_ERR_CLR_2r_fields,
  82696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82697         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  82698         -1,
  82699         -1,
  82700     },
  82701 #endif /* chips */
  82702 
  82703 #if defined(BCM_53570_B0)
  82704     { /* SOC_REG_INT_XQFLL_ERR_CLR_0_BCM53570_B0r */
  82705         soc_block_list[4],
  82706         soc_genreg,
  82707         1,
  82708         0,
  82709         0x20da100,
  82710         SOC_REG_FLAG_WO,
  82711         0,
  82712         1,
  82713         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  82714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82715         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82716         -1,
  82717         -1,
  82718     },
  82719 #endif /* chips */
  82720 
  82721 #if defined(BCM_53570_B0)
  82722     { /* SOC_REG_INT_XQFLL_ERR_CLR_1_BCM53570_B0r */
  82723         soc_block_list[4],
  82724         soc_genreg,
  82725         1,
  82726         0,
  82727         0x20da200,
  82728         SOC_REG_FLAG_WO,
  82729         0,
  82730         1,
  82731         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  82732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82733         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82734         -1,
  82735         -1,
  82736     },
  82737 #endif /* chips */
  82738 
  82739 #if defined(BCM_53570_B0)
  82740     { /* SOC_REG_INT_XQFLL_ERR_CLR_2_BCM53570_B0r */
  82741         soc_block_list[4],
  82742         soc_genreg,
  82743         1,
  82744         0,
  82745         0x20da300,
  82746         SOC_REG_FLAG_WO,
  82747         0,
  82748         1,
  82749         soc_IPMC_GROUP_ERR_CLR_2r_fields,
  82750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82751         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  82752         -1,
  82753         -1,
  82754     },
  82755 #endif /* chips */
  82756 
  82757 #if defined(BCM_53540_A0)
  82758     { /* SOC_REG_INT_XQFLL_ERR_CLR_BCM53540_A0r */
  82759         soc_block_list[4],
  82760         soc_genreg,
  82761         1,
  82762         0,
  82763         0x2073000,
  82764         SOC_REG_FLAG_WO,
  82765         0,
  82766         1,
  82767         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  82768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82769         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82770         -1,
  82771         -1,
  82772     },
  82773 #endif /* chips */
  82774 
  82775 #if defined(BCM_56160_A0)
  82776     { /* SOC_REG_INT_XQFLL_ERR_CLR_BCM56160_A0r */
  82777         soc_block_list[4],
  82778         soc_genreg,
  82779         1,
  82780         0,
  82781         0x2141600,
  82782         SOC_REG_FLAG_WO,
  82783         0,
  82784         1,
  82785         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  82786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82787         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82788         -1,
  82789         -1,
  82790     },
  82791 #endif /* chips */
  82792 
  82793 #if defined(BCM_53400_A0)
  82794     { /* SOC_REG_INT_XQFLL_ERR_VLDr */
  82795         soc_block_list[4],
  82796         soc_genreg,
  82797         1,
  82798         0,
  82799         0x2141400,
  82800         SOC_REG_FLAG_RO,
  82801         0,
  82802         1,
  82803         soc_IPMC_GROUP_ERR_VLDr_fields,
  82804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82805         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  82806         -1,
  82807         -1,
  82808     },
  82809 #endif /* chips */
  82810 
  82811 #if defined(BCM_53570_A0)
  82812     { /* SOC_REG_INT_XQFLL_ERR_VLD_0r */
  82813         soc_block_list[4],
  82814         soc_genreg,
  82815         1,
  82816         0,
  82817         0x20d8a00,
  82818         SOC_REG_FLAG_RO,
  82819         0,
  82820         1,
  82821         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  82822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82823         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82824         -1,
  82825         -1,
  82826     },
  82827 #endif /* chips */
  82828 
  82829 #if defined(BCM_53570_A0)
  82830     { /* SOC_REG_INT_XQFLL_ERR_VLD_1r */
  82831         soc_block_list[4],
  82832         soc_genreg,
  82833         1,
  82834         0,
  82835         0x20d8b00,
  82836         SOC_REG_FLAG_RO,
  82837         0,
  82838         1,
  82839         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  82840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82842         -1,
  82843         -1,
  82844     },
  82845 #endif /* chips */
  82846 
  82847 #if defined(BCM_53570_A0)
  82848     { /* SOC_REG_INT_XQFLL_ERR_VLD_2r */
  82849         soc_block_list[4],
  82850         soc_genreg,
  82851         1,
  82852         0,
  82853         0x20d8c00,
  82854         SOC_REG_FLAG_RO,
  82855         0,
  82856         1,
  82857         soc_IPMC_GROUP_ERR_VLD_2r_fields,
  82858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82859         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  82860         -1,
  82861         -1,
  82862     },
  82863 #endif /* chips */
  82864 
  82865 #if defined(BCM_53570_B0)
  82866     { /* SOC_REG_INT_XQFLL_ERR_VLD_0_BCM53570_B0r */
  82867         soc_block_list[4],
  82868         soc_genreg,
  82869         1,
  82870         0,
  82871         0x20d8d00,
  82872         SOC_REG_FLAG_RO,
  82873         0,
  82874         1,
  82875         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  82876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82878         -1,
  82879         -1,
  82880     },
  82881 #endif /* chips */
  82882 
  82883 #if defined(BCM_53570_B0)
  82884     { /* SOC_REG_INT_XQFLL_ERR_VLD_1_BCM53570_B0r */
  82885         soc_block_list[4],
  82886         soc_genreg,
  82887         1,
  82888         0,
  82889         0x20d8e00,
  82890         SOC_REG_FLAG_RO,
  82891         0,
  82892         1,
  82893         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  82894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82895         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82896         -1,
  82897         -1,
  82898     },
  82899 #endif /* chips */
  82900 
  82901 #if defined(BCM_53570_B0)
  82902     { /* SOC_REG_INT_XQFLL_ERR_VLD_2_BCM53570_B0r */
  82903         soc_block_list[4],
  82904         soc_genreg,
  82905         1,
  82906         0,
  82907         0x20d8f00,
  82908         SOC_REG_FLAG_RO,
  82909         0,
  82910         1,
  82911         soc_IPMC_GROUP_ERR_VLD_2r_fields,
  82912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82913         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  82914         -1,
  82915         -1,
  82916     },
  82917 #endif /* chips */
  82918 
  82919 #if defined(BCM_53540_A0)
  82920     { /* SOC_REG_INT_XQFLL_ERR_VLD_BCM53540_A0r */
  82921         soc_block_list[4],
  82922         soc_genreg,
  82923         1,
  82924         0,
  82925         0x2072000,
  82926         SOC_REG_FLAG_RO,
  82927         0,
  82928         1,
  82929         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  82930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82931         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82932         -1,
  82933         -1,
  82934     },
  82935 #endif /* chips */
  82936 
  82937 #if defined(BCM_56160_A0)
  82938     { /* SOC_REG_INT_XQFLL_ERR_VLD_BCM56160_A0r */
  82939         soc_block_list[4],
  82940         soc_genreg,
  82941         1,
  82942         0,
  82943         0x2141400,
  82944         SOC_REG_FLAG_RO,
  82945         0,
  82946         1,
  82947         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  82948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82949         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82950         -1,
  82951         -1,
  82952     },
  82953 #endif /* chips */
  82954 
  82955 #if defined(BCM_53400_A0)
  82956     { /* SOC_REG_INT_XQFLL_MULTI_ERRr */
  82957         soc_block_list[4],
  82958         soc_genreg,
  82959         1,
  82960         0,
  82961         0x2141500,
  82962         SOC_REG_FLAG_RO,
  82963         0,
  82964         1,
  82965         soc_IPMC_GROUP_MULTI_ERRr_fields,
  82966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82967         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  82968         -1,
  82969         -1,
  82970     },
  82971 #endif /* chips */
  82972 
  82973 #if defined(BCM_53570_A0)
  82974     { /* SOC_REG_INT_XQFLL_MULTI_ERR_0r */
  82975         soc_block_list[4],
  82976         soc_genreg,
  82977         1,
  82978         0,
  82979         0x20d9400,
  82980         SOC_REG_FLAG_RO,
  82981         0,
  82982         1,
  82983         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  82984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82985         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82986         -1,
  82987         -1,
  82988     },
  82989 #endif /* chips */
  82990 
  82991 #if defined(BCM_53570_A0)
  82992     { /* SOC_REG_INT_XQFLL_MULTI_ERR_1r */
  82993         soc_block_list[4],
  82994         soc_genreg,
  82995         1,
  82996         0,
  82997         0x20d9500,
  82998         SOC_REG_FLAG_RO,
  82999         0,
  83000         1,
  83001         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  83002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83003         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  83004         -1,
  83005         -1,
  83006     },
  83007 #endif /* chips */
  83008 
  83009 #if defined(BCM_53570_A0)
  83010     { /* SOC_REG_INT_XQFLL_MULTI_ERR_2r */
  83011         soc_block_list[4],
  83012         soc_genreg,
  83013         1,
  83014         0,
  83015         0x20d9600,
  83016         SOC_REG_FLAG_RO,
  83017         0,
  83018         1,
  83019         soc_IPMC_GROUP_MULTI_ERR_2r_fields,
  83020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83021         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  83022         -1,
  83023         -1,
  83024     },
  83025 #endif /* chips */
  83026 
  83027 #if defined(BCM_53570_B0)
  83028     { /* SOC_REG_INT_XQFLL_MULTI_ERR_0_BCM53570_B0r */
  83029         soc_block_list[4],
  83030         soc_genreg,
  83031         1,
  83032         0,
  83033         0x20d9700,
  83034         SOC_REG_FLAG_RO,
  83035         0,
  83036         1,
  83037         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  83038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83039         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  83040         -1,
  83041         -1,
  83042     },
  83043 #endif /* chips */
  83044 
  83045 #if defined(BCM_53570_B0)
  83046     { /* SOC_REG_INT_XQFLL_MULTI_ERR_1_BCM53570_B0r */
  83047         soc_block_list[4],
  83048         soc_genreg,
  83049         1,
  83050         0,
  83051         0x20d9800,
  83052         SOC_REG_FLAG_RO,
  83053         0,
  83054         1,
  83055         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  83056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83057         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  83058         -1,
  83059         -1,
  83060     },
  83061 #endif /* chips */
  83062 
  83063 #if defined(BCM_53570_B0)
  83064     { /* SOC_REG_INT_XQFLL_MULTI_ERR_2_BCM53570_B0r */
  83065         soc_block_list[4],
  83066         soc_genreg,
  83067         1,
  83068         0,
  83069         0x20d9900,
  83070         SOC_REG_FLAG_RO,
  83071         0,
  83072         1,
  83073         soc_IPMC_GROUP_MULTI_ERR_2r_fields,
  83074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83075         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  83076         -1,
  83077         -1,
  83078     },
  83079 #endif /* chips */
  83080 
  83081 #if defined(BCM_53540_A0)
  83082     { /* SOC_REG_INT_XQFLL_MULTI_ERR_BCM53540_A0r */
  83083         soc_block_list[4],
  83084         soc_genreg,
  83085         1,
  83086         0,
  83087         0x2072800,
  83088         SOC_REG_FLAG_RO,
  83089         0,
  83090         1,
  83091         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  83092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83093         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  83094         -1,
  83095         -1,
  83096     },
  83097 #endif /* chips */
  83098 
  83099 #if defined(BCM_56160_A0)
  83100     { /* SOC_REG_INT_XQFLL_MULTI_ERR_BCM56160_A0r */
  83101         soc_block_list[4],
  83102         soc_genreg,
  83103         1,
  83104         0,
  83105         0x2141500,
  83106         SOC_REG_FLAG_RO,
  83107         0,
  83108         1,
  83109         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  83110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83111         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  83112         -1,
  83113         -1,
  83114     },
  83115 #endif /* chips */
  83116 
  83117 #if defined(BCM_56504_A0) || defined(BCM_56504_B0)
  83118     { /* SOC_REG_INT_XQMEMDEBUGr */
  83119         soc_block_list[4],
  83120         soc_portreg,
  83121         1,
  83122         0,
  83123         0x73,
  83124         0,
  83125         0,
  83126         2,
  83127         soc_AGINGCTRMEMDEBUGr_fields,
  83128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83129         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  83130         -1,
  83131         -1,
  83132     },
  83133 #endif /* chips */
  83134 
  83135 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  83136     { /* SOC_REG_INT_XQMEMDEBUG_BCM53314_A0r */
  83137         soc_block_list[4],
  83138         soc_portreg,
  83139         1,
  83140         0,
  83141         0x71,
  83142         0,
  83143         0,
  83144         2,
  83145         soc_WREDMEMDEBUG_CFG_CELLr_fields,
  83146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83147         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83148         -1,
  83149         -1,
  83150     },
  83151 #endif /* chips */
  83152 
  83153 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  83154     { /* SOC_REG_INT_XQMEMDEBUG_BCM53400_A0r */
  83155         soc_block_list[4],
  83156         soc_genreg,
  83157         1,
  83158         0,
  83159         0x2015a00,
  83160         0,
  83161         0,
  83162         1,
  83163         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
  83164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83165         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83166         -1,
  83167         -1,
  83168     },
  83169 #endif /* chips */
  83170 
  83171 #if defined(BCM_53540_A0)
  83172     { /* SOC_REG_INT_XQMEMDEBUG_BCM53540_A0r */
  83173         soc_block_list[4],
  83174         soc_genreg,
  83175         1,
  83176         0,
  83177         0x201e800,
  83178         0,
  83179         0,
  83180         1,
  83181         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
  83182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83183         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83184         -1,
  83185         -1,
  83186     },
  83187 #endif /* chips */
  83188 
  83189 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  83190     { /* SOC_REG_INT_XQMEMDEBUG_BCM53570_A0r */
  83191         soc_block_list[4],
  83192         soc_genreg,
  83193         1,
  83194         0,
  83195         0x2027800,
  83196         0,
  83197         0,
  83198         1,
  83199         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56260_A0r_fields,
  83200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83201         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83202         -1,
  83203         -1,
  83204     },
  83205 #endif /* chips */
  83206 
  83207 #if defined(BCM_56142_A0)
  83208     { /* SOC_REG_INT_XQMEMDEBUG_BCM56142_A0r */
  83209         soc_block_list[4],
  83210         soc_portreg,
  83211         1,
  83212         0,
  83213         0x15a,
  83214         0,
  83215         0,
  83216         1,
  83217         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
  83218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83219         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83220         -1,
  83221         -1,
  83222     },
  83223 #endif /* chips */
  83224 
  83225 #if defined(BCM_56150_A0)
  83226     { /* SOC_REG_INT_XQMEMDEBUG_BCM56150_A0r */
  83227         soc_block_list[4],
  83228         soc_portreg,
  83229         1,
  83230         0,
  83231         0x15a00,
  83232         0,
  83233         0,
  83234         1,
  83235         soc_FT_CNTR_RAM_CONTROLr_fields,
  83236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83237         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83238         -1,
  83239         79,
  83240     },
  83241 #endif /* chips */
  83242 
  83243 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  83244     { /* SOC_REG_INT_XQMEMDEBUG_BCM56224_A0r */
  83245         soc_block_list[4],
  83246         soc_portreg,
  83247         1,
  83248         0,
  83249         0x71,
  83250         0,
  83251         0,
  83252         1,
  83253         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
  83254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83255         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83256         -1,
  83257         -1,
  83258     },
  83259 #endif /* chips */
  83260 
  83261 #if defined(BCM_56314_A0)
  83262     { /* SOC_REG_INT_XQMEMDEBUG_BCM56314_A0r */
  83263         soc_block_list[4],
  83264         soc_portreg,
  83265         1,
  83266         0,
  83267         0x73,
  83268         0,
  83269         0,
  83270         2,
  83271         soc_L3_HIT_DEBUGr_fields,
  83272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83273         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83274         -1,
  83275         -1,
  83276     },
  83277 #endif /* chips */
  83278 
  83279 #if defined(BCM_56514_A0)
  83280     { /* SOC_REG_INT_XQMEMDEBUG_BCM56514_A0r */
  83281         soc_block_list[4],
  83282         soc_portreg,
  83283         1,
  83284         0,
  83285         0xc8,
  83286         0,
  83287         0,
  83288         6,
  83289         soc_XQMEMDEBUGr_fields,
  83290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83291         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83292         -1,
  83293         -1,
  83294     },
  83295 #endif /* chips */
  83296 
  83297 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  83298     defined(BCM_56504_B0)
  83299     { /* SOC_REG_INT_XQPARITYERRORPBMr */
  83300         soc_block_list[4],
  83301         soc_genreg,
  83302         1,
  83303         0,
  83304         0x80037,
  83305         SOC_REG_FLAG_RO,
  83306         0,
  83307         1,
  83308         soc_XQPARITYERRORPBMr_fields,
  83309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83310         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  83311         -1,
  83312         -1,
  83313     },
  83314 #endif /* chips */
  83315 
  83316 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  83317     { /* SOC_REG_INT_XQPARITYERRORPBM_BCM53314_A0r */
  83318         soc_block_list[4],
  83319         soc_genreg,
  83320         1,
  83321         0,
  83322         0x8002d,
  83323         SOC_REG_FLAG_RO,
  83324         0,
  83325         1,
  83326         soc_XQPARITYERRORPBM_BCM53314_A0r_fields,
  83327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83328         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  83329         -1,
  83330         -1,
  83331     },
  83332 #endif /* chips */
  83333 
  83334 #if defined(BCM_56142_A0)
  83335     { /* SOC_REG_INT_XQPARITYERRORPBM_BCM56142_A0r */
  83336         soc_block_list[4],
  83337         soc_genreg,
  83338         1,
  83339         0,
  83340         0x80045,
  83341         SOC_REG_FLAG_RO,
  83342         0,
  83343         1,
  83344         soc_XQPARITYERRORPBM_BCM56224_A0r_fields,
  83345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83346         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  83347         -1,
  83348         -1,
  83349     },
  83350 #endif /* chips */
  83351 
  83352 #if defined(BCM_56150_A0)
  83353     { /* SOC_REG_INT_XQPARITYERRORPBM_BCM56150_A0r */
  83354         soc_block_list[4],
  83355         soc_genreg,
  83356         1,
  83357         0,
  83358         0x2028600,
  83359         SOC_REG_FLAG_RO,
  83360         0,
  83361         1,
  83362         soc_XQPARITYERRORPBM_BCM56150_A0r_fields,
  83363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83364         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  83365         -1,
  83366         -1,
  83367     },
  83368 #endif /* chips */
  83369 
  83370 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  83371     { /* SOC_REG_INT_XQPARITYERRORPBM_BCM56224_A0r */
  83372         soc_block_list[4],
  83373         soc_genreg,
  83374         1,
  83375         0,
  83376         0x8002d,
  83377         SOC_REG_FLAG_RO,
  83378         0,
  83379         1,
  83380         soc_XQPARITYERRORPBM_BCM56224_A0r_fields,
  83381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83382         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  83383         -1,
  83384         -1,
  83385     },
  83386 #endif /* chips */
  83387 
  83388 #if defined(BCM_56514_A0)
  83389     { /* SOC_REG_INT_XQPARITYERRORPBM_BCM56514_A0r */
  83390         soc_block_list[4],
  83391         soc_genreg,
  83392         1,
  83393         0,
  83394         0x80047,
  83395         SOC_REG_FLAG_RO,
  83396         0,
  83397         1,
  83398         soc_XQPARITYERRORPBMr_fields,
  83399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83400         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  83401         -1,
  83402         -1,
  83403     },
  83404 #endif /* chips */
  83405 
  83406 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  83407     defined(BCM_56504_B0)
  83408     { /* SOC_REG_INT_XQPARITYERRORPTRr */
  83409         soc_block_list[4],
  83410         soc_portreg,
  83411         1,
  83412         0,
  83413         0x72,
  83414         SOC_REG_FLAG_RO,
  83415         0,
  83416         2,
  83417         soc_XQPARITYERRORPTRr_fields,
  83418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83419         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  83420         -1,
  83421         -1,
  83422     },
  83423 #endif /* chips */
  83424 
  83425 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  83426     { /* SOC_REG_INT_XQPARITYERRORPTR_BCM53314_A0r */
  83427         soc_block_list[4],
  83428         soc_portreg,
  83429         1,
  83430         0,
  83431         0x6f,
  83432         SOC_REG_FLAG_RO,
  83433         0,
  83434         3,
  83435         soc_XQPARITYERRORPTR_BCM53314_A0r_fields,
  83436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83437         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  83438         -1,
  83439         -1,
  83440     },
  83441 #endif /* chips */
  83442 
  83443 #if defined(BCM_53400_A0)
  83444     { /* SOC_REG_INT_XQPARITYERRORPTR_BCM53400_A0r */
  83445         soc_block_list[4],
  83446         soc_portreg,
  83447         1,
  83448         0,
  83449         0x15800,
  83450         SOC_REG_FLAG_RO,
  83451         0,
  83452         4,
  83453         soc_XQPARITYERRORPTR_BCM53400_A0r_fields,
  83454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83455         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  83456         -1,
  83457         79,
  83458     },
  83459 #endif /* chips */
  83460 
  83461 #if defined(BCM_53540_A0)
  83462     { /* SOC_REG_INT_XQPARITYERRORPTR_BCM53540_A0r */
  83463         soc_block_list[4],
  83464         soc_portreg,
  83465         1,
  83466         0,
  83467         0x1d800,
  83468         SOC_REG_FLAG_RO,
  83469         0,
  83470         4,
  83471         soc_XQPARITYERRORPTR_BCM53540_A0r_fields,
  83472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83473         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  83474         -1,
  83475         91,
  83476     },
  83477 #endif /* chips */
  83478 
  83479 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  83480     { /* SOC_REG_INT_XQPARITYERRORPTR_BCM53570_A0r */
  83481         soc_block_list[4],
  83482         soc_portreg,
  83483         1,
  83484         0,
  83485         0x25800,
  83486         SOC_REG_FLAG_RO,
  83487         0,
  83488         4,
  83489         soc_XQPARITYERRORPTR_BCM53570_A0r_fields,
  83490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83491         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  83492         -1,
  83493         101,
  83494     },
  83495 #endif /* chips */
  83496 
  83497 #if defined(BCM_56142_A0)
  83498     { /* SOC_REG_INT_XQPARITYERRORPTR_BCM56142_A0r */
  83499         soc_block_list[4],
  83500         soc_portreg,
  83501         1,
  83502         0,
  83503         0x158,
  83504         SOC_REG_FLAG_RO,
  83505         0,
  83506         3,
  83507         soc_XQPARITYERRORPTR_BCM56142_A0r_fields,
  83508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83509         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  83510         -1,
  83511         -1,
  83512     },
  83513 #endif /* chips */
  83514 
  83515 #if defined(BCM_56150_A0)
  83516     { /* SOC_REG_INT_XQPARITYERRORPTR_BCM56150_A0r */
  83517         soc_block_list[4],
  83518         soc_portreg,
  83519         1,
  83520         0,
  83521         0x15800,
  83522         SOC_REG_FLAG_RO,
  83523         0,
  83524         3,
  83525         soc_XQPARITYERRORPTR_BCM56150_A0r_fields,
  83526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83527         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  83528         -1,
  83529         79,
  83530     },
  83531 #endif /* chips */
  83532 
  83533 #if defined(BCM_56160_A0)
  83534     { /* SOC_REG_INT_XQPARITYERRORPTR_BCM56160_A0r */
  83535         soc_block_list[4],
  83536         soc_portreg,
  83537         1,
  83538         0,
  83539         0x15800,
  83540         SOC_REG_FLAG_RO,
  83541         0,
  83542         4,
  83543         soc_XQPARITYERRORPTR_BCM56160_A0r_fields,
  83544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83545         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  83546         -1,
  83547         91,
  83548     },
  83549 #endif /* chips */
  83550 
  83551 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  83552     { /* SOC_REG_INT_XQPARITYERRORPTR_BCM56224_A0r */
  83553         soc_block_list[4],
  83554         soc_portreg,
  83555         1,
  83556         0,
  83557         0x6f,
  83558         SOC_REG_FLAG_RO,
  83559         0,
  83560         3,
  83561         soc_XQPARITYERRORPTR_BCM56224_A0r_fields,
  83562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83563         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  83564         -1,
  83565         -1,
  83566     },
  83567 #endif /* chips */
  83568 
  83569 #if defined(BCM_56514_A0)
  83570     { /* SOC_REG_INT_XQPARITYERRORPTR_BCM56514_A0r */
  83571         soc_block_list[4],
  83572         soc_portreg,
  83573         1,
  83574         0,
  83575         0xc0,
  83576         SOC_REG_FLAG_RO,
  83577         0,
  83578         2,
  83579         soc_XQPARITYERRORPTRr_fields,
  83580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83581         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  83582         -1,
  83583         -1,
  83584     },
  83585 #endif /* chips */
  83586 
  83587 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  83588     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  83589     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  83590     { /* SOC_REG_INT_XQPORT_EHG_RX_DATA_PARITY_STATUS_INTRr */
  83591         soc_block_list[14],
  83592         soc_genreg,
  83593         1,
  83594         0,
  83595         0x80c0c,
  83596         0,
  83597         0,
  83598         4,
  83599         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83601         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83602         -1,
  83603         -1,
  83604     },
  83605 #endif /* chips */
  83606 
  83607 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  83608     { /* SOC_REG_INT_XQPORT_EHG_RX_DATA_PARITY_STATUS_INTR_BCM56334_A0r */
  83609         soc_block_list[14],
  83610         soc_genreg,
  83611         1,
  83612         0,
  83613         0x80c0c,
  83614         0,
  83615         0,
  83616         4,
  83617         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83619         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83620         -1,
  83621         -1,
  83622     },
  83623 #endif /* chips */
  83624 
  83625 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  83626     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  83627     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  83628     { /* SOC_REG_INT_XQPORT_EHG_RX_DATA_PARITY_STATUS_NACKr */
  83629         soc_block_list[14],
  83630         soc_genreg,
  83631         1,
  83632         0,
  83633         0x80c11,
  83634         0,
  83635         0,
  83636         4,
  83637         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83639         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83640         -1,
  83641         -1,
  83642     },
  83643 #endif /* chips */
  83644 
  83645 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  83646     { /* SOC_REG_INT_XQPORT_EHG_RX_DATA_PARITY_STATUS_NACK_BCM56334_A0r */
  83647         soc_block_list[14],
  83648         soc_genreg,
  83649         1,
  83650         0,
  83651         0x80c11,
  83652         0,
  83653         0,
  83654         4,
  83655         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83657         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83658         -1,
  83659         -1,
  83660     },
  83661 #endif /* chips */
  83662 
  83663 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  83664     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  83665     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  83666     { /* SOC_REG_INT_XQPORT_EHG_RX_MASK_PARITY_STATUS_INTRr */
  83667         soc_block_list[14],
  83668         soc_genreg,
  83669         1,
  83670         0,
  83671         0x80c0d,
  83672         0,
  83673         0,
  83674         4,
  83675         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83677         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83678         -1,
  83679         -1,
  83680     },
  83681 #endif /* chips */
  83682 
  83683 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  83684     { /* SOC_REG_INT_XQPORT_EHG_RX_MASK_PARITY_STATUS_INTR_BCM56334_A0r */
  83685         soc_block_list[14],
  83686         soc_genreg,
  83687         1,
  83688         0,
  83689         0x80c0d,
  83690         0,
  83691         0,
  83692         4,
  83693         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83695         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83696         -1,
  83697         -1,
  83698     },
  83699 #endif /* chips */
  83700 
  83701 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  83702     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  83703     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  83704     { /* SOC_REG_INT_XQPORT_EHG_RX_MASK_PARITY_STATUS_NACKr */
  83705         soc_block_list[14],
  83706         soc_genreg,
  83707         1,
  83708         0,
  83709         0x80c12,
  83710         0,
  83711         0,
  83712         4,
  83713         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83715         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83716         -1,
  83717         -1,
  83718     },
  83719 #endif /* chips */
  83720 
  83721 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  83722     { /* SOC_REG_INT_XQPORT_EHG_RX_MASK_PARITY_STATUS_NACK_BCM56334_A0r */
  83723         soc_block_list[14],
  83724         soc_genreg,
  83725         1,
  83726         0,
  83727         0x80c12,
  83728         0,
  83729         0,
  83730         4,
  83731         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83733         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83734         -1,
  83735         -1,
  83736     },
  83737 #endif /* chips */
  83738 
  83739 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  83740     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  83741     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  83742     { /* SOC_REG_INT_XQPORT_EHG_TX_DATA_PARITY_STATUS_INTRr */
  83743         soc_block_list[14],
  83744         soc_genreg,
  83745         1,
  83746         0,
  83747         0x80c0b,
  83748         0,
  83749         0,
  83750         4,
  83751         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83753         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83754         -1,
  83755         -1,
  83756     },
  83757 #endif /* chips */
  83758 
  83759 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  83760     { /* SOC_REG_INT_XQPORT_EHG_TX_DATA_PARITY_STATUS_INTR_BCM56334_A0r */
  83761         soc_block_list[14],
  83762         soc_genreg,
  83763         1,
  83764         0,
  83765         0x80c0b,
  83766         0,
  83767         0,
  83768         4,
  83769         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83771         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83772         -1,
  83773         -1,
  83774     },
  83775 #endif /* chips */
  83776 
  83777 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  83778     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  83779     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  83780     { /* SOC_REG_INT_XQPORT_EHG_TX_DATA_PARITY_STATUS_NACKr */
  83781         soc_block_list[14],
  83782         soc_genreg,
  83783         1,
  83784         0,
  83785         0x80c10,
  83786         0,
  83787         0,
  83788         4,
  83789         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83791         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83792         -1,
  83793         -1,
  83794     },
  83795 #endif /* chips */
  83796 
  83797 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  83798     { /* SOC_REG_INT_XQPORT_EHG_TX_DATA_PARITY_STATUS_NACK_BCM56334_A0r */
  83799         soc_block_list[14],
  83800         soc_genreg,
  83801         1,
  83802         0,
  83803         0x80c10,
  83804         0,
  83805         0,
  83806         4,
  83807         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  83808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83809         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  83810         -1,
  83811         -1,
  83812     },
  83813 #endif /* chips */
  83814 
  83815 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  83816     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  83817     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  83818     { /* SOC_REG_INT_XQPORT_FORCE_DOUBLE_BIT_ERRORr */
  83819         soc_block_list[14],
  83820         soc_genreg,
  83821         1,
  83822         0,
  83823         0x80c07,
  83824         0,
  83825         0,
  83826         5,
  83827         soc_XQPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  83828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83829         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83830         -1,
  83831         -1,
  83832     },
  83833 #endif /* chips */
  83834 
  83835 #if defined(BCM_56142_A0)
  83836     { /* SOC_REG_INT_XQPORT_FORCE_DOUBLE_BIT_ERROR_BCM56142_A0r */
  83837         soc_block_list[14],
  83838         soc_genreg,
  83839         1,
  83840         0,
  83841         0x80c07,
  83842         0,
  83843         0,
  83844         2,
  83845         soc_XQPORT_FORCE_DOUBLE_BIT_ERROR_BCM56142_A0r_fields,
  83846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83847         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83848         -1,
  83849         -1,
  83850     },
  83851 #endif /* chips */
  83852 
  83853 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  83854     { /* SOC_REG_INT_XQPORT_FORCE_DOUBLE_BIT_ERROR_BCM56334_A0r */
  83855         soc_block_list[14],
  83856         soc_genreg,
  83857         1,
  83858         0,
  83859         0x80c07,
  83860         0,
  83861         0,
  83862         5,
  83863         soc_XQPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  83864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83865         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83866         -1,
  83867         -1,
  83868     },
  83869 #endif /* chips */
  83870 
  83871 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  83872     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  83873     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  83874     { /* SOC_REG_INT_XQPORT_FORCE_SINGLE_BIT_ERRORr */
  83875         soc_block_list[14],
  83876         soc_genreg,
  83877         1,
  83878         0,
  83879         0x80c08,
  83880         0,
  83881         0,
  83882         5,
  83883         soc_XQPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  83884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83885         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83886         -1,
  83887         -1,
  83888     },
  83889 #endif /* chips */
  83890 
  83891 #if defined(BCM_56142_A0)
  83892     { /* SOC_REG_INT_XQPORT_FORCE_SINGLE_BIT_ERROR_BCM56142_A0r */
  83893         soc_block_list[14],
  83894         soc_genreg,
  83895         1,
  83896         0,
  83897         0x80c08,
  83898         0,
  83899         0,
  83900         2,
  83901         soc_XQPORT_FORCE_DOUBLE_BIT_ERROR_BCM56142_A0r_fields,
  83902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83904         -1,
  83905         -1,
  83906     },
  83907 #endif /* chips */
  83908 
  83909 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  83910     { /* SOC_REG_INT_XQPORT_FORCE_SINGLE_BIT_ERROR_BCM56334_A0r */
  83911         soc_block_list[14],
  83912         soc_genreg,
  83913         1,
  83914         0,
  83915         0x80c08,
  83916         0,
  83917         0,
  83918         5,
  83919         soc_XQPORT_FORCE_DOUBLE_BIT_ERRORr_fields,
  83920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83922         -1,
  83923         -1,
  83924     },
  83925 #endif /* chips */
  83926 
  83927 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  83928     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  83929     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  83930     { /* SOC_REG_INT_XQPORT_INTR_ENABLEr */
  83931         soc_block_list[14],
  83932         soc_genreg,
  83933         1,
  83934         0,
  83935         0x80c0a,
  83936         0,
  83937         0,
  83938         5,
  83939         soc_XQPORT_INTR_ENABLEr_fields,
  83940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83941         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  83942         -1,
  83943         -1,
  83944     },
  83945 #endif /* chips */
  83946 
  83947 #if defined(BCM_56142_A0)
  83948     { /* SOC_REG_INT_XQPORT_INTR_ENABLE_BCM56142_A0r */
  83949         soc_block_list[14],
  83950         soc_genreg,
  83951         1,
  83952         0,
  83953         0x80c0a,
  83954         0,
  83955         0,
  83956         2,
  83957         soc_XQPORT_INTR_ENABLE_BCM56142_A0r_fields,
  83958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83959         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  83960         -1,
  83961         -1,
  83962     },
  83963 #endif /* chips */
  83964 
  83965 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  83966     { /* SOC_REG_INT_XQPORT_INTR_ENABLE_BCM56334_A0r */
  83967         soc_block_list[14],
  83968         soc_genreg,
  83969         1,
  83970         0,
  83971         0x80c0a,
  83972         0,
  83973         0,
  83974         5,
  83975         soc_XQPORT_INTR_ENABLEr_fields,
  83976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83977         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  83978         -1,
  83979         -1,
  83980     },
  83981 #endif /* chips */
  83982 
  83983 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  83984     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  83985     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  83986     { /* SOC_REG_INT_XQPORT_INTR_STATUSr */
  83987         soc_block_list[14],
  83988         soc_genreg,
  83989         1,
  83990         0,
  83991         0x80c09,
  83992         SOC_REG_FLAG_RO,
  83993         0,
  83994         5,
  83995         soc_XQPORT_INTR_STATUSr_fields,
  83996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83997         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  83998         -1,
  83999         -1,
  84000     },
  84001 #endif /* chips */
  84002 
  84003 #if defined(BCM_56142_A0)
  84004     { /* SOC_REG_INT_XQPORT_INTR_STATUS_BCM56142_A0r */
  84005         soc_block_list[14],
  84006         soc_genreg,
  84007         1,
  84008         0,
  84009         0x80c09,
  84010         SOC_REG_FLAG_RO,
  84011         0,
  84012         2,
  84013         soc_XQPORT_INTR_STATUS_BCM56142_A0r_fields,
  84014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84015         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  84016         -1,
  84017         -1,
  84018     },
  84019 #endif /* chips */
  84020 
  84021 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  84022     { /* SOC_REG_INT_XQPORT_INTR_STATUS_BCM56334_A0r */
  84023         soc_block_list[14],
  84024         soc_genreg,
  84025         1,
  84026         0,
  84027         0x80c09,
  84028         SOC_REG_FLAG_RO,
  84029         0,
  84030         5,
  84031         soc_XQPORT_INTR_STATUSr_fields,
  84032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84033         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  84034         -1,
  84035         -1,
  84036     },
  84037 #endif /* chips */
  84038 
  84039 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  84040     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  84041     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  84042     { /* SOC_REG_INT_XQPORT_MODE_REGr */
  84043         soc_block_list[14],
  84044         soc_genreg,
  84045         1,
  84046         0,
  84047         0x80c00,
  84048         0,
  84049         0,
  84050         1,
  84051         soc_XQPORT_MODE_REGr_fields,
  84052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84053         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84054         -1,
  84055         -1,
  84056     },
  84057 #endif /* chips */
  84058 
  84059 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  84060     defined(BCM_56334_B0)
  84061     { /* SOC_REG_INT_XQPORT_MODE_REG_BCM56334_A0r */
  84062         soc_block_list[14],
  84063         soc_genreg,
  84064         1,
  84065         0,
  84066         0x80c00,
  84067         0,
  84068         0,
  84069         1,
  84070         soc_XQPORT_MODE_REGr_fields,
  84071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84072         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84073         -1,
  84074         -1,
  84075     },
  84076 #endif /* chips */
  84077 
  84078 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  84079     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  84080     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  84081     { /* SOC_REG_INT_XQPORT_PARITY_CONTROLr */
  84082         soc_block_list[14],
  84083         soc_genreg,
  84084         1,
  84085         0,
  84086         0x80c06,
  84087         0,
  84088         0,
  84089         5,
  84090         soc_XQPORT_INTR_ENABLEr_fields,
  84091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84092         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  84093         -1,
  84094         -1,
  84095     },
  84096 #endif /* chips */
  84097 
  84098 #if defined(BCM_56142_A0)
  84099     { /* SOC_REG_INT_XQPORT_PARITY_CONTROL_BCM56142_A0r */
  84100         soc_block_list[14],
  84101         soc_genreg,
  84102         1,
  84103         0,
  84104         0x80c06,
  84105         0,
  84106         0,
  84107         2,
  84108         soc_XQPORT_INTR_ENABLE_BCM56142_A0r_fields,
  84109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84110         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  84111         -1,
  84112         -1,
  84113     },
  84114 #endif /* chips */
  84115 
  84116 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  84117     { /* SOC_REG_INT_XQPORT_PARITY_CONTROL_BCM56334_A0r */
  84118         soc_block_list[14],
  84119         soc_genreg,
  84120         1,
  84121         0,
  84122         0x80c06,
  84123         0,
  84124         0,
  84125         5,
  84126         soc_XQPORT_INTR_ENABLEr_fields,
  84127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84128         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  84129         -1,
  84130         -1,
  84131     },
  84132 #endif /* chips */
  84133 
  84134 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  84135     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  84136     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  84137     { /* SOC_REG_INT_XQPORT_XGXS_NEWCTL_REGr */
  84138         soc_block_list[14],
  84139         soc_genreg,
  84140         1,
  84141         0,
  84142         0x80c01,
  84143         0,
  84144         0,
  84145         1,
  84146         soc_XQPORT_XGXS_NEWCTL_REGr_fields,
  84147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84148         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  84149         -1,
  84150         -1,
  84151     },
  84152 #endif /* chips */
  84153 
  84154 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  84155     defined(BCM_56334_B0)
  84156     { /* SOC_REG_INT_XQPORT_XGXS_NEWCTL_REG_BCM56334_A0r */
  84157         soc_block_list[14],
  84158         soc_genreg,
  84159         1,
  84160         0,
  84161         0x80c01,
  84162         0,
  84163         0,
  84164         1,
  84165         soc_XQPORT_XGXS_NEWCTL_REGr_fields,
  84166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84167         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  84168         -1,
  84169         -1,
  84170     },
  84171 #endif /* chips */
  84172 
  84173 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  84174     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  84175     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  84176     { /* SOC_REG_INT_XQPORT_XGXS_NEWSTATUS0_REGr */
  84177         soc_block_list[14],
  84178         soc_genreg,
  84179         1,
  84180         0,
  84181         0x80c02,
  84182         SOC_REG_FLAG_RO,
  84183         0,
  84184         8,
  84185         soc_XGPORT_EXTRA_XGXS_NEWSTATUS0_REGr_fields,
  84186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84187         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84188         -1,
  84189         -1,
  84190     },
  84191 #endif /* chips */
  84192 
  84193 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  84194     defined(BCM_56334_B0)
  84195     { /* SOC_REG_INT_XQPORT_XGXS_NEWSTATUS0_REG_BCM56334_A0r */
  84196         soc_block_list[14],
  84197         soc_genreg,
  84198         1,
  84199         0,
  84200         0x80c02,
  84201         SOC_REG_FLAG_RO,
  84202         0,
  84203         8,
  84204         soc_XQPORT_XGXS_NEWSTATUS0_REGr_fields,
  84205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84206         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84207         -1,
  84208         -1,
  84209     },
  84210 #endif /* chips */
  84211 
  84212 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  84213     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  84214     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  84215     { /* SOC_REG_INT_XQPORT_XGXS_NEWSTATUS1_REGr */
  84216         soc_block_list[14],
  84217         soc_genreg,
  84218         1,
  84219         0,
  84220         0x80c03,
  84221         SOC_REG_FLAG_RO,
  84222         0,
  84223         8,
  84224         soc_XGPORT_EXTRA_XGXS_NEWSTATUS1_REGr_fields,
  84225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84226         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84227         -1,
  84228         -1,
  84229     },
  84230 #endif /* chips */
  84231 
  84232 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  84233     defined(BCM_56334_B0)
  84234     { /* SOC_REG_INT_XQPORT_XGXS_NEWSTATUS1_REG_BCM56334_A0r */
  84235         soc_block_list[14],
  84236         soc_genreg,
  84237         1,
  84238         0,
  84239         0x80c03,
  84240         SOC_REG_FLAG_RO,
  84241         0,
  84242         8,
  84243         soc_XQPORT_XGXS_NEWSTATUS1_REGr_fields,
  84244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84245         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84246         -1,
  84247         -1,
  84248     },
  84249 #endif /* chips */
  84250 
  84251 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  84252     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  84253     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  84254     { /* SOC_REG_INT_XQPORT_XGXS_NEWSTATUS2_REGr */
  84255         soc_block_list[14],
  84256         soc_genreg,
  84257         1,
  84258         0,
  84259         0x80c04,
  84260         SOC_REG_FLAG_RO,
  84261         0,
  84262         8,
  84263         soc_XQPORT_XGXS_NEWSTATUS2_REGr_fields,
  84264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84265         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84266         -1,
  84267         -1,
  84268     },
  84269 #endif /* chips */
  84270 
  84271 #if defined(BCM_56142_A0)
  84272     { /* SOC_REG_INT_XQPORT_XGXS_NEWSTATUS2_REG_BCM56142_A0r */
  84273         soc_block_list[14],
  84274         soc_genreg,
  84275         1,
  84276         0,
  84277         0x80c04,
  84278         SOC_REG_FLAG_RO,
  84279         0,
  84280         5,
  84281         soc_XQPORT_XGXS_NEWSTATUS2_REG_BCM56142_A0r_fields,
  84282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84283         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84284         -1,
  84285         -1,
  84286     },
  84287 #endif /* chips */
  84288 
  84289 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  84290     { /* SOC_REG_INT_XQPORT_XGXS_NEWSTATUS2_REG_BCM56334_A0r */
  84291         soc_block_list[14],
  84292         soc_genreg,
  84293         1,
  84294         0,
  84295         0x80c04,
  84296         SOC_REG_FLAG_RO,
  84297         0,
  84298         3,
  84299         soc_XQPORT_XGXS_NEWSTATUS2_REG_BCM56334_A0r_fields,
  84300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84301         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84302         -1,
  84303         -1,
  84304     },
  84305 #endif /* chips */
  84306 
  84307 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  84308     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  84309     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  84310     { /* SOC_REG_INT_XQPORT_XGXS_NEWSTATUS3_REGr */
  84311         soc_block_list[14],
  84312         soc_genreg,
  84313         1,
  84314         0,
  84315         0x80c05,
  84316         SOC_REG_FLAG_RO,
  84317         0,
  84318         2,
  84319         soc_XGPORT_EXTRA_XGXS_NEWSTATUS3_REGr_fields,
  84320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84321         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84322         -1,
  84323         -1,
  84324     },
  84325 #endif /* chips */
  84326 
  84327 #if defined(BCM_56142_A0)
  84328     { /* SOC_REG_INT_XQPORT_XGXS_NEWSTATUS3_REG_BCM56142_A0r */
  84329         soc_block_list[14],
  84330         soc_genreg,
  84331         1,
  84332         0,
  84333         0x80c05,
  84334         SOC_REG_FLAG_RO,
  84335         0,
  84336         10,
  84337         soc_XQPORT_XGXS_NEWSTATUS3_REGr_fields,
  84338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84339         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84340         -1,
  84341         -1,
  84342     },
  84343 #endif /* chips */
  84344 
  84345 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  84346     { /* SOC_REG_INT_XQPORT_XGXS_NEWSTATUS3_REG_BCM56334_A0r */
  84347         soc_block_list[14],
  84348         soc_genreg,
  84349         1,
  84350         0,
  84351         0x80c05,
  84352         SOC_REG_FLAG_RO,
  84353         0,
  84354         2,
  84355         soc_XGPORT_EXTRA_XGXS_NEWSTATUS3_REGr_fields,
  84356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84357         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84358         -1,
  84359         -1,
  84360     },
  84361 #endif /* chips */
  84362 
  84363 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  84364     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  84365     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  84366     { /* SOC_REG_INT_XQPORT_XQBODE_TXFIFO_PARITY_STATUS_INTRr */
  84367         soc_block_list[14],
  84368         soc_genreg,
  84369         1,
  84370         0,
  84371         0x80c0f,
  84372         0,
  84373         0,
  84374         4,
  84375         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  84376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84377         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  84378         -1,
  84379         -1,
  84380     },
  84381 #endif /* chips */
  84382 
  84383 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  84384     defined(BCM_56334_B0)
  84385     { /* SOC_REG_INT_XQPORT_XQBODE_TXFIFO_PARITY_STATUS_INTR_BCM56334_A0r */
  84386         soc_block_list[14],
  84387         soc_genreg,
  84388         1,
  84389         0,
  84390         0x80c0f,
  84391         0,
  84392         0,
  84393         4,
  84394         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  84395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84396         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  84397         -1,
  84398         -1,
  84399     },
  84400 #endif /* chips */
  84401 
  84402 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  84403     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  84404     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  84405     { /* SOC_REG_INT_XQPORT_XQBOD_RXFIFO_PARITY_STATUS_INTRr */
  84406         soc_block_list[14],
  84407         soc_genreg,
  84408         1,
  84409         0,
  84410         0x80c0e,
  84411         0,
  84412         0,
  84413         4,
  84414         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  84415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84416         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  84417         -1,
  84418         -1,
  84419     },
  84420 #endif /* chips */
  84421 
  84422 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  84423     defined(BCM_56334_B0)
  84424     { /* SOC_REG_INT_XQPORT_XQBOD_RXFIFO_PARITY_STATUS_INTR_BCM56334_A0r */
  84425         soc_block_list[14],
  84426         soc_genreg,
  84427         1,
  84428         0,
  84429         0x80c0e,
  84430         0,
  84431         0,
  84432         4,
  84433         soc_GPORT_EHG_RX_DATA_PARITY_STATUS_INTRr_fields,
  84434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84435         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  84436         -1,
  84437         -1,
  84438     },
  84439 #endif /* chips */
  84440 
  84441 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  84442     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  84443     { /* SOC_REG_INT_XQREADPOINTERr */
  84444         soc_block_list[4],
  84445         soc_portreg,
  84446         1,
  84447         0,
  84448         0x43,
  84449         SOC_REG_FLAG_RO,
  84450         0,
  84451         2,
  84452         soc_XQREADPOINTERr_fields,
  84453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84454         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  84455         -1,
  84456         -1,
  84457     },
  84458 #endif /* chips */
  84459 
  84460 #if defined(BCM_53400_A0)
  84461     { /* SOC_REG_INT_XQREADPOINTER_BCM53400_A0r */
  84462         soc_block_list[4],
  84463         soc_portreg,
  84464         1,
  84465         0,
  84466         0x13000,
  84467         SOC_REG_FLAG_RO,
  84468         0,
  84469         2,
  84470         soc_XQREADPOINTER_BCM53400_A0r_fields,
  84471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84472         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  84473         -1,
  84474         79,
  84475     },
  84476 #endif /* chips */
  84477 
  84478 #if defined(BCM_53540_A0)
  84479     { /* SOC_REG_INT_XQREADPOINTER_BCM53540_A0r */
  84480         soc_block_list[4],
  84481         soc_portreg,
  84482         1,
  84483         0,
  84484         0x19800,
  84485         SOC_REG_FLAG_RO,
  84486         0,
  84487         2,
  84488         soc_XQREADPOINTER_BCM53540_A0r_fields,
  84489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84490         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  84491         -1,
  84492         91,
  84493     },
  84494 #endif /* chips */
  84495 
  84496 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  84497     { /* SOC_REG_INT_XQREADPOINTER_BCM53570_A0r */
  84498         soc_block_list[4],
  84499         soc_portreg,
  84500         1,
  84501         0,
  84502         0x1a800,
  84503         SOC_REG_FLAG_RO,
  84504         0,
  84505         2,
  84506         soc_XQREADPOINTER_BCM53570_A0r_fields,
  84507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84508         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  84509         -1,
  84510         101,
  84511     },
  84512 #endif /* chips */
  84513 
  84514 #if defined(BCM_56142_A0)
  84515     { /* SOC_REG_INT_XQREADPOINTER_BCM56142_A0r */
  84516         soc_block_list[4],
  84517         soc_portreg,
  84518         1,
  84519         0,
  84520         0x130,
  84521         SOC_REG_FLAG_RO,
  84522         0,
  84523         2,
  84524         soc_XQREADPOINTERr_fields,
  84525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84526         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  84527         -1,
  84528         -1,
  84529     },
  84530 #endif /* chips */
  84531 
  84532 #if defined(BCM_56150_A0)
  84533     { /* SOC_REG_INT_XQREADPOINTER_BCM56150_A0r */
  84534         soc_block_list[4],
  84535         soc_portreg,
  84536         1,
  84537         0,
  84538         0x13000,
  84539         SOC_REG_FLAG_RO,
  84540         0,
  84541         2,
  84542         soc_XQREADPOINTER_BCM56150_A0r_fields,
  84543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84544         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  84545         -1,
  84546         79,
  84547     },
  84548 #endif /* chips */
  84549 
  84550 #if defined(BCM_56160_A0)
  84551     { /* SOC_REG_INT_XQREADPOINTER_BCM56160_A0r */
  84552         soc_block_list[4],
  84553         soc_portreg,
  84554         1,
  84555         0,
  84556         0x13000,
  84557         SOC_REG_FLAG_RO,
  84558         0,
  84559         2,
  84560         soc_XQREADPOINTER_BCM53400_A0r_fields,
  84561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84562         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  84563         -1,
  84564         91,
  84565     },
  84566 #endif /* chips */
  84567 
  84568 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  84569     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  84570     { /* SOC_REG_INT_XQREADPOINTER_BCM56224_A0r */
  84571         soc_block_list[4],
  84572         soc_portreg,
  84573         1,
  84574         0,
  84575         0x5f,
  84576         SOC_REG_FLAG_RO,
  84577         0,
  84578         2,
  84579         soc_XQREADPOINTERr_fields,
  84580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84581         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  84582         -1,
  84583         -1,
  84584     },
  84585 #endif /* chips */
  84586 
  84587 #if defined(BCM_53400_A0)
  84588     { /* SOC_REG_INT_XQ_ERR_CLRr */
  84589         soc_block_list[4],
  84590         soc_genreg,
  84591         1,
  84592         0,
  84593         0x2141200,
  84594         SOC_REG_FLAG_WO,
  84595         0,
  84596         1,
  84597         soc_IPMC_GROUP_ERR_CLRr_fields,
  84598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84599         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  84600         -1,
  84601         -1,
  84602     },
  84603 #endif /* chips */
  84604 
  84605 #if defined(BCM_53570_A0)
  84606     { /* SOC_REG_INT_XQ_ERR_CLR_0r */
  84607         soc_block_list[4],
  84608         soc_genreg,
  84609         1,
  84610         0,
  84611         0x20d8000,
  84612         SOC_REG_FLAG_WO,
  84613         0,
  84614         1,
  84615         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  84616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84618         -1,
  84619         -1,
  84620     },
  84621 #endif /* chips */
  84622 
  84623 #if defined(BCM_53570_A0)
  84624     { /* SOC_REG_INT_XQ_ERR_CLR_1r */
  84625         soc_block_list[4],
  84626         soc_genreg,
  84627         1,
  84628         0,
  84629         0x20d8100,
  84630         SOC_REG_FLAG_WO,
  84631         0,
  84632         1,
  84633         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  84634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84635         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84636         -1,
  84637         -1,
  84638     },
  84639 #endif /* chips */
  84640 
  84641 #if defined(BCM_53570_A0)
  84642     { /* SOC_REG_INT_XQ_ERR_CLR_2r */
  84643         soc_block_list[4],
  84644         soc_genreg,
  84645         1,
  84646         0,
  84647         0x20d8200,
  84648         SOC_REG_FLAG_WO,
  84649         0,
  84650         1,
  84651         soc_IPMC_GROUP_ERR_CLR_2r_fields,
  84652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84653         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  84654         -1,
  84655         -1,
  84656     },
  84657 #endif /* chips */
  84658 
  84659 #if defined(BCM_53570_B0)
  84660     { /* SOC_REG_INT_XQ_ERR_CLR_0_BCM53570_B0r */
  84661         soc_block_list[4],
  84662         soc_genreg,
  84663         1,
  84664         0,
  84665         0x20d8300,
  84666         SOC_REG_FLAG_WO,
  84667         0,
  84668         1,
  84669         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  84670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84671         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84672         -1,
  84673         -1,
  84674     },
  84675 #endif /* chips */
  84676 
  84677 #if defined(BCM_53570_B0)
  84678     { /* SOC_REG_INT_XQ_ERR_CLR_1_BCM53570_B0r */
  84679         soc_block_list[4],
  84680         soc_genreg,
  84681         1,
  84682         0,
  84683         0x20d8400,
  84684         SOC_REG_FLAG_WO,
  84685         0,
  84686         1,
  84687         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  84688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84690         -1,
  84691         -1,
  84692     },
  84693 #endif /* chips */
  84694 
  84695 #if defined(BCM_53570_B0)
  84696     { /* SOC_REG_INT_XQ_ERR_CLR_2_BCM53570_B0r */
  84697         soc_block_list[4],
  84698         soc_genreg,
  84699         1,
  84700         0,
  84701         0x20d8500,
  84702         SOC_REG_FLAG_WO,
  84703         0,
  84704         1,
  84705         soc_IPMC_GROUP_ERR_CLR_2r_fields,
  84706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84707         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  84708         -1,
  84709         -1,
  84710     },
  84711 #endif /* chips */
  84712 
  84713 #if defined(BCM_53540_A0)
  84714     { /* SOC_REG_INT_XQ_ERR_CLR_BCM53540_A0r */
  84715         soc_block_list[4],
  84716         soc_genreg,
  84717         1,
  84718         0,
  84719         0x2071800,
  84720         SOC_REG_FLAG_WO,
  84721         0,
  84722         1,
  84723         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  84724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84726         -1,
  84727         -1,
  84728     },
  84729 #endif /* chips */
  84730 
  84731 #if defined(BCM_56160_A0)
  84732     { /* SOC_REG_INT_XQ_ERR_CLR_BCM56160_A0r */
  84733         soc_block_list[4],
  84734         soc_genreg,
  84735         1,
  84736         0,
  84737         0x2141200,
  84738         SOC_REG_FLAG_WO,
  84739         0,
  84740         1,
  84741         soc_IPMC_GROUP_ERR_CLR_BCM56160_A0r_fields,
  84742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84744         -1,
  84745         -1,
  84746     },
  84747 #endif /* chips */
  84748 
  84749 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  84750     { /* SOC_REG_INT_XQ_ERR_CNTr */
  84751         soc_block_list[4],
  84752         soc_genreg,
  84753         1,
  84754         0,
  84755         0x2142000,
  84756         0,
  84757         0,
  84758         1,
  84759         soc_MEM_ERR_CNT0r_fields,
  84760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84761         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  84762         -1,
  84763         -1,
  84764     },
  84765 #endif /* chips */
  84766 
  84767 #if defined(BCM_53540_A0)
  84768     { /* SOC_REG_INT_XQ_ERR_CNT_BCM53540_A0r */
  84769         soc_block_list[4],
  84770         soc_genreg,
  84771         1,
  84772         0,
  84773         0x2075800,
  84774         0,
  84775         0,
  84776         1,
  84777         soc_MEM_ERR_CNT0r_fields,
  84778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84779         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  84780         -1,
  84781         -1,
  84782     },
  84783 #endif /* chips */
  84784 
  84785 #if defined(BCM_53570_A0)
  84786     { /* SOC_REG_INT_XQ_ERR_CNT_BCM53570_A0r */
  84787         soc_block_list[4],
  84788         soc_genreg,
  84789         1,
  84790         0,
  84791         0x20dce00,
  84792         0,
  84793         0,
  84794         1,
  84795         soc_MEM_ERR_CNT0r_fields,
  84796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84797         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  84798         -1,
  84799         -1,
  84800     },
  84801 #endif /* chips */
  84802 
  84803 #if defined(BCM_53570_B0)
  84804     { /* SOC_REG_INT_XQ_ERR_CNT_BCM53570_B0r */
  84805         soc_block_list[4],
  84806         soc_genreg,
  84807         1,
  84808         0,
  84809         0x20dd100,
  84810         0,
  84811         0,
  84812         1,
  84813         soc_MEM_ERR_CNT0r_fields,
  84814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84815         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  84816         -1,
  84817         -1,
  84818     },
  84819 #endif /* chips */
  84820 
  84821 #if defined(BCM_53400_A0)
  84822     { /* SOC_REG_INT_XQ_ERR_VLDr */
  84823         soc_block_list[4],
  84824         soc_genreg,
  84825         1,
  84826         0,
  84827         0x2141000,
  84828         SOC_REG_FLAG_RO,
  84829         0,
  84830         1,
  84831         soc_IPMC_GROUP_ERR_VLDr_fields,
  84832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84833         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  84834         -1,
  84835         -1,
  84836     },
  84837 #endif /* chips */
  84838 
  84839 #if defined(BCM_53570_A0)
  84840     { /* SOC_REG_INT_XQ_ERR_VLD_0r */
  84841         soc_block_list[4],
  84842         soc_genreg,
  84843         1,
  84844         0,
  84845         0x20d5e00,
  84846         SOC_REG_FLAG_RO,
  84847         0,
  84848         1,
  84849         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  84850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84851         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84852         -1,
  84853         -1,
  84854     },
  84855 #endif /* chips */
  84856 
  84857 #if defined(BCM_53570_A0)
  84858     { /* SOC_REG_INT_XQ_ERR_VLD_1r */
  84859         soc_block_list[4],
  84860         soc_genreg,
  84861         1,
  84862         0,
  84863         0x20d6600,
  84864         SOC_REG_FLAG_RO,
  84865         0,
  84866         1,
  84867         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  84868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84869         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84870         -1,
  84871         -1,
  84872     },
  84873 #endif /* chips */
  84874 
  84875 #if defined(BCM_53570_A0)
  84876     { /* SOC_REG_INT_XQ_ERR_VLD_2r */
  84877         soc_block_list[4],
  84878         soc_genreg,
  84879         1,
  84880         0,
  84881         0x20d6e00,
  84882         SOC_REG_FLAG_RO,
  84883         0,
  84884         1,
  84885         soc_IPMC_GROUP_ERR_VLD_2r_fields,
  84886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84887         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  84888         -1,
  84889         -1,
  84890     },
  84891 #endif /* chips */
  84892 
  84893 #if defined(BCM_53570_B0)
  84894     { /* SOC_REG_INT_XQ_ERR_VLD_0_BCM53570_B0r */
  84895         soc_block_list[4],
  84896         soc_genreg,
  84897         1,
  84898         0,
  84899         0x20d6100,
  84900         SOC_REG_FLAG_RO,
  84901         0,
  84902         1,
  84903         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  84904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84905         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84906         -1,
  84907         -1,
  84908     },
  84909 #endif /* chips */
  84910 
  84911 #if defined(BCM_53570_B0)
  84912     { /* SOC_REG_INT_XQ_ERR_VLD_1_BCM53570_B0r */
  84913         soc_block_list[4],
  84914         soc_genreg,
  84915         1,
  84916         0,
  84917         0x20d6900,
  84918         SOC_REG_FLAG_RO,
  84919         0,
  84920         1,
  84921         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  84922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84923         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84924         -1,
  84925         -1,
  84926     },
  84927 #endif /* chips */
  84928 
  84929 #if defined(BCM_53570_B0)
  84930     { /* SOC_REG_INT_XQ_ERR_VLD_2_BCM53570_B0r */
  84931         soc_block_list[4],
  84932         soc_genreg,
  84933         1,
  84934         0,
  84935         0x20d7100,
  84936         SOC_REG_FLAG_RO,
  84937         0,
  84938         1,
  84939         soc_IPMC_GROUP_ERR_VLD_2r_fields,
  84940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84941         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  84942         -1,
  84943         -1,
  84944     },
  84945 #endif /* chips */
  84946 
  84947 #if defined(BCM_53540_A0)
  84948     { /* SOC_REG_INT_XQ_ERR_VLD_BCM53540_A0r */
  84949         soc_block_list[4],
  84950         soc_genreg,
  84951         1,
  84952         0,
  84953         0x2070800,
  84954         SOC_REG_FLAG_RO,
  84955         0,
  84956         1,
  84957         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  84958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84959         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84960         -1,
  84961         -1,
  84962     },
  84963 #endif /* chips */
  84964 
  84965 #if defined(BCM_56160_A0)
  84966     { /* SOC_REG_INT_XQ_ERR_VLD_BCM56160_A0r */
  84967         soc_block_list[4],
  84968         soc_genreg,
  84969         1,
  84970         0,
  84971         0x2141000,
  84972         SOC_REG_FLAG_RO,
  84973         0,
  84974         1,
  84975         soc_IPMC_GROUP_ERR_VLD_BCM56160_A0r_fields,
  84976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84977         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84978         -1,
  84979         -1,
  84980     },
  84981 #endif /* chips */
  84982 
  84983 #if defined(BCM_53400_A0)
  84984     { /* SOC_REG_INT_XQ_MULTI_ERRr */
  84985         soc_block_list[4],
  84986         soc_genreg,
  84987         1,
  84988         0,
  84989         0x2141100,
  84990         SOC_REG_FLAG_RO,
  84991         0,
  84992         1,
  84993         soc_IPMC_GROUP_MULTI_ERRr_fields,
  84994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84995         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  84996         -1,
  84997         -1,
  84998     },
  84999 #endif /* chips */
  85000 
  85001 #if defined(BCM_53570_A0)
  85002     { /* SOC_REG_INT_XQ_MULTI_ERR_0r */
  85003         soc_block_list[4],
  85004         soc_genreg,
  85005         1,
  85006         0,
  85007         0x20d7600,
  85008         SOC_REG_FLAG_RO,
  85009         0,
  85010         1,
  85011         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  85012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85013         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85014         -1,
  85015         -1,
  85016     },
  85017 #endif /* chips */
  85018 
  85019 #if defined(BCM_53570_A0)
  85020     { /* SOC_REG_INT_XQ_MULTI_ERR_1r */
  85021         soc_block_list[4],
  85022         soc_genreg,
  85023         1,
  85024         0,
  85025         0x20d7700,
  85026         SOC_REG_FLAG_RO,
  85027         0,
  85028         1,
  85029         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  85030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85031         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85032         -1,
  85033         -1,
  85034     },
  85035 #endif /* chips */
  85036 
  85037 #if defined(BCM_53570_A0)
  85038     { /* SOC_REG_INT_XQ_MULTI_ERR_2r */
  85039         soc_block_list[4],
  85040         soc_genreg,
  85041         1,
  85042         0,
  85043         0x20d7800,
  85044         SOC_REG_FLAG_RO,
  85045         0,
  85046         1,
  85047         soc_IPMC_GROUP_MULTI_ERR_2r_fields,
  85048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85049         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  85050         -1,
  85051         -1,
  85052     },
  85053 #endif /* chips */
  85054 
  85055 #if defined(BCM_53570_B0)
  85056     { /* SOC_REG_INT_XQ_MULTI_ERR_0_BCM53570_B0r */
  85057         soc_block_list[4],
  85058         soc_genreg,
  85059         1,
  85060         0,
  85061         0x20d7900,
  85062         SOC_REG_FLAG_RO,
  85063         0,
  85064         1,
  85065         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  85066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85067         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85068         -1,
  85069         -1,
  85070     },
  85071 #endif /* chips */
  85072 
  85073 #if defined(BCM_53570_B0)
  85074     { /* SOC_REG_INT_XQ_MULTI_ERR_1_BCM53570_B0r */
  85075         soc_block_list[4],
  85076         soc_genreg,
  85077         1,
  85078         0,
  85079         0x20d7a00,
  85080         SOC_REG_FLAG_RO,
  85081         0,
  85082         1,
  85083         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  85084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85085         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85086         -1,
  85087         -1,
  85088     },
  85089 #endif /* chips */
  85090 
  85091 #if defined(BCM_53570_B0)
  85092     { /* SOC_REG_INT_XQ_MULTI_ERR_2_BCM53570_B0r */
  85093         soc_block_list[4],
  85094         soc_genreg,
  85095         1,
  85096         0,
  85097         0x20d7b00,
  85098         SOC_REG_FLAG_RO,
  85099         0,
  85100         1,
  85101         soc_IPMC_GROUP_MULTI_ERR_2r_fields,
  85102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85103         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  85104         -1,
  85105         -1,
  85106     },
  85107 #endif /* chips */
  85108 
  85109 #if defined(BCM_53540_A0)
  85110     { /* SOC_REG_INT_XQ_MULTI_ERR_BCM53540_A0r */
  85111         soc_block_list[4],
  85112         soc_genreg,
  85113         1,
  85114         0,
  85115         0x2071000,
  85116         SOC_REG_FLAG_RO,
  85117         0,
  85118         1,
  85119         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  85120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85121         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85122         -1,
  85123         -1,
  85124     },
  85125 #endif /* chips */
  85126 
  85127 #if defined(BCM_56160_A0)
  85128     { /* SOC_REG_INT_XQ_MULTI_ERR_BCM56160_A0r */
  85129         soc_block_list[4],
  85130         soc_genreg,
  85131         1,
  85132         0,
  85133         0x2141100,
  85134         SOC_REG_FLAG_RO,
  85135         0,
  85136         1,
  85137         soc_IPMC_GROUP_MULTI_ERR_BCM56160_A0r_fields,
  85138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85139         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85140         -1,
  85141         -1,
  85142     },
  85143 #endif /* chips */
  85144 
  85145 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  85146     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  85147     { /* SOC_REG_INT_XTHOLr */
  85148         soc_block_list[0],
  85149         soc_portreg,
  85150         1,
  85151         0,
  85152         0x101,
  85153         0,
  85154         0,
  85155         1,
  85156         soc_XTHOLr_fields,
  85157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85158         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85159         -1,
  85160         -1,
  85161     },
  85162 #endif /* chips */
  85163 
  85164 #if defined(BCM_56150_A0)
  85165     { /* SOC_REG_INT_XTHOL_64r */
  85166         soc_block_list[16],
  85167         soc_portreg,
  85168         1,
  85169         0,
  85170         0x7000,
  85171         SOC_REG_FLAG_64_BITS,
  85172         0,
  85173         1,
  85174         soc_EP_NUM_NORM_CELLS_RECVD_BCM56450_A0r_fields,
  85175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85176         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  85177         -1,
  85178         -1,
  85179     },
  85180 #endif /* chips */
  85181 
  85182 #if defined(BCM_2801PM_A0)
  85183     { /* SOC_REG_INT_XTHOL_BCM2801PM_A0r */
  85184         soc_block_list[211],
  85185         soc_portreg,
  85186         1,
  85187         0,
  85188         0x7000,
  85189         SOC_REG_FLAG_64_BITS |
  85190                           SOC_REG_FLAG_COUNTER,
  85191         0,
  85192         1,
  85193         soc_R1023_BCM2801PM_A0r_fields,
  85194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85195         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85196         112,
  85197         -1,
  85198     },
  85199 #endif /* chips */
  85200 
  85201 #if defined(BCM_53400_A0)
  85202     { /* SOC_REG_INT_XTHOL_BCM53400_A0r */
  85203         soc_block_list[16],
  85204         soc_portreg,
  85205         1,
  85206         0,
  85207         0x7000,
  85208         SOC_REG_FLAG_64_BITS |
  85209                           SOC_REG_FLAG_COUNTER,
  85210         0,
  85211         1,
  85212         soc_R1023_BCM2801PM_A0r_fields,
  85213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85214         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85215         211,
  85216         -1,
  85217     },
  85218 #endif /* chips */
  85219 
  85220 #if defined(BCM_56160_A0)
  85221     { /* SOC_REG_INT_XTHOL_BCM56160_A0r */
  85222         soc_block_list[16],
  85223         soc_portreg,
  85224         1,
  85225         0,
  85226         0x7000,
  85227         SOC_REG_FLAG_64_BITS |
  85228                           SOC_REG_FLAG_COUNTER,
  85229         0,
  85230         1,
  85231         soc_R1023_BCM2801PM_A0r_fields,
  85232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85233         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85234         211,
  85235         -1,
  85236     },
  85237 #endif /* chips */
  85238 
  85239 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  85240     { /* SOC_REG_INT_XTHOL_BCM56260_A0r */
  85241         soc_block_list[16],
  85242         soc_portreg,
  85243         1,
  85244         0,
  85245         0x7000,
  85246         SOC_REG_FLAG_64_BITS |
  85247                           SOC_REG_FLAG_COUNTER,
  85248         0,
  85249         1,
  85250         soc_R1023_BCM2801PM_A0r_fields,
  85251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85252         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85253         157,
  85254         -1,
  85255     },
  85256 #endif /* chips */
  85257 
  85258 #if defined(BCM_56270_A0)
  85259     { /* SOC_REG_INT_XTHOL_BCM56270_A0r */
  85260         soc_block_list[16],
  85261         soc_portreg,
  85262         1,
  85263         0,
  85264         0x7000,
  85265         SOC_REG_FLAG_64_BITS |
  85266                           SOC_REG_FLAG_COUNTER,
  85267         0,
  85268         1,
  85269         soc_R1023_BCM2801PM_A0r_fields,
  85270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85271         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85272         157,
  85273         -1,
  85274     },
  85275 #endif /* chips */
  85276 
  85277 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  85278     { /* SOC_REG_INT_XTHOL_BCM56334_A0r */
  85279         soc_block_list[14],
  85280         soc_portreg,
  85281         1,
  85282         0,
  85283         0x825,
  85284         0,
  85285         0,
  85286         1,
  85287         soc_XTHOLr_fields,
  85288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85289         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85290         -1,
  85291         -1,
  85292     },
  85293 #endif /* chips */
  85294 
  85295 #if defined(BCM_56340_A0)
  85296     { /* SOC_REG_INT_XTHOL_BCM56340_A0r */
  85297         soc_block_list[214],
  85298         soc_portreg,
  85299         1,
  85300         0,
  85301         0x21a00,
  85302         0,
  85303         0,
  85304         1,
  85305         soc_AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr_fields,
  85306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85307         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85308         -1,
  85309         -1,
  85310     },
  85311 #endif /* chips */
  85312 
  85313 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  85314     { /* SOC_REG_INT_XTHOL_BCM56440_A0r */
  85315         soc_block_list[83],
  85316         soc_portreg,
  85317         1,
  85318         0,
  85319         0x215,
  85320         0,
  85321         0,
  85322         1,
  85323         soc_XTHOLr_fields,
  85324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85325         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85326         -1,
  85327         -1,
  85328     },
  85329 #endif /* chips */
  85330 
  85331 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  85332     defined(BCM_56450_B1)
  85333     { /* SOC_REG_INT_XTHOL_BCM56450_A0r */
  85334         soc_block_list[83],
  85335         soc_portreg,
  85336         1,
  85337         0,
  85338         0x21500,
  85339         0,
  85340         0,
  85341         1,
  85342         soc_AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr_fields,
  85343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85344         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85345         -1,
  85346         -1,
  85347     },
  85348 #endif /* chips */
  85349 
  85350 #if defined(BCM_56560_A0)
  85351     { /* SOC_REG_INT_XTHOL_BCM56560_A0r */
  85352         soc_block_list[216],
  85353         soc_portreg,
  85354         1,
  85355         0,
  85356         0x7000,
  85357         SOC_REG_FLAG_64_BITS |
  85358                           SOC_REG_FLAG_COUNTER,
  85359         0,
  85360         1,
  85361         soc_R1023_BCM2801PM_A0r_fields,
  85362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85363         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85364         160,
  85365         -1,
  85366     },
  85367 #endif /* chips */
  85368 
  85369 #if defined(BCM_56560_B0)
  85370     { /* SOC_REG_INT_XTHOL_BCM56560_B0r */
  85371         soc_block_list[219],
  85372         soc_portreg,
  85373         1,
  85374         0,
  85375         0x7000,
  85376         SOC_REG_FLAG_64_BITS |
  85377                           SOC_REG_FLAG_COUNTER,
  85378         0,
  85379         1,
  85380         soc_R1023_BCM2801PM_A0r_fields,
  85381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85382         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85383         160,
  85384         -1,
  85385     },
  85386 #endif /* chips */
  85387 
  85388 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  85389     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  85390     { /* SOC_REG_INT_XTHOL_BCM56624_A0r */
  85391         soc_block_list[204],
  85392         soc_portreg,
  85393         1,
  85394         0,
  85395         0x825,
  85396         0,
  85397         0,
  85398         1,
  85399         soc_XTHOLr_fields,
  85400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85401         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85402         -1,
  85403         -1,
  85404     },
  85405 #endif /* chips */
  85406 
  85407 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  85408     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  85409     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  85410     { /* SOC_REG_INT_XTHOL_BCM56634_A0r */
  85411         soc_block_list[208],
  85412         soc_portreg,
  85413         1,
  85414         0,
  85415         0x825,
  85416         0,
  85417         0,
  85418         1,
  85419         soc_XTHOLr_fields,
  85420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85421         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85422         -1,
  85423         -1,
  85424     },
  85425 #endif /* chips */
  85426 
  85427 #if defined(BCM_56640_A0)
  85428     { /* SOC_REG_INT_XTHOL_BCM56640_A0r */
  85429         soc_block_list[212],
  85430         soc_portreg,
  85431         1,
  85432         0,
  85433         0x21a00,
  85434         0,
  85435         0,
  85436         1,
  85437         soc_AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr_fields,
  85438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85439         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85440         -1,
  85441         -1,
  85442     },
  85443 #endif /* chips */
  85444 
  85445 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  85446     { /* SOC_REG_INT_XTHOL_BCM56670_A0r */
  85447         soc_block_list[215],
  85448         soc_portreg,
  85449         1,
  85450         0,
  85451         0x7000,
  85452         SOC_REG_FLAG_64_BITS |
  85453                           SOC_REG_FLAG_COUNTER,
  85454         0,
  85455         1,
  85456         soc_R1023_BCM2801PM_A0r_fields,
  85457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85458         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85459         160,
  85460         -1,
  85461     },
  85462 #endif /* chips */
  85463 
  85464 #if defined(BCM_56800_A0)
  85465     { /* SOC_REG_INT_XTHOL_BCM56800_A0r */
  85466         soc_block_list[9],
  85467         soc_portreg,
  85468         1,
  85469         0,
  85470         0x901,
  85471         0,
  85472         0,
  85473         1,
  85474         soc_XTHOLr_fields,
  85475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85476         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85477         -1,
  85478         -1,
  85479     },
  85480 #endif /* chips */
  85481 
  85482 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  85483     { /* SOC_REG_INT_XTHOL_BCM56820_A0r */
  85484         soc_block_list[9],
  85485         soc_portreg,
  85486         1,
  85487         0,
  85488         0x825,
  85489         0,
  85490         0,
  85491         1,
  85492         soc_XTHOLr_fields,
  85493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85494         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85495         -1,
  85496         -1,
  85497     },
  85498 #endif /* chips */
  85499 
  85500 #if defined(BCM_56840_A0)
  85501     { /* SOC_REG_INT_XTHOL_BCM56840_A0r */
  85502         soc_block_list[16],
  85503         soc_portreg,
  85504         1,
  85505         0,
  85506         0x21d,
  85507         0,
  85508         0,
  85509         1,
  85510         soc_XTHOLr_fields,
  85511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85512         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85513         -1,
  85514         -1,
  85515     },
  85516 #endif /* chips */
  85517 
  85518 #if defined(BCM_56840_B0)
  85519     { /* SOC_REG_INT_XTHOL_BCM56840_B0r */
  85520         soc_block_list[16],
  85521         soc_portreg,
  85522         1,
  85523         0,
  85524         0x21d,
  85525         0,
  85526         0,
  85527         1,
  85528         soc_XTHOLr_fields,
  85529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85530         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85531         -1,
  85532         -1,
  85533     },
  85534 #endif /* chips */
  85535 
  85536 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  85537     { /* SOC_REG_INT_XTHOL_BCM56850_A0r */
  85538         soc_block_list[116],
  85539         soc_portreg,
  85540         1,
  85541         0,
  85542         0x47000,
  85543         0,
  85544         0,
  85545         1,
  85546         soc_AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr_fields,
  85547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85548         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85549         -1,
  85550         -1,
  85551     },
  85552 #endif /* chips */
  85553 
  85554 #if defined(BCM_56960_A0)
  85555     { /* SOC_REG_INT_XTHOL_BCM56960_A0r */
  85556         soc_block_list[215],
  85557         soc_portreg,
  85558         1,
  85559         0,
  85560         0x7000,
  85561         0,
  85562         0,
  85563         1,
  85564         soc_CLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
  85565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85566         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85567         -1,
  85568         -1,
  85569         3,
  85570     },
  85571 #endif /* chips */
  85572 
  85573 #if defined(BCM_56965_A0)
  85574     { /* SOC_REG_INT_XTHOL_BCM56965_A0r */
  85575         soc_block_list[16],
  85576         soc_portreg,
  85577         1,
  85578         0,
  85579         0x7000,
  85580         0,
  85581         0,
  85582         1,
  85583         soc_CLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields,
  85584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85585         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85586         -1,
  85587         -1,
  85588         3,
  85589     },
  85590 #endif /* chips */
  85591 
  85592 #if defined(BCM_88270_A0)
  85593     { /* SOC_REG_INT_XTHOL_BCM88270_A0r */
  85594         soc_block_list[56],
  85595         soc_portreg,
  85596         1,
  85597         0,
  85598         0x7000,
  85599         SOC_REG_FLAG_64_BITS |
  85600                           SOC_REG_FLAG_COUNTER,
  85601         0,
  85602         1,
  85603         soc_XTHOL_BCM88270_A0r_fields,
  85604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85605         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85606         112,
  85607         -1,
  85608     },
  85609 #endif /* chips */
  85610 
  85611 #if defined(BCM_88375_A0)
  85612     { /* SOC_REG_INT_XTHOL_BCM88375_A0r */
  85613         soc_block_list[211],
  85614         soc_portreg,
  85615         1,
  85616         0,
  85617         0x7000,
  85618         SOC_REG_FLAG_64_BITS |
  85619                           SOC_REG_FLAG_COUNTER,
  85620         0,
  85621         1,
  85622         soc_XTHOL_BCM88375_A0r_fields,
  85623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85624         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85625         112,
  85626         -1,
  85627     },
  85628 #endif /* chips */
  85629 
  85630 #if defined(BCM_88375_B0)
  85631     { /* SOC_REG_INT_XTHOL_BCM88375_B0r */
  85632         soc_block_list[211],
  85633         soc_portreg,
  85634         1,
  85635         0,
  85636         0x7000,
  85637         SOC_REG_FLAG_64_BITS |
  85638                           SOC_REG_FLAG_COUNTER,
  85639         0,
  85640         1,
  85641         soc_XTHOL_BCM88375_B0r_fields,
  85642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85643         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85644         112,
  85645         -1,
  85646     },
  85647 #endif /* chips */
  85648 
  85649 #if defined(BCM_88470_A0)
  85650     { /* SOC_REG_INT_XTHOL_BCM88470_A0r */
  85651         soc_block_list[211],
  85652         soc_portreg,
  85653         1,
  85654         0,
  85655         0x7000,
  85656         SOC_REG_FLAG_64_BITS |
  85657                           SOC_REG_FLAG_COUNTER,
  85658         0,
  85659         1,
  85660         soc_XTHOL_BCM88470_A0r_fields,
  85661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85662         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85663         112,
  85664         -1,
  85665     },
  85666 #endif /* chips */
  85667 
  85668 #if defined(BCM_88470_B0)
  85669     { /* SOC_REG_INT_XTHOL_BCM88470_B0r */
  85670         soc_block_list[211],
  85671         soc_portreg,
  85672         1,
  85673         0,
  85674         0x7000,
  85675         SOC_REG_FLAG_64_BITS |
  85676                           SOC_REG_FLAG_COUNTER,
  85677         0,
  85678         1,
  85679         soc_XTHOL_BCM88470_B0r_fields,
  85680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85681         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85682         112,
  85683         -1,
  85684     },
  85685 #endif /* chips */
  85686 
  85687 #if defined(BCM_88675_A0)
  85688     { /* SOC_REG_INT_XTHOL_BCM88675_A0r */
  85689         soc_block_list[211],
  85690         soc_portreg,
  85691         1,
  85692         0,
  85693         0x7000,
  85694         SOC_REG_FLAG_64_BITS |
  85695                           SOC_REG_FLAG_COUNTER,
  85696         0,
  85697         1,
  85698         soc_XTHOL_BCM88675_A0r_fields,
  85699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85700         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85701         112,
  85702         -1,
  85703     },
  85704 #endif /* chips */
  85705 
  85706 #if defined(BCM_88675_B0)
  85707     { /* SOC_REG_INT_XTHOL_BCM88675_B0r */
  85708         soc_block_list[211],
  85709         soc_portreg,
  85710         1,
  85711         0,
  85712         0x7000,
  85713         SOC_REG_FLAG_64_BITS |
  85714                           SOC_REG_FLAG_COUNTER,
  85715         0,
  85716         1,
  85717         soc_XTHOL_BCM88675_B0r_fields,
  85718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85719         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85720         112,
  85721         -1,
  85722     },
  85723 #endif /* chips */
  85724 
  85725 #if defined(BCM_88680_A0)
  85726     { /* SOC_REG_INT_XTHOL_BCM88680_A0r */
  85727         soc_block_list[211],
  85728         soc_portreg,
  85729         1,
  85730         0,
  85731         0x7000,
  85732         SOC_REG_FLAG_64_BITS |
  85733                           SOC_REG_FLAG_COUNTER,
  85734         0,
  85735         1,
  85736         soc_XTHOL_BCM88680_A0r_fields,
  85737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85738         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  85739         112,
  85740         -1,
  85741     },
  85742 #endif /* chips */
  85743 
  85744 #if defined(BCM_88732_A0)
  85745     { /* SOC_REG_INT_XTHOL_BCM88732_A0r */
  85746         soc_block_list[16],
  85747         soc_portreg,
  85748         1,
  85749         0,
  85750         0x21d,
  85751         0,
  85752         0,
  85753         1,
  85754         soc_XTHOLr_fields,
  85755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85757         -1,
  85758         -1,
  85759     },
  85760 #endif /* chips */
  85761 
  85762 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  85763     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  85764     { /* SOC_REG_INT_XTIBPr */
  85765         soc_block_list[0],
  85766         soc_portreg,
  85767         1,
  85768         0,
  85769         0x102,
  85770         0,
  85771         0,
  85772         1,
  85773         soc_XTHOLr_fields,
  85774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85775         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85776         -1,
  85777         -1,
  85778     },
  85779 #endif /* chips */
  85780 
  85781 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  85782     defined(BCM_56334_B0)
  85783     { /* SOC_REG_INT_XTIBP_BCM56334_A0r */
  85784         soc_block_list[14],
  85785         soc_portreg,
  85786         1,
  85787         0,
  85788         0x826,
  85789         0,
  85790         0,
  85791         1,
  85792         soc_XTHOLr_fields,
  85793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85794         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85795         -1,
  85796         -1,
  85797     },
  85798 #endif /* chips */
  85799 
  85800 #if defined(BCM_56340_A0)
  85801     { /* SOC_REG_INT_XTIBP_BCM56340_A0r */
  85802         soc_block_list[214],
  85803         soc_portreg,
  85804         1,
  85805         0,
  85806         0x21b00,
  85807         0,
  85808         0,
  85809         1,
  85810         soc_AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr_fields,
  85811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85812         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85813         -1,
  85814         -1,
  85815     },
  85816 #endif /* chips */
  85817 
  85818 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  85819     { /* SOC_REG_INT_XTIBP_BCM56440_A0r */
  85820         soc_block_list[83],
  85821         soc_portreg,
  85822         1,
  85823         0,
  85824         0x216,
  85825         0,
  85826         0,
  85827         1,
  85828         soc_XTHOLr_fields,
  85829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85830         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85831         -1,
  85832         -1,
  85833     },
  85834 #endif /* chips */
  85835 
  85836 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  85837     defined(BCM_56450_B1)
  85838     { /* SOC_REG_INT_XTIBP_BCM56450_A0r */
  85839         soc_block_list[83],
  85840         soc_portreg,
  85841         1,
  85842         0,
  85843         0x21600,
  85844         0,
  85845         0,
  85846         1,
  85847         soc_AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr_fields,
  85848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85849         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85850         -1,
  85851         -1,
  85852     },
  85853 #endif /* chips */
  85854 
  85855 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  85856     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  85857     { /* SOC_REG_INT_XTIBP_BCM56624_A0r */
  85858         soc_block_list[204],
  85859         soc_portreg,
  85860         1,
  85861         0,
  85862         0x826,
  85863         0,
  85864         0,
  85865         1,
  85866         soc_XTHOLr_fields,
  85867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85868         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85869         -1,
  85870         -1,
  85871     },
  85872 #endif /* chips */
  85873 
  85874 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  85875     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  85876     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  85877     { /* SOC_REG_INT_XTIBP_BCM56634_A0r */
  85878         soc_block_list[208],
  85879         soc_portreg,
  85880         1,
  85881         0,
  85882         0x826,
  85883         0,
  85884         0,
  85885         1,
  85886         soc_XTHOLr_fields,
  85887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85889         -1,
  85890         -1,
  85891     },
  85892 #endif /* chips */
  85893 
  85894 #if defined(BCM_56640_A0)
  85895     { /* SOC_REG_INT_XTIBP_BCM56640_A0r */
  85896         soc_block_list[212],
  85897         soc_portreg,
  85898         1,
  85899         0,
  85900         0x21b00,
  85901         0,
  85902         0,
  85903         1,
  85904         soc_AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr_fields,
  85905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85906         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85907         -1,
  85908         -1,
  85909     },
  85910 #endif /* chips */
  85911 
  85912 #if defined(BCM_56800_A0)
  85913     { /* SOC_REG_INT_XTIBP_BCM56800_A0r */
  85914         soc_block_list[9],
  85915         soc_portreg,
  85916         1,
  85917         0,
  85918         0x902,
  85919         0,
  85920         0,
  85921         1,
  85922         soc_XTHOLr_fields,
  85923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85924         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85925         -1,
  85926         -1,
  85927     },
  85928 #endif /* chips */
  85929 
  85930 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  85931     { /* SOC_REG_INT_XTIBP_BCM56820_A0r */
  85932         soc_block_list[9],
  85933         soc_portreg,
  85934         1,
  85935         0,
  85936         0x826,
  85937         0,
  85938         0,
  85939         1,
  85940         soc_XTHOLr_fields,
  85941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85942         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85943         -1,
  85944         -1,
  85945     },
  85946 #endif /* chips */
  85947 
  85948 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  85949     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  85950     { /* SOC_REG_INT_XTPSEr */
  85951         soc_block_list[0],
  85952         soc_portreg,
  85953         1,
  85954         0,
  85955         0x100,
  85956         0,
  85957         0,
  85958         1,
  85959         soc_XTHOLr_fields,
  85960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85961         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85962         -1,
  85963         -1,
  85964     },
  85965 #endif /* chips */
  85966 
  85967 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  85968     defined(BCM_56334_B0)
  85969     { /* SOC_REG_INT_XTPSE_BCM56334_A0r */
  85970         soc_block_list[14],
  85971         soc_portreg,
  85972         1,
  85973         0,
  85974         0x824,
  85975         0,
  85976         0,
  85977         1,
  85978         soc_XTHOLr_fields,
  85979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85980         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85981         -1,
  85982         -1,
  85983     },
  85984 #endif /* chips */
  85985 
  85986 #if defined(BCM_56340_A0)
  85987     { /* SOC_REG_INT_XTPSE_BCM56340_A0r */
  85988         soc_block_list[214],
  85989         soc_portreg,
  85990         1,
  85991         0,
  85992         0x21900,
  85993         0,
  85994         0,
  85995         1,
  85996         soc_AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr_fields,
  85997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85998         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  85999         -1,
  86000         -1,
  86001     },
  86002 #endif /* chips */
  86003 
  86004 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  86005     { /* SOC_REG_INT_XTPSE_BCM56440_A0r */
  86006         soc_block_list[83],
  86007         soc_portreg,
  86008         1,
  86009         0,
  86010         0x214,
  86011         0,
  86012         0,
  86013         1,
  86014         soc_XTHOLr_fields,
  86015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86016         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  86017         -1,
  86018         -1,
  86019     },
  86020 #endif /* chips */
  86021 
  86022 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  86023     defined(BCM_56450_B1)
  86024     { /* SOC_REG_INT_XTPSE_BCM56450_A0r */
  86025         soc_block_list[83],
  86026         soc_portreg,
  86027         1,
  86028         0,
  86029         0x21400,
  86030         0,
  86031         0,
  86032         1,
  86033         soc_AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr_fields,
  86034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86035         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  86036         -1,
  86037         -1,
  86038     },
  86039 #endif /* chips */
  86040 
  86041 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  86042     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  86043     { /* SOC_REG_INT_XTPSE_BCM56624_A0r */
  86044         soc_block_list[204],
  86045         soc_portreg,
  86046         1,
  86047         0,
  86048         0x824,
  86049         0,
  86050         0,
  86051         1,
  86052         soc_XTHOLr_fields,
  86053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86054         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  86055         -1,
  86056         -1,
  86057     },
  86058 #endif /* chips */
  86059 
  86060 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  86061     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  86062     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  86063     { /* SOC_REG_INT_XTPSE_BCM56634_A0r */
  86064         soc_block_list[208],
  86065         soc_portreg,
  86066         1,
  86067         0,
  86068         0x824,
  86069         0,
  86070         0,
  86071         1,
  86072         soc_XTHOLr_fields,
  86073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86074         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  86075         -1,
  86076         -1,
  86077     },
  86078 #endif /* chips */
  86079 
  86080 #if defined(BCM_56640_A0)
  86081     { /* SOC_REG_INT_XTPSE_BCM56640_A0r */
  86082         soc_block_list[212],
  86083         soc_portreg,
  86084         1,
  86085         0,
  86086         0x21900,
  86087         0,
  86088         0,
  86089         1,
  86090         soc_AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr_fields,
  86091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86092         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  86093         -1,
  86094         -1,
  86095     },
  86096 #endif /* chips */
  86097 
  86098 #if defined(BCM_56800_A0)
  86099     { /* SOC_REG_INT_XTPSE_BCM56800_A0r */
  86100         soc_block_list[9],
  86101         soc_portreg,
  86102         1,
  86103         0,
  86104         0x900,
  86105         0,
  86106         0,
  86107         1,
  86108         soc_XTHOLr_fields,
  86109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86110         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  86111         -1,
  86112         -1,
  86113     },
  86114 #endif /* chips */
  86115 
  86116 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  86117     { /* SOC_REG_INT_XTPSE_BCM56820_A0r */
  86118         soc_block_list[9],
  86119         soc_portreg,
  86120         1,
  86121         0,
  86122         0x824,
  86123         0,
  86124         0,
  86125         1,
  86126         soc_XTHOLr_fields,
  86127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86128         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  86129         -1,
  86130         -1,
  86131     },
  86132 #endif /* chips */
  86133 
  86134 #if defined(BCM_56840_A0)
  86135     { /* SOC_REG_INT_XTPSE_BCM56840_A0r */
  86136         soc_block_list[16],
  86137         soc_portreg,
  86138         1,
  86139         0,
  86140         0x21c,
  86141         0,
  86142         0,
  86143         1,
  86144         soc_XTHOLr_fields,
  86145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86146         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  86147         -1,
  86148         -1,
  86149     },
  86150 #endif /* chips */
  86151 
  86152 #if defined(BCM_56840_B0)
  86153     { /* SOC_REG_INT_XTPSE_BCM56840_B0r */
  86154         soc_block_list[16],
  86155         soc_portreg,
  86156         1,
  86157         0,
  86158         0x21c,
  86159         0,
  86160         0,
  86161         1,
  86162         soc_XTHOLr_fields,
  86163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86164         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  86165         -1,
  86166         -1,
  86167     },
  86168 #endif /* chips */
  86169 
  86170 #if defined(BCM_88732_A0)
  86171     { /* SOC_REG_INT_XTPSE_BCM88732_A0r */
  86172         soc_block_list[16],
  86173         soc_portreg,
  86174         1,
  86175         0,
  86176         0x21c,
  86177         0,
  86178         0,
  86179         1,
  86180         soc_XTHOLr_fields,
  86181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86182         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  86183         -1,
  86184         -1,
  86185     },
  86186 #endif /* chips */
  86187 
  86188 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  86189     { /* SOC_REG_INT_X_CPU_SLOT_COUNTr */
  86190         soc_block_list[4],
  86191         soc_genreg,
  86192         1,
  86193         0,
  86194         0x6080100,
  86195         0,
  86196         0,
  86197         2,
  86198         soc_X_CPU_SLOT_COUNTr_fields,
  86199         SOC_RESET_VAL_DEC(0x00000900, 0x00000000)
  86200         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  86201         -1,
  86202         -1,
  86203     },
  86204 #endif /* chips */
  86205 
  86206 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  86207     { /* SOC_REG_INT_X_GPORT_CNTMAXSIZEr */
  86208         soc_block_list[83],
  86209         soc_portreg,
  86210         1,
  86211         0,
  86212         0x21d,
  86213         0,
  86214         0,
  86215         1,
  86216         soc_GPORT_CNTMAXSIZEr_fields,
  86217         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  86218         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  86219         -1,
  86220         -1,
  86221     },
  86222 #endif /* chips */
  86223 
  86224 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  86225     { /* SOC_REG_INT_X_GPORT_CNTMAXSIZE_BCM56260_A0r */
  86226         soc_block_list[83],
  86227         soc_portreg,
  86228         1,
  86229         0,
  86230         0x20800,
  86231         0,
  86232         0,
  86233         1,
  86234         soc_CLPORT_CNTMAXSIZEr_fields,
  86235         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  86236         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  86237         -1,
  86238         -1,
  86239     },
  86240 #endif /* chips */
  86241 
  86242 #if defined(BCM_56270_A0)
  86243     { /* SOC_REG_INT_X_GPORT_CNTMAXSIZE_BCM56270_A0r */
  86244         soc_block_list[83],
  86245         soc_portreg,
  86246         1,
  86247         0,
  86248         0x20800,
  86249         0,
  86250         0,
  86251         1,
  86252         soc_CLPORT_CNTMAXSIZEr_fields,
  86253         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  86254         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  86255         -1,
  86256         -1,
  86257     },
  86258 #endif /* chips */
  86259 
  86260 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  86261     defined(BCM_56450_B1)
  86262     { /* SOC_REG_INT_X_GPORT_CNTMAXSIZE_BCM56450_A0r */
  86263         soc_block_list[83],
  86264         soc_portreg,
  86265         1,
  86266         0,
  86267         0x21d00,
  86268         0,
  86269         0,
  86270         1,
  86271         soc_PORT_CNTMAXSIZE_BCM56640_A0r_fields,
  86272         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  86273         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  86274         -1,
  86275         -1,
  86276     },
  86277 #endif /* chips */
  86278 
  86279 #if defined(BCM_88270_A0)
  86280     { /* SOC_REG_INT_X_GPORT_CNTMAXSIZE_BCM88270_A0r */
  86281         soc_block_list[149],
  86282         soc_portreg,
  86283         1,
  86284         0,
  86285         0x20400,
  86286         0,
  86287         0,
  86288         1,
  86289         soc_X_GPORT_CNTMAXSIZEr_fields,
  86290         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  86291         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  86292         -1,
  86293         -1,
  86294     },
  86295 #endif /* chips */
  86296 
  86297 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  86298     { /* SOC_REG_INT_X_GPORT_CONFIGr */
  86299         soc_block_list[83],
  86300         soc_portreg,
  86301         1,
  86302         0,
  86303         0x21c,
  86304         0,
  86305         0,
  86306         1,
  86307         soc_GPORT_CONFIG_BCM56840_A0r_fields,
  86308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86309         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86310         -1,
  86311         -1,
  86312     },
  86313 #endif /* chips */
  86314 
  86315 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  86316     defined(BCM_56450_B1)
  86317     { /* SOC_REG_INT_X_GPORT_CONFIG_BCM56450_A0r */
  86318         soc_block_list[83],
  86319         soc_portreg,
  86320         1,
  86321         0,
  86322         0x21c00,
  86323         0,
  86324         0,
  86325         1,
  86326         soc_X_GPORT_CONFIGr_fields,
  86327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86328         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  86329         -1,
  86330         -1,
  86331     },
  86332 #endif /* chips */
  86333 
  86334 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  86335     { /* SOC_REG_INT_X_GPORT_SGNDET_EARLYCRSr */
  86336         soc_block_list[83],
  86337         soc_portreg,
  86338         1,
  86339         0,
  86340         0x21e,
  86341         0,
  86342         0,
  86343         2,
  86344         soc_GPORT_SGNDET_EARLYCRSr_fields,
  86345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86346         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  86347         -1,
  86348         -1,
  86349     },
  86350 #endif /* chips */
  86351 
  86352 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  86353     { /* SOC_REG_INT_X_GPORT_SGNDET_EARLYCRS_BCM56260_A0r */
  86354         soc_block_list[83],
  86355         soc_portreg,
  86356         1,
  86357         0,
  86358         0x20900,
  86359         0,
  86360         0,
  86361         1,
  86362         soc_CLPORT_SGNDET_EARLYCRSr_fields,
  86363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86364         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  86365         -1,
  86366         -1,
  86367     },
  86368 #endif /* chips */
  86369 
  86370 #if defined(BCM_56270_A0)
  86371     { /* SOC_REG_INT_X_GPORT_SGNDET_EARLYCRS_BCM56270_A0r */
  86372         soc_block_list[83],
  86373         soc_portreg,
  86374         1,
  86375         0,
  86376         0x20900,
  86377         0,
  86378         0,
  86379         1,
  86380         soc_CLPORT_SGNDET_EARLYCRSr_fields,
  86381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86382         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  86383         -1,
  86384         -1,
  86385     },
  86386 #endif /* chips */
  86387 
  86388 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  86389     defined(BCM_56450_B1)
  86390     { /* SOC_REG_INT_X_GPORT_SGNDET_EARLYCRS_BCM56450_A0r */
  86391         soc_block_list[83],
  86392         soc_portreg,
  86393         1,
  86394         0,
  86395         0x21e00,
  86396         0,
  86397         0,
  86398         2,
  86399         soc_X_GPORT_SGNDET_EARLYCRSr_fields,
  86400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86401         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  86402         -1,
  86403         -1,
  86404     },
  86405 #endif /* chips */
  86406 
  86407 #if defined(BCM_88270_A0)
  86408     { /* SOC_REG_INT_X_GPORT_SGNDET_EARLYCRS_BCM88270_A0r */
  86409         soc_block_list[149],
  86410         soc_portreg,
  86411         1,
  86412         0,
  86413         0x20500,
  86414         0,
  86415         0,
  86416         1,
  86417         soc_X_GPORT_SGNDET_EARLYCRS_BCM88270_A0r_fields,
  86418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86419         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  86420         -1,
  86421         -1,
  86422     },
  86423 #endif /* chips */
  86424 
  86425 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  86426     { /* SOC_REG_INT_X_TDM_ENr */
  86427         soc_block_list[4],
  86428         soc_genreg,
  86429         1,
  86430         0,
  86431         0x6080110,
  86432         0,
  86433         0,
  86434         1,
  86435         soc_E2E_HOL_ENr_fields,
  86436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  86437         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  86438         -1,
  86439         -1,
  86440     },
  86441 #endif /* chips */
  86442