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allregs_w.i (331038B)

      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_w.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
     16     { /* SOC_REG_INT_WAMUCELLCNTPGr */
     17         soc_block_list[4],
     18         soc_genreg,
     19         2,
     20         0,
     21         0x8a004800,
     22         SOC_REG_FLAG_ARRAY |
     23                           SOC_REG_FLAG_RO,
     24         0,
     25         2,
     26         soc_RDECELLCNTINGr_fields,
     27         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     28         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
     29         -1,
     30         -1,
     31     },
     32 #endif /* chips */
     33 
     34 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
     35     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
     36     defined(BCM_56685_A0) || defined(BCM_56685_B0)
     37     { /* SOC_REG_INT_WAMUDROPCNT2BERRr */
     38         soc_block_list[4],
     39         soc_genreg,
     40         1,
     41         0,
     42         0x2208000b,
     43         0,
     44         0,
     45         1,
     46         soc_WAMUDROPCNT2BERRr_fields,
     47         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     48         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
     49         -1,
     50         -1,
     51     },
     52 #endif /* chips */
     53 
     54 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
     55     { /* SOC_REG_INT_WAMUDROPCNT2BERR_BCM56640_A0r */
     56         soc_block_list[4],
     57         soc_genreg,
     58         1,
     59         0,
     60         0x8a000b00,
     61         0,
     62         0,
     63         1,
     64         soc_WAMUDROPCNT2BERR_BCM56640_A0r_fields,
     65         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     66         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
     67         -1,
     68         -1,
     69     },
     70 #endif /* chips */
     71 
     72 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
     73     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
     74     defined(BCM_56685_A0) || defined(BCM_56685_B0)
     75     { /* SOC_REG_INT_WAMUDROPCNTAGINGr */
     76         soc_block_list[4],
     77         soc_genreg,
     78         1,
     79         0,
     80         0x2208000a,
     81         0,
     82         0,
     83         1,
     84         soc_WAMUDROPCNTAGINGr_fields,
     85         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     86         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
     87         -1,
     88         -1,
     89     },
     90 #endif /* chips */
     91 
     92 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
     93     { /* SOC_REG_INT_WAMUDROPCNTAGING_BCM56640_A0r */
     94         soc_block_list[4],
     95         soc_genreg,
     96         1,
     97         0,
     98         0x8a000a00,
     99         0,
    100         0,
    101         1,
    102         soc_WAMUDROPCNTAGING_BCM56640_A0r_fields,
    103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    104         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    105         -1,
    106         -1,
    107     },
    108 #endif /* chips */
    109 
    110 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    111     { /* SOC_REG_INT_WAMUDROPCNTGLBTHDIPKTr */
    112         soc_block_list[4],
    113         soc_genreg,
    114         1,
    115         0,
    116         0x8a00b100,
    117         0,
    118         0,
    119         1,
    120         soc_WAMUDROPCNTGLBTHDIPKTr_fields,
    121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    122         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    123         -1,
    124         -1,
    125     },
    126 #endif /* chips */
    127 
    128 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    129     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    130     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    131     { /* SOC_REG_INT_WAMUDROPCNTLENr */
    132         soc_block_list[4],
    133         soc_genreg,
    134         1,
    135         0,
    136         0x22080008,
    137         0,
    138         0,
    139         1,
    140         soc_WAMUDROPCNTLENr_fields,
    141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    142         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    143         -1,
    144         -1,
    145     },
    146 #endif /* chips */
    147 
    148 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    149     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    150     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    151     { /* SOC_REG_INT_WAMUDROPCNTLENBYTEr */
    152         soc_block_list[4],
    153         soc_genreg,
    154         1,
    155         0,
    156         0x22080017,
    157         0,
    158         0,
    159         1,
    160         soc_WAMUDROPCNTLENBYTEr_fields,
    161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    162         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    163         -1,
    164         -1,
    165     },
    166 #endif /* chips */
    167 
    168 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    169     { /* SOC_REG_INT_WAMUDROPCNTLENBYTE_BCM56640_A0r */
    170         soc_block_list[4],
    171         soc_genreg,
    172         1,
    173         0,
    174         0x8a001700,
    175         0,
    176         0,
    177         1,
    178         soc_WAMUDROPCNTLENBYTE_BCM56640_A0r_fields,
    179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    180         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    181         -1,
    182         -1,
    183     },
    184 #endif /* chips */
    185 
    186 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    187     { /* SOC_REG_INT_WAMUDROPCNTLEN_BCM56640_A0r */
    188         soc_block_list[4],
    189         soc_genreg,
    190         1,
    191         0,
    192         0x8a000800,
    193         0,
    194         0,
    195         1,
    196         soc_WAMUDROPCNTLEN_BCM56640_A0r_fields,
    197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    198         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    199         -1,
    200         -1,
    201     },
    202 #endif /* chips */
    203 
    204 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    205     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    206     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    207     { /* SOC_REG_INT_WAMUDROPCNTLRUr */
    208         soc_block_list[4],
    209         soc_genreg,
    210         1,
    211         0,
    212         0x2208000c,
    213         0,
    214         0,
    215         1,
    216         soc_WAMUDROPCNTLRUr_fields,
    217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    218         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    219         -1,
    220         -1,
    221     },
    222 #endif /* chips */
    223 
    224 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    225     { /* SOC_REG_INT_WAMUDROPCNTLRU_BCM56640_A0r */
    226         soc_block_list[4],
    227         soc_genreg,
    228         1,
    229         0,
    230         0x8a000c00,
    231         0,
    232         0,
    233         1,
    234         soc_WAMUDROPCNTLRU_BCM56640_A0r_fields,
    235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    236         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    237         -1,
    238         -1,
    239     },
    240 #endif /* chips */
    241 
    242 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    243     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    244     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    245     { /* SOC_REG_INT_WAMUDROPCNTNOLRUr */
    246         soc_block_list[4],
    247         soc_genreg,
    248         1,
    249         0,
    250         0x2208000d,
    251         0,
    252         0,
    253         1,
    254         soc_WAMUDROPCNTNOLRUr_fields,
    255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    256         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    257         -1,
    258         -1,
    259     },
    260 #endif /* chips */
    261 
    262 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    263     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    264     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    265     { /* SOC_REG_INT_WAMUDROPCNTNOLRUBYTEr */
    266         soc_block_list[4],
    267         soc_genreg,
    268         1,
    269         0,
    270         0x22080018,
    271         0,
    272         0,
    273         1,
    274         soc_WAMUDROPCNTNOLRUBYTEr_fields,
    275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    276         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    277         -1,
    278         -1,
    279     },
    280 #endif /* chips */
    281 
    282 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    283     { /* SOC_REG_INT_WAMUDROPCNTNOLRUBYTE_BCM56640_A0r */
    284         soc_block_list[4],
    285         soc_genreg,
    286         1,
    287         0,
    288         0x8a001800,
    289         0,
    290         0,
    291         1,
    292         soc_WAMUDROPCNTNOLRUBYTE_BCM56640_A0r_fields,
    293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    294         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    295         -1,
    296         -1,
    297     },
    298 #endif /* chips */
    299 
    300 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    301     { /* SOC_REG_INT_WAMUDROPCNTNOLRU_BCM56640_A0r */
    302         soc_block_list[4],
    303         soc_genreg,
    304         1,
    305         0,
    306         0x8a000d00,
    307         0,
    308         0,
    309         1,
    310         soc_WAMUDROPCNTNOLRU_BCM56640_A0r_fields,
    311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    312         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    313         -1,
    314         -1,
    315     },
    316 #endif /* chips */
    317 
    318 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    319     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    320     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    321     { /* SOC_REG_INT_WAMUDROPCNTTHDr */
    322         soc_block_list[4],
    323         soc_genreg,
    324         1,
    325         0,
    326         0x22080004,
    327         0,
    328         0,
    329         1,
    330         soc_WAMUDROPCNTTHDr_fields,
    331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    333         -1,
    334         -1,
    335     },
    336 #endif /* chips */
    337 
    338 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    339     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    340     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    341     { /* SOC_REG_INT_WAMUDROPCNTTHDBYTEr */
    342         soc_block_list[4],
    343         soc_genreg,
    344         1,
    345         0,
    346         0x22080016,
    347         0,
    348         0,
    349         1,
    350         soc_WAMUDROPCNTTHDBYTEr_fields,
    351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    352         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    353         -1,
    354         -1,
    355     },
    356 #endif /* chips */
    357 
    358 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    359     { /* SOC_REG_INT_WAMUDROPCNTTHDIBYTEr */
    360         soc_block_list[4],
    361         soc_genreg,
    362         1,
    363         0,
    364         0x8a00b200,
    365         0,
    366         0,
    367         1,
    368         soc_RDETHDODROPr_fields,
    369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    370         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    371         -1,
    372         -1,
    373     },
    374 #endif /* chips */
    375 
    376 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    377     { /* SOC_REG_INT_WAMUDROPCNTTHDIPKTr */
    378         soc_block_list[4],
    379         soc_genreg,
    380         1,
    381         0,
    382         0x8a00b000,
    383         0,
    384         0,
    385         1,
    386         soc_WAMUDROPCNTGLBTHDIPKTr_fields,
    387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    388         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    389         -1,
    390         -1,
    391     },
    392 #endif /* chips */
    393 
    394 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    395     { /* SOC_REG_INT_WAMUDROPCNTTHDOBYTEr */
    396         soc_block_list[4],
    397         soc_genreg,
    398         8,
    399         0,
    400         0x8a00c000,
    401         SOC_REG_FLAG_ARRAY,
    402         0,
    403         1,
    404         soc_RDETHDODROPr_fields,
    405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    406         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    407         -1,
    408         -1,
    409     },
    410 #endif /* chips */
    411 
    412 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    413     { /* SOC_REG_INT_WAMUDROPCNTTHDOPKTr */
    414         soc_block_list[4],
    415         soc_genreg,
    416         8,
    417         0,
    418         0x8a00b300,
    419         SOC_REG_FLAG_ARRAY,
    420         0,
    421         1,
    422         soc_WAMUDROPCNTGLBTHDIPKTr_fields,
    423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    424         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    425         -1,
    426         -1,
    427     },
    428 #endif /* chips */
    429 
    430 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    431     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    432     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    433     { /* SOC_REG_INT_WAMUDROPCNTTYPEr */
    434         soc_block_list[4],
    435         soc_genreg,
    436         1,
    437         0,
    438         0x22080006,
    439         0,
    440         0,
    441         1,
    442         soc_WAMUDROPCNTTYPEr_fields,
    443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    444         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    445         -1,
    446         -1,
    447     },
    448 #endif /* chips */
    449 
    450 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    451     { /* SOC_REG_INT_WAMUDROPCNTTYPE_BCM56640_A0r */
    452         soc_block_list[4],
    453         soc_genreg,
    454         1,
    455         0,
    456         0x8a000600,
    457         0,
    458         0,
    459         1,
    460         soc_WAMUDROPCNTTYPE_BCM56640_A0r_fields,
    461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    462         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    463         -1,
    464         -1,
    465     },
    466 #endif /* chips */
    467 
    468 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    469     { /* SOC_REG_INT_WAMULINKMEMDEBUGr */
    470         soc_block_list[4],
    471         soc_genreg,
    472         1,
    473         0,
    474         0x12002200,
    475         0,
    476         0,
    477         3,
    478         soc_CELLLINKMEMDEBUG_BCM56640_A0r_fields,
    479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    480         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    481         -1,
    482         -1,
    483     },
    484 #endif /* chips */
    485 
    486 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    487     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    488     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    489     { /* SOC_REG_INT_WAMUMEMDEBUGr */
    490         soc_block_list[4],
    491         soc_genreg,
    492         1,
    493         0,
    494         0x22080002,
    495         0,
    496         0,
    497         4,
    498         soc_WAMUMEMDEBUGr_fields,
    499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    500         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    501         -1,
    502         -1,
    503     },
    504 #endif /* chips */
    505 
    506 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    507     { /* SOC_REG_INT_WAMUMEMDEBUG_BCM56640_A0r */
    508         soc_block_list[4],
    509         soc_genreg,
    510         1,
    511         0,
    512         0x8a000200,
    513         SOC_REG_FLAG_64_BITS,
    514         0,
    515         4,
    516         soc_WAMUMEMDEBUG_BCM56640_A0r_fields,
    517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    518         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    519         -1,
    520         -1,
    521     },
    522 #endif /* chips */
    523 
    524 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    525     { /* SOC_REG_INT_WAMUMINLMTPGr */
    526         soc_block_list[4],
    527         soc_genreg,
    528         2,
    529         0,
    530         0x8a003200,
    531         SOC_REG_FLAG_ARRAY,
    532         0,
    533         2,
    534         soc_WAMUMINLMTPGr_fields,
    535         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
    536         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
    537         -1,
    538         -1,
    539     },
    540 #endif /* chips */
    541 
    542 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    543     { /* SOC_REG_INT_WAMUMINLMTPKTQr */
    544         soc_block_list[4],
    545         soc_genreg,
    546         8,
    547         0,
    548         0x8a004c00,
    549         SOC_REG_FLAG_ARRAY,
    550         0,
    551         1,
    552         soc_WAMUMINLMTPKTQr_fields,
    553         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
    554         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    555         -1,
    556         -1,
    557     },
    558 #endif /* chips */
    559 
    560 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    561     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    562     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    563     { /* SOC_REG_INT_WAMUNONFRAGMCNTr */
    564         soc_block_list[4],
    565         soc_genreg,
    566         1,
    567         0,
    568         0x2208000f,
    569         0,
    570         0,
    571         1,
    572         soc_WAMUNONFRAGMCNTr_fields,
    573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    574         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    575         -1,
    576         -1,
    577     },
    578 #endif /* chips */
    579 
    580 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    581     { /* SOC_REG_INT_WAMUNONFRAGMCNT_BCM56640_A0r */
    582         soc_block_list[4],
    583         soc_genreg,
    584         1,
    585         0,
    586         0x8a000f00,
    587         0,
    588         0,
    589         1,
    590         soc_WAMUNONFRAGMCNT_BCM56640_A0r_fields,
    591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    592         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    593         -1,
    594         -1,
    595     },
    596 #endif /* chips */
    597 
    598 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    599     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    600     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    601     { /* SOC_REG_INT_WAMUPARITYERRADRr */
    602         soc_block_list[4],
    603         soc_genreg,
    604         1,
    605         0,
    606         0x22080010,
    607         SOC_REG_FLAG_RO,
    608         0,
    609         1,
    610         soc_WAMUPARITYERRADRr_fields,
    611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    612         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
    613         -1,
    614         -1,
    615     },
    616 #endif /* chips */
    617 
    618 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    619     { /* SOC_REG_INT_WAMUPARITYERRADR_BCM56640_A0r */
    620         soc_block_list[4],
    621         soc_genreg,
    622         1,
    623         0,
    624         0x8a001000,
    625         SOC_REG_FLAG_RO,
    626         0,
    627         1,
    628         soc_WAMUPARITYERRADR_BCM56640_A0r_fields,
    629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    630         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    631         -1,
    632         -1,
    633     },
    634 #endif /* chips */
    635 
    636 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    637     { /* SOC_REG_INT_WAMUPKTCNTPGr */
    638         soc_block_list[4],
    639         soc_genreg,
    640         2,
    641         0,
    642         0x8a004500,
    643         SOC_REG_FLAG_ARRAY |
    644                           SOC_REG_FLAG_RO,
    645         0,
    646         2,
    647         soc_WAMUPKTCNTPGr_fields,
    648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    649         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
    650         -1,
    651         -1,
    652     },
    653 #endif /* chips */
    654 
    655 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    656     { /* SOC_REG_INT_WAMUPKTCNTQr */
    657         soc_block_list[4],
    658         soc_genreg,
    659         8,
    660         0,
    661         0x8a008000,
    662         SOC_REG_FLAG_ARRAY |
    663                           SOC_REG_FLAG_RO,
    664         0,
    665         2,
    666         soc_WAMUPKTCNTPGr_fields,
    667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    668         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
    669         -1,
    670         -1,
    671     },
    672 #endif /* chips */
    673 
    674 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    675     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    676     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    677     { /* SOC_REG_INT_WAMUREASMBCNTr */
    678         soc_block_list[4],
    679         soc_genreg,
    680         1,
    681         0,
    682         0x2208000e,
    683         0,
    684         0,
    685         1,
    686         soc_WAMUREASMBCNTr_fields,
    687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    689         -1,
    690         -1,
    691     },
    692 #endif /* chips */
    693 
    694 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    695     { /* SOC_REG_INT_WAMUREASMBCNT_BCM56640_A0r */
    696         soc_block_list[4],
    697         soc_genreg,
    698         1,
    699         0,
    700         0x8a000e00,
    701         0,
    702         0,
    703         1,
    704         soc_WAMUREASMBCNT_BCM56640_A0r_fields,
    705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    706         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    707         -1,
    708         -1,
    709     },
    710 #endif /* chips */
    711 
    712 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    713     { /* SOC_REG_INT_WAMURSTOFFSETCELLPGr */
    714         soc_block_list[4],
    715         soc_genreg,
    716         2,
    717         0,
    718         0x8a004000,
    719         SOC_REG_FLAG_ARRAY,
    720         0,
    721         2,
    722         soc_RDERSTOFFSETCELLINGr_fields,
    723         SOC_RESET_VAL_DEC(0x0004001f, 0x00000000)
    724         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
    725         -1,
    726         -1,
    727     },
    728 #endif /* chips */
    729 
    730 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    731     { /* SOC_REG_INT_WAMURSTOFFSETPKTPGr */
    732         soc_block_list[4],
    733         soc_genreg,
    734         2,
    735         0,
    736         0x8a003d00,
    737         SOC_REG_FLAG_ARRAY,
    738         0,
    739         2,
    740         soc_WAMURSTOFFSETPKTPGr_fields,
    741         SOC_RESET_VAL_DEC(0x0000801f, 0x00000000)
    742         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
    743         -1,
    744         -1,
    745     },
    746 #endif /* chips */
    747 
    748 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    749     { /* SOC_REG_INT_WAMURSTOFFSETPKTQr */
    750         soc_block_list[4],
    751         soc_genreg,
    752         8,
    753         0,
    754         0x8a006000,
    755         SOC_REG_FLAG_ARRAY,
    756         0,
    757         2,
    758         soc_WAMURSTOFFSETPKTPGr_fields,
    759         SOC_RESET_VAL_DEC(0x0000801f, 0x00000000)
    760         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
    761         -1,
    762         -1,
    763     },
    764 #endif /* chips */
    765 
    766 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    767     { /* SOC_REG_INT_WAMUSHRLMTCELLPGr */
    768         soc_block_list[4],
    769         soc_genreg,
    770         2,
    771         0,
    772         0x8a003a00,
    773         SOC_REG_FLAG_ARRAY,
    774         0,
    775         3,
    776         soc_WAMUSHRLMTCELLPGr_fields,
    777         SOC_RESET_VAL_DEC(0x00800685, 0x00000000)
    778         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
    779         -1,
    780         -1,
    781     },
    782 #endif /* chips */
    783 
    784 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    785     { /* SOC_REG_INT_WAMUSHRLMTPKTPGr */
    786         soc_block_list[4],
    787         soc_genreg,
    788         2,
    789         0,
    790         0x8a003600,
    791         SOC_REG_FLAG_ARRAY,
    792         0,
    793         3,
    794         soc_WAMUSHRLMTPKTPGr_fields,
    795         SOC_RESET_VAL_DEC(0x00008685, 0x00000000)
    796         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    797         -1,
    798         -1,
    799     },
    800 #endif /* chips */
    801 
    802 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    803     { /* SOC_REG_INT_WAMUSHRLMTPKTQr */
    804         soc_block_list[4],
    805         soc_genreg,
    806         8,
    807         0,
    808         0x8a005600,
    809         SOC_REG_FLAG_ARRAY,
    810         0,
    811         3,
    812         soc_WAMUSHRLMTPKTQr_fields,
    813         SOC_RESET_VAL_DEC(0x00008155, 0x00000000)
    814         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    815         -1,
    816         -1,
    817     },
    818 #endif /* chips */
    819 
    820 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    821     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    822     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    823     { /* SOC_REG_INT_WAMUSTATUSr */
    824         soc_block_list[4],
    825         soc_genreg,
    826         1,
    827         0,
    828         0x22080013,
    829         SOC_REG_FLAG_RO,
    830         0,
    831         1,
    832         soc_WAMUSTATUSr_fields,
    833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    834         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    835         -1,
    836         -1,
    837     },
    838 #endif /* chips */
    839 
    840 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    841     { /* SOC_REG_INT_WAMUSTATUS_BCM56640_A0r */
    842         soc_block_list[4],
    843         soc_genreg,
    844         1,
    845         0,
    846         0x8a001300,
    847         SOC_REG_FLAG_RO,
    848         0,
    849         1,
    850         soc_WAMUSTATUS_BCM56640_A0r_fields,
    851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    852         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    853         -1,
    854         -1,
    855     },
    856 #endif /* chips */
    857 
    858 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    859     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    860     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    861     { /* SOC_REG_INT_WAMUTBFRAGMCNTr */
    862         soc_block_list[4],
    863         soc_genreg,
    864         1,
    865         0,
    866         0x22080012,
    867         0,
    868         0,
    869         1,
    870         soc_WAMUTBFRAGMCNTr_fields,
    871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    872         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    873         -1,
    874         -1,
    875     },
    876 #endif /* chips */
    877 
    878 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    879     { /* SOC_REG_INT_WAMUTBFRAGMCNT_BCM56640_A0r */
    880         soc_block_list[4],
    881         soc_genreg,
    882         1,
    883         0,
    884         0x8a001200,
    885         0,
    886         0,
    887         1,
    888         soc_WAMUTBFRAGMCNT_BCM56640_A0r_fields,
    889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    890         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    891         -1,
    892         -1,
    893     },
    894 #endif /* chips */
    895 
    896 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    897     { /* SOC_REG_INT_WAMUTHDBYPASSr */
    898         soc_block_list[4],
    899         soc_genreg,
    900         1,
    901         0,
    902         0x8a00a000,
    903         0,
    904         0,
    905         2,
    906         soc_RDETHDBYPASSr_fields,
    907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    908         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
    909         -1,
    910         -1,
    911     },
    912 #endif /* chips */
    913 
    914 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    915     { /* SOC_REG_INT_WAMUTHDDROPSTr */
    916         soc_block_list[4],
    917         soc_genreg,
    918         1,
    919         0,
    920         0x8a00a200,
    921         SOC_REG_FLAG_RO,
    922         0,
    923         2,
    924         soc_WAMUTHDDROPSTr_fields,
    925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    926         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
    927         -1,
    928         -1,
    929     },
    930 #endif /* chips */
    931 
    932 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    933     { /* SOC_REG_INT_WAMUTOTALSHRLMTINGr */
    934         soc_block_list[4],
    935         soc_genreg,
    936         1,
    937         0,
    938         0x8a003000,
    939         0,
    940         0,
    941         2,
    942         soc_WAMUTOTALSHRLMTINGr_fields,
    943         SOC_RESET_VAL_DEC(0x01300e00, 0x00000000)
    944         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
    945         -1,
    946         -1,
    947     },
    948 #endif /* chips */
    949 
    950 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    951     { /* SOC_REG_INT_WAMUTOTALSHRLMTPKTEGRr */
    952         soc_block_list[4],
    953         soc_genreg,
    954         1,
    955         0,
    956         0x8a004a00,
    957         0,
    958         0,
    959         1,
    960         soc_WAMUTOTALSHRLMTPKTEGRr_fields,
    961         SOC_RESET_VAL_DEC(0x00000c00, 0x00000000)
    962         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    963         -1,
    964         -1,
    965     },
    966 #endif /* chips */
    967 
    968 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    969     { /* SOC_REG_INT_WAMU_PG_FIRST_FRAGMENT_DROP_OFFSETr */
    970         soc_block_list[4],
    971         soc_genreg,
    972         2,
    973         0,
    974         0xa015200,
    975         SOC_REG_FLAG_ARRAY,
    976         0,
    977         1,
    978         soc_WAMU_PG_FIRST_FRAGMENT_DROP_OFFSETr_fields,
    979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    980         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
    981         -1,
    982         -1,
    983     },
    984 #endif /* chips */
    985 
    986 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    987     { /* SOC_REG_INT_WAMU_PG_MIN_CELLr */
    988         soc_block_list[4],
    989         soc_genreg,
    990         2,
    991         0,
    992         0xa014200,
    993         SOC_REG_FLAG_ARRAY,
    994         0,
    995         2,
    996         soc_WAMU_PG_MIN_CELLr_fields,
    997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    998         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    999         -1,
   1000         -1,
   1001     },
   1002 #endif /* chips */
   1003 
   1004 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1005     { /* SOC_REG_INT_WAMU_PG_MIN_COUNT_CELLr */
   1006         soc_block_list[4],
   1007         soc_genreg,
   1008         2,
   1009         0,
   1010         0xa014a00,
   1011         SOC_REG_FLAG_ARRAY |
   1012                           SOC_REG_FLAG_RO,
   1013         0,
   1014         1,
   1015         soc_WAMU_PG_MIN_COUNT_CELLr_fields,
   1016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1017         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1018         -1,
   1019         -1,
   1020     },
   1021 #endif /* chips */
   1022 
   1023 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1024     { /* SOC_REG_INT_WAMU_PG_RESET_FLOOR_CELLr */
   1025         soc_block_list[4],
   1026         soc_genreg,
   1027         2,
   1028         0,
   1029         0xa014600,
   1030         SOC_REG_FLAG_ARRAY,
   1031         0,
   1032         1,
   1033         soc_WAMU_PG_RESET_FLOOR_CELLr_fields,
   1034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1035         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1036         -1,
   1037         -1,
   1038     },
   1039 #endif /* chips */
   1040 
   1041 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1042     { /* SOC_REG_INT_WAMU_PG_RESET_OFFSET_CELLr */
   1043         soc_block_list[4],
   1044         soc_genreg,
   1045         2,
   1046         0,
   1047         0xa014400,
   1048         SOC_REG_FLAG_ARRAY,
   1049         0,
   1050         1,
   1051         soc_WAMU_PG_RESET_OFFSET_CELLr_fields,
   1052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1053         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1054         -1,
   1055         -1,
   1056     },
   1057 #endif /* chips */
   1058 
   1059 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1060     { /* SOC_REG_INT_WAMU_PG_RESUME_LIMITr */
   1061         soc_block_list[4],
   1062         soc_genreg,
   1063         2,
   1064         0,
   1065         0xa015000,
   1066         SOC_REG_FLAG_ARRAY |
   1067                           SOC_REG_FLAG_RO,
   1068         0,
   1069         1,
   1070         soc_WAMU_PG_RESUME_LIMITr_fields,
   1071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1072         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1073         -1,
   1074         -1,
   1075     },
   1076 #endif /* chips */
   1077 
   1078 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1079     { /* SOC_REG_INT_WAMU_PG_SHARED_COUNT_CELLr */
   1080         soc_block_list[4],
   1081         soc_genreg,
   1082         2,
   1083         0,
   1084         0xa014c00,
   1085         SOC_REG_FLAG_ARRAY |
   1086                           SOC_REG_FLAG_RO,
   1087         0,
   1088         1,
   1089         soc_WAMU_PG_SHARED_COUNT_CELLr_fields,
   1090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1091         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1092         -1,
   1093         -1,
   1094     },
   1095 #endif /* chips */
   1096 
   1097 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1098     { /* SOC_REG_INT_WAMU_PG_SHARED_LIMIT_CELLr */
   1099         soc_block_list[4],
   1100         soc_genreg,
   1101         2,
   1102         0,
   1103         0xa014e00,
   1104         SOC_REG_FLAG_ARRAY,
   1105         0,
   1106         2,
   1107         soc_WAMU_PG_SHARED_LIMIT_CELLr_fields,
   1108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1109         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   1110         -1,
   1111         -1,
   1112     },
   1113 #endif /* chips */
   1114 
   1115 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1116     { /* SOC_REG_INT_WAMU_PG_XOFF_STATEr */
   1117         soc_block_list[4],
   1118         soc_genreg,
   1119         1,
   1120         0,
   1121         0xa015400,
   1122         SOC_REG_FLAG_RO,
   1123         0,
   1124         2,
   1125         soc_WAMU_PG_XOFF_STATEr_fields,
   1126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1127         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1128         -1,
   1129         -1,
   1130     },
   1131 #endif /* chips */
   1132 
   1133 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1134     { /* SOC_REG_INT_WAMU_POOL_SELECTr */
   1135         soc_block_list[4],
   1136         soc_genreg,
   1137         1,
   1138         0,
   1139         0xa014000,
   1140         0,
   1141         0,
   1142         1,
   1143         soc_RDE_POOL_SELECTr_fields,
   1144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1145         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1146         -1,
   1147         -1,
   1148     },
   1149 #endif /* chips */
   1150 
   1151 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1152     { /* SOC_REG_INT_WAMU_PORT_SHARED_COUNT_CELLr */
   1153         soc_block_list[4],
   1154         soc_genreg,
   1155         1,
   1156         0,
   1157         0xa014900,
   1158         SOC_REG_FLAG_RO,
   1159         0,
   1160         1,
   1161         soc_PORT_SHARED_COUNT_CELL_BCM56640_A0r_fields,
   1162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1163         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1164         -1,
   1165         -1,
   1166     },
   1167 #endif /* chips */
   1168 
   1169 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1170     { /* SOC_REG_INT_WAMU_PRI_GRPr */
   1171         soc_block_list[4],
   1172         soc_genreg,
   1173         1,
   1174         0,
   1175         0xa014100,
   1176         0,
   1177         0,
   1178         4,
   1179         soc_WAMU_PRI_GRPr_fields,
   1180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1181         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   1182         -1,
   1183         -1,
   1184     },
   1185 #endif /* chips */
   1186 
   1187 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1188     { /* SOC_REG_INT_WAMU_TOTAL_COUNT_CELLr */
   1189         soc_block_list[4],
   1190         soc_genreg,
   1191         1,
   1192         0,
   1193         0xa014800,
   1194         SOC_REG_FLAG_RO,
   1195         0,
   1196         1,
   1197         soc_OP_PORT_TOTAL_COUNT_CELL_BCM56640_A0r_fields,
   1198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1199         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1200         -1,
   1201         -1,
   1202     },
   1203 #endif /* chips */
   1204 
   1205 #if defined(BCM_56640_A0)
   1206     { /* SOC_REG_INT_WCL_CTLr */
   1207         soc_block_list[90],
   1208         soc_genreg,
   1209         6,
   1210         0,
   1211         0x2008100,
   1212         SOC_REG_FLAG_ARRAY,
   1213         0,
   1214         9,
   1215         soc_WCL_CTLr_fields,
   1216         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   1217         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   1218         -1,
   1219         -1,
   1220     },
   1221 #endif /* chips */
   1222 
   1223 #if defined(BCM_56640_A0)
   1224     { /* SOC_REG_INT_WCL_CUR_STSr */
   1225         soc_block_list[90],
   1226         soc_genreg,
   1227         1,
   1228         0,
   1229         0x2008700,
   1230         SOC_REG_FLAG_RO,
   1231         0,
   1232         18,
   1233         soc_WCL_CUR_STSr_fields,
   1234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1235         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   1236         -1,
   1237         -1,
   1238     },
   1239 #endif /* chips */
   1240 
   1241 #if defined(BCM_56640_A0)
   1242     { /* SOC_REG_INT_WCL_INTR_CLEARr */
   1243         soc_block_list[90],
   1244         soc_genreg,
   1245         1,
   1246         0,
   1247         0x2008a00,
   1248         0,
   1249         0,
   1250         1,
   1251         soc_WCL_INTR_CLEARr_fields,
   1252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1253         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1254         -1,
   1255         -1,
   1256     },
   1257 #endif /* chips */
   1258 
   1259 #if defined(BCM_56640_A0)
   1260     { /* SOC_REG_INT_WCL_INTR_ENABLEr */
   1261         soc_block_list[90],
   1262         soc_genreg,
   1263         1,
   1264         0,
   1265         0x2008900,
   1266         0,
   1267         0,
   1268         1,
   1269         soc_WCL_INTR_ENABLEr_fields,
   1270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1271         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   1272         -1,
   1273         -1,
   1274     },
   1275 #endif /* chips */
   1276 
   1277 #if defined(BCM_56640_A0)
   1278     { /* SOC_REG_INT_WCL_INTR_STSr */
   1279         soc_block_list[90],
   1280         soc_genreg,
   1281         1,
   1282         0,
   1283         0x2008800,
   1284         0,
   1285         0,
   1286         18,
   1287         soc_WCL_INTR_STSr_fields,
   1288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1289         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   1290         -1,
   1291         -1,
   1292     },
   1293 #endif /* chips */
   1294 
   1295 #if defined(BCM_56640_A0)
   1296     { /* SOC_REG_INT_WCL_RX_LOST_LOCK_COUNTr */
   1297         soc_block_list[90],
   1298         soc_genreg,
   1299         12,
   1300         0,
   1301         0x2007300,
   1302         SOC_REG_FLAG_ARRAY,
   1303         0,
   1304         2,
   1305         soc_ILAMAC_RX_ALIGNMENT_ERRORS_COUNTr_fields,
   1306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1307         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1308         -1,
   1309         -1,
   1310     },
   1311 #endif /* chips */
   1312 
   1313 #if defined(BCM_56800_A0)
   1314     { /* SOC_REG_INT_WDRRCOUNTr */
   1315         soc_block_list[4],
   1316         soc_portreg,
   1317         8,
   1318         0,
   1319         0x6000060,
   1320         SOC_REG_FLAG_ARRAY |
   1321                           SOC_REG_FLAG_RO,
   1322         0,
   1323         3,
   1324         soc_WDRRCOUNTr_fields,
   1325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1326         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   1327         -1,
   1328         -1,
   1329     },
   1330 #endif /* chips */
   1331 
   1332 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   1333     { /* SOC_REG_INT_WDRRCOUNT_BCM56334_A0r */
   1334         soc_block_list[4],
   1335         soc_portreg,
   1336         48,
   1337         0,
   1338         0x6000140,
   1339         SOC_REG_FLAG_ARRAY |
   1340                           SOC_REG_FLAG_RO,
   1341         0,
   1342         3,
   1343         soc_WDRRCOUNTr_fields,
   1344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1345         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   1346         -1,
   1347         34,
   1348     },
   1349 #endif /* chips */
   1350 
   1351 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   1352     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   1353     { /* SOC_REG_INT_WDRRCOUNT_BCM56624_A0r */
   1354         soc_block_list[4],
   1355         soc_portreg,
   1356         10,
   1357         0,
   1358         0x6000060,
   1359         SOC_REG_FLAG_ARRAY |
   1360                           SOC_REG_FLAG_RO,
   1361         0,
   1362         3,
   1363         soc_WDRRCOUNTr_fields,
   1364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1365         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   1366         -1,
   1367         6,
   1368     },
   1369 #endif /* chips */
   1370 
   1371 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   1372     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   1373     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   1374     { /* SOC_REG_INT_WDRRCOUNT_BCM56634_A0r */
   1375         soc_block_list[4],
   1376         soc_portreg,
   1377         48,
   1378         0,
   1379         0x6000140,
   1380         SOC_REG_FLAG_ARRAY |
   1381                           SOC_REG_FLAG_RO,
   1382         0,
   1383         3,
   1384         soc_WDRRCOUNTr_fields,
   1385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1386         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   1387         -1,
   1388         22,
   1389     },
   1390 #endif /* chips */
   1391 
   1392 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   1393     { /* SOC_REG_INT_WDRRCOUNT_BCM56820_A0r */
   1394         soc_block_list[4],
   1395         soc_portreg,
   1396         8,
   1397         0,
   1398         0x6000060,
   1399         SOC_REG_FLAG_ARRAY |
   1400                           SOC_REG_FLAG_RO,
   1401         0,
   1402         3,
   1403         soc_WDRRCOUNTr_fields,
   1404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1405         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   1406         -1,
   1407         10,
   1408     },
   1409 #endif /* chips */
   1410 
   1411 #if defined(BCM_88732_A0)
   1412     { /* SOC_REG_INT_WDRRCOUNT_BCM88732_A0r */
   1413         soc_block_list[4],
   1414         soc_portreg,
   1415         8,
   1416         0,
   1417         0x6000060,
   1418         SOC_REG_FLAG_ARRAY |
   1419                           SOC_REG_FLAG_RO,
   1420         0,
   1421         3,
   1422         soc_PORTGRP_WDRRCOUNTr_fields,
   1423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1424         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   1425         -1,
   1426         50,
   1427     },
   1428 #endif /* chips */
   1429 
   1430 #if defined(BCM_88650_A0)
   1431     { /* SOC_REG_INT_WDT0_WDOGCONTROLr */
   1432         soc_block_list[1],
   1433         soc_mcsreg,
   1434         1,
   1435         0,
   1436         0x7004008,
   1437         0,
   1438         0,
   1439         1,
   1440         soc_WDT0_WDOGCONTROLr_fields,
   1441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1442         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1443         -1,
   1444         -1,
   1445     },
   1446 #endif /* chips */
   1447 
   1448 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1449     { /* SOC_REG_INT_WDT0_WDOGCONTROL_BCM56440_A0r */
   1450         soc_block_list[1],
   1451         soc_mcsreg,
   1452         1,
   1453         0,
   1454         0x7004008,
   1455         0,
   1456         0,
   1457         1,
   1458         soc_WDT0_WDOGCONTROL_BCM56440_A0r_fields,
   1459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1460         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1461         -1,
   1462         -1,
   1463     },
   1464 #endif /* chips */
   1465 
   1466 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   1467     defined(BCM_56860_A0)
   1468     { /* SOC_REG_INT_WDT0_WDOGCONTROL_BCM56640_A0r */
   1469         soc_block_list[1],
   1470         soc_mcsreg,
   1471         1,
   1472         0,
   1473         0x7004008,
   1474         0,
   1475         0,
   1476         1,
   1477         soc_WDT0_WDOGCONTROL_BCM56640_A0r_fields,
   1478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1479         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1480         -1,
   1481         -1,
   1482     },
   1483 #endif /* chips */
   1484 
   1485 #if defined(BCM_88202_A0)
   1486     { /* SOC_REG_INT_WDT0_WDOGCONTROL_BCM88202_A0r */
   1487         soc_block_list[1],
   1488         soc_mcsreg,
   1489         1,
   1490         0,
   1491         0x7004008,
   1492         0,
   1493         0,
   1494         1,
   1495         soc_WDT0_WDOGCONTROL_BCM88202_A0r_fields,
   1496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1497         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1498         -1,
   1499         -1,
   1500     },
   1501 #endif /* chips */
   1502 
   1503 #if defined(BCM_88650_B0)
   1504     { /* SOC_REG_INT_WDT0_WDOGCONTROL_BCM88650_B0r */
   1505         soc_block_list[1],
   1506         soc_mcsreg,
   1507         1,
   1508         0,
   1509         0x7004008,
   1510         0,
   1511         0,
   1512         1,
   1513         soc_WDT0_WDOGCONTROL_BCM88650_B0r_fields,
   1514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1515         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1516         -1,
   1517         -1,
   1518     },
   1519 #endif /* chips */
   1520 
   1521 #if defined(BCM_88660_A0)
   1522     { /* SOC_REG_INT_WDT0_WDOGCONTROL_BCM88660_A0r */
   1523         soc_block_list[1],
   1524         soc_mcsreg,
   1525         1,
   1526         0,
   1527         0x7004008,
   1528         0,
   1529         0,
   1530         1,
   1531         soc_WDT0_WDOGCONTROL_BCM88660_A0r_fields,
   1532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1533         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1534         -1,
   1535         -1,
   1536     },
   1537 #endif /* chips */
   1538 
   1539 #if defined(BCM_88650_A0)
   1540     { /* SOC_REG_INT_WDT0_WDOGINTCLRr */
   1541         soc_block_list[1],
   1542         soc_mcsreg,
   1543         1,
   1544         0,
   1545         0x700400c,
   1546         0,
   1547         0,
   1548         1,
   1549         soc_WDT0_WDOGINTCLRr_fields,
   1550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1551         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1552         -1,
   1553         -1,
   1554     },
   1555 #endif /* chips */
   1556 
   1557 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1558     { /* SOC_REG_INT_WDT0_WDOGINTCLR_BCM56440_A0r */
   1559         soc_block_list[1],
   1560         soc_mcsreg,
   1561         1,
   1562         0,
   1563         0x700400c,
   1564         0,
   1565         0,
   1566         1,
   1567         soc_WDT0_WDOGINTCLR_BCM56440_A0r_fields,
   1568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1569         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1570         -1,
   1571         -1,
   1572     },
   1573 #endif /* chips */
   1574 
   1575 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   1576     defined(BCM_56860_A0)
   1577     { /* SOC_REG_INT_WDT0_WDOGINTCLR_BCM56640_A0r */
   1578         soc_block_list[1],
   1579         soc_mcsreg,
   1580         1,
   1581         0,
   1582         0x700400c,
   1583         0,
   1584         0,
   1585         1,
   1586         soc_WDT0_WDOGINTCLR_BCM56640_A0r_fields,
   1587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1588         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1589         -1,
   1590         -1,
   1591     },
   1592 #endif /* chips */
   1593 
   1594 #if defined(BCM_88202_A0)
   1595     { /* SOC_REG_INT_WDT0_WDOGINTCLR_BCM88202_A0r */
   1596         soc_block_list[1],
   1597         soc_mcsreg,
   1598         1,
   1599         0,
   1600         0x700400c,
   1601         0,
   1602         0,
   1603         1,
   1604         soc_WDT0_WDOGINTCLR_BCM88202_A0r_fields,
   1605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1606         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1607         -1,
   1608         -1,
   1609     },
   1610 #endif /* chips */
   1611 
   1612 #if defined(BCM_88650_B0)
   1613     { /* SOC_REG_INT_WDT0_WDOGINTCLR_BCM88650_B0r */
   1614         soc_block_list[1],
   1615         soc_mcsreg,
   1616         1,
   1617         0,
   1618         0x700400c,
   1619         0,
   1620         0,
   1621         1,
   1622         soc_WDT0_WDOGINTCLR_BCM88650_B0r_fields,
   1623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1624         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1625         -1,
   1626         -1,
   1627     },
   1628 #endif /* chips */
   1629 
   1630 #if defined(BCM_88660_A0)
   1631     { /* SOC_REG_INT_WDT0_WDOGINTCLR_BCM88660_A0r */
   1632         soc_block_list[1],
   1633         soc_mcsreg,
   1634         1,
   1635         0,
   1636         0x700400c,
   1637         0,
   1638         0,
   1639         1,
   1640         soc_WDT0_WDOGINTCLR_BCM88660_A0r_fields,
   1641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1642         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1643         -1,
   1644         -1,
   1645     },
   1646 #endif /* chips */
   1647 
   1648 #if defined(BCM_88650_A0)
   1649     { /* SOC_REG_INT_WDT0_WDOGITCRr */
   1650         soc_block_list[1],
   1651         soc_mcsreg,
   1652         1,
   1653         0,
   1654         0x7004f00,
   1655         0,
   1656         0,
   1657         1,
   1658         soc_WDT0_WDOGITCRr_fields,
   1659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1660         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1661         -1,
   1662         -1,
   1663     },
   1664 #endif /* chips */
   1665 
   1666 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1667     { /* SOC_REG_INT_WDT0_WDOGITCR_BCM56440_A0r */
   1668         soc_block_list[1],
   1669         soc_mcsreg,
   1670         1,
   1671         0,
   1672         0x7004f00,
   1673         0,
   1674         0,
   1675         1,
   1676         soc_WDT0_WDOGITCR_BCM56440_A0r_fields,
   1677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1678         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1679         -1,
   1680         -1,
   1681     },
   1682 #endif /* chips */
   1683 
   1684 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   1685     defined(BCM_56860_A0)
   1686     { /* SOC_REG_INT_WDT0_WDOGITCR_BCM56640_A0r */
   1687         soc_block_list[1],
   1688         soc_mcsreg,
   1689         1,
   1690         0,
   1691         0x7004f00,
   1692         0,
   1693         0,
   1694         1,
   1695         soc_WDT0_WDOGITCR_BCM56640_A0r_fields,
   1696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1697         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1698         -1,
   1699         -1,
   1700     },
   1701 #endif /* chips */
   1702 
   1703 #if defined(BCM_88202_A0)
   1704     { /* SOC_REG_INT_WDT0_WDOGITCR_BCM88202_A0r */
   1705         soc_block_list[1],
   1706         soc_mcsreg,
   1707         1,
   1708         0,
   1709         0x7004f00,
   1710         0,
   1711         0,
   1712         1,
   1713         soc_WDT0_WDOGITCR_BCM88202_A0r_fields,
   1714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1715         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1716         -1,
   1717         -1,
   1718     },
   1719 #endif /* chips */
   1720 
   1721 #if defined(BCM_88650_B0)
   1722     { /* SOC_REG_INT_WDT0_WDOGITCR_BCM88650_B0r */
   1723         soc_block_list[1],
   1724         soc_mcsreg,
   1725         1,
   1726         0,
   1727         0x7004f00,
   1728         0,
   1729         0,
   1730         1,
   1731         soc_WDT0_WDOGITCR_BCM88650_B0r_fields,
   1732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1733         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1734         -1,
   1735         -1,
   1736     },
   1737 #endif /* chips */
   1738 
   1739 #if defined(BCM_88660_A0)
   1740     { /* SOC_REG_INT_WDT0_WDOGITCR_BCM88660_A0r */
   1741         soc_block_list[1],
   1742         soc_mcsreg,
   1743         1,
   1744         0,
   1745         0x7004f00,
   1746         0,
   1747         0,
   1748         1,
   1749         soc_WDT0_WDOGITCR_BCM88660_A0r_fields,
   1750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1751         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1752         -1,
   1753         -1,
   1754     },
   1755 #endif /* chips */
   1756 
   1757 #if defined(BCM_88650_A0)
   1758     { /* SOC_REG_INT_WDT0_WDOGITOPr */
   1759         soc_block_list[1],
   1760         soc_mcsreg,
   1761         1,
   1762         0,
   1763         0x7004f04,
   1764         0,
   1765         0,
   1766         1,
   1767         soc_WDT0_WDOGITOPr_fields,
   1768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1769         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1770         -1,
   1771         -1,
   1772     },
   1773 #endif /* chips */
   1774 
   1775 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1776     { /* SOC_REG_INT_WDT0_WDOGITOP_BCM56440_A0r */
   1777         soc_block_list[1],
   1778         soc_mcsreg,
   1779         1,
   1780         0,
   1781         0x7004f04,
   1782         0,
   1783         0,
   1784         1,
   1785         soc_WDT0_WDOGITOP_BCM56440_A0r_fields,
   1786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1787         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1788         -1,
   1789         -1,
   1790     },
   1791 #endif /* chips */
   1792 
   1793 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   1794     defined(BCM_56860_A0)
   1795     { /* SOC_REG_INT_WDT0_WDOGITOP_BCM56640_A0r */
   1796         soc_block_list[1],
   1797         soc_mcsreg,
   1798         1,
   1799         0,
   1800         0x7004f04,
   1801         0,
   1802         0,
   1803         1,
   1804         soc_WDT0_WDOGITOP_BCM56640_A0r_fields,
   1805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1806         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1807         -1,
   1808         -1,
   1809     },
   1810 #endif /* chips */
   1811 
   1812 #if defined(BCM_88202_A0)
   1813     { /* SOC_REG_INT_WDT0_WDOGITOP_BCM88202_A0r */
   1814         soc_block_list[1],
   1815         soc_mcsreg,
   1816         1,
   1817         0,
   1818         0x7004f04,
   1819         0,
   1820         0,
   1821         1,
   1822         soc_WDT0_WDOGITOP_BCM88202_A0r_fields,
   1823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1824         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1825         -1,
   1826         -1,
   1827     },
   1828 #endif /* chips */
   1829 
   1830 #if defined(BCM_88650_B0)
   1831     { /* SOC_REG_INT_WDT0_WDOGITOP_BCM88650_B0r */
   1832         soc_block_list[1],
   1833         soc_mcsreg,
   1834         1,
   1835         0,
   1836         0x7004f04,
   1837         0,
   1838         0,
   1839         1,
   1840         soc_WDT0_WDOGITOP_BCM88650_B0r_fields,
   1841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1842         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1843         -1,
   1844         -1,
   1845     },
   1846 #endif /* chips */
   1847 
   1848 #if defined(BCM_88660_A0)
   1849     { /* SOC_REG_INT_WDT0_WDOGITOP_BCM88660_A0r */
   1850         soc_block_list[1],
   1851         soc_mcsreg,
   1852         1,
   1853         0,
   1854         0x7004f04,
   1855         0,
   1856         0,
   1857         1,
   1858         soc_WDT0_WDOGITOP_BCM88660_A0r_fields,
   1859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1860         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1861         -1,
   1862         -1,
   1863     },
   1864 #endif /* chips */
   1865 
   1866 #if defined(BCM_88650_A0)
   1867     { /* SOC_REG_INT_WDT0_WDOGLOADr */
   1868         soc_block_list[1],
   1869         soc_mcsreg,
   1870         1,
   1871         0,
   1872         0x7004000,
   1873         0,
   1874         0,
   1875         1,
   1876         soc_WDT0_WDOGLOADr_fields,
   1877         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   1878         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1879         -1,
   1880         -1,
   1881     },
   1882 #endif /* chips */
   1883 
   1884 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1885     { /* SOC_REG_INT_WDT0_WDOGLOAD_BCM56440_A0r */
   1886         soc_block_list[1],
   1887         soc_mcsreg,
   1888         1,
   1889         0,
   1890         0x7004000,
   1891         0,
   1892         0,
   1893         1,
   1894         soc_WDT0_WDOGLOAD_BCM56440_A0r_fields,
   1895         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   1896         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1897         -1,
   1898         -1,
   1899     },
   1900 #endif /* chips */
   1901 
   1902 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   1903     defined(BCM_56860_A0)
   1904     { /* SOC_REG_INT_WDT0_WDOGLOAD_BCM56640_A0r */
   1905         soc_block_list[1],
   1906         soc_mcsreg,
   1907         1,
   1908         0,
   1909         0x7004000,
   1910         0,
   1911         0,
   1912         1,
   1913         soc_WDT0_WDOGLOAD_BCM56640_A0r_fields,
   1914         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   1915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1916         -1,
   1917         -1,
   1918     },
   1919 #endif /* chips */
   1920 
   1921 #if defined(BCM_88202_A0)
   1922     { /* SOC_REG_INT_WDT0_WDOGLOAD_BCM88202_A0r */
   1923         soc_block_list[1],
   1924         soc_mcsreg,
   1925         1,
   1926         0,
   1927         0x7004000,
   1928         0,
   1929         0,
   1930         1,
   1931         soc_WDT0_WDOGLOAD_BCM88202_A0r_fields,
   1932         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   1933         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1934         -1,
   1935         -1,
   1936     },
   1937 #endif /* chips */
   1938 
   1939 #if defined(BCM_88650_B0)
   1940     { /* SOC_REG_INT_WDT0_WDOGLOAD_BCM88650_B0r */
   1941         soc_block_list[1],
   1942         soc_mcsreg,
   1943         1,
   1944         0,
   1945         0x7004000,
   1946         0,
   1947         0,
   1948         1,
   1949         soc_WDT0_WDOGLOAD_BCM88650_B0r_fields,
   1950         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   1951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1952         -1,
   1953         -1,
   1954     },
   1955 #endif /* chips */
   1956 
   1957 #if defined(BCM_88660_A0)
   1958     { /* SOC_REG_INT_WDT0_WDOGLOAD_BCM88660_A0r */
   1959         soc_block_list[1],
   1960         soc_mcsreg,
   1961         1,
   1962         0,
   1963         0x7004000,
   1964         0,
   1965         0,
   1966         1,
   1967         soc_WDT0_WDOGLOAD_BCM88660_A0r_fields,
   1968         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   1969         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1970         -1,
   1971         -1,
   1972     },
   1973 #endif /* chips */
   1974 
   1975 #if defined(BCM_88650_A0)
   1976     { /* SOC_REG_INT_WDT0_WDOGLOCKr */
   1977         soc_block_list[1],
   1978         soc_mcsreg,
   1979         1,
   1980         0,
   1981         0x7004c00,
   1982         0,
   1983         0,
   1984         1,
   1985         soc_WDT0_WDOGLOCKr_fields,
   1986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1987         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1988         -1,
   1989         -1,
   1990     },
   1991 #endif /* chips */
   1992 
   1993 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1994     { /* SOC_REG_INT_WDT0_WDOGLOCK_BCM56440_A0r */
   1995         soc_block_list[1],
   1996         soc_mcsreg,
   1997         1,
   1998         0,
   1999         0x7004c00,
   2000         0,
   2001         0,
   2002         1,
   2003         soc_WDT0_WDOGLOCK_BCM56440_A0r_fields,
   2004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2005         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2006         -1,
   2007         -1,
   2008     },
   2009 #endif /* chips */
   2010 
   2011 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   2012     defined(BCM_56860_A0)
   2013     { /* SOC_REG_INT_WDT0_WDOGLOCK_BCM56640_A0r */
   2014         soc_block_list[1],
   2015         soc_mcsreg,
   2016         1,
   2017         0,
   2018         0x7004c00,
   2019         0,
   2020         0,
   2021         1,
   2022         soc_WDT0_WDOGLOCK_BCM56640_A0r_fields,
   2023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2024         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2025         -1,
   2026         -1,
   2027     },
   2028 #endif /* chips */
   2029 
   2030 #if defined(BCM_88202_A0)
   2031     { /* SOC_REG_INT_WDT0_WDOGLOCK_BCM88202_A0r */
   2032         soc_block_list[1],
   2033         soc_mcsreg,
   2034         1,
   2035         0,
   2036         0x7004c00,
   2037         0,
   2038         0,
   2039         1,
   2040         soc_WDT0_WDOGLOCK_BCM88202_A0r_fields,
   2041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2042         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2043         -1,
   2044         -1,
   2045     },
   2046 #endif /* chips */
   2047 
   2048 #if defined(BCM_88650_B0)
   2049     { /* SOC_REG_INT_WDT0_WDOGLOCK_BCM88650_B0r */
   2050         soc_block_list[1],
   2051         soc_mcsreg,
   2052         1,
   2053         0,
   2054         0x7004c00,
   2055         0,
   2056         0,
   2057         1,
   2058         soc_WDT0_WDOGLOCK_BCM88650_B0r_fields,
   2059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2060         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2061         -1,
   2062         -1,
   2063     },
   2064 #endif /* chips */
   2065 
   2066 #if defined(BCM_88660_A0)
   2067     { /* SOC_REG_INT_WDT0_WDOGLOCK_BCM88660_A0r */
   2068         soc_block_list[1],
   2069         soc_mcsreg,
   2070         1,
   2071         0,
   2072         0x7004c00,
   2073         0,
   2074         0,
   2075         1,
   2076         soc_WDT0_WDOGLOCK_BCM88660_A0r_fields,
   2077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2078         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2079         -1,
   2080         -1,
   2081     },
   2082 #endif /* chips */
   2083 
   2084 #if defined(BCM_88650_A0)
   2085     { /* SOC_REG_INT_WDT0_WDOGMISr */
   2086         soc_block_list[1],
   2087         soc_mcsreg,
   2088         1,
   2089         0,
   2090         0x7004014,
   2091         SOC_REG_FLAG_RO,
   2092         0,
   2093         1,
   2094         soc_WDT0_WDOGMISr_fields,
   2095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2096         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2097         -1,
   2098         -1,
   2099     },
   2100 #endif /* chips */
   2101 
   2102 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2103     { /* SOC_REG_INT_WDT0_WDOGMIS_BCM56440_A0r */
   2104         soc_block_list[1],
   2105         soc_mcsreg,
   2106         1,
   2107         0,
   2108         0x7004014,
   2109         SOC_REG_FLAG_RO,
   2110         0,
   2111         1,
   2112         soc_WDT0_WDOGMIS_BCM56440_A0r_fields,
   2113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2114         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2115         -1,
   2116         -1,
   2117     },
   2118 #endif /* chips */
   2119 
   2120 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   2121     defined(BCM_56860_A0)
   2122     { /* SOC_REG_INT_WDT0_WDOGMIS_BCM56640_A0r */
   2123         soc_block_list[1],
   2124         soc_mcsreg,
   2125         1,
   2126         0,
   2127         0x7004014,
   2128         SOC_REG_FLAG_RO,
   2129         0,
   2130         1,
   2131         soc_WDT0_WDOGMIS_BCM56640_A0r_fields,
   2132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2133         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2134         -1,
   2135         -1,
   2136     },
   2137 #endif /* chips */
   2138 
   2139 #if defined(BCM_88202_A0)
   2140     { /* SOC_REG_INT_WDT0_WDOGMIS_BCM88202_A0r */
   2141         soc_block_list[1],
   2142         soc_mcsreg,
   2143         1,
   2144         0,
   2145         0x7004014,
   2146         SOC_REG_FLAG_RO,
   2147         0,
   2148         1,
   2149         soc_WDT0_WDOGMIS_BCM88202_A0r_fields,
   2150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2151         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2152         -1,
   2153         -1,
   2154     },
   2155 #endif /* chips */
   2156 
   2157 #if defined(BCM_88650_B0)
   2158     { /* SOC_REG_INT_WDT0_WDOGMIS_BCM88650_B0r */
   2159         soc_block_list[1],
   2160         soc_mcsreg,
   2161         1,
   2162         0,
   2163         0x7004014,
   2164         SOC_REG_FLAG_RO,
   2165         0,
   2166         1,
   2167         soc_WDT0_WDOGMIS_BCM88650_B0r_fields,
   2168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2169         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2170         -1,
   2171         -1,
   2172     },
   2173 #endif /* chips */
   2174 
   2175 #if defined(BCM_88660_A0)
   2176     { /* SOC_REG_INT_WDT0_WDOGMIS_BCM88660_A0r */
   2177         soc_block_list[1],
   2178         soc_mcsreg,
   2179         1,
   2180         0,
   2181         0x7004014,
   2182         SOC_REG_FLAG_RO,
   2183         0,
   2184         1,
   2185         soc_WDT0_WDOGMIS_BCM88660_A0r_fields,
   2186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2187         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2188         -1,
   2189         -1,
   2190     },
   2191 #endif /* chips */
   2192 
   2193 #if defined(BCM_88650_A0)
   2194     { /* SOC_REG_INT_WDT0_WDOGPCELLID0r */
   2195         soc_block_list[1],
   2196         soc_mcsreg,
   2197         1,
   2198         0,
   2199         0x7004ff0,
   2200         SOC_REG_FLAG_RO,
   2201         0,
   2202         1,
   2203         soc_WDT0_WDOGPCELLID0r_fields,
   2204         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   2205         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2206         -1,
   2207         -1,
   2208     },
   2209 #endif /* chips */
   2210 
   2211 #if defined(BCM_88650_A0)
   2212     { /* SOC_REG_INT_WDT0_WDOGPCELLID1r */
   2213         soc_block_list[1],
   2214         soc_mcsreg,
   2215         1,
   2216         0,
   2217         0x7004ff4,
   2218         SOC_REG_FLAG_RO,
   2219         0,
   2220         1,
   2221         soc_WDT0_WDOGPCELLID1r_fields,
   2222         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   2223         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2224         -1,
   2225         -1,
   2226     },
   2227 #endif /* chips */
   2228 
   2229 #if defined(BCM_88650_A0)
   2230     { /* SOC_REG_INT_WDT0_WDOGPCELLID2r */
   2231         soc_block_list[1],
   2232         soc_mcsreg,
   2233         1,
   2234         0,
   2235         0x7004ff8,
   2236         SOC_REG_FLAG_RO,
   2237         0,
   2238         1,
   2239         soc_WDT0_WDOGPCELLID2r_fields,
   2240         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2241         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2242         -1,
   2243         -1,
   2244     },
   2245 #endif /* chips */
   2246 
   2247 #if defined(BCM_88650_A0)
   2248     { /* SOC_REG_INT_WDT0_WDOGPCELLID3r */
   2249         soc_block_list[1],
   2250         soc_mcsreg,
   2251         1,
   2252         0,
   2253         0x7004ffc,
   2254         SOC_REG_FLAG_RO,
   2255         0,
   2256         1,
   2257         soc_WDT0_WDOGPCELLID3r_fields,
   2258         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   2259         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2260         -1,
   2261         -1,
   2262     },
   2263 #endif /* chips */
   2264 
   2265 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2266     { /* SOC_REG_INT_WDT0_WDOGPCELLID0_BCM56440_A0r */
   2267         soc_block_list[1],
   2268         soc_mcsreg,
   2269         1,
   2270         0,
   2271         0x7004ff0,
   2272         SOC_REG_FLAG_RO,
   2273         0,
   2274         1,
   2275         soc_WDT0_WDOGPCELLID0_BCM56440_A0r_fields,
   2276         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   2277         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2278         -1,
   2279         -1,
   2280     },
   2281 #endif /* chips */
   2282 
   2283 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   2284     defined(BCM_56860_A0)
   2285     { /* SOC_REG_INT_WDT0_WDOGPCELLID0_BCM56640_A0r */
   2286         soc_block_list[1],
   2287         soc_mcsreg,
   2288         1,
   2289         0,
   2290         0x7004ff0,
   2291         SOC_REG_FLAG_RO,
   2292         0,
   2293         1,
   2294         soc_WDT0_WDOGPCELLID0_BCM56640_A0r_fields,
   2295         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   2296         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2297         -1,
   2298         -1,
   2299     },
   2300 #endif /* chips */
   2301 
   2302 #if defined(BCM_88202_A0)
   2303     { /* SOC_REG_INT_WDT0_WDOGPCELLID0_BCM88202_A0r */
   2304         soc_block_list[1],
   2305         soc_mcsreg,
   2306         1,
   2307         0,
   2308         0x7004ff0,
   2309         SOC_REG_FLAG_RO,
   2310         0,
   2311         1,
   2312         soc_WDT0_WDOGPCELLID0_BCM88202_A0r_fields,
   2313         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   2314         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2315         -1,
   2316         -1,
   2317     },
   2318 #endif /* chips */
   2319 
   2320 #if defined(BCM_88650_B0)
   2321     { /* SOC_REG_INT_WDT0_WDOGPCELLID0_BCM88650_B0r */
   2322         soc_block_list[1],
   2323         soc_mcsreg,
   2324         1,
   2325         0,
   2326         0x7004ff0,
   2327         SOC_REG_FLAG_RO,
   2328         0,
   2329         1,
   2330         soc_WDT0_WDOGPCELLID0_BCM88650_B0r_fields,
   2331         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   2332         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2333         -1,
   2334         -1,
   2335     },
   2336 #endif /* chips */
   2337 
   2338 #if defined(BCM_88660_A0)
   2339     { /* SOC_REG_INT_WDT0_WDOGPCELLID0_BCM88660_A0r */
   2340         soc_block_list[1],
   2341         soc_mcsreg,
   2342         1,
   2343         0,
   2344         0x7004ff0,
   2345         SOC_REG_FLAG_RO,
   2346         0,
   2347         1,
   2348         soc_WDT0_WDOGPCELLID0_BCM88660_A0r_fields,
   2349         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   2350         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2351         -1,
   2352         -1,
   2353     },
   2354 #endif /* chips */
   2355 
   2356 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2357     { /* SOC_REG_INT_WDT0_WDOGPCELLID1_BCM56440_A0r */
   2358         soc_block_list[1],
   2359         soc_mcsreg,
   2360         1,
   2361         0,
   2362         0x7004ff4,
   2363         SOC_REG_FLAG_RO,
   2364         0,
   2365         1,
   2366         soc_WDT0_WDOGPCELLID1_BCM56440_A0r_fields,
   2367         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   2368         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2369         -1,
   2370         -1,
   2371     },
   2372 #endif /* chips */
   2373 
   2374 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   2375     defined(BCM_56860_A0)
   2376     { /* SOC_REG_INT_WDT0_WDOGPCELLID1_BCM56640_A0r */
   2377         soc_block_list[1],
   2378         soc_mcsreg,
   2379         1,
   2380         0,
   2381         0x7004ff4,
   2382         SOC_REG_FLAG_RO,
   2383         0,
   2384         1,
   2385         soc_WDT0_WDOGPCELLID1_BCM56640_A0r_fields,
   2386         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   2387         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2388         -1,
   2389         -1,
   2390     },
   2391 #endif /* chips */
   2392 
   2393 #if defined(BCM_88202_A0)
   2394     { /* SOC_REG_INT_WDT0_WDOGPCELLID1_BCM88202_A0r */
   2395         soc_block_list[1],
   2396         soc_mcsreg,
   2397         1,
   2398         0,
   2399         0x7004ff4,
   2400         SOC_REG_FLAG_RO,
   2401         0,
   2402         1,
   2403         soc_WDT0_WDOGPCELLID1_BCM88202_A0r_fields,
   2404         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   2405         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2406         -1,
   2407         -1,
   2408     },
   2409 #endif /* chips */
   2410 
   2411 #if defined(BCM_88650_B0)
   2412     { /* SOC_REG_INT_WDT0_WDOGPCELLID1_BCM88650_B0r */
   2413         soc_block_list[1],
   2414         soc_mcsreg,
   2415         1,
   2416         0,
   2417         0x7004ff4,
   2418         SOC_REG_FLAG_RO,
   2419         0,
   2420         1,
   2421         soc_WDT0_WDOGPCELLID1_BCM88650_B0r_fields,
   2422         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   2423         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2424         -1,
   2425         -1,
   2426     },
   2427 #endif /* chips */
   2428 
   2429 #if defined(BCM_88660_A0)
   2430     { /* SOC_REG_INT_WDT0_WDOGPCELLID1_BCM88660_A0r */
   2431         soc_block_list[1],
   2432         soc_mcsreg,
   2433         1,
   2434         0,
   2435         0x7004ff4,
   2436         SOC_REG_FLAG_RO,
   2437         0,
   2438         1,
   2439         soc_WDT0_WDOGPCELLID1_BCM88660_A0r_fields,
   2440         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   2441         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2442         -1,
   2443         -1,
   2444     },
   2445 #endif /* chips */
   2446 
   2447 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2448     { /* SOC_REG_INT_WDT0_WDOGPCELLID2_BCM56440_A0r */
   2449         soc_block_list[1],
   2450         soc_mcsreg,
   2451         1,
   2452         0,
   2453         0x7004ff8,
   2454         SOC_REG_FLAG_RO,
   2455         0,
   2456         1,
   2457         soc_WDT0_WDOGPCELLID2_BCM56440_A0r_fields,
   2458         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2459         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2460         -1,
   2461         -1,
   2462     },
   2463 #endif /* chips */
   2464 
   2465 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   2466     defined(BCM_56860_A0)
   2467     { /* SOC_REG_INT_WDT0_WDOGPCELLID2_BCM56640_A0r */
   2468         soc_block_list[1],
   2469         soc_mcsreg,
   2470         1,
   2471         0,
   2472         0x7004ff8,
   2473         SOC_REG_FLAG_RO,
   2474         0,
   2475         1,
   2476         soc_WDT0_WDOGPCELLID2_BCM56640_A0r_fields,
   2477         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2478         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2479         -1,
   2480         -1,
   2481     },
   2482 #endif /* chips */
   2483 
   2484 #if defined(BCM_88202_A0)
   2485     { /* SOC_REG_INT_WDT0_WDOGPCELLID2_BCM88202_A0r */
   2486         soc_block_list[1],
   2487         soc_mcsreg,
   2488         1,
   2489         0,
   2490         0x7004ff8,
   2491         SOC_REG_FLAG_RO,
   2492         0,
   2493         1,
   2494         soc_WDT0_WDOGPCELLID2_BCM88202_A0r_fields,
   2495         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2496         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2497         -1,
   2498         -1,
   2499     },
   2500 #endif /* chips */
   2501 
   2502 #if defined(BCM_88650_B0)
   2503     { /* SOC_REG_INT_WDT0_WDOGPCELLID2_BCM88650_B0r */
   2504         soc_block_list[1],
   2505         soc_mcsreg,
   2506         1,
   2507         0,
   2508         0x7004ff8,
   2509         SOC_REG_FLAG_RO,
   2510         0,
   2511         1,
   2512         soc_WDT0_WDOGPCELLID2_BCM88650_B0r_fields,
   2513         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2514         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2515         -1,
   2516         -1,
   2517     },
   2518 #endif /* chips */
   2519 
   2520 #if defined(BCM_88660_A0)
   2521     { /* SOC_REG_INT_WDT0_WDOGPCELLID2_BCM88660_A0r */
   2522         soc_block_list[1],
   2523         soc_mcsreg,
   2524         1,
   2525         0,
   2526         0x7004ff8,
   2527         SOC_REG_FLAG_RO,
   2528         0,
   2529         1,
   2530         soc_WDT0_WDOGPCELLID2_BCM88660_A0r_fields,
   2531         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2532         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2533         -1,
   2534         -1,
   2535     },
   2536 #endif /* chips */
   2537 
   2538 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2539     { /* SOC_REG_INT_WDT0_WDOGPCELLID3_BCM56440_A0r */
   2540         soc_block_list[1],
   2541         soc_mcsreg,
   2542         1,
   2543         0,
   2544         0x7004ffc,
   2545         SOC_REG_FLAG_RO,
   2546         0,
   2547         1,
   2548         soc_WDT0_WDOGPCELLID3_BCM56440_A0r_fields,
   2549         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   2550         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2551         -1,
   2552         -1,
   2553     },
   2554 #endif /* chips */
   2555 
   2556 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   2557     defined(BCM_56860_A0)
   2558     { /* SOC_REG_INT_WDT0_WDOGPCELLID3_BCM56640_A0r */
   2559         soc_block_list[1],
   2560         soc_mcsreg,
   2561         1,
   2562         0,
   2563         0x7004ffc,
   2564         SOC_REG_FLAG_RO,
   2565         0,
   2566         1,
   2567         soc_WDT0_WDOGPCELLID3_BCM56640_A0r_fields,
   2568         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   2569         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2570         -1,
   2571         -1,
   2572     },
   2573 #endif /* chips */
   2574 
   2575 #if defined(BCM_88202_A0)
   2576     { /* SOC_REG_INT_WDT0_WDOGPCELLID3_BCM88202_A0r */
   2577         soc_block_list[1],
   2578         soc_mcsreg,
   2579         1,
   2580         0,
   2581         0x7004ffc,
   2582         SOC_REG_FLAG_RO,
   2583         0,
   2584         1,
   2585         soc_WDT0_WDOGPCELLID3_BCM88202_A0r_fields,
   2586         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   2587         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2588         -1,
   2589         -1,
   2590     },
   2591 #endif /* chips */
   2592 
   2593 #if defined(BCM_88650_B0)
   2594     { /* SOC_REG_INT_WDT0_WDOGPCELLID3_BCM88650_B0r */
   2595         soc_block_list[1],
   2596         soc_mcsreg,
   2597         1,
   2598         0,
   2599         0x7004ffc,
   2600         SOC_REG_FLAG_RO,
   2601         0,
   2602         1,
   2603         soc_WDT0_WDOGPCELLID3_BCM88650_B0r_fields,
   2604         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   2605         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2606         -1,
   2607         -1,
   2608     },
   2609 #endif /* chips */
   2610 
   2611 #if defined(BCM_88660_A0)
   2612     { /* SOC_REG_INT_WDT0_WDOGPCELLID3_BCM88660_A0r */
   2613         soc_block_list[1],
   2614         soc_mcsreg,
   2615         1,
   2616         0,
   2617         0x7004ffc,
   2618         SOC_REG_FLAG_RO,
   2619         0,
   2620         1,
   2621         soc_WDT0_WDOGPCELLID3_BCM88660_A0r_fields,
   2622         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   2623         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2624         -1,
   2625         -1,
   2626     },
   2627 #endif /* chips */
   2628 
   2629 #if defined(BCM_88650_A0)
   2630     { /* SOC_REG_INT_WDT0_WDOGPERIPHID0r */
   2631         soc_block_list[1],
   2632         soc_mcsreg,
   2633         1,
   2634         0,
   2635         0x7004fe0,
   2636         SOC_REG_FLAG_RO,
   2637         0,
   2638         1,
   2639         soc_WDT0_WDOGPERIPHID0r_fields,
   2640         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2641         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2642         -1,
   2643         -1,
   2644     },
   2645 #endif /* chips */
   2646 
   2647 #if defined(BCM_88650_A0)
   2648     { /* SOC_REG_INT_WDT0_WDOGPERIPHID1r */
   2649         soc_block_list[1],
   2650         soc_mcsreg,
   2651         1,
   2652         0,
   2653         0x7004fe4,
   2654         SOC_REG_FLAG_RO,
   2655         0,
   2656         1,
   2657         soc_WDT0_WDOGPERIPHID1r_fields,
   2658         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   2659         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2660         -1,
   2661         -1,
   2662     },
   2663 #endif /* chips */
   2664 
   2665 #if defined(BCM_88650_A0)
   2666     { /* SOC_REG_INT_WDT0_WDOGPERIPHID2r */
   2667         soc_block_list[1],
   2668         soc_mcsreg,
   2669         1,
   2670         0,
   2671         0x7004fe8,
   2672         SOC_REG_FLAG_RO,
   2673         0,
   2674         1,
   2675         soc_WDT0_WDOGPERIPHID2r_fields,
   2676         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   2677         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2678         -1,
   2679         -1,
   2680     },
   2681 #endif /* chips */
   2682 
   2683 #if defined(BCM_88650_A0)
   2684     { /* SOC_REG_INT_WDT0_WDOGPERIPHID3r */
   2685         soc_block_list[1],
   2686         soc_mcsreg,
   2687         1,
   2688         0,
   2689         0x7004fec,
   2690         SOC_REG_FLAG_RO,
   2691         0,
   2692         1,
   2693         soc_WDT0_WDOGPERIPHID3r_fields,
   2694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2695         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2696         -1,
   2697         -1,
   2698     },
   2699 #endif /* chips */
   2700 
   2701 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2702     { /* SOC_REG_INT_WDT0_WDOGPERIPHID0_BCM56440_A0r */
   2703         soc_block_list[1],
   2704         soc_mcsreg,
   2705         1,
   2706         0,
   2707         0x7004fe0,
   2708         SOC_REG_FLAG_RO,
   2709         0,
   2710         1,
   2711         soc_WDT0_WDOGPERIPHID0_BCM56440_A0r_fields,
   2712         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2713         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2714         -1,
   2715         -1,
   2716     },
   2717 #endif /* chips */
   2718 
   2719 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   2720     defined(BCM_56860_A0)
   2721     { /* SOC_REG_INT_WDT0_WDOGPERIPHID0_BCM56640_A0r */
   2722         soc_block_list[1],
   2723         soc_mcsreg,
   2724         1,
   2725         0,
   2726         0x7004fe0,
   2727         SOC_REG_FLAG_RO,
   2728         0,
   2729         1,
   2730         soc_WDT0_WDOGPERIPHID0_BCM56640_A0r_fields,
   2731         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2732         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2733         -1,
   2734         -1,
   2735     },
   2736 #endif /* chips */
   2737 
   2738 #if defined(BCM_88202_A0)
   2739     { /* SOC_REG_INT_WDT0_WDOGPERIPHID0_BCM88202_A0r */
   2740         soc_block_list[1],
   2741         soc_mcsreg,
   2742         1,
   2743         0,
   2744         0x7004fe0,
   2745         SOC_REG_FLAG_RO,
   2746         0,
   2747         1,
   2748         soc_WDT0_WDOGPERIPHID0_BCM88202_A0r_fields,
   2749         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2750         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2751         -1,
   2752         -1,
   2753     },
   2754 #endif /* chips */
   2755 
   2756 #if defined(BCM_88650_B0)
   2757     { /* SOC_REG_INT_WDT0_WDOGPERIPHID0_BCM88650_B0r */
   2758         soc_block_list[1],
   2759         soc_mcsreg,
   2760         1,
   2761         0,
   2762         0x7004fe0,
   2763         SOC_REG_FLAG_RO,
   2764         0,
   2765         1,
   2766         soc_WDT0_WDOGPERIPHID0_BCM88650_B0r_fields,
   2767         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2768         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2769         -1,
   2770         -1,
   2771     },
   2772 #endif /* chips */
   2773 
   2774 #if defined(BCM_88660_A0)
   2775     { /* SOC_REG_INT_WDT0_WDOGPERIPHID0_BCM88660_A0r */
   2776         soc_block_list[1],
   2777         soc_mcsreg,
   2778         1,
   2779         0,
   2780         0x7004fe0,
   2781         SOC_REG_FLAG_RO,
   2782         0,
   2783         1,
   2784         soc_WDT0_WDOGPERIPHID0_BCM88660_A0r_fields,
   2785         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   2786         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2787         -1,
   2788         -1,
   2789     },
   2790 #endif /* chips */
   2791 
   2792 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2793     { /* SOC_REG_INT_WDT0_WDOGPERIPHID1_BCM56440_A0r */
   2794         soc_block_list[1],
   2795         soc_mcsreg,
   2796         1,
   2797         0,
   2798         0x7004fe4,
   2799         SOC_REG_FLAG_RO,
   2800         0,
   2801         1,
   2802         soc_WDT0_WDOGPERIPHID1_BCM56440_A0r_fields,
   2803         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   2804         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2805         -1,
   2806         -1,
   2807     },
   2808 #endif /* chips */
   2809 
   2810 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   2811     defined(BCM_56860_A0)
   2812     { /* SOC_REG_INT_WDT0_WDOGPERIPHID1_BCM56640_A0r */
   2813         soc_block_list[1],
   2814         soc_mcsreg,
   2815         1,
   2816         0,
   2817         0x7004fe4,
   2818         SOC_REG_FLAG_RO,
   2819         0,
   2820         1,
   2821         soc_WDT0_WDOGPERIPHID1_BCM56640_A0r_fields,
   2822         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   2823         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2824         -1,
   2825         -1,
   2826     },
   2827 #endif /* chips */
   2828 
   2829 #if defined(BCM_88202_A0)
   2830     { /* SOC_REG_INT_WDT0_WDOGPERIPHID1_BCM88202_A0r */
   2831         soc_block_list[1],
   2832         soc_mcsreg,
   2833         1,
   2834         0,
   2835         0x7004fe4,
   2836         SOC_REG_FLAG_RO,
   2837         0,
   2838         1,
   2839         soc_WDT0_WDOGPERIPHID1_BCM88202_A0r_fields,
   2840         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   2841         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2842         -1,
   2843         -1,
   2844     },
   2845 #endif /* chips */
   2846 
   2847 #if defined(BCM_88650_B0)
   2848     { /* SOC_REG_INT_WDT0_WDOGPERIPHID1_BCM88650_B0r */
   2849         soc_block_list[1],
   2850         soc_mcsreg,
   2851         1,
   2852         0,
   2853         0x7004fe4,
   2854         SOC_REG_FLAG_RO,
   2855         0,
   2856         1,
   2857         soc_WDT0_WDOGPERIPHID1_BCM88650_B0r_fields,
   2858         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   2859         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2860         -1,
   2861         -1,
   2862     },
   2863 #endif /* chips */
   2864 
   2865 #if defined(BCM_88660_A0)
   2866     { /* SOC_REG_INT_WDT0_WDOGPERIPHID1_BCM88660_A0r */
   2867         soc_block_list[1],
   2868         soc_mcsreg,
   2869         1,
   2870         0,
   2871         0x7004fe4,
   2872         SOC_REG_FLAG_RO,
   2873         0,
   2874         1,
   2875         soc_WDT0_WDOGPERIPHID1_BCM88660_A0r_fields,
   2876         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   2877         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2878         -1,
   2879         -1,
   2880     },
   2881 #endif /* chips */
   2882 
   2883 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2884     { /* SOC_REG_INT_WDT0_WDOGPERIPHID2_BCM56440_A0r */
   2885         soc_block_list[1],
   2886         soc_mcsreg,
   2887         1,
   2888         0,
   2889         0x7004fe8,
   2890         SOC_REG_FLAG_RO,
   2891         0,
   2892         1,
   2893         soc_WDT0_WDOGPERIPHID2_BCM56440_A0r_fields,
   2894         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   2895         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2896         -1,
   2897         -1,
   2898     },
   2899 #endif /* chips */
   2900 
   2901 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   2902     defined(BCM_56860_A0)
   2903     { /* SOC_REG_INT_WDT0_WDOGPERIPHID2_BCM56640_A0r */
   2904         soc_block_list[1],
   2905         soc_mcsreg,
   2906         1,
   2907         0,
   2908         0x7004fe8,
   2909         SOC_REG_FLAG_RO,
   2910         0,
   2911         1,
   2912         soc_WDT0_WDOGPERIPHID2_BCM56640_A0r_fields,
   2913         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   2914         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2915         -1,
   2916         -1,
   2917     },
   2918 #endif /* chips */
   2919 
   2920 #if defined(BCM_88202_A0)
   2921     { /* SOC_REG_INT_WDT0_WDOGPERIPHID2_BCM88202_A0r */
   2922         soc_block_list[1],
   2923         soc_mcsreg,
   2924         1,
   2925         0,
   2926         0x7004fe8,
   2927         SOC_REG_FLAG_RO,
   2928         0,
   2929         1,
   2930         soc_WDT0_WDOGPERIPHID2_BCM88202_A0r_fields,
   2931         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   2932         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2933         -1,
   2934         -1,
   2935     },
   2936 #endif /* chips */
   2937 
   2938 #if defined(BCM_88650_B0)
   2939     { /* SOC_REG_INT_WDT0_WDOGPERIPHID2_BCM88650_B0r */
   2940         soc_block_list[1],
   2941         soc_mcsreg,
   2942         1,
   2943         0,
   2944         0x7004fe8,
   2945         SOC_REG_FLAG_RO,
   2946         0,
   2947         1,
   2948         soc_WDT0_WDOGPERIPHID2_BCM88650_B0r_fields,
   2949         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   2950         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2951         -1,
   2952         -1,
   2953     },
   2954 #endif /* chips */
   2955 
   2956 #if defined(BCM_88660_A0)
   2957     { /* SOC_REG_INT_WDT0_WDOGPERIPHID2_BCM88660_A0r */
   2958         soc_block_list[1],
   2959         soc_mcsreg,
   2960         1,
   2961         0,
   2962         0x7004fe8,
   2963         SOC_REG_FLAG_RO,
   2964         0,
   2965         1,
   2966         soc_WDT0_WDOGPERIPHID2_BCM88660_A0r_fields,
   2967         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   2968         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2969         -1,
   2970         -1,
   2971     },
   2972 #endif /* chips */
   2973 
   2974 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2975     { /* SOC_REG_INT_WDT0_WDOGPERIPHID3_BCM56440_A0r */
   2976         soc_block_list[1],
   2977         soc_mcsreg,
   2978         1,
   2979         0,
   2980         0x7004fec,
   2981         SOC_REG_FLAG_RO,
   2982         0,
   2983         1,
   2984         soc_WDT0_WDOGPERIPHID3_BCM56440_A0r_fields,
   2985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2986         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   2987         -1,
   2988         -1,
   2989     },
   2990 #endif /* chips */
   2991 
   2992 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   2993     defined(BCM_56860_A0)
   2994     { /* SOC_REG_INT_WDT0_WDOGPERIPHID3_BCM56640_A0r */
   2995         soc_block_list[1],
   2996         soc_mcsreg,
   2997         1,
   2998         0,
   2999         0x7004fec,
   3000         SOC_REG_FLAG_RO,
   3001         0,
   3002         1,
   3003         soc_WDT0_WDOGPERIPHID3_BCM56640_A0r_fields,
   3004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3005         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   3006         -1,
   3007         -1,
   3008     },
   3009 #endif /* chips */
   3010 
   3011 #if defined(BCM_88202_A0)
   3012     { /* SOC_REG_INT_WDT0_WDOGPERIPHID3_BCM88202_A0r */
   3013         soc_block_list[1],
   3014         soc_mcsreg,
   3015         1,
   3016         0,
   3017         0x7004fec,
   3018         SOC_REG_FLAG_RO,
   3019         0,
   3020         1,
   3021         soc_WDT0_WDOGPERIPHID3_BCM88202_A0r_fields,
   3022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3023         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   3024         -1,
   3025         -1,
   3026     },
   3027 #endif /* chips */
   3028 
   3029 #if defined(BCM_88650_B0)
   3030     { /* SOC_REG_INT_WDT0_WDOGPERIPHID3_BCM88650_B0r */
   3031         soc_block_list[1],
   3032         soc_mcsreg,
   3033         1,
   3034         0,
   3035         0x7004fec,
   3036         SOC_REG_FLAG_RO,
   3037         0,
   3038         1,
   3039         soc_WDT0_WDOGPERIPHID3_BCM88650_B0r_fields,
   3040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3041         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   3042         -1,
   3043         -1,
   3044     },
   3045 #endif /* chips */
   3046 
   3047 #if defined(BCM_88660_A0)
   3048     { /* SOC_REG_INT_WDT0_WDOGPERIPHID3_BCM88660_A0r */
   3049         soc_block_list[1],
   3050         soc_mcsreg,
   3051         1,
   3052         0,
   3053         0x7004fec,
   3054         SOC_REG_FLAG_RO,
   3055         0,
   3056         1,
   3057         soc_WDT0_WDOGPERIPHID3_BCM88660_A0r_fields,
   3058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3059         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   3060         -1,
   3061         -1,
   3062     },
   3063 #endif /* chips */
   3064 
   3065 #if defined(BCM_88650_A0)
   3066     { /* SOC_REG_INT_WDT0_WDOGRISr */
   3067         soc_block_list[1],
   3068         soc_mcsreg,
   3069         1,
   3070         0,
   3071         0x7004010,
   3072         SOC_REG_FLAG_RO,
   3073         0,
   3074         1,
   3075         soc_WDT0_WDOGRISr_fields,
   3076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3077         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3078         -1,
   3079         -1,
   3080     },
   3081 #endif /* chips */
   3082 
   3083 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3084     { /* SOC_REG_INT_WDT0_WDOGRIS_BCM56440_A0r */
   3085         soc_block_list[1],
   3086         soc_mcsreg,
   3087         1,
   3088         0,
   3089         0x7004010,
   3090         SOC_REG_FLAG_RO,
   3091         0,
   3092         1,
   3093         soc_WDT0_WDOGRIS_BCM56440_A0r_fields,
   3094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3095         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3096         -1,
   3097         -1,
   3098     },
   3099 #endif /* chips */
   3100 
   3101 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   3102     defined(BCM_56860_A0)
   3103     { /* SOC_REG_INT_WDT0_WDOGRIS_BCM56640_A0r */
   3104         soc_block_list[1],
   3105         soc_mcsreg,
   3106         1,
   3107         0,
   3108         0x7004010,
   3109         SOC_REG_FLAG_RO,
   3110         0,
   3111         1,
   3112         soc_WDT0_WDOGRIS_BCM56640_A0r_fields,
   3113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3114         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3115         -1,
   3116         -1,
   3117     },
   3118 #endif /* chips */
   3119 
   3120 #if defined(BCM_88202_A0)
   3121     { /* SOC_REG_INT_WDT0_WDOGRIS_BCM88202_A0r */
   3122         soc_block_list[1],
   3123         soc_mcsreg,
   3124         1,
   3125         0,
   3126         0x7004010,
   3127         SOC_REG_FLAG_RO,
   3128         0,
   3129         1,
   3130         soc_WDT0_WDOGRIS_BCM88202_A0r_fields,
   3131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3132         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3133         -1,
   3134         -1,
   3135     },
   3136 #endif /* chips */
   3137 
   3138 #if defined(BCM_88650_B0)
   3139     { /* SOC_REG_INT_WDT0_WDOGRIS_BCM88650_B0r */
   3140         soc_block_list[1],
   3141         soc_mcsreg,
   3142         1,
   3143         0,
   3144         0x7004010,
   3145         SOC_REG_FLAG_RO,
   3146         0,
   3147         1,
   3148         soc_WDT0_WDOGRIS_BCM88650_B0r_fields,
   3149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3150         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3151         -1,
   3152         -1,
   3153     },
   3154 #endif /* chips */
   3155 
   3156 #if defined(BCM_88660_A0)
   3157     { /* SOC_REG_INT_WDT0_WDOGRIS_BCM88660_A0r */
   3158         soc_block_list[1],
   3159         soc_mcsreg,
   3160         1,
   3161         0,
   3162         0x7004010,
   3163         SOC_REG_FLAG_RO,
   3164         0,
   3165         1,
   3166         soc_WDT0_WDOGRIS_BCM88660_A0r_fields,
   3167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3168         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3169         -1,
   3170         -1,
   3171     },
   3172 #endif /* chips */
   3173 
   3174 #if defined(BCM_88650_A0)
   3175     { /* SOC_REG_INT_WDT0_WDOGVALUEr */
   3176         soc_block_list[1],
   3177         soc_mcsreg,
   3178         1,
   3179         0,
   3180         0x7004004,
   3181         SOC_REG_FLAG_RO,
   3182         0,
   3183         1,
   3184         soc_WDT0_WDOGVALUEr_fields,
   3185         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3186         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3187         -1,
   3188         -1,
   3189     },
   3190 #endif /* chips */
   3191 
   3192 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3193     { /* SOC_REG_INT_WDT0_WDOGVALUE_BCM56440_A0r */
   3194         soc_block_list[1],
   3195         soc_mcsreg,
   3196         1,
   3197         0,
   3198         0x7004004,
   3199         SOC_REG_FLAG_RO,
   3200         0,
   3201         1,
   3202         soc_WDT0_WDOGVALUE_BCM56440_A0r_fields,
   3203         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3204         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3205         -1,
   3206         -1,
   3207     },
   3208 #endif /* chips */
   3209 
   3210 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   3211     defined(BCM_56860_A0)
   3212     { /* SOC_REG_INT_WDT0_WDOGVALUE_BCM56640_A0r */
   3213         soc_block_list[1],
   3214         soc_mcsreg,
   3215         1,
   3216         0,
   3217         0x7004004,
   3218         SOC_REG_FLAG_RO,
   3219         0,
   3220         1,
   3221         soc_WDT0_WDOGVALUE_BCM56640_A0r_fields,
   3222         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3223         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3224         -1,
   3225         -1,
   3226     },
   3227 #endif /* chips */
   3228 
   3229 #if defined(BCM_88202_A0)
   3230     { /* SOC_REG_INT_WDT0_WDOGVALUE_BCM88202_A0r */
   3231         soc_block_list[1],
   3232         soc_mcsreg,
   3233         1,
   3234         0,
   3235         0x7004004,
   3236         SOC_REG_FLAG_RO,
   3237         0,
   3238         1,
   3239         soc_WDT0_WDOGVALUE_BCM88202_A0r_fields,
   3240         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3241         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3242         -1,
   3243         -1,
   3244     },
   3245 #endif /* chips */
   3246 
   3247 #if defined(BCM_88650_B0)
   3248     { /* SOC_REG_INT_WDT0_WDOGVALUE_BCM88650_B0r */
   3249         soc_block_list[1],
   3250         soc_mcsreg,
   3251         1,
   3252         0,
   3253         0x7004004,
   3254         SOC_REG_FLAG_RO,
   3255         0,
   3256         1,
   3257         soc_WDT0_WDOGVALUE_BCM88650_B0r_fields,
   3258         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3259         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3260         -1,
   3261         -1,
   3262     },
   3263 #endif /* chips */
   3264 
   3265 #if defined(BCM_88660_A0)
   3266     { /* SOC_REG_INT_WDT0_WDOGVALUE_BCM88660_A0r */
   3267         soc_block_list[1],
   3268         soc_mcsreg,
   3269         1,
   3270         0,
   3271         0x7004004,
   3272         SOC_REG_FLAG_RO,
   3273         0,
   3274         1,
   3275         soc_WDT0_WDOGVALUE_BCM88660_A0r_fields,
   3276         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3277         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3278         -1,
   3279         -1,
   3280     },
   3281 #endif /* chips */
   3282 
   3283 #if defined(BCM_88650_A0)
   3284     { /* SOC_REG_INT_WDT1_WDOGCONTROLr */
   3285         soc_block_list[1],
   3286         soc_mcsreg,
   3287         1,
   3288         0,
   3289         0x7005008,
   3290         0,
   3291         0,
   3292         1,
   3293         soc_WDT1_WDOGCONTROLr_fields,
   3294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3295         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3296         -1,
   3297         -1,
   3298     },
   3299 #endif /* chips */
   3300 
   3301 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3302     { /* SOC_REG_INT_WDT1_WDOGCONTROL_BCM56440_A0r */
   3303         soc_block_list[1],
   3304         soc_mcsreg,
   3305         1,
   3306         0,
   3307         0x7005008,
   3308         0,
   3309         0,
   3310         1,
   3311         soc_WDT0_WDOGCONTROL_BCM56440_A0r_fields,
   3312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3313         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3314         -1,
   3315         -1,
   3316     },
   3317 #endif /* chips */
   3318 
   3319 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   3320     defined(BCM_56860_A0)
   3321     { /* SOC_REG_INT_WDT1_WDOGCONTROL_BCM56640_A0r */
   3322         soc_block_list[1],
   3323         soc_mcsreg,
   3324         1,
   3325         0,
   3326         0x7005008,
   3327         0,
   3328         0,
   3329         1,
   3330         soc_WDT0_WDOGCONTROL_BCM56640_A0r_fields,
   3331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3332         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3333         -1,
   3334         -1,
   3335     },
   3336 #endif /* chips */
   3337 
   3338 #if defined(BCM_88202_A0)
   3339     { /* SOC_REG_INT_WDT1_WDOGCONTROL_BCM88202_A0r */
   3340         soc_block_list[1],
   3341         soc_mcsreg,
   3342         1,
   3343         0,
   3344         0x7005008,
   3345         0,
   3346         0,
   3347         1,
   3348         soc_WDT1_WDOGCONTROL_BCM88202_A0r_fields,
   3349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3350         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3351         -1,
   3352         -1,
   3353     },
   3354 #endif /* chips */
   3355 
   3356 #if defined(BCM_88650_B0)
   3357     { /* SOC_REG_INT_WDT1_WDOGCONTROL_BCM88650_B0r */
   3358         soc_block_list[1],
   3359         soc_mcsreg,
   3360         1,
   3361         0,
   3362         0x7005008,
   3363         0,
   3364         0,
   3365         1,
   3366         soc_WDT1_WDOGCONTROL_BCM88650_B0r_fields,
   3367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3368         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3369         -1,
   3370         -1,
   3371     },
   3372 #endif /* chips */
   3373 
   3374 #if defined(BCM_88660_A0)
   3375     { /* SOC_REG_INT_WDT1_WDOGCONTROL_BCM88660_A0r */
   3376         soc_block_list[1],
   3377         soc_mcsreg,
   3378         1,
   3379         0,
   3380         0x7005008,
   3381         0,
   3382         0,
   3383         1,
   3384         soc_WDT1_WDOGCONTROL_BCM88660_A0r_fields,
   3385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3386         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3387         -1,
   3388         -1,
   3389     },
   3390 #endif /* chips */
   3391 
   3392 #if defined(BCM_88650_A0)
   3393     { /* SOC_REG_INT_WDT1_WDOGINTCLRr */
   3394         soc_block_list[1],
   3395         soc_mcsreg,
   3396         1,
   3397         0,
   3398         0x700500c,
   3399         0,
   3400         0,
   3401         1,
   3402         soc_WDT1_WDOGINTCLRr_fields,
   3403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3404         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3405         -1,
   3406         -1,
   3407     },
   3408 #endif /* chips */
   3409 
   3410 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3411     { /* SOC_REG_INT_WDT1_WDOGINTCLR_BCM56440_A0r */
   3412         soc_block_list[1],
   3413         soc_mcsreg,
   3414         1,
   3415         0,
   3416         0x700500c,
   3417         0,
   3418         0,
   3419         1,
   3420         soc_WDT0_WDOGINTCLR_BCM56440_A0r_fields,
   3421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3422         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3423         -1,
   3424         -1,
   3425     },
   3426 #endif /* chips */
   3427 
   3428 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   3429     defined(BCM_56860_A0)
   3430     { /* SOC_REG_INT_WDT1_WDOGINTCLR_BCM56640_A0r */
   3431         soc_block_list[1],
   3432         soc_mcsreg,
   3433         1,
   3434         0,
   3435         0x700500c,
   3436         0,
   3437         0,
   3438         1,
   3439         soc_WDT0_WDOGINTCLR_BCM56640_A0r_fields,
   3440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3441         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3442         -1,
   3443         -1,
   3444     },
   3445 #endif /* chips */
   3446 
   3447 #if defined(BCM_88202_A0)
   3448     { /* SOC_REG_INT_WDT1_WDOGINTCLR_BCM88202_A0r */
   3449         soc_block_list[1],
   3450         soc_mcsreg,
   3451         1,
   3452         0,
   3453         0x700500c,
   3454         0,
   3455         0,
   3456         1,
   3457         soc_WDT1_WDOGINTCLR_BCM88202_A0r_fields,
   3458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3459         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3460         -1,
   3461         -1,
   3462     },
   3463 #endif /* chips */
   3464 
   3465 #if defined(BCM_88650_B0)
   3466     { /* SOC_REG_INT_WDT1_WDOGINTCLR_BCM88650_B0r */
   3467         soc_block_list[1],
   3468         soc_mcsreg,
   3469         1,
   3470         0,
   3471         0x700500c,
   3472         0,
   3473         0,
   3474         1,
   3475         soc_WDT1_WDOGINTCLR_BCM88650_B0r_fields,
   3476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3477         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3478         -1,
   3479         -1,
   3480     },
   3481 #endif /* chips */
   3482 
   3483 #if defined(BCM_88660_A0)
   3484     { /* SOC_REG_INT_WDT1_WDOGINTCLR_BCM88660_A0r */
   3485         soc_block_list[1],
   3486         soc_mcsreg,
   3487         1,
   3488         0,
   3489         0x700500c,
   3490         0,
   3491         0,
   3492         1,
   3493         soc_WDT1_WDOGINTCLR_BCM88660_A0r_fields,
   3494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3495         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3496         -1,
   3497         -1,
   3498     },
   3499 #endif /* chips */
   3500 
   3501 #if defined(BCM_88650_A0)
   3502     { /* SOC_REG_INT_WDT1_WDOGITCRr */
   3503         soc_block_list[1],
   3504         soc_mcsreg,
   3505         1,
   3506         0,
   3507         0x7005f00,
   3508         0,
   3509         0,
   3510         1,
   3511         soc_WDT1_WDOGITCRr_fields,
   3512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3513         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3514         -1,
   3515         -1,
   3516     },
   3517 #endif /* chips */
   3518 
   3519 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3520     { /* SOC_REG_INT_WDT1_WDOGITCR_BCM56440_A0r */
   3521         soc_block_list[1],
   3522         soc_mcsreg,
   3523         1,
   3524         0,
   3525         0x7005f00,
   3526         0,
   3527         0,
   3528         1,
   3529         soc_WDT0_WDOGITCR_BCM56440_A0r_fields,
   3530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3531         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3532         -1,
   3533         -1,
   3534     },
   3535 #endif /* chips */
   3536 
   3537 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   3538     defined(BCM_56860_A0)
   3539     { /* SOC_REG_INT_WDT1_WDOGITCR_BCM56640_A0r */
   3540         soc_block_list[1],
   3541         soc_mcsreg,
   3542         1,
   3543         0,
   3544         0x7005f00,
   3545         0,
   3546         0,
   3547         1,
   3548         soc_WDT0_WDOGITCR_BCM56640_A0r_fields,
   3549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3550         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3551         -1,
   3552         -1,
   3553     },
   3554 #endif /* chips */
   3555 
   3556 #if defined(BCM_88202_A0)
   3557     { /* SOC_REG_INT_WDT1_WDOGITCR_BCM88202_A0r */
   3558         soc_block_list[1],
   3559         soc_mcsreg,
   3560         1,
   3561         0,
   3562         0x7005f00,
   3563         0,
   3564         0,
   3565         1,
   3566         soc_WDT1_WDOGITCR_BCM88202_A0r_fields,
   3567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3568         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3569         -1,
   3570         -1,
   3571     },
   3572 #endif /* chips */
   3573 
   3574 #if defined(BCM_88650_B0)
   3575     { /* SOC_REG_INT_WDT1_WDOGITCR_BCM88650_B0r */
   3576         soc_block_list[1],
   3577         soc_mcsreg,
   3578         1,
   3579         0,
   3580         0x7005f00,
   3581         0,
   3582         0,
   3583         1,
   3584         soc_WDT1_WDOGITCR_BCM88650_B0r_fields,
   3585         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3586         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3587         -1,
   3588         -1,
   3589     },
   3590 #endif /* chips */
   3591 
   3592 #if defined(BCM_88660_A0)
   3593     { /* SOC_REG_INT_WDT1_WDOGITCR_BCM88660_A0r */
   3594         soc_block_list[1],
   3595         soc_mcsreg,
   3596         1,
   3597         0,
   3598         0x7005f00,
   3599         0,
   3600         0,
   3601         1,
   3602         soc_WDT1_WDOGITCR_BCM88660_A0r_fields,
   3603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3604         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3605         -1,
   3606         -1,
   3607     },
   3608 #endif /* chips */
   3609 
   3610 #if defined(BCM_88650_A0)
   3611     { /* SOC_REG_INT_WDT1_WDOGITOPr */
   3612         soc_block_list[1],
   3613         soc_mcsreg,
   3614         1,
   3615         0,
   3616         0x7005f04,
   3617         0,
   3618         0,
   3619         1,
   3620         soc_WDT1_WDOGITOPr_fields,
   3621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3622         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3623         -1,
   3624         -1,
   3625     },
   3626 #endif /* chips */
   3627 
   3628 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3629     { /* SOC_REG_INT_WDT1_WDOGITOP_BCM56440_A0r */
   3630         soc_block_list[1],
   3631         soc_mcsreg,
   3632         1,
   3633         0,
   3634         0x7005f04,
   3635         0,
   3636         0,
   3637         1,
   3638         soc_WDT0_WDOGITOP_BCM56440_A0r_fields,
   3639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3640         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3641         -1,
   3642         -1,
   3643     },
   3644 #endif /* chips */
   3645 
   3646 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   3647     defined(BCM_56860_A0)
   3648     { /* SOC_REG_INT_WDT1_WDOGITOP_BCM56640_A0r */
   3649         soc_block_list[1],
   3650         soc_mcsreg,
   3651         1,
   3652         0,
   3653         0x7005f04,
   3654         0,
   3655         0,
   3656         1,
   3657         soc_WDT0_WDOGITOP_BCM56640_A0r_fields,
   3658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3659         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3660         -1,
   3661         -1,
   3662     },
   3663 #endif /* chips */
   3664 
   3665 #if defined(BCM_88202_A0)
   3666     { /* SOC_REG_INT_WDT1_WDOGITOP_BCM88202_A0r */
   3667         soc_block_list[1],
   3668         soc_mcsreg,
   3669         1,
   3670         0,
   3671         0x7005f04,
   3672         0,
   3673         0,
   3674         1,
   3675         soc_WDT1_WDOGITOP_BCM88202_A0r_fields,
   3676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3677         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3678         -1,
   3679         -1,
   3680     },
   3681 #endif /* chips */
   3682 
   3683 #if defined(BCM_88650_B0)
   3684     { /* SOC_REG_INT_WDT1_WDOGITOP_BCM88650_B0r */
   3685         soc_block_list[1],
   3686         soc_mcsreg,
   3687         1,
   3688         0,
   3689         0x7005f04,
   3690         0,
   3691         0,
   3692         1,
   3693         soc_WDT1_WDOGITOP_BCM88650_B0r_fields,
   3694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3695         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3696         -1,
   3697         -1,
   3698     },
   3699 #endif /* chips */
   3700 
   3701 #if defined(BCM_88660_A0)
   3702     { /* SOC_REG_INT_WDT1_WDOGITOP_BCM88660_A0r */
   3703         soc_block_list[1],
   3704         soc_mcsreg,
   3705         1,
   3706         0,
   3707         0x7005f04,
   3708         0,
   3709         0,
   3710         1,
   3711         soc_WDT1_WDOGITOP_BCM88660_A0r_fields,
   3712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3713         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   3714         -1,
   3715         -1,
   3716     },
   3717 #endif /* chips */
   3718 
   3719 #if defined(BCM_88650_A0)
   3720     { /* SOC_REG_INT_WDT1_WDOGLOADr */
   3721         soc_block_list[1],
   3722         soc_mcsreg,
   3723         1,
   3724         0,
   3725         0x7005000,
   3726         0,
   3727         0,
   3728         1,
   3729         soc_WDT1_WDOGLOADr_fields,
   3730         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3731         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3732         -1,
   3733         -1,
   3734     },
   3735 #endif /* chips */
   3736 
   3737 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3738     { /* SOC_REG_INT_WDT1_WDOGLOAD_BCM56440_A0r */
   3739         soc_block_list[1],
   3740         soc_mcsreg,
   3741         1,
   3742         0,
   3743         0x7005000,
   3744         0,
   3745         0,
   3746         1,
   3747         soc_WDT0_WDOGLOAD_BCM56440_A0r_fields,
   3748         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3749         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3750         -1,
   3751         -1,
   3752     },
   3753 #endif /* chips */
   3754 
   3755 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   3756     defined(BCM_56860_A0)
   3757     { /* SOC_REG_INT_WDT1_WDOGLOAD_BCM56640_A0r */
   3758         soc_block_list[1],
   3759         soc_mcsreg,
   3760         1,
   3761         0,
   3762         0x7005000,
   3763         0,
   3764         0,
   3765         1,
   3766         soc_WDT0_WDOGLOAD_BCM56640_A0r_fields,
   3767         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3768         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3769         -1,
   3770         -1,
   3771     },
   3772 #endif /* chips */
   3773 
   3774 #if defined(BCM_88202_A0)
   3775     { /* SOC_REG_INT_WDT1_WDOGLOAD_BCM88202_A0r */
   3776         soc_block_list[1],
   3777         soc_mcsreg,
   3778         1,
   3779         0,
   3780         0x7005000,
   3781         0,
   3782         0,
   3783         1,
   3784         soc_WDT1_WDOGLOAD_BCM88202_A0r_fields,
   3785         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3786         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3787         -1,
   3788         -1,
   3789     },
   3790 #endif /* chips */
   3791 
   3792 #if defined(BCM_88650_B0)
   3793     { /* SOC_REG_INT_WDT1_WDOGLOAD_BCM88650_B0r */
   3794         soc_block_list[1],
   3795         soc_mcsreg,
   3796         1,
   3797         0,
   3798         0x7005000,
   3799         0,
   3800         0,
   3801         1,
   3802         soc_WDT1_WDOGLOAD_BCM88650_B0r_fields,
   3803         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3804         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3805         -1,
   3806         -1,
   3807     },
   3808 #endif /* chips */
   3809 
   3810 #if defined(BCM_88660_A0)
   3811     { /* SOC_REG_INT_WDT1_WDOGLOAD_BCM88660_A0r */
   3812         soc_block_list[1],
   3813         soc_mcsreg,
   3814         1,
   3815         0,
   3816         0x7005000,
   3817         0,
   3818         0,
   3819         1,
   3820         soc_WDT1_WDOGLOAD_BCM88660_A0r_fields,
   3821         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3822         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3823         -1,
   3824         -1,
   3825     },
   3826 #endif /* chips */
   3827 
   3828 #if defined(BCM_88650_A0)
   3829     { /* SOC_REG_INT_WDT1_WDOGLOCKr */
   3830         soc_block_list[1],
   3831         soc_mcsreg,
   3832         1,
   3833         0,
   3834         0x7005c00,
   3835         0,
   3836         0,
   3837         1,
   3838         soc_WDT1_WDOGLOCKr_fields,
   3839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3840         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3841         -1,
   3842         -1,
   3843     },
   3844 #endif /* chips */
   3845 
   3846 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3847     { /* SOC_REG_INT_WDT1_WDOGLOCK_BCM56440_A0r */
   3848         soc_block_list[1],
   3849         soc_mcsreg,
   3850         1,
   3851         0,
   3852         0x7005c00,
   3853         0,
   3854         0,
   3855         1,
   3856         soc_WDT0_WDOGLOCK_BCM56440_A0r_fields,
   3857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3858         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3859         -1,
   3860         -1,
   3861     },
   3862 #endif /* chips */
   3863 
   3864 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   3865     defined(BCM_56860_A0)
   3866     { /* SOC_REG_INT_WDT1_WDOGLOCK_BCM56640_A0r */
   3867         soc_block_list[1],
   3868         soc_mcsreg,
   3869         1,
   3870         0,
   3871         0x7005c00,
   3872         0,
   3873         0,
   3874         1,
   3875         soc_WDT0_WDOGLOCK_BCM56640_A0r_fields,
   3876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3878         -1,
   3879         -1,
   3880     },
   3881 #endif /* chips */
   3882 
   3883 #if defined(BCM_88202_A0)
   3884     { /* SOC_REG_INT_WDT1_WDOGLOCK_BCM88202_A0r */
   3885         soc_block_list[1],
   3886         soc_mcsreg,
   3887         1,
   3888         0,
   3889         0x7005c00,
   3890         0,
   3891         0,
   3892         1,
   3893         soc_WDT1_WDOGLOCK_BCM88202_A0r_fields,
   3894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3895         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3896         -1,
   3897         -1,
   3898     },
   3899 #endif /* chips */
   3900 
   3901 #if defined(BCM_88650_B0)
   3902     { /* SOC_REG_INT_WDT1_WDOGLOCK_BCM88650_B0r */
   3903         soc_block_list[1],
   3904         soc_mcsreg,
   3905         1,
   3906         0,
   3907         0x7005c00,
   3908         0,
   3909         0,
   3910         1,
   3911         soc_WDT1_WDOGLOCK_BCM88650_B0r_fields,
   3912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3913         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3914         -1,
   3915         -1,
   3916     },
   3917 #endif /* chips */
   3918 
   3919 #if defined(BCM_88660_A0)
   3920     { /* SOC_REG_INT_WDT1_WDOGLOCK_BCM88660_A0r */
   3921         soc_block_list[1],
   3922         soc_mcsreg,
   3923         1,
   3924         0,
   3925         0x7005c00,
   3926         0,
   3927         0,
   3928         1,
   3929         soc_WDT1_WDOGLOCK_BCM88660_A0r_fields,
   3930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3931         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3932         -1,
   3933         -1,
   3934     },
   3935 #endif /* chips */
   3936 
   3937 #if defined(BCM_88650_A0)
   3938     { /* SOC_REG_INT_WDT1_WDOGMISr */
   3939         soc_block_list[1],
   3940         soc_mcsreg,
   3941         1,
   3942         0,
   3943         0x7005014,
   3944         SOC_REG_FLAG_RO,
   3945         0,
   3946         1,
   3947         soc_WDT1_WDOGMISr_fields,
   3948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3949         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3950         -1,
   3951         -1,
   3952     },
   3953 #endif /* chips */
   3954 
   3955 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3956     { /* SOC_REG_INT_WDT1_WDOGMIS_BCM56440_A0r */
   3957         soc_block_list[1],
   3958         soc_mcsreg,
   3959         1,
   3960         0,
   3961         0x7005014,
   3962         SOC_REG_FLAG_RO,
   3963         0,
   3964         1,
   3965         soc_WDT0_WDOGMIS_BCM56440_A0r_fields,
   3966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3967         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3968         -1,
   3969         -1,
   3970     },
   3971 #endif /* chips */
   3972 
   3973 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   3974     defined(BCM_56860_A0)
   3975     { /* SOC_REG_INT_WDT1_WDOGMIS_BCM56640_A0r */
   3976         soc_block_list[1],
   3977         soc_mcsreg,
   3978         1,
   3979         0,
   3980         0x7005014,
   3981         SOC_REG_FLAG_RO,
   3982         0,
   3983         1,
   3984         soc_WDT0_WDOGMIS_BCM56640_A0r_fields,
   3985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3986         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3987         -1,
   3988         -1,
   3989     },
   3990 #endif /* chips */
   3991 
   3992 #if defined(BCM_88202_A0)
   3993     { /* SOC_REG_INT_WDT1_WDOGMIS_BCM88202_A0r */
   3994         soc_block_list[1],
   3995         soc_mcsreg,
   3996         1,
   3997         0,
   3998         0x7005014,
   3999         SOC_REG_FLAG_RO,
   4000         0,
   4001         1,
   4002         soc_WDT1_WDOGMIS_BCM88202_A0r_fields,
   4003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4004         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4005         -1,
   4006         -1,
   4007     },
   4008 #endif /* chips */
   4009 
   4010 #if defined(BCM_88650_B0)
   4011     { /* SOC_REG_INT_WDT1_WDOGMIS_BCM88650_B0r */
   4012         soc_block_list[1],
   4013         soc_mcsreg,
   4014         1,
   4015         0,
   4016         0x7005014,
   4017         SOC_REG_FLAG_RO,
   4018         0,
   4019         1,
   4020         soc_WDT1_WDOGMIS_BCM88650_B0r_fields,
   4021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4022         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4023         -1,
   4024         -1,
   4025     },
   4026 #endif /* chips */
   4027 
   4028 #if defined(BCM_88660_A0)
   4029     { /* SOC_REG_INT_WDT1_WDOGMIS_BCM88660_A0r */
   4030         soc_block_list[1],
   4031         soc_mcsreg,
   4032         1,
   4033         0,
   4034         0x7005014,
   4035         SOC_REG_FLAG_RO,
   4036         0,
   4037         1,
   4038         soc_WDT1_WDOGMIS_BCM88660_A0r_fields,
   4039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4040         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4041         -1,
   4042         -1,
   4043     },
   4044 #endif /* chips */
   4045 
   4046 #if defined(BCM_88650_A0)
   4047     { /* SOC_REG_INT_WDT1_WDOGPCELLID0r */
   4048         soc_block_list[1],
   4049         soc_mcsreg,
   4050         1,
   4051         0,
   4052         0x7005ff0,
   4053         SOC_REG_FLAG_RO,
   4054         0,
   4055         1,
   4056         soc_WDT1_WDOGPCELLID0r_fields,
   4057         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   4058         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4059         -1,
   4060         -1,
   4061     },
   4062 #endif /* chips */
   4063 
   4064 #if defined(BCM_88650_A0)
   4065     { /* SOC_REG_INT_WDT1_WDOGPCELLID1r */
   4066         soc_block_list[1],
   4067         soc_mcsreg,
   4068         1,
   4069         0,
   4070         0x7005ff4,
   4071         SOC_REG_FLAG_RO,
   4072         0,
   4073         1,
   4074         soc_WDT1_WDOGPCELLID1r_fields,
   4075         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   4076         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4077         -1,
   4078         -1,
   4079     },
   4080 #endif /* chips */
   4081 
   4082 #if defined(BCM_88650_A0)
   4083     { /* SOC_REG_INT_WDT1_WDOGPCELLID2r */
   4084         soc_block_list[1],
   4085         soc_mcsreg,
   4086         1,
   4087         0,
   4088         0x7005ff8,
   4089         SOC_REG_FLAG_RO,
   4090         0,
   4091         1,
   4092         soc_WDT1_WDOGPCELLID2r_fields,
   4093         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4094         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4095         -1,
   4096         -1,
   4097     },
   4098 #endif /* chips */
   4099 
   4100 #if defined(BCM_88650_A0)
   4101     { /* SOC_REG_INT_WDT1_WDOGPCELLID3r */
   4102         soc_block_list[1],
   4103         soc_mcsreg,
   4104         1,
   4105         0,
   4106         0x7005ffc,
   4107         SOC_REG_FLAG_RO,
   4108         0,
   4109         1,
   4110         soc_WDT1_WDOGPCELLID3r_fields,
   4111         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   4112         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4113         -1,
   4114         -1,
   4115     },
   4116 #endif /* chips */
   4117 
   4118 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4119     { /* SOC_REG_INT_WDT1_WDOGPCELLID0_BCM56440_A0r */
   4120         soc_block_list[1],
   4121         soc_mcsreg,
   4122         1,
   4123         0,
   4124         0x7005ff0,
   4125         SOC_REG_FLAG_RO,
   4126         0,
   4127         1,
   4128         soc_WDT0_WDOGPCELLID0_BCM56440_A0r_fields,
   4129         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   4130         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4131         -1,
   4132         -1,
   4133     },
   4134 #endif /* chips */
   4135 
   4136 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4137     defined(BCM_56860_A0)
   4138     { /* SOC_REG_INT_WDT1_WDOGPCELLID0_BCM56640_A0r */
   4139         soc_block_list[1],
   4140         soc_mcsreg,
   4141         1,
   4142         0,
   4143         0x7005ff0,
   4144         SOC_REG_FLAG_RO,
   4145         0,
   4146         1,
   4147         soc_WDT0_WDOGPCELLID0_BCM56640_A0r_fields,
   4148         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   4149         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4150         -1,
   4151         -1,
   4152     },
   4153 #endif /* chips */
   4154 
   4155 #if defined(BCM_88202_A0)
   4156     { /* SOC_REG_INT_WDT1_WDOGPCELLID0_BCM88202_A0r */
   4157         soc_block_list[1],
   4158         soc_mcsreg,
   4159         1,
   4160         0,
   4161         0x7005ff0,
   4162         SOC_REG_FLAG_RO,
   4163         0,
   4164         1,
   4165         soc_WDT1_WDOGPCELLID0_BCM88202_A0r_fields,
   4166         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   4167         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4168         -1,
   4169         -1,
   4170     },
   4171 #endif /* chips */
   4172 
   4173 #if defined(BCM_88650_B0)
   4174     { /* SOC_REG_INT_WDT1_WDOGPCELLID0_BCM88650_B0r */
   4175         soc_block_list[1],
   4176         soc_mcsreg,
   4177         1,
   4178         0,
   4179         0x7005ff0,
   4180         SOC_REG_FLAG_RO,
   4181         0,
   4182         1,
   4183         soc_WDT1_WDOGPCELLID0_BCM88650_B0r_fields,
   4184         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   4185         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4186         -1,
   4187         -1,
   4188     },
   4189 #endif /* chips */
   4190 
   4191 #if defined(BCM_88660_A0)
   4192     { /* SOC_REG_INT_WDT1_WDOGPCELLID0_BCM88660_A0r */
   4193         soc_block_list[1],
   4194         soc_mcsreg,
   4195         1,
   4196         0,
   4197         0x7005ff0,
   4198         SOC_REG_FLAG_RO,
   4199         0,
   4200         1,
   4201         soc_WDT1_WDOGPCELLID0_BCM88660_A0r_fields,
   4202         SOC_RESET_VAL_DEC(0x0000000d, 0x00000000)
   4203         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4204         -1,
   4205         -1,
   4206     },
   4207 #endif /* chips */
   4208 
   4209 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4210     { /* SOC_REG_INT_WDT1_WDOGPCELLID1_BCM56440_A0r */
   4211         soc_block_list[1],
   4212         soc_mcsreg,
   4213         1,
   4214         0,
   4215         0x7005ff4,
   4216         SOC_REG_FLAG_RO,
   4217         0,
   4218         1,
   4219         soc_WDT0_WDOGPCELLID1_BCM56440_A0r_fields,
   4220         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   4221         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4222         -1,
   4223         -1,
   4224     },
   4225 #endif /* chips */
   4226 
   4227 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4228     defined(BCM_56860_A0)
   4229     { /* SOC_REG_INT_WDT1_WDOGPCELLID1_BCM56640_A0r */
   4230         soc_block_list[1],
   4231         soc_mcsreg,
   4232         1,
   4233         0,
   4234         0x7005ff4,
   4235         SOC_REG_FLAG_RO,
   4236         0,
   4237         1,
   4238         soc_WDT0_WDOGPCELLID1_BCM56640_A0r_fields,
   4239         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   4240         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4241         -1,
   4242         -1,
   4243     },
   4244 #endif /* chips */
   4245 
   4246 #if defined(BCM_88202_A0)
   4247     { /* SOC_REG_INT_WDT1_WDOGPCELLID1_BCM88202_A0r */
   4248         soc_block_list[1],
   4249         soc_mcsreg,
   4250         1,
   4251         0,
   4252         0x7005ff4,
   4253         SOC_REG_FLAG_RO,
   4254         0,
   4255         1,
   4256         soc_WDT1_WDOGPCELLID1_BCM88202_A0r_fields,
   4257         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   4258         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4259         -1,
   4260         -1,
   4261     },
   4262 #endif /* chips */
   4263 
   4264 #if defined(BCM_88650_B0)
   4265     { /* SOC_REG_INT_WDT1_WDOGPCELLID1_BCM88650_B0r */
   4266         soc_block_list[1],
   4267         soc_mcsreg,
   4268         1,
   4269         0,
   4270         0x7005ff4,
   4271         SOC_REG_FLAG_RO,
   4272         0,
   4273         1,
   4274         soc_WDT1_WDOGPCELLID1_BCM88650_B0r_fields,
   4275         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   4276         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4277         -1,
   4278         -1,
   4279     },
   4280 #endif /* chips */
   4281 
   4282 #if defined(BCM_88660_A0)
   4283     { /* SOC_REG_INT_WDT1_WDOGPCELLID1_BCM88660_A0r */
   4284         soc_block_list[1],
   4285         soc_mcsreg,
   4286         1,
   4287         0,
   4288         0x7005ff4,
   4289         SOC_REG_FLAG_RO,
   4290         0,
   4291         1,
   4292         soc_WDT1_WDOGPCELLID1_BCM88660_A0r_fields,
   4293         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
   4294         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4295         -1,
   4296         -1,
   4297     },
   4298 #endif /* chips */
   4299 
   4300 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4301     { /* SOC_REG_INT_WDT1_WDOGPCELLID2_BCM56440_A0r */
   4302         soc_block_list[1],
   4303         soc_mcsreg,
   4304         1,
   4305         0,
   4306         0x7005ff8,
   4307         SOC_REG_FLAG_RO,
   4308         0,
   4309         1,
   4310         soc_WDT0_WDOGPCELLID2_BCM56440_A0r_fields,
   4311         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4312         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4313         -1,
   4314         -1,
   4315     },
   4316 #endif /* chips */
   4317 
   4318 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4319     defined(BCM_56860_A0)
   4320     { /* SOC_REG_INT_WDT1_WDOGPCELLID2_BCM56640_A0r */
   4321         soc_block_list[1],
   4322         soc_mcsreg,
   4323         1,
   4324         0,
   4325         0x7005ff8,
   4326         SOC_REG_FLAG_RO,
   4327         0,
   4328         1,
   4329         soc_WDT0_WDOGPCELLID2_BCM56640_A0r_fields,
   4330         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4331         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4332         -1,
   4333         -1,
   4334     },
   4335 #endif /* chips */
   4336 
   4337 #if defined(BCM_88202_A0)
   4338     { /* SOC_REG_INT_WDT1_WDOGPCELLID2_BCM88202_A0r */
   4339         soc_block_list[1],
   4340         soc_mcsreg,
   4341         1,
   4342         0,
   4343         0x7005ff8,
   4344         SOC_REG_FLAG_RO,
   4345         0,
   4346         1,
   4347         soc_WDT1_WDOGPCELLID2_BCM88202_A0r_fields,
   4348         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4349         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4350         -1,
   4351         -1,
   4352     },
   4353 #endif /* chips */
   4354 
   4355 #if defined(BCM_88650_B0)
   4356     { /* SOC_REG_INT_WDT1_WDOGPCELLID2_BCM88650_B0r */
   4357         soc_block_list[1],
   4358         soc_mcsreg,
   4359         1,
   4360         0,
   4361         0x7005ff8,
   4362         SOC_REG_FLAG_RO,
   4363         0,
   4364         1,
   4365         soc_WDT1_WDOGPCELLID2_BCM88650_B0r_fields,
   4366         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4367         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4368         -1,
   4369         -1,
   4370     },
   4371 #endif /* chips */
   4372 
   4373 #if defined(BCM_88660_A0)
   4374     { /* SOC_REG_INT_WDT1_WDOGPCELLID2_BCM88660_A0r */
   4375         soc_block_list[1],
   4376         soc_mcsreg,
   4377         1,
   4378         0,
   4379         0x7005ff8,
   4380         SOC_REG_FLAG_RO,
   4381         0,
   4382         1,
   4383         soc_WDT1_WDOGPCELLID2_BCM88660_A0r_fields,
   4384         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4385         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4386         -1,
   4387         -1,
   4388     },
   4389 #endif /* chips */
   4390 
   4391 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4392     { /* SOC_REG_INT_WDT1_WDOGPCELLID3_BCM56440_A0r */
   4393         soc_block_list[1],
   4394         soc_mcsreg,
   4395         1,
   4396         0,
   4397         0x7005ffc,
   4398         SOC_REG_FLAG_RO,
   4399         0,
   4400         1,
   4401         soc_WDT0_WDOGPCELLID3_BCM56440_A0r_fields,
   4402         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   4403         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4404         -1,
   4405         -1,
   4406     },
   4407 #endif /* chips */
   4408 
   4409 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4410     defined(BCM_56860_A0)
   4411     { /* SOC_REG_INT_WDT1_WDOGPCELLID3_BCM56640_A0r */
   4412         soc_block_list[1],
   4413         soc_mcsreg,
   4414         1,
   4415         0,
   4416         0x7005ffc,
   4417         SOC_REG_FLAG_RO,
   4418         0,
   4419         1,
   4420         soc_WDT0_WDOGPCELLID3_BCM56640_A0r_fields,
   4421         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   4422         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4423         -1,
   4424         -1,
   4425     },
   4426 #endif /* chips */
   4427 
   4428 #if defined(BCM_88202_A0)
   4429     { /* SOC_REG_INT_WDT1_WDOGPCELLID3_BCM88202_A0r */
   4430         soc_block_list[1],
   4431         soc_mcsreg,
   4432         1,
   4433         0,
   4434         0x7005ffc,
   4435         SOC_REG_FLAG_RO,
   4436         0,
   4437         1,
   4438         soc_WDT1_WDOGPCELLID3_BCM88202_A0r_fields,
   4439         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   4440         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4441         -1,
   4442         -1,
   4443     },
   4444 #endif /* chips */
   4445 
   4446 #if defined(BCM_88650_B0)
   4447     { /* SOC_REG_INT_WDT1_WDOGPCELLID3_BCM88650_B0r */
   4448         soc_block_list[1],
   4449         soc_mcsreg,
   4450         1,
   4451         0,
   4452         0x7005ffc,
   4453         SOC_REG_FLAG_RO,
   4454         0,
   4455         1,
   4456         soc_WDT1_WDOGPCELLID3_BCM88650_B0r_fields,
   4457         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   4458         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4459         -1,
   4460         -1,
   4461     },
   4462 #endif /* chips */
   4463 
   4464 #if defined(BCM_88660_A0)
   4465     { /* SOC_REG_INT_WDT1_WDOGPCELLID3_BCM88660_A0r */
   4466         soc_block_list[1],
   4467         soc_mcsreg,
   4468         1,
   4469         0,
   4470         0x7005ffc,
   4471         SOC_REG_FLAG_RO,
   4472         0,
   4473         1,
   4474         soc_WDT1_WDOGPCELLID3_BCM88660_A0r_fields,
   4475         SOC_RESET_VAL_DEC(0x000000b1, 0x00000000)
   4476         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4477         -1,
   4478         -1,
   4479     },
   4480 #endif /* chips */
   4481 
   4482 #if defined(BCM_88650_A0)
   4483     { /* SOC_REG_INT_WDT1_WDOGPERIPHID0r */
   4484         soc_block_list[1],
   4485         soc_mcsreg,
   4486         1,
   4487         0,
   4488         0x7005fe0,
   4489         SOC_REG_FLAG_RO,
   4490         0,
   4491         1,
   4492         soc_WDT1_WDOGPERIPHID0r_fields,
   4493         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4494         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4495         -1,
   4496         -1,
   4497     },
   4498 #endif /* chips */
   4499 
   4500 #if defined(BCM_88650_A0)
   4501     { /* SOC_REG_INT_WDT1_WDOGPERIPHID1r */
   4502         soc_block_list[1],
   4503         soc_mcsreg,
   4504         1,
   4505         0,
   4506         0x7005fe4,
   4507         SOC_REG_FLAG_RO,
   4508         0,
   4509         1,
   4510         soc_WDT1_WDOGPERIPHID1r_fields,
   4511         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   4512         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4513         -1,
   4514         -1,
   4515     },
   4516 #endif /* chips */
   4517 
   4518 #if defined(BCM_88650_A0)
   4519     { /* SOC_REG_INT_WDT1_WDOGPERIPHID2r */
   4520         soc_block_list[1],
   4521         soc_mcsreg,
   4522         1,
   4523         0,
   4524         0x7005fe8,
   4525         SOC_REG_FLAG_RO,
   4526         0,
   4527         1,
   4528         soc_WDT1_WDOGPERIPHID2r_fields,
   4529         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   4530         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4531         -1,
   4532         -1,
   4533     },
   4534 #endif /* chips */
   4535 
   4536 #if defined(BCM_88650_A0)
   4537     { /* SOC_REG_INT_WDT1_WDOGPERIPHID3r */
   4538         soc_block_list[1],
   4539         soc_mcsreg,
   4540         1,
   4541         0,
   4542         0x7005fec,
   4543         SOC_REG_FLAG_RO,
   4544         0,
   4545         1,
   4546         soc_WDT1_WDOGPERIPHID3r_fields,
   4547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4548         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4549         -1,
   4550         -1,
   4551     },
   4552 #endif /* chips */
   4553 
   4554 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4555     { /* SOC_REG_INT_WDT1_WDOGPERIPHID0_BCM56440_A0r */
   4556         soc_block_list[1],
   4557         soc_mcsreg,
   4558         1,
   4559         0,
   4560         0x7005fe0,
   4561         SOC_REG_FLAG_RO,
   4562         0,
   4563         1,
   4564         soc_WDT0_WDOGPERIPHID0_BCM56440_A0r_fields,
   4565         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4566         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4567         -1,
   4568         -1,
   4569     },
   4570 #endif /* chips */
   4571 
   4572 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4573     defined(BCM_56860_A0)
   4574     { /* SOC_REG_INT_WDT1_WDOGPERIPHID0_BCM56640_A0r */
   4575         soc_block_list[1],
   4576         soc_mcsreg,
   4577         1,
   4578         0,
   4579         0x7005fe0,
   4580         SOC_REG_FLAG_RO,
   4581         0,
   4582         1,
   4583         soc_WDT0_WDOGPERIPHID0_BCM56640_A0r_fields,
   4584         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4585         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4586         -1,
   4587         -1,
   4588     },
   4589 #endif /* chips */
   4590 
   4591 #if defined(BCM_88202_A0)
   4592     { /* SOC_REG_INT_WDT1_WDOGPERIPHID0_BCM88202_A0r */
   4593         soc_block_list[1],
   4594         soc_mcsreg,
   4595         1,
   4596         0,
   4597         0x7005fe0,
   4598         SOC_REG_FLAG_RO,
   4599         0,
   4600         1,
   4601         soc_WDT1_WDOGPERIPHID0_BCM88202_A0r_fields,
   4602         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4603         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4604         -1,
   4605         -1,
   4606     },
   4607 #endif /* chips */
   4608 
   4609 #if defined(BCM_88650_B0)
   4610     { /* SOC_REG_INT_WDT1_WDOGPERIPHID0_BCM88650_B0r */
   4611         soc_block_list[1],
   4612         soc_mcsreg,
   4613         1,
   4614         0,
   4615         0x7005fe0,
   4616         SOC_REG_FLAG_RO,
   4617         0,
   4618         1,
   4619         soc_WDT1_WDOGPERIPHID0_BCM88650_B0r_fields,
   4620         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4621         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4622         -1,
   4623         -1,
   4624     },
   4625 #endif /* chips */
   4626 
   4627 #if defined(BCM_88660_A0)
   4628     { /* SOC_REG_INT_WDT1_WDOGPERIPHID0_BCM88660_A0r */
   4629         soc_block_list[1],
   4630         soc_mcsreg,
   4631         1,
   4632         0,
   4633         0x7005fe0,
   4634         SOC_REG_FLAG_RO,
   4635         0,
   4636         1,
   4637         soc_WDT1_WDOGPERIPHID0_BCM88660_A0r_fields,
   4638         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
   4639         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4640         -1,
   4641         -1,
   4642     },
   4643 #endif /* chips */
   4644 
   4645 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4646     { /* SOC_REG_INT_WDT1_WDOGPERIPHID1_BCM56440_A0r */
   4647         soc_block_list[1],
   4648         soc_mcsreg,
   4649         1,
   4650         0,
   4651         0x7005fe4,
   4652         SOC_REG_FLAG_RO,
   4653         0,
   4654         1,
   4655         soc_WDT0_WDOGPERIPHID1_BCM56440_A0r_fields,
   4656         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   4657         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4658         -1,
   4659         -1,
   4660     },
   4661 #endif /* chips */
   4662 
   4663 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4664     defined(BCM_56860_A0)
   4665     { /* SOC_REG_INT_WDT1_WDOGPERIPHID1_BCM56640_A0r */
   4666         soc_block_list[1],
   4667         soc_mcsreg,
   4668         1,
   4669         0,
   4670         0x7005fe4,
   4671         SOC_REG_FLAG_RO,
   4672         0,
   4673         1,
   4674         soc_WDT0_WDOGPERIPHID1_BCM56640_A0r_fields,
   4675         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   4676         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4677         -1,
   4678         -1,
   4679     },
   4680 #endif /* chips */
   4681 
   4682 #if defined(BCM_88202_A0)
   4683     { /* SOC_REG_INT_WDT1_WDOGPERIPHID1_BCM88202_A0r */
   4684         soc_block_list[1],
   4685         soc_mcsreg,
   4686         1,
   4687         0,
   4688         0x7005fe4,
   4689         SOC_REG_FLAG_RO,
   4690         0,
   4691         1,
   4692         soc_WDT1_WDOGPERIPHID1_BCM88202_A0r_fields,
   4693         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   4694         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4695         -1,
   4696         -1,
   4697     },
   4698 #endif /* chips */
   4699 
   4700 #if defined(BCM_88650_B0)
   4701     { /* SOC_REG_INT_WDT1_WDOGPERIPHID1_BCM88650_B0r */
   4702         soc_block_list[1],
   4703         soc_mcsreg,
   4704         1,
   4705         0,
   4706         0x7005fe4,
   4707         SOC_REG_FLAG_RO,
   4708         0,
   4709         1,
   4710         soc_WDT1_WDOGPERIPHID1_BCM88650_B0r_fields,
   4711         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   4712         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4713         -1,
   4714         -1,
   4715     },
   4716 #endif /* chips */
   4717 
   4718 #if defined(BCM_88660_A0)
   4719     { /* SOC_REG_INT_WDT1_WDOGPERIPHID1_BCM88660_A0r */
   4720         soc_block_list[1],
   4721         soc_mcsreg,
   4722         1,
   4723         0,
   4724         0x7005fe4,
   4725         SOC_REG_FLAG_RO,
   4726         0,
   4727         1,
   4728         soc_WDT1_WDOGPERIPHID1_BCM88660_A0r_fields,
   4729         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
   4730         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4731         -1,
   4732         -1,
   4733     },
   4734 #endif /* chips */
   4735 
   4736 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4737     { /* SOC_REG_INT_WDT1_WDOGPERIPHID2_BCM56440_A0r */
   4738         soc_block_list[1],
   4739         soc_mcsreg,
   4740         1,
   4741         0,
   4742         0x7005fe8,
   4743         SOC_REG_FLAG_RO,
   4744         0,
   4745         1,
   4746         soc_WDT0_WDOGPERIPHID2_BCM56440_A0r_fields,
   4747         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   4748         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4749         -1,
   4750         -1,
   4751     },
   4752 #endif /* chips */
   4753 
   4754 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4755     defined(BCM_56860_A0)
   4756     { /* SOC_REG_INT_WDT1_WDOGPERIPHID2_BCM56640_A0r */
   4757         soc_block_list[1],
   4758         soc_mcsreg,
   4759         1,
   4760         0,
   4761         0x7005fe8,
   4762         SOC_REG_FLAG_RO,
   4763         0,
   4764         1,
   4765         soc_WDT0_WDOGPERIPHID2_BCM56640_A0r_fields,
   4766         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   4767         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4768         -1,
   4769         -1,
   4770     },
   4771 #endif /* chips */
   4772 
   4773 #if defined(BCM_88202_A0)
   4774     { /* SOC_REG_INT_WDT1_WDOGPERIPHID2_BCM88202_A0r */
   4775         soc_block_list[1],
   4776         soc_mcsreg,
   4777         1,
   4778         0,
   4779         0x7005fe8,
   4780         SOC_REG_FLAG_RO,
   4781         0,
   4782         1,
   4783         soc_WDT1_WDOGPERIPHID2_BCM88202_A0r_fields,
   4784         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   4785         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4786         -1,
   4787         -1,
   4788     },
   4789 #endif /* chips */
   4790 
   4791 #if defined(BCM_88650_B0)
   4792     { /* SOC_REG_INT_WDT1_WDOGPERIPHID2_BCM88650_B0r */
   4793         soc_block_list[1],
   4794         soc_mcsreg,
   4795         1,
   4796         0,
   4797         0x7005fe8,
   4798         SOC_REG_FLAG_RO,
   4799         0,
   4800         1,
   4801         soc_WDT1_WDOGPERIPHID2_BCM88650_B0r_fields,
   4802         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   4803         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4804         -1,
   4805         -1,
   4806     },
   4807 #endif /* chips */
   4808 
   4809 #if defined(BCM_88660_A0)
   4810     { /* SOC_REG_INT_WDT1_WDOGPERIPHID2_BCM88660_A0r */
   4811         soc_block_list[1],
   4812         soc_mcsreg,
   4813         1,
   4814         0,
   4815         0x7005fe8,
   4816         SOC_REG_FLAG_RO,
   4817         0,
   4818         1,
   4819         soc_WDT1_WDOGPERIPHID2_BCM88660_A0r_fields,
   4820         SOC_RESET_VAL_DEC(0x00000014, 0x00000000)
   4821         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4822         -1,
   4823         -1,
   4824     },
   4825 #endif /* chips */
   4826 
   4827 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4828     { /* SOC_REG_INT_WDT1_WDOGPERIPHID3_BCM56440_A0r */
   4829         soc_block_list[1],
   4830         soc_mcsreg,
   4831         1,
   4832         0,
   4833         0x7005fec,
   4834         SOC_REG_FLAG_RO,
   4835         0,
   4836         1,
   4837         soc_WDT0_WDOGPERIPHID3_BCM56440_A0r_fields,
   4838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4839         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4840         -1,
   4841         -1,
   4842     },
   4843 #endif /* chips */
   4844 
   4845 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4846     defined(BCM_56860_A0)
   4847     { /* SOC_REG_INT_WDT1_WDOGPERIPHID3_BCM56640_A0r */
   4848         soc_block_list[1],
   4849         soc_mcsreg,
   4850         1,
   4851         0,
   4852         0x7005fec,
   4853         SOC_REG_FLAG_RO,
   4854         0,
   4855         1,
   4856         soc_WDT0_WDOGPERIPHID3_BCM56640_A0r_fields,
   4857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4858         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4859         -1,
   4860         -1,
   4861     },
   4862 #endif /* chips */
   4863 
   4864 #if defined(BCM_88202_A0)
   4865     { /* SOC_REG_INT_WDT1_WDOGPERIPHID3_BCM88202_A0r */
   4866         soc_block_list[1],
   4867         soc_mcsreg,
   4868         1,
   4869         0,
   4870         0x7005fec,
   4871         SOC_REG_FLAG_RO,
   4872         0,
   4873         1,
   4874         soc_WDT1_WDOGPERIPHID3_BCM88202_A0r_fields,
   4875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4876         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4877         -1,
   4878         -1,
   4879     },
   4880 #endif /* chips */
   4881 
   4882 #if defined(BCM_88650_B0)
   4883     { /* SOC_REG_INT_WDT1_WDOGPERIPHID3_BCM88650_B0r */
   4884         soc_block_list[1],
   4885         soc_mcsreg,
   4886         1,
   4887         0,
   4888         0x7005fec,
   4889         SOC_REG_FLAG_RO,
   4890         0,
   4891         1,
   4892         soc_WDT1_WDOGPERIPHID3_BCM88650_B0r_fields,
   4893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4894         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4895         -1,
   4896         -1,
   4897     },
   4898 #endif /* chips */
   4899 
   4900 #if defined(BCM_88660_A0)
   4901     { /* SOC_REG_INT_WDT1_WDOGPERIPHID3_BCM88660_A0r */
   4902         soc_block_list[1],
   4903         soc_mcsreg,
   4904         1,
   4905         0,
   4906         0x7005fec,
   4907         SOC_REG_FLAG_RO,
   4908         0,
   4909         1,
   4910         soc_WDT1_WDOGPERIPHID3_BCM88660_A0r_fields,
   4911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4912         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   4913         -1,
   4914         -1,
   4915     },
   4916 #endif /* chips */
   4917 
   4918 #if defined(BCM_88650_A0)
   4919     { /* SOC_REG_INT_WDT1_WDOGRISr */
   4920         soc_block_list[1],
   4921         soc_mcsreg,
   4922         1,
   4923         0,
   4924         0x7005010,
   4925         SOC_REG_FLAG_RO,
   4926         0,
   4927         1,
   4928         soc_WDT1_WDOGRISr_fields,
   4929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4930         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4931         -1,
   4932         -1,
   4933     },
   4934 #endif /* chips */
   4935 
   4936 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   4937     { /* SOC_REG_INT_WDT1_WDOGRIS_BCM56440_A0r */
   4938         soc_block_list[1],
   4939         soc_mcsreg,
   4940         1,
   4941         0,
   4942         0x7005010,
   4943         SOC_REG_FLAG_RO,
   4944         0,
   4945         1,
   4946         soc_WDT0_WDOGRIS_BCM56440_A0r_fields,
   4947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4948         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4949         -1,
   4950         -1,
   4951     },
   4952 #endif /* chips */
   4953 
   4954 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   4955     defined(BCM_56860_A0)
   4956     { /* SOC_REG_INT_WDT1_WDOGRIS_BCM56640_A0r */
   4957         soc_block_list[1],
   4958         soc_mcsreg,
   4959         1,
   4960         0,
   4961         0x7005010,
   4962         SOC_REG_FLAG_RO,
   4963         0,
   4964         1,
   4965         soc_WDT0_WDOGRIS_BCM56640_A0r_fields,
   4966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4967         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4968         -1,
   4969         -1,
   4970     },
   4971 #endif /* chips */
   4972 
   4973 #if defined(BCM_88202_A0)
   4974     { /* SOC_REG_INT_WDT1_WDOGRIS_BCM88202_A0r */
   4975         soc_block_list[1],
   4976         soc_mcsreg,
   4977         1,
   4978         0,
   4979         0x7005010,
   4980         SOC_REG_FLAG_RO,
   4981         0,
   4982         1,
   4983         soc_WDT1_WDOGRIS_BCM88202_A0r_fields,
   4984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4985         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   4986         -1,
   4987         -1,
   4988     },
   4989 #endif /* chips */
   4990 
   4991 #if defined(BCM_88650_B0)
   4992     { /* SOC_REG_INT_WDT1_WDOGRIS_BCM88650_B0r */
   4993         soc_block_list[1],
   4994         soc_mcsreg,
   4995         1,
   4996         0,
   4997         0x7005010,
   4998         SOC_REG_FLAG_RO,
   4999         0,
   5000         1,
   5001         soc_WDT1_WDOGRIS_BCM88650_B0r_fields,
   5002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5003         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5004         -1,
   5005         -1,
   5006     },
   5007 #endif /* chips */
   5008 
   5009 #if defined(BCM_88660_A0)
   5010     { /* SOC_REG_INT_WDT1_WDOGRIS_BCM88660_A0r */
   5011         soc_block_list[1],
   5012         soc_mcsreg,
   5013         1,
   5014         0,
   5015         0x7005010,
   5016         SOC_REG_FLAG_RO,
   5017         0,
   5018         1,
   5019         soc_WDT1_WDOGRIS_BCM88660_A0r_fields,
   5020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5021         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5022         -1,
   5023         -1,
   5024     },
   5025 #endif /* chips */
   5026 
   5027 #if defined(BCM_88650_A0)
   5028     { /* SOC_REG_INT_WDT1_WDOGVALUEr */
   5029         soc_block_list[1],
   5030         soc_mcsreg,
   5031         1,
   5032         0,
   5033         0x7005004,
   5034         SOC_REG_FLAG_RO,
   5035         0,
   5036         1,
   5037         soc_WDT1_WDOGVALUEr_fields,
   5038         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   5039         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5040         -1,
   5041         -1,
   5042     },
   5043 #endif /* chips */
   5044 
   5045 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5046     { /* SOC_REG_INT_WDT1_WDOGVALUE_BCM56440_A0r */
   5047         soc_block_list[1],
   5048         soc_mcsreg,
   5049         1,
   5050         0,
   5051         0x7005004,
   5052         SOC_REG_FLAG_RO,
   5053         0,
   5054         1,
   5055         soc_WDT0_WDOGVALUE_BCM56440_A0r_fields,
   5056         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   5057         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5058         -1,
   5059         -1,
   5060     },
   5061 #endif /* chips */
   5062 
   5063 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   5064     defined(BCM_56860_A0)
   5065     { /* SOC_REG_INT_WDT1_WDOGVALUE_BCM56640_A0r */
   5066         soc_block_list[1],
   5067         soc_mcsreg,
   5068         1,
   5069         0,
   5070         0x7005004,
   5071         SOC_REG_FLAG_RO,
   5072         0,
   5073         1,
   5074         soc_WDT0_WDOGVALUE_BCM56640_A0r_fields,
   5075         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   5076         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5077         -1,
   5078         -1,
   5079     },
   5080 #endif /* chips */
   5081 
   5082 #if defined(BCM_88202_A0)
   5083     { /* SOC_REG_INT_WDT1_WDOGVALUE_BCM88202_A0r */
   5084         soc_block_list[1],
   5085         soc_mcsreg,
   5086         1,
   5087         0,
   5088         0x7005004,
   5089         SOC_REG_FLAG_RO,
   5090         0,
   5091         1,
   5092         soc_WDT1_WDOGVALUE_BCM88202_A0r_fields,
   5093         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   5094         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5095         -1,
   5096         -1,
   5097     },
   5098 #endif /* chips */
   5099 
   5100 #if defined(BCM_88650_B0)
   5101     { /* SOC_REG_INT_WDT1_WDOGVALUE_BCM88650_B0r */
   5102         soc_block_list[1],
   5103         soc_mcsreg,
   5104         1,
   5105         0,
   5106         0x7005004,
   5107         SOC_REG_FLAG_RO,
   5108         0,
   5109         1,
   5110         soc_WDT1_WDOGVALUE_BCM88650_B0r_fields,
   5111         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   5112         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5113         -1,
   5114         -1,
   5115     },
   5116 #endif /* chips */
   5117 
   5118 #if defined(BCM_88660_A0)
   5119     { /* SOC_REG_INT_WDT1_WDOGVALUE_BCM88660_A0r */
   5120         soc_block_list[1],
   5121         soc_mcsreg,
   5122         1,
   5123         0,
   5124         0x7005004,
   5125         SOC_REG_FLAG_RO,
   5126         0,
   5127         1,
   5128         soc_WDT1_WDOGVALUE_BCM88660_A0r_fields,
   5129         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   5130         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5131         -1,
   5132         -1,
   5133     },
   5134 #endif /* chips */
   5135 
   5136 #if defined(BCM_88650_A0)
   5137     { /* SOC_REG_INT_WDT_0_RESET_MASKr */
   5138         soc_block_list[1],
   5139         soc_mcsreg,
   5140         1,
   5141         0,
   5142         0x70060c0,
   5143         0,
   5144         0,
   5145         3,
   5146         soc_WDT_0_RESET_MASKr_fields,
   5147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5148         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5149         -1,
   5150         -1,
   5151     },
   5152 #endif /* chips */
   5153 
   5154 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5155     { /* SOC_REG_INT_WDT_0_RESET_MASK_BCM56440_A0r */
   5156         soc_block_list[1],
   5157         soc_mcsreg,
   5158         1,
   5159         0,
   5160         0x70060c0,
   5161         0,
   5162         0,
   5163         3,
   5164         soc_WDT_0_RESET_MASK_BCM56440_A0r_fields,
   5165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5166         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5167         -1,
   5168         -1,
   5169     },
   5170 #endif /* chips */
   5171 
   5172 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   5173     defined(BCM_56860_A0)
   5174     { /* SOC_REG_INT_WDT_0_RESET_MASK_BCM56640_A0r */
   5175         soc_block_list[1],
   5176         soc_mcsreg,
   5177         1,
   5178         0,
   5179         0x70060c0,
   5180         0,
   5181         0,
   5182         3,
   5183         soc_WDT_0_RESET_MASK_BCM56640_A0r_fields,
   5184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5186         -1,
   5187         -1,
   5188     },
   5189 #endif /* chips */
   5190 
   5191 #if defined(BCM_88202_A0)
   5192     { /* SOC_REG_INT_WDT_0_RESET_MASK_BCM88202_A0r */
   5193         soc_block_list[1],
   5194         soc_mcsreg,
   5195         1,
   5196         0,
   5197         0x70060c0,
   5198         0,
   5199         0,
   5200         3,
   5201         soc_WDT_0_RESET_MASK_BCM88202_A0r_fields,
   5202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5203         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5204         -1,
   5205         -1,
   5206     },
   5207 #endif /* chips */
   5208 
   5209 #if defined(BCM_88650_B0)
   5210     { /* SOC_REG_INT_WDT_0_RESET_MASK_BCM88650_B0r */
   5211         soc_block_list[1],
   5212         soc_mcsreg,
   5213         1,
   5214         0,
   5215         0x70060c0,
   5216         0,
   5217         0,
   5218         3,
   5219         soc_WDT_0_RESET_MASK_BCM88650_B0r_fields,
   5220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5221         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5222         -1,
   5223         -1,
   5224     },
   5225 #endif /* chips */
   5226 
   5227 #if defined(BCM_88660_A0)
   5228     { /* SOC_REG_INT_WDT_0_RESET_MASK_BCM88660_A0r */
   5229         soc_block_list[1],
   5230         soc_mcsreg,
   5231         1,
   5232         0,
   5233         0x70060c0,
   5234         0,
   5235         0,
   5236         3,
   5237         soc_WDT_0_RESET_MASK_BCM88660_A0r_fields,
   5238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5239         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5240         -1,
   5241         -1,
   5242     },
   5243 #endif /* chips */
   5244 
   5245 #if defined(BCM_88650_A0)
   5246     { /* SOC_REG_INT_WDT_1_RESET_MASKr */
   5247         soc_block_list[1],
   5248         soc_mcsreg,
   5249         1,
   5250         0,
   5251         0x70060c4,
   5252         0,
   5253         0,
   5254         3,
   5255         soc_WDT_1_RESET_MASKr_fields,
   5256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5258         -1,
   5259         -1,
   5260     },
   5261 #endif /* chips */
   5262 
   5263 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5264     { /* SOC_REG_INT_WDT_1_RESET_MASK_BCM56440_A0r */
   5265         soc_block_list[1],
   5266         soc_mcsreg,
   5267         1,
   5268         0,
   5269         0x70060c4,
   5270         0,
   5271         0,
   5272         3,
   5273         soc_WDT_0_RESET_MASK_BCM56440_A0r_fields,
   5274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5276         -1,
   5277         -1,
   5278     },
   5279 #endif /* chips */
   5280 
   5281 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
   5282     defined(BCM_56860_A0)
   5283     { /* SOC_REG_INT_WDT_1_RESET_MASK_BCM56640_A0r */
   5284         soc_block_list[1],
   5285         soc_mcsreg,
   5286         1,
   5287         0,
   5288         0x70060c4,
   5289         0,
   5290         0,
   5291         3,
   5292         soc_WDT_0_RESET_MASK_BCM56640_A0r_fields,
   5293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5294         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5295         -1,
   5296         -1,
   5297     },
   5298 #endif /* chips */
   5299 
   5300 #if defined(BCM_88202_A0)
   5301     { /* SOC_REG_INT_WDT_1_RESET_MASK_BCM88202_A0r */
   5302         soc_block_list[1],
   5303         soc_mcsreg,
   5304         1,
   5305         0,
   5306         0x70060c4,
   5307         0,
   5308         0,
   5309         3,
   5310         soc_WDT_1_RESET_MASK_BCM88202_A0r_fields,
   5311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5312         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5313         -1,
   5314         -1,
   5315     },
   5316 #endif /* chips */
   5317 
   5318 #if defined(BCM_88650_B0)
   5319     { /* SOC_REG_INT_WDT_1_RESET_MASK_BCM88650_B0r */
   5320         soc_block_list[1],
   5321         soc_mcsreg,
   5322         1,
   5323         0,
   5324         0x70060c4,
   5325         0,
   5326         0,
   5327         3,
   5328         soc_WDT_1_RESET_MASK_BCM88650_B0r_fields,
   5329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5330         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5331         -1,
   5332         -1,
   5333     },
   5334 #endif /* chips */
   5335 
   5336 #if defined(BCM_88660_A0)
   5337     { /* SOC_REG_INT_WDT_1_RESET_MASK_BCM88660_A0r */
   5338         soc_block_list[1],
   5339         soc_mcsreg,
   5340         1,
   5341         0,
   5342         0x70060c4,
   5343         0,
   5344         0,
   5345         3,
   5346         soc_WDT_1_RESET_MASK_BCM88660_A0r_fields,
   5347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5348         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5349         -1,
   5350         -1,
   5351     },
   5352 #endif /* chips */
   5353 
   5354 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5355     { /* SOC_REG_INT_WERRCOUNTr */
   5356         soc_block_list[4],
   5357         soc_portreg,
   5358         48,
   5359         0,
   5360         0x6000140,
   5361         SOC_REG_FLAG_ARRAY |
   5362                           SOC_REG_FLAG_RO,
   5363         0,
   5364         2,
   5365         soc_WERRCOUNTr_fields,
   5366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5367         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   5368         -1,
   5369         46,
   5370     },
   5371 #endif /* chips */
   5372 
   5373 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   5374     { /* SOC_REG_INT_WLAN_DECAP_NLF_MTU_CHECKr */
   5375         soc_block_list[5],
   5376         soc_genreg,
   5377         1,
   5378         0,
   5379         0x2000c00,
   5380         0,
   5381         0,
   5382         2,
   5383         soc_WLAN_DECAP_NLF_MTU_CHECKr_fields,
   5384         SOC_RESET_VAL_DEC(0x000ea000, 0x00000000)
   5385         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   5386         -1,
   5387         -1,
   5388     },
   5389 #endif /* chips */
   5390 
   5391 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   5392     { /* SOC_REG_INT_WLAN_ENCAP_NLF_MTU_CHECKr */
   5393         soc_block_list[5],
   5394         soc_genreg,
   5395         1,
   5396         0,
   5397         0x2000d00,
   5398         0,
   5399         0,
   5400         2,
   5401         soc_WLAN_ENCAP_NLF_MTU_CHECKr_fields,
   5402         SOC_RESET_VAL_DEC(0x000ee000, 0x00000000)
   5403         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   5404         -1,
   5405         -1,
   5406     },
   5407 #endif /* chips */
   5408 
   5409 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5410     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5411     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5412     { /* SOC_REG_INT_WLAN_SVP_ECC_CONTROLr */
   5413         soc_block_list[5],
   5414         soc_genreg,
   5415         1,
   5416         0,
   5417         0x2080128,
   5418         0,
   5419         0,
   5420         1,
   5421         soc_EGR_INITBUF_ECC_CONTROLr_fields,
   5422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5423         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   5424         -1,
   5425         -1,
   5426     },
   5427 #endif /* chips */
   5428 
   5429 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5430     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5431     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5432     { /* SOC_REG_INT_WLAN_SVP_ECC_STATUS_INTRr */
   5433         soc_block_list[5],
   5434         soc_genreg,
   5435         1,
   5436         0,
   5437         0x2080129,
   5438         0,
   5439         0,
   5440         4,
   5441         soc_WLAN_SVP_ECC_STATUS_INTRr_fields,
   5442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5443         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   5444         -1,
   5445         -1,
   5446     },
   5447 #endif /* chips */
   5448 
   5449 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5450     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5451     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5452     { /* SOC_REG_INT_WLAN_SVP_ECC_STATUS_NACKr */
   5453         soc_block_list[5],
   5454         soc_genreg,
   5455         1,
   5456         0,
   5457         0x208012a,
   5458         0,
   5459         0,
   5460         4,
   5461         soc_WLAN_SVP_ECC_STATUS_INTRr_fields,
   5462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5463         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   5464         -1,
   5465         -1,
   5466     },
   5467 #endif /* chips */
   5468 
   5469 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5470     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5471     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5472     { /* SOC_REG_INT_WL_DROP_POLICYr */
   5473         soc_block_list[4],
   5474         soc_genreg,
   5475         1,
   5476         0,
   5477         0x2080130,
   5478         0,
   5479         0,
   5480         6,
   5481         soc_WL_DROP_POLICYr_fields,
   5482         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   5483         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   5484         -1,
   5485         -1,
   5486     },
   5487 #endif /* chips */
   5488 
   5489 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5490     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5491     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5492     { /* SOC_REG_INT_WL_PORT_COUNT_CELLr */
   5493         soc_block_list[4],
   5494         soc_genreg,
   5495         1,
   5496         0,
   5497         0x2080280,
   5498         SOC_REG_FLAG_RO,
   5499         0,
   5500         1,
   5501         soc_PORT_COUNT_CELLr_fields,
   5502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5503         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   5504         -1,
   5505         -1,
   5506     },
   5507 #endif /* chips */
   5508 
   5509 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5510     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5511     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5512     { /* SOC_REG_INT_WL_PORT_COUNT_PACKETr */
   5513         soc_block_list[4],
   5514         soc_genreg,
   5515         1,
   5516         0,
   5517         0x2080281,
   5518         SOC_REG_FLAG_RO,
   5519         0,
   5520         1,
   5521         soc_WL_PORT_COUNT_PACKETr_fields,
   5522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5523         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5524         -1,
   5525         -1,
   5526     },
   5527 #endif /* chips */
   5528 
   5529 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5530     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5531     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5532     { /* SOC_REG_INT_WL_PORT_SHARED_COUNT_CELLr */
   5533         soc_block_list[4],
   5534         soc_genreg,
   5535         1,
   5536         0,
   5537         0x2080284,
   5538         SOC_REG_FLAG_RO,
   5539         0,
   5540         1,
   5541         soc_PORT_SHARED_COUNT_CELLr_fields,
   5542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5543         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   5544         -1,
   5545         -1,
   5546     },
   5547 #endif /* chips */
   5548 
   5549 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5550     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5551     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5552     { /* SOC_REG_INT_WL_PORT_SHARED_COUNT_PACKETr */
   5553         soc_block_list[4],
   5554         soc_genreg,
   5555         1,
   5556         0,
   5557         0x2080285,
   5558         SOC_REG_FLAG_RO,
   5559         0,
   5560         1,
   5561         soc_WL_PORT_SHARED_COUNT_PACKETr_fields,
   5562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5563         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5564         -1,
   5565         -1,
   5566     },
   5567 #endif /* chips */
   5568 
   5569 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5570     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5571     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5572     { /* SOC_REG_INT_WL_PORT_SHARED_LIMIT_CELLr */
   5573         soc_block_list[4],
   5574         soc_genreg,
   5575         1,
   5576         0,
   5577         0x2080223,
   5578         0,
   5579         0,
   5580         1,
   5581         soc_WL_PORT_SHARED_LIMIT_CELLr_fields,
   5582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5583         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   5584         -1,
   5585         -1,
   5586     },
   5587 #endif /* chips */
   5588 
   5589 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5590     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5591     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5592     { /* SOC_REG_INT_WL_PORT_SHARED_LIMIT_PACKETr */
   5593         soc_block_list[4],
   5594         soc_genreg,
   5595         1,
   5596         0,
   5597         0x2080224,
   5598         0,
   5599         0,
   5600         1,
   5601         soc_WL_PORT_SHARED_LIMIT_PACKETr_fields,
   5602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5603         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5604         -1,
   5605         -1,
   5606     },
   5607 #endif /* chips */
   5608 
   5609 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   5610     { /* SOC_REG_INT_WORKFIFO_MEMORY_DEBUG_TMr */
   5611         soc_block_list[4],
   5612         soc_genreg,
   5613         1,
   5614         0,
   5615         0x92026800,
   5616         0,
   5617         0,
   5618         1,
   5619         soc_REPBUF_MEMORY_DEBUG_TMr_fields,
   5620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5621         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5622         -1,
   5623         -1,
   5624     },
   5625 #endif /* chips */
   5626 
   5627 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   5628     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   5629     { /* SOC_REG_INT_WREDAVGQSIZE_CELLr */
   5630         soc_block_list[4],
   5631         soc_portreg,
   5632         24,
   5633         0,
   5634         0x17000240,
   5635         SOC_REG_FLAG_ARRAY,
   5636         0,
   5637         2,
   5638         soc_GLOBAL_WREDAVGQSIZE_CELLr_fields,
   5639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5640         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   5641         -1,
   5642         1,
   5643     },
   5644 #endif /* chips */
   5645 
   5646 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   5647     { /* SOC_REG_INT_WREDAVGQSIZE_CELL_BCM56334_A0r */
   5648         soc_block_list[4],
   5649         soc_portreg,
   5650         24,
   5651         0,
   5652         0x17000240,
   5653         SOC_REG_FLAG_ARRAY,
   5654         0,
   5655         2,
   5656         soc_GLOBAL_WREDAVGQSIZE_CELLr_fields,
   5657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5658         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   5659         -1,
   5660         29,
   5661     },
   5662 #endif /* chips */
   5663 
   5664 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5665     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5666     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5667     { /* SOC_REG_INT_WREDAVGQSIZE_CELL_BCM56634_A0r */
   5668         soc_block_list[4],
   5669         soc_portreg,
   5670         24,
   5671         0,
   5672         0x17000240,
   5673         SOC_REG_FLAG_ARRAY,
   5674         0,
   5675         2,
   5676         soc_GLOBAL_WREDAVGQSIZE_CELLr_fields,
   5677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5678         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   5679         -1,
   5680         13,
   5681     },
   5682 #endif /* chips */
   5683 
   5684 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   5685     { /* SOC_REG_INT_WREDAVGQSIZE_CELL_BCM56820_A0r */
   5686         soc_block_list[4],
   5687         soc_portreg,
   5688         8,
   5689         0,
   5690         0x12000240,
   5691         SOC_REG_FLAG_ARRAY,
   5692         0,
   5693         2,
   5694         soc_GLOBAL_WREDAVGQSIZE_CELLr_fields,
   5695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5696         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   5697         -1,
   5698         10,
   5699     },
   5700 #endif /* chips */
   5701 
   5702 #if defined(BCM_88732_A0)
   5703     { /* SOC_REG_INT_WREDAVGQSIZE_CELL_BCM88732_A0r */
   5704         soc_block_list[4],
   5705         soc_portreg,
   5706         8,
   5707         0,
   5708         0x12000340,
   5709         SOC_REG_FLAG_ARRAY,
   5710         0,
   5711         1,
   5712         soc_GLOBAL_WREDAVGQSIZE_CELL_BCM88732_A0r_fields,
   5713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5714         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5715         -1,
   5716         50,
   5717     },
   5718 #endif /* chips */
   5719 
   5720 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   5721     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   5722     { /* SOC_REG_INT_WREDAVGQSIZE_PACKETr */
   5723         soc_block_list[4],
   5724         soc_portreg,
   5725         24,
   5726         0,
   5727         0x170003c0,
   5728         SOC_REG_FLAG_ARRAY,
   5729         0,
   5730         2,
   5731         soc_GLOBAL_WREDAVGQSIZE_PACKETr_fields,
   5732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5733         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   5734         -1,
   5735         1,
   5736     },
   5737 #endif /* chips */
   5738 
   5739 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   5740     { /* SOC_REG_INT_WREDAVGQSIZE_PACKET_BCM56334_A0r */
   5741         soc_block_list[4],
   5742         soc_portreg,
   5743         24,
   5744         0,
   5745         0x170003c0,
   5746         SOC_REG_FLAG_ARRAY,
   5747         0,
   5748         2,
   5749         soc_GLOBAL_WREDAVGQSIZE_PACKETr_fields,
   5750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5751         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   5752         -1,
   5753         29,
   5754     },
   5755 #endif /* chips */
   5756 
   5757 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5758     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5759     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5760     { /* SOC_REG_INT_WREDAVGQSIZE_PACKET_BCM56634_A0r */
   5761         soc_block_list[4],
   5762         soc_portreg,
   5763         24,
   5764         0,
   5765         0x170003c0,
   5766         SOC_REG_FLAG_ARRAY,
   5767         0,
   5768         2,
   5769         soc_GLOBAL_WREDAVGQSIZE_PACKETr_fields,
   5770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5771         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   5772         -1,
   5773         13,
   5774     },
   5775 #endif /* chips */
   5776 
   5777 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   5778     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   5779     { /* SOC_REG_INT_WREDCONFIG_CELLr */
   5780         soc_block_list[4],
   5781         soc_portreg,
   5782         24,
   5783         0,
   5784         0x17000200,
   5785         SOC_REG_FLAG_ARRAY,
   5786         0,
   5787         8,
   5788         soc_GLOBAL_WREDCONFIG_CELLr_fields,
   5789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5790         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   5791         -1,
   5792         1,
   5793     },
   5794 #endif /* chips */
   5795 
   5796 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   5797     { /* SOC_REG_INT_WREDCONFIG_CELL_BCM56334_A0r */
   5798         soc_block_list[4],
   5799         soc_portreg,
   5800         24,
   5801         0,
   5802         0x17000200,
   5803         SOC_REG_FLAG_ARRAY,
   5804         0,
   5805         8,
   5806         soc_GLOBAL_WREDCONFIG_CELLr_fields,
   5807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5808         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   5809         -1,
   5810         29,
   5811     },
   5812 #endif /* chips */
   5813 
   5814 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5815     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5816     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5817     { /* SOC_REG_INT_WREDCONFIG_CELL_BCM56634_A0r */
   5818         soc_block_list[4],
   5819         soc_portreg,
   5820         24,
   5821         0,
   5822         0x17000200,
   5823         SOC_REG_FLAG_ARRAY,
   5824         0,
   5825         8,
   5826         soc_GLOBAL_WREDCONFIG_CELLr_fields,
   5827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5828         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   5829         -1,
   5830         13,
   5831     },
   5832 #endif /* chips */
   5833 
   5834 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   5835     { /* SOC_REG_INT_WREDCONFIG_CELL_BCM56820_A0r */
   5836         soc_block_list[4],
   5837         soc_portreg,
   5838         8,
   5839         0,
   5840         0x12000200,
   5841         SOC_REG_FLAG_ARRAY,
   5842         0,
   5843         8,
   5844         soc_GLOBAL_WREDCONFIG_CELLr_fields,
   5845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5846         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   5847         -1,
   5848         10,
   5849     },
   5850 #endif /* chips */
   5851 
   5852 #if defined(BCM_88732_A0)
   5853     { /* SOC_REG_INT_WREDCONFIG_CELL_BCM88732_A0r */
   5854         soc_block_list[4],
   5855         soc_portreg,
   5856         8,
   5857         0,
   5858         0x12000300,
   5859         SOC_REG_FLAG_ARRAY,
   5860         0,
   5861         8,
   5862         soc_GLOBAL_WREDCONFIG_CELL_BCM88732_A0r_fields,
   5863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5864         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   5865         -1,
   5866         50,
   5867     },
   5868 #endif /* chips */
   5869 
   5870 #if defined(BCM_88732_A0)
   5871     { /* SOC_REG_INT_WREDCONFIG_ECCPr */
   5872         soc_block_list[4],
   5873         soc_portreg,
   5874         8,
   5875         0,
   5876         0x12000480,
   5877         SOC_REG_FLAG_ARRAY,
   5878         0,
   5879         1,
   5880         soc_CPUPKTECCr_fields,
   5881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5882         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   5883         -1,
   5884         50,
   5885     },
   5886 #endif /* chips */
   5887 
   5888 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   5889     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   5890     { /* SOC_REG_INT_WREDCONFIG_PACKETr */
   5891         soc_block_list[4],
   5892         soc_portreg,
   5893         24,
   5894         0,
   5895         0x17000380,
   5896         SOC_REG_FLAG_ARRAY,
   5897         0,
   5898         8,
   5899         soc_GLOBAL_WREDCONFIG_CELLr_fields,
   5900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5901         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   5902         -1,
   5903         1,
   5904     },
   5905 #endif /* chips */
   5906 
   5907 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   5908     { /* SOC_REG_INT_WREDCONFIG_PACKET_BCM56334_A0r */
   5909         soc_block_list[4],
   5910         soc_portreg,
   5911         24,
   5912         0,
   5913         0x17000380,
   5914         SOC_REG_FLAG_ARRAY,
   5915         0,
   5916         8,
   5917         soc_GLOBAL_WREDCONFIG_CELLr_fields,
   5918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5919         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   5920         -1,
   5921         29,
   5922     },
   5923 #endif /* chips */
   5924 
   5925 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5926     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5927     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5928     { /* SOC_REG_INT_WREDCONFIG_PACKET_BCM56634_A0r */
   5929         soc_block_list[4],
   5930         soc_portreg,
   5931         24,
   5932         0,
   5933         0x17000380,
   5934         SOC_REG_FLAG_ARRAY,
   5935         0,
   5936         8,
   5937         soc_GLOBAL_WREDCONFIG_CELLr_fields,
   5938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5939         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   5940         -1,
   5941         13,
   5942     },
   5943 #endif /* chips */
   5944 
   5945 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5946     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZEr */
   5947         soc_block_list[4],
   5948         soc_genreg,
   5949         1,
   5950         0,
   5951         0x17080c01,
   5952         0,
   5953         0,
   5954         3,
   5955         soc_L3_DEFIP_128_DATA_DBGCTRL_BCM56840_A0r_fields,
   5956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5957         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5958         -1,
   5959         -1,
   5960     },
   5961 #endif /* chips */
   5962 
   5963 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   5964     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_BCM56640_A0r */
   5965         soc_block_list[4],
   5966         soc_genreg,
   5967         1,
   5968         0,
   5969         0x560c0300,
   5970         0,
   5971         0,
   5972         1,
   5973         soc_FT_CNTR_RAM_CONTROLr_fields,
   5974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5975         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5976         -1,
   5977         -1,
   5978     },
   5979 #endif /* chips */
   5980 
   5981 #if defined(BCM_53570_A0)
   5982     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_QG_TMr */
   5983         soc_block_list[4],
   5984         soc_genreg,
   5985         1,
   5986         0,
   5987         0x20f0600,
   5988         0,
   5989         0,
   5990         1,
   5991         soc_E2EFC_MEM_TMr_fields,
   5992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5993         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   5994         -1,
   5995         -1,
   5996     },
   5997 #endif /* chips */
   5998 
   5999 #if defined(BCM_53570_B0)
   6000     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_QG_TM_BCM53570_B0r */
   6001         soc_block_list[4],
   6002         soc_genreg,
   6003         1,
   6004         0,
   6005         0x20f0900,
   6006         0,
   6007         0,
   6008         1,
   6009         soc_E2EFC_MEM_TMr_fields,
   6010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6012         -1,
   6013         -1,
   6014     },
   6015 #endif /* chips */
   6016 
   6017 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
   6018     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_TMr */
   6019         soc_block_list[4],
   6020         soc_genreg,
   6021         1,
   6022         0,
   6023         0x216a100,
   6024         0,
   6025         0,
   6026         1,
   6027         soc_DSCP_CONTROLr_fields,
   6028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6029         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6030         -1,
   6031         -1,
   6032     },
   6033 #endif /* chips */
   6034 
   6035 #if defined(BCM_53540_A0)
   6036     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_TM_BCM53540_A0r */
   6037         soc_block_list[4],
   6038         soc_genreg,
   6039         1,
   6040         0,
   6041         0x2084000,
   6042         0,
   6043         0,
   6044         1,
   6045         soc_DSCP_CONTROLr_fields,
   6046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6048         -1,
   6049         -1,
   6050     },
   6051 #endif /* chips */
   6052 
   6053 #if defined(BCM_53570_A0)
   6054     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_TM_BCM53570_A0r */
   6055         soc_block_list[4],
   6056         soc_genreg,
   6057         1,
   6058         0,
   6059         0x20ef600,
   6060         0,
   6061         0,
   6062         1,
   6063         soc_DSCP_CONTROLr_fields,
   6064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6065         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6066         -1,
   6067         -1,
   6068     },
   6069 #endif /* chips */
   6070 
   6071 #if defined(BCM_53570_B0)
   6072     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_TM_BCM53570_B0r */
   6073         soc_block_list[4],
   6074         soc_genreg,
   6075         1,
   6076         0,
   6077         0x20ef900,
   6078         0,
   6079         0,
   6080         1,
   6081         soc_DSCP_CONTROLr_fields,
   6082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6083         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6084         -1,
   6085         -1,
   6086     },
   6087 #endif /* chips */
   6088 
   6089 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6090     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_TM_BCM56960_A0r */
   6091         soc_block_list[124],
   6092         soc_pipereg,
   6093         1,
   6094         0,
   6095         0x21801000,
   6096         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6097         0,
   6098         1,
   6099         soc_DSCP_CONTROLr_fields,
   6100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6101         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6102         -1,
   6103         -1,
   6104         3,
   6105     },
   6106 #endif /* chips */
   6107 
   6108 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   6109     defined(BCM_56870_A0) || defined(BCM_56970_A0)
   6110     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_TM_BCM56970_A0r */
   6111         soc_block_list[124],
   6112         soc_pipereg,
   6113         1,
   6114         0,
   6115         0x21801100,
   6116         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6117         0,
   6118         1,
   6119         soc_FP_METER_TMr_fields,
   6120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6121         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6122         -1,
   6123         -1,
   6124         3,
   6125     },
   6126 #endif /* chips */
   6127 
   6128 #if defined(BCM_56850_A0)
   6129     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_X_PIPE_TMr */
   6130         soc_block_list[4],
   6131         soc_genreg,
   6132         1,
   6133         0,
   6134         0x760c0200,
   6135         0,
   6136         0,
   6137         1,
   6138         soc_INTFO_QCN_SRAM_TMr_fields,
   6139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6140         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6141         -1,
   6142         -1,
   6143     },
   6144 #endif /* chips */
   6145 
   6146 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   6147     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_X_PIPE_TM_BCM56560_A0r */
   6148         soc_block_list[4],
   6149         soc_genreg,
   6150         1,
   6151         0,
   6152         0x760c0200,
   6153         0,
   6154         0,
   6155         1,
   6156         soc_CCPMEMDEBUG_BCM56560_A0r_fields,
   6157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6158         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6159         -1,
   6160         -1,
   6161     },
   6162 #endif /* chips */
   6163 
   6164 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   6165     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_X_PIPE_TM_BCM56670_A0r */
   6166         soc_block_list[4],
   6167         soc_genreg,
   6168         1,
   6169         0,
   6170         0x760c0200,
   6171         0,
   6172         0,
   6173         1,
   6174         soc_E2EFC_MEM_TMr_fields,
   6175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6176         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6177         -1,
   6178         -1,
   6179     },
   6180 #endif /* chips */
   6181 
   6182 #if defined(BCM_56860_A0)
   6183     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_X_PIPE_TM_BCM56860_A0r */
   6184         soc_block_list[4],
   6185         soc_genreg,
   6186         1,
   6187         0,
   6188         0x760c0200,
   6189         0,
   6190         0,
   6191         1,
   6192         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r_fields,
   6193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6194         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6195         -1,
   6196         -1,
   6197     },
   6198 #endif /* chips */
   6199 
   6200 #if defined(BCM_56850_A0)
   6201     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_Y_PIPE_TMr */
   6202         soc_block_list[4],
   6203         soc_genreg,
   6204         1,
   6205         0,
   6206         0x760c0300,
   6207         0,
   6208         0,
   6209         1,
   6210         soc_INTFO_QCN_SRAM_TMr_fields,
   6211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6212         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6213         -1,
   6214         -1,
   6215     },
   6216 #endif /* chips */
   6217 
   6218 #if defined(BCM_56860_A0)
   6219     { /* SOC_REG_INT_WREDMEMDEBUG_AVG_QSIZE_Y_PIPE_TM_BCM56860_A0r */
   6220         soc_block_list[4],
   6221         soc_genreg,
   6222         1,
   6223         0,
   6224         0x760c0300,
   6225         0,
   6226         0,
   6227         1,
   6228         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r_fields,
   6229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6230         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6231         -1,
   6232         -1,
   6233     },
   6234 #endif /* chips */
   6235 
   6236 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   6237     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   6238     { /* SOC_REG_INT_WREDMEMDEBUG_CFG_CELLr */
   6239         soc_block_list[4],
   6240         soc_genreg,
   6241         1,
   6242         0,
   6243         0x17080400,
   6244         0,
   6245         0,
   6246         2,
   6247         soc_WREDMEMDEBUG_CFG_CELLr_fields,
   6248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6250         -1,
   6251         -1,
   6252     },
   6253 #endif /* chips */
   6254 
   6255 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   6256     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6257     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6258     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6259     { /* SOC_REG_INT_WREDMEMDEBUG_CFG_CELL_BCM56634_A0r */
   6260         soc_block_list[4],
   6261         soc_genreg,
   6262         1,
   6263         0,
   6264         0x17080400,
   6265         0,
   6266         0,
   6267         1,
   6268         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
   6269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6270         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6271         -1,
   6272         -1,
   6273     },
   6274 #endif /* chips */
   6275 
   6276 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6277     { /* SOC_REG_INT_WREDMEMDEBUG_CFG_CELL_BCM56820_A0r */
   6278         soc_block_list[4],
   6279         soc_genreg,
   6280         1,
   6281         0,
   6282         0x12080400,
   6283         0,
   6284         0,
   6285         2,
   6286         soc_WREDMEMDEBUG_CFG_CELLr_fields,
   6287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6288         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6289         -1,
   6290         -1,
   6291     },
   6292 #endif /* chips */
   6293 
   6294 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   6295     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   6296     { /* SOC_REG_INT_WREDMEMDEBUG_CFG_PACKETr */
   6297         soc_block_list[4],
   6298         soc_genreg,
   6299         1,
   6300         0,
   6301         0x17080403,
   6302         0,
   6303         0,
   6304         2,
   6305         soc_WREDMEMDEBUG_CFG_CELLr_fields,
   6306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6307         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6308         -1,
   6309         -1,
   6310     },
   6311 #endif /* chips */
   6312 
   6313 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   6314     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6315     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6316     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6317     { /* SOC_REG_INT_WREDMEMDEBUG_CFG_PACKET_BCM56634_A0r */
   6318         soc_block_list[4],
   6319         soc_genreg,
   6320         1,
   6321         0,
   6322         0x17080403,
   6323         0,
   6324         0,
   6325         1,
   6326         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
   6327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6328         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6329         -1,
   6330         -1,
   6331     },
   6332 #endif /* chips */
   6333 
   6334 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6335     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIGr */
   6336         soc_block_list[4],
   6337         soc_genreg,
   6338         1,
   6339         0,
   6340         0x17080c00,
   6341         0,
   6342         0,
   6343         3,
   6344         soc_L3_DEFIP_128_DATA_DBGCTRL_BCM56840_A0r_fields,
   6345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6346         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6347         -1,
   6348         -1,
   6349     },
   6350 #endif /* chips */
   6351 
   6352 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   6353     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_BCM56640_A0r */
   6354         soc_block_list[4],
   6355         soc_genreg,
   6356         1,
   6357         0,
   6358         0x560c0000,
   6359         0,
   6360         0,
   6361         1,
   6362         soc_FT_CNTR_RAM_CONTROLr_fields,
   6363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6364         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6365         -1,
   6366         -1,
   6367     },
   6368 #endif /* chips */
   6369 
   6370 #if defined(BCM_53570_A0)
   6371     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_QG_TMr */
   6372         soc_block_list[4],
   6373         soc_genreg,
   6374         1,
   6375         0,
   6376         0x20efe00,
   6377         0,
   6378         0,
   6379         1,
   6380         soc_E2EFC_MEM_TMr_fields,
   6381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6382         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6383         -1,
   6384         -1,
   6385     },
   6386 #endif /* chips */
   6387 
   6388 #if defined(BCM_53570_B0)
   6389     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_QG_TM_BCM53570_B0r */
   6390         soc_block_list[4],
   6391         soc_genreg,
   6392         1,
   6393         0,
   6394         0x20f0100,
   6395         0,
   6396         0,
   6397         1,
   6398         soc_E2EFC_MEM_TMr_fields,
   6399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6400         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6401         -1,
   6402         -1,
   6403     },
   6404 #endif /* chips */
   6405 
   6406 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
   6407     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_TMr */
   6408         soc_block_list[4],
   6409         soc_genreg,
   6410         1,
   6411         0,
   6412         0x216a000,
   6413         0,
   6414         0,
   6415         1,
   6416         soc_DSCP_CONTROLr_fields,
   6417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6418         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6419         -1,
   6420         -1,
   6421     },
   6422 #endif /* chips */
   6423 
   6424 #if defined(BCM_53540_A0)
   6425     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_TM_BCM53540_A0r */
   6426         soc_block_list[4],
   6427         soc_genreg,
   6428         1,
   6429         0,
   6430         0x2083800,
   6431         0,
   6432         0,
   6433         1,
   6434         soc_DSCP_CONTROLr_fields,
   6435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6436         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6437         -1,
   6438         -1,
   6439     },
   6440 #endif /* chips */
   6441 
   6442 #if defined(BCM_53570_A0)
   6443     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_TM_BCM53570_A0r */
   6444         soc_block_list[4],
   6445         soc_genreg,
   6446         1,
   6447         0,
   6448         0x20eee00,
   6449         0,
   6450         0,
   6451         1,
   6452         soc_DSCP_CONTROLr_fields,
   6453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6454         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6455         -1,
   6456         -1,
   6457     },
   6458 #endif /* chips */
   6459 
   6460 #if defined(BCM_53570_B0)
   6461     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_TM_BCM53570_B0r */
   6462         soc_block_list[4],
   6463         soc_genreg,
   6464         1,
   6465         0,
   6466         0x20ef100,
   6467         0,
   6468         0,
   6469         1,
   6470         soc_DSCP_CONTROLr_fields,
   6471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6472         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6473         -1,
   6474         -1,
   6475     },
   6476 #endif /* chips */
   6477 
   6478 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6479     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_TM_BCM56960_A0r */
   6480         soc_block_list[124],
   6481         soc_pipereg,
   6482         1,
   6483         0,
   6484         0x21800f00,
   6485         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6486         0,
   6487         1,
   6488         soc_DSCP_CONTROLr_fields,
   6489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6490         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6491         -1,
   6492         -1,
   6493         3,
   6494     },
   6495 #endif /* chips */
   6496 
   6497 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   6498     defined(BCM_56870_A0) || defined(BCM_56970_A0)
   6499     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_TM_BCM56970_A0r */
   6500         soc_block_list[124],
   6501         soc_pipereg,
   6502         1,
   6503         0,
   6504         0x21801000,
   6505         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6506         0,
   6507         1,
   6508         soc_FP_METER_TMr_fields,
   6509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6510         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6511         -1,
   6512         -1,
   6513         3,
   6514     },
   6515 #endif /* chips */
   6516 
   6517 #if defined(BCM_56850_A0)
   6518     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_X_PIPE_TMr */
   6519         soc_block_list[4],
   6520         soc_genreg,
   6521         1,
   6522         0,
   6523         0x760c0000,
   6524         0,
   6525         0,
   6526         1,
   6527         soc_INTFO_QCN_SRAM_TMr_fields,
   6528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6529         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6530         -1,
   6531         -1,
   6532     },
   6533 #endif /* chips */
   6534 
   6535 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   6536     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   6537     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_X_PIPE_TM_BCM56560_A0r */
   6538         soc_block_list[4],
   6539         soc_genreg,
   6540         1,
   6541         0,
   6542         0x760c0000,
   6543         0,
   6544         0,
   6545         1,
   6546         soc_DSCP_CONTROLr_fields,
   6547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6548         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6549         -1,
   6550         -1,
   6551     },
   6552 #endif /* chips */
   6553 
   6554 #if defined(BCM_56860_A0)
   6555     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_X_PIPE_TM_BCM56860_A0r */
   6556         soc_block_list[4],
   6557         soc_genreg,
   6558         1,
   6559         0,
   6560         0x760c0000,
   6561         0,
   6562         0,
   6563         1,
   6564         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r_fields,
   6565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6566         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6567         -1,
   6568         -1,
   6569     },
   6570 #endif /* chips */
   6571 
   6572 #if defined(BCM_56850_A0)
   6573     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_Y_PIPE_TMr */
   6574         soc_block_list[4],
   6575         soc_genreg,
   6576         1,
   6577         0,
   6578         0x760c0100,
   6579         0,
   6580         0,
   6581         1,
   6582         soc_INTFO_QCN_SRAM_TMr_fields,
   6583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6584         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6585         -1,
   6586         -1,
   6587     },
   6588 #endif /* chips */
   6589 
   6590 #if defined(BCM_56860_A0)
   6591     { /* SOC_REG_INT_WREDMEMDEBUG_CONFIG_Y_PIPE_TM_BCM56860_A0r */
   6592         soc_block_list[4],
   6593         soc_genreg,
   6594         1,
   6595         0,
   6596         0x760c0100,
   6597         0,
   6598         0,
   6599         1,
   6600         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r_fields,
   6601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6602         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6603         -1,
   6604         -1,
   6605     },
   6606 #endif /* chips */
   6607 
   6608 #if defined(BCM_56850_A0)
   6609     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_CURVE_PROFILE_TMr */
   6610         soc_block_list[4],
   6611         soc_genreg,
   6612         1,
   6613         0,
   6614         0x760c1600,
   6615         0,
   6616         0,
   6617         1,
   6618         soc_MMU_REPL_STATE_MEMDEBUGr_fields,
   6619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6620         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6621         -1,
   6622         -1,
   6623     },
   6624 #endif /* chips */
   6625 
   6626 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   6627     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   6628     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_CURVE_PROFILE_TM_BCM56560_A0r */
   6629         soc_block_list[4],
   6630         soc_genreg,
   6631         1,
   6632         0,
   6633         0x760c1600,
   6634         0,
   6635         0,
   6636         1,
   6637         soc_E2EFC_MEM_TMr_fields,
   6638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6639         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6640         -1,
   6641         -1,
   6642     },
   6643 #endif /* chips */
   6644 
   6645 #if defined(BCM_56860_A0)
   6646     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_CURVE_PROFILE_TM_BCM56860_A0r */
   6647         soc_block_list[4],
   6648         soc_genreg,
   6649         1,
   6650         0,
   6651         0x760c1600,
   6652         0,
   6653         0,
   6654         1,
   6655         soc_IFP_COUNTER_MUX_RAM_CONTROLr_fields,
   6656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6657         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6658         -1,
   6659         -1,
   6660     },
   6661 #endif /* chips */
   6662 
   6663 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6664     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_CURVE_PROFILE_TM_BCM56960_A0r */
   6665         soc_block_list[124],
   6666         soc_genreg,
   6667         1,
   6668         0,
   6669         0x22001700,
   6670         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6671         0,
   6672         1,
   6673         soc_E2EFC_MEM_TMr_fields,
   6674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6675         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6676         -1,
   6677         -1,
   6678         3,
   6679     },
   6680 #endif /* chips */
   6681 
   6682 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   6683     defined(BCM_56870_A0) || defined(BCM_56970_A0)
   6684     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_CURVE_PROFILE_TM_BCM56970_A0r */
   6685         soc_block_list[124],
   6686         soc_genreg,
   6687         1,
   6688         0,
   6689         0x22001900,
   6690         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6691         0,
   6692         1,
   6693         soc_FP_METER_TMr_fields,
   6694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6695         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6696         -1,
   6697         -1,
   6698         3,
   6699     },
   6700 #endif /* chips */
   6701 
   6702 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
   6703     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_MARK_PROFILES_TMr */
   6704         soc_block_list[4],
   6705         soc_genreg,
   6706         1,
   6707         0,
   6708         0x216a300,
   6709         0,
   6710         0,
   6711         1,
   6712         soc_E2EFC_MEM_TMr_fields,
   6713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6714         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6715         -1,
   6716         -1,
   6717     },
   6718 #endif /* chips */
   6719 
   6720 #if defined(BCM_53540_A0)
   6721     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_MARK_PROFILES_TM_BCM53540_A0r */
   6722         soc_block_list[4],
   6723         soc_genreg,
   6724         1,
   6725         0,
   6726         0x2085000,
   6727         0,
   6728         0,
   6729         1,
   6730         soc_E2EFC_MEM_TMr_fields,
   6731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6732         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6733         -1,
   6734         -1,
   6735     },
   6736 #endif /* chips */
   6737 
   6738 #if defined(BCM_53570_A0)
   6739     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_MARK_PROFILES_TM_BCM53570_A0r */
   6740         soc_block_list[4],
   6741         soc_genreg,
   6742         1,
   6743         0,
   6744         0x20f1600,
   6745         0,
   6746         0,
   6747         1,
   6748         soc_E2EFC_MEM_TMr_fields,
   6749         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6750         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6751         -1,
   6752         -1,
   6753     },
   6754 #endif /* chips */
   6755 
   6756 #if defined(BCM_53570_B0)
   6757     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_MARK_PROFILES_TM_BCM53570_B0r */
   6758         soc_block_list[4],
   6759         soc_genreg,
   6760         1,
   6761         0,
   6762         0x20f1900,
   6763         0,
   6764         0,
   6765         1,
   6766         soc_E2EFC_MEM_TMr_fields,
   6767         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6768         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6769         -1,
   6770         -1,
   6771     },
   6772 #endif /* chips */
   6773 
   6774 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6775     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_THD_UC_DEQ0r */
   6776         soc_block_list[4],
   6777         soc_genreg,
   6778         1,
   6779         0,
   6780         0x17080c0e,
   6781         0,
   6782         0,
   6783         3,
   6784         soc_L3_DEFIP_128_DATA_DBGCTRL_BCM56840_A0r_fields,
   6785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6786         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6787         -1,
   6788         -1,
   6789     },
   6790 #endif /* chips */
   6791 
   6792 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6793     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_THD_UC_DEQ1r */
   6794         soc_block_list[4],
   6795         soc_genreg,
   6796         1,
   6797         0,
   6798         0x17080c0f,
   6799         0,
   6800         0,
   6801         3,
   6802         soc_L3_DEFIP_128_DATA_DBGCTRL_BCM56840_A0r_fields,
   6803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6804         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6805         -1,
   6806         -1,
   6807     },
   6808 #endif /* chips */
   6809 
   6810 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6811     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_THD_UC_ENQ0r */
   6812         soc_block_list[4],
   6813         soc_genreg,
   6814         1,
   6815         0,
   6816         0x17080c0c,
   6817         0,
   6818         0,
   6819         3,
   6820         soc_L3_DEFIP_128_DATA_DBGCTRL_BCM56840_A0r_fields,
   6821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6822         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6823         -1,
   6824         -1,
   6825     },
   6826 #endif /* chips */
   6827 
   6828 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6829     { /* SOC_REG_INT_WREDMEMDEBUG_DROP_THD_UC_ENQ1r */
   6830         soc_block_list[4],
   6831         soc_genreg,
   6832         1,
   6833         0,
   6834         0x17080c0d,
   6835         0,
   6836         0,
   6837         3,
   6838         soc_L3_DEFIP_128_DATA_DBGCTRL_BCM56840_A0r_fields,
   6839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6840         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6841         -1,
   6842         -1,
   6843     },
   6844 #endif /* chips */
   6845 
   6846 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
   6847     { /* SOC_REG_INT_WREDMEMDEBUG_MARK_THD_TMr */
   6848         soc_block_list[4],
   6849         soc_genreg,
   6850         1,
   6851         0,
   6852         0x216a200,
   6853         0,
   6854         0,
   6855         1,
   6856         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   6857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6858         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6859         -1,
   6860         -1,
   6861     },
   6862 #endif /* chips */
   6863 
   6864 #if defined(BCM_53540_A0)
   6865     { /* SOC_REG_INT_WREDMEMDEBUG_MARK_THD_TM_BCM53540_A0r */
   6866         soc_block_list[4],
   6867         soc_genreg,
   6868         1,
   6869         0,
   6870         0x2084800,
   6871         0,
   6872         0,
   6873         1,
   6874         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   6875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6876         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6877         -1,
   6878         -1,
   6879     },
   6880 #endif /* chips */
   6881 
   6882 #if defined(BCM_53570_A0)
   6883     { /* SOC_REG_INT_WREDMEMDEBUG_MARK_THD_TM_BCM53570_A0r */
   6884         soc_block_list[4],
   6885         soc_genreg,
   6886         1,
   6887         0,
   6888         0x20f0e00,
   6889         0,
   6890         0,
   6891         1,
   6892         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56260_A0r_fields,
   6893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6894         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6895         -1,
   6896         -1,
   6897     },
   6898 #endif /* chips */
   6899 
   6900 #if defined(BCM_53570_B0)
   6901     { /* SOC_REG_INT_WREDMEMDEBUG_MARK_THD_TM_BCM53570_B0r */
   6902         soc_block_list[4],
   6903         soc_genreg,
   6904         1,
   6905         0,
   6906         0x20f1100,
   6907         0,
   6908         0,
   6909         1,
   6910         soc_L2_USER_ENTRY_CAM_DBGCTRL_BCM56260_A0r_fields,
   6911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6912         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6913         -1,
   6914         -1,
   6915     },
   6916 #endif /* chips */
   6917 
   6918 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6919     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_AVG_QSIZEr */
   6920         soc_block_list[4],
   6921         soc_genreg,
   6922         1,
   6923         0,
   6924         0x17080016,
   6925         0,
   6926         0,
   6927         2,
   6928         soc_WREDMEMDEBUG_OPN_AVG_QSIZEr_fields,
   6929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6930         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6931         -1,
   6932         -1,
   6933     },
   6934 #endif /* chips */
   6935 
   6936 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   6937     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_AVG_QSIZE_BCM56260_A0r */
   6938         soc_block_list[4],
   6939         soc_genreg,
   6940         1,
   6941         0,
   6942         0x5e002600,
   6943         0,
   6944         0,
   6945         1,
   6946         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   6947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6948         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6949         -1,
   6950         -1,
   6951     },
   6952 #endif /* chips */
   6953 
   6954 #if defined(BCM_56270_A0)
   6955     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_AVG_QSIZE_BCM56270_A0r */
   6956         soc_block_list[4],
   6957         soc_genreg,
   6958         1,
   6959         0,
   6960         0x5e001c00,
   6961         0,
   6962         0,
   6963         1,
   6964         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   6965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6966         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6967         -1,
   6968         -1,
   6969     },
   6970 #endif /* chips */
   6971 
   6972 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6973     defined(BCM_56450_B1)
   6974     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_AVG_QSIZE_BCM56450_A0r */
   6975         soc_block_list[4],
   6976         soc_genreg,
   6977         1,
   6978         0,
   6979         0x5e002600,
   6980         0,
   6981         0,
   6982         1,
   6983         soc_FT_CNTR_RAM_CONTROLr_fields,
   6984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6985         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6986         -1,
   6987         -1,
   6988     },
   6989 #endif /* chips */
   6990 
   6991 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6992     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_CONFIGr */
   6993         soc_block_list[4],
   6994         soc_genreg,
   6995         1,
   6996         0,
   6997         0x17080015,
   6998         0,
   6999         0,
   7000         2,
   7001         soc_WREDMEMDEBUG_OPN_AVG_QSIZEr_fields,
   7002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7003         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7004         -1,
   7005         -1,
   7006     },
   7007 #endif /* chips */
   7008 
   7009 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   7010     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_CONFIG_BCM56260_A0r */
   7011         soc_block_list[4],
   7012         soc_genreg,
   7013         1,
   7014         0,
   7015         0x5e002500,
   7016         0,
   7017         0,
   7018         1,
   7019         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   7020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7021         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7022         -1,
   7023         -1,
   7024     },
   7025 #endif /* chips */
   7026 
   7027 #if defined(BCM_56270_A0)
   7028     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_CONFIG_BCM56270_A0r */
   7029         soc_block_list[4],
   7030         soc_genreg,
   7031         1,
   7032         0,
   7033         0x5e001b00,
   7034         0,
   7035         0,
   7036         1,
   7037         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   7038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7039         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7040         -1,
   7041         -1,
   7042     },
   7043 #endif /* chips */
   7044 
   7045 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7046     defined(BCM_56450_B1)
   7047     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_CONFIG_BCM56450_A0r */
   7048         soc_block_list[4],
   7049         soc_genreg,
   7050         1,
   7051         0,
   7052         0x5e002500,
   7053         0,
   7054         0,
   7055         1,
   7056         soc_FT_CNTR_RAM_CONTROLr_fields,
   7057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7058         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7059         -1,
   7060         -1,
   7061     },
   7062 #endif /* chips */
   7063 
   7064 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7065     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_DROP_THD_DEQr */
   7066         soc_block_list[4],
   7067         soc_genreg,
   7068         1,
   7069         0,
   7070         0x1708001a,
   7071         0,
   7072         0,
   7073         2,
   7074         soc_WREDMEMDEBUG_OPN_AVG_QSIZEr_fields,
   7075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7076         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7077         -1,
   7078         -1,
   7079     },
   7080 #endif /* chips */
   7081 
   7082 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   7083     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_DROP_THD_DEQ_BCM56260_A0r */
   7084         soc_block_list[4],
   7085         soc_genreg,
   7086         1,
   7087         0,
   7088         0x5e002b00,
   7089         0,
   7090         0,
   7091         1,
   7092         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   7093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7094         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7095         -1,
   7096         -1,
   7097     },
   7098 #endif /* chips */
   7099 
   7100 #if defined(BCM_56270_A0)
   7101     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_DROP_THD_DEQ_BCM56270_A0r */
   7102         soc_block_list[4],
   7103         soc_genreg,
   7104         1,
   7105         0,
   7106         0x5e002100,
   7107         0,
   7108         0,
   7109         1,
   7110         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   7111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7112         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7113         -1,
   7114         -1,
   7115     },
   7116 #endif /* chips */
   7117 
   7118 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7119     defined(BCM_56450_B1)
   7120     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_DROP_THD_DEQ_BCM56450_A0r */
   7121         soc_block_list[4],
   7122         soc_genreg,
   7123         1,
   7124         0,
   7125         0x5e002b00,
   7126         0,
   7127         0,
   7128         1,
   7129         soc_FT_CNTR_RAM_CONTROLr_fields,
   7130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7131         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7132         -1,
   7133         -1,
   7134     },
   7135 #endif /* chips */
   7136 
   7137 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7138     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_DROP_THD_ENQr */
   7139         soc_block_list[4],
   7140         soc_genreg,
   7141         1,
   7142         0,
   7143         0x17080019,
   7144         0,
   7145         0,
   7146         2,
   7147         soc_WREDMEMDEBUG_OPN_AVG_QSIZEr_fields,
   7148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7150         -1,
   7151         -1,
   7152     },
   7153 #endif /* chips */
   7154 
   7155 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   7156     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_DROP_THD_ENQ_BCM56260_A0r */
   7157         soc_block_list[4],
   7158         soc_genreg,
   7159         1,
   7160         0,
   7161         0x5e002a00,
   7162         0,
   7163         0,
   7164         1,
   7165         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   7166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7167         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7168         -1,
   7169         -1,
   7170     },
   7171 #endif /* chips */
   7172 
   7173 #if defined(BCM_56270_A0)
   7174     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_DROP_THD_ENQ_BCM56270_A0r */
   7175         soc_block_list[4],
   7176         soc_genreg,
   7177         1,
   7178         0,
   7179         0x5e002000,
   7180         0,
   7181         0,
   7182         1,
   7183         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   7184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7185         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7186         -1,
   7187         -1,
   7188     },
   7189 #endif /* chips */
   7190 
   7191 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7192     defined(BCM_56450_B1)
   7193     { /* SOC_REG_INT_WREDMEMDEBUG_OPN_DROP_THD_ENQ_BCM56450_A0r */
   7194         soc_block_list[4],
   7195         soc_genreg,
   7196         1,
   7197         0,
   7198         0x5e002a00,
   7199         0,
   7200         0,
   7201         1,
   7202         soc_FT_CNTR_RAM_CONTROLr_fields,
   7203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7204         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7205         -1,
   7206         -1,
   7207     },
   7208 #endif /* chips */
   7209 
   7210 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   7211     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_DROP_THDr */
   7212         soc_block_list[4],
   7213         soc_genreg,
   7214         1,
   7215         0,
   7216         0x560c0c00,
   7217         0,
   7218         0,
   7219         1,
   7220         soc_FT_CNTR_RAM_CONTROLr_fields,
   7221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7222         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7223         -1,
   7224         -1,
   7225     },
   7226 #endif /* chips */
   7227 
   7228 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7229     defined(BCM_56870_A0) || defined(BCM_56970_A0)
   7230     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_DROP_THD_MARK_TMr */
   7231         soc_block_list[124],
   7232         soc_pipereg,
   7233         1,
   7234         0,
   7235         0x21801700,
   7236         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7237         0,
   7238         1,
   7239         soc_FP_METER_TMr_fields,
   7240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7241         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7242         -1,
   7243         -1,
   7244         3,
   7245     },
   7246 #endif /* chips */
   7247 
   7248 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7249     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_DROP_THD_TMr */
   7250         soc_block_list[124],
   7251         soc_pipereg,
   7252         1,
   7253         0,
   7254         0x21801500,
   7255         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7256         0,
   7257         1,
   7258         soc_E2EFC_MEM_TMr_fields,
   7259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7260         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7261         -1,
   7262         -1,
   7263         3,
   7264     },
   7265 #endif /* chips */
   7266 
   7267 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7268     defined(BCM_56870_A0) || defined(BCM_56970_A0)
   7269     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_DROP_THD_TM_BCM56970_A0r */
   7270         soc_block_list[124],
   7271         soc_pipereg,
   7272         1,
   7273         0,
   7274         0x21801600,
   7275         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7276         0,
   7277         1,
   7278         soc_FP_METER_TMr_fields,
   7279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7280         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7281         -1,
   7282         -1,
   7283         3,
   7284     },
   7285 #endif /* chips */
   7286 
   7287 #if defined(BCM_56850_A0)
   7288     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_DROP_THD_X_PIPE_TMr */
   7289         soc_block_list[4],
   7290         soc_genreg,
   7291         1,
   7292         0,
   7293         0x760c0e00,
   7294         0,
   7295         0,
   7296         1,
   7297         soc_MMU_REPL_STATE_MEMDEBUGr_fields,
   7298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7299         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7300         -1,
   7301         -1,
   7302     },
   7303 #endif /* chips */
   7304 
   7305 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   7306     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   7307     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_DROP_THD_X_PIPE_TM_BCM56560_A0r */
   7308         soc_block_list[4],
   7309         soc_genreg,
   7310         1,
   7311         0,
   7312         0x760c0e00,
   7313         0,
   7314         0,
   7315         1,
   7316         soc_E2EFC_MEM_TMr_fields,
   7317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7318         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7319         -1,
   7320         -1,
   7321     },
   7322 #endif /* chips */
   7323 
   7324 #if defined(BCM_56860_A0)
   7325     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_DROP_THD_X_PIPE_TM_BCM56860_A0r */
   7326         soc_block_list[4],
   7327         soc_genreg,
   7328         1,
   7329         0,
   7330         0x760c0e00,
   7331         0,
   7332         0,
   7333         1,
   7334         soc_IFP_COUNTER_MUX_RAM_CONTROLr_fields,
   7335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7336         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7337         -1,
   7338         -1,
   7339     },
   7340 #endif /* chips */
   7341 
   7342 #if defined(BCM_56850_A0)
   7343     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_DROP_THD_Y_PIPE_TMr */
   7344         soc_block_list[4],
   7345         soc_genreg,
   7346         1,
   7347         0,
   7348         0x760c0f00,
   7349         0,
   7350         0,
   7351         1,
   7352         soc_MMU_REPL_STATE_MEMDEBUGr_fields,
   7353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7354         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7355         -1,
   7356         -1,
   7357     },
   7358 #endif /* chips */
   7359 
   7360 #if defined(BCM_56860_A0)
   7361     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_DROP_THD_Y_PIPE_TM_BCM56860_A0r */
   7362         soc_block_list[4],
   7363         soc_genreg,
   7364         1,
   7365         0,
   7366         0x760c0f00,
   7367         0,
   7368         0,
   7369         1,
   7370         soc_IFP_COUNTER_MUX_RAM_CONTROLr_fields,
   7371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7372         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7373         -1,
   7374         -1,
   7375     },
   7376 #endif /* chips */
   7377 
   7378 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   7379     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_SHARED_COUNTr */
   7380         soc_block_list[4],
   7381         soc_genreg,
   7382         1,
   7383         0,
   7384         0x560c0800,
   7385         0,
   7386         0,
   7387         1,
   7388         soc_UCQDBMEMDEBUGr_fields,
   7389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7390         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7391         -1,
   7392         -1,
   7393     },
   7394 #endif /* chips */
   7395 
   7396 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7397     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_SHARED_COUNT_TMr */
   7398         soc_block_list[124],
   7399         soc_pipereg,
   7400         1,
   7401         0,
   7402         0x21801600,
   7403         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7404         0,
   7405         1,
   7406         soc_CCPMEMDEBUG_BCM56960_A0r_fields,
   7407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7408         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7409         -1,
   7410         -1,
   7411         3,
   7412     },
   7413 #endif /* chips */
   7414 
   7415 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7416     defined(BCM_56870_A0) || defined(BCM_56970_A0)
   7417     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_SHARED_COUNT_TM_BCM56970_A0r */
   7418         soc_block_list[124],
   7419         soc_pipereg,
   7420         1,
   7421         0,
   7422         0x21801800,
   7423         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7424         0,
   7425         1,
   7426         soc_CCPMEMDEBUG_BCM56960_A0r_fields,
   7427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7429         -1,
   7430         -1,
   7431         3,
   7432     },
   7433 #endif /* chips */
   7434 
   7435 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   7436     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_SHARED_COUNT_X_PIPE_TMr */
   7437         soc_block_list[4],
   7438         soc_genreg,
   7439         1,
   7440         0,
   7441         0x760c1400,
   7442         0,
   7443         0,
   7444         1,
   7445         soc_UCQDBMEMDEBUGr_fields,
   7446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7447         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7448         -1,
   7449         -1,
   7450     },
   7451 #endif /* chips */
   7452 
   7453 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   7454     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   7455     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_SHARED_COUNT_X_PIPE_TM_BCM56560_A0r */
   7456         soc_block_list[4],
   7457         soc_genreg,
   7458         1,
   7459         0,
   7460         0x760c1400,
   7461         0,
   7462         0,
   7463         1,
   7464         soc_CCPMEMDEBUG_BCM56960_A0r_fields,
   7465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7466         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7467         -1,
   7468         -1,
   7469     },
   7470 #endif /* chips */
   7471 
   7472 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   7473     { /* SOC_REG_INT_WREDMEMDEBUG_PORT_SP_SHARED_COUNT_Y_PIPE_TMr */
   7474         soc_block_list[4],
   7475         soc_genreg,
   7476         1,
   7477         0,
   7478         0x760c1500,
   7479         0,
   7480         0,
   7481         1,
   7482         soc_UCQDBMEMDEBUGr_fields,
   7483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7484         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7485         -1,
   7486         -1,
   7487     },
   7488 #endif /* chips */
   7489 
   7490 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   7491     { /* SOC_REG_INT_WREDMEMDEBUG_PROFILEr */
   7492         soc_block_list[4],
   7493         soc_genreg,
   7494         1,
   7495         0,
   7496         0x17080c02,
   7497         0,
   7498         0,
   7499         6,
   7500         soc_WREDMEMDEBUG_PROFILEr_fields,
   7501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7502         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7503         -1,
   7504         -1,
   7505     },
   7506 #endif /* chips */
   7507 
   7508 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   7509     { /* SOC_REG_INT_WREDMEMDEBUG_PROFILE_BCM56260_A0r */
   7510         soc_block_list[4],
   7511         soc_genreg,
   7512         1,
   7513         0,
   7514         0x5e002700,
   7515         0,
   7516         0,
   7517         1,
   7518         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   7519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7520         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7521         -1,
   7522         -1,
   7523     },
   7524 #endif /* chips */
   7525 
   7526 #if defined(BCM_56270_A0)
   7527     { /* SOC_REG_INT_WREDMEMDEBUG_PROFILE_BCM56270_A0r */
   7528         soc_block_list[4],
   7529         soc_genreg,
   7530         1,
   7531         0,
   7532         0x5e001d00,
   7533         0,
   7534         0,
   7535         1,
   7536         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   7537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7539         -1,
   7540         -1,
   7541     },
   7542 #endif /* chips */
   7543 
   7544 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7545     defined(BCM_56450_B1)
   7546     { /* SOC_REG_INT_WREDMEMDEBUG_PROFILE_BCM56450_A0r */
   7547         soc_block_list[4],
   7548         soc_genreg,
   7549         1,
   7550         0,
   7551         0x5e002700,
   7552         0,
   7553         0,
   7554         1,
   7555         soc_FT_CNTR_RAM_CONTROLr_fields,
   7556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7558         -1,
   7559         -1,
   7560     },
   7561 #endif /* chips */
   7562 
   7563 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   7564     { /* SOC_REG_INT_WREDMEMDEBUG_QGROUP_DROP_THDr */
   7565         soc_block_list[4],
   7566         soc_genreg,
   7567         1,
   7568         0,
   7569         0x560c0b00,
   7570         0,
   7571         0,
   7572         1,
   7573         soc_FT_CNTR_RAM_CONTROLr_fields,
   7574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7575         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7576         -1,
   7577         -1,
   7578     },
   7579 #endif /* chips */
   7580 
   7581 #if defined(BCM_56850_A0)
   7582     { /* SOC_REG_INT_WREDMEMDEBUG_QGROUP_DROP_THD_X_PIPE_TMr */
   7583         soc_block_list[4],
   7584         soc_genreg,
   7585         1,
   7586         0,
   7587         0x760c0c00,
   7588         0,
   7589         0,
   7590         1,
   7591         soc_MMU_REPL_STATE_MEMDEBUGr_fields,
   7592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7593         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7594         -1,
   7595         -1,
   7596     },
   7597 #endif /* chips */
   7598 
   7599 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   7600     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   7601     { /* SOC_REG_INT_WREDMEMDEBUG_QGROUP_DROP_THD_X_PIPE_TM_BCM56560_A0r */
   7602         soc_block_list[4],
   7603         soc_genreg,
   7604         1,
   7605         0,
   7606         0x760c0c00,
   7607         0,
   7608         0,
   7609         1,
   7610         soc_DSCP_CONTROLr_fields,
   7611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7613         -1,
   7614         -1,
   7615     },
   7616 #endif /* chips */
   7617 
   7618 #if defined(BCM_56860_A0)
   7619     { /* SOC_REG_INT_WREDMEMDEBUG_QGROUP_DROP_THD_X_PIPE_TM_BCM56860_A0r */
   7620         soc_block_list[4],
   7621         soc_genreg,
   7622         1,
   7623         0,
   7624         0x760c0c00,
   7625         0,
   7626         0,
   7627         1,
   7628         soc_IFP_COUNTER_MUX_RAM_CONTROLr_fields,
   7629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7630         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7631         -1,
   7632         -1,
   7633     },
   7634 #endif /* chips */
   7635 
   7636 #if defined(BCM_56850_A0)
   7637     { /* SOC_REG_INT_WREDMEMDEBUG_QGROUP_DROP_THD_Y_PIPE_TMr */
   7638         soc_block_list[4],
   7639         soc_genreg,
   7640         1,
   7641         0,
   7642         0x760c0d00,
   7643         0,
   7644         0,
   7645         1,
   7646         soc_MMU_REPL_STATE_MEMDEBUGr_fields,
   7647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7649         -1,
   7650         -1,
   7651     },
   7652 #endif /* chips */
   7653 
   7654 #if defined(BCM_56860_A0)
   7655     { /* SOC_REG_INT_WREDMEMDEBUG_QGROUP_DROP_THD_Y_PIPE_TM_BCM56860_A0r */
   7656         soc_block_list[4],
   7657         soc_genreg,
   7658         1,
   7659         0,
   7660         0x760c0d00,
   7661         0,
   7662         0,
   7663         1,
   7664         soc_IFP_COUNTER_MUX_RAM_CONTROLr_fields,
   7665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7666         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7667         -1,
   7668         -1,
   7669     },
   7670 #endif /* chips */
   7671 
   7672 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   7673     { /* SOC_REG_INT_WREDMEMDEBUG_QGROUP_SHARED_COUNTr */
   7674         soc_block_list[4],
   7675         soc_genreg,
   7676         1,
   7677         0,
   7678         0x560c0700,
   7679         0,
   7680         0,
   7681         1,
   7682         soc_UCQDBMEMDEBUGr_fields,
   7683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7684         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7685         -1,
   7686         -1,
   7687     },
   7688 #endif /* chips */
   7689 
   7690 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   7691     { /* SOC_REG_INT_WREDMEMDEBUG_QGROUP_SHARED_COUNT_X_PIPE_TMr */
   7692         soc_block_list[4],
   7693         soc_genreg,
   7694         1,
   7695         0,
   7696         0x760c1200,
   7697         0,
   7698         0,
   7699         1,
   7700         soc_UCQDBMEMDEBUGr_fields,
   7701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7702         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7703         -1,
   7704         -1,
   7705     },
   7706 #endif /* chips */
   7707 
   7708 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   7709     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   7710     { /* SOC_REG_INT_WREDMEMDEBUG_QGROUP_SHARED_COUNT_X_PIPE_TM_BCM56560_A0r */
   7711         soc_block_list[4],
   7712         soc_genreg,
   7713         1,
   7714         0,
   7715         0x760c1200,
   7716         0,
   7717         0,
   7718         1,
   7719         soc_CCPMEMDEBUG_BCM56960_A0r_fields,
   7720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7721         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7722         -1,
   7723         -1,
   7724     },
   7725 #endif /* chips */
   7726 
   7727 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   7728     { /* SOC_REG_INT_WREDMEMDEBUG_QGROUP_SHARED_COUNT_Y_PIPE_TMr */
   7729         soc_block_list[4],
   7730         soc_genreg,
   7731         1,
   7732         0,
   7733         0x760c1300,
   7734         0,
   7735         0,
   7736         1,
   7737         soc_UCQDBMEMDEBUGr_fields,
   7738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7739         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7740         -1,
   7741         -1,
   7742     },
   7743 #endif /* chips */
   7744 
   7745 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7746     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_AVG_QSIZEr */
   7747         soc_block_list[4],
   7748         soc_genreg,
   7749         1,
   7750         0,
   7751         0x17080014,
   7752         0,
   7753         0,
   7754         2,
   7755         soc_WREDMEMDEBUG_OPN_AVG_QSIZEr_fields,
   7756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7757         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7758         -1,
   7759         -1,
   7760     },
   7761 #endif /* chips */
   7762 
   7763 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   7764     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_AVG_QSIZE_BCM56260_A0r */
   7765         soc_block_list[4],
   7766         soc_genreg,
   7767         1,
   7768         0,
   7769         0x5e002400,
   7770         0,
   7771         0,
   7772         1,
   7773         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   7774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7775         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7776         -1,
   7777         -1,
   7778     },
   7779 #endif /* chips */
   7780 
   7781 #if defined(BCM_56270_A0)
   7782     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_AVG_QSIZE_BCM56270_A0r */
   7783         soc_block_list[4],
   7784         soc_genreg,
   7785         1,
   7786         0,
   7787         0x5e001a00,
   7788         0,
   7789         0,
   7790         1,
   7791         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   7792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7793         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7794         -1,
   7795         -1,
   7796     },
   7797 #endif /* chips */
   7798 
   7799 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7800     defined(BCM_56450_B1)
   7801     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_AVG_QSIZE_BCM56450_A0r */
   7802         soc_block_list[4],
   7803         soc_genreg,
   7804         1,
   7805         0,
   7806         0x5e002400,
   7807         0,
   7808         0,
   7809         3,
   7810         soc_WREDMEMDEBUG_QUEUE_AVG_QSIZEr_fields,
   7811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7812         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7813         -1,
   7814         -1,
   7815     },
   7816 #endif /* chips */
   7817 
   7818 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7819     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_CONFIGr */
   7820         soc_block_list[4],
   7821         soc_genreg,
   7822         1,
   7823         0,
   7824         0x17080013,
   7825         0,
   7826         0,
   7827         2,
   7828         soc_WREDMEMDEBUG_OPN_AVG_QSIZEr_fields,
   7829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7830         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7831         -1,
   7832         -1,
   7833     },
   7834 #endif /* chips */
   7835 
   7836 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   7837     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_CONFIG_BCM56260_A0r */
   7838         soc_block_list[4],
   7839         soc_genreg,
   7840         1,
   7841         0,
   7842         0x5e002300,
   7843         0,
   7844         0,
   7845         1,
   7846         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   7847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7848         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7849         -1,
   7850         -1,
   7851     },
   7852 #endif /* chips */
   7853 
   7854 #if defined(BCM_56270_A0)
   7855     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_CONFIG_BCM56270_A0r */
   7856         soc_block_list[4],
   7857         soc_genreg,
   7858         1,
   7859         0,
   7860         0x5e001900,
   7861         0,
   7862         0,
   7863         1,
   7864         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   7865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7866         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7867         -1,
   7868         -1,
   7869     },
   7870 #endif /* chips */
   7871 
   7872 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7873     defined(BCM_56450_B1)
   7874     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_CONFIG_BCM56450_A0r */
   7875         soc_block_list[4],
   7876         soc_genreg,
   7877         1,
   7878         0,
   7879         0x5e002300,
   7880         0,
   7881         0,
   7882         3,
   7883         soc_WREDMEMDEBUG_QUEUE_AVG_QSIZEr_fields,
   7884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7885         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7886         -1,
   7887         -1,
   7888     },
   7889 #endif /* chips */
   7890 
   7891 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7892     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_DROP_THD_DEQr */
   7893         soc_block_list[4],
   7894         soc_genreg,
   7895         1,
   7896         0,
   7897         0x17080018,
   7898         0,
   7899         0,
   7900         2,
   7901         soc_WREDMEMDEBUG_OPN_AVG_QSIZEr_fields,
   7902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7904         -1,
   7905         -1,
   7906     },
   7907 #endif /* chips */
   7908 
   7909 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   7910     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_DROP_THD_DEQ_BCM56260_A0r */
   7911         soc_block_list[4],
   7912         soc_genreg,
   7913         1,
   7914         0,
   7915         0x5e002900,
   7916         0,
   7917         0,
   7918         1,
   7919         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   7920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7922         -1,
   7923         -1,
   7924     },
   7925 #endif /* chips */
   7926 
   7927 #if defined(BCM_56270_A0)
   7928     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_DROP_THD_DEQ_BCM56270_A0r */
   7929         soc_block_list[4],
   7930         soc_genreg,
   7931         1,
   7932         0,
   7933         0x5e001f00,
   7934         0,
   7935         0,
   7936         1,
   7937         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   7938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7939         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7940         -1,
   7941         -1,
   7942     },
   7943 #endif /* chips */
   7944 
   7945 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7946     defined(BCM_56450_B1)
   7947     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_DROP_THD_DEQ_BCM56450_A0r */
   7948         soc_block_list[4],
   7949         soc_genreg,
   7950         1,
   7951         0,
   7952         0x5e002900,
   7953         0,
   7954         0,
   7955         3,
   7956         soc_WREDMEMDEBUG_QUEUE_AVG_QSIZEr_fields,
   7957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7958         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7959         -1,
   7960         -1,
   7961     },
   7962 #endif /* chips */
   7963 
   7964 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   7965     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_DROP_THD_ENQr */
   7966         soc_block_list[4],
   7967         soc_genreg,
   7968         1,
   7969         0,
   7970         0x17080017,
   7971         0,
   7972         0,
   7973         2,
   7974         soc_WREDMEMDEBUG_OPN_AVG_QSIZEr_fields,
   7975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7976         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7977         -1,
   7978         -1,
   7979     },
   7980 #endif /* chips */
   7981 
   7982 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   7983     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_DROP_THD_ENQ_BCM56260_A0r */
   7984         soc_block_list[4],
   7985         soc_genreg,
   7986         1,
   7987         0,
   7988         0x5e002800,
   7989         0,
   7990         0,
   7991         1,
   7992         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   7993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7994         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7995         -1,
   7996         -1,
   7997     },
   7998 #endif /* chips */
   7999 
   8000 #if defined(BCM_56270_A0)
   8001     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_DROP_THD_ENQ_BCM56270_A0r */
   8002         soc_block_list[4],
   8003         soc_genreg,
   8004         1,
   8005         0,
   8006         0x5e001e00,
   8007         0,
   8008         0,
   8009         1,
   8010         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   8011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8012         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8013         -1,
   8014         -1,
   8015     },
   8016 #endif /* chips */
   8017 
   8018 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   8019     defined(BCM_56450_B1)
   8020     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_DROP_THD_ENQ_BCM56450_A0r */
   8021         soc_block_list[4],
   8022         soc_genreg,
   8023         1,
   8024         0,
   8025         0x5e002800,
   8026         0,
   8027         0,
   8028         3,
   8029         soc_WREDMEMDEBUG_QUEUE_AVG_QSIZEr_fields,
   8030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8032         -1,
   8033         -1,
   8034     },
   8035 #endif /* chips */
   8036 
   8037 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8038     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_OPN_MAPr */
   8039         soc_block_list[4],
   8040         soc_genreg,
   8041         1,
   8042         0,
   8043         0x1708001b,
   8044         0,
   8045         0,
   8046         2,
   8047         soc_WREDMEMDEBUG_OPN_AVG_QSIZEr_fields,
   8048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8049         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8050         -1,
   8051         -1,
   8052     },
   8053 #endif /* chips */
   8054 
   8055 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   8056     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_OPN_MAP_BCM56260_A0r */
   8057         soc_block_list[4],
   8058         soc_genreg,
   8059         1,
   8060         0,
   8061         0x5e002c00,
   8062         0,
   8063         0,
   8064         1,
   8065         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   8066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8067         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8068         -1,
   8069         -1,
   8070     },
   8071 #endif /* chips */
   8072 
   8073 #if defined(BCM_56270_A0)
   8074     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_OPN_MAP_BCM56270_A0r */
   8075         soc_block_list[4],
   8076         soc_genreg,
   8077         1,
   8078         0,
   8079         0x5e002200,
   8080         0,
   8081         0,
   8082         1,
   8083         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   8084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8085         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8086         -1,
   8087         -1,
   8088     },
   8089 #endif /* chips */
   8090 
   8091 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   8092     defined(BCM_56450_B1)
   8093     { /* SOC_REG_INT_WREDMEMDEBUG_QUEUE_OPN_MAP_BCM56450_A0r */
   8094         soc_block_list[4],
   8095         soc_genreg,
   8096         1,
   8097         0,
   8098         0x5e002c00,
   8099         0,
   8100         0,
   8101         3,
   8102         soc_WREDMEMDEBUG_QUEUE_AVG_QSIZEr_fields,
   8103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8105         -1,
   8106         -1,
   8107     },
   8108 #endif /* chips */
   8109 
   8110 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   8111     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   8112     { /* SOC_REG_INT_WREDMEMDEBUG_THD_0_CELLr */
   8113         soc_block_list[4],
   8114         soc_genreg,
   8115         1,
   8116         0,
   8117         0x17080401,
   8118         0,
   8119         0,
   8120         2,
   8121         soc_WREDMEMDEBUG_CFG_CELLr_fields,
   8122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8124         -1,
   8125         -1,
   8126     },
   8127 #endif /* chips */
   8128 
   8129 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   8130     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8131     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8132     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8133     { /* SOC_REG_INT_WREDMEMDEBUG_THD_0_CELL_BCM56634_A0r */
   8134         soc_block_list[4],
   8135         soc_genreg,
   8136         1,
   8137         0,
   8138         0x17080401,
   8139         0,
   8140         0,
   8141         1,
   8142         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
   8143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8144         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8145         -1,
   8146         -1,
   8147     },
   8148 #endif /* chips */
   8149 
   8150 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8151     { /* SOC_REG_INT_WREDMEMDEBUG_THD_0_CELL_BCM56820_A0r */
   8152         soc_block_list[4],
   8153         soc_genreg,
   8154         1,
   8155         0,
   8156         0x12080401,
   8157         0,
   8158         0,
   8159         2,
   8160         soc_WREDMEMDEBUG_CFG_CELLr_fields,
   8161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8162         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8163         -1,
   8164         -1,
   8165     },
   8166 #endif /* chips */
   8167 
   8168 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   8169     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   8170     { /* SOC_REG_INT_WREDMEMDEBUG_THD_0_PACKETr */
   8171         soc_block_list[4],
   8172         soc_genreg,
   8173         1,
   8174         0,
   8175         0x17080404,
   8176         0,
   8177         0,
   8178         2,
   8179         soc_WREDMEMDEBUG_CFG_CELLr_fields,
   8180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8182         -1,
   8183         -1,
   8184     },
   8185 #endif /* chips */
   8186 
   8187 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   8188     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8189     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8190     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8191     { /* SOC_REG_INT_WREDMEMDEBUG_THD_0_PACKET_BCM56634_A0r */
   8192         soc_block_list[4],
   8193         soc_genreg,
   8194         1,
   8195         0,
   8196         0x17080404,
   8197         0,
   8198         0,
   8199         1,
   8200         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
   8201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8202         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8203         -1,
   8204         -1,
   8205     },
   8206 #endif /* chips */
   8207 
   8208 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   8209     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   8210     { /* SOC_REG_INT_WREDMEMDEBUG_THD_1_CELLr */
   8211         soc_block_list[4],
   8212         soc_genreg,
   8213         1,
   8214         0,
   8215         0x17080402,
   8216         0,
   8217         0,
   8218         2,
   8219         soc_WREDMEMDEBUG_CFG_CELLr_fields,
   8220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8221         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8222         -1,
   8223         -1,
   8224     },
   8225 #endif /* chips */
   8226 
   8227 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   8228     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8229     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8230     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8231     { /* SOC_REG_INT_WREDMEMDEBUG_THD_1_CELL_BCM56634_A0r */
   8232         soc_block_list[4],
   8233         soc_genreg,
   8234         1,
   8235         0,
   8236         0x17080402,
   8237         0,
   8238         0,
   8239         1,
   8240         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
   8241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8242         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8243         -1,
   8244         -1,
   8245     },
   8246 #endif /* chips */
   8247 
   8248 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8249     { /* SOC_REG_INT_WREDMEMDEBUG_THD_1_CELL_BCM56820_A0r */
   8250         soc_block_list[4],
   8251         soc_genreg,
   8252         1,
   8253         0,
   8254         0x12080402,
   8255         0,
   8256         0,
   8257         2,
   8258         soc_WREDMEMDEBUG_CFG_CELLr_fields,
   8259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8260         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8261         -1,
   8262         -1,
   8263     },
   8264 #endif /* chips */
   8265 
   8266 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   8267     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   8268     { /* SOC_REG_INT_WREDMEMDEBUG_THD_1_PACKETr */
   8269         soc_block_list[4],
   8270         soc_genreg,
   8271         1,
   8272         0,
   8273         0x17080405,
   8274         0,
   8275         0,
   8276         2,
   8277         soc_WREDMEMDEBUG_CFG_CELLr_fields,
   8278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8279         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8280         -1,
   8281         -1,
   8282     },
   8283 #endif /* chips */
   8284 
   8285 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   8286     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8287     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8288     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8289     { /* SOC_REG_INT_WREDMEMDEBUG_THD_1_PACKET_BCM56634_A0r */
   8290         soc_block_list[4],
   8291         soc_genreg,
   8292         1,
   8293         0,
   8294         0x17080405,
   8295         0,
   8296         0,
   8297         1,
   8298         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
   8299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8300         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8301         -1,
   8302         -1,
   8303     },
   8304 #endif /* chips */
   8305 
   8306 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   8307     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_0_TMr */
   8308         soc_block_list[124],
   8309         soc_pipereg,
   8310         1,
   8311         0,
   8312         0x21801100,
   8313         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8314         0,
   8315         1,
   8316         soc_E2EFC_MEM_TMr_fields,
   8317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8318         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8319         -1,
   8320         -1,
   8321         3,
   8322     },
   8323 #endif /* chips */
   8324 
   8325 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   8326     defined(BCM_56870_A0) || defined(BCM_56970_A0)
   8327     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_0_TM_BCM56970_A0r */
   8328         soc_block_list[124],
   8329         soc_pipereg,
   8330         1,
   8331         0,
   8332         0x21801200,
   8333         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8334         0,
   8335         1,
   8336         soc_FP_METER_TMr_fields,
   8337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8339         -1,
   8340         -1,
   8341         3,
   8342     },
   8343 #endif /* chips */
   8344 
   8345 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   8346     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_1_TMr */
   8347         soc_block_list[124],
   8348         soc_pipereg,
   8349         1,
   8350         0,
   8351         0x21801200,
   8352         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8353         0,
   8354         1,
   8355         soc_E2EFC_MEM_TMr_fields,
   8356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8357         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8358         -1,
   8359         -1,
   8360         3,
   8361     },
   8362 #endif /* chips */
   8363 
   8364 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8365     defined(BCM_56970_A0)
   8366     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_1_TM_BCM56970_A0r */
   8367         soc_block_list[124],
   8368         soc_pipereg,
   8369         1,
   8370         0,
   8371         0x21801300,
   8372         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8373         0,
   8374         1,
   8375         soc_FP_METER_TMr_fields,
   8376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8377         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8378         -1,
   8379         -1,
   8380         3,
   8381     },
   8382 #endif /* chips */
   8383 
   8384 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   8385     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQr */
   8386         soc_block_list[4],
   8387         soc_genreg,
   8388         1,
   8389         0,
   8390         0x560c0a00,
   8391         0,
   8392         0,
   8393         1,
   8394         soc_FT_CNTR_RAM_CONTROLr_fields,
   8395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8396         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8397         -1,
   8398         -1,
   8399     },
   8400 #endif /* chips */
   8401 
   8402 #if defined(BCM_56850_A0)
   8403     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_X_PIPE_0_TMr */
   8404         soc_block_list[4],
   8405         soc_genreg,
   8406         1,
   8407         0,
   8408         0x760c0800,
   8409         0,
   8410         0,
   8411         1,
   8412         soc_FT_CNTR_RAM_CONTROLr_fields,
   8413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8414         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8415         -1,
   8416         -1,
   8417     },
   8418 #endif /* chips */
   8419 
   8420 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   8421     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_X_PIPE_0_TM_BCM56560_A0r */
   8422         soc_block_list[4],
   8423         soc_genreg,
   8424         1,
   8425         0,
   8426         0x760c0800,
   8427         0,
   8428         0,
   8429         1,
   8430         soc_CCPMEMDEBUG_BCM56560_A0r_fields,
   8431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8433         -1,
   8434         -1,
   8435     },
   8436 #endif /* chips */
   8437 
   8438 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   8439     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_X_PIPE_0_TM_BCM56670_A0r */
   8440         soc_block_list[4],
   8441         soc_genreg,
   8442         1,
   8443         0,
   8444         0x760c0800,
   8445         0,
   8446         0,
   8447         1,
   8448         soc_E2EFC_MEM_TMr_fields,
   8449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8450         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8451         -1,
   8452         -1,
   8453     },
   8454 #endif /* chips */
   8455 
   8456 #if defined(BCM_56860_A0)
   8457     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_X_PIPE_0_TM_BCM56860_A0r */
   8458         soc_block_list[4],
   8459         soc_genreg,
   8460         1,
   8461         0,
   8462         0x760c0800,
   8463         0,
   8464         0,
   8465         1,
   8466         soc_MCFP_MEM_DEBUG_TMr_fields,
   8467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8468         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8469         -1,
   8470         -1,
   8471     },
   8472 #endif /* chips */
   8473 
   8474 #if defined(BCM_56850_A0)
   8475     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_X_PIPE_1_TMr */
   8476         soc_block_list[4],
   8477         soc_genreg,
   8478         1,
   8479         0,
   8480         0x760c0900,
   8481         0,
   8482         0,
   8483         1,
   8484         soc_FT_CNTR_RAM_CONTROLr_fields,
   8485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8486         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8487         -1,
   8488         -1,
   8489     },
   8490 #endif /* chips */
   8491 
   8492 #if defined(BCM_56860_A0)
   8493     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_X_PIPE_1_TM_BCM56860_A0r */
   8494         soc_block_list[4],
   8495         soc_genreg,
   8496         1,
   8497         0,
   8498         0x760c0900,
   8499         0,
   8500         0,
   8501         1,
   8502         soc_MCFP_MEM_DEBUG_TMr_fields,
   8503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8504         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8505         -1,
   8506         -1,
   8507     },
   8508 #endif /* chips */
   8509 
   8510 #if defined(BCM_56850_A0)
   8511     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_Y_PIPE_0_TMr */
   8512         soc_block_list[4],
   8513         soc_genreg,
   8514         1,
   8515         0,
   8516         0x760c0a00,
   8517         0,
   8518         0,
   8519         1,
   8520         soc_FT_CNTR_RAM_CONTROLr_fields,
   8521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8522         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8523         -1,
   8524         -1,
   8525     },
   8526 #endif /* chips */
   8527 
   8528 #if defined(BCM_56860_A0)
   8529     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_Y_PIPE_0_TM_BCM56860_A0r */
   8530         soc_block_list[4],
   8531         soc_genreg,
   8532         1,
   8533         0,
   8534         0x760c0a00,
   8535         0,
   8536         0,
   8537         1,
   8538         soc_MCFP_MEM_DEBUG_TMr_fields,
   8539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8540         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8541         -1,
   8542         -1,
   8543     },
   8544 #endif /* chips */
   8545 
   8546 #if defined(BCM_56850_A0)
   8547     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_Y_PIPE_1_TMr */
   8548         soc_block_list[4],
   8549         soc_genreg,
   8550         1,
   8551         0,
   8552         0x760c0b00,
   8553         0,
   8554         0,
   8555         1,
   8556         soc_FT_CNTR_RAM_CONTROLr_fields,
   8557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8559         -1,
   8560         -1,
   8561     },
   8562 #endif /* chips */
   8563 
   8564 #if defined(BCM_56860_A0)
   8565     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_Y_PIPE_1_TM_BCM56860_A0r */
   8566         soc_block_list[4],
   8567         soc_genreg,
   8568         1,
   8569         0,
   8570         0x760c0b00,
   8571         0,
   8572         0,
   8573         1,
   8574         soc_MCFP_MEM_DEBUG_TMr_fields,
   8575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8577         -1,
   8578         -1,
   8579     },
   8580 #endif /* chips */
   8581 
   8582 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   8583     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQr */
   8584         soc_block_list[4],
   8585         soc_genreg,
   8586         1,
   8587         0,
   8588         0x560c0900,
   8589         0,
   8590         0,
   8591         1,
   8592         soc_FT_CNTR_RAM_CONTROLr_fields,
   8593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8594         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8595         -1,
   8596         -1,
   8597     },
   8598 #endif /* chips */
   8599 
   8600 #if defined(BCM_56850_A0)
   8601     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_X_PIPE_0_TMr */
   8602         soc_block_list[4],
   8603         soc_genreg,
   8604         1,
   8605         0,
   8606         0x760c0400,
   8607         0,
   8608         0,
   8609         1,
   8610         soc_FT_CNTR_RAM_CONTROLr_fields,
   8611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8613         -1,
   8614         -1,
   8615     },
   8616 #endif /* chips */
   8617 
   8618 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   8619     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_X_PIPE_0_TM_BCM56560_A0r */
   8620         soc_block_list[4],
   8621         soc_genreg,
   8622         1,
   8623         0,
   8624         0x760c0400,
   8625         0,
   8626         0,
   8627         1,
   8628         soc_CCPMEMDEBUG_BCM56560_A0r_fields,
   8629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8630         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8631         -1,
   8632         -1,
   8633     },
   8634 #endif /* chips */
   8635 
   8636 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   8637     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_X_PIPE_0_TM_BCM56670_A0r */
   8638         soc_block_list[4],
   8639         soc_genreg,
   8640         1,
   8641         0,
   8642         0x760c0400,
   8643         0,
   8644         0,
   8645         1,
   8646         soc_E2EFC_MEM_TMr_fields,
   8647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8649         -1,
   8650         -1,
   8651     },
   8652 #endif /* chips */
   8653 
   8654 #if defined(BCM_56860_A0)
   8655     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_X_PIPE_0_TM_BCM56860_A0r */
   8656         soc_block_list[4],
   8657         soc_genreg,
   8658         1,
   8659         0,
   8660         0x760c0400,
   8661         0,
   8662         0,
   8663         1,
   8664         soc_MCFP_MEM_DEBUG_TMr_fields,
   8665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8666         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8667         -1,
   8668         -1,
   8669     },
   8670 #endif /* chips */
   8671 
   8672 #if defined(BCM_56850_A0)
   8673     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_X_PIPE_1_TMr */
   8674         soc_block_list[4],
   8675         soc_genreg,
   8676         1,
   8677         0,
   8678         0x760c0500,
   8679         0,
   8680         0,
   8681         1,
   8682         soc_FT_CNTR_RAM_CONTROLr_fields,
   8683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8684         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8685         -1,
   8686         -1,
   8687     },
   8688 #endif /* chips */
   8689 
   8690 #if defined(BCM_56860_A0)
   8691     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_X_PIPE_1_TM_BCM56860_A0r */
   8692         soc_block_list[4],
   8693         soc_genreg,
   8694         1,
   8695         0,
   8696         0x760c0500,
   8697         0,
   8698         0,
   8699         1,
   8700         soc_MCFP_MEM_DEBUG_TMr_fields,
   8701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8702         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8703         -1,
   8704         -1,
   8705     },
   8706 #endif /* chips */
   8707 
   8708 #if defined(BCM_56850_A0)
   8709     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_Y_PIPE_0_TMr */
   8710         soc_block_list[4],
   8711         soc_genreg,
   8712         1,
   8713         0,
   8714         0x760c0600,
   8715         0,
   8716         0,
   8717         1,
   8718         soc_FT_CNTR_RAM_CONTROLr_fields,
   8719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8720         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8721         -1,
   8722         -1,
   8723     },
   8724 #endif /* chips */
   8725 
   8726 #if defined(BCM_56860_A0)
   8727     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_Y_PIPE_0_TM_BCM56860_A0r */
   8728         soc_block_list[4],
   8729         soc_genreg,
   8730         1,
   8731         0,
   8732         0x760c0600,
   8733         0,
   8734         0,
   8735         1,
   8736         soc_MCFP_MEM_DEBUG_TMr_fields,
   8737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8738         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8739         -1,
   8740         -1,
   8741     },
   8742 #endif /* chips */
   8743 
   8744 #if defined(BCM_56850_A0)
   8745     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_Y_PIPE_1_TMr */
   8746         soc_block_list[4],
   8747         soc_genreg,
   8748         1,
   8749         0,
   8750         0x760c0700,
   8751         0,
   8752         0,
   8753         1,
   8754         soc_FT_CNTR_RAM_CONTROLr_fields,
   8755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8756         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8757         -1,
   8758         -1,
   8759     },
   8760 #endif /* chips */
   8761 
   8762 #if defined(BCM_56860_A0)
   8763     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_Y_PIPE_1_TM_BCM56860_A0r */
   8764         soc_block_list[4],
   8765         soc_genreg,
   8766         1,
   8767         0,
   8768         0x760c0700,
   8769         0,
   8770         0,
   8771         1,
   8772         soc_MCFP_MEM_DEBUG_TMr_fields,
   8773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8774         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8775         -1,
   8776         -1,
   8777     },
   8778 #endif /* chips */
   8779 
   8780 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   8781     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_MARK_TMr */
   8782         soc_block_list[124],
   8783         soc_pipereg,
   8784         1,
   8785         0,
   8786         0x21801300,
   8787         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8788         0,
   8789         1,
   8790         soc_E2EFC_MEM_TMr_fields,
   8791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8792         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8793         -1,
   8794         -1,
   8795         3,
   8796     },
   8797 #endif /* chips */
   8798 
   8799 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   8800     defined(BCM_56870_A0) || defined(BCM_56970_A0)
   8801     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_DROP_THD_MARK_TM_BCM56970_A0r */
   8802         soc_block_list[124],
   8803         soc_pipereg,
   8804         1,
   8805         0,
   8806         0x21801400,
   8807         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8808         0,
   8809         1,
   8810         soc_FP_METER_TMr_fields,
   8811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8812         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8813         -1,
   8814         -1,
   8815         3,
   8816     },
   8817 #endif /* chips */
   8818 
   8819 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   8820     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_TOTAL_COUNTr */
   8821         soc_block_list[4],
   8822         soc_genreg,
   8823         1,
   8824         0,
   8825         0x560c0600,
   8826         0,
   8827         0,
   8828         1,
   8829         soc_UCQDBMEMDEBUGr_fields,
   8830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8831         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8832         -1,
   8833         -1,
   8834     },
   8835 #endif /* chips */
   8836 
   8837 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   8838     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_TOTAL_COUNT_TMr */
   8839         soc_block_list[124],
   8840         soc_pipereg,
   8841         1,
   8842         0,
   8843         0x21801400,
   8844         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8845         0,
   8846         1,
   8847         soc_CCPMEMDEBUG_BCM56960_A0r_fields,
   8848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8849         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8850         -1,
   8851         -1,
   8852         3,
   8853     },
   8854 #endif /* chips */
   8855 
   8856 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   8857     defined(BCM_56870_A0) || defined(BCM_56970_A0)
   8858     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_TOTAL_COUNT_TM_BCM56970_A0r */
   8859         soc_block_list[124],
   8860         soc_pipereg,
   8861         1,
   8862         0,
   8863         0x21801500,
   8864         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8865         0,
   8866         1,
   8867         soc_CCPMEMDEBUG_BCM56960_A0r_fields,
   8868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8869         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8870         -1,
   8871         -1,
   8872         3,
   8873     },
   8874 #endif /* chips */
   8875 
   8876 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   8877     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_TOTAL_COUNT_X_PIPE_TMr */
   8878         soc_block_list[4],
   8879         soc_genreg,
   8880         1,
   8881         0,
   8882         0x760c1000,
   8883         0,
   8884         0,
   8885         1,
   8886         soc_UCQDBMEMDEBUGr_fields,
   8887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8888         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8889         -1,
   8890         -1,
   8891     },
   8892 #endif /* chips */
   8893 
   8894 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   8895     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   8896     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_TOTAL_COUNT_X_PIPE_TM_BCM56560_A0r */
   8897         soc_block_list[4],
   8898         soc_genreg,
   8899         1,
   8900         0,
   8901         0x760c1000,
   8902         0,
   8903         0,
   8904         1,
   8905         soc_CCPMEMDEBUG_BCM56960_A0r_fields,
   8906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8907         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8908         -1,
   8909         -1,
   8910     },
   8911 #endif /* chips */
   8912 
   8913 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   8914     { /* SOC_REG_INT_WREDMEMDEBUG_UC_QUEUE_TOTAL_COUNT_Y_PIPE_TMr */
   8915         soc_block_list[4],
   8916         soc_genreg,
   8917         1,
   8918         0,
   8919         0x760c1100,
   8920         0,
   8921         0,
   8922         1,
   8923         soc_UCQDBMEMDEBUGr_fields,
   8924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8926         -1,
   8927         -1,
   8928     },
   8929 #endif /* chips */
   8930 
   8931 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   8932     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   8933     { /* SOC_REG_INT_WREDPARAM_CELLr */
   8934         soc_block_list[4],
   8935         soc_portreg,
   8936         24,
   8937         0,
   8938         0x17000100,
   8939         SOC_REG_FLAG_ARRAY,
   8940         0,
   8941         3,
   8942         soc_GLOBAL_WREDPARAM_CELLr_fields,
   8943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8944         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   8945         -1,
   8946         1,
   8947     },
   8948 #endif /* chips */
   8949 
   8950 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   8951     { /* SOC_REG_INT_WREDPARAM_CELL_BCM56334_A0r */
   8952         soc_block_list[4],
   8953         soc_portreg,
   8954         24,
   8955         0,
   8956         0x17000100,
   8957         SOC_REG_FLAG_ARRAY,
   8958         0,
   8959         3,
   8960         soc_GLOBAL_WREDPARAM_PACKETr_fields,
   8961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8962         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8963         -1,
   8964         29,
   8965     },
   8966 #endif /* chips */
   8967 
   8968 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8969     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8970     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8971     { /* SOC_REG_INT_WREDPARAM_CELL_BCM56634_A0r */
   8972         soc_block_list[4],
   8973         soc_portreg,
   8974         24,
   8975         0,
   8976         0x17000100,
   8977         SOC_REG_FLAG_ARRAY,
   8978         0,
   8979         3,
   8980         soc_GLOBAL_WREDPARAM_CELLr_fields,
   8981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8982         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   8983         -1,
   8984         13,
   8985     },
   8986 #endif /* chips */
   8987 
   8988 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8989     { /* SOC_REG_INT_WREDPARAM_CELL_BCM56820_A0r */
   8990         soc_block_list[4],
   8991         soc_portreg,
   8992         8,
   8993         0,
   8994         0x12000100,
   8995         SOC_REG_FLAG_ARRAY,
   8996         0,
   8997         3,
   8998         soc_GLOBAL_WREDPARAM_PACKETr_fields,
   8999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9000         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9001         -1,
   9002         10,
   9003     },
   9004 #endif /* chips */
   9005 
   9006 #if defined(BCM_88732_A0)
   9007     { /* SOC_REG_INT_WREDPARAM_END_CELLr */
   9008         soc_block_list[4],
   9009         soc_portreg,
   9010         8,
   9011         0,
   9012         0x12000140,
   9013         SOC_REG_FLAG_ARRAY,
   9014         0,
   9015         1,
   9016         soc_GLOBAL_WREDPARAM_END_CELLr_fields,
   9017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9018         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   9019         -1,
   9020         50,
   9021     },
   9022 #endif /* chips */
   9023 
   9024 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9025     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9026     { /* SOC_REG_INT_WREDPARAM_NONTCP_CELLr */
   9027         soc_block_list[4],
   9028         soc_portreg,
   9029         24,
   9030         0,
   9031         0x170001c0,
   9032         SOC_REG_FLAG_ARRAY,
   9033         0,
   9034         3,
   9035         soc_GLOBAL_WREDPARAM_NONTCP_CELLr_fields,
   9036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9037         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   9038         -1,
   9039         1,
   9040     },
   9041 #endif /* chips */
   9042 
   9043 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   9044     { /* SOC_REG_INT_WREDPARAM_NONTCP_CELL_BCM56334_A0r */
   9045         soc_block_list[4],
   9046         soc_portreg,
   9047         24,
   9048         0,
   9049         0x170001c0,
   9050         SOC_REG_FLAG_ARRAY,
   9051         0,
   9052         3,
   9053         soc_GLOBAL_WREDPARAM_NONTCP_PACKETr_fields,
   9054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9055         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9056         -1,
   9057         29,
   9058     },
   9059 #endif /* chips */
   9060 
   9061 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9062     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9063     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9064     { /* SOC_REG_INT_WREDPARAM_NONTCP_CELL_BCM56634_A0r */
   9065         soc_block_list[4],
   9066         soc_portreg,
   9067         24,
   9068         0,
   9069         0x170001c0,
   9070         SOC_REG_FLAG_ARRAY,
   9071         0,
   9072         3,
   9073         soc_GLOBAL_WREDPARAM_NONTCP_CELLr_fields,
   9074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9075         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   9076         -1,
   9077         13,
   9078     },
   9079 #endif /* chips */
   9080 
   9081 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   9082     { /* SOC_REG_INT_WREDPARAM_NONTCP_CELL_BCM56820_A0r */
   9083         soc_block_list[4],
   9084         soc_portreg,
   9085         8,
   9086         0,
   9087         0x120001c0,
   9088         SOC_REG_FLAG_ARRAY,
   9089         0,
   9090         3,
   9091         soc_GLOBAL_WREDPARAM_NONTCP_PACKETr_fields,
   9092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9093         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9094         -1,
   9095         10,
   9096     },
   9097 #endif /* chips */
   9098 
   9099 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9100     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9101     { /* SOC_REG_INT_WREDPARAM_NONTCP_PACKETr */
   9102         soc_block_list[4],
   9103         soc_portreg,
   9104         24,
   9105         0,
   9106         0x17000340,
   9107         SOC_REG_FLAG_ARRAY,
   9108         0,
   9109         3,
   9110         soc_GLOBAL_WREDPARAM_NONTCP_PACKETr_fields,
   9111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9112         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9113         -1,
   9114         1,
   9115     },
   9116 #endif /* chips */
   9117 
   9118 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   9119     { /* SOC_REG_INT_WREDPARAM_NONTCP_PACKET_BCM56334_A0r */
   9120         soc_block_list[4],
   9121         soc_portreg,
   9122         24,
   9123         0,
   9124         0x17000340,
   9125         SOC_REG_FLAG_ARRAY,
   9126         0,
   9127         3,
   9128         soc_GLOBAL_WREDPARAM_NONTCP_PACKET_BCM56334_A0r_fields,
   9129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9130         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
   9131         -1,
   9132         29,
   9133     },
   9134 #endif /* chips */
   9135 
   9136 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9137     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9138     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9139     { /* SOC_REG_INT_WREDPARAM_NONTCP_PACKET_BCM56634_A0r */
   9140         soc_block_list[4],
   9141         soc_portreg,
   9142         24,
   9143         0,
   9144         0x17000340,
   9145         SOC_REG_FLAG_ARRAY,
   9146         0,
   9147         3,
   9148         soc_GLOBAL_WREDPARAM_NONTCP_PACKETr_fields,
   9149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9150         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9151         -1,
   9152         13,
   9153     },
   9154 #endif /* chips */
   9155 
   9156 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9157     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9158     { /* SOC_REG_INT_WREDPARAM_PACKETr */
   9159         soc_block_list[4],
   9160         soc_portreg,
   9161         24,
   9162         0,
   9163         0x17000280,
   9164         SOC_REG_FLAG_ARRAY,
   9165         0,
   9166         3,
   9167         soc_GLOBAL_WREDPARAM_PACKETr_fields,
   9168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9169         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9170         -1,
   9171         1,
   9172     },
   9173 #endif /* chips */
   9174 
   9175 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   9176     { /* SOC_REG_INT_WREDPARAM_PACKET_BCM56334_A0r */
   9177         soc_block_list[4],
   9178         soc_portreg,
   9179         24,
   9180         0,
   9181         0x17000280,
   9182         SOC_REG_FLAG_ARRAY,
   9183         0,
   9184         3,
   9185         soc_GLOBAL_WREDPARAM_PACKET_BCM56334_A0r_fields,
   9186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9187         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
   9188         -1,
   9189         29,
   9190     },
   9191 #endif /* chips */
   9192 
   9193 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9194     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9195     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9196     { /* SOC_REG_INT_WREDPARAM_PACKET_BCM56634_A0r */
   9197         soc_block_list[4],
   9198         soc_portreg,
   9199         24,
   9200         0,
   9201         0x17000280,
   9202         SOC_REG_FLAG_ARRAY,
   9203         0,
   9204         3,
   9205         soc_GLOBAL_WREDPARAM_PACKETr_fields,
   9206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9207         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9208         -1,
   9209         13,
   9210     },
   9211 #endif /* chips */
   9212 
   9213 #if defined(BCM_88732_A0)
   9214     { /* SOC_REG_INT_WREDPARAM_PRI0_END_CELLr */
   9215         soc_block_list[4],
   9216         soc_portreg,
   9217         8,
   9218         0,
   9219         0x120002c0,
   9220         SOC_REG_FLAG_ARRAY,
   9221         0,
   9222         1,
   9223         soc_GLOBAL_WREDPARAM_PRI0_END_CELLr_fields,
   9224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9225         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   9226         -1,
   9227         50,
   9228     },
   9229 #endif /* chips */
   9230 
   9231 #if defined(BCM_88732_A0)
   9232     { /* SOC_REG_INT_WREDPARAM_PRI0_START_CELLr */
   9233         soc_block_list[4],
   9234         soc_portreg,
   9235         8,
   9236         0,
   9237         0x12000280,
   9238         SOC_REG_FLAG_ARRAY,
   9239         0,
   9240         1,
   9241         soc_GLOBAL_WREDPARAM_PRI0_START_CELLr_fields,
   9242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9243         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   9244         -1,
   9245         50,
   9246     },
   9247 #endif /* chips */
   9248 
   9249 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9250     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9251     { /* SOC_REG_INT_WREDPARAM_RED_CELLr */
   9252         soc_block_list[4],
   9253         soc_portreg,
   9254         24,
   9255         0,
   9256         0x17000180,
   9257         SOC_REG_FLAG_ARRAY,
   9258         0,
   9259         3,
   9260         soc_GLOBAL_WREDPARAM_RED_CELLr_fields,
   9261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9262         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   9263         -1,
   9264         1,
   9265     },
   9266 #endif /* chips */
   9267 
   9268 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   9269     { /* SOC_REG_INT_WREDPARAM_RED_CELL_BCM56334_A0r */
   9270         soc_block_list[4],
   9271         soc_portreg,
   9272         24,
   9273         0,
   9274         0x17000180,
   9275         SOC_REG_FLAG_ARRAY,
   9276         0,
   9277         3,
   9278         soc_GLOBAL_WREDPARAM_RED_PACKETr_fields,
   9279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9280         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9281         -1,
   9282         29,
   9283     },
   9284 #endif /* chips */
   9285 
   9286 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9287     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9288     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9289     { /* SOC_REG_INT_WREDPARAM_RED_CELL_BCM56634_A0r */
   9290         soc_block_list[4],
   9291         soc_portreg,
   9292         24,
   9293         0,
   9294         0x17000180,
   9295         SOC_REG_FLAG_ARRAY,
   9296         0,
   9297         3,
   9298         soc_GLOBAL_WREDPARAM_RED_CELLr_fields,
   9299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9300         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   9301         -1,
   9302         13,
   9303     },
   9304 #endif /* chips */
   9305 
   9306 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   9307     { /* SOC_REG_INT_WREDPARAM_RED_CELL_BCM56820_A0r */
   9308         soc_block_list[4],
   9309         soc_portreg,
   9310         8,
   9311         0,
   9312         0x12000180,
   9313         SOC_REG_FLAG_ARRAY,
   9314         0,
   9315         3,
   9316         soc_GLOBAL_WREDPARAM_RED_PACKETr_fields,
   9317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9318         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9319         -1,
   9320         10,
   9321     },
   9322 #endif /* chips */
   9323 
   9324 #if defined(BCM_88732_A0)
   9325     { /* SOC_REG_INT_WREDPARAM_RED_END_CELLr */
   9326         soc_block_list[4],
   9327         soc_portreg,
   9328         8,
   9329         0,
   9330         0x12000240,
   9331         SOC_REG_FLAG_ARRAY,
   9332         0,
   9333         1,
   9334         soc_GLOBAL_WREDPARAM_RED_END_CELLr_fields,
   9335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9336         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   9337         -1,
   9338         50,
   9339     },
   9340 #endif /* chips */
   9341 
   9342 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9343     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9344     { /* SOC_REG_INT_WREDPARAM_RED_PACKETr */
   9345         soc_block_list[4],
   9346         soc_portreg,
   9347         24,
   9348         0,
   9349         0x17000300,
   9350         SOC_REG_FLAG_ARRAY,
   9351         0,
   9352         3,
   9353         soc_GLOBAL_WREDPARAM_RED_PACKETr_fields,
   9354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9355         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9356         -1,
   9357         1,
   9358     },
   9359 #endif /* chips */
   9360 
   9361 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   9362     { /* SOC_REG_INT_WREDPARAM_RED_PACKET_BCM56334_A0r */
   9363         soc_block_list[4],
   9364         soc_portreg,
   9365         24,
   9366         0,
   9367         0x17000300,
   9368         SOC_REG_FLAG_ARRAY,
   9369         0,
   9370         3,
   9371         soc_GLOBAL_WREDPARAM_RED_PACKET_BCM56334_A0r_fields,
   9372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9373         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
   9374         -1,
   9375         29,
   9376     },
   9377 #endif /* chips */
   9378 
   9379 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9380     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9381     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9382     { /* SOC_REG_INT_WREDPARAM_RED_PACKET_BCM56634_A0r */
   9383         soc_block_list[4],
   9384         soc_portreg,
   9385         24,
   9386         0,
   9387         0x17000300,
   9388         SOC_REG_FLAG_ARRAY,
   9389         0,
   9390         3,
   9391         soc_GLOBAL_WREDPARAM_RED_PACKETr_fields,
   9392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9393         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9394         -1,
   9395         13,
   9396     },
   9397 #endif /* chips */
   9398 
   9399 #if defined(BCM_88732_A0)
   9400     { /* SOC_REG_INT_WREDPARAM_RED_START_CELLr */
   9401         soc_block_list[4],
   9402         soc_portreg,
   9403         8,
   9404         0,
   9405         0x12000200,
   9406         SOC_REG_FLAG_ARRAY,
   9407         0,
   9408         1,
   9409         soc_GLOBAL_WREDPARAM_RED_START_CELLr_fields,
   9410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9411         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   9412         -1,
   9413         50,
   9414     },
   9415 #endif /* chips */
   9416 
   9417 #if defined(BCM_88732_A0)
   9418     { /* SOC_REG_INT_WREDPARAM_START_CELLr */
   9419         soc_block_list[4],
   9420         soc_portreg,
   9421         8,
   9422         0,
   9423         0x12000100,
   9424         SOC_REG_FLAG_ARRAY,
   9425         0,
   9426         1,
   9427         soc_GLOBAL_WREDPARAM_START_CELLr_fields,
   9428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9429         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   9430         -1,
   9431         50,
   9432     },
   9433 #endif /* chips */
   9434 
   9435 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9436     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9437     { /* SOC_REG_INT_WREDPARAM_YELLOW_CELLr */
   9438         soc_block_list[4],
   9439         soc_portreg,
   9440         24,
   9441         0,
   9442         0x17000140,
   9443         SOC_REG_FLAG_ARRAY,
   9444         0,
   9445         3,
   9446         soc_GLOBAL_WREDPARAM_YELLOW_CELLr_fields,
   9447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9448         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   9449         -1,
   9450         1,
   9451     },
   9452 #endif /* chips */
   9453 
   9454 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   9455     { /* SOC_REG_INT_WREDPARAM_YELLOW_CELL_BCM56334_A0r */
   9456         soc_block_list[4],
   9457         soc_portreg,
   9458         24,
   9459         0,
   9460         0x17000140,
   9461         SOC_REG_FLAG_ARRAY,
   9462         0,
   9463         3,
   9464         soc_GLOBAL_WREDPARAM_YELLOW_PACKETr_fields,
   9465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9466         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9467         -1,
   9468         29,
   9469     },
   9470 #endif /* chips */
   9471 
   9472 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9473     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9474     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9475     { /* SOC_REG_INT_WREDPARAM_YELLOW_CELL_BCM56634_A0r */
   9476         soc_block_list[4],
   9477         soc_portreg,
   9478         24,
   9479         0,
   9480         0x17000140,
   9481         SOC_REG_FLAG_ARRAY,
   9482         0,
   9483         3,
   9484         soc_GLOBAL_WREDPARAM_YELLOW_CELLr_fields,
   9485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9486         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
   9487         -1,
   9488         13,
   9489     },
   9490 #endif /* chips */
   9491 
   9492 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   9493     { /* SOC_REG_INT_WREDPARAM_YELLOW_CELL_BCM56820_A0r */
   9494         soc_block_list[4],
   9495         soc_portreg,
   9496         8,
   9497         0,
   9498         0x12000140,
   9499         SOC_REG_FLAG_ARRAY,
   9500         0,
   9501         3,
   9502         soc_GLOBAL_WREDPARAM_YELLOW_PACKETr_fields,
   9503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9504         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9505         -1,
   9506         10,
   9507     },
   9508 #endif /* chips */
   9509 
   9510 #if defined(BCM_88732_A0)
   9511     { /* SOC_REG_INT_WREDPARAM_YELLOW_END_CELLr */
   9512         soc_block_list[4],
   9513         soc_portreg,
   9514         8,
   9515         0,
   9516         0x120001c0,
   9517         SOC_REG_FLAG_ARRAY,
   9518         0,
   9519         1,
   9520         soc_GLOBAL_WREDPARAM_YELLOW_END_CELLr_fields,
   9521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9522         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   9523         -1,
   9524         50,
   9525     },
   9526 #endif /* chips */
   9527 
   9528 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   9529     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   9530     { /* SOC_REG_INT_WREDPARAM_YELLOW_PACKETr */
   9531         soc_block_list[4],
   9532         soc_portreg,
   9533         24,
   9534         0,
   9535         0x170002c0,
   9536         SOC_REG_FLAG_ARRAY,
   9537         0,
   9538         3,
   9539         soc_GLOBAL_WREDPARAM_YELLOW_PACKETr_fields,
   9540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9541         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9542         -1,
   9543         1,
   9544     },
   9545 #endif /* chips */
   9546 
   9547 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   9548     { /* SOC_REG_INT_WREDPARAM_YELLOW_PACKET_BCM56334_A0r */
   9549         soc_block_list[4],
   9550         soc_portreg,
   9551         24,
   9552         0,
   9553         0x170002c0,
   9554         SOC_REG_FLAG_ARRAY,
   9555         0,
   9556         3,
   9557         soc_GLOBAL_WREDPARAM_YELLOW_PACKET_BCM56334_A0r_fields,
   9558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9559         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
   9560         -1,
   9561         29,
   9562     },
   9563 #endif /* chips */
   9564 
   9565 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9566     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9567     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9568     { /* SOC_REG_INT_WREDPARAM_YELLOW_PACKET_BCM56634_A0r */
   9569         soc_block_list[4],
   9570         soc_portreg,
   9571         24,
   9572         0,
   9573         0x170002c0,
   9574         SOC_REG_FLAG_ARRAY,
   9575         0,
   9576         3,
   9577         soc_GLOBAL_WREDPARAM_YELLOW_PACKETr_fields,
   9578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9579         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   9580         -1,
   9581         13,
   9582     },
   9583 #endif /* chips */
   9584 
   9585 #if defined(BCM_88732_A0)
   9586     { /* SOC_REG_INT_WREDPARAM_YELLOW_START_CELLr */
   9587         soc_block_list[4],
   9588         soc_portreg,
   9589         8,
   9590         0,
   9591         0x12000180,
   9592         SOC_REG_FLAG_ARRAY,
   9593         0,
   9594         1,
   9595         soc_GLOBAL_WREDPARAM_YELLOW_START_CELLr_fields,
   9596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9597         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   9598         -1,
   9599         50,
   9600     },
   9601 #endif /* chips */
   9602 
   9603 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   9604     { /* SOC_REG_INT_WRED_AVG_QSIZEr */
   9605         soc_block_list[4],
   9606         soc_portreg,
   9607         8,
   9608         0,
   9609         0x17000028,
   9610         SOC_REG_FLAG_ARRAY,
   9611         0,
   9612         3,
   9613         soc_GLOBAL_SP_WRED_AVG_QSIZEr_fields,
   9614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9615         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9616         -1,
   9617         41,
   9618     },
   9619 #endif /* chips */
   9620 
   9621 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
   9622     { /* SOC_REG_INT_WRED_AVG_QSIZE_PARITY_ERR_PTRr */
   9623         soc_block_list[4],
   9624         soc_genreg,
   9625         1,
   9626         0,
   9627         0x2169100,
   9628         SOC_REG_FLAG_RO,
   9629         0,
   9630         1,
   9631         soc_WRED_AVG_QSIZE_PARITY_ERR_PTRr_fields,
   9632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9633         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9634         -1,
   9635         -1,
   9636     },
   9637 #endif /* chips */
   9638 
   9639 #if defined(BCM_53540_A0)
   9640     { /* SOC_REG_INT_WRED_AVG_QSIZE_PARITY_ERR_PTR_BCM53540_A0r */
   9641         soc_block_list[4],
   9642         soc_genreg,
   9643         1,
   9644         0,
   9645         0x207f800,
   9646         SOC_REG_FLAG_RO,
   9647         0,
   9648         1,
   9649         soc_WRED_AVG_QSIZE_PARITY_ERR_PTRr_fields,
   9650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9651         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9652         -1,
   9653         -1,
   9654     },
   9655 #endif /* chips */
   9656 
   9657 #if defined(BCM_53570_A0)
   9658     { /* SOC_REG_INT_WRED_AVG_QSIZE_PARITY_ERR_PTR_BCM53570_A0r */
   9659         soc_block_list[4],
   9660         soc_genreg,
   9661         1,
   9662         0,
   9663         0x20eae00,
   9664         SOC_REG_FLAG_RO,
   9665         0,
   9666         1,
   9667         soc_WRED_AVG_QSIZE_PARITY_ERR_PTR_BCM53570_A0r_fields,
   9668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9669         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   9670         -1,
   9671         -1,
   9672     },
   9673 #endif /* chips */
   9674 
   9675 #if defined(BCM_53570_B0)
   9676     { /* SOC_REG_INT_WRED_AVG_QSIZE_PARITY_ERR_PTR_BCM53570_B0r */
   9677         soc_block_list[4],
   9678         soc_genreg,
   9679         1,
   9680         0,
   9681         0x20eb100,
   9682         SOC_REG_FLAG_RO,
   9683         0,
   9684         1,
   9685         soc_WRED_AVG_QSIZE_PARITY_ERR_PTR_BCM53570_A0r_fields,
   9686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9687         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   9688         -1,
   9689         -1,
   9690     },
   9691 #endif /* chips */
   9692 
   9693 #if defined(BCM_53570_A0)
   9694     { /* SOC_REG_INT_WRED_AVG_QSIZE_QG_PARITY_ERR_PTRr */
   9695         soc_block_list[4],
   9696         soc_genreg,
   9697         1,
   9698         0,
   9699         0x20e9e00,
   9700         SOC_REG_FLAG_RO,
   9701         0,
   9702         1,
   9703         soc_WRED_AVG_QSIZE_QG_PARITY_ERR_PTRr_fields,
   9704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9705         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   9706         -1,
   9707         -1,
   9708     },
   9709 #endif /* chips */
   9710 
   9711 #if defined(BCM_53570_B0)
   9712     { /* SOC_REG_INT_WRED_AVG_QSIZE_QG_PARITY_ERR_PTR_BCM53570_B0r */
   9713         soc_block_list[4],
   9714         soc_genreg,
   9715         1,
   9716         0,
   9717         0x20ea100,
   9718         SOC_REG_FLAG_RO,
   9719         0,
   9720         1,
   9721         soc_WRED_AVG_QSIZE_QG_PARITY_ERR_PTRr_fields,
   9722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9723         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   9724         -1,
   9725         -1,
   9726     },
   9727 #endif /* chips */
   9728 
   9729 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   9730     { /* SOC_REG_INT_WRED_CONFIGr */
   9731         soc_block_list[4],
   9732         soc_portreg,
   9733         8,
   9734         0,
   9735         0x17000020,
   9736         SOC_REG_FLAG_ARRAY,
   9737         0,
   9738         8,
   9739         soc_DMVOQ_WRED_CONFIGr_fields,
   9740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9741         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   9742         -1,
   9743         41,
   9744     },
   9745 #endif /* chips */
   9746 
   9747 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
   9748     { /* SOC_REG_INT_WRED_CONFIG_PARITY_ERR_PTRr */
   9749         soc_block_list[4],
   9750         soc_genreg,
   9751         1,
   9752         0,
   9753         0x2169200,
   9754         SOC_REG_FLAG_RO,
   9755         0,
   9756         1,
   9757         soc_WRED_AVG_QSIZE_PARITY_ERR_PTRr_fields,
   9758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9759         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9760         -1,
   9761         -1,
   9762     },
   9763 #endif /* chips */
   9764 
   9765 #if defined(BCM_53540_A0)
   9766     { /* SOC_REG_INT_WRED_CONFIG_PARITY_ERR_PTR_BCM53540_A0r */
   9767         soc_block_list[4],
   9768         soc_genreg,
   9769         1,
   9770         0,
   9771         0x2080000,
   9772         SOC_REG_FLAG_RO,
   9773         0,
   9774         1,
   9775         soc_WRED_AVG_QSIZE_PARITY_ERR_PTRr_fields,
   9776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9777         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   9778         -1,
   9779         -1,
   9780     },
   9781 #endif /* chips */
   9782 
   9783 #if defined(BCM_53570_A0)
   9784     { /* SOC_REG_INT_WRED_CONFIG_PARITY_ERR_PTR_BCM53570_A0r */
   9785         soc_block_list[4],
   9786         soc_genreg,
   9787         1,
   9788         0,
   9789         0x20eb600,
   9790         SOC_REG_FLAG_RO,
   9791         0,
   9792         1,
   9793         soc_WRED_AVG_QSIZE_PARITY_ERR_PTR_BCM53570_A0r_fields,
   9794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9795         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   9796         -1,
   9797         -1,
   9798     },
   9799 #endif /* chips */
   9800 
   9801 #if defined(BCM_53570_B0)
   9802     { /* SOC_REG_INT_WRED_CONFIG_PARITY_ERR_PTR_BCM53570_B0r */
   9803         soc_block_list[4],
   9804         soc_genreg,
   9805         1,
   9806         0,
   9807         0x20eb900,
   9808         SOC_REG_FLAG_RO,
   9809         0,
   9810         1,
   9811         soc_WRED_AVG_QSIZE_PARITY_ERR_PTR_BCM53570_A0r_fields,
   9812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9813         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   9814         -1,
   9815         -1,
   9816     },
   9817 #endif /* chips */
   9818 
   9819 #if defined(BCM_53570_A0)
   9820     { /* SOC_REG_INT_WRED_CONFIG_QG_PARITY_ERR_PTRr */
   9821         soc_block_list[4],
   9822         soc_genreg,
   9823         1,
   9824         0,
   9825         0x20ea600,
   9826         SOC_REG_FLAG_RO,
   9827         0,
   9828         1,
   9829         soc_WRED_AVG_QSIZE_QG_PARITY_ERR_PTRr_fields,
   9830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9831         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   9832         -1,
   9833         -1,
   9834     },
   9835 #endif /* chips */
   9836 
   9837 #if defined(BCM_53570_B0)
   9838     { /* SOC_REG_INT_WRED_CONFIG_QG_PARITY_ERR_PTR_BCM53570_B0r */
   9839         soc_block_list[4],
   9840         soc_genreg,
   9841         1,
   9842         0,
   9843         0x20ea900,
   9844         SOC_REG_FLAG_RO,
   9845         0,
   9846         1,
   9847         soc_WRED_AVG_QSIZE_QG_PARITY_ERR_PTRr_fields,
   9848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9849         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   9850         -1,
   9851         -1,
   9852     },
   9853 #endif /* chips */
   9854 
   9855 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9856     { /* SOC_REG_INT_WRED_CONG_NOTIFICATION_RESOLUTION_TABLEr */
   9857         soc_block_list[124],
   9858         soc_genreg,
   9859         4,
   9860         0,
   9861         0x22000700,
   9862         SOC_REG_FLAG_ARRAY |
   9863                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9864         0,
   9865         1,
   9866         soc_WRED_CONG_NOTIFICATION_RESOLUTION_TABLEr_fields,
   9867         SOC_RESET_VAL_DEC(0x00000aaa, 0x00000000)
   9868         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   9869         -1,
   9870         -1,
   9871         3,
   9872     },
   9873 #endif /* chips */
   9874 
   9875 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   9876     defined(BCM_56870_A0) || defined(BCM_56970_A0)
   9877     { /* SOC_REG_INT_WRED_CONG_NOTIFICATION_RESOLUTION_TABLE_BCM56970_A0r */
   9878         soc_block_list[124],
   9879         soc_genreg,
   9880         4,
   9881         0,
   9882         0x22000800,
   9883         SOC_REG_FLAG_ARRAY |
   9884                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9885         0,
   9886         1,
   9887         soc_WRED_CONG_NOTIFICATION_RESOLUTION_TABLEr_fields,
   9888         SOC_RESET_VAL_DEC(0x00000aaa, 0x00000000)
   9889         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   9890         -1,
   9891         -1,
   9892         3,
   9893     },
   9894 #endif /* chips */
   9895 
   9896 #if defined(BCM_88732_A0)
   9897     { /* SOC_REG_INT_WRED_DEBUG_ENQ_DROP_GLOBALr */
   9898         soc_block_list[4],
   9899         soc_genreg,
   9900         1,
   9901         0,
   9902         0x12080400,
   9903         0,
   9904         0,
   9905         1,
   9906         soc_WRED_DEBUG_ENQ_DROP_GLOBALr_fields,
   9907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9908         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9909         -1,
   9910         -1,
   9911     },
   9912 #endif /* chips */
   9913 
   9914 #if defined(BCM_88732_A0)
   9915     { /* SOC_REG_INT_WRED_DEBUG_ENQ_DROP_PORTr */
   9916         soc_block_list[4],
   9917         soc_portreg,
   9918         1,
   9919         0,
   9920         0x12000401,
   9921         0,
   9922         0,
   9923         2,
   9924         soc_WRED_DEBUG_ENQ_DROP_PORTr_fields,
   9925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9926         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9927         -1,
   9928         50,
   9929     },
   9930 #endif /* chips */
   9931 
   9932 #if defined(BCM_53400_A0)
   9933     { /* SOC_REG_INT_WRED_DROP_COUNTERr */
   9934         soc_block_list[4],
   9935         soc_portreg,
   9936         1,
   9937         0,
   9938         0x163000,
   9939         0,
   9940         0,
   9941         1,
   9942         soc_IHOST_PTIM_TIMER_COUNTERr_fields,
   9943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9944         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9945         -1,
   9946         80,
   9947     },
   9948 #endif /* chips */
   9949 
   9950 #if defined(BCM_53540_A0)
   9951     { /* SOC_REG_INT_WRED_DROP_COUNTER_BCM53540_A0r */
   9952         soc_block_list[4],
   9953         soc_portreg,
   9954         1,
   9955         0,
   9956         0x7c800,
   9957         0,
   9958         0,
   9959         1,
   9960         soc_IHOST_PTIM_TIMER_COUNTERr_fields,
   9961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9962         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9963         -1,
   9964         92,
   9965     },
   9966 #endif /* chips */
   9967 
   9968 #if defined(BCM_53570_A0)
   9969     { /* SOC_REG_INT_WRED_DROP_COUNTER_BCM53570_A0r */
   9970         soc_block_list[4],
   9971         soc_portreg,
   9972         1,
   9973         0,
   9974         0xe5e00,
   9975         0,
   9976         0,
   9977         1,
   9978         soc_IHOST_PTIM_TIMER_COUNTERr_fields,
   9979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9980         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9981         -1,
   9982         103,
   9983     },
   9984 #endif /* chips */
   9985 
   9986 #if defined(BCM_53570_B0)
   9987     { /* SOC_REG_INT_WRED_DROP_COUNTER_BCM53570_B0r */
   9988         soc_block_list[4],
   9989         soc_portreg,
   9990         1,
   9991         0,
   9992         0xe6100,
   9993         0,
   9994         0,
   9995         1,
   9996         soc_IHOST_PTIM_TIMER_COUNTERr_fields,
   9997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9998         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9999         -1,
  10000         103,
  10001     },
  10002 #endif /* chips */
  10003 
  10004 #if defined(BCM_56160_A0)
  10005     { /* SOC_REG_INT_WRED_DROP_COUNTER_BCM56160_A0r */
  10006         soc_block_list[4],
  10007         soc_portreg,
  10008         1,
  10009         0,
  10010         0x163000,
  10011         0,
  10012         0,
  10013         1,
  10014         soc_IHOST_PTIM_TIMER_COUNTERr_fields,
  10015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10016         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10017         -1,
  10018         92,
  10019     },
  10020 #endif /* chips */
  10021 
  10022 #if defined(BCM_53400_A0)
  10023     { /* SOC_REG_INT_WRED_DROP_CTR_CONFIGr */
  10024         soc_block_list[4],
  10025         soc_portreg,
  10026         1,
  10027         0,
  10028         0x161000,
  10029         0,
  10030         0,
  10031         2,
  10032         soc_WRED_DROP_CTR_CONFIGr_fields,
  10033         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  10034         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  10035         -1,
  10036         80,
  10037     },
  10038 #endif /* chips */
  10039 
  10040 #if defined(BCM_53540_A0)
  10041     { /* SOC_REG_INT_WRED_DROP_CTR_CONFIG_BCM53540_A0r */
  10042         soc_block_list[4],
  10043         soc_portreg,
  10044         1,
  10045         0,
  10046         0x7c000,
  10047         0,
  10048         0,
  10049         2,
  10050         soc_WRED_DROP_CTR_CONFIGr_fields,
  10051         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  10052         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  10053         -1,
  10054         92,
  10055     },
  10056 #endif /* chips */
  10057 
  10058 #if defined(BCM_53570_A0)
  10059     { /* SOC_REG_INT_WRED_DROP_CTR_CONFIG_BCM53570_A0r */
  10060         soc_block_list[4],
  10061         soc_portreg,
  10062         1,
  10063         0,
  10064         0xe3e00,
  10065         0,
  10066         0,
  10067         2,
  10068         soc_WRED_DROP_CTR_CONFIGr_fields,
  10069         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  10070         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  10071         -1,
  10072         104,
  10073     },
  10074 #endif /* chips */
  10075 
  10076 #if defined(BCM_53570_B0)
  10077     { /* SOC_REG_INT_WRED_DROP_CTR_CONFIG_BCM53570_B0r */
  10078         soc_block_list[4],
  10079         soc_portreg,
  10080         1,
  10081         0,
  10082         0xe4100,
  10083         0,
  10084         0,
  10085         2,
  10086         soc_WRED_DROP_CTR_CONFIGr_fields,
  10087         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  10088         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  10089         -1,
  10090         104,
  10091     },
  10092 #endif /* chips */
  10093 
  10094 #if defined(BCM_56160_A0)
  10095     { /* SOC_REG_INT_WRED_DROP_CTR_CONFIG_BCM56160_A0r */
  10096         soc_block_list[4],
  10097         soc_portreg,
  10098         1,
  10099         0,
  10100         0x161000,
  10101         0,
  10102         0,
  10103         2,
  10104         soc_WRED_DROP_CTR_CONFIGr_fields,
  10105         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  10106         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  10107         -1,
  10108         92,
  10109     },
  10110 #endif /* chips */
  10111 
  10112 #if defined(BCM_53570_A0)
  10113     { /* SOC_REG_INT_WRED_DROP_CTR_CONFIG_COLOR_MASK_QLAYERr */
  10114         soc_block_list[4],
  10115         soc_portreg,
  10116         1,
  10117         0,
  10118         0xe4600,
  10119         0,
  10120         0,
  10121         1,
  10122         soc_WRED_DROP_CTR_CONFIG_COLOR_MASK_QLAYERr_fields,
  10123         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  10124         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  10125         -1,
  10126         99,
  10127     },
  10128 #endif /* chips */
  10129 
  10130 #if defined(BCM_53570_B0)
  10131     { /* SOC_REG_INT_WRED_DROP_CTR_CONFIG_COLOR_MASK_QLAYER_BCM53570_B0r */
  10132         soc_block_list[4],
  10133         soc_portreg,
  10134         1,
  10135         0,
  10136         0xe4900,
  10137         0,
  10138         0,
  10139         1,
  10140         soc_WRED_DROP_CTR_CONFIG_COLOR_MASK_QLAYERr_fields,
  10141         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  10142         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  10143         -1,
  10144         99,
  10145     },
  10146 #endif /* chips */
  10147 
  10148 #if defined(BCM_53570_A0)
  10149     { /* SOC_REG_INT_WRED_DROP_CTR_CONFIG_QLAYER_0r */
  10150         soc_block_list[4],
  10151         soc_portreg,
  10152         1,
  10153         0,
  10154         0xe4e00,
  10155         0,
  10156         0,
  10157         1,
  10158         soc_WRED_DROP_CTR_CONFIG_QLAYER_0r_fields,
  10159         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  10160         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10161         -1,
  10162         99,
  10163     },
  10164 #endif /* chips */
  10165 
  10166 #if defined(BCM_53570_A0)
  10167     { /* SOC_REG_INT_WRED_DROP_CTR_CONFIG_QLAYER_1r */
  10168         soc_block_list[4],
  10169         soc_portreg,
  10170         1,
  10171         0,
  10172         0xe5600,
  10173         0,
  10174         0,
  10175         1,
  10176         soc_WRED_DROP_CTR_CONFIG_QLAYER_0r_fields,
  10177         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  10178         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10179         -1,
  10180         99,
  10181     },
  10182 #endif /* chips */
  10183 
  10184 #if defined(BCM_53570_B0)
  10185     { /* SOC_REG_INT_WRED_DROP_CTR_CONFIG_QLAYER_0_BCM53570_B0r */
  10186         soc_block_list[4],
  10187         soc_portreg,
  10188         1,
  10189         0,
  10190         0xe5100,
  10191         0,
  10192         0,
  10193         1,
  10194         soc_WRED_DROP_CTR_CONFIG_QLAYER_0r_fields,
  10195         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  10196         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10197         -1,
  10198         99,
  10199     },
  10200 #endif /* chips */
  10201 
  10202 #if defined(BCM_53570_B0)
  10203     { /* SOC_REG_INT_WRED_DROP_CTR_CONFIG_QLAYER_1_BCM53570_B0r */
  10204         soc_block_list[4],
  10205         soc_portreg,
  10206         1,
  10207         0,
  10208         0xe5900,
  10209         0,
  10210         0,
  10211         1,
  10212         soc_WRED_DROP_CTR_CONFIG_QLAYER_0r_fields,
  10213         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  10214         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10215         -1,
  10216         99,
  10217     },
  10218 #endif /* chips */
  10219 
  10220 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  10221     { /* SOC_REG_INT_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr */
  10222         soc_block_list[4],
  10223         soc_genreg,
  10224         1,
  10225         0,
  10226         0x2169300,
  10227         SOC_REG_FLAG_RO,
  10228         0,
  10229         1,
  10230         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10232         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10233         -1,
  10234         -1,
  10235     },
  10236 #endif /* chips */
  10237 
  10238 #if defined(BCM_53540_A0)
  10239     { /* SOC_REG_INT_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTR_BCM53540_A0r */
  10240         soc_block_list[4],
  10241         soc_genreg,
  10242         1,
  10243         0,
  10244         0x2080800,
  10245         SOC_REG_FLAG_RO,
  10246         0,
  10247         1,
  10248         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10250         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10251         -1,
  10252         -1,
  10253     },
  10254 #endif /* chips */
  10255 
  10256 #if defined(BCM_53570_A0)
  10257     { /* SOC_REG_INT_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTR_BCM53570_A0r */
  10258         soc_block_list[4],
  10259         soc_genreg,
  10260         1,
  10261         0,
  10262         0x20ebe00,
  10263         SOC_REG_FLAG_RO,
  10264         0,
  10265         1,
  10266         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10268         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10269         -1,
  10270         -1,
  10271     },
  10272 #endif /* chips */
  10273 
  10274 #if defined(BCM_53570_B0)
  10275     { /* SOC_REG_INT_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTR_BCM53570_B0r */
  10276         soc_block_list[4],
  10277         soc_genreg,
  10278         1,
  10279         0,
  10280         0x20ec100,
  10281         SOC_REG_FLAG_RO,
  10282         0,
  10283         1,
  10284         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10286         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10287         -1,
  10288         -1,
  10289     },
  10290 #endif /* chips */
  10291 
  10292 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  10293     { /* SOC_REG_INT_WRED_DROP_PROFILE_RED_PARITY_ERR_PTRr */
  10294         soc_block_list[4],
  10295         soc_genreg,
  10296         1,
  10297         0,
  10298         0x2169500,
  10299         SOC_REG_FLAG_RO,
  10300         0,
  10301         1,
  10302         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10304         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10305         -1,
  10306         -1,
  10307     },
  10308 #endif /* chips */
  10309 
  10310 #if defined(BCM_53540_A0)
  10311     { /* SOC_REG_INT_WRED_DROP_PROFILE_RED_PARITY_ERR_PTR_BCM53540_A0r */
  10312         soc_block_list[4],
  10313         soc_genreg,
  10314         1,
  10315         0,
  10316         0x2081800,
  10317         SOC_REG_FLAG_RO,
  10318         0,
  10319         1,
  10320         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10322         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10323         -1,
  10324         -1,
  10325     },
  10326 #endif /* chips */
  10327 
  10328 #if defined(BCM_53570_A0)
  10329     { /* SOC_REG_INT_WRED_DROP_PROFILE_RED_PARITY_ERR_PTR_BCM53570_A0r */
  10330         soc_block_list[4],
  10331         soc_genreg,
  10332         1,
  10333         0,
  10334         0x20ece00,
  10335         SOC_REG_FLAG_RO,
  10336         0,
  10337         1,
  10338         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10340         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10341         -1,
  10342         -1,
  10343     },
  10344 #endif /* chips */
  10345 
  10346 #if defined(BCM_53570_B0)
  10347     { /* SOC_REG_INT_WRED_DROP_PROFILE_RED_PARITY_ERR_PTR_BCM53570_B0r */
  10348         soc_block_list[4],
  10349         soc_genreg,
  10350         1,
  10351         0,
  10352         0x20ed100,
  10353         SOC_REG_FLAG_RO,
  10354         0,
  10355         1,
  10356         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10358         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10359         -1,
  10360         -1,
  10361     },
  10362 #endif /* chips */
  10363 
  10364 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  10365     { /* SOC_REG_INT_WRED_DROP_PROFILE_YELLOW_PARITY_ERR_PTRr */
  10366         soc_block_list[4],
  10367         soc_genreg,
  10368         1,
  10369         0,
  10370         0x2169400,
  10371         SOC_REG_FLAG_RO,
  10372         0,
  10373         1,
  10374         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10376         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10377         -1,
  10378         -1,
  10379     },
  10380 #endif /* chips */
  10381 
  10382 #if defined(BCM_53540_A0)
  10383     { /* SOC_REG_INT_WRED_DROP_PROFILE_YELLOW_PARITY_ERR_PTR_BCM53540_A0r */
  10384         soc_block_list[4],
  10385         soc_genreg,
  10386         1,
  10387         0,
  10388         0x2081000,
  10389         SOC_REG_FLAG_RO,
  10390         0,
  10391         1,
  10392         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10394         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10395         -1,
  10396         -1,
  10397     },
  10398 #endif /* chips */
  10399 
  10400 #if defined(BCM_53570_A0)
  10401     { /* SOC_REG_INT_WRED_DROP_PROFILE_YELLOW_PARITY_ERR_PTR_BCM53570_A0r */
  10402         soc_block_list[4],
  10403         soc_genreg,
  10404         1,
  10405         0,
  10406         0x20ec600,
  10407         SOC_REG_FLAG_RO,
  10408         0,
  10409         1,
  10410         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10412         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10413         -1,
  10414         -1,
  10415     },
  10416 #endif /* chips */
  10417 
  10418 #if defined(BCM_53570_B0)
  10419     { /* SOC_REG_INT_WRED_DROP_PROFILE_YELLOW_PARITY_ERR_PTR_BCM53570_B0r */
  10420         soc_block_list[4],
  10421         soc_genreg,
  10422         1,
  10423         0,
  10424         0x20ec900,
  10425         SOC_REG_FLAG_RO,
  10426         0,
  10427         1,
  10428         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10430         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10431         -1,
  10432         -1,
  10433     },
  10434 #endif /* chips */
  10435 
  10436 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  10437     { /* SOC_REG_INT_WRED_DROP_THD_READ_CONTROLr */
  10438         soc_block_list[4],
  10439         soc_genreg,
  10440         1,
  10441         0,
  10442         0x2165000,
  10443         0,
  10444         0,
  10445         2,
  10446         soc_WRED_DROP_THD_READ_CONTROLr_fields,
  10447         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  10448         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  10449         -1,
  10450         -1,
  10451     },
  10452 #endif /* chips */
  10453 
  10454 #if defined(BCM_53540_A0)
  10455     { /* SOC_REG_INT_WRED_DROP_THD_READ_CONTROL_BCM53540_A0r */
  10456         soc_block_list[4],
  10457         soc_genreg,
  10458         1,
  10459         0,
  10460         0x207d000,
  10461         0,
  10462         0,
  10463         2,
  10464         soc_WRED_DROP_THD_READ_CONTROLr_fields,
  10465         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  10466         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  10467         -1,
  10468         -1,
  10469     },
  10470 #endif /* chips */
  10471 
  10472 #if defined(BCM_53570_A0)
  10473     { /* SOC_REG_INT_WRED_DROP_THD_READ_CONTROL_BCM53570_A0r */
  10474         soc_block_list[4],
  10475         soc_genreg,
  10476         1,
  10477         0,
  10478         0x20e6600,
  10479         0,
  10480         0,
  10481         2,
  10482         soc_WRED_DROP_THD_READ_CONTROL_BCM53570_A0r_fields,
  10483         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  10484         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  10485         -1,
  10486         -1,
  10487     },
  10488 #endif /* chips */
  10489 
  10490 #if defined(BCM_53570_B0)
  10491     { /* SOC_REG_INT_WRED_DROP_THD_READ_CONTROL_BCM53570_B0r */
  10492         soc_block_list[4],
  10493         soc_genreg,
  10494         1,
  10495         0,
  10496         0x20e6900,
  10497         0,
  10498         0,
  10499         2,
  10500         soc_WRED_DROP_THD_READ_CONTROL_BCM53570_A0r_fields,
  10501         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  10502         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  10503         -1,
  10504         -1,
  10505     },
  10506 #endif /* chips */
  10507 
  10508 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  10509     { /* SOC_REG_INT_WRED_DROP_THD_READ_DATAr */
  10510         soc_block_list[4],
  10511         soc_genreg,
  10512         1,
  10513         0,
  10514         0x2166000,
  10515         SOC_REG_FLAG_RO,
  10516         0,
  10517         4,
  10518         soc_WRED_DROP_THD_READ_DATAr_fields,
  10519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10520         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  10521         -1,
  10522         -1,
  10523     },
  10524 #endif /* chips */
  10525 
  10526 #if defined(BCM_53540_A0)
  10527     { /* SOC_REG_INT_WRED_DROP_THD_READ_DATA_BCM53540_A0r */
  10528         soc_block_list[4],
  10529         soc_genreg,
  10530         1,
  10531         0,
  10532         0x207d800,
  10533         SOC_REG_FLAG_RO,
  10534         0,
  10535         4,
  10536         soc_WRED_DROP_THD_READ_DATAr_fields,
  10537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10538         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  10539         -1,
  10540         -1,
  10541     },
  10542 #endif /* chips */
  10543 
  10544 #if defined(BCM_53570_A0)
  10545     { /* SOC_REG_INT_WRED_DROP_THD_READ_DATA_BCM53570_A0r */
  10546         soc_block_list[4],
  10547         soc_genreg,
  10548         1,
  10549         0,
  10550         0x20e6e00,
  10551         SOC_REG_FLAG_RO,
  10552         0,
  10553         4,
  10554         soc_WRED_DROP_THD_READ_DATAr_fields,
  10555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10556         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  10557         -1,
  10558         -1,
  10559     },
  10560 #endif /* chips */
  10561 
  10562 #if defined(BCM_53570_B0)
  10563     { /* SOC_REG_INT_WRED_DROP_THD_READ_DATA_BCM53570_B0r */
  10564         soc_block_list[4],
  10565         soc_genreg,
  10566         1,
  10567         0,
  10568         0x20e7100,
  10569         SOC_REG_FLAG_RO,
  10570         0,
  10571         4,
  10572         soc_WRED_DROP_THD_READ_DATAr_fields,
  10573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10574         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  10575         -1,
  10576         -1,
  10577     },
  10578 #endif /* chips */
  10579 
  10580 #if defined(BCM_56860_A0)
  10581     { /* SOC_REG_INT_WRED_EN_COR_ERR_RPT_X_PIPEr */
  10582         soc_block_list[4],
  10583         soc_genreg,
  10584         1,
  10585         0,
  10586         0x760c1800,
  10587         0,
  10588         0,
  10589         17,
  10590         soc_WRED_EN_COR_ERR_RPT_X_PIPEr_fields,
  10591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10592         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10593         -1,
  10594         -1,
  10595     },
  10596 #endif /* chips */
  10597 
  10598 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  10599     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10600     { /* SOC_REG_INT_WRED_EN_COR_ERR_RPT_X_PIPE_BCM56560_A0r */
  10601         soc_block_list[4],
  10602         soc_genreg,
  10603         1,
  10604         0,
  10605         0x760c1800,
  10606         0,
  10607         0,
  10608         17,
  10609         soc_WRED_EN_COR_ERR_RPT_X_PIPE_BCM56560_A0r_fields,
  10610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10612         -1,
  10613         -1,
  10614     },
  10615 #endif /* chips */
  10616 
  10617 #if defined(BCM_56860_A0)
  10618     { /* SOC_REG_INT_WRED_EN_COR_ERR_RPT_Y_PIPEr */
  10619         soc_block_list[4],
  10620         soc_genreg,
  10621         1,
  10622         0,
  10623         0x760c1900,
  10624         0,
  10625         0,
  10626         17,
  10627         soc_WRED_EN_COR_ERR_RPT_X_PIPEr_fields,
  10628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10629         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10630         -1,
  10631         -1,
  10632     },
  10633 #endif /* chips */
  10634 
  10635 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  10636     { /* SOC_REG_INT_WRED_ERR_CLRr */
  10637         soc_block_list[4],
  10638         soc_genreg,
  10639         1,
  10640         0,
  10641         0x2098500,
  10642         SOC_REG_FLAG_WO,
  10643         0,
  10644         1,
  10645         soc_WRED_ERR_CLRr_fields,
  10646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10647         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  10648         -1,
  10649         -1,
  10650     },
  10651 #endif /* chips */
  10652 
  10653 #if defined(BCM_53540_A0)
  10654     { /* SOC_REG_INT_WRED_ERR_CLR_BCM53540_A0r */
  10655         soc_block_list[4],
  10656         soc_genreg,
  10657         1,
  10658         0,
  10659         0x202d800,
  10660         SOC_REG_FLAG_WO,
  10661         0,
  10662         1,
  10663         soc_WRED_ERR_CLRr_fields,
  10664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10665         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  10666         -1,
  10667         -1,
  10668     },
  10669 #endif /* chips */
  10670 
  10671 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  10672     { /* SOC_REG_INT_WRED_ERR_CLR_BCM53570_A0r */
  10673         soc_block_list[4],
  10674         soc_genreg,
  10675         1,
  10676         0,
  10677         0x204ea00,
  10678         SOC_REG_FLAG_WO,
  10679         0,
  10680         1,
  10681         soc_WRED_ERR_CLR_BCM53570_A0r_fields,
  10682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10683         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  10684         -1,
  10685         -1,
  10686     },
  10687 #endif /* chips */
  10688 
  10689 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  10690     { /* SOC_REG_INT_WRED_MARK_PROFILE_GREEN_PARITY_ERR_PTRr */
  10691         soc_block_list[4],
  10692         soc_genreg,
  10693         1,
  10694         0,
  10695         0x2169600,
  10696         SOC_REG_FLAG_RO,
  10697         0,
  10698         1,
  10699         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10701         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10702         -1,
  10703         -1,
  10704     },
  10705 #endif /* chips */
  10706 
  10707 #if defined(BCM_53540_A0)
  10708     { /* SOC_REG_INT_WRED_MARK_PROFILE_GREEN_PARITY_ERR_PTR_BCM53540_A0r */
  10709         soc_block_list[4],
  10710         soc_genreg,
  10711         1,
  10712         0,
  10713         0x2082000,
  10714         SOC_REG_FLAG_RO,
  10715         0,
  10716         1,
  10717         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10719         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10720         -1,
  10721         -1,
  10722     },
  10723 #endif /* chips */
  10724 
  10725 #if defined(BCM_53570_A0)
  10726     { /* SOC_REG_INT_WRED_MARK_PROFILE_GREEN_PARITY_ERR_PTR_BCM53570_A0r */
  10727         soc_block_list[4],
  10728         soc_genreg,
  10729         1,
  10730         0,
  10731         0x20ed600,
  10732         SOC_REG_FLAG_RO,
  10733         0,
  10734         1,
  10735         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10737         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10738         -1,
  10739         -1,
  10740     },
  10741 #endif /* chips */
  10742 
  10743 #if defined(BCM_53570_B0)
  10744     { /* SOC_REG_INT_WRED_MARK_PROFILE_GREEN_PARITY_ERR_PTR_BCM53570_B0r */
  10745         soc_block_list[4],
  10746         soc_genreg,
  10747         1,
  10748         0,
  10749         0x20ed900,
  10750         SOC_REG_FLAG_RO,
  10751         0,
  10752         1,
  10753         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10755         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10756         -1,
  10757         -1,
  10758     },
  10759 #endif /* chips */
  10760 
  10761 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  10762     { /* SOC_REG_INT_WRED_MARK_PROFILE_RED_PARITY_ERR_PTRr */
  10763         soc_block_list[4],
  10764         soc_genreg,
  10765         1,
  10766         0,
  10767         0x2169800,
  10768         SOC_REG_FLAG_RO,
  10769         0,
  10770         1,
  10771         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10773         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10774         -1,
  10775         -1,
  10776     },
  10777 #endif /* chips */
  10778 
  10779 #if defined(BCM_53540_A0)
  10780     { /* SOC_REG_INT_WRED_MARK_PROFILE_RED_PARITY_ERR_PTR_BCM53540_A0r */
  10781         soc_block_list[4],
  10782         soc_genreg,
  10783         1,
  10784         0,
  10785         0x2083000,
  10786         SOC_REG_FLAG_RO,
  10787         0,
  10788         1,
  10789         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10791         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10792         -1,
  10793         -1,
  10794     },
  10795 #endif /* chips */
  10796 
  10797 #if defined(BCM_53570_A0)
  10798     { /* SOC_REG_INT_WRED_MARK_PROFILE_RED_PARITY_ERR_PTR_BCM53570_A0r */
  10799         soc_block_list[4],
  10800         soc_genreg,
  10801         1,
  10802         0,
  10803         0x20ee600,
  10804         SOC_REG_FLAG_RO,
  10805         0,
  10806         1,
  10807         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10809         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10810         -1,
  10811         -1,
  10812     },
  10813 #endif /* chips */
  10814 
  10815 #if defined(BCM_53570_B0)
  10816     { /* SOC_REG_INT_WRED_MARK_PROFILE_RED_PARITY_ERR_PTR_BCM53570_B0r */
  10817         soc_block_list[4],
  10818         soc_genreg,
  10819         1,
  10820         0,
  10821         0x20ee900,
  10822         SOC_REG_FLAG_RO,
  10823         0,
  10824         1,
  10825         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10827         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10828         -1,
  10829         -1,
  10830     },
  10831 #endif /* chips */
  10832 
  10833 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  10834     { /* SOC_REG_INT_WRED_MARK_PROFILE_YELLOW_PARITY_ERR_PTRr */
  10835         soc_block_list[4],
  10836         soc_genreg,
  10837         1,
  10838         0,
  10839         0x2169700,
  10840         SOC_REG_FLAG_RO,
  10841         0,
  10842         1,
  10843         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10845         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10846         -1,
  10847         -1,
  10848     },
  10849 #endif /* chips */
  10850 
  10851 #if defined(BCM_53540_A0)
  10852     { /* SOC_REG_INT_WRED_MARK_PROFILE_YELLOW_PARITY_ERR_PTR_BCM53540_A0r */
  10853         soc_block_list[4],
  10854         soc_genreg,
  10855         1,
  10856         0,
  10857         0x2082800,
  10858         SOC_REG_FLAG_RO,
  10859         0,
  10860         1,
  10861         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10863         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10864         -1,
  10865         -1,
  10866     },
  10867 #endif /* chips */
  10868 
  10869 #if defined(BCM_53570_A0)
  10870     { /* SOC_REG_INT_WRED_MARK_PROFILE_YELLOW_PARITY_ERR_PTR_BCM53570_A0r */
  10871         soc_block_list[4],
  10872         soc_genreg,
  10873         1,
  10874         0,
  10875         0x20ede00,
  10876         SOC_REG_FLAG_RO,
  10877         0,
  10878         1,
  10879         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10881         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10882         -1,
  10883         -1,
  10884     },
  10885 #endif /* chips */
  10886 
  10887 #if defined(BCM_53570_B0)
  10888     { /* SOC_REG_INT_WRED_MARK_PROFILE_YELLOW_PARITY_ERR_PTR_BCM53570_B0r */
  10889         soc_block_list[4],
  10890         soc_genreg,
  10891         1,
  10892         0,
  10893         0x20ee100,
  10894         SOC_REG_FLAG_RO,
  10895         0,
  10896         1,
  10897         soc_WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr_fields,
  10898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10899         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  10900         -1,
  10901         -1,
  10902     },
  10903 #endif /* chips */
  10904 
  10905 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  10906     { /* SOC_REG_INT_WRED_MARK_THD_PARITY_ERR_PTRr */
  10907         soc_block_list[4],
  10908         soc_genreg,
  10909         1,
  10910         0,
  10911         0x2169000,
  10912         SOC_REG_FLAG_RO,
  10913         0,
  10914         1,
  10915         soc_WRED_AVG_QSIZE_PARITY_ERR_PTRr_fields,
  10916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10917         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  10918         -1,
  10919         -1,
  10920     },
  10921 #endif /* chips */
  10922 
  10923 #if defined(BCM_53540_A0)
  10924     { /* SOC_REG_INT_WRED_MARK_THD_PARITY_ERR_PTR_BCM53540_A0r */
  10925         soc_block_list[4],
  10926         soc_genreg,
  10927         1,
  10928         0,
  10929         0x207f000,
  10930         SOC_REG_FLAG_RO,
  10931         0,
  10932         1,
  10933         soc_WRED_AVG_QSIZE_PARITY_ERR_PTRr_fields,
  10934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10935         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  10936         -1,
  10937         -1,
  10938     },
  10939 #endif /* chips */
  10940 
  10941 #if defined(BCM_53570_A0)
  10942     { /* SOC_REG_INT_WRED_MARK_THD_PARITY_ERR_PTR_BCM53570_A0r */
  10943         soc_block_list[4],
  10944         soc_genreg,
  10945         1,
  10946         0,
  10947         0x20e9600,
  10948         SOC_REG_FLAG_RO,
  10949         0,
  10950         1,
  10951         soc_WRED_AVG_QSIZE_PARITY_ERR_PTR_BCM53570_A0r_fields,
  10952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10953         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  10954         -1,
  10955         -1,
  10956     },
  10957 #endif /* chips */
  10958 
  10959 #if defined(BCM_53570_B0)
  10960     { /* SOC_REG_INT_WRED_MARK_THD_PARITY_ERR_PTR_BCM53570_B0r */
  10961         soc_block_list[4],
  10962         soc_genreg,
  10963         1,
  10964         0,
  10965         0x20e9900,
  10966         SOC_REG_FLAG_RO,
  10967         0,
  10968         1,
  10969         soc_WRED_AVG_QSIZE_PARITY_ERR_PTR_BCM53570_A0r_fields,
  10970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10971         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  10972         -1,
  10973         -1,
  10974     },
  10975 #endif /* chips */
  10976 
  10977 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  10978     defined(BCM_56870_A0) || defined(BCM_56970_A0)
  10979     { /* SOC_REG_INT_WRED_MEM_INIT_STATUSr */
  10980         soc_block_list[124],
  10981         soc_xpereg,
  10982         1,
  10983         0,
  10984         0x22800700,
  10985         SOC_REG_FLAG_RO |
  10986                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10987         0,
  10988         1,
  10989         soc_WRED_MEM_INIT_STATUSr_fields,
  10990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10991         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10992         -1,
  10993         -1,
  10994         3,
  10995     },
  10996 #endif /* chips */
  10997 
  10998 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10999     { /* SOC_REG_INT_WRED_MISCCONFIGr */
  11000         soc_block_list[4],
  11001         soc_genreg,
  11002         1,
  11003         0,
  11004         0x1708000d,
  11005         0,
  11006         0,
  11007         7,
  11008         soc_WRED_MISCCONFIGr_fields,
  11009         SOC_RESET_VAL_DEC(0x00000803, 0x00000000)
  11010         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  11011         -1,
  11012         -1,
  11013     },
  11014 #endif /* chips */
  11015 
  11016 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  11017     { /* SOC_REG_INT_WRED_MISCCONFIG_BCM56260_A0r */
  11018         soc_block_list[4],
  11019         soc_genreg,
  11020         1,
  11021         0,
  11022         0x5e001400,
  11023         0,
  11024         0,
  11025         8,
  11026         soc_WRED_MISCCONFIG_BCM56260_A0r_fields,
  11027         SOC_RESET_VAL_DEC(0x00000c03, 0x00000000)
  11028         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  11029         -1,
  11030         -1,
  11031     },
  11032 #endif /* chips */
  11033 
  11034 #if defined(BCM_56270_A0)
  11035     { /* SOC_REG_INT_WRED_MISCCONFIG_BCM56270_A0r */
  11036         soc_block_list[4],
  11037         soc_genreg,
  11038         1,
  11039         0,
  11040         0x5e000a00,
  11041         0,
  11042         0,
  11043         8,
  11044         soc_WRED_MISCCONFIG_BCM56270_A0r_fields,
  11045         SOC_RESET_VAL_DEC(0x00000403, 0x00000000)
  11046         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  11047         -1,
  11048         -1,
  11049     },
  11050 #endif /* chips */
  11051 
  11052 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11053     defined(BCM_56450_B1)
  11054     { /* SOC_REG_INT_WRED_MISCCONFIG_BCM56450_A0r */
  11055         soc_block_list[4],
  11056         soc_genreg,
  11057         1,
  11058         0,
  11059         0x5e001400,
  11060         0,
  11061         0,
  11062         8,
  11063         soc_WRED_MISCCONFIG_BCM56450_A0r_fields,
  11064         SOC_RESET_VAL_DEC(0x00000603, 0x00000000)
  11065         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  11066         -1,
  11067         -1,
  11068     },
  11069 #endif /* chips */
  11070 
  11071 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  11072     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11073     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11074     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11075     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  11076     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11077     { /* SOC_REG_INT_WRED_PARITY_ERROR_BITMAPr */
  11078         soc_block_list[4],
  11079         soc_genreg,
  11080         1,
  11081         0,
  11082         0x17080002,
  11083         0,
  11084         0,
  11085         1,
  11086         soc_WRED_PARITY_ERROR_BITMAPr_fields,
  11087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11088         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  11089         -1,
  11090         -1,
  11091     },
  11092 #endif /* chips */
  11093 
  11094 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  11095     { /* SOC_REG_INT_WRED_PARITY_ERROR_BITMAP_BCM56260_A0r */
  11096         soc_block_list[4],
  11097         soc_genreg,
  11098         1,
  11099         0,
  11100         0x5e001a00,
  11101         0,
  11102         0,
  11103         3,
  11104         soc_WRED_PARITY_ERROR_BITMAP_BCM56260_A0r_fields,
  11105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11106         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11107         -1,
  11108         -1,
  11109     },
  11110 #endif /* chips */
  11111 
  11112 #if defined(BCM_56270_A0)
  11113     { /* SOC_REG_INT_WRED_PARITY_ERROR_BITMAP_BCM56270_A0r */
  11114         soc_block_list[4],
  11115         soc_genreg,
  11116         1,
  11117         0,
  11118         0x5e001000,
  11119         0,
  11120         0,
  11121         3,
  11122         soc_WRED_PARITY_ERROR_BITMAP_BCM56260_A0r_fields,
  11123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11124         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11125         -1,
  11126         -1,
  11127     },
  11128 #endif /* chips */
  11129 
  11130 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11131     { /* SOC_REG_INT_WRED_PARITY_ERROR_BITMAP_BCM56440_A0r */
  11132         soc_block_list[4],
  11133         soc_genreg,
  11134         1,
  11135         0,
  11136         0x17080012,
  11137         0,
  11138         0,
  11139         3,
  11140         soc_WRED_PARITY_ERROR_BITMAP_BCM56440_A0r_fields,
  11141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11142         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11143         -1,
  11144         -1,
  11145     },
  11146 #endif /* chips */
  11147 
  11148 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11149     defined(BCM_56450_B1)
  11150     { /* SOC_REG_INT_WRED_PARITY_ERROR_BITMAP_BCM56450_A0r */
  11151         soc_block_list[4],
  11152         soc_genreg,
  11153         1,
  11154         0,
  11155         0x5e001a00,
  11156         0,
  11157         0,
  11158         3,
  11159         soc_WRED_PARITY_ERROR_BITMAP_BCM56450_A0r_fields,
  11160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11161         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11162         -1,
  11163         -1,
  11164     },
  11165 #endif /* chips */
  11166 
  11167 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  11168     { /* SOC_REG_INT_WRED_PARITY_ERROR_BITMAP_BCM56640_A0r */
  11169         soc_block_list[4],
  11170         soc_genreg,
  11171         1,
  11172         0,
  11173         0x56000500,
  11174         0,
  11175         0,
  11176         1,
  11177         soc_WRED_PARITY_ERROR_BITMAP_BCM56640_A0r_fields,
  11178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11179         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  11180         -1,
  11181         -1,
  11182     },
  11183 #endif /* chips */
  11184 
  11185 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  11186     { /* SOC_REG_INT_WRED_PARITY_ERROR_BITMAP_BCM56820_A0r */
  11187         soc_block_list[4],
  11188         soc_genreg,
  11189         1,
  11190         0,
  11191         0x12080002,
  11192         0,
  11193         0,
  11194         1,
  11195         soc_WRED_PARITY_ERROR_BITMAP_BCM56820_A0r_fields,
  11196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11197         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  11198         -1,
  11199         -1,
  11200     },
  11201 #endif /* chips */
  11202 
  11203 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11204     { /* SOC_REG_INT_WRED_PARITY_ERROR_BITMAP_BCM56840_A0r */
  11205         soc_block_list[4],
  11206         soc_genreg,
  11207         1,
  11208         0,
  11209         0x17080005,
  11210         0,
  11211         0,
  11212         1,
  11213         soc_WRED_PARITY_ERROR_BITMAP_BCM56820_A0r_fields,
  11214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11215         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  11216         -1,
  11217         -1,
  11218     },
  11219 #endif /* chips */
  11220 
  11221 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11222     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11223     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11224     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  11225     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11226     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFOr */
  11227         soc_block_list[4],
  11228         soc_genreg,
  11229         1,
  11230         0,
  11231         0x17080001,
  11232         0,
  11233         0,
  11234         1,
  11235         soc_WRED_PARITY_ERROR_INFOr_fields,
  11236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11237         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11238         -1,
  11239         -1,
  11240     },
  11241 #endif /* chips */
  11242 
  11243 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11244     defined(BCM_56450_B1)
  11245     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFO_2BITr */
  11246         soc_block_list[4],
  11247         soc_genreg,
  11248         1,
  11249         0,
  11250         0x5e001700,
  11251         SOC_REG_FLAG_RO,
  11252         0,
  11253         1,
  11254         soc_WRED_PARITY_ERROR_INFO_2BITr_fields,
  11255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11256         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11257         -1,
  11258         -1,
  11259     },
  11260 #endif /* chips */
  11261 
  11262 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  11263     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFO_2BIT_BCM56260_A0r */
  11264         soc_block_list[4],
  11265         soc_genreg,
  11266         1,
  11267         0,
  11268         0x5e001700,
  11269         SOC_REG_FLAG_RO,
  11270         0,
  11271         1,
  11272         soc_WRED_PARITY_ERROR_INFO_2BIT_BCM56260_A0r_fields,
  11273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11274         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11275         -1,
  11276         -1,
  11277     },
  11278 #endif /* chips */
  11279 
  11280 #if defined(BCM_56270_A0)
  11281     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFO_2BIT_BCM56270_A0r */
  11282         soc_block_list[4],
  11283         soc_genreg,
  11284         1,
  11285         0,
  11286         0x5e000d00,
  11287         SOC_REG_FLAG_RO,
  11288         0,
  11289         1,
  11290         soc_WRED_PARITY_ERROR_INFO_2BIT_BCM56260_A0r_fields,
  11291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11292         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11293         -1,
  11294         -1,
  11295     },
  11296 #endif /* chips */
  11297 
  11298 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  11299     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFO_BCM56260_A0r */
  11300         soc_block_list[4],
  11301         soc_genreg,
  11302         1,
  11303         0,
  11304         0x5e001800,
  11305         SOC_REG_FLAG_RO,
  11306         0,
  11307         1,
  11308         soc_WRED_PARITY_ERROR_INFO_BCM56260_A0r_fields,
  11309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11310         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11311         -1,
  11312         -1,
  11313     },
  11314 #endif /* chips */
  11315 
  11316 #if defined(BCM_56270_A0)
  11317     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFO_BCM56270_A0r */
  11318         soc_block_list[4],
  11319         soc_genreg,
  11320         1,
  11321         0,
  11322         0x5e000e00,
  11323         SOC_REG_FLAG_RO,
  11324         0,
  11325         1,
  11326         soc_WRED_PARITY_ERROR_INFO_BCM56260_A0r_fields,
  11327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11328         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11329         -1,
  11330         -1,
  11331     },
  11332 #endif /* chips */
  11333 
  11334 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  11335     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFO_BCM56334_A0r */
  11336         soc_block_list[4],
  11337         soc_genreg,
  11338         1,
  11339         0,
  11340         0x17080001,
  11341         0,
  11342         0,
  11343         1,
  11344         soc_WRED_PARITY_ERROR_INFO_BCM56334_A0r_fields,
  11345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11346         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  11347         -1,
  11348         -1,
  11349     },
  11350 #endif /* chips */
  11351 
  11352 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11353     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFO_BCM56440_A0r */
  11354         soc_block_list[4],
  11355         soc_genreg,
  11356         1,
  11357         0,
  11358         0x17080010,
  11359         SOC_REG_FLAG_RO,
  11360         0,
  11361         1,
  11362         soc_WRED_PARITY_ERROR_INFO_BCM56440_A0r_fields,
  11363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11364         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11365         -1,
  11366         -1,
  11367     },
  11368 #endif /* chips */
  11369 
  11370 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11371     defined(BCM_56450_B1)
  11372     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFO_BCM56450_A0r */
  11373         soc_block_list[4],
  11374         soc_genreg,
  11375         1,
  11376         0,
  11377         0x5e001800,
  11378         SOC_REG_FLAG_RO,
  11379         0,
  11380         1,
  11381         soc_WRED_PARITY_ERROR_INFO_BCM56450_A0r_fields,
  11382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11384         -1,
  11385         -1,
  11386     },
  11387 #endif /* chips */
  11388 
  11389 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  11390     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFO_BCM56640_A0r */
  11391         soc_block_list[4],
  11392         soc_genreg,
  11393         1,
  11394         0,
  11395         0x56000400,
  11396         0,
  11397         0,
  11398         1,
  11399         soc_WRED_PARITY_ERROR_INFO_BCM56640_A0r_fields,
  11400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11401         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  11402         -1,
  11403         -1,
  11404     },
  11405 #endif /* chips */
  11406 
  11407 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  11408     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFO_BCM56820_A0r */
  11409         soc_block_list[4],
  11410         soc_genreg,
  11411         1,
  11412         0,
  11413         0x12080001,
  11414         0,
  11415         0,
  11416         1,
  11417         soc_WRED_PARITY_ERROR_INFO_BCM56820_A0r_fields,
  11418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11419         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  11420         -1,
  11421         -1,
  11422     },
  11423 #endif /* chips */
  11424 
  11425 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11426     { /* SOC_REG_INT_WRED_PARITY_ERROR_INFO_BCM56840_A0r */
  11427         soc_block_list[4],
  11428         soc_genreg,
  11429         1,
  11430         0,
  11431         0x17080004,
  11432         0,
  11433         0,
  11434         1,
  11435         soc_WRED_PARITY_ERROR_INFO_BCM56840_A0r_fields,
  11436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11437         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  11438         -1,
  11439         -1,
  11440     },
  11441 #endif /* chips */
  11442 
  11443 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11444     { /* SOC_REG_INT_WRED_PARITY_ERROR_MASKr */
  11445         soc_block_list[4],
  11446         soc_genreg,
  11447         1,
  11448         0,
  11449         0x17080011,
  11450         0,
  11451         0,
  11452         4,
  11453         soc_WRED_PARITY_ERROR_MASKr_fields,
  11454         SOC_RESET_VAL_DEC(0x07ffffff, 0x00000000)
  11455         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  11456         -1,
  11457         -1,
  11458     },
  11459 #endif /* chips */
  11460 
  11461 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  11462     { /* SOC_REG_INT_WRED_PARITY_ERROR_MASK_BCM56260_A0r */
  11463         soc_block_list[4],
  11464         soc_genreg,
  11465         1,
  11466         0,
  11467         0x5e001900,
  11468         0,
  11469         0,
  11470         4,
  11471         soc_WRED_PARITY_ERROR_MASK_BCM56260_A0r_fields,
  11472         SOC_RESET_VAL_DEC(0x07ffffff, 0x00000000)
  11473         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  11474         -1,
  11475         -1,
  11476     },
  11477 #endif /* chips */
  11478 
  11479 #if defined(BCM_56270_A0)
  11480     { /* SOC_REG_INT_WRED_PARITY_ERROR_MASK_BCM56270_A0r */
  11481         soc_block_list[4],
  11482         soc_genreg,
  11483         1,
  11484         0,
  11485         0x5e000f00,
  11486         0,
  11487         0,
  11488         4,
  11489         soc_WRED_PARITY_ERROR_MASK_BCM56260_A0r_fields,
  11490         SOC_RESET_VAL_DEC(0x07ffffff, 0x00000000)
  11491         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  11492         -1,
  11493         -1,
  11494     },
  11495 #endif /* chips */
  11496 
  11497 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11498     defined(BCM_56450_B1)
  11499     { /* SOC_REG_INT_WRED_PARITY_ERROR_MASK_BCM56450_A0r */
  11500         soc_block_list[4],
  11501         soc_genreg,
  11502         1,
  11503         0,
  11504         0x5e001900,
  11505         0,
  11506         0,
  11507         4,
  11508         soc_WRED_PARITY_ERROR_MASK_BCM56450_A0r_fields,
  11509         SOC_RESET_VAL_DEC(0x07ffffff, 0x00000000)
  11510         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  11511         -1,
  11512         -1,
  11513     },
  11514 #endif /* chips */
  11515 
  11516 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11517     { /* SOC_REG_INT_WRED_PARITY_ERROR_POINTERr */
  11518         soc_block_list[4],
  11519         soc_genreg,
  11520         1,
  11521         0,
  11522         0x1708000f,
  11523         SOC_REG_FLAG_RO,
  11524         0,
  11525         3,
  11526         soc_WRED_PARITY_ERROR_POINTERr_fields,
  11527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11528         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11529         -1,
  11530         -1,
  11531     },
  11532 #endif /* chips */
  11533 
  11534 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  11535     { /* SOC_REG_INT_WRED_PARITY_ERROR_POINTER_BCM56260_A0r */
  11536         soc_block_list[4],
  11537         soc_genreg,
  11538         1,
  11539         0,
  11540         0x5e001600,
  11541         SOC_REG_FLAG_RO,
  11542         0,
  11543         3,
  11544         soc_WRED_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  11545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11546         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11547         -1,
  11548         -1,
  11549     },
  11550 #endif /* chips */
  11551 
  11552 #if defined(BCM_56270_A0)
  11553     { /* SOC_REG_INT_WRED_PARITY_ERROR_POINTER_BCM56270_A0r */
  11554         soc_block_list[4],
  11555         soc_genreg,
  11556         1,
  11557         0,
  11558         0x5e000c00,
  11559         SOC_REG_FLAG_RO,
  11560         0,
  11561         3,
  11562         soc_WRED_PARITY_ERROR_POINTER_BCM56270_A0r_fields,
  11563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11564         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11565         -1,
  11566         -1,
  11567     },
  11568 #endif /* chips */
  11569 
  11570 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11571     defined(BCM_56450_B1)
  11572     { /* SOC_REG_INT_WRED_PARITY_ERROR_POINTER_BCM56450_A0r */
  11573         soc_block_list[4],
  11574         soc_genreg,
  11575         1,
  11576         0,
  11577         0x5e001600,
  11578         SOC_REG_FLAG_RO,
  11579         0,
  11580         3,
  11581         soc_WRED_PARITY_ERROR_POINTER_BCM56450_A0r_fields,
  11582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11583         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11584         -1,
  11585         -1,
  11586     },
  11587 #endif /* chips */
  11588 
  11589 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  11590     { /* SOC_REG_INT_WRED_PARITY_ERR_COUNTERr */
  11591         soc_block_list[4],
  11592         soc_genreg,
  11593         1,
  11594         0,
  11595         0x2167000,
  11596         0,
  11597         0,
  11598         1,
  11599         soc_WRED_PARITY_ERR_COUNTERr_fields,
  11600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11601         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  11602         -1,
  11603         -1,
  11604     },
  11605 #endif /* chips */
  11606 
  11607 #if defined(BCM_53540_A0)
  11608     { /* SOC_REG_INT_WRED_PARITY_ERR_COUNTER_BCM53540_A0r */
  11609         soc_block_list[4],
  11610         soc_genreg,
  11611         1,
  11612         0,
  11613         0x207e000,
  11614         0,
  11615         0,
  11616         1,
  11617         soc_WRED_PARITY_ERR_COUNTERr_fields,
  11618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11619         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  11620         -1,
  11621         -1,
  11622     },
  11623 #endif /* chips */
  11624 
  11625 #if defined(BCM_53570_A0)
  11626     { /* SOC_REG_INT_WRED_PARITY_ERR_COUNTER_BCM53570_A0r */
  11627         soc_block_list[4],
  11628         soc_genreg,
  11629         1,
  11630         0,
  11631         0x20e8600,
  11632         0,
  11633         0,
  11634         1,
  11635         soc_WRED_PARITY_ERR_COUNTERr_fields,
  11636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11637         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  11638         -1,
  11639         -1,
  11640     },
  11641 #endif /* chips */
  11642 
  11643 #if defined(BCM_53570_B0)
  11644     { /* SOC_REG_INT_WRED_PARITY_ERR_COUNTER_BCM53570_B0r */
  11645         soc_block_list[4],
  11646         soc_genreg,
  11647         1,
  11648         0,
  11649         0x20e8900,
  11650         0,
  11651         0,
  11652         1,
  11653         soc_WRED_PARITY_ERR_COUNTERr_fields,
  11654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11655         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  11656         -1,
  11657         -1,
  11658     },
  11659 #endif /* chips */
  11660 
  11661 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  11662     { /* SOC_REG_INT_WRED_PARITY_ERR_STATUSr */
  11663         soc_block_list[4],
  11664         soc_genreg,
  11665         1,
  11666         0,
  11667         0x2168000,
  11668         SOC_REG_FLAG_RO,
  11669         0,
  11670         2,
  11671         soc_WRED_PARITY_ERR_STATUSr_fields,
  11672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11673         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  11674         -1,
  11675         -1,
  11676     },
  11677 #endif /* chips */
  11678 
  11679 #if defined(BCM_53540_A0)
  11680     { /* SOC_REG_INT_WRED_PARITY_ERR_STATUS_BCM53540_A0r */
  11681         soc_block_list[4],
  11682         soc_genreg,
  11683         1,
  11684         0,
  11685         0x207e800,
  11686         SOC_REG_FLAG_RO,
  11687         0,
  11688         2,
  11689         soc_WRED_PARITY_ERR_STATUSr_fields,
  11690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11691         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  11692         -1,
  11693         -1,
  11694     },
  11695 #endif /* chips */
  11696 
  11697 #if defined(BCM_53570_A0)
  11698     { /* SOC_REG_INT_WRED_PARITY_ERR_STATUS_BCM53570_A0r */
  11699         soc_block_list[4],
  11700         soc_genreg,
  11701         1,
  11702         0,
  11703         0x20e8e00,
  11704         SOC_REG_FLAG_RO,
  11705         0,
  11706         2,
  11707         soc_WRED_PARITY_ERR_STATUS_BCM53570_A0r_fields,
  11708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11709         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  11710         -1,
  11711         -1,
  11712     },
  11713 #endif /* chips */
  11714 
  11715 #if defined(BCM_53570_B0)
  11716     { /* SOC_REG_INT_WRED_PARITY_ERR_STATUS_BCM53570_B0r */
  11717         soc_block_list[4],
  11718         soc_genreg,
  11719         1,
  11720         0,
  11721         0x20e9100,
  11722         SOC_REG_FLAG_RO,
  11723         0,
  11724         2,
  11725         soc_WRED_PARITY_ERR_STATUS_BCM53570_A0r_fields,
  11726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11727         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  11728         -1,
  11729         -1,
  11730     },
  11731 #endif /* chips */
  11732 
  11733 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11734     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_0r */
  11735         soc_block_list[124],
  11736         soc_genreg,
  11737         1,
  11738         0,
  11739         0x22000b00,
  11740         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11741         0,
  11742         2,
  11743         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  11744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11745         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  11746         -1,
  11747         -1,
  11748         3,
  11749     },
  11750 #endif /* chips */
  11751 
  11752 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11753     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_1r */
  11754         soc_block_list[124],
  11755         soc_genreg,
  11756         1,
  11757         0,
  11758         0x22000c00,
  11759         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11760         0,
  11761         2,
  11762         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  11763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11764         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  11765         -1,
  11766         -1,
  11767         3,
  11768     },
  11769 #endif /* chips */
  11770 
  11771 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11772     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_2r */
  11773         soc_block_list[124],
  11774         soc_genreg,
  11775         1,
  11776         0,
  11777         0x22000d00,
  11778         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11779         0,
  11780         2,
  11781         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  11782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11783         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  11784         -1,
  11785         -1,
  11786         3,
  11787     },
  11788 #endif /* chips */
  11789 
  11790 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11791     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_3r */
  11792         soc_block_list[124],
  11793         soc_genreg,
  11794         1,
  11795         0,
  11796         0x22000e00,
  11797         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11798         0,
  11799         2,
  11800         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  11801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11802         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  11803         -1,
  11804         -1,
  11805         3,
  11806     },
  11807 #endif /* chips */
  11808 
  11809 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  11810     defined(BCM_56870_A0)
  11811     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_0_BCM56870_A0r */
  11812         soc_block_list[124],
  11813         soc_genreg,
  11814         1,
  11815         0,
  11816         0x22000c00,
  11817         SOC_REG_FLAG_64_BITS |
  11818                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11819         0,
  11820         2,
  11821         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56870_A0r_fields,
  11822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11823         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  11824         -1,
  11825         -1,
  11826         3,
  11827     },
  11828 #endif /* chips */
  11829 
  11830 #if defined(BCM_56970_A0)
  11831     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r */
  11832         soc_block_list[124],
  11833         soc_genreg,
  11834         1,
  11835         0,
  11836         0x22000c00,
  11837         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11838         0,
  11839         2,
  11840         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  11841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11842         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11843         -1,
  11844         -1,
  11845         3,
  11846     },
  11847 #endif /* chips */
  11848 
  11849 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11850     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_0_XPE0r */
  11851         soc_block_list[124],
  11852         soc_genreg,
  11853         1,
  11854         0,
  11855         0x22000b00,
  11856         0,
  11857         0,
  11858         2,
  11859         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  11860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11861         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  11862         -1,
  11863         -1,
  11864         3,
  11865     },
  11866 #endif /* chips */
  11867 
  11868 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11869     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_0_XPE1r */
  11870         soc_block_list[124],
  11871         soc_genreg,
  11872         1,
  11873         0,
  11874         0x22000b00,
  11875         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11876         0,
  11877         2,
  11878         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  11879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11880         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  11881         -1,
  11882         -1,
  11883         3,
  11884     },
  11885 #endif /* chips */
  11886 
  11887 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11888     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_0_XPE2r */
  11889         soc_block_list[124],
  11890         soc_genreg,
  11891         1,
  11892         0,
  11893         0x22000b00,
  11894         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11895         0,
  11896         2,
  11897         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  11898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11899         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  11900         -1,
  11901         -1,
  11902         3,
  11903     },
  11904 #endif /* chips */
  11905 
  11906 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11907     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_0_XPE3r */
  11908         soc_block_list[124],
  11909         soc_genreg,
  11910         1,
  11911         0,
  11912         0x22000b00,
  11913         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11914         0,
  11915         2,
  11916         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  11917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11918         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  11919         -1,
  11920         -1,
  11921         3,
  11922     },
  11923 #endif /* chips */
  11924 
  11925 #if defined(BCM_56970_A0)
  11926     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_0_XPE0_BCM56970_A0r */
  11927         soc_block_list[124],
  11928         soc_genreg,
  11929         1,
  11930         0,
  11931         0x22000c00,
  11932         0,
  11933         0,
  11934         2,
  11935         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  11936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11937         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11938         -1,
  11939         -1,
  11940         3,
  11941     },
  11942 #endif /* chips */
  11943 
  11944 #if defined(BCM_56970_A0)
  11945     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_0_XPE1_BCM56970_A0r */
  11946         soc_block_list[124],
  11947         soc_genreg,
  11948         1,
  11949         0,
  11950         0x22000c00,
  11951         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11952         0,
  11953         2,
  11954         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  11955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11956         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11957         -1,
  11958         -1,
  11959         3,
  11960     },
  11961 #endif /* chips */
  11962 
  11963 #if defined(BCM_56970_A0)
  11964     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_0_XPE2_BCM56970_A0r */
  11965         soc_block_list[124],
  11966         soc_genreg,
  11967         1,
  11968         0,
  11969         0x22000c00,
  11970         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11971         0,
  11972         2,
  11973         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  11974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11975         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11976         -1,
  11977         -1,
  11978         3,
  11979     },
  11980 #endif /* chips */
  11981 
  11982 #if defined(BCM_56970_A0)
  11983     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_0_XPE3_BCM56970_A0r */
  11984         soc_block_list[124],
  11985         soc_genreg,
  11986         1,
  11987         0,
  11988         0x22000c00,
  11989         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11990         0,
  11991         2,
  11992         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  11993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11994         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11995         -1,
  11996         -1,
  11997         3,
  11998     },
  11999 #endif /* chips */
  12000 
  12001 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  12002     defined(BCM_56870_A0)
  12003     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_1_BCM56870_A0r */
  12004         soc_block_list[124],
  12005         soc_genreg,
  12006         1,
  12007         0,
  12008         0x22000d00,
  12009         SOC_REG_FLAG_64_BITS |
  12010                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12011         0,
  12012         2,
  12013         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56870_A0r_fields,
  12014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12015         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  12016         -1,
  12017         -1,
  12018         3,
  12019     },
  12020 #endif /* chips */
  12021 
  12022 #if defined(BCM_56970_A0)
  12023     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_1_BCM56970_A0r */
  12024         soc_block_list[124],
  12025         soc_genreg,
  12026         1,
  12027         0,
  12028         0x22000d00,
  12029         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12030         0,
  12031         2,
  12032         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12034         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12035         -1,
  12036         -1,
  12037         3,
  12038     },
  12039 #endif /* chips */
  12040 
  12041 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12042     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_1_XPE0r */
  12043         soc_block_list[124],
  12044         soc_genreg,
  12045         1,
  12046         0,
  12047         0x22000c00,
  12048         0,
  12049         0,
  12050         2,
  12051         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12053         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12054         -1,
  12055         -1,
  12056         3,
  12057     },
  12058 #endif /* chips */
  12059 
  12060 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12061     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_1_XPE1r */
  12062         soc_block_list[124],
  12063         soc_genreg,
  12064         1,
  12065         0,
  12066         0x22000c00,
  12067         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12068         0,
  12069         2,
  12070         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12072         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12073         -1,
  12074         -1,
  12075         3,
  12076     },
  12077 #endif /* chips */
  12078 
  12079 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12080     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_1_XPE2r */
  12081         soc_block_list[124],
  12082         soc_genreg,
  12083         1,
  12084         0,
  12085         0x22000c00,
  12086         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12087         0,
  12088         2,
  12089         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12091         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12092         -1,
  12093         -1,
  12094         3,
  12095     },
  12096 #endif /* chips */
  12097 
  12098 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12099     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_1_XPE3r */
  12100         soc_block_list[124],
  12101         soc_genreg,
  12102         1,
  12103         0,
  12104         0x22000c00,
  12105         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12106         0,
  12107         2,
  12108         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12110         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12111         -1,
  12112         -1,
  12113         3,
  12114     },
  12115 #endif /* chips */
  12116 
  12117 #if defined(BCM_56970_A0)
  12118     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_1_XPE0_BCM56970_A0r */
  12119         soc_block_list[124],
  12120         soc_genreg,
  12121         1,
  12122         0,
  12123         0x22000d00,
  12124         0,
  12125         0,
  12126         2,
  12127         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12129         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12130         -1,
  12131         -1,
  12132         3,
  12133     },
  12134 #endif /* chips */
  12135 
  12136 #if defined(BCM_56970_A0)
  12137     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_1_XPE1_BCM56970_A0r */
  12138         soc_block_list[124],
  12139         soc_genreg,
  12140         1,
  12141         0,
  12142         0x22000d00,
  12143         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12144         0,
  12145         2,
  12146         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12148         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12149         -1,
  12150         -1,
  12151         3,
  12152     },
  12153 #endif /* chips */
  12154 
  12155 #if defined(BCM_56970_A0)
  12156     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_1_XPE2_BCM56970_A0r */
  12157         soc_block_list[124],
  12158         soc_genreg,
  12159         1,
  12160         0,
  12161         0x22000d00,
  12162         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12163         0,
  12164         2,
  12165         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12168         -1,
  12169         -1,
  12170         3,
  12171     },
  12172 #endif /* chips */
  12173 
  12174 #if defined(BCM_56970_A0)
  12175     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_1_XPE3_BCM56970_A0r */
  12176         soc_block_list[124],
  12177         soc_genreg,
  12178         1,
  12179         0,
  12180         0x22000d00,
  12181         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12182         0,
  12183         2,
  12184         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12186         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12187         -1,
  12188         -1,
  12189         3,
  12190     },
  12191 #endif /* chips */
  12192 
  12193 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  12194     defined(BCM_56870_A0)
  12195     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_2_BCM56870_A0r */
  12196         soc_block_list[124],
  12197         soc_genreg,
  12198         1,
  12199         0,
  12200         0x22000e00,
  12201         SOC_REG_FLAG_64_BITS |
  12202                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12203         0,
  12204         2,
  12205         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56870_A0r_fields,
  12206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12207         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  12208         -1,
  12209         -1,
  12210         3,
  12211     },
  12212 #endif /* chips */
  12213 
  12214 #if defined(BCM_56970_A0)
  12215     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_2_BCM56970_A0r */
  12216         soc_block_list[124],
  12217         soc_genreg,
  12218         1,
  12219         0,
  12220         0x22000e00,
  12221         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12222         0,
  12223         2,
  12224         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12226         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12227         -1,
  12228         -1,
  12229         3,
  12230     },
  12231 #endif /* chips */
  12232 
  12233 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12234     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_2_XPE0r */
  12235         soc_block_list[124],
  12236         soc_genreg,
  12237         1,
  12238         0,
  12239         0x22000d00,
  12240         0,
  12241         0,
  12242         2,
  12243         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12245         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12246         -1,
  12247         -1,
  12248         3,
  12249     },
  12250 #endif /* chips */
  12251 
  12252 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12253     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_2_XPE1r */
  12254         soc_block_list[124],
  12255         soc_genreg,
  12256         1,
  12257         0,
  12258         0x22000d00,
  12259         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12260         0,
  12261         2,
  12262         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12264         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12265         -1,
  12266         -1,
  12267         3,
  12268     },
  12269 #endif /* chips */
  12270 
  12271 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12272     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_2_XPE2r */
  12273         soc_block_list[124],
  12274         soc_genreg,
  12275         1,
  12276         0,
  12277         0x22000d00,
  12278         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12279         0,
  12280         2,
  12281         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12283         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12284         -1,
  12285         -1,
  12286         3,
  12287     },
  12288 #endif /* chips */
  12289 
  12290 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12291     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_2_XPE3r */
  12292         soc_block_list[124],
  12293         soc_genreg,
  12294         1,
  12295         0,
  12296         0x22000d00,
  12297         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12298         0,
  12299         2,
  12300         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12302         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12303         -1,
  12304         -1,
  12305         3,
  12306     },
  12307 #endif /* chips */
  12308 
  12309 #if defined(BCM_56970_A0)
  12310     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_2_XPE0_BCM56970_A0r */
  12311         soc_block_list[124],
  12312         soc_genreg,
  12313         1,
  12314         0,
  12315         0x22000e00,
  12316         0,
  12317         0,
  12318         2,
  12319         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12321         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12322         -1,
  12323         -1,
  12324         3,
  12325     },
  12326 #endif /* chips */
  12327 
  12328 #if defined(BCM_56970_A0)
  12329     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_2_XPE1_BCM56970_A0r */
  12330         soc_block_list[124],
  12331         soc_genreg,
  12332         1,
  12333         0,
  12334         0x22000e00,
  12335         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12336         0,
  12337         2,
  12338         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12340         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12341         -1,
  12342         -1,
  12343         3,
  12344     },
  12345 #endif /* chips */
  12346 
  12347 #if defined(BCM_56970_A0)
  12348     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_2_XPE2_BCM56970_A0r */
  12349         soc_block_list[124],
  12350         soc_genreg,
  12351         1,
  12352         0,
  12353         0x22000e00,
  12354         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12355         0,
  12356         2,
  12357         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12359         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12360         -1,
  12361         -1,
  12362         3,
  12363     },
  12364 #endif /* chips */
  12365 
  12366 #if defined(BCM_56970_A0)
  12367     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_2_XPE3_BCM56970_A0r */
  12368         soc_block_list[124],
  12369         soc_genreg,
  12370         1,
  12371         0,
  12372         0x22000e00,
  12373         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12374         0,
  12375         2,
  12376         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12378         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12379         -1,
  12380         -1,
  12381         3,
  12382     },
  12383 #endif /* chips */
  12384 
  12385 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  12386     defined(BCM_56870_A0)
  12387     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_3_BCM56870_A0r */
  12388         soc_block_list[124],
  12389         soc_genreg,
  12390         1,
  12391         0,
  12392         0x22000f00,
  12393         SOC_REG_FLAG_64_BITS |
  12394                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12395         0,
  12396         2,
  12397         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56870_A0r_fields,
  12398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12399         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  12400         -1,
  12401         -1,
  12402         3,
  12403     },
  12404 #endif /* chips */
  12405 
  12406 #if defined(BCM_56970_A0)
  12407     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_3_BCM56970_A0r */
  12408         soc_block_list[124],
  12409         soc_genreg,
  12410         1,
  12411         0,
  12412         0x22000f00,
  12413         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12414         0,
  12415         2,
  12416         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12418         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12419         -1,
  12420         -1,
  12421         3,
  12422     },
  12423 #endif /* chips */
  12424 
  12425 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12426     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_3_XPE0r */
  12427         soc_block_list[124],
  12428         soc_genreg,
  12429         1,
  12430         0,
  12431         0x22000e00,
  12432         0,
  12433         0,
  12434         2,
  12435         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12437         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12438         -1,
  12439         -1,
  12440         3,
  12441     },
  12442 #endif /* chips */
  12443 
  12444 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12445     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_3_XPE1r */
  12446         soc_block_list[124],
  12447         soc_genreg,
  12448         1,
  12449         0,
  12450         0x22000e00,
  12451         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12452         0,
  12453         2,
  12454         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12456         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12457         -1,
  12458         -1,
  12459         3,
  12460     },
  12461 #endif /* chips */
  12462 
  12463 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12464     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_3_XPE2r */
  12465         soc_block_list[124],
  12466         soc_genreg,
  12467         1,
  12468         0,
  12469         0x22000e00,
  12470         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12471         0,
  12472         2,
  12473         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12475         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12476         -1,
  12477         -1,
  12478         3,
  12479     },
  12480 #endif /* chips */
  12481 
  12482 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  12483     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_3_XPE3r */
  12484         soc_block_list[124],
  12485         soc_genreg,
  12486         1,
  12487         0,
  12488         0x22000e00,
  12489         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12490         0,
  12491         2,
  12492         soc_WRED_POOL_INST_CONG_LIMIT_0r_fields,
  12493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12494         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  12495         -1,
  12496         -1,
  12497         3,
  12498     },
  12499 #endif /* chips */
  12500 
  12501 #if defined(BCM_56970_A0)
  12502     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_3_XPE0_BCM56970_A0r */
  12503         soc_block_list[124],
  12504         soc_genreg,
  12505         1,
  12506         0,
  12507         0x22000f00,
  12508         0,
  12509         0,
  12510         2,
  12511         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12513         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12514         -1,
  12515         -1,
  12516         3,
  12517     },
  12518 #endif /* chips */
  12519 
  12520 #if defined(BCM_56970_A0)
  12521     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_3_XPE1_BCM56970_A0r */
  12522         soc_block_list[124],
  12523         soc_genreg,
  12524         1,
  12525         0,
  12526         0x22000f00,
  12527         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12528         0,
  12529         2,
  12530         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12532         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12533         -1,
  12534         -1,
  12535         3,
  12536     },
  12537 #endif /* chips */
  12538 
  12539 #if defined(BCM_56970_A0)
  12540     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_3_XPE2_BCM56970_A0r */
  12541         soc_block_list[124],
  12542         soc_genreg,
  12543         1,
  12544         0,
  12545         0x22000f00,
  12546         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12547         0,
  12548         2,
  12549         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12551         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12552         -1,
  12553         -1,
  12554         3,
  12555     },
  12556 #endif /* chips */
  12557 
  12558 #if defined(BCM_56970_A0)
  12559     { /* SOC_REG_INT_WRED_POOL_INST_CONG_LIMIT_3_XPE3_BCM56970_A0r */
  12560         soc_block_list[124],
  12561         soc_genreg,
  12562         1,
  12563         0,
  12564         0x22000f00,
  12565         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12566         0,
  12567         2,
  12568         soc_WRED_POOL_INST_CONG_LIMIT_0_BCM56970_A0r_fields,
  12569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12570         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12571         -1,
  12572         -1,
  12573         3,
  12574     },
  12575 #endif /* chips */
  12576 
  12577 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12578     defined(BCM_56450_B1)
  12579     { /* SOC_REG_INT_WRED_PROFILE0_PARITY_ERROR_POINTERr */
  12580         soc_block_list[4],
  12581         soc_genreg,
  12582         1,
  12583         0,
  12584         0x5e001d00,
  12585         SOC_REG_FLAG_RO,
  12586         0,
  12587         3,
  12588         soc_WRED_PROFILE0_PARITY_ERROR_POINTERr_fields,
  12589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12590         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12591         -1,
  12592         -1,
  12593     },
  12594 #endif /* chips */
  12595 
  12596 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12597     { /* SOC_REG_INT_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r */
  12598         soc_block_list[4],
  12599         soc_genreg,
  12600         1,
  12601         0,
  12602         0x5e001d00,
  12603         SOC_REG_FLAG_RO,
  12604         0,
  12605         3,
  12606         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12608         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12609         -1,
  12610         -1,
  12611     },
  12612 #endif /* chips */
  12613 
  12614 #if defined(BCM_56270_A0)
  12615     { /* SOC_REG_INT_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56270_A0r */
  12616         soc_block_list[4],
  12617         soc_genreg,
  12618         1,
  12619         0,
  12620         0x5e001300,
  12621         SOC_REG_FLAG_RO,
  12622         0,
  12623         3,
  12624         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12626         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12627         -1,
  12628         -1,
  12629     },
  12630 #endif /* chips */
  12631 
  12632 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12633     defined(BCM_56450_B1)
  12634     { /* SOC_REG_INT_WRED_PROFILE1_PARITY_ERROR_POINTERr */
  12635         soc_block_list[4],
  12636         soc_genreg,
  12637         1,
  12638         0,
  12639         0x5e001e00,
  12640         SOC_REG_FLAG_RO,
  12641         0,
  12642         3,
  12643         soc_WRED_PROFILE0_PARITY_ERROR_POINTERr_fields,
  12644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12646         -1,
  12647         -1,
  12648     },
  12649 #endif /* chips */
  12650 
  12651 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12652     { /* SOC_REG_INT_WRED_PROFILE1_PARITY_ERROR_POINTER_BCM56260_A0r */
  12653         soc_block_list[4],
  12654         soc_genreg,
  12655         1,
  12656         0,
  12657         0x5e001e00,
  12658         SOC_REG_FLAG_RO,
  12659         0,
  12660         3,
  12661         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12663         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12664         -1,
  12665         -1,
  12666     },
  12667 #endif /* chips */
  12668 
  12669 #if defined(BCM_56270_A0)
  12670     { /* SOC_REG_INT_WRED_PROFILE1_PARITY_ERROR_POINTER_BCM56270_A0r */
  12671         soc_block_list[4],
  12672         soc_genreg,
  12673         1,
  12674         0,
  12675         0x5e001400,
  12676         SOC_REG_FLAG_RO,
  12677         0,
  12678         3,
  12679         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12681         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12682         -1,
  12683         -1,
  12684     },
  12685 #endif /* chips */
  12686 
  12687 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12688     defined(BCM_56450_B1)
  12689     { /* SOC_REG_INT_WRED_PROFILE2_PARITY_ERROR_POINTERr */
  12690         soc_block_list[4],
  12691         soc_genreg,
  12692         1,
  12693         0,
  12694         0x5e001f00,
  12695         SOC_REG_FLAG_RO,
  12696         0,
  12697         3,
  12698         soc_WRED_PROFILE0_PARITY_ERROR_POINTERr_fields,
  12699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12700         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12701         -1,
  12702         -1,
  12703     },
  12704 #endif /* chips */
  12705 
  12706 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12707     { /* SOC_REG_INT_WRED_PROFILE2_PARITY_ERROR_POINTER_BCM56260_A0r */
  12708         soc_block_list[4],
  12709         soc_genreg,
  12710         1,
  12711         0,
  12712         0x5e001f00,
  12713         SOC_REG_FLAG_RO,
  12714         0,
  12715         3,
  12716         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12718         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12719         -1,
  12720         -1,
  12721     },
  12722 #endif /* chips */
  12723 
  12724 #if defined(BCM_56270_A0)
  12725     { /* SOC_REG_INT_WRED_PROFILE2_PARITY_ERROR_POINTER_BCM56270_A0r */
  12726         soc_block_list[4],
  12727         soc_genreg,
  12728         1,
  12729         0,
  12730         0x5e001500,
  12731         SOC_REG_FLAG_RO,
  12732         0,
  12733         3,
  12734         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12736         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12737         -1,
  12738         -1,
  12739     },
  12740 #endif /* chips */
  12741 
  12742 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12743     defined(BCM_56450_B1)
  12744     { /* SOC_REG_INT_WRED_PROFILE3_PARITY_ERROR_POINTERr */
  12745         soc_block_list[4],
  12746         soc_genreg,
  12747         1,
  12748         0,
  12749         0x5e002000,
  12750         SOC_REG_FLAG_RO,
  12751         0,
  12752         3,
  12753         soc_WRED_PROFILE0_PARITY_ERROR_POINTERr_fields,
  12754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12755         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12756         -1,
  12757         -1,
  12758     },
  12759 #endif /* chips */
  12760 
  12761 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12762     { /* SOC_REG_INT_WRED_PROFILE3_PARITY_ERROR_POINTER_BCM56260_A0r */
  12763         soc_block_list[4],
  12764         soc_genreg,
  12765         1,
  12766         0,
  12767         0x5e002000,
  12768         SOC_REG_FLAG_RO,
  12769         0,
  12770         3,
  12771         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12773         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12774         -1,
  12775         -1,
  12776     },
  12777 #endif /* chips */
  12778 
  12779 #if defined(BCM_56270_A0)
  12780     { /* SOC_REG_INT_WRED_PROFILE3_PARITY_ERROR_POINTER_BCM56270_A0r */
  12781         soc_block_list[4],
  12782         soc_genreg,
  12783         1,
  12784         0,
  12785         0x5e001600,
  12786         SOC_REG_FLAG_RO,
  12787         0,
  12788         3,
  12789         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12791         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12792         -1,
  12793         -1,
  12794     },
  12795 #endif /* chips */
  12796 
  12797 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12798     defined(BCM_56450_B1)
  12799     { /* SOC_REG_INT_WRED_PROFILE4_PARITY_ERROR_POINTERr */
  12800         soc_block_list[4],
  12801         soc_genreg,
  12802         1,
  12803         0,
  12804         0x5e002100,
  12805         SOC_REG_FLAG_RO,
  12806         0,
  12807         3,
  12808         soc_WRED_PROFILE0_PARITY_ERROR_POINTERr_fields,
  12809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12810         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12811         -1,
  12812         -1,
  12813     },
  12814 #endif /* chips */
  12815 
  12816 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12817     { /* SOC_REG_INT_WRED_PROFILE4_PARITY_ERROR_POINTER_BCM56260_A0r */
  12818         soc_block_list[4],
  12819         soc_genreg,
  12820         1,
  12821         0,
  12822         0x5e002100,
  12823         SOC_REG_FLAG_RO,
  12824         0,
  12825         3,
  12826         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12828         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12829         -1,
  12830         -1,
  12831     },
  12832 #endif /* chips */
  12833 
  12834 #if defined(BCM_56270_A0)
  12835     { /* SOC_REG_INT_WRED_PROFILE4_PARITY_ERROR_POINTER_BCM56270_A0r */
  12836         soc_block_list[4],
  12837         soc_genreg,
  12838         1,
  12839         0,
  12840         0x5e001700,
  12841         SOC_REG_FLAG_RO,
  12842         0,
  12843         3,
  12844         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12846         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12847         -1,
  12848         -1,
  12849     },
  12850 #endif /* chips */
  12851 
  12852 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12853     defined(BCM_56450_B1)
  12854     { /* SOC_REG_INT_WRED_PROFILE5_PARITY_ERROR_POINTERr */
  12855         soc_block_list[4],
  12856         soc_genreg,
  12857         1,
  12858         0,
  12859         0x5e002200,
  12860         SOC_REG_FLAG_RO,
  12861         0,
  12862         3,
  12863         soc_WRED_PROFILE0_PARITY_ERROR_POINTERr_fields,
  12864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12865         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12866         -1,
  12867         -1,
  12868     },
  12869 #endif /* chips */
  12870 
  12871 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12872     { /* SOC_REG_INT_WRED_PROFILE5_PARITY_ERROR_POINTER_BCM56260_A0r */
  12873         soc_block_list[4],
  12874         soc_genreg,
  12875         1,
  12876         0,
  12877         0x5e002200,
  12878         SOC_REG_FLAG_RO,
  12879         0,
  12880         3,
  12881         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12883         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12884         -1,
  12885         -1,
  12886     },
  12887 #endif /* chips */
  12888 
  12889 #if defined(BCM_56270_A0)
  12890     { /* SOC_REG_INT_WRED_PROFILE5_PARITY_ERROR_POINTER_BCM56270_A0r */
  12891         soc_block_list[4],
  12892         soc_genreg,
  12893         1,
  12894         0,
  12895         0x5e001800,
  12896         SOC_REG_FLAG_RO,
  12897         0,
  12898         3,
  12899         soc_WRED_PROFILE0_PARITY_ERROR_POINTER_BCM56260_A0r_fields,
  12900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12901         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12902         -1,
  12903         -1,
  12904     },
  12905 #endif /* chips */
  12906 
  12907 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12908     defined(BCM_56450_B1)
  12909     { /* SOC_REG_INT_WRED_PROFILE_PARITY_ERROR_BITMAPr */
  12910         soc_block_list[4],
  12911         soc_genreg,
  12912         1,
  12913         0,
  12914         0x5e001c00,
  12915         0,
  12916         0,
  12917         2,
  12918         soc_WRED_PROFILE_PARITY_ERROR_BITMAPr_fields,
  12919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12920         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12921         -1,
  12922         -1,
  12923     },
  12924 #endif /* chips */
  12925 
  12926 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12927     { /* SOC_REG_INT_WRED_PROFILE_PARITY_ERROR_BITMAP_BCM56260_A0r */
  12928         soc_block_list[4],
  12929         soc_genreg,
  12930         1,
  12931         0,
  12932         0x5e001c00,
  12933         0,
  12934         0,
  12935         2,
  12936         soc_WRED_PROFILE_PARITY_ERROR_BITMAP_BCM56260_A0r_fields,
  12937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12938         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12939         -1,
  12940         -1,
  12941     },
  12942 #endif /* chips */
  12943 
  12944 #if defined(BCM_56270_A0)
  12945     { /* SOC_REG_INT_WRED_PROFILE_PARITY_ERROR_BITMAP_BCM56270_A0r */
  12946         soc_block_list[4],
  12947         soc_genreg,
  12948         1,
  12949         0,
  12950         0x5e001200,
  12951         0,
  12952         0,
  12953         2,
  12954         soc_WRED_PROFILE_PARITY_ERROR_BITMAP_BCM56260_A0r_fields,
  12955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12956         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12957         -1,
  12958         -1,
  12959     },
  12960 #endif /* chips */
  12961 
  12962 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12963     defined(BCM_56450_B1)
  12964     { /* SOC_REG_INT_WRED_PROFILE_PARITY_ERROR_MASKr */
  12965         soc_block_list[4],
  12966         soc_genreg,
  12967         1,
  12968         0,
  12969         0x5e001b00,
  12970         0,
  12971         0,
  12972         2,
  12973         soc_WRED_PROFILE_PARITY_ERROR_MASKr_fields,
  12974         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  12975         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12976         -1,
  12977         -1,
  12978     },
  12979 #endif /* chips */
  12980 
  12981 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12982     { /* SOC_REG_INT_WRED_PROFILE_PARITY_ERROR_MASK_BCM56260_A0r */
  12983         soc_block_list[4],
  12984         soc_genreg,
  12985         1,
  12986         0,
  12987         0x5e001b00,
  12988         0,
  12989         0,
  12990         2,
  12991         soc_WRED_PROFILE_PARITY_ERROR_MASK_BCM56260_A0r_fields,
  12992         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  12993         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  12994         -1,
  12995         -1,
  12996     },
  12997 #endif /* chips */
  12998 
  12999 #if defined(BCM_56270_A0)
  13000     { /* SOC_REG_INT_WRED_PROFILE_PARITY_ERROR_MASK_BCM56270_A0r */
  13001         soc_block_list[4],
  13002         soc_genreg,
  13003         1,
  13004         0,
  13005         0x5e001100,
  13006         0,
  13007         0,
  13008         2,
  13009         soc_WRED_PROFILE_PARITY_ERROR_MASK_BCM56260_A0r_fields,
  13010         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  13011         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13012         -1,
  13013         -1,
  13014     },
  13015 #endif /* chips */
  13016 
  13017 #if defined(BCM_53570_A0)
  13018     { /* SOC_REG_INT_WRED_QGROUP_THD_READ_CONTROLr */
  13019         soc_block_list[4],
  13020         soc_genreg,
  13021         1,
  13022         0,
  13023         0x20e7600,
  13024         0,
  13025         0,
  13026         3,
  13027         soc_WRED_QGROUP_THD_READ_CONTROLr_fields,
  13028         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  13029         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13030         -1,
  13031         -1,
  13032     },
  13033 #endif /* chips */
  13034 
  13035 #if defined(BCM_53570_B0)
  13036     { /* SOC_REG_INT_WRED_QGROUP_THD_READ_CONTROL_BCM53570_B0r */
  13037         soc_block_list[4],
  13038         soc_genreg,
  13039         1,
  13040         0,
  13041         0x20e7900,
  13042         0,
  13043         0,
  13044         3,
  13045         soc_WRED_QGROUP_THD_READ_CONTROLr_fields,
  13046         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  13047         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13048         -1,
  13049         -1,
  13050     },
  13051 #endif /* chips */
  13052 
  13053 #if defined(BCM_53570_A0)
  13054     { /* SOC_REG_INT_WRED_QGROUP_THD_READ_DATAr */
  13055         soc_block_list[4],
  13056         soc_genreg,
  13057         1,
  13058         0,
  13059         0x20e7e00,
  13060         SOC_REG_FLAG_RO,
  13061         0,
  13062         4,
  13063         soc_WRED_DROP_THD_READ_DATAr_fields,
  13064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13065         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  13066         -1,
  13067         -1,
  13068     },
  13069 #endif /* chips */
  13070 
  13071 #if defined(BCM_53570_B0)
  13072     { /* SOC_REG_INT_WRED_QGROUP_THD_READ_DATA_BCM53570_B0r */
  13073         soc_block_list[4],
  13074         soc_genreg,
  13075         1,
  13076         0,
  13077         0x20e8100,
  13078         SOC_REG_FLAG_RO,
  13079         0,
  13080         4,
  13081         soc_WRED_DROP_THD_READ_DATAr_fields,
  13082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13083         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  13084         -1,
  13085         -1,
  13086     },
  13087 #endif /* chips */
  13088 
  13089 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  13090     { /* SOC_REG_INT_WRED_REFRESH_CONTROLr */
  13091         soc_block_list[4],
  13092         soc_genreg,
  13093         1,
  13094         0,
  13095         0x56000100,
  13096         0,
  13097         0,
  13098         2,
  13099         soc_WRED_REFRESH_CONTROLr_fields,
  13100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13101         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  13102         -1,
  13103         -1,
  13104     },
  13105 #endif /* chips */
  13106 
  13107 #if defined(BCM_53400_A0) || defined(BCM_56160_A0)
  13108     { /* SOC_REG_INT_WRED_REFRESH_CONTROL_BCM53400_A0r */
  13109         soc_block_list[4],
  13110         soc_genreg,
  13111         1,
  13112         0,
  13113         0x2160100,
  13114         0,
  13115         0,
  13116         2,
  13117         soc_WRED_REFRESH_CONTROL_BCM53400_A0r_fields,
  13118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13119         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  13120         -1,
  13121         -1,
  13122     },
  13123 #endif /* chips */
  13124 
  13125 #if defined(BCM_53540_A0)
  13126     { /* SOC_REG_INT_WRED_REFRESH_CONTROL_BCM53540_A0r */
  13127         soc_block_list[4],
  13128         soc_genreg,
  13129         1,
  13130         0,
  13131         0x207b000,
  13132         0,
  13133         0,
  13134         2,
  13135         soc_WRED_REFRESH_CONTROL_BCM53400_A0r_fields,
  13136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13137         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  13138         -1,
  13139         -1,
  13140     },
  13141 #endif /* chips */
  13142 
  13143 #if defined(BCM_53570_A0)
  13144     { /* SOC_REG_INT_WRED_REFRESH_CONTROL_BCM53570_A0r */
  13145         soc_block_list[4],
  13146         soc_genreg,
  13147         1,
  13148         0,
  13149         0x20e1e00,
  13150         0,
  13151         0,
  13152         2,
  13153         soc_WRED_REFRESH_CONTROL_BCM53400_A0r_fields,
  13154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13155         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  13156         -1,
  13157         -1,
  13158     },
  13159 #endif /* chips */
  13160 
  13161 #if defined(BCM_53570_B0)
  13162     { /* SOC_REG_INT_WRED_REFRESH_CONTROL_BCM53570_B0r */
  13163         soc_block_list[4],
  13164         soc_genreg,
  13165         1,
  13166         0,
  13167         0x20e2100,
  13168         0,
  13169         0,
  13170         2,
  13171         soc_WRED_REFRESH_CONTROL_BCM53400_A0r_fields,
  13172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13173         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  13174         -1,
  13175         -1,
  13176     },
  13177 #endif /* chips */
  13178 
  13179 #if defined(BCM_56370_A0)
  13180     { /* SOC_REG_INT_WRED_REFRESH_CONTROL_BCM56370_A0r */
  13181         soc_block_list[124],
  13182         soc_genreg,
  13183         1,
  13184         0,
  13185         0x22000600,
  13186         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13187         0,
  13188         3,
  13189         soc_WRED_REFRESH_CONTROL_BCM56370_A0r_fields,
  13190         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  13191         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13192         -1,
  13193         -1,
  13194         3,
  13195     },
  13196 #endif /* chips */
  13197 
  13198 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  13199     { /* SOC_REG_INT_WRED_REFRESH_CONTROL_BCM56560_A0r */
  13200         soc_block_list[4],
  13201         soc_genreg,
  13202         1,
  13203         0,
  13204         0x76000100,
  13205         0,
  13206         0,
  13207         4,
  13208         soc_WRED_REFRESH_CONTROL_BCM56560_A0r_fields,
  13209         SOC_RESET_VAL_DEC(0x000049f0, 0x00000000)
  13210         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  13211         -1,
  13212         -1,
  13213     },
  13214 #endif /* chips */
  13215 
  13216 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13217     { /* SOC_REG_INT_WRED_REFRESH_CONTROL_BCM56670_A0r */
  13218         soc_block_list[4],
  13219         soc_genreg,
  13220         1,
  13221         0,
  13222         0x76000100,
  13223         0,
  13224         0,
  13225         4,
  13226         soc_WRED_REFRESH_CONTROL_BCM56670_A0r_fields,
  13227         SOC_RESET_VAL_DEC(0x00004240, 0x00000000)
  13228         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  13229         -1,
  13230         -1,
  13231     },
  13232 #endif /* chips */
  13233 
  13234 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  13235     { /* SOC_REG_INT_WRED_REFRESH_CONTROL_BCM56850_A0r */
  13236         soc_block_list[4],
  13237         soc_genreg,
  13238         1,
  13239         0,
  13240         0x76000100,
  13241         0,
  13242         0,
  13243         2,
  13244         soc_WRED_REFRESH_CONTROLr_fields,
  13245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13246         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  13247         -1,
  13248         -1,
  13249     },
  13250 #endif /* chips */
  13251 
  13252 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13253     { /* SOC_REG_INT_WRED_REFRESH_CONTROL_BCM56960_A0r */
  13254         soc_block_list[124],
  13255         soc_genreg,
  13256         1,
  13257         0,
  13258         0x22000600,
  13259         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13260         0,
  13261         2,
  13262         soc_WRED_REFRESH_CONTROL_BCM56960_A0r_fields,
  13263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13264         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  13265         -1,
  13266         -1,
  13267         3,
  13268     },
  13269 #endif /* chips */
  13270 
  13271 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13272     defined(BCM_56970_A0)
  13273     { /* SOC_REG_INT_WRED_REFRESH_CONTROL_BCM56970_A0r */
  13274         soc_block_list[124],
  13275         soc_genreg,
  13276         1,
  13277         0,
  13278         0x22000600,
  13279         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13280         0,
  13281         2,
  13282         soc_WRED_REFRESH_CONTROL_BCM56970_A0r_fields,
  13283         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  13284         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  13285         -1,
  13286         -1,
  13287         3,
  13288     },
  13289 #endif /* chips */
  13290 
  13291 #if defined(BCM_53400_A0)
  13292     { /* SOC_REG_INT_WRED_REFRESH_PORT_CONTROLr */
  13293         soc_block_list[4],
  13294         soc_genreg,
  13295         1,
  13296         0,
  13297         0x2160200,
  13298         0,
  13299         0,
  13300         2,
  13301         soc_WRED_REFRESH_PORT_CONTROLr_fields,
  13302         SOC_RESET_VAL_DEC(0x3ffffffc, 0x00000000)
  13303         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  13304         -1,
  13305         -1,
  13306     },
  13307 #endif /* chips */
  13308 
  13309 #if defined(BCM_53570_A0)
  13310     { /* SOC_REG_INT_WRED_REFRESH_PORT_CONTROL_0r */
  13311         soc_block_list[4],
  13312         soc_genreg,
  13313         1,
  13314         0,
  13315         0x20e2600,
  13316         0,
  13317         0,
  13318         1,
  13319         soc_WRED_REFRESH_PORT_CONTROL_0r_fields,
  13320         SOC_RESET_VAL_DEC(0xfffffffc, 0x00000000)
  13321         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13322         -1,
  13323         -1,
  13324     },
  13325 #endif /* chips */
  13326 
  13327 #if defined(BCM_53570_A0)
  13328     { /* SOC_REG_INT_WRED_REFRESH_PORT_CONTROL_1r */
  13329         soc_block_list[4],
  13330         soc_genreg,
  13331         1,
  13332         0,
  13333         0x20e2e00,
  13334         0,
  13335         0,
  13336         1,
  13337         soc_WRED_REFRESH_PORT_CONTROL_1r_fields,
  13338         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  13339         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13340         -1,
  13341         -1,
  13342     },
  13343 #endif /* chips */
  13344 
  13345 #if defined(BCM_53570_A0)
  13346     { /* SOC_REG_INT_WRED_REFRESH_PORT_CONTROL_2r */
  13347         soc_block_list[4],
  13348         soc_genreg,
  13349         1,
  13350         0,
  13351         0x20e3600,
  13352         0,
  13353         0,
  13354         1,
  13355         soc_WRED_REFRESH_PORT_CONTROL_2r_fields,
  13356         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  13357         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13358         -1,
  13359         -1,
  13360     },
  13361 #endif /* chips */
  13362 
  13363 #if defined(BCM_53570_B0)
  13364     { /* SOC_REG_INT_WRED_REFRESH_PORT_CONTROL_0_BCM53570_B0r */
  13365         soc_block_list[4],
  13366         soc_genreg,
  13367         1,
  13368         0,
  13369         0x20e2900,
  13370         0,
  13371         0,
  13372         1,
  13373         soc_WRED_REFRESH_PORT_CONTROL_0r_fields,
  13374         SOC_RESET_VAL_DEC(0xfffffffc, 0x00000000)
  13375         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13376         -1,
  13377         -1,
  13378     },
  13379 #endif /* chips */
  13380 
  13381 #if defined(BCM_53570_B0)
  13382     { /* SOC_REG_INT_WRED_REFRESH_PORT_CONTROL_1_BCM53570_B0r */
  13383         soc_block_list[4],
  13384         soc_genreg,
  13385         1,
  13386         0,
  13387         0x20e3100,
  13388         0,
  13389         0,
  13390         1,
  13391         soc_WRED_REFRESH_PORT_CONTROL_1r_fields,
  13392         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  13393         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13394         -1,
  13395         -1,
  13396     },
  13397 #endif /* chips */
  13398 
  13399 #if defined(BCM_53570_B0)
  13400     { /* SOC_REG_INT_WRED_REFRESH_PORT_CONTROL_2_BCM53570_B0r */
  13401         soc_block_list[4],
  13402         soc_genreg,
  13403         1,
  13404         0,
  13405         0x20e3900,
  13406         0,
  13407         0,
  13408         1,
  13409         soc_WRED_REFRESH_PORT_CONTROL_2r_fields,
  13410         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  13411         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13412         -1,
  13413         -1,
  13414     },
  13415 #endif /* chips */
  13416 
  13417 #if defined(BCM_53540_A0)
  13418     { /* SOC_REG_INT_WRED_REFRESH_PORT_CONTROL_BCM53540_A0r */
  13419         soc_block_list[4],
  13420         soc_genreg,
  13421         1,
  13422         0,
  13423         0x207b800,
  13424         0,
  13425         0,
  13426         2,
  13427         soc_WRED_REFRESH_PORT_CONTROL_BCM56160_A0r_fields,
  13428         SOC_RESET_VAL_DEC(0xfffffffc, 0x00000000)
  13429         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13430         -1,
  13431         -1,
  13432     },
  13433 #endif /* chips */
  13434 
  13435 #if defined(BCM_56160_A0)
  13436     { /* SOC_REG_INT_WRED_REFRESH_PORT_CONTROL_BCM56160_A0r */
  13437         soc_block_list[4],
  13438         soc_genreg,
  13439         1,
  13440         0,
  13441         0x2160200,
  13442         0,
  13443         0,
  13444         2,
  13445         soc_WRED_REFRESH_PORT_CONTROL_BCM56160_A0r_fields,
  13446         SOC_RESET_VAL_DEC(0xfffffffc, 0x00000000)
  13447         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13448         -1,
  13449         -1,
  13450     },
  13451 #endif /* chips */
  13452 
  13453 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  13454     { /* SOC_REG_INT_WRED_REFRESH_TICK_ERROR_STATUSr */
  13455         soc_block_list[4],
  13456         soc_genreg,
  13457         1,
  13458         0,
  13459         0x760c1900,
  13460         0,
  13461         0,
  13462         1,
  13463         soc_WRED_REFRESH_TICK_ERROR_STATUSr_fields,
  13464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13465         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  13466         -1,
  13467         -1,
  13468     },
  13469 #endif /* chips */
  13470 
  13471 #if defined(BCM_56370_A0)
  13472     { /* SOC_REG_INT_WRED_REFRESH_TICK_ERROR_STATUS_BCM56370_A0r */
  13473         soc_block_list[124],
  13474         soc_xpereg,
  13475         1,
  13476         0,
  13477         0x22801c00,
  13478         SOC_REG_FLAG_RO |
  13479                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13480         0,
  13481         1,
  13482         soc_WRED_REFRESH_TICK_ERROR_STATUS_BCM56370_A0r_fields,
  13483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13484         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13485         -1,
  13486         -1,
  13487         3,
  13488     },
  13489 #endif /* chips */
  13490 
  13491 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13492     { /* SOC_REG_INT_WRED_REFRESH_TICK_ERROR_STATUS_BCM56670_A0r */
  13493         soc_block_list[4],
  13494         soc_genreg,
  13495         1,
  13496         0,
  13497         0x760c1900,
  13498         0,
  13499         0,
  13500         1,
  13501         soc_WRED_REFRESH_TICK_ERROR_STATUS_BCM56670_A0r_fields,
  13502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13503         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13504         -1,
  13505         -1,
  13506     },
  13507 #endif /* chips */
  13508 
  13509 #if defined(BCM_88732_A0)
  13510     { /* SOC_REG_INT_WRED_THD_0_ECCPr */
  13511         soc_block_list[4],
  13512         soc_portreg,
  13513         8,
  13514         0,
  13515         0x120004c0,
  13516         SOC_REG_FLAG_ARRAY,
  13517         0,
  13518         1,
  13519         soc_BUCKET_ECCr_fields,
  13520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13521         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13522         -1,
  13523         50,
  13524     },
  13525 #endif /* chips */
  13526 
  13527 #if defined(BCM_88732_A0)
  13528     { /* SOC_REG_INT_WRED_THD_1_ECCPr */
  13529         soc_block_list[4],
  13530         soc_portreg,
  13531         8,
  13532         0,
  13533         0x12000500,
  13534         SOC_REG_FLAG_ARRAY,
  13535         0,
  13536         1,
  13537         soc_BUCKET_ECCr_fields,
  13538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13539         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13540         -1,
  13541         50,
  13542     },
  13543 #endif /* chips */
  13544 
  13545 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  13546     defined(BCM_56504_B0)
  13547     { /* SOC_REG_INT_WRRWEIGHTSr */
  13548         soc_block_list[4],
  13549         soc_portreg,
  13550         1,
  13551         0,
  13552         0x46,
  13553         0,
  13554         0,
  13555         8,
  13556         soc_WRRWEIGHTSr_fields,
  13557         SOC_RESET_VAL_DEC(0x87654321, 0x00000000)
  13558         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13559         -1,
  13560         -1,
  13561     },
  13562 #endif /* chips */
  13563 
  13564 #if defined(BCM_56514_A0)
  13565     { /* SOC_REG_INT_WRRWEIGHT_COSr */
  13566         soc_block_list[4],
  13567         soc_portreg,
  13568         8,
  13569         0,
  13570         0x80,
  13571         SOC_REG_FLAG_ARRAY,
  13572         0,
  13573         2,
  13574         soc_WRRWEIGHT_COSr_fields,
  13575         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  13576         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13577         -1,
  13578         -1,
  13579     },
  13580 #endif /* chips */
  13581 
  13582 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  13583     { /* SOC_REG_INT_WRRWEIGHT_COS_BCM53314_A0r */
  13584         soc_block_list[4],
  13585         soc_portreg,
  13586         4,
  13587         0,
  13588         0x62,
  13589         SOC_REG_FLAG_ARRAY,
  13590         0,
  13591         2,
  13592         soc_WRRWEIGHT_COS_BCM56224_A0r_fields,
  13593         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13594         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13595         -1,
  13596         -1,
  13597     },
  13598 #endif /* chips */
  13599 
  13600 #if defined(BCM_53400_A0)
  13601     { /* SOC_REG_INT_WRRWEIGHT_COS_BCM53400_A0r */
  13602         soc_block_list[4],
  13603         soc_portreg,
  13604         8,
  13605         0,
  13606         0x13300,
  13607         SOC_REG_FLAG_ARRAY,
  13608         0,
  13609         2,
  13610         soc_WRRWEIGHT_COS_BCM53400_A0r_fields,
  13611         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13612         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13613         -1,
  13614         79,
  13615     },
  13616 #endif /* chips */
  13617 
  13618 #if defined(BCM_53540_A0)
  13619     { /* SOC_REG_INT_WRRWEIGHT_COS_BCM53540_A0r */
  13620         soc_block_list[4],
  13621         soc_portreg,
  13622         8,
  13623         0,
  13624         0x1b000,
  13625         SOC_REG_FLAG_ARRAY,
  13626         0,
  13627         2,
  13628         soc_WRRWEIGHT_COS_BCM53400_A0r_fields,
  13629         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13630         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13631         -1,
  13632         91,
  13633     },
  13634 #endif /* chips */
  13635 
  13636 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  13637     { /* SOC_REG_INT_WRRWEIGHT_COS_BCM53570_A0r */
  13638         soc_block_list[4],
  13639         soc_portreg,
  13640         8,
  13641         0,
  13642         0x1c800,
  13643         SOC_REG_FLAG_ARRAY,
  13644         0,
  13645         2,
  13646         soc_WRRWEIGHT_COS_BCM53400_A0r_fields,
  13647         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13648         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13649         -1,
  13650         102,
  13651     },
  13652 #endif /* chips */
  13653 
  13654 #if defined(BCM_56142_A0)
  13655     { /* SOC_REG_INT_WRRWEIGHT_COS_BCM56142_A0r */
  13656         soc_block_list[4],
  13657         soc_portreg,
  13658         8,
  13659         0,
  13660         0x133,
  13661         SOC_REG_FLAG_ARRAY,
  13662         0,
  13663         2,
  13664         soc_WRRWEIGHT_COS_BCM56224_A0r_fields,
  13665         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13666         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13667         -1,
  13668         -1,
  13669     },
  13670 #endif /* chips */
  13671 
  13672 #if defined(BCM_56150_A0)
  13673     { /* SOC_REG_INT_WRRWEIGHT_COS_BCM56150_A0r */
  13674         soc_block_list[4],
  13675         soc_portreg,
  13676         8,
  13677         0,
  13678         0x13300,
  13679         SOC_REG_FLAG_ARRAY,
  13680         0,
  13681         2,
  13682         soc_WRRWEIGHT_COS_BCM56150_A0r_fields,
  13683         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13684         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13685         -1,
  13686         79,
  13687     },
  13688 #endif /* chips */
  13689 
  13690 #if defined(BCM_56160_A0)
  13691     { /* SOC_REG_INT_WRRWEIGHT_COS_BCM56160_A0r */
  13692         soc_block_list[4],
  13693         soc_portreg,
  13694         8,
  13695         0,
  13696         0x13300,
  13697         SOC_REG_FLAG_ARRAY,
  13698         0,
  13699         2,
  13700         soc_WRRWEIGHT_COS_BCM53400_A0r_fields,
  13701         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13702         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13703         -1,
  13704         91,
  13705     },
  13706 #endif /* chips */
  13707 
  13708 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  13709     { /* SOC_REG_INT_WRRWEIGHT_COS_BCM56224_A0r */
  13710         soc_block_list[4],
  13711         soc_portreg,
  13712         8,
  13713         0,
  13714         0x62,
  13715         SOC_REG_FLAG_ARRAY,
  13716         0,
  13717         2,
  13718         soc_WRRWEIGHT_COS_BCM56224_A0r_fields,
  13719         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13720         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13721         -1,
  13722         -1,
  13723     },
  13724 #endif /* chips */
  13725 
  13726 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  13727     { /* SOC_REG_INT_WRRWEIGHT_COS_QGROUPr */
  13728         soc_block_list[4],
  13729         soc_portreg,
  13730         8,
  13731         0,
  13732         0x22800,
  13733         SOC_REG_FLAG_ARRAY,
  13734         0,
  13735         2,
  13736         soc_WRRWEIGHT_COS_BCM53400_A0r_fields,
  13737         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13738         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13739         -1,
  13740         99,
  13741     },
  13742 #endif /* chips */
  13743 
  13744 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  13745     { /* SOC_REG_INT_WRRWEIGHT_COS_QLAYERr */
  13746         soc_block_list[4],
  13747         soc_portreg,
  13748         64,
  13749         0,
  13750         0x1e800,
  13751         SOC_REG_FLAG_ARRAY,
  13752         0,
  13753         2,
  13754         soc_WRRWEIGHT_COS_BCM53400_A0r_fields,
  13755         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  13756         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  13757         -1,
  13758         99,
  13759     },
  13760 #endif /* chips */
  13761