allregs_v.i - openbcm - Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM

allregs_v.i (590658B)
      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_v.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
     16     { /* SOC_REG_INT_VBS_FC_CONFIGr */
     17         soc_block_list[4],
     18         soc_genreg,
     19         1,
     20         0,
     21         0x96080b00,
     22         0,
     23         0,
     24         4,
     25         soc_VBS_FC_CONFIGr_fields,
     26         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
     27         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
     28         -1,
     29         -1,
     30     },
     31 #endif /* chips */
     32 
     33 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
     34     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
     35     defined(BCM_56685_A0) || defined(BCM_56685_B0)
     36     { /* SOC_REG_INT_VFI_1_PARITY_CONTROLr */
     37         soc_block_list[5],
     38         soc_genreg,
     39         1,
     40         0,
     41         0x5080172,
     42         0,
     43         0,
     44         1,
     45         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
     46         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     47         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
     48         -1,
     49         -1,
     50     },
     51 #endif /* chips */
     52 
     53 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
     54     defined(BCM_56270_A0)
     55     { /* SOC_REG_INT_VFI_1_PARITY_CONTROL_BCM56260_A0r */
     56         soc_block_list[5],
     57         soc_genreg,
     58         1,
     59         0,
     60         0x16011900,
     61         0,
     62         0,
     63         1,
     64         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
     65         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     66         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
     67         -1,
     68         -1,
     69     },
     70 #endif /* chips */
     71 
     72 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
     73     { /* SOC_REG_INT_VFI_1_PARITY_CONTROL_BCM56334_A0r */
     74         soc_block_list[5],
     75         soc_genreg,
     76         1,
     77         0,
     78         0x6080147,
     79         0,
     80         0,
     81         1,
     82         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
     83         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     84         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
     85         -1,
     86         -1,
     87     },
     88 #endif /* chips */
     89 
     90 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
     91     defined(BCM_56450_B1)
     92     { /* SOC_REG_INT_VFI_1_PARITY_CONTROL_BCM56450_A0r */
     93         soc_block_list[5],
     94         soc_genreg,
     95         1,
     96         0,
     97         0x16011800,
     98         0,
     99         0,
    100         1,
    101         soc_FT_CNTR_SER_CONTROLr_fields,
    102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    103         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    104         -1,
    105         -1,
    106     },
    107 #endif /* chips */
    108 
    109 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
    110     defined(BCM_56670_A0) || defined(BCM_56670_B0)
    111     { /* SOC_REG_INT_VFI_1_PARITY_CONTROL_BCM56560_A0r */
    112         soc_block_list[5],
    113         soc_genreg,
    114         1,
    115         0,
    116         0x630b0000,
    117         0,
    118         0,
    119         1,
    120         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
    121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    122         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    123         -1,
    124         -1,
    125     },
    126 #endif /* chips */
    127 
    128 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
    129     defined(BCM_56840_A0) || defined(BCM_56840_B0)
    130     { /* SOC_REG_INT_VFI_1_PARITY_CONTROL_BCM56840_A0r */
    131         soc_block_list[5],
    132         soc_genreg,
    133         1,
    134         0,
    135         0x5080d18,
    136         0,
    137         0,
    138         1,
    139         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
    140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    141         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    142         -1,
    143         -1,
    144     },
    145 #endif /* chips */
    146 
    147 #if defined(BCM_56850_A0)
    148     { /* SOC_REG_INT_VFI_1_PARITY_CONTROL_BCM56850_A0r */
    149         soc_block_list[5],
    150         soc_genreg,
    151         1,
    152         0,
    153         0x530c0000,
    154         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    155         0,
    156         1,
    157         soc_FT_CNTR_SER_CONTROLr_fields,
    158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    159         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    160         -1,
    161         -1,
    162     },
    163 #endif /* chips */
    164 
    165 #if defined(BCM_56860_A0)
    166     { /* SOC_REG_INT_VFI_1_PARITY_CONTROL_BCM56860_A0r */
    167         soc_block_list[5],
    168         soc_genreg,
    169         1,
    170         0,
    171         0x630b0000,
    172         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    173         0,
    174         1,
    175         soc_FT_CNTR_SER_CONTROLr_fields,
    176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    177         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    178         -1,
    179         -1,
    180     },
    181 #endif /* chips */
    182 
    183 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    184     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    185     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    186     { /* SOC_REG_INT_VFI_1_PARITY_STATUS_INTRr */
    187         soc_block_list[5],
    188         soc_genreg,
    189         1,
    190         0,
    191         0x5080173,
    192         0,
    193         0,
    194         3,
    195         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
    196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    197         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    198         -1,
    199         -1,
    200     },
    201 #endif /* chips */
    202 
    203 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
    204     { /* SOC_REG_INT_VFI_1_PARITY_STATUS_INTR_BCM56334_A0r */
    205         soc_block_list[5],
    206         soc_genreg,
    207         1,
    208         0,
    209         0x6080148,
    210         0,
    211         0,
    212         3,
    213         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
    214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    215         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    216         -1,
    217         -1,
    218     },
    219 #endif /* chips */
    220 
    221 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    222     { /* SOC_REG_INT_VFI_1_PARITY_STATUS_INTR_BCM56440_A0r */
    223         soc_block_list[5],
    224         soc_genreg,
    225         1,
    226         0,
    227         0x5080d19,
    228         0,
    229         0,
    230         3,
    231         soc_CPB_PARITY_STATUS_INTRr_fields,
    232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    233         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    234         -1,
    235         -1,
    236     },
    237 #endif /* chips */
    238 
    239 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    240     defined(BCM_56450_B1)
    241     { /* SOC_REG_INT_VFI_1_PARITY_STATUS_INTR_BCM56450_A0r */
    242         soc_block_list[5],
    243         soc_genreg,
    244         1,
    245         0,
    246         0x16011900,
    247         0,
    248         0,
    249         3,
    250         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
    251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    252         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    253         -1,
    254         -1,
    255     },
    256 #endif /* chips */
    257 
    258 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
    259     { /* SOC_REG_INT_VFI_1_PARITY_STATUS_INTR_BCM56840_A0r */
    260         soc_block_list[5],
    261         soc_genreg,
    262         1,
    263         0,
    264         0x5080d19,
    265         0,
    266         0,
    267         3,
    268         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
    269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    270         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    271         -1,
    272         -1,
    273     },
    274 #endif /* chips */
    275 
    276 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    277     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    278     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    279     { /* SOC_REG_INT_VFI_1_PARITY_STATUS_NACKr */
    280         soc_block_list[5],
    281         soc_genreg,
    282         1,
    283         0,
    284         0x5080174,
    285         0,
    286         0,
    287         3,
    288         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
    289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    290         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    291         -1,
    292         -1,
    293     },
    294 #endif /* chips */
    295 
    296 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    297     { /* SOC_REG_INT_VFI_1_PARITY_STATUS_NACK_BCM56440_A0r */
    298         soc_block_list[5],
    299         soc_genreg,
    300         1,
    301         0,
    302         0x5080d1a,
    303         0,
    304         0,
    305         3,
    306         soc_CPB_PARITY_STATUS_INTRr_fields,
    307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    308         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    309         -1,
    310         -1,
    311     },
    312 #endif /* chips */
    313 
    314 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    315     defined(BCM_56450_B1)
    316     { /* SOC_REG_INT_VFI_1_PARITY_STATUS_NACK_BCM56450_A0r */
    317         soc_block_list[5],
    318         soc_genreg,
    319         1,
    320         0,
    321         0x16011a00,
    322         0,
    323         0,
    324         3,
    325         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
    326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    327         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    328         -1,
    329         -1,
    330     },
    331 #endif /* chips */
    332 
    333 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
    334     { /* SOC_REG_INT_VFI_1_PARITY_STATUS_NACK_BCM56840_A0r */
    335         soc_block_list[5],
    336         soc_genreg,
    337         1,
    338         0,
    339         0x5080d1a,
    340         0,
    341         0,
    342         3,
    343         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
    344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    345         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    346         -1,
    347         -1,
    348     },
    349 #endif /* chips */
    350 
    351 #if defined(BCM_53570_B0)
    352     { /* SOC_REG_INT_VFI_DBGCTRLr */
    353         soc_block_list[5],
    354         soc_genreg,
    355         1,
    356         0,
    357         0x12010a00,
    358         0,
    359         0,
    360         1,
    361         soc_DSCP_CONTROLr_fields,
    362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    363         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    364         -1,
    365         -1,
    366     },
    367 #endif /* chips */
    368 
    369 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
    370     defined(BCM_56270_A0)
    371     { /* SOC_REG_INT_VFI_ECC_CONTROLr */
    372         soc_block_list[5],
    373         soc_genreg,
    374         1,
    375         0,
    376         0x16011600,
    377         0,
    378         0,
    379         2,
    380         soc_EGR_MASK_ECC_CONTROLr_fields,
    381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    382         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    383         -1,
    384         -1,
    385     },
    386 #endif /* chips */
    387 
    388 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    389     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    390     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    391     { /* SOC_REG_INT_VFI_PARITY_CONTROLr */
    392         soc_block_list[5],
    393         soc_genreg,
    394         1,
    395         0,
    396         0x508016f,
    397         0,
    398         0,
    399         1,
    400         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
    401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    402         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    403         -1,
    404         -1,
    405     },
    406 #endif /* chips */
    407 
    408 #if defined(BCM_53570_B0)
    409     { /* SOC_REG_INT_VFI_PARITY_CONTROL_BCM53570_B0r */
    410         soc_block_list[5],
    411         soc_genreg,
    412         1,
    413         0,
    414         0x12011100,
    415         0,
    416         0,
    417         1,
    418         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
    419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    420         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    421         -1,
    422         -1,
    423     },
    424 #endif /* chips */
    425 
    426 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
    427     { /* SOC_REG_INT_VFI_PARITY_CONTROL_BCM56334_A0r */
    428         soc_block_list[5],
    429         soc_genreg,
    430         1,
    431         0,
    432         0x6080144,
    433         0,
    434         0,
    435         1,
    436         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
    437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    438         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    439         -1,
    440         -1,
    441     },
    442 #endif /* chips */
    443 
    444 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    445     defined(BCM_56450_B1)
    446     { /* SOC_REG_INT_VFI_PARITY_CONTROL_BCM56450_A0r */
    447         soc_block_list[5],
    448         soc_genreg,
    449         1,
    450         0,
    451         0x16011500,
    452         0,
    453         0,
    454         1,
    455         soc_FT_CNTR_SER_CONTROLr_fields,
    456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    457         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    458         -1,
    459         -1,
    460     },
    461 #endif /* chips */
    462 
    463 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
    464     defined(BCM_56670_A0) || defined(BCM_56670_B0)
    465     { /* SOC_REG_INT_VFI_PARITY_CONTROL_BCM56560_A0r */
    466         soc_block_list[5],
    467         soc_genreg,
    468         1,
    469         0,
    470         0x630a0000,
    471         0,
    472         0,
    473         1,
    474         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
    475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    476         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    477         -1,
    478         -1,
    479     },
    480 #endif /* chips */
    481 
    482 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
    483     defined(BCM_56840_A0) || defined(BCM_56840_B0)
    484     { /* SOC_REG_INT_VFI_PARITY_CONTROL_BCM56840_A0r */
    485         soc_block_list[5],
    486         soc_genreg,
    487         1,
    488         0,
    489         0x5080d15,
    490         0,
    491         0,
    492         1,
    493         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
    494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    495         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    496         -1,
    497         -1,
    498     },
    499 #endif /* chips */
    500 
    501 #if defined(BCM_56850_A0)
    502     { /* SOC_REG_INT_VFI_PARITY_CONTROL_BCM56850_A0r */
    503         soc_block_list[5],
    504         soc_genreg,
    505         1,
    506         0,
    507         0x530b0000,
    508         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    509         0,
    510         1,
    511         soc_FT_CNTR_SER_CONTROLr_fields,
    512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    514         -1,
    515         -1,
    516     },
    517 #endif /* chips */
    518 
    519 #if defined(BCM_56860_A0)
    520     { /* SOC_REG_INT_VFI_PARITY_CONTROL_BCM56860_A0r */
    521         soc_block_list[5],
    522         soc_genreg,
    523         1,
    524         0,
    525         0x630a0000,
    526         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    527         0,
    528         1,
    529         soc_FT_CNTR_SER_CONTROLr_fields,
    530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    531         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    532         -1,
    533         -1,
    534     },
    535 #endif /* chips */
    536 
    537 #if defined(BCM_53570_B0)
    538     { /* SOC_REG_INT_VFI_PARITY_STATUSr */
    539         soc_block_list[5],
    540         soc_genreg,
    541         1,
    542         0,
    543         0x12011200,
    544         0,
    545         0,
    546         3,
    547         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
    548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    549         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    550         -1,
    551         -1,
    552     },
    553 #endif /* chips */
    554 
    555 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    556     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    557     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    558     { /* SOC_REG_INT_VFI_PARITY_STATUS_INTRr */
    559         soc_block_list[5],
    560         soc_genreg,
    561         1,
    562         0,
    563         0x5080170,
    564         0,
    565         0,
    566         3,
    567         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
    568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    569         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    570         -1,
    571         -1,
    572     },
    573 #endif /* chips */
    574 
    575 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
    576     { /* SOC_REG_INT_VFI_PARITY_STATUS_INTR_BCM56334_A0r */
    577         soc_block_list[5],
    578         soc_genreg,
    579         1,
    580         0,
    581         0x6080145,
    582         0,
    583         0,
    584         3,
    585         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
    586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    587         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    588         -1,
    589         -1,
    590     },
    591 #endif /* chips */
    592 
    593 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    594     { /* SOC_REG_INT_VFI_PARITY_STATUS_INTR_BCM56440_A0r */
    595         soc_block_list[5],
    596         soc_genreg,
    597         1,
    598         0,
    599         0x5080d16,
    600         0,
    601         0,
    602         3,
    603         soc_CPB_PARITY_STATUS_INTRr_fields,
    604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    605         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    606         -1,
    607         -1,
    608     },
    609 #endif /* chips */
    610 
    611 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    612     defined(BCM_56450_B1)
    613     { /* SOC_REG_INT_VFI_PARITY_STATUS_INTR_BCM56450_A0r */
    614         soc_block_list[5],
    615         soc_genreg,
    616         1,
    617         0,
    618         0x16011600,
    619         0,
    620         0,
    621         3,
    622         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
    623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    624         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    625         -1,
    626         -1,
    627     },
    628 #endif /* chips */
    629 
    630 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
    631     { /* SOC_REG_INT_VFI_PARITY_STATUS_INTR_BCM56840_A0r */
    632         soc_block_list[5],
    633         soc_genreg,
    634         1,
    635         0,
    636         0x5080d16,
    637         0,
    638         0,
    639         3,
    640         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
    641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    642         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    643         -1,
    644         -1,
    645     },
    646 #endif /* chips */
    647 
    648 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    649     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    650     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    651     { /* SOC_REG_INT_VFI_PARITY_STATUS_NACKr */
    652         soc_block_list[5],
    653         soc_genreg,
    654         1,
    655         0,
    656         0x5080171,
    657         0,
    658         0,
    659         3,
    660         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
    661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    662         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    663         -1,
    664         -1,
    665     },
    666 #endif /* chips */
    667 
    668 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    669     { /* SOC_REG_INT_VFI_PARITY_STATUS_NACK_BCM56440_A0r */
    670         soc_block_list[5],
    671         soc_genreg,
    672         1,
    673         0,
    674         0x5080d17,
    675         0,
    676         0,
    677         3,
    678         soc_CPB_PARITY_STATUS_INTRr_fields,
    679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    680         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    681         -1,
    682         -1,
    683     },
    684 #endif /* chips */
    685 
    686 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    687     defined(BCM_56450_B1)
    688     { /* SOC_REG_INT_VFI_PARITY_STATUS_NACK_BCM56450_A0r */
    689         soc_block_list[5],
    690         soc_genreg,
    691         1,
    692         0,
    693         0x16011700,
    694         0,
    695         0,
    696         3,
    697         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
    698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    700         -1,
    701         -1,
    702     },
    703 #endif /* chips */
    704 
    705 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
    706     { /* SOC_REG_INT_VFI_PARITY_STATUS_NACK_BCM56840_A0r */
    707         soc_block_list[5],
    708         soc_genreg,
    709         1,
    710         0,
    711         0x5080d17,
    712         0,
    713         0,
    714         3,
    715         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
    716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    718         -1,
    719         -1,
    720     },
    721 #endif /* chips */
    722 
    723 #if defined(BCM_56640_A0)
    724     { /* SOC_REG_INT_VFI_PDA_CONTROLr */
    725         soc_block_list[5],
    726         soc_genreg,
    727         1,
    728         0,
    729         0x16010d00,
    730         0,
    731         0,
    732         4,
    733         soc_VFI_PDA_CONTROLr_fields,
    734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    735         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    736         -1,
    737         -1,
    738     },
    739 #endif /* chips */
    740 
    741 #if defined(BCM_56340_A0)
    742     { /* SOC_REG_INT_VFI_PDA_CONTROL_BCM56340_A0r */
    743         soc_block_list[5],
    744         soc_genreg,
    745         1,
    746         0,
    747         0x16010d00,
    748         0,
    749         0,
    750         1,
    751         soc_VFI_PDA_CONTROL_BCM56340_A0r_fields,
    752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    754         -1,
    755         -1,
    756     },
    757 #endif /* chips */
    758 
    759 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    760     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    761     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIGr */
    762         soc_block_list[5],
    763         soc_genreg,
    764         1,
    765         0,
    766         0x4080117,
    767         0,
    768         0,
    769         4,
    770         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
    771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    772         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    773         -1,
    774         -1,
    775     },
    776 #endif /* chips */
    777 
    778 #if defined(BCM_56970_A0)
    779     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_2r */
    780         soc_block_list[5],
    781         soc_genreg,
    782         1,
    783         0,
    784         0x570f0000,
    785         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    786         0,
    787         8,
    788         soc_DST_COMPRESSION_CAM_BIST_CONFIG_2r_fields,
    789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    790         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    791         -1,
    792         -1,
    793         0,
    794     },
    795 #endif /* chips */
    796 
    797 #if defined(BCM_56970_A0)
    798     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64r */
    799         soc_block_list[5],
    800         soc_genreg,
    801         1,
    802         0,
    803         0x570d0000,
    804         SOC_REG_FLAG_64_BITS |
    805                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    806         0,
    807         5,
    808         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
    809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    810         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    811         -1,
    812         -1,
    813         0,
    814     },
    815 #endif /* chips */
    816 
    817 #if defined(BCM_56970_A0)
    818     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_2_PIPE0r */
    819         soc_block_list[5],
    820         soc_genreg,
    821         1,
    822         0,
    823         0x570f0000,
    824         0,
    825         0,
    826         8,
    827         soc_DST_COMPRESSION_CAM_BIST_CONFIG_2r_fields,
    828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    829         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    830         -1,
    831         -1,
    832         0,
    833     },
    834 #endif /* chips */
    835 
    836 #if defined(BCM_56970_A0)
    837     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_2_PIPE1r */
    838         soc_block_list[5],
    839         soc_genreg,
    840         1,
    841         0,
    842         0x570f0000,
    843         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    844         0,
    845         8,
    846         soc_DST_COMPRESSION_CAM_BIST_CONFIG_2r_fields,
    847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    848         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    849         -1,
    850         -1,
    851         0,
    852     },
    853 #endif /* chips */
    854 
    855 #if defined(BCM_56970_A0)
    856     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_2_PIPE2r */
    857         soc_block_list[5],
    858         soc_genreg,
    859         1,
    860         0,
    861         0x570f0000,
    862         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    863         0,
    864         8,
    865         soc_DST_COMPRESSION_CAM_BIST_CONFIG_2r_fields,
    866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    867         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    868         -1,
    869         -1,
    870         0,
    871     },
    872 #endif /* chips */
    873 
    874 #if defined(BCM_56970_A0)
    875     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_2_PIPE3r */
    876         soc_block_list[5],
    877         soc_genreg,
    878         1,
    879         0,
    880         0x570f0000,
    881         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    882         0,
    883         8,
    884         soc_DST_COMPRESSION_CAM_BIST_CONFIG_2r_fields,
    885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    886         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    887         -1,
    888         -1,
    889         0,
    890     },
    891 #endif /* chips */
    892 
    893 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
    894     defined(BCM_56870_A0)
    895     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_BCM56870_A0r */
    896         soc_block_list[5],
    897         soc_genreg,
    898         1,
    899         0,
    900         0x57060000,
    901         SOC_REG_FLAG_64_BITS |
    902                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    903         0,
    904         6,
    905         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
    906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    907         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    908         -1,
    909         -1,
    910         0,
    911     },
    912 #endif /* chips */
    913 
    914 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
    915     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_BCM56980_A0r */
    916         soc_block_list[5],
    917         soc_genreg,
    918         1,
    919         0,
    920         0xa010600,
    921         SOC_REG_FLAG_64_BITS |
    922                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    923         0,
    924         5,
    925         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
    926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    927         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    928         -1,
    929         -1,
    930         3,
    931     },
    932 #endif /* chips */
    933 
    934 #if defined(BCM_56970_A0)
    935     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE0r */
    936         soc_block_list[5],
    937         soc_genreg,
    938         1,
    939         0,
    940         0x570d0000,
    941         SOC_REG_FLAG_64_BITS,
    942         0,
    943         5,
    944         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
    945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    946         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    947         -1,
    948         -1,
    949         0,
    950     },
    951 #endif /* chips */
    952 
    953 #if defined(BCM_56970_A0)
    954     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE1r */
    955         soc_block_list[5],
    956         soc_genreg,
    957         1,
    958         0,
    959         0x570d0000,
    960         SOC_REG_FLAG_64_BITS |
    961                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    962         0,
    963         5,
    964         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
    965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    966         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    967         -1,
    968         -1,
    969         0,
    970     },
    971 #endif /* chips */
    972 
    973 #if defined(BCM_56970_A0)
    974     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE2r */
    975         soc_block_list[5],
    976         soc_genreg,
    977         1,
    978         0,
    979         0x570d0000,
    980         SOC_REG_FLAG_64_BITS |
    981                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    982         0,
    983         5,
    984         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
    985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    986         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    987         -1,
    988         -1,
    989         0,
    990     },
    991 #endif /* chips */
    992 
    993 #if defined(BCM_56970_A0)
    994     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE3r */
    995         soc_block_list[5],
    996         soc_genreg,
    997         1,
    998         0,
    999         0x570d0000,
   1000         SOC_REG_FLAG_64_BITS |
   1001                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1002         0,
   1003         5,
   1004         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
   1005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1006         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1007         -1,
   1008         -1,
   1009         0,
   1010     },
   1011 #endif /* chips */
   1012 
   1013 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1014     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE4r */
   1015         soc_block_list[5],
   1016         soc_genreg,
   1017         1,
   1018         0,
   1019         0xa010600,
   1020         SOC_REG_FLAG_64_BITS |
   1021                           (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1022         0,
   1023         5,
   1024         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
   1025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1026         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1027         -1,
   1028         -1,
   1029         3,
   1030     },
   1031 #endif /* chips */
   1032 
   1033 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1034     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE5r */
   1035         soc_block_list[5],
   1036         soc_genreg,
   1037         1,
   1038         0,
   1039         0xa010600,
   1040         SOC_REG_FLAG_64_BITS |
   1041                           (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1042         0,
   1043         5,
   1044         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
   1045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1046         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1047         -1,
   1048         -1,
   1049         3,
   1050     },
   1051 #endif /* chips */
   1052 
   1053 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1054     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE6r */
   1055         soc_block_list[5],
   1056         soc_genreg,
   1057         1,
   1058         0,
   1059         0xa010600,
   1060         SOC_REG_FLAG_64_BITS |
   1061                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1062         0,
   1063         5,
   1064         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
   1065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1066         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1067         -1,
   1068         -1,
   1069         3,
   1070     },
   1071 #endif /* chips */
   1072 
   1073 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1074     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE7r */
   1075         soc_block_list[5],
   1076         soc_genreg,
   1077         1,
   1078         0,
   1079         0xa010600,
   1080         SOC_REG_FLAG_64_BITS |
   1081                           (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1082         0,
   1083         5,
   1084         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
   1085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1086         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1087         -1,
   1088         -1,
   1089         3,
   1090     },
   1091 #endif /* chips */
   1092 
   1093 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   1094     defined(BCM_56870_A0)
   1095     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE0_BCM56870_A0r */
   1096         soc_block_list[5],
   1097         soc_genreg,
   1098         1,
   1099         0,
   1100         0x57060000,
   1101         SOC_REG_FLAG_64_BITS,
   1102         0,
   1103         6,
   1104         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
   1105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1106         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1107         -1,
   1108         -1,
   1109         0,
   1110     },
   1111 #endif /* chips */
   1112 
   1113 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1114     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE0_BCM56980_A0r */
   1115         soc_block_list[5],
   1116         soc_genreg,
   1117         1,
   1118         0,
   1119         0xa010600,
   1120         SOC_REG_FLAG_64_BITS,
   1121         0,
   1122         5,
   1123         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
   1124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1125         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1126         -1,
   1127         -1,
   1128         3,
   1129     },
   1130 #endif /* chips */
   1131 
   1132 #if defined(BCM_56870_A0)
   1133     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE1_BCM56870_A0r */
   1134         soc_block_list[5],
   1135         soc_genreg,
   1136         1,
   1137         0,
   1138         0x57060000,
   1139         SOC_REG_FLAG_64_BITS |
   1140                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1141         0,
   1142         6,
   1143         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
   1144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1145         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1146         -1,
   1147         -1,
   1148         0,
   1149     },
   1150 #endif /* chips */
   1151 
   1152 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1153     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE1_BCM56980_A0r */
   1154         soc_block_list[5],
   1155         soc_genreg,
   1156         1,
   1157         0,
   1158         0xa010600,
   1159         SOC_REG_FLAG_64_BITS |
   1160                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1161         0,
   1162         5,
   1163         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
   1164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1165         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1166         -1,
   1167         -1,
   1168         3,
   1169     },
   1170 #endif /* chips */
   1171 
   1172 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1173     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE2_BCM56980_A0r */
   1174         soc_block_list[5],
   1175         soc_genreg,
   1176         1,
   1177         0,
   1178         0xa010600,
   1179         SOC_REG_FLAG_64_BITS |
   1180                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1181         0,
   1182         5,
   1183         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
   1184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1185         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1186         -1,
   1187         -1,
   1188         3,
   1189     },
   1190 #endif /* chips */
   1191 
   1192 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1193     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_64_PIPE3_BCM56980_A0r */
   1194         soc_block_list[5],
   1195         soc_genreg,
   1196         1,
   1197         0,
   1198         0xa010600,
   1199         SOC_REG_FLAG_64_BITS |
   1200                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1201         0,
   1202         5,
   1203         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
   1204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1205         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1206         -1,
   1207         -1,
   1208         3,
   1209     },
   1210 #endif /* chips */
   1211 
   1212 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   1213     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   1214     defined(BCM_56160_A0)
   1215     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM53400_A0r */
   1216         soc_block_list[5],
   1217         soc_genreg,
   1218         1,
   1219         0,
   1220         0xe011d00,
   1221         0,
   1222         0,
   1223         4,
   1224         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1226         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1227         -1,
   1228         -1,
   1229     },
   1230 #endif /* chips */
   1231 
   1232 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   1233     defined(BCM_56270_A0)
   1234     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56260_A0r */
   1235         soc_block_list[5],
   1236         soc_genreg,
   1237         1,
   1238         0,
   1239         0x12011a00,
   1240         0,
   1241         0,
   1242         4,
   1243         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1245         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1246         -1,
   1247         -1,
   1248     },
   1249 #endif /* chips */
   1250 
   1251 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   1252     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56334_A0r */
   1253         soc_block_list[5],
   1254         soc_genreg,
   1255         1,
   1256         0,
   1257         0x408012a,
   1258         0,
   1259         0,
   1260         4,
   1261         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
   1262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1264         -1,
   1265         -1,
   1266     },
   1267 #endif /* chips */
   1268 
   1269 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1270     defined(BCM_56450_B1)
   1271     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56450_A0r */
   1272         soc_block_list[5],
   1273         soc_genreg,
   1274         1,
   1275         0,
   1276         0x12011900,
   1277         0,
   1278         0,
   1279         4,
   1280         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
   1281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1282         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1283         -1,
   1284         -1,
   1285     },
   1286 #endif /* chips */
   1287 
   1288 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   1289     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56560_A0r */
   1290         soc_block_list[5],
   1291         soc_genreg,
   1292         1,
   1293         0,
   1294         0x130e0000,
   1295         0,
   1296         0,
   1297         4,
   1298         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1300         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1301         -1,
   1302         -1,
   1303     },
   1304 #endif /* chips */
   1305 
   1306 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   1307     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   1308     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   1309     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56634_A0r */
   1310         soc_block_list[5],
   1311         soc_genreg,
   1312         1,
   1313         0,
   1314         0x4080149,
   1315         0,
   1316         0,
   1317         4,
   1318         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
   1319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1321         -1,
   1322         -1,
   1323     },
   1324 #endif /* chips */
   1325 
   1326 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1327     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56640_A0r */
   1328         soc_block_list[5],
   1329         soc_genreg,
   1330         1,
   1331         0,
   1332         0x12010c00,
   1333         0,
   1334         0,
   1335         4,
   1336         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
   1337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1339         -1,
   1340         -1,
   1341     },
   1342 #endif /* chips */
   1343 
   1344 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   1345     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56670_A0r */
   1346         soc_block_list[5],
   1347         soc_genreg,
   1348         1,
   1349         0,
   1350         0x130f0000,
   1351         0,
   1352         0,
   1353         4,
   1354         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1356         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1357         -1,
   1358         -1,
   1359     },
   1360 #endif /* chips */
   1361 
   1362 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   1363     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56820_A0r */
   1364         soc_block_list[5],
   1365         soc_genreg,
   1366         1,
   1367         0,
   1368         0x4080c35,
   1369         0,
   1370         0,
   1371         4,
   1372         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
   1373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1374         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1375         -1,
   1376         -1,
   1377     },
   1378 #endif /* chips */
   1379 
   1380 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   1381     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   1382     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56840_A0r */
   1383         soc_block_list[5],
   1384         soc_genreg,
   1385         1,
   1386         0,
   1387         0x4080d18,
   1388         0,
   1389         0,
   1390         4,
   1391         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
   1392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1393         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1394         -1,
   1395         -1,
   1396     },
   1397 #endif /* chips */
   1398 
   1399 #if defined(BCM_56850_A0)
   1400     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56850_A0r */
   1401         soc_block_list[5],
   1402         soc_genreg,
   1403         1,
   1404         0,
   1405         0x13100000,
   1406         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1407         0,
   1408         4,
   1409         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
   1410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1411         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1412         -1,
   1413         -1,
   1414     },
   1415 #endif /* chips */
   1416 
   1417 #if defined(BCM_56860_A0)
   1418     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56860_A0r */
   1419         soc_block_list[5],
   1420         soc_genreg,
   1421         1,
   1422         0,
   1423         0x130e0000,
   1424         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1425         0,
   1426         4,
   1427         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
   1428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1429         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1430         -1,
   1431         -1,
   1432     },
   1433 #endif /* chips */
   1434 
   1435 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   1436     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56960_A0r */
   1437         soc_block_list[5],
   1438         soc_genreg,
   1439         1,
   1440         0,
   1441         0x330c0000,
   1442         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1443         0,
   1444         4,
   1445         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1447         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1448         -1,
   1449         -1,
   1450         0,
   1451     },
   1452 #endif /* chips */
   1453 
   1454 #if defined(BCM_56970_A0)
   1455     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56970_A0r */
   1456         soc_block_list[5],
   1457         soc_genreg,
   1458         1,
   1459         0,
   1460         0x570e0000,
   1461         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1462         0,
   1463         4,
   1464         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1466         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1467         -1,
   1468         -1,
   1469         0,
   1470     },
   1471 #endif /* chips */
   1472 
   1473 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1474     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_BCM56980_A0r */
   1475         soc_block_list[5],
   1476         soc_genreg,
   1477         1,
   1478         0,
   1479         0xa010500,
   1480         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1481         0,
   1482         4,
   1483         soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIGr_fields,
   1484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1485         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1486         -1,
   1487         -1,
   1488         3,
   1489     },
   1490 #endif /* chips */
   1491 
   1492 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   1493     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE0r */
   1494         soc_block_list[5],
   1495         soc_genreg,
   1496         1,
   1497         0,
   1498         0x330c0000,
   1499         0,
   1500         0,
   1501         4,
   1502         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1504         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1505         -1,
   1506         -1,
   1507         0,
   1508     },
   1509 #endif /* chips */
   1510 
   1511 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   1512     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE1r */
   1513         soc_block_list[5],
   1514         soc_genreg,
   1515         1,
   1516         0,
   1517         0x330c0000,
   1518         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1519         0,
   1520         4,
   1521         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1523         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1524         -1,
   1525         -1,
   1526         0,
   1527     },
   1528 #endif /* chips */
   1529 
   1530 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   1531     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE2r */
   1532         soc_block_list[5],
   1533         soc_genreg,
   1534         1,
   1535         0,
   1536         0x330c0000,
   1537         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1538         0,
   1539         4,
   1540         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1542         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1543         -1,
   1544         -1,
   1545         0,
   1546     },
   1547 #endif /* chips */
   1548 
   1549 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   1550     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE3r */
   1551         soc_block_list[5],
   1552         soc_genreg,
   1553         1,
   1554         0,
   1555         0x330c0000,
   1556         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1557         0,
   1558         4,
   1559         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1562         -1,
   1563         -1,
   1564         0,
   1565     },
   1566 #endif /* chips */
   1567 
   1568 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1569     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE4r */
   1570         soc_block_list[5],
   1571         soc_genreg,
   1572         1,
   1573         0,
   1574         0xa010500,
   1575         (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1576         0,
   1577         4,
   1578         soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIGr_fields,
   1579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1580         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1581         -1,
   1582         -1,
   1583         3,
   1584     },
   1585 #endif /* chips */
   1586 
   1587 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1588     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE5r */
   1589         soc_block_list[5],
   1590         soc_genreg,
   1591         1,
   1592         0,
   1593         0xa010500,
   1594         (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1595         0,
   1596         4,
   1597         soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIGr_fields,
   1598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1599         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1600         -1,
   1601         -1,
   1602         3,
   1603     },
   1604 #endif /* chips */
   1605 
   1606 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1607     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE6r */
   1608         soc_block_list[5],
   1609         soc_genreg,
   1610         1,
   1611         0,
   1612         0xa010500,
   1613         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1614         0,
   1615         4,
   1616         soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIGr_fields,
   1617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1618         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1619         -1,
   1620         -1,
   1621         3,
   1622     },
   1623 #endif /* chips */
   1624 
   1625 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1626     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE7r */
   1627         soc_block_list[5],
   1628         soc_genreg,
   1629         1,
   1630         0,
   1631         0xa010500,
   1632         (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1633         0,
   1634         4,
   1635         soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIGr_fields,
   1636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1637         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1638         -1,
   1639         -1,
   1640         3,
   1641     },
   1642 #endif /* chips */
   1643 
   1644 #if defined(BCM_56970_A0)
   1645     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE0_BCM56970_A0r */
   1646         soc_block_list[5],
   1647         soc_genreg,
   1648         1,
   1649         0,
   1650         0x570e0000,
   1651         0,
   1652         0,
   1653         4,
   1654         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1656         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1657         -1,
   1658         -1,
   1659         0,
   1660     },
   1661 #endif /* chips */
   1662 
   1663 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1664     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE0_BCM56980_A0r */
   1665         soc_block_list[5],
   1666         soc_genreg,
   1667         1,
   1668         0,
   1669         0xa010500,
   1670         0,
   1671         0,
   1672         4,
   1673         soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIGr_fields,
   1674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1675         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1676         -1,
   1677         -1,
   1678         3,
   1679     },
   1680 #endif /* chips */
   1681 
   1682 #if defined(BCM_56970_A0)
   1683     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE1_BCM56970_A0r */
   1684         soc_block_list[5],
   1685         soc_genreg,
   1686         1,
   1687         0,
   1688         0x570e0000,
   1689         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1690         0,
   1691         4,
   1692         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1694         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1695         -1,
   1696         -1,
   1697         0,
   1698     },
   1699 #endif /* chips */
   1700 
   1701 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1702     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE1_BCM56980_A0r */
   1703         soc_block_list[5],
   1704         soc_genreg,
   1705         1,
   1706         0,
   1707         0xa010500,
   1708         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1709         0,
   1710         4,
   1711         soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIGr_fields,
   1712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1713         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1714         -1,
   1715         -1,
   1716         3,
   1717     },
   1718 #endif /* chips */
   1719 
   1720 #if defined(BCM_56970_A0)
   1721     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE2_BCM56970_A0r */
   1722         soc_block_list[5],
   1723         soc_genreg,
   1724         1,
   1725         0,
   1726         0x570e0000,
   1727         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1728         0,
   1729         4,
   1730         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1732         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1733         -1,
   1734         -1,
   1735         0,
   1736     },
   1737 #endif /* chips */
   1738 
   1739 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1740     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE2_BCM56980_A0r */
   1741         soc_block_list[5],
   1742         soc_genreg,
   1743         1,
   1744         0,
   1745         0xa010500,
   1746         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1747         0,
   1748         4,
   1749         soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIGr_fields,
   1750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1751         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1752         -1,
   1753         -1,
   1754         3,
   1755     },
   1756 #endif /* chips */
   1757 
   1758 #if defined(BCM_56970_A0)
   1759     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE3_BCM56970_A0r */
   1760         soc_block_list[5],
   1761         soc_genreg,
   1762         1,
   1763         0,
   1764         0x570e0000,
   1765         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1766         0,
   1767         4,
   1768         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
   1769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1770         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1771         -1,
   1772         -1,
   1773         0,
   1774     },
   1775 #endif /* chips */
   1776 
   1777 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1778     { /* SOC_REG_INT_VFP_CAM_BIST_CONFIG_PIPE3_BCM56980_A0r */
   1779         soc_block_list[5],
   1780         soc_genreg,
   1781         1,
   1782         0,
   1783         0xa010500,
   1784         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1785         0,
   1786         4,
   1787         soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIGr_fields,
   1788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1790         -1,
   1791         -1,
   1792         3,
   1793     },
   1794 #endif /* chips */
   1795 
   1796 #if defined(BCM_56514_A0)
   1797     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROLr */
   1798         soc_block_list[5],
   1799         soc_genreg,
   1800         1,
   1801         0,
   1802         0x408001a,
   1803         0,
   1804         0,
   1805         17,
   1806         soc_VFP_CAM_BIST_CONTROLr_fields,
   1807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1808         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1809         -1,
   1810         -1,
   1811     },
   1812 #endif /* chips */
   1813 
   1814 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   1815     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   1816     defined(BCM_56160_A0)
   1817     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM53400_A0r */
   1818         soc_block_list[5],
   1819         soc_genreg,
   1820         1,
   1821         0,
   1822         0xe011a00,
   1823         0,
   1824         0,
   1825         8,
   1826         soc_VFP_CAM_BIST_CONTROL_BCM53400_A0r_fields,
   1827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1828         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1829         -1,
   1830         -1,
   1831     },
   1832 #endif /* chips */
   1833 
   1834 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   1835     defined(BCM_56270_A0)
   1836     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56260_A0r */
   1837         soc_block_list[5],
   1838         soc_genreg,
   1839         1,
   1840         0,
   1841         0x12011700,
   1842         0,
   1843         0,
   1844         16,
   1845         soc_VFP_CAM_BIST_CONTROL_BCM56960_A0r_fields,
   1846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1847         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1848         -1,
   1849         -1,
   1850     },
   1851 #endif /* chips */
   1852 
   1853 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   1854     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56334_A0r */
   1855         soc_block_list[5],
   1856         soc_genreg,
   1857         1,
   1858         0,
   1859         0x4080127,
   1860         0,
   1861         0,
   1862         16,
   1863         soc_VFP_CAM_BIST_CONTROL_BCM56624_A0r_fields,
   1864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1865         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1866         -1,
   1867         -1,
   1868     },
   1869 #endif /* chips */
   1870 
   1871 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1872     defined(BCM_56450_B1)
   1873     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56450_A0r */
   1874         soc_block_list[5],
   1875         soc_genreg,
   1876         1,
   1877         0,
   1878         0x12011600,
   1879         0,
   1880         0,
   1881         16,
   1882         soc_VFP_CAM_BIST_CONTROL_BCM56640_A0r_fields,
   1883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1884         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1885         -1,
   1886         -1,
   1887     },
   1888 #endif /* chips */
   1889 
   1890 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   1891     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56560_A0r */
   1892         soc_block_list[5],
   1893         soc_genreg,
   1894         1,
   1895         0,
   1896         0x130b0000,
   1897         0,
   1898         0,
   1899         16,
   1900         soc_VFP_CAM_BIST_CONTROL_BCM56960_A0r_fields,
   1901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1902         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1903         -1,
   1904         -1,
   1905     },
   1906 #endif /* chips */
   1907 
   1908 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   1909     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   1910     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56624_A0r */
   1911         soc_block_list[5],
   1912         soc_genreg,
   1913         1,
   1914         0,
   1915         0x4080114,
   1916         0,
   1917         0,
   1918         16,
   1919         soc_VFP_CAM_BIST_CONTROL_BCM56624_A0r_fields,
   1920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1922         -1,
   1923         -1,
   1924     },
   1925 #endif /* chips */
   1926 
   1927 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   1928     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   1929     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   1930     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56634_A0r */
   1931         soc_block_list[5],
   1932         soc_genreg,
   1933         1,
   1934         0,
   1935         0x4080146,
   1936         0,
   1937         0,
   1938         16,
   1939         soc_VFP_CAM_BIST_CONTROL_BCM56624_A0r_fields,
   1940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1941         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1942         -1,
   1943         -1,
   1944     },
   1945 #endif /* chips */
   1946 
   1947 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   1948     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56640_A0r */
   1949         soc_block_list[5],
   1950         soc_genreg,
   1951         1,
   1952         0,
   1953         0x12010800,
   1954         0,
   1955         0,
   1956         16,
   1957         soc_VFP_CAM_BIST_CONTROL_BCM56640_A0r_fields,
   1958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1959         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1960         -1,
   1961         -1,
   1962     },
   1963 #endif /* chips */
   1964 
   1965 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   1966     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56670_A0r */
   1967         soc_block_list[5],
   1968         soc_genreg,
   1969         1,
   1970         0,
   1971         0x130c0000,
   1972         0,
   1973         0,
   1974         16,
   1975         soc_VFP_CAM_BIST_CONTROL_BCM56960_A0r_fields,
   1976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1977         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1978         -1,
   1979         -1,
   1980     },
   1981 #endif /* chips */
   1982 
   1983 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   1984     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56820_A0r */
   1985         soc_block_list[5],
   1986         soc_genreg,
   1987         1,
   1988         0,
   1989         0x4080c2c,
   1990         0,
   1991         0,
   1992         16,
   1993         soc_VFP_CAM_BIST_CONTROL_BCM56624_A0r_fields,
   1994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1995         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1996         -1,
   1997         -1,
   1998     },
   1999 #endif /* chips */
   2000 
   2001 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   2002     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   2003     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56840_A0r */
   2004         soc_block_list[5],
   2005         soc_genreg,
   2006         1,
   2007         0,
   2008         0x4080d15,
   2009         0,
   2010         0,
   2011         16,
   2012         soc_VFP_CAM_BIST_CONTROL_BCM56624_A0r_fields,
   2013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2014         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2015         -1,
   2016         -1,
   2017     },
   2018 #endif /* chips */
   2019 
   2020 #if defined(BCM_56850_A0)
   2021     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56850_A0r */
   2022         soc_block_list[5],
   2023         soc_genreg,
   2024         1,
   2025         0,
   2026         0x130d0000,
   2027         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2028         0,
   2029         16,
   2030         soc_VFP_CAM_BIST_CONTROL_BCM56640_A0r_fields,
   2031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2032         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2033         -1,
   2034         -1,
   2035     },
   2036 #endif /* chips */
   2037 
   2038 #if defined(BCM_56860_A0)
   2039     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56860_A0r */
   2040         soc_block_list[5],
   2041         soc_genreg,
   2042         1,
   2043         0,
   2044         0x130b0000,
   2045         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2046         0,
   2047         16,
   2048         soc_VFP_CAM_BIST_CONTROL_BCM56640_A0r_fields,
   2049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2050         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2051         -1,
   2052         -1,
   2053     },
   2054 #endif /* chips */
   2055 
   2056 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2057     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56960_A0r */
   2058         soc_block_list[5],
   2059         soc_genreg,
   2060         1,
   2061         0,
   2062         0x33090000,
   2063         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2064         0,
   2065         16,
   2066         soc_VFP_CAM_BIST_CONTROL_BCM56960_A0r_fields,
   2067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2068         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2069         -1,
   2070         -1,
   2071         0,
   2072     },
   2073 #endif /* chips */
   2074 
   2075 #if defined(BCM_56970_A0)
   2076     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56970_A0r */
   2077         soc_block_list[5],
   2078         soc_genreg,
   2079         1,
   2080         0,
   2081         0x57090000,
   2082         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2083         0,
   2084         18,
   2085         soc_VFP_CAM_BIST_CONTROL_BCM56970_A0r_fields,
   2086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2088         -1,
   2089         -1,
   2090         0,
   2091     },
   2092 #endif /* chips */
   2093 
   2094 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2095     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_BCM56980_A0r */
   2096         soc_block_list[5],
   2097         soc_genreg,
   2098         1,
   2099         0,
   2100         0xa010700,
   2101         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2102         0,
   2103         18,
   2104         soc_VFP_CAM_BIST_CONTROL_BCM56980_A0r_fields,
   2105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2106         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2107         -1,
   2108         -1,
   2109         3,
   2110     },
   2111 #endif /* chips */
   2112 
   2113 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2114     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE0r */
   2115         soc_block_list[5],
   2116         soc_genreg,
   2117         1,
   2118         0,
   2119         0x33090000,
   2120         0,
   2121         0,
   2122         16,
   2123         soc_VFP_CAM_BIST_CONTROL_BCM56960_A0r_fields,
   2124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2125         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2126         -1,
   2127         -1,
   2128         0,
   2129     },
   2130 #endif /* chips */
   2131 
   2132 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2133     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE1r */
   2134         soc_block_list[5],
   2135         soc_genreg,
   2136         1,
   2137         0,
   2138         0x33090000,
   2139         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2140         0,
   2141         16,
   2142         soc_VFP_CAM_BIST_CONTROL_BCM56960_A0r_fields,
   2143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2144         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2145         -1,
   2146         -1,
   2147         0,
   2148     },
   2149 #endif /* chips */
   2150 
   2151 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2152     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE2r */
   2153         soc_block_list[5],
   2154         soc_genreg,
   2155         1,
   2156         0,
   2157         0x33090000,
   2158         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2159         0,
   2160         16,
   2161         soc_VFP_CAM_BIST_CONTROL_BCM56960_A0r_fields,
   2162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2163         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2164         -1,
   2165         -1,
   2166         0,
   2167     },
   2168 #endif /* chips */
   2169 
   2170 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2171     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE3r */
   2172         soc_block_list[5],
   2173         soc_genreg,
   2174         1,
   2175         0,
   2176         0x33090000,
   2177         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2178         0,
   2179         16,
   2180         soc_VFP_CAM_BIST_CONTROL_BCM56960_A0r_fields,
   2181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2182         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2183         -1,
   2184         -1,
   2185         0,
   2186     },
   2187 #endif /* chips */
   2188 
   2189 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2190     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE4r */
   2191         soc_block_list[5],
   2192         soc_genreg,
   2193         1,
   2194         0,
   2195         0xa010700,
   2196         (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2197         0,
   2198         18,
   2199         soc_VFP_CAM_BIST_CONTROL_BCM56980_A0r_fields,
   2200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2201         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2202         -1,
   2203         -1,
   2204         3,
   2205     },
   2206 #endif /* chips */
   2207 
   2208 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2209     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE5r */
   2210         soc_block_list[5],
   2211         soc_genreg,
   2212         1,
   2213         0,
   2214         0xa010700,
   2215         (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2216         0,
   2217         18,
   2218         soc_VFP_CAM_BIST_CONTROL_BCM56980_A0r_fields,
   2219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2220         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2221         -1,
   2222         -1,
   2223         3,
   2224     },
   2225 #endif /* chips */
   2226 
   2227 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2228     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE6r */
   2229         soc_block_list[5],
   2230         soc_genreg,
   2231         1,
   2232         0,
   2233         0xa010700,
   2234         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2235         0,
   2236         18,
   2237         soc_VFP_CAM_BIST_CONTROL_BCM56980_A0r_fields,
   2238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2239         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2240         -1,
   2241         -1,
   2242         3,
   2243     },
   2244 #endif /* chips */
   2245 
   2246 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2247     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE7r */
   2248         soc_block_list[5],
   2249         soc_genreg,
   2250         1,
   2251         0,
   2252         0xa010700,
   2253         (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2254         0,
   2255         18,
   2256         soc_VFP_CAM_BIST_CONTROL_BCM56980_A0r_fields,
   2257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2258         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2259         -1,
   2260         -1,
   2261         3,
   2262     },
   2263 #endif /* chips */
   2264 
   2265 #if defined(BCM_56970_A0)
   2266     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE0_BCM56970_A0r */
   2267         soc_block_list[5],
   2268         soc_genreg,
   2269         1,
   2270         0,
   2271         0x57090000,
   2272         0,
   2273         0,
   2274         18,
   2275         soc_VFP_CAM_BIST_CONTROL_BCM56970_A0r_fields,
   2276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2277         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2278         -1,
   2279         -1,
   2280         0,
   2281     },
   2282 #endif /* chips */
   2283 
   2284 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2285     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE0_BCM56980_A0r */
   2286         soc_block_list[5],
   2287         soc_genreg,
   2288         1,
   2289         0,
   2290         0xa010700,
   2291         0,
   2292         0,
   2293         18,
   2294         soc_VFP_CAM_BIST_CONTROL_BCM56980_A0r_fields,
   2295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2296         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2297         -1,
   2298         -1,
   2299         3,
   2300     },
   2301 #endif /* chips */
   2302 
   2303 #if defined(BCM_56970_A0)
   2304     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE1_BCM56970_A0r */
   2305         soc_block_list[5],
   2306         soc_genreg,
   2307         1,
   2308         0,
   2309         0x57090000,
   2310         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2311         0,
   2312         18,
   2313         soc_VFP_CAM_BIST_CONTROL_BCM56970_A0r_fields,
   2314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2315         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2316         -1,
   2317         -1,
   2318         0,
   2319     },
   2320 #endif /* chips */
   2321 
   2322 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2323     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE1_BCM56980_A0r */
   2324         soc_block_list[5],
   2325         soc_genreg,
   2326         1,
   2327         0,
   2328         0xa010700,
   2329         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2330         0,
   2331         18,
   2332         soc_VFP_CAM_BIST_CONTROL_BCM56980_A0r_fields,
   2333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2334         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2335         -1,
   2336         -1,
   2337         3,
   2338     },
   2339 #endif /* chips */
   2340 
   2341 #if defined(BCM_56970_A0)
   2342     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE2_BCM56970_A0r */
   2343         soc_block_list[5],
   2344         soc_genreg,
   2345         1,
   2346         0,
   2347         0x57090000,
   2348         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2349         0,
   2350         18,
   2351         soc_VFP_CAM_BIST_CONTROL_BCM56970_A0r_fields,
   2352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2353         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2354         -1,
   2355         -1,
   2356         0,
   2357     },
   2358 #endif /* chips */
   2359 
   2360 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2361     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE2_BCM56980_A0r */
   2362         soc_block_list[5],
   2363         soc_genreg,
   2364         1,
   2365         0,
   2366         0xa010700,
   2367         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2368         0,
   2369         18,
   2370         soc_VFP_CAM_BIST_CONTROL_BCM56980_A0r_fields,
   2371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2372         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2373         -1,
   2374         -1,
   2375         3,
   2376     },
   2377 #endif /* chips */
   2378 
   2379 #if defined(BCM_56970_A0)
   2380     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE3_BCM56970_A0r */
   2381         soc_block_list[5],
   2382         soc_genreg,
   2383         1,
   2384         0,
   2385         0x57090000,
   2386         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2387         0,
   2388         18,
   2389         soc_VFP_CAM_BIST_CONTROL_BCM56970_A0r_fields,
   2390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2391         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2392         -1,
   2393         -1,
   2394         0,
   2395     },
   2396 #endif /* chips */
   2397 
   2398 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2399     { /* SOC_REG_INT_VFP_CAM_BIST_CONTROL_PIPE3_BCM56980_A0r */
   2400         soc_block_list[5],
   2401         soc_genreg,
   2402         1,
   2403         0,
   2404         0xa010700,
   2405         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2406         0,
   2407         18,
   2408         soc_VFP_CAM_BIST_CONTROL_BCM56980_A0r_fields,
   2409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2410         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2411         -1,
   2412         -1,
   2413         3,
   2414     },
   2415 #endif /* chips */
   2416 
   2417 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   2418     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   2419     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATAr */
   2420         soc_block_list[5],
   2421         soc_genreg,
   2422         1,
   2423         0,
   2424         0x4080116,
   2425         SOC_REG_FLAG_WO,
   2426         0,
   2427         1,
   2428         soc_FP_CAM_DEBUG_DATA_0r_fields,
   2429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2430         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2431         -1,
   2432         -1,
   2433     },
   2434 #endif /* chips */
   2435 
   2436 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   2437     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   2438     defined(BCM_56160_A0)
   2439     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM53400_A0r */
   2440         soc_block_list[5],
   2441         soc_genreg,
   2442         1,
   2443         0,
   2444         0xe011c00,
   2445         SOC_REG_FLAG_WO,
   2446         0,
   2447         1,
   2448         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2450         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2451         -1,
   2452         -1,
   2453     },
   2454 #endif /* chips */
   2455 
   2456 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   2457     defined(BCM_56270_A0)
   2458     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56260_A0r */
   2459         soc_block_list[5],
   2460         soc_genreg,
   2461         1,
   2462         0,
   2463         0x12011900,
   2464         SOC_REG_FLAG_WO,
   2465         0,
   2466         1,
   2467         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2469         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2470         -1,
   2471         -1,
   2472     },
   2473 #endif /* chips */
   2474 
   2475 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   2476     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56334_A0r */
   2477         soc_block_list[5],
   2478         soc_genreg,
   2479         1,
   2480         0,
   2481         0x4080129,
   2482         SOC_REG_FLAG_WO,
   2483         0,
   2484         1,
   2485         soc_FP_CAM_DEBUG_DATA_0r_fields,
   2486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2488         -1,
   2489         -1,
   2490     },
   2491 #endif /* chips */
   2492 
   2493 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2494     defined(BCM_56450_B1)
   2495     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56450_A0r */
   2496         soc_block_list[5],
   2497         soc_genreg,
   2498         1,
   2499         0,
   2500         0x12011800,
   2501         SOC_REG_FLAG_WO,
   2502         0,
   2503         1,
   2504         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
   2505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2506         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2507         -1,
   2508         -1,
   2509     },
   2510 #endif /* chips */
   2511 
   2512 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   2513     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56560_A0r */
   2514         soc_block_list[5],
   2515         soc_genreg,
   2516         1,
   2517         0,
   2518         0x130d0000,
   2519         SOC_REG_FLAG_WO,
   2520         0,
   2521         1,
   2522         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2524         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2525         -1,
   2526         -1,
   2527     },
   2528 #endif /* chips */
   2529 
   2530 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   2531     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   2532     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   2533     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56634_A0r */
   2534         soc_block_list[5],
   2535         soc_genreg,
   2536         1,
   2537         0,
   2538         0x4080148,
   2539         SOC_REG_FLAG_WO,
   2540         0,
   2541         1,
   2542         soc_FP_CAM_DEBUG_DATA_0r_fields,
   2543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2544         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2545         -1,
   2546         -1,
   2547     },
   2548 #endif /* chips */
   2549 
   2550 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   2551     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56640_A0r */
   2552         soc_block_list[5],
   2553         soc_genreg,
   2554         1,
   2555         0,
   2556         0x12010b00,
   2557         SOC_REG_FLAG_WO,
   2558         0,
   2559         1,
   2560         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
   2561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2562         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2563         -1,
   2564         -1,
   2565     },
   2566 #endif /* chips */
   2567 
   2568 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   2569     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56670_A0r */
   2570         soc_block_list[5],
   2571         soc_genreg,
   2572         1,
   2573         0,
   2574         0x130e0000,
   2575         SOC_REG_FLAG_WO,
   2576         0,
   2577         1,
   2578         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2580         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2581         -1,
   2582         -1,
   2583     },
   2584 #endif /* chips */
   2585 
   2586 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   2587     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56820_A0r */
   2588         soc_block_list[5],
   2589         soc_genreg,
   2590         1,
   2591         0,
   2592         0x4080c2e,
   2593         SOC_REG_FLAG_WO,
   2594         0,
   2595         1,
   2596         soc_FP_CAM_DEBUG_DATA_0r_fields,
   2597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2598         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2599         -1,
   2600         -1,
   2601     },
   2602 #endif /* chips */
   2603 
   2604 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   2605     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   2606     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56840_A0r */
   2607         soc_block_list[5],
   2608         soc_genreg,
   2609         1,
   2610         0,
   2611         0x4080d17,
   2612         SOC_REG_FLAG_WO,
   2613         0,
   2614         1,
   2615         soc_FP_CAM_DEBUG_DATA_0r_fields,
   2616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2617         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2618         -1,
   2619         -1,
   2620     },
   2621 #endif /* chips */
   2622 
   2623 #if defined(BCM_56850_A0)
   2624     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56850_A0r */
   2625         soc_block_list[5],
   2626         soc_genreg,
   2627         1,
   2628         0,
   2629         0x130f0000,
   2630         SOC_REG_FLAG_WO |
   2631                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2632         0,
   2633         1,
   2634         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
   2635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2636         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2637         -1,
   2638         -1,
   2639     },
   2640 #endif /* chips */
   2641 
   2642 #if defined(BCM_56860_A0)
   2643     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56860_A0r */
   2644         soc_block_list[5],
   2645         soc_genreg,
   2646         1,
   2647         0,
   2648         0x130d0000,
   2649         SOC_REG_FLAG_WO |
   2650                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2651         0,
   2652         1,
   2653         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
   2654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2655         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2656         -1,
   2657         -1,
   2658     },
   2659 #endif /* chips */
   2660 
   2661 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2662     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56960_A0r */
   2663         soc_block_list[5],
   2664         soc_genreg,
   2665         1,
   2666         0,
   2667         0x330b0000,
   2668         SOC_REG_FLAG_WO |
   2669                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2670         0,
   2671         1,
   2672         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2674         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2675         -1,
   2676         -1,
   2677         0,
   2678     },
   2679 #endif /* chips */
   2680 
   2681 #if defined(BCM_56970_A0)
   2682     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56970_A0r */
   2683         soc_block_list[5],
   2684         soc_genreg,
   2685         1,
   2686         0,
   2687         0x570c0000,
   2688         SOC_REG_FLAG_WO |
   2689                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2690         0,
   2691         1,
   2692         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2694         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2695         -1,
   2696         -1,
   2697         0,
   2698     },
   2699 #endif /* chips */
   2700 
   2701 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2702     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_BCM56980_A0r */
   2703         soc_block_list[5],
   2704         soc_genreg,
   2705         1,
   2706         0,
   2707         0xa010800,
   2708         SOC_REG_FLAG_WO |
   2709                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2710         0,
   2711         1,
   2712         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2714         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2715         -1,
   2716         -1,
   2717         3,
   2718     },
   2719 #endif /* chips */
   2720 
   2721 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2722     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE0r */
   2723         soc_block_list[5],
   2724         soc_genreg,
   2725         1,
   2726         0,
   2727         0x330b0000,
   2728         SOC_REG_FLAG_WO,
   2729         0,
   2730         1,
   2731         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2733         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2734         -1,
   2735         -1,
   2736         0,
   2737     },
   2738 #endif /* chips */
   2739 
   2740 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2741     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE1r */
   2742         soc_block_list[5],
   2743         soc_genreg,
   2744         1,
   2745         0,
   2746         0x330b0000,
   2747         SOC_REG_FLAG_WO |
   2748                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2749         0,
   2750         1,
   2751         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2754         -1,
   2755         -1,
   2756         0,
   2757     },
   2758 #endif /* chips */
   2759 
   2760 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2761     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE2r */
   2762         soc_block_list[5],
   2763         soc_genreg,
   2764         1,
   2765         0,
   2766         0x330b0000,
   2767         SOC_REG_FLAG_WO |
   2768                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2769         0,
   2770         1,
   2771         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2773         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2774         -1,
   2775         -1,
   2776         0,
   2777     },
   2778 #endif /* chips */
   2779 
   2780 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2781     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE3r */
   2782         soc_block_list[5],
   2783         soc_genreg,
   2784         1,
   2785         0,
   2786         0x330b0000,
   2787         SOC_REG_FLAG_WO |
   2788                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2789         0,
   2790         1,
   2791         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2793         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2794         -1,
   2795         -1,
   2796         0,
   2797     },
   2798 #endif /* chips */
   2799 
   2800 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2801     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE4r */
   2802         soc_block_list[5],
   2803         soc_genreg,
   2804         1,
   2805         0,
   2806         0xa010800,
   2807         SOC_REG_FLAG_WO |
   2808                           (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2809         0,
   2810         1,
   2811         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2814         -1,
   2815         -1,
   2816         3,
   2817     },
   2818 #endif /* chips */
   2819 
   2820 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2821     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE5r */
   2822         soc_block_list[5],
   2823         soc_genreg,
   2824         1,
   2825         0,
   2826         0xa010800,
   2827         SOC_REG_FLAG_WO |
   2828                           (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2829         0,
   2830         1,
   2831         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2833         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2834         -1,
   2835         -1,
   2836         3,
   2837     },
   2838 #endif /* chips */
   2839 
   2840 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2841     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE6r */
   2842         soc_block_list[5],
   2843         soc_genreg,
   2844         1,
   2845         0,
   2846         0xa010800,
   2847         SOC_REG_FLAG_WO |
   2848                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2849         0,
   2850         1,
   2851         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2853         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2854         -1,
   2855         -1,
   2856         3,
   2857     },
   2858 #endif /* chips */
   2859 
   2860 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2861     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE7r */
   2862         soc_block_list[5],
   2863         soc_genreg,
   2864         1,
   2865         0,
   2866         0xa010800,
   2867         SOC_REG_FLAG_WO |
   2868                           (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2869         0,
   2870         1,
   2871         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2873         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2874         -1,
   2875         -1,
   2876         3,
   2877     },
   2878 #endif /* chips */
   2879 
   2880 #if defined(BCM_56970_A0)
   2881     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE0_BCM56970_A0r */
   2882         soc_block_list[5],
   2883         soc_genreg,
   2884         1,
   2885         0,
   2886         0x570c0000,
   2887         SOC_REG_FLAG_WO,
   2888         0,
   2889         1,
   2890         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2892         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2893         -1,
   2894         -1,
   2895         0,
   2896     },
   2897 #endif /* chips */
   2898 
   2899 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2900     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE0_BCM56980_A0r */
   2901         soc_block_list[5],
   2902         soc_genreg,
   2903         1,
   2904         0,
   2905         0xa010800,
   2906         SOC_REG_FLAG_WO,
   2907         0,
   2908         1,
   2909         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2912         -1,
   2913         -1,
   2914         3,
   2915     },
   2916 #endif /* chips */
   2917 
   2918 #if defined(BCM_56970_A0)
   2919     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE1_BCM56970_A0r */
   2920         soc_block_list[5],
   2921         soc_genreg,
   2922         1,
   2923         0,
   2924         0x570c0000,
   2925         SOC_REG_FLAG_WO |
   2926                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2927         0,
   2928         1,
   2929         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2931         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2932         -1,
   2933         -1,
   2934         0,
   2935     },
   2936 #endif /* chips */
   2937 
   2938 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2939     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE1_BCM56980_A0r */
   2940         soc_block_list[5],
   2941         soc_genreg,
   2942         1,
   2943         0,
   2944         0xa010800,
   2945         SOC_REG_FLAG_WO |
   2946                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2947         0,
   2948         1,
   2949         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2952         -1,
   2953         -1,
   2954         3,
   2955     },
   2956 #endif /* chips */
   2957 
   2958 #if defined(BCM_56970_A0)
   2959     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE2_BCM56970_A0r */
   2960         soc_block_list[5],
   2961         soc_genreg,
   2962         1,
   2963         0,
   2964         0x570c0000,
   2965         SOC_REG_FLAG_WO |
   2966                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2967         0,
   2968         1,
   2969         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2971         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2972         -1,
   2973         -1,
   2974         0,
   2975     },
   2976 #endif /* chips */
   2977 
   2978 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2979     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE2_BCM56980_A0r */
   2980         soc_block_list[5],
   2981         soc_genreg,
   2982         1,
   2983         0,
   2984         0xa010800,
   2985         SOC_REG_FLAG_WO |
   2986                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2987         0,
   2988         1,
   2989         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   2990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2991         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2992         -1,
   2993         -1,
   2994         3,
   2995     },
   2996 #endif /* chips */
   2997 
   2998 #if defined(BCM_56970_A0)
   2999     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE3_BCM56970_A0r */
   3000         soc_block_list[5],
   3001         soc_genreg,
   3002         1,
   3003         0,
   3004         0x570c0000,
   3005         SOC_REG_FLAG_WO |
   3006                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3007         0,
   3008         1,
   3009         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   3010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3012         -1,
   3013         -1,
   3014         0,
   3015     },
   3016 #endif /* chips */
   3017 
   3018 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3019     { /* SOC_REG_INT_VFP_CAM_BIST_DBG_DATA_PIPE3_BCM56980_A0r */
   3020         soc_block_list[5],
   3021         soc_genreg,
   3022         1,
   3023         0,
   3024         0xa010800,
   3025         SOC_REG_FLAG_WO |
   3026                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3027         0,
   3028         1,
   3029         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
   3030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3032         -1,
   3033         -1,
   3034         3,
   3035     },
   3036 #endif /* chips */
   3037 
   3038 #if defined(BCM_56514_A0)
   3039     { /* SOC_REG_INT_VFP_CAM_BIST_S10_STATUSr */
   3040         soc_block_list[5],
   3041         soc_genreg,
   3042         1,
   3043         0,
   3044         0x4080015,
   3045         SOC_REG_FLAG_RO,
   3046         0,
   3047         1,
   3048         soc_EFP_CAM_BIST_S10_STATUSr_fields,
   3049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3050         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3051         -1,
   3052         -1,
   3053     },
   3054 #endif /* chips */
   3055 
   3056 #if defined(BCM_56514_A0)
   3057     { /* SOC_REG_INT_VFP_CAM_BIST_S12_STATUSr */
   3058         soc_block_list[5],
   3059         soc_genreg,
   3060         1,
   3061         0,
   3062         0x4080016,
   3063         SOC_REG_FLAG_RO,
   3064         0,
   3065         1,
   3066         soc_EFP_CAM_BIST_S12_STATUSr_fields,
   3067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3068         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3069         -1,
   3070         -1,
   3071     },
   3072 #endif /* chips */
   3073 
   3074 #if defined(BCM_56514_A0)
   3075     { /* SOC_REG_INT_VFP_CAM_BIST_S14_STATUSr */
   3076         soc_block_list[5],
   3077         soc_genreg,
   3078         1,
   3079         0,
   3080         0x4080017,
   3081         SOC_REG_FLAG_RO,
   3082         0,
   3083         1,
   3084         soc_EFP_CAM_BIST_S14_STATUSr_fields,
   3085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3086         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3087         -1,
   3088         -1,
   3089     },
   3090 #endif /* chips */
   3091 
   3092 #if defined(BCM_56514_A0)
   3093     { /* SOC_REG_INT_VFP_CAM_BIST_S15_STATUSr */
   3094         soc_block_list[5],
   3095         soc_genreg,
   3096         1,
   3097         0,
   3098         0x4080018,
   3099         SOC_REG_FLAG_RO,
   3100         0,
   3101         1,
   3102         soc_EFP_CAM_BIST_S15_STATUSr_fields,
   3103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3105         -1,
   3106         -1,
   3107     },
   3108 #endif /* chips */
   3109 
   3110 #if defined(BCM_56514_A0)
   3111     { /* SOC_REG_INT_VFP_CAM_BIST_S2_STATUSr */
   3112         soc_block_list[5],
   3113         soc_genreg,
   3114         1,
   3115         0,
   3116         0x4080010,
   3117         SOC_REG_FLAG_RO,
   3118         0,
   3119         1,
   3120         soc_EFP_CAM_BIST_S2_STATUSr_fields,
   3121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3122         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3123         -1,
   3124         -1,
   3125     },
   3126 #endif /* chips */
   3127 
   3128 #if defined(BCM_56514_A0)
   3129     { /* SOC_REG_INT_VFP_CAM_BIST_S3_STATUSr */
   3130         soc_block_list[5],
   3131         soc_genreg,
   3132         1,
   3133         0,
   3134         0x4080011,
   3135         SOC_REG_FLAG_RO,
   3136         0,
   3137         1,
   3138         soc_EFP_CAM_BIST_S3_STATUSr_fields,
   3139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3140         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3141         -1,
   3142         -1,
   3143     },
   3144 #endif /* chips */
   3145 
   3146 #if defined(BCM_56514_A0)
   3147     { /* SOC_REG_INT_VFP_CAM_BIST_S5_STATUSr */
   3148         soc_block_list[5],
   3149         soc_genreg,
   3150         1,
   3151         0,
   3152         0x4080012,
   3153         SOC_REG_FLAG_RO,
   3154         0,
   3155         1,
   3156         soc_EFP_CAM_BIST_S5_STATUSr_fields,
   3157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3158         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3159         -1,
   3160         -1,
   3161     },
   3162 #endif /* chips */
   3163 
   3164 #if defined(BCM_56514_A0)
   3165     { /* SOC_REG_INT_VFP_CAM_BIST_S6_STATUSr */
   3166         soc_block_list[5],
   3167         soc_genreg,
   3168         1,
   3169         0,
   3170         0x4080013,
   3171         SOC_REG_FLAG_RO,
   3172         0,
   3173         1,
   3174         soc_EFP_CAM_BIST_S6_STATUSr_fields,
   3175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3176         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3177         -1,
   3178         -1,
   3179     },
   3180 #endif /* chips */
   3181 
   3182 #if defined(BCM_56514_A0)
   3183     { /* SOC_REG_INT_VFP_CAM_BIST_S8_STATUSr */
   3184         soc_block_list[5],
   3185         soc_genreg,
   3186         1,
   3187         0,
   3188         0x4080014,
   3189         SOC_REG_FLAG_RO,
   3190         0,
   3191         1,
   3192         soc_EFP_CAM_BIST_S8_STATUSr_fields,
   3193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3194         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3195         -1,
   3196         -1,
   3197     },
   3198 #endif /* chips */
   3199 
   3200 #if defined(BCM_56514_A0)
   3201     { /* SOC_REG_INT_VFP_CAM_BIST_STATUSr */
   3202         soc_block_list[5],
   3203         soc_genreg,
   3204         1,
   3205         0,
   3206         0x4080019,
   3207         SOC_REG_FLAG_RO,
   3208         0,
   3209         2,
   3210         soc_EFP_CAM_BIST_STATUSr_fields,
   3211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3212         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3213         -1,
   3214         -1,
   3215     },
   3216 #endif /* chips */
   3217 
   3218 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3219     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   3220     defined(BCM_56160_A0)
   3221     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM53400_A0r */
   3222         soc_block_list[5],
   3223         soc_genreg,
   3224         1,
   3225         0,
   3226         0xe011900,
   3227         SOC_REG_FLAG_RO,
   3228         0,
   3229         1,
   3230         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3232         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3233         -1,
   3234         -1,
   3235     },
   3236 #endif /* chips */
   3237 
   3238 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   3239     defined(BCM_56270_A0)
   3240     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56260_A0r */
   3241         soc_block_list[5],
   3242         soc_genreg,
   3243         1,
   3244         0,
   3245         0x12011600,
   3246         SOC_REG_FLAG_RO,
   3247         0,
   3248         1,
   3249         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3252         -1,
   3253         -1,
   3254     },
   3255 #endif /* chips */
   3256 
   3257 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   3258     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56334_A0r */
   3259         soc_block_list[5],
   3260         soc_genreg,
   3261         1,
   3262         0,
   3263         0x4080126,
   3264         SOC_REG_FLAG_RO,
   3265         0,
   3266         1,
   3267         soc_EFP_CAM_BIST_STATUS_BCM56624_A0r_fields,
   3268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3269         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3270         -1,
   3271         -1,
   3272     },
   3273 #endif /* chips */
   3274 
   3275 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3276     defined(BCM_56450_B1)
   3277     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56450_A0r */
   3278         soc_block_list[5],
   3279         soc_genreg,
   3280         1,
   3281         0,
   3282         0x12011500,
   3283         SOC_REG_FLAG_RO,
   3284         0,
   3285         1,
   3286         soc_EFP_CAM_BIST_STATUS_BCM56640_A0r_fields,
   3287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3288         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3289         -1,
   3290         -1,
   3291     },
   3292 #endif /* chips */
   3293 
   3294 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   3295     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56560_A0r */
   3296         soc_block_list[5],
   3297         soc_genreg,
   3298         1,
   3299         0,
   3300         0x130a0000,
   3301         SOC_REG_FLAG_RO,
   3302         0,
   3303         1,
   3304         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3307         -1,
   3308         -1,
   3309     },
   3310 #endif /* chips */
   3311 
   3312 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   3313     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   3314     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56624_A0r */
   3315         soc_block_list[5],
   3316         soc_genreg,
   3317         1,
   3318         0,
   3319         0x4080113,
   3320         SOC_REG_FLAG_RO,
   3321         0,
   3322         1,
   3323         soc_EFP_CAM_BIST_STATUS_BCM56624_A0r_fields,
   3324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3326         -1,
   3327         -1,
   3328     },
   3329 #endif /* chips */
   3330 
   3331 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   3332     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   3333     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   3334     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56634_A0r */
   3335         soc_block_list[5],
   3336         soc_genreg,
   3337         1,
   3338         0,
   3339         0x4080145,
   3340         SOC_REG_FLAG_RO,
   3341         0,
   3342         1,
   3343         soc_EFP_CAM_BIST_STATUS_BCM56624_A0r_fields,
   3344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3345         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3346         -1,
   3347         -1,
   3348     },
   3349 #endif /* chips */
   3350 
   3351 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   3352     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56640_A0r */
   3353         soc_block_list[5],
   3354         soc_genreg,
   3355         1,
   3356         0,
   3357         0x12010700,
   3358         SOC_REG_FLAG_RO,
   3359         0,
   3360         1,
   3361         soc_EFP_CAM_BIST_STATUS_BCM56640_A0r_fields,
   3362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3363         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3364         -1,
   3365         -1,
   3366     },
   3367 #endif /* chips */
   3368 
   3369 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   3370     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56670_A0r */
   3371         soc_block_list[5],
   3372         soc_genreg,
   3373         1,
   3374         0,
   3375         0x130b0000,
   3376         SOC_REG_FLAG_RO,
   3377         0,
   3378         1,
   3379         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3381         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3382         -1,
   3383         -1,
   3384     },
   3385 #endif /* chips */
   3386 
   3387 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   3388     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56820_A0r */
   3389         soc_block_list[5],
   3390         soc_genreg,
   3391         1,
   3392         0,
   3393         0x4080c23,
   3394         SOC_REG_FLAG_RO,
   3395         0,
   3396         1,
   3397         soc_EFP_CAM_BIST_STATUS_BCM56624_A0r_fields,
   3398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3399         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3400         -1,
   3401         -1,
   3402     },
   3403 #endif /* chips */
   3404 
   3405 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   3406     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   3407     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56840_A0r */
   3408         soc_block_list[5],
   3409         soc_genreg,
   3410         1,
   3411         0,
   3412         0x4080d14,
   3413         SOC_REG_FLAG_RO,
   3414         0,
   3415         1,
   3416         soc_EFP_CAM_BIST_STATUS_BCM56624_A0r_fields,
   3417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3418         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3419         -1,
   3420         -1,
   3421     },
   3422 #endif /* chips */
   3423 
   3424 #if defined(BCM_56850_A0)
   3425     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56850_A0r */
   3426         soc_block_list[5],
   3427         soc_genreg,
   3428         1,
   3429         0,
   3430         0x130c0000,
   3431         SOC_REG_FLAG_RO |
   3432                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3433         0,
   3434         1,
   3435         soc_EFP_CAM_BIST_STATUS_BCM56640_A0r_fields,
   3436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3437         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3438         -1,
   3439         -1,
   3440     },
   3441 #endif /* chips */
   3442 
   3443 #if defined(BCM_56860_A0)
   3444     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56860_A0r */
   3445         soc_block_list[5],
   3446         soc_genreg,
   3447         1,
   3448         0,
   3449         0x130a0000,
   3450         SOC_REG_FLAG_RO |
   3451                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3452         0,
   3453         1,
   3454         soc_EFP_CAM_BIST_STATUS_BCM56640_A0r_fields,
   3455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3456         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3457         -1,
   3458         -1,
   3459     },
   3460 #endif /* chips */
   3461 
   3462 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   3463     defined(BCM_56870_A0)
   3464     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56870_A0r */
   3465         soc_block_list[5],
   3466         soc_genreg,
   3467         1,
   3468         0,
   3469         0x57040000,
   3470         SOC_REG_FLAG_RO |
   3471                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3472         0,
   3473         1,
   3474         soc_CPU_COS_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3476         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3477         -1,
   3478         -1,
   3479         0,
   3480     },
   3481 #endif /* chips */
   3482 
   3483 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3484     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56960_A0r */
   3485         soc_block_list[5],
   3486         soc_genreg,
   3487         1,
   3488         0,
   3489         0x33080000,
   3490         SOC_REG_FLAG_RO |
   3491                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3492         0,
   3493         1,
   3494         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3496         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3497         -1,
   3498         -1,
   3499         0,
   3500     },
   3501 #endif /* chips */
   3502 
   3503 #if defined(BCM_56970_A0)
   3504     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56970_A0r */
   3505         soc_block_list[5],
   3506         soc_genreg,
   3507         1,
   3508         0,
   3509         0x57080000,
   3510         SOC_REG_FLAG_RO |
   3511                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3512         0,
   3513         1,
   3514         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3516         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3517         -1,
   3518         -1,
   3519         0,
   3520     },
   3521 #endif /* chips */
   3522 
   3523 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3524     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_BCM56980_A0r */
   3525         soc_block_list[5],
   3526         soc_genreg,
   3527         1,
   3528         0,
   3529         0xa010900,
   3530         SOC_REG_FLAG_RO |
   3531                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3532         0,
   3533         1,
   3534         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3536         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3537         -1,
   3538         -1,
   3539         3,
   3540     },
   3541 #endif /* chips */
   3542 
   3543 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3544     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE0r */
   3545         soc_block_list[5],
   3546         soc_genreg,
   3547         1,
   3548         0,
   3549         0x33080000,
   3550         SOC_REG_FLAG_RO,
   3551         0,
   3552         1,
   3553         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3556         -1,
   3557         -1,
   3558         0,
   3559     },
   3560 #endif /* chips */
   3561 
   3562 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3563     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE1r */
   3564         soc_block_list[5],
   3565         soc_genreg,
   3566         1,
   3567         0,
   3568         0x33080000,
   3569         SOC_REG_FLAG_RO |
   3570                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3571         0,
   3572         1,
   3573         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3575         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3576         -1,
   3577         -1,
   3578         0,
   3579     },
   3580 #endif /* chips */
   3581 
   3582 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3583     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE2r */
   3584         soc_block_list[5],
   3585         soc_genreg,
   3586         1,
   3587         0,
   3588         0x33080000,
   3589         SOC_REG_FLAG_RO |
   3590                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3591         0,
   3592         1,
   3593         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3595         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3596         -1,
   3597         -1,
   3598         0,
   3599     },
   3600 #endif /* chips */
   3601 
   3602 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3603     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE3r */
   3604         soc_block_list[5],
   3605         soc_genreg,
   3606         1,
   3607         0,
   3608         0x33080000,
   3609         SOC_REG_FLAG_RO |
   3610                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3611         0,
   3612         1,
   3613         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3616         -1,
   3617         -1,
   3618         0,
   3619     },
   3620 #endif /* chips */
   3621 
   3622 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3623     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE4r */
   3624         soc_block_list[5],
   3625         soc_genreg,
   3626         1,
   3627         0,
   3628         0xa010900,
   3629         SOC_REG_FLAG_RO |
   3630                           (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3631         0,
   3632         1,
   3633         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3635         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3636         -1,
   3637         -1,
   3638         3,
   3639     },
   3640 #endif /* chips */
   3641 
   3642 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3643     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE5r */
   3644         soc_block_list[5],
   3645         soc_genreg,
   3646         1,
   3647         0,
   3648         0xa010900,
   3649         SOC_REG_FLAG_RO |
   3650                           (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3651         0,
   3652         1,
   3653         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3655         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3656         -1,
   3657         -1,
   3658         3,
   3659     },
   3660 #endif /* chips */
   3661 
   3662 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3663     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE6r */
   3664         soc_block_list[5],
   3665         soc_genreg,
   3666         1,
   3667         0,
   3668         0xa010900,
   3669         SOC_REG_FLAG_RO |
   3670                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3671         0,
   3672         1,
   3673         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3675         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3676         -1,
   3677         -1,
   3678         3,
   3679     },
   3680 #endif /* chips */
   3681 
   3682 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3683     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE7r */
   3684         soc_block_list[5],
   3685         soc_genreg,
   3686         1,
   3687         0,
   3688         0xa010900,
   3689         SOC_REG_FLAG_RO |
   3690                           (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3691         0,
   3692         1,
   3693         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3695         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3696         -1,
   3697         -1,
   3698         3,
   3699     },
   3700 #endif /* chips */
   3701 
   3702 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   3703     defined(BCM_56870_A0)
   3704     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE0_BCM56870_A0r */
   3705         soc_block_list[5],
   3706         soc_genreg,
   3707         1,
   3708         0,
   3709         0x57040000,
   3710         SOC_REG_FLAG_RO,
   3711         0,
   3712         1,
   3713         soc_CPU_COS_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3715         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3716         -1,
   3717         -1,
   3718         0,
   3719     },
   3720 #endif /* chips */
   3721 
   3722 #if defined(BCM_56970_A0)
   3723     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE0_BCM56970_A0r */
   3724         soc_block_list[5],
   3725         soc_genreg,
   3726         1,
   3727         0,
   3728         0x57080000,
   3729         SOC_REG_FLAG_RO,
   3730         0,
   3731         1,
   3732         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3734         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3735         -1,
   3736         -1,
   3737         0,
   3738     },
   3739 #endif /* chips */
   3740 
   3741 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3742     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE0_BCM56980_A0r */
   3743         soc_block_list[5],
   3744         soc_genreg,
   3745         1,
   3746         0,
   3747         0xa010900,
   3748         SOC_REG_FLAG_RO,
   3749         0,
   3750         1,
   3751         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3754         -1,
   3755         -1,
   3756         3,
   3757     },
   3758 #endif /* chips */
   3759 
   3760 #if defined(BCM_56870_A0)
   3761     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE1_BCM56870_A0r */
   3762         soc_block_list[5],
   3763         soc_genreg,
   3764         1,
   3765         0,
   3766         0x57040000,
   3767         SOC_REG_FLAG_RO |
   3768                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3769         0,
   3770         1,
   3771         soc_CPU_COS_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3773         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3774         -1,
   3775         -1,
   3776         0,
   3777     },
   3778 #endif /* chips */
   3779 
   3780 #if defined(BCM_56970_A0)
   3781     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE1_BCM56970_A0r */
   3782         soc_block_list[5],
   3783         soc_genreg,
   3784         1,
   3785         0,
   3786         0x57080000,
   3787         SOC_REG_FLAG_RO |
   3788                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3789         0,
   3790         1,
   3791         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3793         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3794         -1,
   3795         -1,
   3796         0,
   3797     },
   3798 #endif /* chips */
   3799 
   3800 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3801     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE1_BCM56980_A0r */
   3802         soc_block_list[5],
   3803         soc_genreg,
   3804         1,
   3805         0,
   3806         0xa010900,
   3807         SOC_REG_FLAG_RO |
   3808                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3809         0,
   3810         1,
   3811         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3814         -1,
   3815         -1,
   3816         3,
   3817     },
   3818 #endif /* chips */
   3819 
   3820 #if defined(BCM_56970_A0)
   3821     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE2_BCM56970_A0r */
   3822         soc_block_list[5],
   3823         soc_genreg,
   3824         1,
   3825         0,
   3826         0x57080000,
   3827         SOC_REG_FLAG_RO |
   3828                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3829         0,
   3830         1,
   3831         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3833         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3834         -1,
   3835         -1,
   3836         0,
   3837     },
   3838 #endif /* chips */
   3839 
   3840 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3841     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE2_BCM56980_A0r */
   3842         soc_block_list[5],
   3843         soc_genreg,
   3844         1,
   3845         0,
   3846         0xa010900,
   3847         SOC_REG_FLAG_RO |
   3848                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3849         0,
   3850         1,
   3851         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3853         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3854         -1,
   3855         -1,
   3856         3,
   3857     },
   3858 #endif /* chips */
   3859 
   3860 #if defined(BCM_56970_A0)
   3861     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE3_BCM56970_A0r */
   3862         soc_block_list[5],
   3863         soc_genreg,
   3864         1,
   3865         0,
   3866         0x57080000,
   3867         SOC_REG_FLAG_RO |
   3868                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3869         0,
   3870         1,
   3871         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3873         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3874         -1,
   3875         -1,
   3876         0,
   3877     },
   3878 #endif /* chips */
   3879 
   3880 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3881     { /* SOC_REG_INT_VFP_CAM_BIST_STATUS_PIPE3_BCM56980_A0r */
   3882         soc_block_list[5],
   3883         soc_genreg,
   3884         1,
   3885         0,
   3886         0xa010900,
   3887         SOC_REG_FLAG_RO |
   3888                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3889         0,
   3890         1,
   3891         soc_EFP_CAM_BIST_STATUS_BCM53400_A0r_fields,
   3892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3893         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3894         -1,
   3895         -1,
   3896         3,
   3897     },
   3898 #endif /* chips */
   3899 
   3900 #if defined(BCM_56514_A0)
   3901     { /* SOC_REG_INT_VFP_CAM_CONTROL_3_THRU_0r */
   3902         soc_block_list[5],
   3903         soc_genreg,
   3904         1,
   3905         0,
   3906         0x408001c,
   3907         0,
   3908         0,
   3909         4,
   3910         soc_VFP_CAM_CONTROL_3_THRU_0r_fields,
   3911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3912         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3913         -1,
   3914         -1,
   3915     },
   3916 #endif /* chips */
   3917 
   3918 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   3919     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   3920     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0r */
   3921         soc_block_list[5],
   3922         soc_genreg,
   3923         1,
   3924         0,
   3925         0x4080115,
   3926         0,
   3927         0,
   3928         8,
   3929         soc_VFP_CAM_CONTROL_SLICE_3_0r_fields,
   3930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3931         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3932         -1,
   3933         -1,
   3934     },
   3935 #endif /* chips */
   3936 
   3937 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3938     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   3939     defined(BCM_56160_A0)
   3940     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_64r */
   3941         soc_block_list[5],
   3942         soc_genreg,
   3943         1,
   3944         0,
   3945         0xe011b00,
   3946         SOC_REG_FLAG_64_BITS,
   3947         0,
   3948         4,
   3949         soc_VFP_CAM_CONTROL_SLICE_3_0_64r_fields,
   3950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3951         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3952         -1,
   3953         -1,
   3954     },
   3955 #endif /* chips */
   3956 
   3957 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   3958     defined(BCM_56270_A0)
   3959     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56260_A0r */
   3960         soc_block_list[5],
   3961         soc_genreg,
   3962         1,
   3963         0,
   3964         0x12011800,
   3965         0,
   3966         0,
   3967         1,
   3968         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56960_A0r_fields,
   3969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3970         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3971         -1,
   3972         -1,
   3973     },
   3974 #endif /* chips */
   3975 
   3976 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   3977     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56334_A0r */
   3978         soc_block_list[5],
   3979         soc_genreg,
   3980         1,
   3981         0,
   3982         0x4080128,
   3983         0,
   3984         0,
   3985         8,
   3986         soc_VFP_CAM_CONTROL_SLICE_3_0r_fields,
   3987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3988         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3989         -1,
   3990         -1,
   3991     },
   3992 #endif /* chips */
   3993 
   3994 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3995     defined(BCM_56450_B1)
   3996     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56450_A0r */
   3997         soc_block_list[5],
   3998         soc_genreg,
   3999         1,
   4000         0,
   4001         0x12011700,
   4002         0,
   4003         0,
   4004         1,
   4005         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r_fields,
   4006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4007         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4008         -1,
   4009         -1,
   4010     },
   4011 #endif /* chips */
   4012 
   4013 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   4014     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56560_A0r */
   4015         soc_block_list[5],
   4016         soc_genreg,
   4017         1,
   4018         0,
   4019         0x130c0000,
   4020         0,
   4021         0,
   4022         1,
   4023         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56960_A0r_fields,
   4024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4025         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4026         -1,
   4027         -1,
   4028     },
   4029 #endif /* chips */
   4030 
   4031 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   4032     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   4033     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   4034     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56634_A0r */
   4035         soc_block_list[5],
   4036         soc_genreg,
   4037         1,
   4038         0,
   4039         0x4080147,
   4040         0,
   4041         0,
   4042         8,
   4043         soc_VFP_CAM_CONTROL_SLICE_3_0r_fields,
   4044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4045         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4046         -1,
   4047         -1,
   4048     },
   4049 #endif /* chips */
   4050 
   4051 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   4052     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r */
   4053         soc_block_list[5],
   4054         soc_genreg,
   4055         1,
   4056         0,
   4057         0x12010a00,
   4058         0,
   4059         0,
   4060         1,
   4061         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r_fields,
   4062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4063         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4064         -1,
   4065         -1,
   4066     },
   4067 #endif /* chips */
   4068 
   4069 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   4070     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56670_A0r */
   4071         soc_block_list[5],
   4072         soc_genreg,
   4073         1,
   4074         0,
   4075         0x130d0000,
   4076         0,
   4077         0,
   4078         1,
   4079         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56960_A0r_fields,
   4080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4081         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4082         -1,
   4083         -1,
   4084     },
   4085 #endif /* chips */
   4086 
   4087 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   4088     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56820_A0r */
   4089         soc_block_list[5],
   4090         soc_genreg,
   4091         1,
   4092         0,
   4093         0x4080c2d,
   4094         0,
   4095         0,
   4096         8,
   4097         soc_VFP_CAM_CONTROL_SLICE_3_0r_fields,
   4098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4099         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4100         -1,
   4101         -1,
   4102     },
   4103 #endif /* chips */
   4104 
   4105 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   4106     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   4107     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56840_A0r */
   4108         soc_block_list[5],
   4109         soc_genreg,
   4110         1,
   4111         0,
   4112         0x4080d16,
   4113         0,
   4114         0,
   4115         1,
   4116         soc_FP_CAM_CONTROL_SLICE_3_0r_fields,
   4117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4118         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4119         -1,
   4120         -1,
   4121     },
   4122 #endif /* chips */
   4123 
   4124 #if defined(BCM_56850_A0)
   4125     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56850_A0r */
   4126         soc_block_list[5],
   4127         soc_genreg,
   4128         1,
   4129         0,
   4130         0x130e0000,
   4131         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4132         0,
   4133         1,
   4134         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r_fields,
   4135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4136         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4137         -1,
   4138         -1,
   4139     },
   4140 #endif /* chips */
   4141 
   4142 #if defined(BCM_56860_A0)
   4143     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56860_A0r */
   4144         soc_block_list[5],
   4145         soc_genreg,
   4146         1,
   4147         0,
   4148         0x130c0000,
   4149         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4150         0,
   4151         1,
   4152         soc_FP_CAM_CONTROL_SLICE_11_4r_fields,
   4153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4154         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4155         -1,
   4156         -1,
   4157     },
   4158 #endif /* chips */
   4159 
   4160 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   4161     defined(BCM_56870_A0)
   4162     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56870_A0r */
   4163         soc_block_list[5],
   4164         soc_genreg,
   4165         1,
   4166         0,
   4167         0x57050000,
   4168         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4169         0,
   4170         7,
   4171         soc_DST_COMPRESSION_CAM_DBGCTRL_BCM56870_A0r_fields,
   4172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4174         -1,
   4175         -1,
   4176         0,
   4177     },
   4178 #endif /* chips */
   4179 
   4180 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   4181     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56960_A0r */
   4182         soc_block_list[5],
   4183         soc_genreg,
   4184         1,
   4185         0,
   4186         0x330a0000,
   4187         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4188         0,
   4189         1,
   4190         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56960_A0r_fields,
   4191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4192         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4193         -1,
   4194         -1,
   4195         0,
   4196     },
   4197 #endif /* chips */
   4198 
   4199 #if defined(BCM_56970_A0)
   4200     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56970_A0r */
   4201         soc_block_list[5],
   4202         soc_genreg,
   4203         1,
   4204         0,
   4205         0x570a0000,
   4206         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4207         0,
   4208         2,
   4209         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56970_A0r_fields,
   4210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4211         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4212         -1,
   4213         -1,
   4214         0,
   4215     },
   4216 #endif /* chips */
   4217 
   4218 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4219     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_BCM56980_A0r */
   4220         soc_block_list[5],
   4221         soc_genreg,
   4222         1,
   4223         0,
   4224         0xa010a00,
   4225         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4226         0,
   4227         3,
   4228         soc_CPU_COS_MAP_CAM_CONTROLr_fields,
   4229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4230         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4231         -1,
   4232         -1,
   4233         3,
   4234     },
   4235 #endif /* chips */
   4236 
   4237 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   4238     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE0r */
   4239         soc_block_list[5],
   4240         soc_genreg,
   4241         1,
   4242         0,
   4243         0x330a0000,
   4244         0,
   4245         0,
   4246         1,
   4247         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56960_A0r_fields,
   4248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4250         -1,
   4251         -1,
   4252         0,
   4253     },
   4254 #endif /* chips */
   4255 
   4256 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   4257     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE1r */
   4258         soc_block_list[5],
   4259         soc_genreg,
   4260         1,
   4261         0,
   4262         0x330a0000,
   4263         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4264         0,
   4265         1,
   4266         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56960_A0r_fields,
   4267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4268         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4269         -1,
   4270         -1,
   4271         0,
   4272     },
   4273 #endif /* chips */
   4274 
   4275 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   4276     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE2r */
   4277         soc_block_list[5],
   4278         soc_genreg,
   4279         1,
   4280         0,
   4281         0x330a0000,
   4282         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4283         0,
   4284         1,
   4285         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56960_A0r_fields,
   4286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4287         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4288         -1,
   4289         -1,
   4290         0,
   4291     },
   4292 #endif /* chips */
   4293 
   4294 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   4295     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE3r */
   4296         soc_block_list[5],
   4297         soc_genreg,
   4298         1,
   4299         0,
   4300         0x330a0000,
   4301         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4302         0,
   4303         1,
   4304         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56960_A0r_fields,
   4305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4307         -1,
   4308         -1,
   4309         0,
   4310     },
   4311 #endif /* chips */
   4312 
   4313 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4314     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE4r */
   4315         soc_block_list[5],
   4316         soc_genreg,
   4317         1,
   4318         0,
   4319         0xa010a00,
   4320         (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4321         0,
   4322         3,
   4323         soc_CPU_COS_MAP_CAM_CONTROLr_fields,
   4324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4326         -1,
   4327         -1,
   4328         3,
   4329     },
   4330 #endif /* chips */
   4331 
   4332 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4333     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE5r */
   4334         soc_block_list[5],
   4335         soc_genreg,
   4336         1,
   4337         0,
   4338         0xa010a00,
   4339         (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4340         0,
   4341         3,
   4342         soc_CPU_COS_MAP_CAM_CONTROLr_fields,
   4343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4344         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4345         -1,
   4346         -1,
   4347         3,
   4348     },
   4349 #endif /* chips */
   4350 
   4351 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4352     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE6r */
   4353         soc_block_list[5],
   4354         soc_genreg,
   4355         1,
   4356         0,
   4357         0xa010a00,
   4358         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4359         0,
   4360         3,
   4361         soc_CPU_COS_MAP_CAM_CONTROLr_fields,
   4362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4363         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4364         -1,
   4365         -1,
   4366         3,
   4367     },
   4368 #endif /* chips */
   4369 
   4370 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4371     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE7r */
   4372         soc_block_list[5],
   4373         soc_genreg,
   4374         1,
   4375         0,
   4376         0xa010a00,
   4377         (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4378         0,
   4379         3,
   4380         soc_CPU_COS_MAP_CAM_CONTROLr_fields,
   4381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4382         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4383         -1,
   4384         -1,
   4385         3,
   4386     },
   4387 #endif /* chips */
   4388 
   4389 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   4390     defined(BCM_56870_A0)
   4391     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE0_BCM56870_A0r */
   4392         soc_block_list[5],
   4393         soc_genreg,
   4394         1,
   4395         0,
   4396         0x57050000,
   4397         0,
   4398         0,
   4399         7,
   4400         soc_DST_COMPRESSION_CAM_DBGCTRL_BCM56870_A0r_fields,
   4401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4402         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4403         -1,
   4404         -1,
   4405         0,
   4406     },
   4407 #endif /* chips */
   4408 
   4409 #if defined(BCM_56970_A0)
   4410     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE0_BCM56970_A0r */
   4411         soc_block_list[5],
   4412         soc_genreg,
   4413         1,
   4414         0,
   4415         0x570a0000,
   4416         0,
   4417         0,
   4418         2,
   4419         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56970_A0r_fields,
   4420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4421         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4422         -1,
   4423         -1,
   4424         0,
   4425     },
   4426 #endif /* chips */
   4427 
   4428 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4429     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE0_BCM56980_A0r */
   4430         soc_block_list[5],
   4431         soc_genreg,
   4432         1,
   4433         0,
   4434         0xa010a00,
   4435         0,
   4436         0,
   4437         3,
   4438         soc_CPU_COS_MAP_CAM_CONTROLr_fields,
   4439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4440         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4441         -1,
   4442         -1,
   4443         3,
   4444     },
   4445 #endif /* chips */
   4446 
   4447 #if defined(BCM_56870_A0)
   4448     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE1_BCM56870_A0r */
   4449         soc_block_list[5],
   4450         soc_genreg,
   4451         1,
   4452         0,
   4453         0x57050000,
   4454         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4455         0,
   4456         7,
   4457         soc_DST_COMPRESSION_CAM_DBGCTRL_BCM56870_A0r_fields,
   4458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4459         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4460         -1,
   4461         -1,
   4462         0,
   4463     },
   4464 #endif /* chips */
   4465 
   4466 #if defined(BCM_56970_A0)
   4467     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE1_BCM56970_A0r */
   4468         soc_block_list[5],
   4469         soc_genreg,
   4470         1,
   4471         0,
   4472         0x570a0000,
   4473         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4474         0,
   4475         2,
   4476         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56970_A0r_fields,
   4477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4478         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4479         -1,
   4480         -1,
   4481         0,
   4482     },
   4483 #endif /* chips */
   4484 
   4485 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4486     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE1_BCM56980_A0r */
   4487         soc_block_list[5],
   4488         soc_genreg,
   4489         1,
   4490         0,
   4491         0xa010a00,
   4492         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4493         0,
   4494         3,
   4495         soc_CPU_COS_MAP_CAM_CONTROLr_fields,
   4496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4497         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4498         -1,
   4499         -1,
   4500         3,
   4501     },
   4502 #endif /* chips */
   4503 
   4504 #if defined(BCM_56970_A0)
   4505     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE2_BCM56970_A0r */
   4506         soc_block_list[5],
   4507         soc_genreg,
   4508         1,
   4509         0,
   4510         0x570a0000,
   4511         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4512         0,
   4513         2,
   4514         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56970_A0r_fields,
   4515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4516         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4517         -1,
   4518         -1,
   4519         0,
   4520     },
   4521 #endif /* chips */
   4522 
   4523 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4524     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE2_BCM56980_A0r */
   4525         soc_block_list[5],
   4526         soc_genreg,
   4527         1,
   4528         0,
   4529         0xa010a00,
   4530         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4531         0,
   4532         3,
   4533         soc_CPU_COS_MAP_CAM_CONTROLr_fields,
   4534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4535         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4536         -1,
   4537         -1,
   4538         3,
   4539     },
   4540 #endif /* chips */
   4541 
   4542 #if defined(BCM_56970_A0)
   4543     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE3_BCM56970_A0r */
   4544         soc_block_list[5],
   4545         soc_genreg,
   4546         1,
   4547         0,
   4548         0x570a0000,
   4549         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4550         0,
   4551         2,
   4552         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56970_A0r_fields,
   4553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4554         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4555         -1,
   4556         -1,
   4557         0,
   4558     },
   4559 #endif /* chips */
   4560 
   4561 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4562     { /* SOC_REG_INT_VFP_CAM_CONTROL_SLICE_3_0_PIPE3_BCM56980_A0r */
   4563         soc_block_list[5],
   4564         soc_genreg,
   4565         1,
   4566         0,
   4567         0xa010a00,
   4568         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4569         0,
   4570         3,
   4571         soc_CPU_COS_MAP_CAM_CONTROLr_fields,
   4572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4573         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4574         -1,
   4575         -1,
   4576         3,
   4577     },
   4578 #endif /* chips */
   4579 
   4580 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   4581     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   4582     { /* SOC_REG_INT_VFP_CAM_CONTROL_TM_7_THRU_0r */
   4583         soc_block_list[5],
   4584         soc_genreg,
   4585         1,
   4586         0,
   4587         0x4080118,
   4588         0,
   4589         0,
   4590         1,
   4591         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
   4592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4593         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4594         -1,
   4595         -1,
   4596     },
   4597 #endif /* chips */
   4598 
   4599 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   4600     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   4601     defined(BCM_56160_A0)
   4602     { /* SOC_REG_INT_VFP_CAM_CONTROL_TM_7_THRU_0_BCM53400_A0r */
   4603         soc_block_list[5],
   4604         soc_genreg,
   4605         1,
   4606         0,
   4607         0xe011e00,
   4608         0,
   4609         0,
   4610         1,
   4611         soc_VFP_CAM_CONTROL_TM_7_THRU_0r_fields,
   4612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4613         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4614         -1,
   4615         -1,
   4616     },
   4617 #endif /* chips */
   4618 
   4619 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   4620     { /* SOC_REG_INT_VFP_CAM_CONTROL_TM_7_THRU_0_BCM56334_A0r */
   4621         soc_block_list[5],
   4622         soc_genreg,
   4623         1,
   4624         0,
   4625         0x408012b,
   4626         0,
   4627         0,
   4628         1,
   4629         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
   4630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4632         -1,
   4633         -1,
   4634     },
   4635 #endif /* chips */
   4636 
   4637 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   4638     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   4639     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   4640     { /* SOC_REG_INT_VFP_CAM_CONTROL_TM_7_THRU_0_BCM56634_A0r */
   4641         soc_block_list[5],
   4642         soc_genreg,
   4643         1,
   4644         0,
   4645         0x408014a,
   4646         0,
   4647         0,
   4648         1,
   4649         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
   4650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4652         -1,
   4653         -1,
   4654     },
   4655 #endif /* chips */
   4656 
   4657 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   4658     { /* SOC_REG_INT_VFP_CAM_CONTROL_TM_7_THRU_0_BCM56820_A0r */
   4659         soc_block_list[5],
   4660         soc_genreg,
   4661         1,
   4662         0,
   4663         0x4080c37,
   4664         0,
   4665         0,
   4666         1,
   4667         soc_CBPCELLHDRMEMDEBUG_BCM56800_A0r_fields,
   4668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4669         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4670         -1,
   4671         -1,
   4672     },
   4673 #endif /* chips */
   4674 
   4675 #if defined(BCM_56514_A0)
   4676     { /* SOC_REG_INT_VFP_CAM_DEBUG_DATA_0r */
   4677         soc_block_list[5],
   4678         soc_genreg,
   4679         1,
   4680         0,
   4681         0x408001d,
   4682         SOC_REG_FLAG_WO,
   4683         0,
   4684         1,
   4685         soc_FP_CAM_DEBUG_DATA_0r_fields,
   4686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4687         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4688         -1,
   4689         -1,
   4690     },
   4691 #endif /* chips */
   4692 
   4693 #if defined(BCM_56514_A0)
   4694     { /* SOC_REG_INT_VFP_CAM_DEBUG_DATA_1r */
   4695         soc_block_list[5],
   4696         soc_genreg,
   4697         1,
   4698         0,
   4699         0x408001e,
   4700         SOC_REG_FLAG_WO,
   4701         0,
   4702         1,
   4703         soc_FP_CAM_DEBUG_DATA_0r_fields,
   4704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4706         -1,
   4707         -1,
   4708     },
   4709 #endif /* chips */
   4710 
   4711 #if defined(BCM_56514_A0)
   4712     { /* SOC_REG_INT_VFP_CAM_DEBUG_DATA_2r */
   4713         soc_block_list[5],
   4714         soc_genreg,
   4715         1,
   4716         0,
   4717         0x408001f,
   4718         SOC_REG_FLAG_WO,
   4719         0,
   4720         1,
   4721         soc_FP_CAM_DEBUG_DATA_0r_fields,
   4722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4723         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4724         -1,
   4725         -1,
   4726     },
   4727 #endif /* chips */
   4728 
   4729 #if defined(BCM_56514_A0)
   4730     { /* SOC_REG_INT_VFP_CAM_DEBUG_DATA_3r */
   4731         soc_block_list[5],
   4732         soc_genreg,
   4733         1,
   4734         0,
   4735         0x4080020,
   4736         SOC_REG_FLAG_WO,
   4737         0,
   4738         1,
   4739         soc_FP_CAM_DEBUG_DATA_0r_fields,
   4740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4741         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4742         -1,
   4743         -1,
   4744     },
   4745 #endif /* chips */
   4746 
   4747 #if defined(BCM_56514_A0)
   4748     { /* SOC_REG_INT_VFP_CAM_DEBUG_DATA_4r */
   4749         soc_block_list[5],
   4750         soc_genreg,
   4751         1,
   4752         0,
   4753         0x4080021,
   4754         SOC_REG_FLAG_WO,
   4755         0,
   4756         1,
   4757         soc_FP_CAM_DEBUG_DATA_0r_fields,
   4758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4760         -1,
   4761         -1,
   4762     },
   4763 #endif /* chips */
   4764 
   4765 #if defined(BCM_56514_A0)
   4766     { /* SOC_REG_INT_VFP_CAM_DEBUG_DATA_5r */
   4767         soc_block_list[5],
   4768         soc_genreg,
   4769         1,
   4770         0,
   4771         0x4080022,
   4772         SOC_REG_FLAG_WO,
   4773         0,
   4774         1,
   4775         soc_FP_CAM_DEBUG_DATA_5r_fields,
   4776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4777         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4778         -1,
   4779         -1,
   4780     },
   4781 #endif /* chips */
   4782 
   4783 #if defined(BCM_56514_A0)
   4784     { /* SOC_REG_INT_VFP_CAM_DEBUG_GLOBAL_MASKr */
   4785         soc_block_list[5],
   4786         soc_genreg,
   4787         1,
   4788         0,
   4789         0x4080023,
   4790         SOC_REG_FLAG_WO,
   4791         0,
   4792         1,
   4793         soc_FP_CAM_DEBUG_DATA_0r_fields,
   4794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4795         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4796         -1,
   4797         -1,
   4798     },
   4799 #endif /* chips */
   4800 
   4801 #if defined(BCM_56514_A0)
   4802     { /* SOC_REG_INT_VFP_CAM_DEBUG_SENDr */
   4803         soc_block_list[5],
   4804         soc_genreg,
   4805         1,
   4806         0,
   4807         0x4080024,
   4808         SOC_REG_FLAG_WO,
   4809         0,
   4810         1,
   4811         soc_FP_CAM_DEBUG_SENDr_fields,
   4812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4814         -1,
   4815         -1,
   4816     },
   4817 #endif /* chips */
   4818 
   4819 #if defined(BCM_56970_A0)
   4820     { /* SOC_REG_INT_VFP_CAM_SER_CONTROLr */
   4821         soc_block_list[5],
   4822         soc_genreg,
   4823         1,
   4824         0,
   4825         0x570b0000,
   4826         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4827         0,
   4828         2,
   4829         soc_IFP_TCAM_CAM_CONTROLr_fields,
   4830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4831         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4832         -1,
   4833         -1,
   4834         0,
   4835     },
   4836 #endif /* chips */
   4837 
   4838 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4839     { /* SOC_REG_INT_VFP_CAM_SER_CONTROL_BCM56980_A0r */
   4840         soc_block_list[5],
   4841         soc_genreg,
   4842         1,
   4843         0,
   4844         0xa010b00,
   4845         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   4846         0,
   4847         4,
   4848         soc_CPU_COS_CAM_SERCTRL_BCM56980_A0r_fields,
   4849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4850         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   4851         -1,
   4852         -1,
   4853         3,
   4854     },
   4855 #endif /* chips */
   4856 
   4857 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   4858     { /* SOC_REG_INT_VFP_FLEX_COUNTER_STRENGTHr */
   4859         soc_block_list[5],
   4860         soc_genreg,
   4861         1,
   4862         0,
   4863         0x12004600,
   4864         0,
   4865         0,
   4866         1,
   4867         soc_L2_ENTRY_FLEX_COUNTER_STRENGTHr_fields,
   4868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4869         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4870         -1,
   4871         -1,
   4872     },
   4873 #endif /* chips */
   4874 
   4875 #if defined(BCM_56514_A0)
   4876     { /* SOC_REG_INT_VFP_KEY_CONTROLr */
   4877         soc_block_list[5],
   4878         soc_genreg,
   4879         1,
   4880         0,
   4881         0x4080025,
   4882         0,
   4883         0,
   4884         16,
   4885         soc_VFP_KEY_CONTROLr_fields,
   4886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4887         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
   4888         -1,
   4889         -1,
   4890     },
   4891 #endif /* chips */
   4892 
   4893 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   4894     { /* SOC_REG_INT_VFP_KEY_CONTROL_1r */
   4895         soc_block_list[5],
   4896         soc_genreg,
   4897         1,
   4898         0,
   4899         0x12000300,
   4900         SOC_REG_FLAG_64_BITS,
   4901         0,
   4902         22,
   4903         soc_VFP_KEY_CONTROL_1r_fields,
   4904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4905         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   4906         -1,
   4907         -1,
   4908     },
   4909 #endif /* chips */
   4910 
   4911 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   4912     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   4913     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   4914     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   4915     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   4916     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   4917     { /* SOC_REG_INT_VFP_KEY_CONTROL_2r */
   4918         soc_block_list[5],
   4919         soc_genreg,
   4920         1,
   4921         0,
   4922         0x4080022,
   4923         0,
   4924         0,
   4925         4,
   4926         soc_VFP_KEY_CONTROL_2r_fields,
   4927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4928         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4929         -1,
   4930         -1,
   4931     },
   4932 #endif /* chips */
   4933 
   4934 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   4935     defined(BCM_56270_A0)
   4936     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_BCM56260_A0r */
   4937         soc_block_list[5],
   4938         soc_genreg,
   4939         1,
   4940         0,
   4941         0x12000300,
   4942         SOC_REG_FLAG_64_BITS,
   4943         0,
   4944         22,
   4945         soc_VFP_KEY_CONTROL_1_BCM56260_A0r_fields,
   4946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4947         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   4948         -1,
   4949         -1,
   4950     },
   4951 #endif /* chips */
   4952 
   4953 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4954     defined(BCM_56450_B1)
   4955     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_BCM56450_A0r */
   4956         soc_block_list[5],
   4957         soc_genreg,
   4958         1,
   4959         0,
   4960         0x12000300,
   4961         SOC_REG_FLAG_64_BITS,
   4962         0,
   4963         22,
   4964         soc_VFP_KEY_CONTROL_1_BCM56450_A0r_fields,
   4965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4966         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   4967         -1,
   4968         -1,
   4969     },
   4970 #endif /* chips */
   4971 
   4972 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   4973     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   4974     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_BCM56560_A0r */
   4975         soc_block_list[5],
   4976         soc_genreg,
   4977         1,
   4978         0,
   4979         0x12002100,
   4980         SOC_REG_FLAG_64_BITS,
   4981         0,
   4982         22,
   4983         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   4984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4985         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   4986         -1,
   4987         -1,
   4988     },
   4989 #endif /* chips */
   4990 
   4991 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   4992     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_BCM56850_A0r */
   4993         soc_block_list[5],
   4994         soc_genreg,
   4995         1,
   4996         0,
   4997         0x12002100,
   4998         SOC_REG_FLAG_64_BITS |
   4999                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5000         0,
   5001         22,
   5002         soc_VFP_KEY_CONTROL_1r_fields,
   5003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5004         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5005         -1,
   5006         -1,
   5007     },
   5008 #endif /* chips */
   5009 
   5010 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   5011     defined(BCM_56870_A0)
   5012     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_BCM56870_A0r */
   5013         soc_block_list[5],
   5014         soc_genreg,
   5015         1,
   5016         0,
   5017         0x56002900,
   5018         SOC_REG_FLAG_64_BITS |
   5019                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5020         0,
   5021         22,
   5022         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5024         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5025         -1,
   5026         -1,
   5027         0,
   5028     },
   5029 #endif /* chips */
   5030 
   5031 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5032     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_BCM56960_A0r */
   5033         soc_block_list[5],
   5034         soc_genreg,
   5035         1,
   5036         0,
   5037         0x32000300,
   5038         SOC_REG_FLAG_64_BITS |
   5039                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5040         0,
   5041         22,
   5042         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5044         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5045         -1,
   5046         -1,
   5047         0,
   5048     },
   5049 #endif /* chips */
   5050 
   5051 #if defined(BCM_56970_A0)
   5052     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_BCM56970_A0r */
   5053         soc_block_list[5],
   5054         soc_genreg,
   5055         1,
   5056         0,
   5057         0x56000300,
   5058         SOC_REG_FLAG_64_BITS |
   5059                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5060         0,
   5061         22,
   5062         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5064         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5065         -1,
   5066         -1,
   5067         0,
   5068     },
   5069 #endif /* chips */
   5070 
   5071 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5072     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_BCM56980_A0r */
   5073         soc_block_list[5],
   5074         soc_genreg,
   5075         1,
   5076         0,
   5077         0xa000200,
   5078         SOC_REG_FLAG_64_BITS |
   5079                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5080         0,
   5081         22,
   5082         soc_VFP_KEY_CONTROL_1_BCM56980_A0r_fields,
   5083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5084         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5085         -1,
   5086         -1,
   5087         3,
   5088     },
   5089 #endif /* chips */
   5090 
   5091 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5092     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE0r */
   5093         soc_block_list[5],
   5094         soc_genreg,
   5095         1,
   5096         0,
   5097         0x32000300,
   5098         SOC_REG_FLAG_64_BITS,
   5099         0,
   5100         22,
   5101         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5103         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5104         -1,
   5105         -1,
   5106         0,
   5107     },
   5108 #endif /* chips */
   5109 
   5110 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5111     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE1r */
   5112         soc_block_list[5],
   5113         soc_genreg,
   5114         1,
   5115         0,
   5116         0x32000300,
   5117         SOC_REG_FLAG_64_BITS |
   5118                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5119         0,
   5120         22,
   5121         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5123         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5124         -1,
   5125         -1,
   5126         0,
   5127     },
   5128 #endif /* chips */
   5129 
   5130 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5131     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE2r */
   5132         soc_block_list[5],
   5133         soc_genreg,
   5134         1,
   5135         0,
   5136         0x32000300,
   5137         SOC_REG_FLAG_64_BITS |
   5138                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5139         0,
   5140         22,
   5141         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5143         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5144         -1,
   5145         -1,
   5146         0,
   5147     },
   5148 #endif /* chips */
   5149 
   5150 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5151     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE3r */
   5152         soc_block_list[5],
   5153         soc_genreg,
   5154         1,
   5155         0,
   5156         0x32000300,
   5157         SOC_REG_FLAG_64_BITS |
   5158                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5159         0,
   5160         22,
   5161         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5163         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5164         -1,
   5165         -1,
   5166         0,
   5167     },
   5168 #endif /* chips */
   5169 
   5170 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5171     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE4r */
   5172         soc_block_list[5],
   5173         soc_genreg,
   5174         1,
   5175         0,
   5176         0xa000200,
   5177         SOC_REG_FLAG_64_BITS |
   5178                           (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5179         0,
   5180         22,
   5181         soc_VFP_KEY_CONTROL_1_BCM56980_A0r_fields,
   5182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5183         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5184         -1,
   5185         -1,
   5186         3,
   5187     },
   5188 #endif /* chips */
   5189 
   5190 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5191     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE5r */
   5192         soc_block_list[5],
   5193         soc_genreg,
   5194         1,
   5195         0,
   5196         0xa000200,
   5197         SOC_REG_FLAG_64_BITS |
   5198                           (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5199         0,
   5200         22,
   5201         soc_VFP_KEY_CONTROL_1_BCM56980_A0r_fields,
   5202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5203         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5204         -1,
   5205         -1,
   5206         3,
   5207     },
   5208 #endif /* chips */
   5209 
   5210 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5211     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE6r */
   5212         soc_block_list[5],
   5213         soc_genreg,
   5214         1,
   5215         0,
   5216         0xa000200,
   5217         SOC_REG_FLAG_64_BITS |
   5218                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5219         0,
   5220         22,
   5221         soc_VFP_KEY_CONTROL_1_BCM56980_A0r_fields,
   5222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5223         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5224         -1,
   5225         -1,
   5226         3,
   5227     },
   5228 #endif /* chips */
   5229 
   5230 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5231     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE7r */
   5232         soc_block_list[5],
   5233         soc_genreg,
   5234         1,
   5235         0,
   5236         0xa000200,
   5237         SOC_REG_FLAG_64_BITS |
   5238                           (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5239         0,
   5240         22,
   5241         soc_VFP_KEY_CONTROL_1_BCM56980_A0r_fields,
   5242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5243         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5244         -1,
   5245         -1,
   5246         3,
   5247     },
   5248 #endif /* chips */
   5249 
   5250 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   5251     defined(BCM_56870_A0)
   5252     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE0_BCM56870_A0r */
   5253         soc_block_list[5],
   5254         soc_genreg,
   5255         1,
   5256         0,
   5257         0x56002900,
   5258         SOC_REG_FLAG_64_BITS,
   5259         0,
   5260         22,
   5261         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5263         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5264         -1,
   5265         -1,
   5266         0,
   5267     },
   5268 #endif /* chips */
   5269 
   5270 #if defined(BCM_56970_A0)
   5271     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE0_BCM56970_A0r */
   5272         soc_block_list[5],
   5273         soc_genreg,
   5274         1,
   5275         0,
   5276         0x56000300,
   5277         SOC_REG_FLAG_64_BITS,
   5278         0,
   5279         22,
   5280         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5282         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5283         -1,
   5284         -1,
   5285         0,
   5286     },
   5287 #endif /* chips */
   5288 
   5289 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5290     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE0_BCM56980_A0r */
   5291         soc_block_list[5],
   5292         soc_genreg,
   5293         1,
   5294         0,
   5295         0xa000200,
   5296         SOC_REG_FLAG_64_BITS,
   5297         0,
   5298         22,
   5299         soc_VFP_KEY_CONTROL_1_BCM56980_A0r_fields,
   5300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5301         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5302         -1,
   5303         -1,
   5304         3,
   5305     },
   5306 #endif /* chips */
   5307 
   5308 #if defined(BCM_56870_A0)
   5309     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE1_BCM56870_A0r */
   5310         soc_block_list[5],
   5311         soc_genreg,
   5312         1,
   5313         0,
   5314         0x56002900,
   5315         SOC_REG_FLAG_64_BITS |
   5316                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5317         0,
   5318         22,
   5319         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5321         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5322         -1,
   5323         -1,
   5324         0,
   5325     },
   5326 #endif /* chips */
   5327 
   5328 #if defined(BCM_56970_A0)
   5329     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE1_BCM56970_A0r */
   5330         soc_block_list[5],
   5331         soc_genreg,
   5332         1,
   5333         0,
   5334         0x56000300,
   5335         SOC_REG_FLAG_64_BITS |
   5336                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5337         0,
   5338         22,
   5339         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5341         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5342         -1,
   5343         -1,
   5344         0,
   5345     },
   5346 #endif /* chips */
   5347 
   5348 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5349     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE1_BCM56980_A0r */
   5350         soc_block_list[5],
   5351         soc_genreg,
   5352         1,
   5353         0,
   5354         0xa000200,
   5355         SOC_REG_FLAG_64_BITS |
   5356                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5357         0,
   5358         22,
   5359         soc_VFP_KEY_CONTROL_1_BCM56980_A0r_fields,
   5360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5361         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5362         -1,
   5363         -1,
   5364         3,
   5365     },
   5366 #endif /* chips */
   5367 
   5368 #if defined(BCM_56970_A0)
   5369     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE2_BCM56970_A0r */
   5370         soc_block_list[5],
   5371         soc_genreg,
   5372         1,
   5373         0,
   5374         0x56000300,
   5375         SOC_REG_FLAG_64_BITS |
   5376                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5377         0,
   5378         22,
   5379         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5381         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5382         -1,
   5383         -1,
   5384         0,
   5385     },
   5386 #endif /* chips */
   5387 
   5388 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5389     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE2_BCM56980_A0r */
   5390         soc_block_list[5],
   5391         soc_genreg,
   5392         1,
   5393         0,
   5394         0xa000200,
   5395         SOC_REG_FLAG_64_BITS |
   5396                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5397         0,
   5398         22,
   5399         soc_VFP_KEY_CONTROL_1_BCM56980_A0r_fields,
   5400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5401         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5402         -1,
   5403         -1,
   5404         3,
   5405     },
   5406 #endif /* chips */
   5407 
   5408 #if defined(BCM_56970_A0)
   5409     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE3_BCM56970_A0r */
   5410         soc_block_list[5],
   5411         soc_genreg,
   5412         1,
   5413         0,
   5414         0x56000300,
   5415         SOC_REG_FLAG_64_BITS |
   5416                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5417         0,
   5418         22,
   5419         soc_VFP_KEY_CONTROL_1_BCM56960_A0r_fields,
   5420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5421         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5422         -1,
   5423         -1,
   5424         0,
   5425     },
   5426 #endif /* chips */
   5427 
   5428 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5429     { /* SOC_REG_INT_VFP_KEY_CONTROL_1_PIPE3_BCM56980_A0r */
   5430         soc_block_list[5],
   5431         soc_genreg,
   5432         1,
   5433         0,
   5434         0xa000200,
   5435         SOC_REG_FLAG_64_BITS |
   5436                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5437         0,
   5438         22,
   5439         soc_VFP_KEY_CONTROL_1_BCM56980_A0r_fields,
   5440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5441         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5442         -1,
   5443         -1,
   5444         3,
   5445     },
   5446 #endif /* chips */
   5447 
   5448 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   5449     defined(BCM_56270_A0)
   5450     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_BCM56260_A0r */
   5451         soc_block_list[5],
   5452         soc_genreg,
   5453         1,
   5454         0,
   5455         0x12000400,
   5456         0,
   5457         0,
   5458         4,
   5459         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5461         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5462         -1,
   5463         -1,
   5464     },
   5465 #endif /* chips */
   5466 
   5467 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5468     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_BCM56440_A0r */
   5469         soc_block_list[5],
   5470         soc_genreg,
   5471         1,
   5472         0,
   5473         0x4080622,
   5474         0,
   5475         0,
   5476         8,
   5477         soc_VFP_KEY_CONTROL_2_BCM56440_A0r_fields,
   5478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5479         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   5480         -1,
   5481         -1,
   5482     },
   5483 #endif /* chips */
   5484 
   5485 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5486     defined(BCM_56450_B1)
   5487     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_BCM56450_A0r */
   5488         soc_block_list[5],
   5489         soc_genreg,
   5490         1,
   5491         0,
   5492         0x12000400,
   5493         0,
   5494         0,
   5495         4,
   5496         soc_VFP_KEY_CONTROL_2_BCM56640_A0r_fields,
   5497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5498         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5499         -1,
   5500         -1,
   5501     },
   5502 #endif /* chips */
   5503 
   5504 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   5505     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   5506     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_BCM56560_A0r */
   5507         soc_block_list[5],
   5508         soc_genreg,
   5509         1,
   5510         0,
   5511         0x12002200,
   5512         0,
   5513         0,
   5514         4,
   5515         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5517         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5518         -1,
   5519         -1,
   5520     },
   5521 #endif /* chips */
   5522 
   5523 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   5524     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_BCM56640_A0r */
   5525         soc_block_list[5],
   5526         soc_genreg,
   5527         1,
   5528         0,
   5529         0x12000400,
   5530         0,
   5531         0,
   5532         4,
   5533         soc_VFP_KEY_CONTROL_2_BCM56640_A0r_fields,
   5534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5535         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5536         -1,
   5537         -1,
   5538     },
   5539 #endif /* chips */
   5540 
   5541 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   5542     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_BCM56820_A0r */
   5543         soc_block_list[5],
   5544         soc_genreg,
   5545         1,
   5546         0,
   5547         0x4080603,
   5548         0,
   5549         0,
   5550         4,
   5551         soc_VFP_KEY_CONTROL_2r_fields,
   5552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5553         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5554         -1,
   5555         -1,
   5556     },
   5557 #endif /* chips */
   5558 
   5559 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5560     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_BCM56840_A0r */
   5561         soc_block_list[5],
   5562         soc_genreg,
   5563         1,
   5564         0,
   5565         0x4080622,
   5566         0,
   5567         0,
   5568         4,
   5569         soc_VFP_KEY_CONTROL_2r_fields,
   5570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5571         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5572         -1,
   5573         -1,
   5574     },
   5575 #endif /* chips */
   5576 
   5577 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   5578     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_BCM56850_A0r */
   5579         soc_block_list[5],
   5580         soc_genreg,
   5581         1,
   5582         0,
   5583         0x12002200,
   5584         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5585         0,
   5586         4,
   5587         soc_VFP_KEY_CONTROL_2_BCM56640_A0r_fields,
   5588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5589         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5590         -1,
   5591         -1,
   5592     },
   5593 #endif /* chips */
   5594 
   5595 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5596     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_BCM56960_A0r */
   5597         soc_block_list[5],
   5598         soc_genreg,
   5599         1,
   5600         0,
   5601         0x32000400,
   5602         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5603         0,
   5604         4,
   5605         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5607         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5608         -1,
   5609         -1,
   5610         0,
   5611     },
   5612 #endif /* chips */
   5613 
   5614 #if defined(BCM_56970_A0)
   5615     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_BCM56970_A0r */
   5616         soc_block_list[5],
   5617         soc_genreg,
   5618         1,
   5619         0,
   5620         0x56000400,
   5621         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5622         0,
   5623         4,
   5624         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5626         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5627         -1,
   5628         -1,
   5629         0,
   5630     },
   5631 #endif /* chips */
   5632 
   5633 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5634     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_BCM56980_A0r */
   5635         soc_block_list[5],
   5636         soc_genreg,
   5637         1,
   5638         0,
   5639         0xa000300,
   5640         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5641         0,
   5642         4,
   5643         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5645         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5646         -1,
   5647         -1,
   5648         3,
   5649     },
   5650 #endif /* chips */
   5651 
   5652 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5653     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE0r */
   5654         soc_block_list[5],
   5655         soc_genreg,
   5656         1,
   5657         0,
   5658         0x32000400,
   5659         0,
   5660         0,
   5661         4,
   5662         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5664         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5665         -1,
   5666         -1,
   5667         0,
   5668     },
   5669 #endif /* chips */
   5670 
   5671 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5672     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE1r */
   5673         soc_block_list[5],
   5674         soc_genreg,
   5675         1,
   5676         0,
   5677         0x32000400,
   5678         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5679         0,
   5680         4,
   5681         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5683         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5684         -1,
   5685         -1,
   5686         0,
   5687     },
   5688 #endif /* chips */
   5689 
   5690 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5691     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE2r */
   5692         soc_block_list[5],
   5693         soc_genreg,
   5694         1,
   5695         0,
   5696         0x32000400,
   5697         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5698         0,
   5699         4,
   5700         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5702         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5703         -1,
   5704         -1,
   5705         0,
   5706     },
   5707 #endif /* chips */
   5708 
   5709 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   5710     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE3r */
   5711         soc_block_list[5],
   5712         soc_genreg,
   5713         1,
   5714         0,
   5715         0x32000400,
   5716         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5717         0,
   5718         4,
   5719         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5721         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5722         -1,
   5723         -1,
   5724         0,
   5725     },
   5726 #endif /* chips */
   5727 
   5728 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5729     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE4r */
   5730         soc_block_list[5],
   5731         soc_genreg,
   5732         1,
   5733         0,
   5734         0xa000300,
   5735         (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5736         0,
   5737         4,
   5738         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5740         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5741         -1,
   5742         -1,
   5743         3,
   5744     },
   5745 #endif /* chips */
   5746 
   5747 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5748     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE5r */
   5749         soc_block_list[5],
   5750         soc_genreg,
   5751         1,
   5752         0,
   5753         0xa000300,
   5754         (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5755         0,
   5756         4,
   5757         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5759         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5760         -1,
   5761         -1,
   5762         3,
   5763     },
   5764 #endif /* chips */
   5765 
   5766 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5767     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE6r */
   5768         soc_block_list[5],
   5769         soc_genreg,
   5770         1,
   5771         0,
   5772         0xa000300,
   5773         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5774         0,
   5775         4,
   5776         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5778         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5779         -1,
   5780         -1,
   5781         3,
   5782     },
   5783 #endif /* chips */
   5784 
   5785 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5786     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE7r */
   5787         soc_block_list[5],
   5788         soc_genreg,
   5789         1,
   5790         0,
   5791         0xa000300,
   5792         (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5793         0,
   5794         4,
   5795         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5797         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5798         -1,
   5799         -1,
   5800         3,
   5801     },
   5802 #endif /* chips */
   5803 
   5804 #if defined(BCM_56970_A0)
   5805     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE0_BCM56970_A0r */
   5806         soc_block_list[5],
   5807         soc_genreg,
   5808         1,
   5809         0,
   5810         0x56000400,
   5811         0,
   5812         0,
   5813         4,
   5814         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5816         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5817         -1,
   5818         -1,
   5819         0,
   5820     },
   5821 #endif /* chips */
   5822 
   5823 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5824     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE0_BCM56980_A0r */
   5825         soc_block_list[5],
   5826         soc_genreg,
   5827         1,
   5828         0,
   5829         0xa000300,
   5830         0,
   5831         0,
   5832         4,
   5833         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5835         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5836         -1,
   5837         -1,
   5838         3,
   5839     },
   5840 #endif /* chips */
   5841 
   5842 #if defined(BCM_56970_A0)
   5843     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE1_BCM56970_A0r */
   5844         soc_block_list[5],
   5845         soc_genreg,
   5846         1,
   5847         0,
   5848         0x56000400,
   5849         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5850         0,
   5851         4,
   5852         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5854         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5855         -1,
   5856         -1,
   5857         0,
   5858     },
   5859 #endif /* chips */
   5860 
   5861 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5862     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE1_BCM56980_A0r */
   5863         soc_block_list[5],
   5864         soc_genreg,
   5865         1,
   5866         0,
   5867         0xa000300,
   5868         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5869         0,
   5870         4,
   5871         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5873         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5874         -1,
   5875         -1,
   5876         3,
   5877     },
   5878 #endif /* chips */
   5879 
   5880 #if defined(BCM_56970_A0)
   5881     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE2_BCM56970_A0r */
   5882         soc_block_list[5],
   5883         soc_genreg,
   5884         1,
   5885         0,
   5886         0x56000400,
   5887         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5888         0,
   5889         4,
   5890         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5892         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5893         -1,
   5894         -1,
   5895         0,
   5896     },
   5897 #endif /* chips */
   5898 
   5899 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5900     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE2_BCM56980_A0r */
   5901         soc_block_list[5],
   5902         soc_genreg,
   5903         1,
   5904         0,
   5905         0xa000300,
   5906         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5907         0,
   5908         4,
   5909         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5911         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5912         -1,
   5913         -1,
   5914         3,
   5915     },
   5916 #endif /* chips */
   5917 
   5918 #if defined(BCM_56970_A0)
   5919     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE3_BCM56970_A0r */
   5920         soc_block_list[5],
   5921         soc_genreg,
   5922         1,
   5923         0,
   5924         0x56000400,
   5925         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5926         0,
   5927         4,
   5928         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5930         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5931         -1,
   5932         -1,
   5933         0,
   5934     },
   5935 #endif /* chips */
   5936 
   5937 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5938     { /* SOC_REG_INT_VFP_KEY_CONTROL_2_PIPE3_BCM56980_A0r */
   5939         soc_block_list[5],
   5940         soc_genreg,
   5941         1,
   5942         0,
   5943         0xa000300,
   5944         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   5945         0,
   5946         4,
   5947         soc_VFP_KEY_CONTROL_2_BCM56960_A0r_fields,
   5948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5949         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   5950         -1,
   5951         -1,
   5952         3,
   5953     },
   5954 #endif /* chips */
   5955 
   5956 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5957     defined(BCM_53570_A0) || defined(BCM_56160_A0)
   5958     { /* SOC_REG_INT_VFP_KEY_CONTROL_BCM53400_A0r */
   5959         soc_block_list[5],
   5960         soc_genreg,
   5961         1,
   5962         0,
   5963         0xe000200,
   5964         0,
   5965         0,
   5966         10,
   5967         soc_VFP_KEY_CONTROL_BCM53400_A0r_fields,
   5968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5969         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
   5970         -1,
   5971         -1,
   5972     },
   5973 #endif /* chips */
   5974 
   5975 #if defined(BCM_53570_B0)
   5976     { /* SOC_REG_INT_VFP_KEY_CONTROL_BCM53570_B0r */
   5977         soc_block_list[5],
   5978         soc_genreg,
   5979         1,
   5980         0,
   5981         0xe000200,
   5982         0,
   5983         0,
   5984         10,
   5985         soc_VFP_KEY_CONTROL_BCM53570_B0r_fields,
   5986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5987         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   5988         -1,
   5989         -1,
   5990     },
   5991 #endif /* chips */
   5992 
   5993 #if defined(BCM_56150_A0)
   5994     { /* SOC_REG_INT_VFP_KEY_CONTROL_BCM56150_A0r */
   5995         soc_block_list[5],
   5996         soc_genreg,
   5997         1,
   5998         0,
   5999         0x12000200,
   6000         0,
   6001         0,
   6002         10,
   6003         soc_VFP_KEY_CONTROL_BCM56150_A0r_fields,
   6004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6005         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
   6006         -1,
   6007         -1,
   6008     },
   6009 #endif /* chips */
   6010 
   6011 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   6012     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6013     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   6014     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6015     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   6016     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6017     { /* SOC_REG_INT_VFP_KEY_CONTROL_BCM56624_A0r */
   6018         soc_block_list[5],
   6019         soc_genreg,
   6020         1,
   6021         0,
   6022         0x4080021,
   6023         0,
   6024         0,
   6025         18,
   6026         soc_VFP_KEY_CONTROL_BCM56624_A0r_fields,
   6027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6028         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6029         -1,
   6030         -1,
   6031     },
   6032 #endif /* chips */
   6033 
   6034 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6035     { /* SOC_REG_INT_VFP_KEY_CONTROL_BCM56820_A0r */
   6036         soc_block_list[5],
   6037         soc_genreg,
   6038         1,
   6039         0,
   6040         0x4080602,
   6041         0,
   6042         0,
   6043         18,
   6044         soc_VFP_KEY_CONTROL_BCM56624_A0r_fields,
   6045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6046         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6047         -1,
   6048         -1,
   6049     },
   6050 #endif /* chips */
   6051 
   6052 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   6053     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6054     { /* SOC_REG_INT_VFP_KEY_CONTROL_BCM56840_A0r */
   6055         soc_block_list[5],
   6056         soc_genreg,
   6057         1,
   6058         0,
   6059         0x4080621,
   6060         0,
   6061         0,
   6062         18,
   6063         soc_VFP_KEY_CONTROL_BCM56624_A0r_fields,
   6064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6065         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6066         -1,
   6067         -1,
   6068     },
   6069 #endif /* chips */
   6070 
   6071 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   6072     defined(BCM_56270_A0)
   6073     { /* SOC_REG_INT_VFP_POLICY_ECC_CONTROLr */
   6074         soc_block_list[5],
   6075         soc_genreg,
   6076         1,
   6077         0,
   6078         0x12011300,
   6079         0,
   6080         0,
   6081         2,
   6082         soc_EGR_MASK_ECC_CONTROLr_fields,
   6083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6084         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6085         -1,
   6086         -1,
   6087     },
   6088 #endif /* chips */
   6089 
   6090 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6091     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6092     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6093     { /* SOC_REG_INT_VFP_POLICY_PARITY_CONTROLr */
   6094         soc_block_list[5],
   6095         soc_genreg,
   6096         1,
   6097         0,
   6098         0x4080142,
   6099         0,
   6100         0,
   6101         1,
   6102         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   6103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6104         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6105         -1,
   6106         -1,
   6107     },
   6108 #endif /* chips */
   6109 
   6110 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6111     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6112     defined(BCM_56160_A0)
   6113     { /* SOC_REG_INT_VFP_POLICY_PARITY_CONTROL_BCM53400_A0r */
   6114         soc_block_list[5],
   6115         soc_genreg,
   6116         1,
   6117         0,
   6118         0xe011400,
   6119         0,
   6120         0,
   6121         1,
   6122         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
   6123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6124         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6125         -1,
   6126         -1,
   6127     },
   6128 #endif /* chips */
   6129 
   6130 #if defined(BCM_56150_A0)
   6131     { /* SOC_REG_INT_VFP_POLICY_PARITY_CONTROL_BCM56150_A0r */
   6132         soc_block_list[5],
   6133         soc_genreg,
   6134         1,
   6135         0,
   6136         0x12011000,
   6137         0,
   6138         0,
   6139         1,
   6140         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
   6141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6142         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6143         -1,
   6144         -1,
   6145     },
   6146 #endif /* chips */
   6147 
   6148 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   6149     { /* SOC_REG_INT_VFP_POLICY_PARITY_CONTROL_BCM56334_A0r */
   6150         soc_block_list[5],
   6151         soc_genreg,
   6152         1,
   6153         0,
   6154         0x4080121,
   6155         0,
   6156         0,
   6157         1,
   6158         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   6159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6160         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   6161         -1,
   6162         -1,
   6163     },
   6164 #endif /* chips */
   6165 
   6166 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6167     defined(BCM_56450_B1)
   6168     { /* SOC_REG_INT_VFP_POLICY_PARITY_CONTROL_BCM56450_A0r */
   6169         soc_block_list[5],
   6170         soc_genreg,
   6171         1,
   6172         0,
   6173         0x12011200,
   6174         0,
   6175         0,
   6176         1,
   6177         soc_FT_CNTR_SER_CONTROLr_fields,
   6178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6179         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6180         -1,
   6181         -1,
   6182     },
   6183 #endif /* chips */
   6184 
   6185 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   6186     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6187     { /* SOC_REG_INT_VFP_POLICY_PARITY_CONTROL_BCM56840_A0r */
   6188         soc_block_list[5],
   6189         soc_genreg,
   6190         1,
   6191         0,
   6192         0x4080d11,
   6193         0,
   6194         0,
   6195         1,
   6196         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
   6197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6198         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6199         -1,
   6200         -1,
   6201     },
   6202 #endif /* chips */
   6203 
   6204 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6205     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6206     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6207     { /* SOC_REG_INT_VFP_POLICY_PARITY_STATUS_INTRr */
   6208         soc_block_list[5],
   6209         soc_genreg,
   6210         1,
   6211         0,
   6212         0x4080143,
   6213         0,
   6214         0,
   6215         3,
   6216         soc_EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr_fields,
   6217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6218         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   6219         -1,
   6220         -1,
   6221     },
   6222 #endif /* chips */
   6223 
   6224 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6225     defined(BCM_56160_A0)
   6226     { /* SOC_REG_INT_VFP_POLICY_PARITY_STATUS_INTR_BCM53400_A0r */
   6227         soc_block_list[5],
   6228         soc_genreg,
   6229         1,
   6230         0,
   6231         0xe011500,
   6232         0,
   6233         0,
   6234         3,
   6235         soc_EGR_ETAG_PCP_DE_MAPPING_PARITY_STATUSr_fields,
   6236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6237         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   6238         -1,
   6239         -1,
   6240     },
   6241 #endif /* chips */
   6242 
   6243 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   6244     { /* SOC_REG_INT_VFP_POLICY_PARITY_STATUS_INTR_BCM53570_A0r */
   6245         soc_block_list[5],
   6246         soc_genreg,
   6247         1,
   6248         0,
   6249         0xe011500,
   6250         0,
   6251         0,
   6252         3,
   6253         soc_EGR_L3_NEXT_HOP_PARITY_STATUS_BCM53400_A0r_fields,
   6254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6255         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   6256         -1,
   6257         -1,
   6258     },
   6259 #endif /* chips */
   6260 
   6261 #if defined(BCM_56150_A0)
   6262     { /* SOC_REG_INT_VFP_POLICY_PARITY_STATUS_INTR_BCM56150_A0r */
   6263         soc_block_list[5],
   6264         soc_genreg,
   6265         1,
   6266         0,
   6267         0x12011100,
   6268         0,
   6269         0,
   6270         3,
   6271         soc_AXP_WTX_FRAG_ID_PAR_STATUS_INTRr_fields,
   6272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6273         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   6274         -1,
   6275         -1,
   6276     },
   6277 #endif /* chips */
   6278 
   6279 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   6280     { /* SOC_REG_INT_VFP_POLICY_PARITY_STATUS_INTR_BCM56334_A0r */
   6281         soc_block_list[5],
   6282         soc_genreg,
   6283         1,
   6284         0,
   6285         0x4080122,
   6286         0,
   6287         0,
   6288         3,
   6289         soc_EGR_IP_TUNNEL_PARITY_STATUSr_fields,
   6290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6291         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   6292         -1,
   6293         -1,
   6294     },
   6295 #endif /* chips */
   6296 
   6297 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6298     defined(BCM_56450_B1)
   6299     { /* SOC_REG_INT_VFP_POLICY_PARITY_STATUS_INTR_BCM56450_A0r */
   6300         soc_block_list[5],
   6301         soc_genreg,
   6302         1,
   6303         0,
   6304         0x12011300,
   6305         0,
   6306         0,
   6307         3,
   6308         soc_EGR_MPLS_EXP_MAPPING_1_PARITY_STATUS_INTRr_fields,
   6309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6310         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6311         -1,
   6312         -1,
   6313     },
   6314 #endif /* chips */
   6315 
   6316 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   6317     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6318     { /* SOC_REG_INT_VFP_POLICY_PARITY_STATUS_INTR_BCM56840_A0r */
   6319         soc_block_list[5],
   6320         soc_genreg,
   6321         1,
   6322         0,
   6323         0x4080d12,
   6324         0,
   6325         0,
   6326         3,
   6327         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
   6328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6329         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6330         -1,
   6331         -1,
   6332     },
   6333 #endif /* chips */
   6334 
   6335 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6336     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6337     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6338     { /* SOC_REG_INT_VFP_POLICY_PARITY_STATUS_NACKr */
   6339         soc_block_list[5],
   6340         soc_genreg,
   6341         1,
   6342         0,
   6343         0x4080144,
   6344         0,
   6345         0,
   6346         3,
   6347         soc_EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr_fields,
   6348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6349         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   6350         -1,
   6351         -1,
   6352     },
   6353 #endif /* chips */
   6354 
   6355 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6356     defined(BCM_56450_B1)
   6357     { /* SOC_REG_INT_VFP_POLICY_PARITY_STATUS_NACK_BCM56450_A0r */
   6358         soc_block_list[5],
   6359         soc_genreg,
   6360         1,
   6361         0,
   6362         0x12011400,
   6363         0,
   6364         0,
   6365         3,
   6366         soc_EGR_MPLS_EXP_MAPPING_1_PARITY_STATUS_INTRr_fields,
   6367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6368         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6369         -1,
   6370         -1,
   6371     },
   6372 #endif /* chips */
   6373 
   6374 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   6375     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6376     { /* SOC_REG_INT_VFP_POLICY_PARITY_STATUS_NACK_BCM56840_A0r */
   6377         soc_block_list[5],
   6378         soc_genreg,
   6379         1,
   6380         0,
   6381         0x4080d13,
   6382         0,
   6383         0,
   6384         3,
   6385         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
   6386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6387         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6388         -1,
   6389         -1,
   6390     },
   6391 #endif /* chips */
   6392 
   6393 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6394     { /* SOC_REG_INT_VFP_POLICY_TABLE_PARITY_CONTROLr */
   6395         soc_block_list[5],
   6396         soc_genreg,
   6397         1,
   6398         0,
   6399         0x4080c07,
   6400         0,
   6401         0,
   6402         2,
   6403         soc_L2_ENTRY_PARITY_CONTROLr_fields,
   6404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6405         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6406         -1,
   6407         -1,
   6408     },
   6409 #endif /* chips */
   6410 
   6411 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6412     { /* SOC_REG_INT_VFP_POLICY_TABLE_PARITY_STATUSr */
   6413         soc_block_list[5],
   6414         soc_genreg,
   6415         1,
   6416         0,
   6417         0x4080c08,
   6418         SOC_REG_FLAG_RO,
   6419         0,
   6420         2,
   6421         soc_VFP_POLICY_TABLE_PARITY_STATUSr_fields,
   6422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6423         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6424         -1,
   6425         -1,
   6426     },
   6427 #endif /* chips */
   6428 
   6429 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   6430     { /* SOC_REG_INT_VFP_POLICY_TABLE_PDAr */
   6431         soc_block_list[5],
   6432         soc_genreg,
   6433         1,
   6434         0,
   6435         0x12010e00,
   6436         0,
   6437         0,
   6438         4,
   6439         soc_EFP_POLICY_PDAr_fields,
   6440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6441         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6442         -1,
   6443         -1,
   6444     },
   6445 #endif /* chips */
   6446 
   6447 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   6448     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   6449     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROLr */
   6450         soc_block_list[5],
   6451         soc_genreg,
   6452         1,
   6453         0,
   6454         0x4080119,
   6455         0,
   6456         0,
   6457         4,
   6458         soc_VFP_POLICY_TABLE_RAM_CONTROLr_fields,
   6459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6460         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6461         -1,
   6462         -1,
   6463     },
   6464 #endif /* chips */
   6465 
   6466 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6467     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6468     defined(BCM_56160_A0)
   6469     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_64r */
   6470         soc_block_list[5],
   6471         soc_genreg,
   6472         1,
   6473         0,
   6474         0xe011f00,
   6475         SOC_REG_FLAG_64_BITS,
   6476         0,
   6477         4,
   6478         soc_VFP_POLICY_TABLE_RAM_CONTROL_64r_fields,
   6479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6480         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6481         -1,
   6482         -1,
   6483     },
   6484 #endif /* chips */
   6485 
   6486 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6487     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_64_BCM56960_A0r */
   6488         soc_block_list[5],
   6489         soc_genreg,
   6490         1,
   6491         0,
   6492         0x330d0000,
   6493         SOC_REG_FLAG_64_BITS |
   6494                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6495         0,
   6496         8,
   6497         soc_VFP_POLICY_TABLE_RAM_CONTROL_64_BCM56960_A0r_fields,
   6498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6499         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6500         -1,
   6501         -1,
   6502         0,
   6503     },
   6504 #endif /* chips */
   6505 
   6506 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6507     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_64_PIPE0r */
   6508         soc_block_list[5],
   6509         soc_genreg,
   6510         1,
   6511         0,
   6512         0x330d0000,
   6513         SOC_REG_FLAG_64_BITS,
   6514         0,
   6515         8,
   6516         soc_VFP_POLICY_TABLE_RAM_CONTROL_64_BCM56960_A0r_fields,
   6517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6518         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6519         -1,
   6520         -1,
   6521         0,
   6522     },
   6523 #endif /* chips */
   6524 
   6525 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6526     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_64_PIPE1r */
   6527         soc_block_list[5],
   6528         soc_genreg,
   6529         1,
   6530         0,
   6531         0x330d0000,
   6532         SOC_REG_FLAG_64_BITS |
   6533                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6534         0,
   6535         8,
   6536         soc_VFP_POLICY_TABLE_RAM_CONTROL_64_BCM56960_A0r_fields,
   6537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6539         -1,
   6540         -1,
   6541         0,
   6542     },
   6543 #endif /* chips */
   6544 
   6545 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6546     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_64_PIPE2r */
   6547         soc_block_list[5],
   6548         soc_genreg,
   6549         1,
   6550         0,
   6551         0x330d0000,
   6552         SOC_REG_FLAG_64_BITS |
   6553                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6554         0,
   6555         8,
   6556         soc_VFP_POLICY_TABLE_RAM_CONTROL_64_BCM56960_A0r_fields,
   6557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6559         -1,
   6560         -1,
   6561         0,
   6562     },
   6563 #endif /* chips */
   6564 
   6565 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   6566     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_64_PIPE3r */
   6567         soc_block_list[5],
   6568         soc_genreg,
   6569         1,
   6570         0,
   6571         0x330d0000,
   6572         SOC_REG_FLAG_64_BITS |
   6573                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6574         0,
   6575         8,
   6576         soc_VFP_POLICY_TABLE_RAM_CONTROL_64_BCM56960_A0r_fields,
   6577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6578         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6579         -1,
   6580         -1,
   6581         0,
   6582     },
   6583 #endif /* chips */
   6584 
   6585 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   6586     defined(BCM_56270_A0)
   6587     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56260_A0r */
   6588         soc_block_list[5],
   6589         soc_genreg,
   6590         1,
   6591         0,
   6592         0x12011b00,
   6593         0,
   6594         0,
   6595         5,
   6596         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56260_A0r_fields,
   6597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6598         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6599         -1,
   6600         -1,
   6601     },
   6602 #endif /* chips */
   6603 
   6604 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   6605     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56334_A0r */
   6606         soc_block_list[5],
   6607         soc_genreg,
   6608         1,
   6609         0,
   6610         0x408012c,
   6611         0,
   6612         0,
   6613         4,
   6614         soc_VFP_POLICY_TABLE_RAM_CONTROLr_fields,
   6615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6616         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6617         -1,
   6618         -1,
   6619     },
   6620 #endif /* chips */
   6621 
   6622 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6623     defined(BCM_56450_B1)
   6624     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56450_A0r */
   6625         soc_block_list[5],
   6626         soc_genreg,
   6627         1,
   6628         0,
   6629         0x12011a00,
   6630         0,
   6631         0,
   6632         8,
   6633         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56640_A0r_fields,
   6634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6635         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6636         -1,
   6637         -1,
   6638     },
   6639 #endif /* chips */
   6640 
   6641 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   6642     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56560_A0r */
   6643         soc_block_list[5],
   6644         soc_genreg,
   6645         1,
   6646         0,
   6647         0x130f0000,
   6648         0,
   6649         0,
   6650         1,
   6651         soc_DSCP_CONTROLr_fields,
   6652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6653         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6654         -1,
   6655         -1,
   6656     },
   6657 #endif /* chips */
   6658 
   6659 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6660     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6661     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6662     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56634_A0r */
   6663         soc_block_list[5],
   6664         soc_genreg,
   6665         1,
   6666         0,
   6667         0x408014b,
   6668         0,
   6669         0,
   6670         4,
   6671         soc_VFP_POLICY_TABLE_RAM_CONTROLr_fields,
   6672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6673         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6674         -1,
   6675         -1,
   6676     },
   6677 #endif /* chips */
   6678 
   6679 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   6680     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56640_A0r */
   6681         soc_block_list[5],
   6682         soc_genreg,
   6683         1,
   6684         0,
   6685         0x12010d00,
   6686         0,
   6687         0,
   6688         8,
   6689         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56640_A0r_fields,
   6690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6692         -1,
   6693         -1,
   6694     },
   6695 #endif /* chips */
   6696 
   6697 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   6698     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56670_A0r */
   6699         soc_block_list[5],
   6700         soc_genreg,
   6701         1,
   6702         0,
   6703         0x13100000,
   6704         0,
   6705         0,
   6706         1,
   6707         soc_E2EFC_MEM_TMr_fields,
   6708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6709         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6710         -1,
   6711         -1,
   6712     },
   6713 #endif /* chips */
   6714 
   6715 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6716     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56820_A0r */
   6717         soc_block_list[5],
   6718         soc_genreg,
   6719         1,
   6720         0,
   6721         0x4080c38,
   6722         0,
   6723         0,
   6724         8,
   6725         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56820_A0r_fields,
   6726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6727         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6728         -1,
   6729         -1,
   6730     },
   6731 #endif /* chips */
   6732 
   6733 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   6734     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6735     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56840_A0r */
   6736         soc_block_list[5],
   6737         soc_genreg,
   6738         1,
   6739         0,
   6740         0x4080d19,
   6741         0,
   6742         0,
   6743         8,
   6744         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56840_A0r_fields,
   6745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6746         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6747         -1,
   6748         -1,
   6749     },
   6750 #endif /* chips */
   6751 
   6752 #if defined(BCM_56850_A0)
   6753     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56850_A0r */
   6754         soc_block_list[5],
   6755         soc_genreg,
   6756         1,
   6757         0,
   6758         0x13110000,
   6759         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6760         0,
   6761         8,
   6762         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56850_A0r_fields,
   6763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6764         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6765         -1,
   6766         -1,
   6767     },
   6768 #endif /* chips */
   6769 
   6770 #if defined(BCM_56860_A0)
   6771     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56860_A0r */
   6772         soc_block_list[5],
   6773         soc_genreg,
   6774         1,
   6775         0,
   6776         0x130f0000,
   6777         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6778         0,
   6779         1,
   6780         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r_fields,
   6781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6782         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6783         -1,
   6784         -1,
   6785     },
   6786 #endif /* chips */
   6787 
   6788 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   6789     defined(BCM_56870_A0)
   6790     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56870_A0r */
   6791         soc_block_list[5],
   6792         soc_genreg,
   6793         1,
   6794         0,
   6795         0x57070000,
   6796         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6797         0,
   6798         4,
   6799         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56970_A0r_fields,
   6800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6801         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6802         -1,
   6803         -1,
   6804         0,
   6805     },
   6806 #endif /* chips */
   6807 
   6808 #if defined(BCM_56970_A0)
   6809     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56970_A0r */
   6810         soc_block_list[5],
   6811         soc_genreg,
   6812         1,
   6813         0,
   6814         0x57100000,
   6815         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6816         0,
   6817         4,
   6818         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56970_A0r_fields,
   6819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6820         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6821         -1,
   6822         -1,
   6823         0,
   6824     },
   6825 #endif /* chips */
   6826 
   6827 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6828     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_BCM56980_A0r */
   6829         soc_block_list[5],
   6830         soc_genreg,
   6831         1,
   6832         0,
   6833         0xa010c00,
   6834         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6835         0,
   6836         6,
   6837         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56980_A0r_fields,
   6838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6839         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6840         -1,
   6841         -1,
   6842         3,
   6843     },
   6844 #endif /* chips */
   6845 
   6846 #if defined(BCM_56970_A0)
   6847     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_PIPE0r */
   6848         soc_block_list[5],
   6849         soc_genreg,
   6850         1,
   6851         0,
   6852         0x57100000,
   6853         0,
   6854         0,
   6855         4,
   6856         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56970_A0r_fields,
   6857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6858         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6859         -1,
   6860         -1,
   6861         0,
   6862     },
   6863 #endif /* chips */
   6864 
   6865 #if defined(BCM_56970_A0)
   6866     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_PIPE1r */
   6867         soc_block_list[5],
   6868         soc_genreg,
   6869         1,
   6870         0,
   6871         0x57100000,
   6872         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6873         0,
   6874         4,
   6875         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56970_A0r_fields,
   6876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6877         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6878         -1,
   6879         -1,
   6880         0,
   6881     },
   6882 #endif /* chips */
   6883 
   6884 #if defined(BCM_56970_A0)
   6885     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_PIPE2r */
   6886         soc_block_list[5],
   6887         soc_genreg,
   6888         1,
   6889         0,
   6890         0x57100000,
   6891         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6892         0,
   6893         4,
   6894         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56970_A0r_fields,
   6895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6896         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6897         -1,
   6898         -1,
   6899         0,
   6900     },
   6901 #endif /* chips */
   6902 
   6903 #if defined(BCM_56970_A0)
   6904     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_PIPE3r */
   6905         soc_block_list[5],
   6906         soc_genreg,
   6907         1,
   6908         0,
   6909         0x57100000,
   6910         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6911         0,
   6912         4,
   6913         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56970_A0r_fields,
   6914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6916         -1,
   6917         -1,
   6918         0,
   6919     },
   6920 #endif /* chips */
   6921 
   6922 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   6923     defined(BCM_56870_A0)
   6924     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_PIPE0_BCM56870_A0r */
   6925         soc_block_list[5],
   6926         soc_genreg,
   6927         1,
   6928         0,
   6929         0x57070000,
   6930         0,
   6931         0,
   6932         4,
   6933         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56970_A0r_fields,
   6934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6935         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6936         -1,
   6937         -1,
   6938         0,
   6939     },
   6940 #endif /* chips */
   6941 
   6942 #if defined(BCM_56870_A0)
   6943     { /* SOC_REG_INT_VFP_POLICY_TABLE_RAM_CONTROL_PIPE1_BCM56870_A0r */
   6944         soc_block_list[5],
   6945         soc_genreg,
   6946         1,
   6947         0,
   6948         0x57070000,
   6949         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   6950         0,
   6951         4,
   6952         soc_VFP_POLICY_TABLE_RAM_CONTROL_BCM56970_A0r_fields,
   6953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6954         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6955         -1,
   6956         -1,
   6957         0,
   6958     },
   6959 #endif /* chips */
   6960 
   6961 #if defined(BCM_56514_A0)
   6962     { /* SOC_REG_INT_VFP_SLICE_CONTROLr */
   6963         soc_block_list[5],
   6964         soc_genreg,
   6965         1,
   6966         0,
   6967         0x408001b,
   6968         0,
   6969         0,
   6970         8,
   6971         soc_VFP_SLICE_CONTROLr_fields,
   6972         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   6973         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6974         -1,
   6975         -1,
   6976     },
   6977 #endif /* chips */
   6978 
   6979 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6980     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6981     defined(BCM_56160_A0)
   6982     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM53400_A0r */
   6983         soc_block_list[5],
   6984         soc_genreg,
   6985         1,
   6986         0,
   6987         0xe000100,
   6988         0,
   6989         0,
   6990         8,
   6991         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   6992         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   6993         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   6994         -1,
   6995         -1,
   6996     },
   6997 #endif /* chips */
   6998 
   6999 #if defined(BCM_56150_A0)
   7000     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56150_A0r */
   7001         soc_block_list[5],
   7002         soc_genreg,
   7003         1,
   7004         0,
   7005         0x12000100,
   7006         0,
   7007         0,
   7008         8,
   7009         soc_VFP_SLICE_CONTROL_BCM56640_A0r_fields,
   7010         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7011         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7012         -1,
   7013         -1,
   7014     },
   7015 #endif /* chips */
   7016 
   7017 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   7018     defined(BCM_56270_A0)
   7019     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56260_A0r */
   7020         soc_block_list[5],
   7021         soc_genreg,
   7022         1,
   7023         0,
   7024         0x12000200,
   7025         0,
   7026         0,
   7027         8,
   7028         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7029         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7030         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7031         -1,
   7032         -1,
   7033     },
   7034 #endif /* chips */
   7035 
   7036 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7037     defined(BCM_56450_B1)
   7038     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56450_A0r */
   7039         soc_block_list[5],
   7040         soc_genreg,
   7041         1,
   7042         0,
   7043         0x12000200,
   7044         0,
   7045         0,
   7046         8,
   7047         soc_VFP_SLICE_CONTROL_BCM56640_A0r_fields,
   7048         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7049         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7050         -1,
   7051         -1,
   7052     },
   7053 #endif /* chips */
   7054 
   7055 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   7056     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   7057     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56560_A0r */
   7058         soc_block_list[5],
   7059         soc_genreg,
   7060         1,
   7061         0,
   7062         0x12002000,
   7063         0,
   7064         0,
   7065         8,
   7066         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7067         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7068         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7069         -1,
   7070         -1,
   7071     },
   7072 #endif /* chips */
   7073 
   7074 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   7075     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   7076     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   7077     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   7078     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   7079     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   7080     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56624_A0r */
   7081         soc_block_list[5],
   7082         soc_genreg,
   7083         1,
   7084         0,
   7085         0x4080020,
   7086         0,
   7087         0,
   7088         8,
   7089         soc_VFP_SLICE_CONTROLr_fields,
   7090         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7091         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7092         -1,
   7093         -1,
   7094     },
   7095 #endif /* chips */
   7096 
   7097 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   7098     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56640_A0r */
   7099         soc_block_list[5],
   7100         soc_genreg,
   7101         1,
   7102         0,
   7103         0x12000200,
   7104         0,
   7105         0,
   7106         8,
   7107         soc_VFP_SLICE_CONTROL_BCM56640_A0r_fields,
   7108         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7109         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7110         -1,
   7111         -1,
   7112     },
   7113 #endif /* chips */
   7114 
   7115 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   7116     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56820_A0r */
   7117         soc_block_list[5],
   7118         soc_genreg,
   7119         1,
   7120         0,
   7121         0x4080601,
   7122         0,
   7123         0,
   7124         8,
   7125         soc_VFP_SLICE_CONTROLr_fields,
   7126         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7127         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7128         -1,
   7129         -1,
   7130     },
   7131 #endif /* chips */
   7132 
   7133 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   7134     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   7135     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56840_A0r */
   7136         soc_block_list[5],
   7137         soc_genreg,
   7138         1,
   7139         0,
   7140         0x4080620,
   7141         0,
   7142         0,
   7143         8,
   7144         soc_VFP_SLICE_CONTROLr_fields,
   7145         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7146         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7147         -1,
   7148         -1,
   7149     },
   7150 #endif /* chips */
   7151 
   7152 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   7153     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56850_A0r */
   7154         soc_block_list[5],
   7155         soc_genreg,
   7156         1,
   7157         0,
   7158         0x12002000,
   7159         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7160         0,
   7161         8,
   7162         soc_VFP_SLICE_CONTROL_BCM56640_A0r_fields,
   7163         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7164         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7165         -1,
   7166         -1,
   7167     },
   7168 #endif /* chips */
   7169 
   7170 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7171     defined(BCM_56870_A0)
   7172     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56870_A0r */
   7173         soc_block_list[5],
   7174         soc_genreg,
   7175         1,
   7176         0,
   7177         0x56002800,
   7178         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7179         0,
   7180         8,
   7181         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7182         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7183         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7184         -1,
   7185         -1,
   7186         0,
   7187     },
   7188 #endif /* chips */
   7189 
   7190 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7191     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56960_A0r */
   7192         soc_block_list[5],
   7193         soc_genreg,
   7194         1,
   7195         0,
   7196         0x32000200,
   7197         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7198         0,
   7199         8,
   7200         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7201         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7202         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7203         -1,
   7204         -1,
   7205         0,
   7206     },
   7207 #endif /* chips */
   7208 
   7209 #if defined(BCM_56970_A0)
   7210     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56970_A0r */
   7211         soc_block_list[5],
   7212         soc_genreg,
   7213         1,
   7214         0,
   7215         0x56000200,
   7216         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7217         0,
   7218         8,
   7219         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7220         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7221         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7222         -1,
   7223         -1,
   7224         0,
   7225     },
   7226 #endif /* chips */
   7227 
   7228 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7229     { /* SOC_REG_INT_VFP_SLICE_CONTROL_BCM56980_A0r */
   7230         soc_block_list[5],
   7231         soc_genreg,
   7232         1,
   7233         0,
   7234         0xa000400,
   7235         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7236         0,
   7237         8,
   7238         soc_VFP_SLICE_CONTROL_BCM56980_A0r_fields,
   7239         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7240         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7241         -1,
   7242         -1,
   7243         3,
   7244     },
   7245 #endif /* chips */
   7246 
   7247 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7248     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE0r */
   7249         soc_block_list[5],
   7250         soc_genreg,
   7251         1,
   7252         0,
   7253         0x32000200,
   7254         0,
   7255         0,
   7256         8,
   7257         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7258         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7259         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7260         -1,
   7261         -1,
   7262         0,
   7263     },
   7264 #endif /* chips */
   7265 
   7266 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7267     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE1r */
   7268         soc_block_list[5],
   7269         soc_genreg,
   7270         1,
   7271         0,
   7272         0x32000200,
   7273         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7274         0,
   7275         8,
   7276         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7277         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7278         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7279         -1,
   7280         -1,
   7281         0,
   7282     },
   7283 #endif /* chips */
   7284 
   7285 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7286     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE2r */
   7287         soc_block_list[5],
   7288         soc_genreg,
   7289         1,
   7290         0,
   7291         0x32000200,
   7292         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7293         0,
   7294         8,
   7295         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7296         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7297         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7298         -1,
   7299         -1,
   7300         0,
   7301     },
   7302 #endif /* chips */
   7303 
   7304 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7305     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE3r */
   7306         soc_block_list[5],
   7307         soc_genreg,
   7308         1,
   7309         0,
   7310         0x32000200,
   7311         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7312         0,
   7313         8,
   7314         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7315         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7316         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7317         -1,
   7318         -1,
   7319         0,
   7320     },
   7321 #endif /* chips */
   7322 
   7323 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7324     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE4r */
   7325         soc_block_list[5],
   7326         soc_genreg,
   7327         1,
   7328         0,
   7329         0xa000400,
   7330         (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7331         0,
   7332         8,
   7333         soc_VFP_SLICE_CONTROL_BCM56980_A0r_fields,
   7334         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7335         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7336         -1,
   7337         -1,
   7338         3,
   7339     },
   7340 #endif /* chips */
   7341 
   7342 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7343     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE5r */
   7344         soc_block_list[5],
   7345         soc_genreg,
   7346         1,
   7347         0,
   7348         0xa000400,
   7349         (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7350         0,
   7351         8,
   7352         soc_VFP_SLICE_CONTROL_BCM56980_A0r_fields,
   7353         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7354         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7355         -1,
   7356         -1,
   7357         3,
   7358     },
   7359 #endif /* chips */
   7360 
   7361 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7362     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE6r */
   7363         soc_block_list[5],
   7364         soc_genreg,
   7365         1,
   7366         0,
   7367         0xa000400,
   7368         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7369         0,
   7370         8,
   7371         soc_VFP_SLICE_CONTROL_BCM56980_A0r_fields,
   7372         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7373         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7374         -1,
   7375         -1,
   7376         3,
   7377     },
   7378 #endif /* chips */
   7379 
   7380 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7381     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE7r */
   7382         soc_block_list[5],
   7383         soc_genreg,
   7384         1,
   7385         0,
   7386         0xa000400,
   7387         (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7388         0,
   7389         8,
   7390         soc_VFP_SLICE_CONTROL_BCM56980_A0r_fields,
   7391         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7392         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7393         -1,
   7394         -1,
   7395         3,
   7396     },
   7397 #endif /* chips */
   7398 
   7399 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7400     defined(BCM_56870_A0)
   7401     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE0_BCM56870_A0r */
   7402         soc_block_list[5],
   7403         soc_genreg,
   7404         1,
   7405         0,
   7406         0x56002800,
   7407         0,
   7408         0,
   7409         8,
   7410         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7411         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7412         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7413         -1,
   7414         -1,
   7415         0,
   7416     },
   7417 #endif /* chips */
   7418 
   7419 #if defined(BCM_56970_A0)
   7420     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE0_BCM56970_A0r */
   7421         soc_block_list[5],
   7422         soc_genreg,
   7423         1,
   7424         0,
   7425         0x56000200,
   7426         0,
   7427         0,
   7428         8,
   7429         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7430         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7431         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7432         -1,
   7433         -1,
   7434         0,
   7435     },
   7436 #endif /* chips */
   7437 
   7438 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7439     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE0_BCM56980_A0r */
   7440         soc_block_list[5],
   7441         soc_genreg,
   7442         1,
   7443         0,
   7444         0xa000400,
   7445         0,
   7446         0,
   7447         8,
   7448         soc_VFP_SLICE_CONTROL_BCM56980_A0r_fields,
   7449         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7450         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7451         -1,
   7452         -1,
   7453         3,
   7454     },
   7455 #endif /* chips */
   7456 
   7457 #if defined(BCM_56870_A0)
   7458     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE1_BCM56870_A0r */
   7459         soc_block_list[5],
   7460         soc_genreg,
   7461         1,
   7462         0,
   7463         0x56002800,
   7464         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7465         0,
   7466         8,
   7467         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7468         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7469         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7470         -1,
   7471         -1,
   7472         0,
   7473     },
   7474 #endif /* chips */
   7475 
   7476 #if defined(BCM_56970_A0)
   7477     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE1_BCM56970_A0r */
   7478         soc_block_list[5],
   7479         soc_genreg,
   7480         1,
   7481         0,
   7482         0x56000200,
   7483         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7484         0,
   7485         8,
   7486         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7487         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7488         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7489         -1,
   7490         -1,
   7491         0,
   7492     },
   7493 #endif /* chips */
   7494 
   7495 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7496     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE1_BCM56980_A0r */
   7497         soc_block_list[5],
   7498         soc_genreg,
   7499         1,
   7500         0,
   7501         0xa000400,
   7502         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7503         0,
   7504         8,
   7505         soc_VFP_SLICE_CONTROL_BCM56980_A0r_fields,
   7506         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7507         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7508         -1,
   7509         -1,
   7510         3,
   7511     },
   7512 #endif /* chips */
   7513 
   7514 #if defined(BCM_56970_A0)
   7515     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE2_BCM56970_A0r */
   7516         soc_block_list[5],
   7517         soc_genreg,
   7518         1,
   7519         0,
   7520         0x56000200,
   7521         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7522         0,
   7523         8,
   7524         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7525         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7526         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7527         -1,
   7528         -1,
   7529         0,
   7530     },
   7531 #endif /* chips */
   7532 
   7533 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7534     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE2_BCM56980_A0r */
   7535         soc_block_list[5],
   7536         soc_genreg,
   7537         1,
   7538         0,
   7539         0xa000400,
   7540         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7541         0,
   7542         8,
   7543         soc_VFP_SLICE_CONTROL_BCM56980_A0r_fields,
   7544         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7545         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7546         -1,
   7547         -1,
   7548         3,
   7549     },
   7550 #endif /* chips */
   7551 
   7552 #if defined(BCM_56970_A0)
   7553     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE3_BCM56970_A0r */
   7554         soc_block_list[5],
   7555         soc_genreg,
   7556         1,
   7557         0,
   7558         0x56000200,
   7559         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7560         0,
   7561         8,
   7562         soc_VFP_SLICE_CONTROL_BCM53400_A0r_fields,
   7563         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7564         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7565         -1,
   7566         -1,
   7567         0,
   7568     },
   7569 #endif /* chips */
   7570 
   7571 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7572     { /* SOC_REG_INT_VFP_SLICE_CONTROL_PIPE3_BCM56980_A0r */
   7573         soc_block_list[5],
   7574         soc_genreg,
   7575         1,
   7576         0,
   7577         0xa000400,
   7578         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7579         0,
   7580         8,
   7581         soc_VFP_SLICE_CONTROL_BCM56980_A0r_fields,
   7582         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
   7583         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7584         -1,
   7585         -1,
   7586         3,
   7587     },
   7588 #endif /* chips */
   7589 
   7590 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   7591     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   7592     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   7593     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   7594     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   7595     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   7596     { /* SOC_REG_INT_VFP_SLICE_MAPr */
   7597         soc_block_list[5],
   7598         soc_genreg,
   7599         1,
   7600         0,
   7601         0x4080036,
   7602         0,
   7603         0,
   7604         8,
   7605         soc_EFP_SLICE_MAPr_fields,
   7606         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7607         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7608         -1,
   7609         -1,
   7610     },
   7611 #endif /* chips */
   7612 
   7613 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7614     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7615     defined(BCM_56160_A0)
   7616     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM53400_A0r */
   7617         soc_block_list[5],
   7618         soc_genreg,
   7619         1,
   7620         0,
   7621         0xe000300,
   7622         0,
   7623         0,
   7624         8,
   7625         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   7626         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7627         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7628         -1,
   7629         -1,
   7630     },
   7631 #endif /* chips */
   7632 
   7633 #if defined(BCM_56150_A0)
   7634     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56150_A0r */
   7635         soc_block_list[5],
   7636         soc_genreg,
   7637         1,
   7638         0,
   7639         0x12000300,
   7640         0,
   7641         0,
   7642         8,
   7643         soc_EFP_SLICE_MAP_BCM56640_A0r_fields,
   7644         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7645         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7646         -1,
   7647         -1,
   7648     },
   7649 #endif /* chips */
   7650 
   7651 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   7652     defined(BCM_56270_A0)
   7653     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56260_A0r */
   7654         soc_block_list[5],
   7655         soc_genreg,
   7656         1,
   7657         0,
   7658         0x12000500,
   7659         0,
   7660         0,
   7661         8,
   7662         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   7663         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7664         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7665         -1,
   7666         -1,
   7667     },
   7668 #endif /* chips */
   7669 
   7670 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7671     defined(BCM_56450_B1)
   7672     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56450_A0r */
   7673         soc_block_list[5],
   7674         soc_genreg,
   7675         1,
   7676         0,
   7677         0x12000500,
   7678         0,
   7679         0,
   7680         8,
   7681         soc_EFP_SLICE_MAP_BCM56640_A0r_fields,
   7682         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7683         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7684         -1,
   7685         -1,
   7686     },
   7687 #endif /* chips */
   7688 
   7689 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   7690     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   7691     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56560_A0r */
   7692         soc_block_list[5],
   7693         soc_genreg,
   7694         1,
   7695         0,
   7696         0x12003600,
   7697         0,
   7698         0,
   7699         8,
   7700         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   7701         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7702         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7703         -1,
   7704         -1,
   7705     },
   7706 #endif /* chips */
   7707 
   7708 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   7709     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56640_A0r */
   7710         soc_block_list[5],
   7711         soc_genreg,
   7712         1,
   7713         0,
   7714         0x12000500,
   7715         0,
   7716         0,
   7717         8,
   7718         soc_EFP_SLICE_MAP_BCM56640_A0r_fields,
   7719         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7720         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7721         -1,
   7722         -1,
   7723     },
   7724 #endif /* chips */
   7725 
   7726 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   7727     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56820_A0r */
   7728         soc_block_list[5],
   7729         soc_genreg,
   7730         1,
   7731         0,
   7732         0x4080604,
   7733         0,
   7734         0,
   7735         8,
   7736         soc_VFP_SLICE_MAPr_fields,
   7737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7738         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7739         -1,
   7740         -1,
   7741     },
   7742 #endif /* chips */
   7743 
   7744 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   7745     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   7746     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56840_A0r */
   7747         soc_block_list[5],
   7748         soc_genreg,
   7749         1,
   7750         0,
   7751         0x4080636,
   7752         0,
   7753         0,
   7754         8,
   7755         soc_EFP_SLICE_MAPr_fields,
   7756         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7757         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7758         -1,
   7759         -1,
   7760     },
   7761 #endif /* chips */
   7762 
   7763 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   7764     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56850_A0r */
   7765         soc_block_list[5],
   7766         soc_genreg,
   7767         1,
   7768         0,
   7769         0x12003600,
   7770         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7771         0,
   7772         8,
   7773         soc_EFP_SLICE_MAP_BCM56640_A0r_fields,
   7774         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7775         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7776         -1,
   7777         -1,
   7778     },
   7779 #endif /* chips */
   7780 
   7781 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   7782     defined(BCM_56870_A0)
   7783     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56870_A0r */
   7784         soc_block_list[5],
   7785         soc_genreg,
   7786         1,
   7787         0,
   7788         0x56002a00,
   7789         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7790         0,
   7791         8,
   7792         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   7793         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7794         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7795         -1,
   7796         -1,
   7797         0,
   7798     },
   7799 #endif /* chips */
   7800 
   7801 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7802     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56960_A0r */
   7803         soc_block_list[5],
   7804         soc_genreg,
   7805         1,
   7806         0,
   7807         0x32000500,
   7808         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7809         0,
   7810         8,
   7811         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   7812         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7813         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7814         -1,
   7815         -1,
   7816         0,
   7817     },
   7818 #endif /* chips */
   7819 
   7820 #if defined(BCM_56970_A0)
   7821     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56970_A0r */
   7822         soc_block_list[5],
   7823         soc_genreg,
   7824         1,
   7825         0,
   7826         0x56000500,
   7827         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7828         0,
   7829         8,
   7830         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   7831         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7832         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7833         -1,
   7834         -1,
   7835         0,
   7836     },
   7837 #endif /* chips */
   7838 
   7839 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7840     { /* SOC_REG_INT_VFP_SLICE_MAP_BCM56980_A0r */
   7841         soc_block_list[5],
   7842         soc_genreg,
   7843         1,
   7844         0,
   7845         0xa000500,
   7846         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7847         0,
   7848         8,
   7849         soc_EFP_SLICE_MAP_BCM56980_A0r_fields,
   7850         SOC_RESET_VAL_DEC(0x0000fa50, 0x00000000)
   7851         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7852         -1,
   7853         -1,
   7854         3,
   7855     },
   7856 #endif /* chips */
   7857 
   7858 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7859     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE0r */
   7860         soc_block_list[5],
   7861         soc_genreg,
   7862         1,
   7863         0,
   7864         0x32000500,
   7865         0,
   7866         0,
   7867         8,
   7868         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   7869         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7870         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7871         -1,
   7872         -1,
   7873         0,
   7874     },
   7875 #endif /* chips */
   7876 
   7877 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7878     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE1r */
   7879         soc_block_list[5],
   7880         soc_genreg,
   7881         1,
   7882         0,
   7883         0x32000500,
   7884         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7885         0,
   7886         8,
   7887         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   7888         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7889         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7890         -1,
   7891         -1,
   7892         0,
   7893     },
   7894 #endif /* chips */
   7895 
   7896 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7897     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE2r */
   7898         soc_block_list[5],
   7899         soc_genreg,
   7900         1,
   7901         0,
   7902         0x32000500,
   7903         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7904         0,
   7905         8,
   7906         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   7907         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7908         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7909         -1,
   7910         -1,
   7911         0,
   7912     },
   7913 #endif /* chips */
   7914 
   7915 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   7916     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE3r */
   7917         soc_block_list[5],
   7918         soc_genreg,
   7919         1,
   7920         0,
   7921         0x32000500,
   7922         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7923         0,
   7924         8,
   7925         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   7926         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   7927         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7928         -1,
   7929         -1,
   7930         0,
   7931     },
   7932 #endif /* chips */
   7933 
   7934 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7935     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE4r */
   7936         soc_block_list[5],
   7937         soc_genreg,
   7938         1,
   7939         0,
   7940         0xa000500,
   7941         (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7942         0,
   7943         8,
   7944         soc_EFP_SLICE_MAP_BCM56980_A0r_fields,
   7945         SOC_RESET_VAL_DEC(0x0000fa50, 0x00000000)
   7946         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7947         -1,
   7948         -1,
   7949         3,
   7950     },
   7951 #endif /* chips */
   7952 
   7953 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7954     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE5r */
   7955         soc_block_list[5],
   7956         soc_genreg,
   7957         1,
   7958         0,
   7959         0xa000500,
   7960         (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7961         0,
   7962         8,
   7963         soc_EFP_SLICE_MAP_BCM56980_A0r_fields,
   7964         SOC_RESET_VAL_DEC(0x0000fa50, 0x00000000)
   7965         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7966         -1,
   7967         -1,
   7968         3,
   7969     },
   7970 #endif /* chips */
   7971 
   7972 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7973     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE6r */
   7974         soc_block_list[5],
   7975         soc_genreg,
   7976         1,
   7977         0,
   7978         0xa000500,
   7979         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7980         0,
   7981         8,
   7982         soc_EFP_SLICE_MAP_BCM56980_A0r_fields,
   7983         SOC_RESET_VAL_DEC(0x0000fa50, 0x00000000)
   7984         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   7985         -1,
   7986         -1,
   7987         3,
   7988     },
   7989 #endif /* chips */
   7990 
   7991 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7992     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE7r */
   7993         soc_block_list[5],
   7994         soc_genreg,
   7995         1,
   7996         0,
   7997         0xa000500,
   7998         (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   7999         0,
   8000         8,
   8001         soc_EFP_SLICE_MAP_BCM56980_A0r_fields,
   8002         SOC_RESET_VAL_DEC(0x0000fa50, 0x00000000)
   8003         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8004         -1,
   8005         -1,
   8006         3,
   8007     },
   8008 #endif /* chips */
   8009 
   8010 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   8011     defined(BCM_56870_A0)
   8012     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE0_BCM56870_A0r */
   8013         soc_block_list[5],
   8014         soc_genreg,
   8015         1,
   8016         0,
   8017         0x56002a00,
   8018         0,
   8019         0,
   8020         8,
   8021         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   8022         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   8023         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8024         -1,
   8025         -1,
   8026         0,
   8027     },
   8028 #endif /* chips */
   8029 
   8030 #if defined(BCM_56970_A0)
   8031     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE0_BCM56970_A0r */
   8032         soc_block_list[5],
   8033         soc_genreg,
   8034         1,
   8035         0,
   8036         0x56000500,
   8037         0,
   8038         0,
   8039         8,
   8040         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   8041         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   8042         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8043         -1,
   8044         -1,
   8045         0,
   8046     },
   8047 #endif /* chips */
   8048 
   8049 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8050     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE0_BCM56980_A0r */
   8051         soc_block_list[5],
   8052         soc_genreg,
   8053         1,
   8054         0,
   8055         0xa000500,
   8056         0,
   8057         0,
   8058         8,
   8059         soc_EFP_SLICE_MAP_BCM56980_A0r_fields,
   8060         SOC_RESET_VAL_DEC(0x0000fa50, 0x00000000)
   8061         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8062         -1,
   8063         -1,
   8064         3,
   8065     },
   8066 #endif /* chips */
   8067 
   8068 #if defined(BCM_56870_A0)
   8069     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE1_BCM56870_A0r */
   8070         soc_block_list[5],
   8071         soc_genreg,
   8072         1,
   8073         0,
   8074         0x56002a00,
   8075         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8076         0,
   8077         8,
   8078         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   8079         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   8080         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8081         -1,
   8082         -1,
   8083         0,
   8084     },
   8085 #endif /* chips */
   8086 
   8087 #if defined(BCM_56970_A0)
   8088     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE1_BCM56970_A0r */
   8089         soc_block_list[5],
   8090         soc_genreg,
   8091         1,
   8092         0,
   8093         0x56000500,
   8094         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8095         0,
   8096         8,
   8097         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   8098         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   8099         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8100         -1,
   8101         -1,
   8102         0,
   8103     },
   8104 #endif /* chips */
   8105 
   8106 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8107     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE1_BCM56980_A0r */
   8108         soc_block_list[5],
   8109         soc_genreg,
   8110         1,
   8111         0,
   8112         0xa000500,
   8113         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8114         0,
   8115         8,
   8116         soc_EFP_SLICE_MAP_BCM56980_A0r_fields,
   8117         SOC_RESET_VAL_DEC(0x0000fa50, 0x00000000)
   8118         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8119         -1,
   8120         -1,
   8121         3,
   8122     },
   8123 #endif /* chips */
   8124 
   8125 #if defined(BCM_56970_A0)
   8126     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE2_BCM56970_A0r */
   8127         soc_block_list[5],
   8128         soc_genreg,
   8129         1,
   8130         0,
   8131         0x56000500,
   8132         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8133         0,
   8134         8,
   8135         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   8136         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   8137         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8138         -1,
   8139         -1,
   8140         0,
   8141     },
   8142 #endif /* chips */
   8143 
   8144 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8145     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE2_BCM56980_A0r */
   8146         soc_block_list[5],
   8147         soc_genreg,
   8148         1,
   8149         0,
   8150         0xa000500,
   8151         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8152         0,
   8153         8,
   8154         soc_EFP_SLICE_MAP_BCM56980_A0r_fields,
   8155         SOC_RESET_VAL_DEC(0x0000fa50, 0x00000000)
   8156         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8157         -1,
   8158         -1,
   8159         3,
   8160     },
   8161 #endif /* chips */
   8162 
   8163 #if defined(BCM_56970_A0)
   8164     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE3_BCM56970_A0r */
   8165         soc_block_list[5],
   8166         soc_genreg,
   8167         1,
   8168         0,
   8169         0x56000500,
   8170         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8171         0,
   8172         8,
   8173         soc_EFP_SLICE_MAP_BCM53400_A0r_fields,
   8174         SOC_RESET_VAL_DEC(0x0000e4e4, 0x00000000)
   8175         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8176         -1,
   8177         -1,
   8178         0,
   8179     },
   8180 #endif /* chips */
   8181 
   8182 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8183     { /* SOC_REG_INT_VFP_SLICE_MAP_PIPE3_BCM56980_A0r */
   8184         soc_block_list[5],
   8185         soc_genreg,
   8186         1,
   8187         0,
   8188         0xa000500,
   8189         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8190         0,
   8191         8,
   8192         soc_EFP_SLICE_MAP_BCM56980_A0r_fields,
   8193         SOC_RESET_VAL_DEC(0x0000fa50, 0x00000000)
   8194         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8195         -1,
   8196         -1,
   8197         3,
   8198     },
   8199 #endif /* chips */
   8200 
   8201 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   8202     { /* SOC_REG_INT_VFP_TCAM_BLKSELr */
   8203         soc_block_list[5],
   8204         soc_genreg,
   8205         1,
   8206         0,
   8207         0x12010900,
   8208         0,
   8209         0,
   8210         8,
   8211         soc_VFP_TCAM_BLKSELr_fields,
   8212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8213         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8214         -1,
   8215         -1,
   8216     },
   8217 #endif /* chips */
   8218 
   8219 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8220     { /* SOC_REG_INT_VFP_TMr */
   8221         soc_block_list[5],
   8222         soc_genreg,
   8223         1,
   8224         0,
   8225         0xa010d00,
   8226         SOC_REG_FLAG_64_BITS |
   8227                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8228         0,
   8229         1,
   8230         soc_ADAPT_RAM_CONTROLr_fields,
   8231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8232         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8233         -1,
   8234         -1,
   8235         3,
   8236     },
   8237 #endif /* chips */
   8238 
   8239 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8240     { /* SOC_REG_INT_VFP_TM_PIPE0r */
   8241         soc_block_list[5],
   8242         soc_genreg,
   8243         1,
   8244         0,
   8245         0xa010d00,
   8246         SOC_REG_FLAG_64_BITS,
   8247         0,
   8248         1,
   8249         soc_ADAPT_RAM_CONTROLr_fields,
   8250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8252         -1,
   8253         -1,
   8254         3,
   8255     },
   8256 #endif /* chips */
   8257 
   8258 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8259     { /* SOC_REG_INT_VFP_TM_PIPE1r */
   8260         soc_block_list[5],
   8261         soc_genreg,
   8262         1,
   8263         0,
   8264         0xa010d00,
   8265         SOC_REG_FLAG_64_BITS |
   8266                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8267         0,
   8268         1,
   8269         soc_ADAPT_RAM_CONTROLr_fields,
   8270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8271         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8272         -1,
   8273         -1,
   8274         3,
   8275     },
   8276 #endif /* chips */
   8277 
   8278 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8279     { /* SOC_REG_INT_VFP_TM_PIPE2r */
   8280         soc_block_list[5],
   8281         soc_genreg,
   8282         1,
   8283         0,
   8284         0xa010d00,
   8285         SOC_REG_FLAG_64_BITS |
   8286                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8287         0,
   8288         1,
   8289         soc_ADAPT_RAM_CONTROLr_fields,
   8290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8291         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8292         -1,
   8293         -1,
   8294         3,
   8295     },
   8296 #endif /* chips */
   8297 
   8298 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8299     { /* SOC_REG_INT_VFP_TM_PIPE3r */
   8300         soc_block_list[5],
   8301         soc_genreg,
   8302         1,
   8303         0,
   8304         0xa010d00,
   8305         SOC_REG_FLAG_64_BITS |
   8306                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8307         0,
   8308         1,
   8309         soc_ADAPT_RAM_CONTROLr_fields,
   8310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8311         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8312         -1,
   8313         -1,
   8314         3,
   8315     },
   8316 #endif /* chips */
   8317 
   8318 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8319     { /* SOC_REG_INT_VFP_TM_PIPE4r */
   8320         soc_block_list[5],
   8321         soc_genreg,
   8322         1,
   8323         0,
   8324         0xa010d00,
   8325         SOC_REG_FLAG_64_BITS |
   8326                           (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8327         0,
   8328         1,
   8329         soc_ADAPT_RAM_CONTROLr_fields,
   8330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8331         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8332         -1,
   8333         -1,
   8334         3,
   8335     },
   8336 #endif /* chips */
   8337 
   8338 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8339     { /* SOC_REG_INT_VFP_TM_PIPE5r */
   8340         soc_block_list[5],
   8341         soc_genreg,
   8342         1,
   8343         0,
   8344         0xa010d00,
   8345         SOC_REG_FLAG_64_BITS |
   8346                           (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8347         0,
   8348         1,
   8349         soc_ADAPT_RAM_CONTROLr_fields,
   8350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8351         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8352         -1,
   8353         -1,
   8354         3,
   8355     },
   8356 #endif /* chips */
   8357 
   8358 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8359     { /* SOC_REG_INT_VFP_TM_PIPE6r */
   8360         soc_block_list[5],
   8361         soc_genreg,
   8362         1,
   8363         0,
   8364         0xa010d00,
   8365         SOC_REG_FLAG_64_BITS |
   8366                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8367         0,
   8368         1,
   8369         soc_ADAPT_RAM_CONTROLr_fields,
   8370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8372         -1,
   8373         -1,
   8374         3,
   8375     },
   8376 #endif /* chips */
   8377 
   8378 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8379     { /* SOC_REG_INT_VFP_TM_PIPE7r */
   8380         soc_block_list[5],
   8381         soc_genreg,
   8382         1,
   8383         0,
   8384         0xa010d00,
   8385         SOC_REG_FLAG_64_BITS |
   8386                           (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8387         0,
   8388         1,
   8389         soc_ADAPT_RAM_CONTROLr_fields,
   8390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8391         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8392         -1,
   8393         -1,
   8394         3,
   8395     },
   8396 #endif /* chips */
   8397 
   8398 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8399     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8400     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8401     { /* SOC_REG_INT_VLAN_COS_MAP_PARITY_CONTROLr */
   8402         soc_block_list[5],
   8403         soc_genreg,
   8404         1,
   8405         0,
   8406         0xe080279,
   8407         0,
   8408         0,
   8409         1,
   8410         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   8411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8412         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8413         -1,
   8414         -1,
   8415     },
   8416 #endif /* chips */
   8417 
   8418 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8419     { /* SOC_REG_INT_VLAN_COS_MAP_PARITY_CONTROL_BCM56440_A0r */
   8420         soc_block_list[5],
   8421         soc_genreg,
   8422         1,
   8423         0,
   8424         0xf080d48,
   8425         0,
   8426         0,
   8427         1,
   8428         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
   8429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8430         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8431         -1,
   8432         -1,
   8433     },
   8434 #endif /* chips */
   8435 
   8436 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   8437     { /* SOC_REG_INT_VLAN_COS_MAP_PARITY_CONTROL_BCM56840_A0r */
   8438         soc_block_list[5],
   8439         soc_genreg,
   8440         1,
   8441         0,
   8442         0xf080d46,
   8443         0,
   8444         0,
   8445         1,
   8446         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
   8447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8448         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8449         -1,
   8450         -1,
   8451     },
   8452 #endif /* chips */
   8453 
   8454 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8455     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8456     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8457     { /* SOC_REG_INT_VLAN_COS_MAP_PARITY_STATUS_INTRr */
   8458         soc_block_list[5],
   8459         soc_genreg,
   8460         1,
   8461         0,
   8462         0xe08027a,
   8463         0,
   8464         0,
   8465         3,
   8466         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
   8467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8468         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   8469         -1,
   8470         -1,
   8471     },
   8472 #endif /* chips */
   8473 
   8474 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8475     { /* SOC_REG_INT_VLAN_COS_MAP_PARITY_STATUS_INTR_BCM56440_A0r */
   8476         soc_block_list[5],
   8477         soc_genreg,
   8478         1,
   8479         0,
   8480         0xf080d49,
   8481         0,
   8482         0,
   8483         3,
   8484         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
   8485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8486         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8487         -1,
   8488         -1,
   8489     },
   8490 #endif /* chips */
   8491 
   8492 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   8493     { /* SOC_REG_INT_VLAN_COS_MAP_PARITY_STATUS_INTR_BCM56840_A0r */
   8494         soc_block_list[5],
   8495         soc_genreg,
   8496         1,
   8497         0,
   8498         0xf080d47,
   8499         0,
   8500         0,
   8501         3,
   8502         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
   8503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8504         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8505         -1,
   8506         -1,
   8507     },
   8508 #endif /* chips */
   8509 
   8510 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8511     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8512     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8513     { /* SOC_REG_INT_VLAN_COS_MAP_PARITY_STATUS_NACKr */
   8514         soc_block_list[5],
   8515         soc_genreg,
   8516         1,
   8517         0,
   8518         0xe08027b,
   8519         0,
   8520         0,
   8521         3,
   8522         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
   8523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8524         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   8525         -1,
   8526         -1,
   8527     },
   8528 #endif /* chips */
   8529 
   8530 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   8531     { /* SOC_REG_INT_VLAN_COS_MAP_PARITY_STATUS_NACK_BCM56440_A0r */
   8532         soc_block_list[5],
   8533         soc_genreg,
   8534         1,
   8535         0,
   8536         0xf080d4a,
   8537         0,
   8538         0,
   8539         3,
   8540         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
   8541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8542         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8543         -1,
   8544         -1,
   8545     },
   8546 #endif /* chips */
   8547 
   8548 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   8549     { /* SOC_REG_INT_VLAN_COS_MAP_PARITY_STATUS_NACK_BCM56840_A0r */
   8550         soc_block_list[5],
   8551         soc_genreg,
   8552         1,
   8553         0,
   8554         0xf080d48,
   8555         0,
   8556         0,
   8557         3,
   8558         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
   8559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8560         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8561         -1,
   8562         -1,
   8563     },
   8564 #endif /* chips */
   8565 
   8566 #if defined(BCM_56504_A0)
   8567     { /* SOC_REG_INT_VLAN_CTRLr */
   8568         soc_block_list[5],
   8569         soc_genreg,
   8570         1,
   8571         0,
   8572         0x1080002,
   8573         0,
   8574         0,
   8575         3,
   8576         soc_VLAN_CTRLr_fields,
   8577         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8578         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8579         -1,
   8580         -1,
   8581     },
   8582 #endif /* chips */
   8583 
   8584 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   8585     { /* SOC_REG_INT_VLAN_CTRL_BCM53314_A0r */
   8586         soc_block_list[5],
   8587         soc_genreg,
   8588         1,
   8589         0,
   8590         0x1080003,
   8591         0,
   8592         0,
   8593         3,
   8594         soc_VLAN_CTRL_BCM53314_A0r_fields,
   8595         SOC_RESET_VAL_DEC(0x10201001, 0x00000000)
   8596         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8597         -1,
   8598         -1,
   8599     },
   8600 #endif /* chips */
   8601 
   8602 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8603     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8604     defined(BCM_56160_A0) || defined(BCM_56560_A0) || \
   8605     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   8606     defined(BCM_56670_B0)
   8607     { /* SOC_REG_INT_VLAN_CTRL_BCM53400_A0r */
   8608         soc_block_list[5],
   8609         soc_genreg,
   8610         1,
   8611         0,
   8612         0x6000300,
   8613         0,
   8614         0,
   8615         3,
   8616         soc_VLAN_CTRL_BCM53400_A0r_fields,
   8617         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8618         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8619         -1,
   8620         -1,
   8621     },
   8622 #endif /* chips */
   8623 
   8624 #if defined(BCM_56150_A0)
   8625     { /* SOC_REG_INT_VLAN_CTRL_BCM56150_A0r */
   8626         soc_block_list[5],
   8627         soc_genreg,
   8628         1,
   8629         0,
   8630         0x6000300,
   8631         0,
   8632         0,
   8633         3,
   8634         soc_VLAN_CTRL_BCM56640_A0r_fields,
   8635         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8636         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8637         -1,
   8638         -1,
   8639     },
   8640 #endif /* chips */
   8641 
   8642 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   8643     defined(BCM_56270_A0)
   8644     { /* SOC_REG_INT_VLAN_CTRL_BCM56260_A0r */
   8645         soc_block_list[5],
   8646         soc_genreg,
   8647         1,
   8648         0,
   8649         0x6000200,
   8650         0,
   8651         0,
   8652         3,
   8653         soc_VLAN_CTRL_BCM53400_A0r_fields,
   8654         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8655         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8656         -1,
   8657         -1,
   8658     },
   8659 #endif /* chips */
   8660 
   8661 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   8662     defined(BCM_56450_B1)
   8663     { /* SOC_REG_INT_VLAN_CTRL_BCM56450_A0r */
   8664         soc_block_list[5],
   8665         soc_genreg,
   8666         1,
   8667         0,
   8668         0x6000200,
   8669         0,
   8670         0,
   8671         3,
   8672         soc_VLAN_CTRL_BCM56640_A0r_fields,
   8673         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8674         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8675         -1,
   8676         -1,
   8677     },
   8678 #endif /* chips */
   8679 
   8680 #if defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   8681     defined(BCM_56224_B0) || defined(BCM_56314_A0) || \
   8682     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   8683     defined(BCM_56504_B0) || defined(BCM_56514_A0) || \
   8684     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   8685     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   8686     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   8687     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   8688     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   8689     { /* SOC_REG_INT_VLAN_CTRL_BCM56504_B0r */
   8690         soc_block_list[5],
   8691         soc_genreg,
   8692         1,
   8693         0,
   8694         0x1080003,
   8695         0,
   8696         0,
   8697         3,
   8698         soc_VLAN_CTRLr_fields,
   8699         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8700         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8701         -1,
   8702         -1,
   8703     },
   8704 #endif /* chips */
   8705 
   8706 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   8707     { /* SOC_REG_INT_VLAN_CTRL_BCM56640_A0r */
   8708         soc_block_list[5],
   8709         soc_genreg,
   8710         1,
   8711         0,
   8712         0x6000200,
   8713         0,
   8714         0,
   8715         3,
   8716         soc_VLAN_CTRL_BCM56640_A0r_fields,
   8717         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8718         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8719         -1,
   8720         -1,
   8721     },
   8722 #endif /* chips */
   8723 
   8724 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   8725     defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
   8726     defined(BCM_56820_A0) || defined(BCM_56840_A0) || \
   8727     defined(BCM_56840_B0)
   8728     { /* SOC_REG_INT_VLAN_CTRL_BCM56800_A0r */
   8729         soc_block_list[5],
   8730         soc_genreg,
   8731         1,
   8732         0,
   8733         0x1080603,
   8734         0,
   8735         0,
   8736         3,
   8737         soc_VLAN_CTRLr_fields,
   8738         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8739         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8740         -1,
   8741         -1,
   8742     },
   8743 #endif /* chips */
   8744 
   8745 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   8746     { /* SOC_REG_INT_VLAN_CTRL_BCM56850_A0r */
   8747         soc_block_list[5],
   8748         soc_genreg,
   8749         1,
   8750         0,
   8751         0x6000300,
   8752         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8753         0,
   8754         3,
   8755         soc_VLAN_CTRL_BCM56640_A0r_fields,
   8756         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8757         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8758         -1,
   8759         -1,
   8760     },
   8761 #endif /* chips */
   8762 
   8763 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   8764     defined(BCM_56870_A0)
   8765     { /* SOC_REG_INT_VLAN_CTRL_BCM56870_A0r */
   8766         soc_block_list[115],
   8767         soc_genreg,
   8768         1,
   8769         0,
   8770         0x2001100,
   8771         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8772         SOC_REG_FLAG_CCH,
   8773         3,
   8774         soc_VLAN_CTRL_BCM53400_A0r_fields,
   8775         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8776         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8777         -1,
   8778         -1,
   8779         3,
   8780     },
   8781 #endif /* chips */
   8782 
   8783 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   8784     { /* SOC_REG_INT_VLAN_CTRL_BCM56960_A0r */
   8785         soc_block_list[5],
   8786         soc_genreg,
   8787         1,
   8788         0,
   8789         0x2a000200,
   8790         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8791         0,
   8792         3,
   8793         soc_VLAN_CTRL_BCM53400_A0r_fields,
   8794         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8795         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8796         -1,
   8797         -1,
   8798         3,
   8799     },
   8800 #endif /* chips */
   8801 
   8802 #if defined(BCM_56970_A0)
   8803     { /* SOC_REG_INT_VLAN_CTRL_BCM56970_A0r */
   8804         soc_block_list[5],
   8805         soc_genreg,
   8806         1,
   8807         0,
   8808         0x4e000200,
   8809         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8810         0,
   8811         3,
   8812         soc_VLAN_CTRL_BCM53400_A0r_fields,
   8813         SOC_RESET_VAL_DEC(0x10200000, 0x00000000)
   8814         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   8815         -1,
   8816         -1,
   8817         3,
   8818     },
   8819 #endif /* chips */
   8820 
   8821 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8822     { /* SOC_REG_INT_VLAN_CTRL_BCM56980_A0r */
   8823         soc_block_list[5],
   8824         soc_genreg,
   8825         1,
   8826         0,
   8827         0x6002600,
   8828         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   8829         0,
   8830         2,
   8831         soc_VLAN_CTRL_BCM56980_A0r_fields,
   8832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8833         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   8834         -1,
   8835         -1,
   8836         3,
   8837     },
   8838 #endif /* chips */
   8839 
   8840 #if defined(BCM_56800_A0)
   8841     { /* SOC_REG_INT_VLAN_DBGCTRLr */
   8842         soc_block_list[5],
   8843         soc_genreg,
   8844         1,
   8845         0,
   8846         0x5080c00,
   8847         0,
   8848         0,
   8849         1,
   8850         soc_CFAPMEMDEBUGr_fields,
   8851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8852         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8853         -1,
   8854         -1,
   8855     },
   8856 #endif /* chips */
   8857 
   8858 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8859     { /* SOC_REG_INT_VLAN_DBGCTRL_0r */
   8860         soc_block_list[5],
   8861         soc_genreg,
   8862         1,
   8863         0,
   8864         0x12010600,
   8865         0,
   8866         0,
   8867         3,
   8868         soc_VLAN_DBGCTRL_0r_fields,
   8869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8870         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8871         -1,
   8872         -1,
   8873     },
   8874 #endif /* chips */
   8875 
   8876 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   8877     { /* SOC_REG_INT_VLAN_DBGCTRL_1r */
   8878         soc_block_list[5],
   8879         soc_genreg,
   8880         1,
   8881         0,
   8882         0x12010700,
   8883         0,
   8884         0,
   8885         2,
   8886         soc_VLAN_DBGCTRL_1r_fields,
   8887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8888         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8889         -1,
   8890         -1,
   8891     },
   8892 #endif /* chips */
   8893 
   8894 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8895     defined(BCM_56160_A0)
   8896     { /* SOC_REG_INT_VLAN_DBGCTRL_BCM53400_A0r */
   8897         soc_block_list[5],
   8898         soc_genreg,
   8899         1,
   8900         0,
   8901         0x12010000,
   8902         0,
   8903         0,
   8904         2,
   8905         soc_VLAN_DBGCTRL_BCM53400_A0r_fields,
   8906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8907         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8908         -1,
   8909         -1,
   8910     },
   8911 #endif /* chips */
   8912 
   8913 #if defined(BCM_56150_A0)
   8914     { /* SOC_REG_INT_VLAN_DBGCTRL_BCM56150_A0r */
   8915         soc_block_list[5],
   8916         soc_genreg,
   8917         1,
   8918         0,
   8919         0x16010000,
   8920         0,
   8921         0,
   8922         2,
   8923         soc_VLAN_DBGCTRL_BCM56150_A0r_fields,
   8924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8926         -1,
   8927         -1,
   8928     },
   8929 #endif /* chips */
   8930 
   8931 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   8932     defined(BCM_56334_B0)
   8933     { /* SOC_REG_INT_VLAN_DBGCTRL_BCM56334_A0r */
   8934         soc_block_list[5],
   8935         soc_genreg,
   8936         1,
   8937         0,
   8938         0x508012d,
   8939         0,
   8940         0,
   8941         2,
   8942         soc_VLAN_DBGCTRLr_fields,
   8943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8944         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8945         -1,
   8946         -1,
   8947     },
   8948 #endif /* chips */
   8949 
   8950 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   8951     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   8952     { /* SOC_REG_INT_VLAN_DBGCTRL_BCM56624_A0r */
   8953         soc_block_list[5],
   8954         soc_genreg,
   8955         1,
   8956         0,
   8957         0x508011a,
   8958         0,
   8959         0,
   8960         1,
   8961         soc_CFAPMEMDEBUGr_fields,
   8962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8963         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8964         -1,
   8965         -1,
   8966     },
   8967 #endif /* chips */
   8968 
   8969 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8970     { /* SOC_REG_INT_VLAN_DBGCTRL_BCM56820_A0r */
   8971         soc_block_list[5],
   8972         soc_genreg,
   8973         1,
   8974         0,
   8975         0x5080c00,
   8976         0,
   8977         0,
   8978         2,
   8979         soc_CFAPMEMDEBUG_BCM56820_A0r_fields,
   8980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8981         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8982         -1,
   8983         -1,
   8984     },
   8985 #endif /* chips */
   8986 
   8987 #if defined(BCM_56150_A0)
   8988     { /* SOC_REG_INT_VLAN_DEFAULT_PBMr */
   8989         soc_block_list[5],
   8990         soc_genreg,
   8991         1,
   8992         0,
   8993         0x16000000,
   8994         0,
   8995         0,
   8996         1,
   8997         soc_VLAN_DEFAULT_PBMr_fields,
   8998         SOC_RESET_VAL_DEC(0x3ffffffc, 0x00000000)
   8999         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   9000         -1,
   9001         -1,
   9002     },
   9003 #endif /* chips */
   9004 
   9005 #if defined(BCM_53400_A0)
   9006     { /* SOC_REG_INT_VLAN_DEFAULT_PBM_BCM53400_A0r */
   9007         soc_block_list[5],
   9008         soc_genreg,
   9009         1,
   9010         0,
   9011         0x12000000,
   9012         0,
   9013         0,
   9014         1,
   9015         soc_VLAN_DEFAULT_PBM_BCM53400_A0r_fields,
   9016         SOC_RESET_VAL_DEC(0x3ffffffc, 0x00000000)
   9017         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   9018         -1,
   9019         -1,
   9020     },
   9021 #endif /* chips */
   9022 
   9023 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
   9024     { /* SOC_REG_INT_VLAN_DEFAULT_PBM_BCM56160_A0r */
   9025         soc_block_list[5],
   9026         soc_genreg,
   9027         1,
   9028         0,
   9029         0x12000000,
   9030         0,
   9031         0,
   9032         1,
   9033         soc_VLAN_DEFAULT_PBM_BCM56160_A0r_fields,
   9034         SOC_RESET_VAL_DEC(0xfffffffc, 0x00000000)
   9035         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9036         -1,
   9037         -1,
   9038     },
   9039 #endif /* chips */
   9040 
   9041 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   9042     { /* SOC_REG_INT_VLAN_DEFAULT_PBM_HIr */
   9043         soc_block_list[5],
   9044         soc_genreg,
   9045         1,
   9046         0,
   9047         0x12000100,
   9048         SOC_REG_FLAG_64_BITS,
   9049         0,
   9050         2,
   9051         soc_VLAN_DEFAULT_PBM_HIr_fields,
   9052         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   9053         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9054         -1,
   9055         -1,
   9056     },
   9057 #endif /* chips */
   9058 
   9059 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   9060     { /* SOC_REG_INT_VLAN_DEFAULT_PBM_LOr */
   9061         soc_block_list[5],
   9062         soc_genreg,
   9063         1,
   9064         0,
   9065         0x12000000,
   9066         SOC_REG_FLAG_64_BITS,
   9067         0,
   9068         3,
   9069         soc_VLAN_DEFAULT_PBM_LOr_fields,
   9070         SOC_RESET_VAL_DEC(0xfffffffc, 0xffffffff)
   9071         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9072         -1,
   9073         -1,
   9074     },
   9075 #endif /* chips */
   9076 
   9077 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   9078     defined(BCM_56270_A0)
   9079     { /* SOC_REG_INT_VLAN_ECC_CONTROLr */
   9080         soc_block_list[5],
   9081         soc_genreg,
   9082         1,
   9083         0,
   9084         0x16010000,
   9085         0,
   9086         0,
   9087         2,
   9088         soc_EGR_MASK_ECC_CONTROLr_fields,
   9089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9090         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9091         -1,
   9092         -1,
   9093     },
   9094 #endif /* chips */
   9095 
   9096 #if defined(BCM_88732_A0)
   9097     { /* SOC_REG_INT_VLAN_ECC_STATUSr */
   9098         soc_block_list[5],
   9099         soc_genreg,
   9100         1,
   9101         0,
   9102         0x5080158,
   9103         0,
   9104         0,
   9105         1,
   9106         soc_VLAN_ECC_STATUSr_fields,
   9107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9109         -1,
   9110         -1,
   9111     },
   9112 #endif /* chips */
   9113 
   9114 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   9115     { /* SOC_REG_INT_VLAN_ING_PRI_CNG_MAP_DBGCTRLr */
   9116         soc_block_list[5],
   9117         soc_genreg,
   9118         1,
   9119         0,
   9120         0x4080c44,
   9121         0,
   9122         0,
   9123         2,
   9124         soc_CFAPMEMDEBUG_BCM56820_A0r_fields,
   9125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9126         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9127         -1,
   9128         -1,
   9129     },
   9130 #endif /* chips */
   9131 
   9132 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   9133     { /* SOC_REG_INT_VLAN_MAC_AUX_HASH_CONTROLr */
   9134         soc_block_list[5],
   9135         soc_genreg,
   9136         1,
   9137         0,
   9138         0x4080010,
   9139         0,
   9140         0,
   9141         2,
   9142         soc_L2_AUX_HASH_CONTROLr_fields,
   9143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9144         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9145         -1,
   9146         -1,
   9147     },
   9148 #endif /* chips */
   9149 
   9150 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   9151     { /* SOC_REG_INT_VLAN_MAC_AUX_HASH_CONTROL_BCM53314_A0r */
   9152         soc_block_list[5],
   9153         soc_genreg,
   9154         1,
   9155         0,
   9156         0x4080010,
   9157         0,
   9158         0,
   9159         2,
   9160         soc_L2_AUX_HASH_CONTROL_BCM53314_A0r_fields,
   9161         SOC_RESET_VAL_DEC(0x00000009, 0x00000000)
   9162         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   9163         -1,
   9164         -1,
   9165     },
   9166 #endif /* chips */
   9167 
   9168 #if defined(BCM_56800_A0)
   9169     { /* SOC_REG_INT_VLAN_MAC_DBGCTRLr */
   9170         soc_block_list[5],
   9171         soc_genreg,
   9172         1,
   9173         0,
   9174         0x4080c11,
   9175         0,
   9176         0,
   9177         1,
   9178         soc_CFAPMEMDEBUGr_fields,
   9179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9180         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9181         -1,
   9182         -1,
   9183     },
   9184 #endif /* chips */
   9185 
   9186 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   9187     { /* SOC_REG_INT_VLAN_MAC_OR_XLATE_PARITY_CONTROLr */
   9188         soc_block_list[5],
   9189         soc_genreg,
   9190         1,
   9191         0,
   9192         0x4080c05,
   9193         0,
   9194         0,
   9195         2,
   9196         soc_L2_ENTRY_PARITY_CONTROLr_fields,
   9197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9198         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   9199         -1,
   9200         -1,
   9201     },
   9202 #endif /* chips */
   9203 
   9204 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   9205     { /* SOC_REG_INT_VLAN_MAC_OR_XLATE_PARITY_STATUSr */
   9206         soc_block_list[5],
   9207         soc_genreg,
   9208         1,
   9209         0,
   9210         0x4080c06,
   9211         SOC_REG_FLAG_RO,
   9212         0,
   9213         4,
   9214         soc_VLAN_MAC_OR_XLATE_PARITY_STATUSr_fields,
   9215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9216         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
   9217         -1,
   9218         -1,
   9219     },
   9220 #endif /* chips */
   9221 
   9222 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9223     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9224     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9225     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRLr */
   9226         soc_block_list[5],
   9227         soc_genreg,
   9228         1,
   9229         0,
   9230         0x6080152,
   9231         0,
   9232         0,
   9233         3,
   9234         soc_VLAN_MEMORY_DBGCTRLr_fields,
   9235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9236         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9237         -1,
   9238         -1,
   9239     },
   9240 #endif /* chips */
   9241 
   9242 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9243     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_0r */
   9244         soc_block_list[5],
   9245         soc_genreg,
   9246         1,
   9247         0,
   9248         0x3b050000,
   9249         SOC_REG_FLAG_64_BITS |
   9250                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9251         0,
   9252         8,
   9253         soc_VLAN_MEMORY_DBGCTRL_0r_fields,
   9254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9255         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9256         -1,
   9257         -1,
   9258         3,
   9259     },
   9260 #endif /* chips */
   9261 
   9262 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9263     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1r */
   9264         soc_block_list[5],
   9265         soc_genreg,
   9266         1,
   9267         0,
   9268         0x3b060000,
   9269         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9270         0,
   9271         2,
   9272         soc_VLAN_MEMORY_DBGCTRL_1r_fields,
   9273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9274         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9275         -1,
   9276         -1,
   9277         3,
   9278     },
   9279 #endif /* chips */
   9280 
   9281 #if defined(BCM_56970_A0)
   9282     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_0_BCM56970_A0r */
   9283         soc_block_list[5],
   9284         soc_genreg,
   9285         1,
   9286         0,
   9287         0x5f060000,
   9288         SOC_REG_FLAG_64_BITS |
   9289                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9290         0,
   9291         8,
   9292         soc_VLAN_MEMORY_DBGCTRL_0_BCM56970_A0r_fields,
   9293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9294         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9295         -1,
   9296         -1,
   9297         3,
   9298     },
   9299 #endif /* chips */
   9300 
   9301 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9302     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_0_PIPE0r */
   9303         soc_block_list[5],
   9304         soc_genreg,
   9305         1,
   9306         0,
   9307         0x3b050000,
   9308         SOC_REG_FLAG_64_BITS,
   9309         0,
   9310         8,
   9311         soc_VLAN_MEMORY_DBGCTRL_0r_fields,
   9312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9313         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9314         -1,
   9315         -1,
   9316         3,
   9317     },
   9318 #endif /* chips */
   9319 
   9320 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9321     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_0_PIPE1r */
   9322         soc_block_list[5],
   9323         soc_genreg,
   9324         1,
   9325         0,
   9326         0x3b050000,
   9327         SOC_REG_FLAG_64_BITS |
   9328                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9329         0,
   9330         8,
   9331         soc_VLAN_MEMORY_DBGCTRL_0r_fields,
   9332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9333         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9334         -1,
   9335         -1,
   9336         3,
   9337     },
   9338 #endif /* chips */
   9339 
   9340 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9341     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_0_PIPE2r */
   9342         soc_block_list[5],
   9343         soc_genreg,
   9344         1,
   9345         0,
   9346         0x3b050000,
   9347         SOC_REG_FLAG_64_BITS |
   9348                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9349         0,
   9350         8,
   9351         soc_VLAN_MEMORY_DBGCTRL_0r_fields,
   9352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9353         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9354         -1,
   9355         -1,
   9356         3,
   9357     },
   9358 #endif /* chips */
   9359 
   9360 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9361     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_0_PIPE3r */
   9362         soc_block_list[5],
   9363         soc_genreg,
   9364         1,
   9365         0,
   9366         0x3b050000,
   9367         SOC_REG_FLAG_64_BITS |
   9368                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9369         0,
   9370         8,
   9371         soc_VLAN_MEMORY_DBGCTRL_0r_fields,
   9372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9373         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9374         -1,
   9375         -1,
   9376         3,
   9377     },
   9378 #endif /* chips */
   9379 
   9380 #if defined(BCM_56970_A0)
   9381     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_0_PIPE0_BCM56970_A0r */
   9382         soc_block_list[5],
   9383         soc_genreg,
   9384         1,
   9385         0,
   9386         0x5f060000,
   9387         SOC_REG_FLAG_64_BITS,
   9388         0,
   9389         8,
   9390         soc_VLAN_MEMORY_DBGCTRL_0_BCM56970_A0r_fields,
   9391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9392         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9393         -1,
   9394         -1,
   9395         3,
   9396     },
   9397 #endif /* chips */
   9398 
   9399 #if defined(BCM_56970_A0)
   9400     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_0_PIPE1_BCM56970_A0r */
   9401         soc_block_list[5],
   9402         soc_genreg,
   9403         1,
   9404         0,
   9405         0x5f060000,
   9406         SOC_REG_FLAG_64_BITS |
   9407                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9408         0,
   9409         8,
   9410         soc_VLAN_MEMORY_DBGCTRL_0_BCM56970_A0r_fields,
   9411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9412         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9413         -1,
   9414         -1,
   9415         3,
   9416     },
   9417 #endif /* chips */
   9418 
   9419 #if defined(BCM_56970_A0)
   9420     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_0_PIPE2_BCM56970_A0r */
   9421         soc_block_list[5],
   9422         soc_genreg,
   9423         1,
   9424         0,
   9425         0x5f060000,
   9426         SOC_REG_FLAG_64_BITS |
   9427                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9428         0,
   9429         8,
   9430         soc_VLAN_MEMORY_DBGCTRL_0_BCM56970_A0r_fields,
   9431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9433         -1,
   9434         -1,
   9435         3,
   9436     },
   9437 #endif /* chips */
   9438 
   9439 #if defined(BCM_56970_A0)
   9440     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_0_PIPE3_BCM56970_A0r */
   9441         soc_block_list[5],
   9442         soc_genreg,
   9443         1,
   9444         0,
   9445         0x5f060000,
   9446         SOC_REG_FLAG_64_BITS |
   9447                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9448         0,
   9449         8,
   9450         soc_VLAN_MEMORY_DBGCTRL_0_BCM56970_A0r_fields,
   9451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9452         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9453         -1,
   9454         -1,
   9455         3,
   9456     },
   9457 #endif /* chips */
   9458 
   9459 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   9460     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_BCM56560_A0r */
   9461         soc_block_list[5],
   9462         soc_genreg,
   9463         1,
   9464         0,
   9465         0x17060000,
   9466         0,
   9467         0,
   9468         4,
   9469         soc_VLAN_MEMORY_DBGCTRL_1_BCM56560_A0r_fields,
   9470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9471         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9472         -1,
   9473         -1,
   9474     },
   9475 #endif /* chips */
   9476 
   9477 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9478     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_BCM56670_A0r */
   9479         soc_block_list[5],
   9480         soc_genreg,
   9481         1,
   9482         0,
   9483         0x17060000,
   9484         0,
   9485         0,
   9486         4,
   9487         soc_VLAN_MEMORY_DBGCTRL_1_BCM56670_A0r_fields,
   9488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9489         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9490         -1,
   9491         -1,
   9492     },
   9493 #endif /* chips */
   9494 
   9495 #if defined(BCM_56860_A0)
   9496     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_BCM56860_A0r */
   9497         soc_block_list[5],
   9498         soc_genreg,
   9499         1,
   9500         0,
   9501         0x17060000,
   9502         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9503         0,
   9504         4,
   9505         soc_VLAN_MEMORY_DBGCTRL_1_BCM56860_A0r_fields,
   9506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9507         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9508         -1,
   9509         -1,
   9510     },
   9511 #endif /* chips */
   9512 
   9513 #if defined(BCM_56970_A0)
   9514     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_BCM56970_A0r */
   9515         soc_block_list[5],
   9516         soc_genreg,
   9517         1,
   9518         0,
   9519         0x5f070000,
   9520         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9521         0,
   9522         3,
   9523         soc_VLAN_MEMORY_DBGCTRL_1_BCM56970_A0r_fields,
   9524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9525         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9526         -1,
   9527         -1,
   9528         3,
   9529     },
   9530 #endif /* chips */
   9531 
   9532 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9533     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_PIPE0r */
   9534         soc_block_list[5],
   9535         soc_genreg,
   9536         1,
   9537         0,
   9538         0x3b060000,
   9539         0,
   9540         0,
   9541         2,
   9542         soc_VLAN_MEMORY_DBGCTRL_1r_fields,
   9543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9544         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9545         -1,
   9546         -1,
   9547         3,
   9548     },
   9549 #endif /* chips */
   9550 
   9551 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9552     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_PIPE1r */
   9553         soc_block_list[5],
   9554         soc_genreg,
   9555         1,
   9556         0,
   9557         0x3b060000,
   9558         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9559         0,
   9560         2,
   9561         soc_VLAN_MEMORY_DBGCTRL_1r_fields,
   9562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9564         -1,
   9565         -1,
   9566         3,
   9567     },
   9568 #endif /* chips */
   9569 
   9570 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9571     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_PIPE2r */
   9572         soc_block_list[5],
   9573         soc_genreg,
   9574         1,
   9575         0,
   9576         0x3b060000,
   9577         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9578         0,
   9579         2,
   9580         soc_VLAN_MEMORY_DBGCTRL_1r_fields,
   9581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9582         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9583         -1,
   9584         -1,
   9585         3,
   9586     },
   9587 #endif /* chips */
   9588 
   9589 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   9590     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_PIPE3r */
   9591         soc_block_list[5],
   9592         soc_genreg,
   9593         1,
   9594         0,
   9595         0x3b060000,
   9596         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9597         0,
   9598         2,
   9599         soc_VLAN_MEMORY_DBGCTRL_1r_fields,
   9600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9601         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9602         -1,
   9603         -1,
   9604         3,
   9605     },
   9606 #endif /* chips */
   9607 
   9608 #if defined(BCM_56970_A0)
   9609     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_PIPE0_BCM56970_A0r */
   9610         soc_block_list[5],
   9611         soc_genreg,
   9612         1,
   9613         0,
   9614         0x5f070000,
   9615         0,
   9616         0,
   9617         3,
   9618         soc_VLAN_MEMORY_DBGCTRL_1_BCM56970_A0r_fields,
   9619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9620         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9621         -1,
   9622         -1,
   9623         3,
   9624     },
   9625 #endif /* chips */
   9626 
   9627 #if defined(BCM_56970_A0)
   9628     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_PIPE1_BCM56970_A0r */
   9629         soc_block_list[5],
   9630         soc_genreg,
   9631         1,
   9632         0,
   9633         0x5f070000,
   9634         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9635         0,
   9636         3,
   9637         soc_VLAN_MEMORY_DBGCTRL_1_BCM56970_A0r_fields,
   9638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9639         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9640         -1,
   9641         -1,
   9642         3,
   9643     },
   9644 #endif /* chips */
   9645 
   9646 #if defined(BCM_56970_A0)
   9647     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_PIPE2_BCM56970_A0r */
   9648         soc_block_list[5],
   9649         soc_genreg,
   9650         1,
   9651         0,
   9652         0x5f070000,
   9653         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9654         0,
   9655         3,
   9656         soc_VLAN_MEMORY_DBGCTRL_1_BCM56970_A0r_fields,
   9657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9658         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9659         -1,
   9660         -1,
   9661         3,
   9662     },
   9663 #endif /* chips */
   9664 
   9665 #if defined(BCM_56970_A0)
   9666     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_1_PIPE3_BCM56970_A0r */
   9667         soc_block_list[5],
   9668         soc_genreg,
   9669         1,
   9670         0,
   9671         0x5f070000,
   9672         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9673         0,
   9674         3,
   9675         soc_VLAN_MEMORY_DBGCTRL_1_BCM56970_A0r_fields,
   9676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9677         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9678         -1,
   9679         -1,
   9680         3,
   9681     },
   9682 #endif /* chips */
   9683 
   9684 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   9685     defined(BCM_56450_B1)
   9686     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_BCM56450_A0r */
   9687         soc_block_list[5],
   9688         soc_genreg,
   9689         1,
   9690         0,
   9691         0x16010000,
   9692         0,
   9693         0,
   9694         6,
   9695         soc_VLAN_MEMORY_DBGCTRL_BCM56450_A0r_fields,
   9696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9697         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9698         -1,
   9699         -1,
   9700     },
   9701 #endif /* chips */
   9702 
   9703 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   9704     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9705     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_BCM56560_A0r */
   9706         soc_block_list[5],
   9707         soc_genreg,
   9708         1,
   9709         0,
   9710         0x17050000,
   9711         0,
   9712         0,
   9713         4,
   9714         soc_VLAN_MEMORY_DBGCTRL_BCM56560_A0r_fields,
   9715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9716         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9717         -1,
   9718         -1,
   9719     },
   9720 #endif /* chips */
   9721 
   9722 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   9723     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_BCM56640_A0r */
   9724         soc_block_list[5],
   9725         soc_genreg,
   9726         1,
   9727         0,
   9728         0x16010000,
   9729         0,
   9730         0,
   9731         6,
   9732         soc_VLAN_MEMORY_DBGCTRL_BCM56640_A0r_fields,
   9733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9734         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9735         -1,
   9736         -1,
   9737     },
   9738 #endif /* chips */
   9739 
   9740 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   9741     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   9742     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_BCM56840_A0r */
   9743         soc_block_list[5],
   9744         soc_genreg,
   9745         1,
   9746         0,
   9747         0x5080d00,
   9748         0,
   9749         0,
   9750         6,
   9751         soc_VLAN_MEMORY_DBGCTRL_BCM56840_A0r_fields,
   9752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9754         -1,
   9755         -1,
   9756     },
   9757 #endif /* chips */
   9758 
   9759 #if defined(BCM_56850_A0)
   9760     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_BCM56850_A0r */
   9761         soc_block_list[5],
   9762         soc_genreg,
   9763         1,
   9764         0,
   9765         0x17030000,
   9766         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9767         0,
   9768         10,
   9769         soc_VLAN_MEMORY_DBGCTRL_BCM56850_A0r_fields,
   9770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9772         -1,
   9773         -1,
   9774     },
   9775 #endif /* chips */
   9776 
   9777 #if defined(BCM_56860_A0)
   9778     { /* SOC_REG_INT_VLAN_MEMORY_DBGCTRL_BCM56860_A0r */
   9779         soc_block_list[5],
   9780         soc_genreg,
   9781         1,
   9782         0,
   9783         0x17050000,
   9784         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9785         0,
   9786         4,
   9787         soc_VLAN_MEMORY_DBGCTRL_BCM56860_A0r_fields,
   9788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9790         -1,
   9791         -1,
   9792     },
   9793 #endif /* chips */
   9794 
   9795 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9796     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9797     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9798     { /* SOC_REG_INT_VLAN_MPLS_PARITY_CONTROLr */
   9799         soc_block_list[5],
   9800         soc_genreg,
   9801         1,
   9802         0,
   9803         0x508016c,
   9804         0,
   9805         0,
   9806         1,
   9807         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
   9808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9809         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9810         -1,
   9811         -1,
   9812     },
   9813 #endif /* chips */
   9814 
   9815 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   9816     defined(BCM_56270_A0)
   9817     { /* SOC_REG_INT_VLAN_MPLS_PARITY_CONTROL_BCM56260_A0r */
   9818         soc_block_list[5],
   9819         soc_genreg,
   9820         1,
   9821         0,
   9822         0x16011300,
   9823         0,
   9824         0,
   9825         1,
   9826         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
   9827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9828         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9829         -1,
   9830         -1,
   9831     },
   9832 #endif /* chips */
   9833 
   9834 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   9835     defined(BCM_56450_B1)
   9836     { /* SOC_REG_INT_VLAN_MPLS_PARITY_CONTROL_BCM56450_A0r */
   9837         soc_block_list[5],
   9838         soc_genreg,
   9839         1,
   9840         0,
   9841         0x16011200,
   9842         0,
   9843         0,
   9844         1,
   9845         soc_FT_CNTR_SER_CONTROLr_fields,
   9846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9847         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9848         -1,
   9849         -1,
   9850     },
   9851 #endif /* chips */
   9852 
   9853 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   9854     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9855     { /* SOC_REG_INT_VLAN_MPLS_PARITY_CONTROL_BCM56560_A0r */
   9856         soc_block_list[5],
   9857         soc_genreg,
   9858         1,
   9859         0,
   9860         0x63090000,
   9861         0,
   9862         0,
   9863         1,
   9864         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
   9865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9866         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9867         -1,
   9868         -1,
   9869     },
   9870 #endif /* chips */
   9871 
   9872 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   9873     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   9874     { /* SOC_REG_INT_VLAN_MPLS_PARITY_CONTROL_BCM56840_A0r */
   9875         soc_block_list[5],
   9876         soc_genreg,
   9877         1,
   9878         0,
   9879         0x5080d12,
   9880         0,
   9881         0,
   9882         1,
   9883         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
   9884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9885         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9886         -1,
   9887         -1,
   9888     },
   9889 #endif /* chips */
   9890 
   9891 #if defined(BCM_56850_A0)
   9892     { /* SOC_REG_INT_VLAN_MPLS_PARITY_CONTROL_BCM56850_A0r */
   9893         soc_block_list[5],
   9894         soc_genreg,
   9895         1,
   9896         0,
   9897         0x530a0000,
   9898         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9899         0,
   9900         1,
   9901         soc_FT_CNTR_SER_CONTROLr_fields,
   9902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9904         -1,
   9905         -1,
   9906     },
   9907 #endif /* chips */
   9908 
   9909 #if defined(BCM_56860_A0)
   9910     { /* SOC_REG_INT_VLAN_MPLS_PARITY_CONTROL_BCM56860_A0r */
   9911         soc_block_list[5],
   9912         soc_genreg,
   9913         1,
   9914         0,
   9915         0x63090000,
   9916         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   9917         0,
   9918         1,
   9919         soc_FT_CNTR_SER_CONTROLr_fields,
   9920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9921         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9922         -1,
   9923         -1,
   9924     },
   9925 #endif /* chips */
   9926 
   9927 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9928     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9929     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9930     { /* SOC_REG_INT_VLAN_MPLS_PARITY_STATUS_INTRr */
   9931         soc_block_list[5],
   9932         soc_genreg,
   9933         1,
   9934         0,
   9935         0x508016d,
   9936         0,
   9937         0,
   9938         3,
   9939         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
   9940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9941         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   9942         -1,
   9943         -1,
   9944     },
   9945 #endif /* chips */
   9946 
   9947 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   9948     defined(BCM_56450_B1)
   9949     { /* SOC_REG_INT_VLAN_MPLS_PARITY_STATUS_INTR_BCM56450_A0r */
   9950         soc_block_list[5],
   9951         soc_genreg,
   9952         1,
   9953         0,
   9954         0x16011300,
   9955         0,
   9956         0,
   9957         3,
   9958         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
   9959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9960         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9961         -1,
   9962         -1,
   9963     },
   9964 #endif /* chips */
   9965 
   9966 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
   9967     defined(BCM_56840_A0) || defined(BCM_56840_B0)
   9968     { /* SOC_REG_INT_VLAN_MPLS_PARITY_STATUS_INTR_BCM56840_A0r */
   9969         soc_block_list[5],
   9970         soc_genreg,
   9971         1,
   9972         0,
   9973         0x5080d13,
   9974         0,
   9975         0,
   9976         3,
   9977         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
   9978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9979         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   9980         -1,
   9981         -1,
   9982     },
   9983 #endif /* chips */
   9984 
   9985 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   9986     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   9987     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   9988     { /* SOC_REG_INT_VLAN_MPLS_PARITY_STATUS_NACKr */
   9989         soc_block_list[5],
   9990         soc_genreg,
   9991         1,
   9992         0,
   9993         0x508016e,
   9994         0,
   9995         0,
   9996         3,
   9997         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
   9998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9999         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10000         -1,
  10001         -1,
  10002     },
  10003 #endif /* chips */
  10004 
  10005 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10006     defined(BCM_56450_B1)
  10007     { /* SOC_REG_INT_VLAN_MPLS_PARITY_STATUS_NACK_BCM56450_A0r */
  10008         soc_block_list[5],
  10009         soc_genreg,
  10010         1,
  10011         0,
  10012         0x16011400,
  10013         0,
  10014         0,
  10015         3,
  10016         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
  10017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10018         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10019         -1,
  10020         -1,
  10021     },
  10022 #endif /* chips */
  10023 
  10024 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  10025     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  10026     { /* SOC_REG_INT_VLAN_MPLS_PARITY_STATUS_NACK_BCM56840_A0r */
  10027         soc_block_list[5],
  10028         soc_genreg,
  10029         1,
  10030         0,
  10031         0x5080d14,
  10032         0,
  10033         0,
  10034         3,
  10035         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
  10036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10037         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10038         -1,
  10039         -1,
  10040     },
  10041 #endif /* chips */
  10042 
  10043 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10044     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10045     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10046     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_COUNT_PARITY_CONTROLr */
  10047         soc_block_list[5],
  10048         soc_genreg,
  10049         1,
  10050         0,
  10051         0x7080196,
  10052         0,
  10053         0,
  10054         1,
  10055         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  10056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10057         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10058         -1,
  10059         -1,
  10060     },
  10061 #endif /* chips */
  10062 
  10063 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10064     defined(BCM_56270_A0)
  10065     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_COUNT_PARITY_CONTROL_BCM56260_A0r */
  10066         soc_block_list[5],
  10067         soc_genreg,
  10068         1,
  10069         0,
  10070         0x1a011d00,
  10071         0,
  10072         0,
  10073         1,
  10074         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  10075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10076         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10077         -1,
  10078         -1,
  10079     },
  10080 #endif /* chips */
  10081 
  10082 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10083     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_COUNT_PARITY_CONTROL_BCM56440_A0r */
  10084         soc_block_list[5],
  10085         soc_genreg,
  10086         1,
  10087         0,
  10088         0x6080319,
  10089         0,
  10090         0,
  10091         1,
  10092         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  10093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10094         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10095         -1,
  10096         -1,
  10097     },
  10098 #endif /* chips */
  10099 
  10100 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10101     defined(BCM_56450_B1)
  10102     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_COUNT_PARITY_CONTROL_BCM56450_A0r */
  10103         soc_block_list[5],
  10104         soc_genreg,
  10105         1,
  10106         0,
  10107         0x1a011a00,
  10108         0,
  10109         0,
  10110         1,
  10111         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  10112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10113         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10114         -1,
  10115         -1,
  10116     },
  10117 #endif /* chips */
  10118 
  10119 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10120     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10121     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10122     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_INTRr */
  10123         soc_block_list[5],
  10124         soc_genreg,
  10125         1,
  10126         0,
  10127         0x7080197,
  10128         0,
  10129         0,
  10130         3,
  10131         soc_EGR_MASK_PARITY_STATUSr_fields,
  10132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10133         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10134         -1,
  10135         -1,
  10136     },
  10137 #endif /* chips */
  10138 
  10139 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10140     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_INTR_BCM56440_A0r */
  10141         soc_block_list[5],
  10142         soc_genreg,
  10143         1,
  10144         0,
  10145         0x608031a,
  10146         0,
  10147         0,
  10148         3,
  10149         soc_EGR_MASK_PARITY_STATUSr_fields,
  10150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10151         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10152         -1,
  10153         -1,
  10154     },
  10155 #endif /* chips */
  10156 
  10157 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10158     defined(BCM_56450_B1)
  10159     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_INTR_BCM56450_A0r */
  10160         soc_block_list[5],
  10161         soc_genreg,
  10162         1,
  10163         0,
  10164         0x1a011b00,
  10165         0,
  10166         0,
  10167         3,
  10168         soc_DSCP_TABLE_PARITY_STATUS_INTRr_fields,
  10169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10170         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10171         -1,
  10172         -1,
  10173     },
  10174 #endif /* chips */
  10175 
  10176 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10177     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10178     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10179     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_NACKr */
  10180         soc_block_list[5],
  10181         soc_genreg,
  10182         1,
  10183         0,
  10184         0x7080198,
  10185         0,
  10186         0,
  10187         3,
  10188         soc_EGR_MASK_PARITY_STATUSr_fields,
  10189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10190         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10191         -1,
  10192         -1,
  10193     },
  10194 #endif /* chips */
  10195 
  10196 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10197     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_NACK_BCM56440_A0r */
  10198         soc_block_list[5],
  10199         soc_genreg,
  10200         1,
  10201         0,
  10202         0x608031b,
  10203         0,
  10204         0,
  10205         3,
  10206         soc_EGR_MASK_PARITY_STATUSr_fields,
  10207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10208         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10209         -1,
  10210         -1,
  10211     },
  10212 #endif /* chips */
  10213 
  10214 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10215     defined(BCM_56450_B1)
  10216     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_NACK_BCM56450_A0r */
  10217         soc_block_list[5],
  10218         soc_genreg,
  10219         1,
  10220         0,
  10221         0x1a011c00,
  10222         0,
  10223         0,
  10224         3,
  10225         soc_DSCP_TABLE_PARITY_STATUS_INTRr_fields,
  10226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10227         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10228         -1,
  10229         -1,
  10230     },
  10231 #endif /* chips */
  10232 
  10233 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  10234     defined(BCM_56270_A0)
  10235     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_LIMIT_ECC_CONTROLr */
  10236         soc_block_list[5],
  10237         soc_genreg,
  10238         1,
  10239         0,
  10240         0x1a012000,
  10241         0,
  10242         0,
  10243         2,
  10244         soc_ING_DVP_TABLE_ECCP_CONTROLr_fields,
  10245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10246         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10247         -1,
  10248         -1,
  10249     },
  10250 #endif /* chips */
  10251 
  10252 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10253     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10254     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10255     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_LIMIT_PARITY_CONTROLr */
  10256         soc_block_list[5],
  10257         soc_genreg,
  10258         1,
  10259         0,
  10260         0x7080199,
  10261         0,
  10262         0,
  10263         1,
  10264         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  10265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10266         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10267         -1,
  10268         -1,
  10269     },
  10270 #endif /* chips */
  10271 
  10272 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10273     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_LIMIT_PARITY_CONTROL_BCM56440_A0r */
  10274         soc_block_list[5],
  10275         soc_genreg,
  10276         1,
  10277         0,
  10278         0x608031c,
  10279         0,
  10280         0,
  10281         1,
  10282         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  10283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10284         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10285         -1,
  10286         -1,
  10287     },
  10288 #endif /* chips */
  10289 
  10290 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10291     defined(BCM_56450_B1)
  10292     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_LIMIT_PARITY_CONTROL_BCM56450_A0r */
  10293         soc_block_list[5],
  10294         soc_genreg,
  10295         1,
  10296         0,
  10297         0x1a011d00,
  10298         0,
  10299         0,
  10300         1,
  10301         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  10302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10303         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10304         -1,
  10305         -1,
  10306     },
  10307 #endif /* chips */
  10308 
  10309 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10310     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10311     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10312     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_INTRr */
  10313         soc_block_list[5],
  10314         soc_genreg,
  10315         1,
  10316         0,
  10317         0x708019a,
  10318         0,
  10319         0,
  10320         3,
  10321         soc_EGR_MASK_PARITY_STATUSr_fields,
  10322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10323         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10324         -1,
  10325         -1,
  10326     },
  10327 #endif /* chips */
  10328 
  10329 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10330     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_INTR_BCM56440_A0r */
  10331         soc_block_list[5],
  10332         soc_genreg,
  10333         1,
  10334         0,
  10335         0x608031d,
  10336         0,
  10337         0,
  10338         3,
  10339         soc_EGR_MASK_PARITY_STATUSr_fields,
  10340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10341         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10342         -1,
  10343         -1,
  10344     },
  10345 #endif /* chips */
  10346 
  10347 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10348     defined(BCM_56450_B1)
  10349     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_INTR_BCM56450_A0r */
  10350         soc_block_list[5],
  10351         soc_genreg,
  10352         1,
  10353         0,
  10354         0x1a011e00,
  10355         0,
  10356         0,
  10357         3,
  10358         soc_DSCP_TABLE_PARITY_STATUS_INTRr_fields,
  10359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10360         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10361         -1,
  10362         -1,
  10363     },
  10364 #endif /* chips */
  10365 
  10366 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10367     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10368     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10369     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_NACKr */
  10370         soc_block_list[5],
  10371         soc_genreg,
  10372         1,
  10373         0,
  10374         0x708019b,
  10375         0,
  10376         0,
  10377         3,
  10378         soc_EGR_MASK_PARITY_STATUSr_fields,
  10379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10380         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10381         -1,
  10382         -1,
  10383     },
  10384 #endif /* chips */
  10385 
  10386 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  10387     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_NACK_BCM56440_A0r */
  10388         soc_block_list[5],
  10389         soc_genreg,
  10390         1,
  10391         0,
  10392         0x608031e,
  10393         0,
  10394         0,
  10395         3,
  10396         soc_EGR_MASK_PARITY_STATUSr_fields,
  10397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10398         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10399         -1,
  10400         -1,
  10401     },
  10402 #endif /* chips */
  10403 
  10404 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10405     defined(BCM_56450_B1)
  10406     { /* SOC_REG_INT_VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_NACK_BCM56450_A0r */
  10407         soc_block_list[5],
  10408         soc_genreg,
  10409         1,
  10410         0,
  10411         0x1a011f00,
  10412         0,
  10413         0,
  10414         3,
  10415         soc_DSCP_TABLE_PARITY_STATUS_INTRr_fields,
  10416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10417         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  10418         -1,
  10419         -1,
  10420     },
  10421 #endif /* chips */
  10422 
  10423 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  10424     defined(BCM_56820_A0)
  10425     { /* SOC_REG_INT_VLAN_PARITY_CONTROLr */
  10426         soc_block_list[5],
  10427         soc_genreg,
  10428         1,
  10429         0,
  10430         0x5080c02,
  10431         0,
  10432         0,
  10433         2,
  10434         soc_L2_ENTRY_PARITY_CONTROLr_fields,
  10435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10436         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10437         -1,
  10438         -1,
  10439     },
  10440 #endif /* chips */
  10441 
  10442 #if defined(BCM_53400_A0)
  10443     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM53400_A0r */
  10444         soc_block_list[5],
  10445         soc_genreg,
  10446         1,
  10447         0,
  10448         0x12010200,
  10449         0,
  10450         0,
  10451         1,
  10452         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  10453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10454         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10455         -1,
  10456         -1,
  10457     },
  10458 #endif /* chips */
  10459 
  10460 #if defined(BCM_53570_A0)
  10461     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM53570_A0r */
  10462         soc_block_list[5],
  10463         soc_genreg,
  10464         1,
  10465         0,
  10466         0x12010a00,
  10467         0,
  10468         0,
  10469         1,
  10470         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  10471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10472         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10473         -1,
  10474         -1,
  10475     },
  10476 #endif /* chips */
  10477 
  10478 #if defined(BCM_53570_B0)
  10479     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM53570_B0r */
  10480         soc_block_list[5],
  10481         soc_genreg,
  10482         1,
  10483         0,
  10484         0x12010b00,
  10485         0,
  10486         0,
  10487         1,
  10488         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  10489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10490         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10491         -1,
  10492         -1,
  10493     },
  10494 #endif /* chips */
  10495 
  10496 #if defined(BCM_56150_A0)
  10497     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM56150_A0r */
  10498         soc_block_list[5],
  10499         soc_genreg,
  10500         1,
  10501         0,
  10502         0x16010200,
  10503         0,
  10504         0,
  10505         1,
  10506         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  10507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10508         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10509         -1,
  10510         -1,
  10511     },
  10512 #endif /* chips */
  10513 
  10514 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  10515     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM56160_A0r */
  10516         soc_block_list[5],
  10517         soc_genreg,
  10518         1,
  10519         0,
  10520         0x12010300,
  10521         0,
  10522         0,
  10523         1,
  10524         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  10525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10526         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10527         -1,
  10528         -1,
  10529     },
  10530 #endif /* chips */
  10531 
  10532 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  10533     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  10534     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM56224_A0r */
  10535         soc_block_list[5],
  10536         soc_genreg,
  10537         1,
  10538         0,
  10539         0x5080001,
  10540         0,
  10541         0,
  10542         2,
  10543         soc_L2_ENTRY_PARITY_CONTROLr_fields,
  10544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10545         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10546         -1,
  10547         -1,
  10548     },
  10549 #endif /* chips */
  10550 
  10551 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  10552     defined(BCM_56334_B0)
  10553     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM56334_A0r */
  10554         soc_block_list[5],
  10555         soc_genreg,
  10556         1,
  10557         0,
  10558         0x508012f,
  10559         0,
  10560         0,
  10561         1,
  10562         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  10563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10564         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10565         -1,
  10566         -1,
  10567     },
  10568 #endif /* chips */
  10569 
  10570 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10571     defined(BCM_56450_B1)
  10572     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM56450_A0r */
  10573         soc_block_list[5],
  10574         soc_genreg,
  10575         1,
  10576         0,
  10577         0x16010100,
  10578         0,
  10579         0,
  10580         1,
  10581         soc_FT_CNTR_SER_CONTROLr_fields,
  10582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10583         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10584         -1,
  10585         -1,
  10586     },
  10587 #endif /* chips */
  10588 
  10589 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  10590     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10591     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM56560_A0r */
  10592         soc_block_list[5],
  10593         soc_genreg,
  10594         1,
  10595         0,
  10596         0x17070000,
  10597         0,
  10598         0,
  10599         1,
  10600         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  10601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10602         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10603         -1,
  10604         -1,
  10605     },
  10606 #endif /* chips */
  10607 
  10608 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  10609     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  10610     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM56624_A0r */
  10611         soc_block_list[5],
  10612         soc_genreg,
  10613         1,
  10614         0,
  10615         0x508011c,
  10616         0,
  10617         0,
  10618         1,
  10619         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  10620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10621         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10622         -1,
  10623         -1,
  10624     },
  10625 #endif /* chips */
  10626 
  10627 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10628     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10629     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10630     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM56634_A0r */
  10631         soc_block_list[5],
  10632         soc_genreg,
  10633         1,
  10634         0,
  10635         0x6080153,
  10636         0,
  10637         0,
  10638         1,
  10639         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  10640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10641         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10642         -1,
  10643         -1,
  10644     },
  10645 #endif /* chips */
  10646 
  10647 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  10648     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  10649     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM56840_A0r */
  10650         soc_block_list[5],
  10651         soc_genreg,
  10652         1,
  10653         0,
  10654         0x5080d01,
  10655         0,
  10656         0,
  10657         1,
  10658         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  10659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10660         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10661         -1,
  10662         -1,
  10663     },
  10664 #endif /* chips */
  10665 
  10666 #if defined(BCM_56850_A0)
  10667     { /* SOC_REG_INT_VLAN_PARITY_CONTROL_BCM56850_A0r */
  10668         soc_block_list[5],
  10669         soc_genreg,
  10670         1,
  10671         0,
  10672         0x17040000,
  10673         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  10674         0,
  10675         1,
  10676         soc_FT_CNTR_SER_CONTROLr_fields,
  10677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10678         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10679         -1,
  10680         -1,
  10681     },
  10682 #endif /* chips */
  10683 
  10684 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  10685     defined(BCM_56820_A0)
  10686     { /* SOC_REG_INT_VLAN_PARITY_STATUSr */
  10687         soc_block_list[5],
  10688         soc_genreg,
  10689         1,
  10690         0,
  10691         0x5080c03,
  10692         SOC_REG_FLAG_RO,
  10693         0,
  10694         2,
  10695         soc_VLAN_PARITY_STATUSr_fields,
  10696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10697         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  10698         -1,
  10699         -1,
  10700     },
  10701 #endif /* chips */
  10702 
  10703 #if defined(BCM_53400_A0)
  10704     { /* SOC_REG_INT_VLAN_PARITY_STATUS_BCM53400_A0r */
  10705         soc_block_list[5],
  10706         soc_genreg,
  10707         1,
  10708         0,
  10709         0x12010300,
  10710         0,
  10711         0,
  10712         3,
  10713         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
  10714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10715         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10716         -1,
  10717         -1,
  10718     },
  10719 #endif /* chips */
  10720 
  10721 #if defined(BCM_53570_A0)
  10722     { /* SOC_REG_INT_VLAN_PARITY_STATUS_BCM53570_A0r */
  10723         soc_block_list[5],
  10724         soc_genreg,
  10725         1,
  10726         0,
  10727         0x12010b00,
  10728         0,
  10729         0,
  10730         3,
  10731         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
  10732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10733         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10734         -1,
  10735         -1,
  10736     },
  10737 #endif /* chips */
  10738 
  10739 #if defined(BCM_53570_B0)
  10740     { /* SOC_REG_INT_VLAN_PARITY_STATUS_BCM53570_B0r */
  10741         soc_block_list[5],
  10742         soc_genreg,
  10743         1,
  10744         0,
  10745         0x12010c00,
  10746         0,
  10747         0,
  10748         3,
  10749         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
  10750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10751         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10752         -1,
  10753         -1,
  10754     },
  10755 #endif /* chips */
  10756 
  10757 #if defined(BCM_56150_A0)
  10758     { /* SOC_REG_INT_VLAN_PARITY_STATUS_BCM56150_A0r */
  10759         soc_block_list[5],
  10760         soc_genreg,
  10761         1,
  10762         0,
  10763         0x16010300,
  10764         0,
  10765         0,
  10766         3,
  10767         soc_AXP_WTX_DSCP_MAP_PAR_STATUS_INTRr_fields,
  10768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10769         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10770         -1,
  10771         -1,
  10772     },
  10773 #endif /* chips */
  10774 
  10775 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  10776     { /* SOC_REG_INT_VLAN_PARITY_STATUS_BCM56160_A0r */
  10777         soc_block_list[5],
  10778         soc_genreg,
  10779         1,
  10780         0,
  10781         0x12010400,
  10782         0,
  10783         0,
  10784         3,
  10785         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUSr_fields,
  10786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10787         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10788         -1,
  10789         -1,
  10790     },
  10791 #endif /* chips */
  10792 
  10793 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  10794     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  10795     { /* SOC_REG_INT_VLAN_PARITY_STATUS_BCM56224_A0r */
  10796         soc_block_list[5],
  10797         soc_genreg,
  10798         1,
  10799         0,
  10800         0x5080002,
  10801         SOC_REG_FLAG_RO,
  10802         0,
  10803         2,
  10804         soc_ING_L3_NEXT_HOP_PARITY_STATUSr_fields,
  10805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10806         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  10807         -1,
  10808         -1,
  10809     },
  10810 #endif /* chips */
  10811 
  10812 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  10813     defined(BCM_56334_B0)
  10814     { /* SOC_REG_INT_VLAN_PARITY_STATUS_BCM56334_A0r */
  10815         soc_block_list[5],
  10816         soc_genreg,
  10817         1,
  10818         0,
  10819         0x5080130,
  10820         0,
  10821         0,
  10822         3,
  10823         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  10824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10825         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10826         -1,
  10827         -1,
  10828     },
  10829 #endif /* chips */
  10830 
  10831 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  10832     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  10833     { /* SOC_REG_INT_VLAN_PARITY_STATUS_BCM56624_A0r */
  10834         soc_block_list[5],
  10835         soc_genreg,
  10836         1,
  10837         0,
  10838         0x508011d,
  10839         0,
  10840         0,
  10841         3,
  10842         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  10843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10844         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10845         -1,
  10846         -1,
  10847     },
  10848 #endif /* chips */
  10849 
  10850 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10851     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10852     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10853     { /* SOC_REG_INT_VLAN_PARITY_STATUS_INTRr */
  10854         soc_block_list[5],
  10855         soc_genreg,
  10856         1,
  10857         0,
  10858         0x6080154,
  10859         0,
  10860         0,
  10861         3,
  10862         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  10863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10864         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10865         -1,
  10866         -1,
  10867     },
  10868 #endif /* chips */
  10869 
  10870 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10871     defined(BCM_56450_B1)
  10872     { /* SOC_REG_INT_VLAN_PARITY_STATUS_INTR_BCM56450_A0r */
  10873         soc_block_list[5],
  10874         soc_genreg,
  10875         1,
  10876         0,
  10877         0x16010200,
  10878         0,
  10879         0,
  10880         3,
  10881         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
  10882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10883         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10884         -1,
  10885         -1,
  10886     },
  10887 #endif /* chips */
  10888 
  10889 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  10890     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  10891     { /* SOC_REG_INT_VLAN_PARITY_STATUS_INTR_BCM56840_A0r */
  10892         soc_block_list[5],
  10893         soc_genreg,
  10894         1,
  10895         0,
  10896         0x5080d02,
  10897         0,
  10898         0,
  10899         3,
  10900         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
  10901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10902         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10903         -1,
  10904         -1,
  10905     },
  10906 #endif /* chips */
  10907 
  10908 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10909     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10910     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10911     { /* SOC_REG_INT_VLAN_PARITY_STATUS_NACKr */
  10912         soc_block_list[5],
  10913         soc_genreg,
  10914         1,
  10915         0,
  10916         0x6080155,
  10917         0,
  10918         0,
  10919         3,
  10920         soc_EGR_L3_INTF_PARITY_STATUS_BCM56624_A0r_fields,
  10921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10922         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  10923         -1,
  10924         -1,
  10925     },
  10926 #endif /* chips */
  10927 
  10928 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10929     defined(BCM_56450_B1)
  10930     { /* SOC_REG_INT_VLAN_PARITY_STATUS_NACK_BCM56450_A0r */
  10931         soc_block_list[5],
  10932         soc_genreg,
  10933         1,
  10934         0,
  10935         0x16010300,
  10936         0,
  10937         0,
  10938         3,
  10939         soc_EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr_fields,
  10940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10941         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10942         -1,
  10943         -1,
  10944     },
  10945 #endif /* chips */
  10946 
  10947 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  10948     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  10949     { /* SOC_REG_INT_VLAN_PARITY_STATUS_NACK_BCM56840_A0r */
  10950         soc_block_list[5],
  10951         soc_genreg,
  10952         1,
  10953         0,
  10954         0x5080d03,
  10955         0,
  10956         0,
  10957         3,
  10958         soc_EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr_fields,
  10959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10960         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10961         -1,
  10962         -1,
  10963     },
  10964 #endif /* chips */
  10965 
  10966 #if defined(BCM_88732_A0)
  10967     { /* SOC_REG_INT_VLAN_PROFILE_2_ECC_STATUSr */
  10968         soc_block_list[5],
  10969         soc_genreg,
  10970         1,
  10971         0,
  10972         0x80801c9,
  10973         0,
  10974         0,
  10975         1,
  10976         soc_EGR_EDB_CM_ECC_STATUSr_fields,
  10977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10978         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  10979         -1,
  10980         -1,
  10981     },
  10982 #endif /* chips */
  10983 
  10984 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  10985     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  10986     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  10987     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_CONTROLr */
  10988         soc_block_list[5],
  10989         soc_genreg,
  10990         1,
  10991         0,
  10992         0xe080270,
  10993         0,
  10994         0,
  10995         1,
  10996         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  10997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10998         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10999         -1,
  11000         -1,
  11001     },
  11002 #endif /* chips */
  11003 
  11004 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  11005     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  11006     defined(BCM_56160_A0)
  11007     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_CONTROL_BCM53400_A0r */
  11008         soc_block_list[5],
  11009         soc_genreg,
  11010         1,
  11011         0,
  11012         0x42012400,
  11013         0,
  11014         0,
  11015         1,
  11016         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  11017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11018         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  11019         -1,
  11020         -1,
  11021     },
  11022 #endif /* chips */
  11023 
  11024 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  11025     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_CONTROL_BCM53570_A0r */
  11026         soc_block_list[5],
  11027         soc_genreg,
  11028         1,
  11029         0,
  11030         0x42013000,
  11031         0,
  11032         0,
  11033         1,
  11034         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  11035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11036         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  11037         -1,
  11038         -1,
  11039     },
  11040 #endif /* chips */
  11041 
  11042 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  11043     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  11044     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_CONTROL_BCM56160_A0r */
  11045         soc_block_list[5],
  11046         soc_genreg,
  11047         1,
  11048         0,
  11049         0x42012800,
  11050         0,
  11051         0,
  11052         1,
  11053         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  11054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11055         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  11056         -1,
  11057         -1,
  11058     },
  11059 #endif /* chips */
  11060 
  11061 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  11062     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_CONTROL_BCM56260_A0r */
  11063         soc_block_list[5],
  11064         soc_genreg,
  11065         1,
  11066         0,
  11067         0x3e014000,
  11068         0,
  11069         0,
  11070         1,
  11071         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  11072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11073         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11074         -1,
  11075         -1,
  11076     },
  11077 #endif /* chips */
  11078 
  11079 #if defined(BCM_56270_A0)
  11080     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_CONTROL_BCM56270_A0r */
  11081         soc_block_list[5],
  11082         soc_genreg,
  11083         1,
  11084         0,
  11085         0x3e013200,
  11086         0,
  11087         0,
  11088         1,
  11089         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  11090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11091         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11092         -1,
  11093         -1,
  11094     },
  11095 #endif /* chips */
  11096 
  11097 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11098     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_CONTROL_BCM56440_A0r */
  11099         soc_block_list[5],
  11100         soc_genreg,
  11101         1,
  11102         0,
  11103         0xf080d3f,
  11104         0,
  11105         0,
  11106         1,
  11107         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  11108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11110         -1,
  11111         -1,
  11112     },
  11113 #endif /* chips */
  11114 
  11115 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11116     defined(BCM_56450_B1)
  11117     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_CONTROL_BCM56450_A0r */
  11118         soc_block_list[5],
  11119         soc_genreg,
  11120         1,
  11121         0,
  11122         0x3e013f00,
  11123         0,
  11124         0,
  11125         1,
  11126         soc_FT_CNTR_SER_CONTROLr_fields,
  11127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11128         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11129         -1,
  11130         -1,
  11131     },
  11132 #endif /* chips */
  11133 
  11134 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11135     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_CONTROL_BCM56840_A0r */
  11136         soc_block_list[5],
  11137         soc_genreg,
  11138         1,
  11139         0,
  11140         0xf080d3d,
  11141         0,
  11142         0,
  11143         1,
  11144         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  11145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11146         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11147         -1,
  11148         -1,
  11149     },
  11150 #endif /* chips */
  11151 
  11152 #if defined(BCM_53400_A0)
  11153     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_STATUSr */
  11154         soc_block_list[5],
  11155         soc_genreg,
  11156         1,
  11157         0,
  11158         0x42012500,
  11159         0,
  11160         0,
  11161         3,
  11162         soc_VLAN_PROFILE_2_PARITY_STATUSr_fields,
  11163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11164         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11165         -1,
  11166         -1,
  11167     },
  11168 #endif /* chips */
  11169 
  11170 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  11171     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_STATUS_BCM53570_A0r */
  11172         soc_block_list[5],
  11173         soc_genreg,
  11174         1,
  11175         0,
  11176         0x42013100,
  11177         0,
  11178         0,
  11179         3,
  11180         soc_VLAN_PROFILE_2_PARITY_STATUSr_fields,
  11181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11182         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11183         -1,
  11184         -1,
  11185     },
  11186 #endif /* chips */
  11187 
  11188 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  11189     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_STATUS_BCM56160_A0r */
  11190         soc_block_list[5],
  11191         soc_genreg,
  11192         1,
  11193         0,
  11194         0x42012900,
  11195         0,
  11196         0,
  11197         3,
  11198         soc_VLAN_PROFILE_2_PARITY_STATUSr_fields,
  11199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11200         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11201         -1,
  11202         -1,
  11203     },
  11204 #endif /* chips */
  11205 
  11206 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11207     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11208     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11209     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_STATUS_INTRr */
  11210         soc_block_list[5],
  11211         soc_genreg,
  11212         1,
  11213         0,
  11214         0xe080271,
  11215         0,
  11216         0,
  11217         3,
  11218         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  11219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11220         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  11221         -1,
  11222         -1,
  11223     },
  11224 #endif /* chips */
  11225 
  11226 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11227     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_STATUS_INTR_BCM56440_A0r */
  11228         soc_block_list[5],
  11229         soc_genreg,
  11230         1,
  11231         0,
  11232         0xf080d40,
  11233         0,
  11234         0,
  11235         3,
  11236         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  11237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11238         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11239         -1,
  11240         -1,
  11241     },
  11242 #endif /* chips */
  11243 
  11244 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11245     defined(BCM_56450_B1)
  11246     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_STATUS_INTR_BCM56450_A0r */
  11247         soc_block_list[5],
  11248         soc_genreg,
  11249         1,
  11250         0,
  11251         0x3e014000,
  11252         0,
  11253         0,
  11254         3,
  11255         soc_ING_PHYSICAL_PORT_TABLE_PARITY_STATUS_INTRr_fields,
  11256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11257         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11258         -1,
  11259         -1,
  11260     },
  11261 #endif /* chips */
  11262 
  11263 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11264     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_STATUS_INTR_BCM56840_A0r */
  11265         soc_block_list[5],
  11266         soc_genreg,
  11267         1,
  11268         0,
  11269         0xf080d3e,
  11270         0,
  11271         0,
  11272         3,
  11273         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  11274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11275         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11276         -1,
  11277         -1,
  11278     },
  11279 #endif /* chips */
  11280 
  11281 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11282     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11283     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11284     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_STATUS_NACKr */
  11285         soc_block_list[5],
  11286         soc_genreg,
  11287         1,
  11288         0,
  11289         0xe080272,
  11290         0,
  11291         0,
  11292         3,
  11293         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  11294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11295         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  11296         -1,
  11297         -1,
  11298     },
  11299 #endif /* chips */
  11300 
  11301 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  11302     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_STATUS_NACK_BCM56440_A0r */
  11303         soc_block_list[5],
  11304         soc_genreg,
  11305         1,
  11306         0,
  11307         0xf080d41,
  11308         0,
  11309         0,
  11310         3,
  11311         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  11312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11313         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11314         -1,
  11315         -1,
  11316     },
  11317 #endif /* chips */
  11318 
  11319 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11320     defined(BCM_56450_B1)
  11321     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_STATUS_NACK_BCM56450_A0r */
  11322         soc_block_list[5],
  11323         soc_genreg,
  11324         1,
  11325         0,
  11326         0x3e014100,
  11327         0,
  11328         0,
  11329         3,
  11330         soc_ING_PHYSICAL_PORT_TABLE_PARITY_STATUS_INTRr_fields,
  11331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11332         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11333         -1,
  11334         -1,
  11335     },
  11336 #endif /* chips */
  11337 
  11338 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11339     { /* SOC_REG_INT_VLAN_PROFILE_2_PARITY_STATUS_NACK_BCM56840_A0r */
  11340         soc_block_list[5],
  11341         soc_genreg,
  11342         1,
  11343         0,
  11344         0xf080d3f,
  11345         0,
  11346         0,
  11347         3,
  11348         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  11349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11350         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11351         -1,
  11352         -1,
  11353     },
  11354 #endif /* chips */
  11355 
  11356 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  11357     defined(BCM_56270_A0)
  11358     { /* SOC_REG_INT_VLAN_PROFILE_PARITY_CONTROLr */
  11359         soc_block_list[5],
  11360         soc_genreg,
  11361         1,
  11362         0,
  11363         0x16010600,
  11364         0,
  11365         0,
  11366         1,
  11367         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  11368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11369         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11370         -1,
  11371         -1,
  11372     },
  11373 #endif /* chips */
  11374 
  11375 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  11376     defined(BCM_56870_A0)
  11377     { /* SOC_REG_INT_VLAN_PROFILE_TABr */
  11378         soc_block_list[115],
  11379         soc_genreg,
  11380         1,
  11381         0,
  11382         0x2000300,
  11383         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11384         SOC_REG_FLAG_CCH,
  11385         1,
  11386         soc_VLAN_PROFILE_TABr_fields,
  11387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11388         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11389         -1,
  11390         -1,
  11391         3,
  11392     },
  11393 #endif /* chips */
  11394 
  11395 #if defined(BCM_56800_A0)
  11396     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRLr */
  11397         soc_block_list[5],
  11398         soc_genreg,
  11399         1,
  11400         0,
  11401         0x4080c12,
  11402         0,
  11403         0,
  11404         1,
  11405         soc_CFAPMEMDEBUGr_fields,
  11406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11408         -1,
  11409         -1,
  11410     },
  11411 #endif /* chips */
  11412 
  11413 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  11414     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  11415     defined(BCM_56160_A0)
  11416     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM53400_A0r */
  11417         soc_block_list[5],
  11418         soc_genreg,
  11419         1,
  11420         0,
  11421         0xe010700,
  11422         0,
  11423         0,
  11424         1,
  11425         soc_DSCP_CONTROLr_fields,
  11426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11427         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11428         -1,
  11429         -1,
  11430     },
  11431 #endif /* chips */
  11432 
  11433 #if defined(BCM_56150_A0)
  11434     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56150_A0r */
  11435         soc_block_list[5],
  11436         soc_genreg,
  11437         1,
  11438         0,
  11439         0x12010700,
  11440         0,
  11441         0,
  11442         1,
  11443         soc_INTFO_QCN_SRAM_TMr_fields,
  11444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11445         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11446         -1,
  11447         -1,
  11448     },
  11449 #endif /* chips */
  11450 
  11451 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  11452     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56260_A0r */
  11453         soc_block_list[5],
  11454         soc_genreg,
  11455         1,
  11456         0,
  11457         0x12010500,
  11458         0,
  11459         0,
  11460         1,
  11461         soc_ING_VLAN_TAG_ACTION_PROFILE_DATA_DBGCTRLr_fields,
  11462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11463         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11464         -1,
  11465         -1,
  11466     },
  11467 #endif /* chips */
  11468 
  11469 #if defined(BCM_56270_A0)
  11470     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56270_A0r */
  11471         soc_block_list[5],
  11472         soc_genreg,
  11473         1,
  11474         0,
  11475         0x12010500,
  11476         0,
  11477         0,
  11478         1,
  11479         soc_DSCP_CONTROLr_fields,
  11480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11481         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11482         -1,
  11483         -1,
  11484     },
  11485 #endif /* chips */
  11486 
  11487 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  11488     defined(BCM_56334_B0)
  11489     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56334_A0r */
  11490         soc_block_list[5],
  11491         soc_genreg,
  11492         1,
  11493         0,
  11494         0x4080116,
  11495         0,
  11496         0,
  11497         1,
  11498         soc_CFAPMEMDEBUGr_fields,
  11499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11500         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11501         -1,
  11502         -1,
  11503     },
  11504 #endif /* chips */
  11505 
  11506 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  11507     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  11508     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56560_A0r */
  11509         soc_block_list[5],
  11510         soc_genreg,
  11511         1,
  11512         0,
  11513         0x13060000,
  11514         0,
  11515         0,
  11516         1,
  11517         soc_DSCP_CONTROLr_fields,
  11518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11519         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11520         -1,
  11521         -1,
  11522     },
  11523 #endif /* chips */
  11524 
  11525 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  11526     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  11527     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56624_A0r */
  11528         soc_block_list[5],
  11529         soc_genreg,
  11530         1,
  11531         0,
  11532         0x408010e,
  11533         0,
  11534         0,
  11535         1,
  11536         soc_CFAPMEMDEBUGr_fields,
  11537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11539         -1,
  11540         -1,
  11541     },
  11542 #endif /* chips */
  11543 
  11544 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  11545     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  11546     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  11547     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56634_A0r */
  11548         soc_block_list[5],
  11549         soc_genreg,
  11550         1,
  11551         0,
  11552         0x408013a,
  11553         0,
  11554         0,
  11555         1,
  11556         soc_CFAPMEMDEBUGr_fields,
  11557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11559         -1,
  11560         -1,
  11561     },
  11562 #endif /* chips */
  11563 
  11564 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  11565     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56640_A0r */
  11566         soc_block_list[5],
  11567         soc_genreg,
  11568         1,
  11569         0,
  11570         0x12010600,
  11571         0,
  11572         0,
  11573         2,
  11574         soc_IFP_ING_DVP_2_CONTROL_BCM56640_A0r_fields,
  11575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11577         -1,
  11578         -1,
  11579     },
  11580 #endif /* chips */
  11581 
  11582 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  11583     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56670_A0r */
  11584         soc_block_list[5],
  11585         soc_genreg,
  11586         1,
  11587         0,
  11588         0x13070000,
  11589         0,
  11590         0,
  11591         1,
  11592         soc_DSCP_CONTROLr_fields,
  11593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11594         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11595         -1,
  11596         -1,
  11597     },
  11598 #endif /* chips */
  11599 
  11600 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  11601     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56820_A0r */
  11602         soc_block_list[5],
  11603         soc_genreg,
  11604         1,
  11605         0,
  11606         0x4080c42,
  11607         0,
  11608         0,
  11609         2,
  11610         soc_CFAPMEMDEBUG_BCM56820_A0r_fields,
  11611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11613         -1,
  11614         -1,
  11615     },
  11616 #endif /* chips */
  11617 
  11618 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  11619     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  11620     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56840_A0r */
  11621         soc_block_list[5],
  11622         soc_genreg,
  11623         1,
  11624         0,
  11625         0x4080d07,
  11626         0,
  11627         0,
  11628         2,
  11629         soc_IFP_ING_DVP_2_CONTROLr_fields,
  11630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11631         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11632         -1,
  11633         -1,
  11634     },
  11635 #endif /* chips */
  11636 
  11637 #if defined(BCM_56850_A0)
  11638     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56850_A0r */
  11639         soc_block_list[5],
  11640         soc_genreg,
  11641         1,
  11642         0,
  11643         0x13060000,
  11644         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11645         0,
  11646         2,
  11647         soc_IFP_ING_DVP_2_CONTROL_BCM56640_A0r_fields,
  11648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11649         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11650         -1,
  11651         -1,
  11652     },
  11653 #endif /* chips */
  11654 
  11655 #if defined(BCM_56860_A0)
  11656     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56860_A0r */
  11657         soc_block_list[5],
  11658         soc_genreg,
  11659         1,
  11660         0,
  11661         0x13060000,
  11662         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11663         0,
  11664         1,
  11665         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r_fields,
  11666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11667         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11668         -1,
  11669         -1,
  11670     },
  11671 #endif /* chips */
  11672 
  11673 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11674     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56960_A0r */
  11675         soc_block_list[5],
  11676         soc_genreg,
  11677         1,
  11678         0,
  11679         0x33060000,
  11680         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11681         0,
  11682         2,
  11683         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  11684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11685         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11686         -1,
  11687         -1,
  11688         0,
  11689     },
  11690 #endif /* chips */
  11691 
  11692 #if defined(BCM_56970_A0)
  11693     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_BCM56970_A0r */
  11694         soc_block_list[5],
  11695         soc_genreg,
  11696         1,
  11697         0,
  11698         0x57060000,
  11699         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11700         0,
  11701         2,
  11702         soc_VLAN_PROTOCOL_DATA_DBGCTRLr_fields,
  11703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11704         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11705         -1,
  11706         -1,
  11707         0,
  11708     },
  11709 #endif /* chips */
  11710 
  11711 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11712     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_PIPE0r */
  11713         soc_block_list[5],
  11714         soc_genreg,
  11715         1,
  11716         0,
  11717         0x33060000,
  11718         0,
  11719         0,
  11720         2,
  11721         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  11722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11723         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11724         -1,
  11725         -1,
  11726         0,
  11727     },
  11728 #endif /* chips */
  11729 
  11730 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11731     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_PIPE1r */
  11732         soc_block_list[5],
  11733         soc_genreg,
  11734         1,
  11735         0,
  11736         0x33060000,
  11737         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11738         0,
  11739         2,
  11740         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  11741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11742         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11743         -1,
  11744         -1,
  11745         0,
  11746     },
  11747 #endif /* chips */
  11748 
  11749 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11750     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_PIPE2r */
  11751         soc_block_list[5],
  11752         soc_genreg,
  11753         1,
  11754         0,
  11755         0x33060000,
  11756         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11757         0,
  11758         2,
  11759         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  11760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11762         -1,
  11763         -1,
  11764         0,
  11765     },
  11766 #endif /* chips */
  11767 
  11768 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11769     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_PIPE3r */
  11770         soc_block_list[5],
  11771         soc_genreg,
  11772         1,
  11773         0,
  11774         0x33060000,
  11775         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11776         0,
  11777         2,
  11778         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  11779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11780         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11781         -1,
  11782         -1,
  11783         0,
  11784     },
  11785 #endif /* chips */
  11786 
  11787 #if defined(BCM_56970_A0)
  11788     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_PIPE0_BCM56970_A0r */
  11789         soc_block_list[5],
  11790         soc_genreg,
  11791         1,
  11792         0,
  11793         0x57060000,
  11794         0,
  11795         0,
  11796         2,
  11797         soc_VLAN_PROTOCOL_DATA_DBGCTRLr_fields,
  11798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11799         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11800         -1,
  11801         -1,
  11802         0,
  11803     },
  11804 #endif /* chips */
  11805 
  11806 #if defined(BCM_56970_A0)
  11807     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_PIPE1_BCM56970_A0r */
  11808         soc_block_list[5],
  11809         soc_genreg,
  11810         1,
  11811         0,
  11812         0x57060000,
  11813         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11814         0,
  11815         2,
  11816         soc_VLAN_PROTOCOL_DATA_DBGCTRLr_fields,
  11817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11818         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11819         -1,
  11820         -1,
  11821         0,
  11822     },
  11823 #endif /* chips */
  11824 
  11825 #if defined(BCM_56970_A0)
  11826     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_PIPE2_BCM56970_A0r */
  11827         soc_block_list[5],
  11828         soc_genreg,
  11829         1,
  11830         0,
  11831         0x57060000,
  11832         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11833         0,
  11834         2,
  11835         soc_VLAN_PROTOCOL_DATA_DBGCTRLr_fields,
  11836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11837         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11838         -1,
  11839         -1,
  11840         0,
  11841     },
  11842 #endif /* chips */
  11843 
  11844 #if defined(BCM_56970_A0)
  11845     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_DBGCTRL_PIPE3_BCM56970_A0r */
  11846         soc_block_list[5],
  11847         soc_genreg,
  11848         1,
  11849         0,
  11850         0x57060000,
  11851         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  11852         0,
  11853         2,
  11854         soc_VLAN_PROTOCOL_DATA_DBGCTRLr_fields,
  11855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11856         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11857         -1,
  11858         -1,
  11859         0,
  11860     },
  11861 #endif /* chips */
  11862 
  11863 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  11864     defined(BCM_56334_B0)
  11865     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_PARITY_CONTROLr */
  11866         soc_block_list[5],
  11867         soc_genreg,
  11868         1,
  11869         0,
  11870         0x408011d,
  11871         0,
  11872         0,
  11873         1,
  11874         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  11875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11876         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  11877         -1,
  11878         -1,
  11879     },
  11880 #endif /* chips */
  11881 
  11882 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  11883     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  11884     defined(BCM_56160_A0)
  11885     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_PARITY_CONTROL_BCM53400_A0r */
  11886         soc_block_list[5],
  11887         soc_genreg,
  11888         1,
  11889         0,
  11890         0xe011000,
  11891         0,
  11892         0,
  11893         1,
  11894         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  11895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11896         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  11897         -1,
  11898         -1,
  11899     },
  11900 #endif /* chips */
  11901 
  11902 #if defined(BCM_56150_A0)
  11903     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_PARITY_CONTROL_BCM56150_A0r */
  11904         soc_block_list[5],
  11905         soc_genreg,
  11906         1,
  11907         0,
  11908         0x12010c00,
  11909         0,
  11910         0,
  11911         1,
  11912         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  11913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11914         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  11915         -1,
  11916         -1,
  11917     },
  11918 #endif /* chips */
  11919 
  11920 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  11921     defined(BCM_56334_B0)
  11922     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_PARITY_STATUSr */
  11923         soc_block_list[5],
  11924         soc_genreg,
  11925         1,
  11926         0,
  11927         0x408011e,
  11928         0,
  11929         0,
  11930         3,
  11931         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_STATUSr_fields,
  11932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11933         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  11934         -1,
  11935         -1,
  11936     },
  11937 #endif /* chips */
  11938 
  11939 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  11940     defined(BCM_56160_A0)
  11941     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_PARITY_STATUS_BCM53400_A0r */
  11942         soc_block_list[5],
  11943         soc_genreg,
  11944         1,
  11945         0,
  11946         0xe011100,
  11947         0,
  11948         0,
  11949         3,
  11950         soc_EFP_METER_TABLE_PARITY_STATUSr_fields,
  11951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11952         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  11953         -1,
  11954         -1,
  11955     },
  11956 #endif /* chips */
  11957 
  11958 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  11959     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_PARITY_STATUS_BCM53570_A0r */
  11960         soc_block_list[5],
  11961         soc_genreg,
  11962         1,
  11963         0,
  11964         0xe011100,
  11965         0,
  11966         0,
  11967         3,
  11968         soc_EGR_L3_NEXT_HOP_PARITY_STATUS_BCM53400_A0r_fields,
  11969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11970         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  11971         -1,
  11972         -1,
  11973     },
  11974 #endif /* chips */
  11975 
  11976 #if defined(BCM_56150_A0)
  11977     { /* SOC_REG_INT_VLAN_PROTOCOL_DATA_PARITY_STATUS_BCM56150_A0r */
  11978         soc_block_list[5],
  11979         soc_genreg,
  11980         1,
  11981         0,
  11982         0x12010d00,
  11983         0,
  11984         0,
  11985         3,
  11986         soc_EGR_FP_COUNTER_PARITY_STATUSr_fields,
  11987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11988         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  11989         -1,
  11990         -1,
  11991     },
  11992 #endif /* chips */
  11993 
  11994 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  11995     defined(BCM_56270_A0)
  11996     { /* SOC_REG_INT_VLAN_PROT_ECC_CONTROLr */
  11997         soc_block_list[5],
  11998         soc_genreg,
  11999         1,
  12000         0,
  12001         0x12011c00,
  12002         0,
  12003         0,
  12004         2,
  12005         soc_EGR_MASK_ECC_CONTROLr_fields,
  12006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12007         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12008         -1,
  12009         -1,
  12010     },
  12011 #endif /* chips */
  12012 
  12013 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12014     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12015     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12016     { /* SOC_REG_INT_VLAN_PROT_PARITY_CONTROLr */
  12017         soc_block_list[5],
  12018         soc_genreg,
  12019         1,
  12020         0,
  12021         0x408014c,
  12022         0,
  12023         0,
  12024         1,
  12025         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  12026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12027         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12028         -1,
  12029         -1,
  12030     },
  12031 #endif /* chips */
  12032 
  12033 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12034     defined(BCM_56450_B1)
  12035     { /* SOC_REG_INT_VLAN_PROT_PARITY_CONTROL_BCM56450_A0r */
  12036         soc_block_list[5],
  12037         soc_genreg,
  12038         1,
  12039         0,
  12040         0x12011b00,
  12041         0,
  12042         0,
  12043         1,
  12044         soc_FT_CNTR_SER_CONTROLr_fields,
  12045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12046         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12047         -1,
  12048         -1,
  12049     },
  12050 #endif /* chips */
  12051 
  12052 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  12053     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  12054     { /* SOC_REG_INT_VLAN_PROT_PARITY_CONTROL_BCM56840_A0r */
  12055         soc_block_list[5],
  12056         soc_genreg,
  12057         1,
  12058         0,
  12059         0x4080d1a,
  12060         0,
  12061         0,
  12062         1,
  12063         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  12064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12065         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12066         -1,
  12067         -1,
  12068     },
  12069 #endif /* chips */
  12070 
  12071 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12072     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12073     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12074     { /* SOC_REG_INT_VLAN_PROT_PARITY_STATUS_INTRr */
  12075         soc_block_list[5],
  12076         soc_genreg,
  12077         1,
  12078         0,
  12079         0x408014d,
  12080         0,
  12081         0,
  12082         3,
  12083         soc_EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr_fields,
  12084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12085         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  12086         -1,
  12087         -1,
  12088     },
  12089 #endif /* chips */
  12090 
  12091 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12092     defined(BCM_56450_B1)
  12093     { /* SOC_REG_INT_VLAN_PROT_PARITY_STATUS_INTR_BCM56450_A0r */
  12094         soc_block_list[5],
  12095         soc_genreg,
  12096         1,
  12097         0,
  12098         0x12011c00,
  12099         0,
  12100         0,
  12101         3,
  12102         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  12103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12105         -1,
  12106         -1,
  12107     },
  12108 #endif /* chips */
  12109 
  12110 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  12111     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  12112     { /* SOC_REG_INT_VLAN_PROT_PARITY_STATUS_INTR_BCM56840_A0r */
  12113         soc_block_list[5],
  12114         soc_genreg,
  12115         1,
  12116         0,
  12117         0x4080d1b,
  12118         0,
  12119         0,
  12120         3,
  12121         soc_CPB_PARITY_STATUS_INTRr_fields,
  12122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12124         -1,
  12125         -1,
  12126     },
  12127 #endif /* chips */
  12128 
  12129 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12130     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12131     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12132     { /* SOC_REG_INT_VLAN_PROT_PARITY_STATUS_NACKr */
  12133         soc_block_list[5],
  12134         soc_genreg,
  12135         1,
  12136         0,
  12137         0x408014e,
  12138         0,
  12139         0,
  12140         3,
  12141         soc_EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr_fields,
  12142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12143         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  12144         -1,
  12145         -1,
  12146     },
  12147 #endif /* chips */
  12148 
  12149 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12150     defined(BCM_56450_B1)
  12151     { /* SOC_REG_INT_VLAN_PROT_PARITY_STATUS_NACK_BCM56450_A0r */
  12152         soc_block_list[5],
  12153         soc_genreg,
  12154         1,
  12155         0,
  12156         0x12011d00,
  12157         0,
  12158         0,
  12159         3,
  12160         soc_EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr_fields,
  12161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12162         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12163         -1,
  12164         -1,
  12165     },
  12166 #endif /* chips */
  12167 
  12168 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  12169     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  12170     { /* SOC_REG_INT_VLAN_PROT_PARITY_STATUS_NACK_BCM56840_A0r */
  12171         soc_block_list[5],
  12172         soc_genreg,
  12173         1,
  12174         0,
  12175         0x4080d1c,
  12176         0,
  12177         0,
  12178         3,
  12179         soc_CPB_PARITY_STATUS_INTRr_fields,
  12180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12182         -1,
  12183         -1,
  12184     },
  12185 #endif /* chips */
  12186 
  12187 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  12188     { /* SOC_REG_INT_VLAN_RAM_DBGCTRLr */
  12189         soc_block_list[5],
  12190         soc_genreg,
  12191         1,
  12192         0,
  12193         0x16012200,
  12194         SOC_REG_FLAG_64_BITS,
  12195         0,
  12196         4,
  12197         soc_VLAN_RAM_DBGCTRLr_fields,
  12198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12200         -1,
  12201         -1,
  12202     },
  12203 #endif /* chips */
  12204 
  12205 #if defined(BCM_56270_A0)
  12206     { /* SOC_REG_INT_VLAN_RAM_DBGCTRL_BCM56270_A0r */
  12207         soc_block_list[5],
  12208         soc_genreg,
  12209         1,
  12210         0,
  12211         0x16012200,
  12212         SOC_REG_FLAG_64_BITS,
  12213         0,
  12214         3,
  12215         soc_VLAN_RAM_DBGCTRL_BCM56270_A0r_fields,
  12216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12217         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12218         -1,
  12219         -1,
  12220     },
  12221 #endif /* chips */
  12222 
  12223 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12224     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12225     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12226     { /* SOC_REG_INT_VLAN_RANGE_PARITY_CONTROLr */
  12227         soc_block_list[5],
  12228         soc_genreg,
  12229         1,
  12230         0,
  12231         0x208011c,
  12232         0,
  12233         0,
  12234         1,
  12235         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  12236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12237         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12238         -1,
  12239         -1,
  12240     },
  12241 #endif /* chips */
  12242 
  12243 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12244     defined(BCM_56270_A0)
  12245     { /* SOC_REG_INT_VLAN_RANGE_PARITY_CONTROL_BCM56260_A0r */
  12246         soc_block_list[5],
  12247         soc_genreg,
  12248         1,
  12249         0,
  12250         0xa011600,
  12251         0,
  12252         0,
  12253         1,
  12254         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  12255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12256         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12257         -1,
  12258         -1,
  12259     },
  12260 #endif /* chips */
  12261 
  12262 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12263     defined(BCM_56450_B1)
  12264     { /* SOC_REG_INT_VLAN_RANGE_PARITY_CONTROL_BCM56450_A0r */
  12265         soc_block_list[5],
  12266         soc_genreg,
  12267         1,
  12268         0,
  12269         0xa010c00,
  12270         0,
  12271         0,
  12272         1,
  12273         soc_FT_CNTR_SER_CONTROLr_fields,
  12274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12275         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12276         -1,
  12277         -1,
  12278     },
  12279 #endif /* chips */
  12280 
  12281 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  12282     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  12283     { /* SOC_REG_INT_VLAN_RANGE_PARITY_CONTROL_BCM56840_A0r */
  12284         soc_block_list[5],
  12285         soc_genreg,
  12286         1,
  12287         0,
  12288         0x2080d0c,
  12289         0,
  12290         0,
  12291         1,
  12292         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  12293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12294         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12295         -1,
  12296         -1,
  12297     },
  12298 #endif /* chips */
  12299 
  12300 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12301     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12302     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12303     { /* SOC_REG_INT_VLAN_RANGE_PARITY_STATUS_INTRr */
  12304         soc_block_list[5],
  12305         soc_genreg,
  12306         1,
  12307         0,
  12308         0x208011d,
  12309         0,
  12310         0,
  12311         3,
  12312         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTRr_fields,
  12313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12314         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12315         -1,
  12316         -1,
  12317     },
  12318 #endif /* chips */
  12319 
  12320 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12321     { /* SOC_REG_INT_VLAN_RANGE_PARITY_STATUS_INTR_BCM56440_A0r */
  12322         soc_block_list[5],
  12323         soc_genreg,
  12324         1,
  12325         0,
  12326         0x2080d0d,
  12327         0,
  12328         0,
  12329         3,
  12330         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  12331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12332         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12333         -1,
  12334         -1,
  12335     },
  12336 #endif /* chips */
  12337 
  12338 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12339     defined(BCM_56450_B1)
  12340     { /* SOC_REG_INT_VLAN_RANGE_PARITY_STATUS_INTR_BCM56450_A0r */
  12341         soc_block_list[5],
  12342         soc_genreg,
  12343         1,
  12344         0,
  12345         0xa010d00,
  12346         0,
  12347         0,
  12348         3,
  12349         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  12350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12351         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12352         -1,
  12353         -1,
  12354     },
  12355 #endif /* chips */
  12356 
  12357 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  12358     { /* SOC_REG_INT_VLAN_RANGE_PARITY_STATUS_INTR_BCM56840_A0r */
  12359         soc_block_list[5],
  12360         soc_genreg,
  12361         1,
  12362         0,
  12363         0x2080d0d,
  12364         0,
  12365         0,
  12366         3,
  12367         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  12368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12369         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12370         -1,
  12371         -1,
  12372     },
  12373 #endif /* chips */
  12374 
  12375 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12376     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12377     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12378     { /* SOC_REG_INT_VLAN_RANGE_PARITY_STATUS_NACKr */
  12379         soc_block_list[5],
  12380         soc_genreg,
  12381         1,
  12382         0,
  12383         0x208011e,
  12384         0,
  12385         0,
  12386         3,
  12387         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTRr_fields,
  12388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12389         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12390         -1,
  12391         -1,
  12392     },
  12393 #endif /* chips */
  12394 
  12395 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  12396     { /* SOC_REG_INT_VLAN_RANGE_PARITY_STATUS_NACK_BCM56440_A0r */
  12397         soc_block_list[5],
  12398         soc_genreg,
  12399         1,
  12400         0,
  12401         0x2080d0e,
  12402         0,
  12403         0,
  12404         3,
  12405         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  12406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12408         -1,
  12409         -1,
  12410     },
  12411 #endif /* chips */
  12412 
  12413 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12414     defined(BCM_56450_B1)
  12415     { /* SOC_REG_INT_VLAN_RANGE_PARITY_STATUS_NACK_BCM56450_A0r */
  12416         soc_block_list[5],
  12417         soc_genreg,
  12418         1,
  12419         0,
  12420         0xa010e00,
  12421         0,
  12422         0,
  12423         3,
  12424         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  12425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12426         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12427         -1,
  12428         -1,
  12429     },
  12430 #endif /* chips */
  12431 
  12432 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  12433     { /* SOC_REG_INT_VLAN_RANGE_PARITY_STATUS_NACK_BCM56840_A0r */
  12434         soc_block_list[5],
  12435         soc_genreg,
  12436         1,
  12437         0,
  12438         0x2080d0e,
  12439         0,
  12440         0,
  12441         3,
  12442         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  12443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12444         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12445         -1,
  12446         -1,
  12447     },
  12448 #endif /* chips */
  12449 
  12450 #if defined(BCM_88732_A0)
  12451     { /* SOC_REG_INT_VLAN_STACKING_MODEr */
  12452         soc_block_list[5],
  12453         soc_genreg,
  12454         1,
  12455         0,
  12456         0x2080019,
  12457         0,
  12458         0,
  12459         1,
  12460         soc_VLAN_STACKING_MODEr_fields,
  12461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12462         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12463         -1,
  12464         -1,
  12465     },
  12466 #endif /* chips */
  12467 
  12468 #if defined(BCM_56514_A0)
  12469     { /* SOC_REG_INT_VLAN_STG_ADDR_MASKr */
  12470         soc_block_list[5],
  12471         soc_genreg,
  12472         1,
  12473         0,
  12474         0x5080000,
  12475         0,
  12476         0,
  12477         1,
  12478         soc_EGR_VLAN_STG_ADDR_MASKr_fields,
  12479         SOC_RESET_VAL_DEC(0x000001ff, 0x00000000)
  12480         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12481         -1,
  12482         -1,
  12483     },
  12484 #endif /* chips */
  12485 
  12486 #if defined(BCM_56800_A0)
  12487     { /* SOC_REG_INT_VLAN_STG_DBGCTRLr */
  12488         soc_block_list[5],
  12489         soc_genreg,
  12490         1,
  12491         0,
  12492         0x5080c01,
  12493         0,
  12494         0,
  12495         1,
  12496         soc_CFAPMEMDEBUGr_fields,
  12497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12498         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12499         -1,
  12500         -1,
  12501     },
  12502 #endif /* chips */
  12503 
  12504 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  12505     defined(BCM_56160_A0)
  12506     { /* SOC_REG_INT_VLAN_STG_DBGCTRL_BCM53400_A0r */
  12507         soc_block_list[5],
  12508         soc_genreg,
  12509         1,
  12510         0,
  12511         0x12010100,
  12512         0,
  12513         0,
  12514         1,
  12515         soc_DSCP_CONTROLr_fields,
  12516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12517         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12518         -1,
  12519         -1,
  12520     },
  12521 #endif /* chips */
  12522 
  12523 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  12524     { /* SOC_REG_INT_VLAN_STG_DBGCTRL_BCM53570_A0r */
  12525         soc_block_list[5],
  12526         soc_genreg,
  12527         1,
  12528         0,
  12529         0x12010800,
  12530         0,
  12531         0,
  12532         2,
  12533         soc_VLAN_STG_DBGCTRLr_fields,
  12534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12535         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12536         -1,
  12537         -1,
  12538     },
  12539 #endif /* chips */
  12540 
  12541 #if defined(BCM_56150_A0)
  12542     { /* SOC_REG_INT_VLAN_STG_DBGCTRL_BCM56150_A0r */
  12543         soc_block_list[5],
  12544         soc_genreg,
  12545         1,
  12546         0,
  12547         0x16010100,
  12548         0,
  12549         0,
  12550         1,
  12551         soc_INTFO_QCN_SRAM_TMr_fields,
  12552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12553         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12554         -1,
  12555         -1,
  12556     },
  12557 #endif /* chips */
  12558 
  12559 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  12560     defined(BCM_56334_B0)
  12561     { /* SOC_REG_INT_VLAN_STG_DBGCTRL_BCM56334_A0r */
  12562         soc_block_list[5],
  12563         soc_genreg,
  12564         1,
  12565         0,
  12566         0x508012e,
  12567         0,
  12568         0,
  12569         1,
  12570         soc_CFAPMEMDEBUGr_fields,
  12571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12572         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12573         -1,
  12574         -1,
  12575     },
  12576 #endif /* chips */
  12577 
  12578 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  12579     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  12580     { /* SOC_REG_INT_VLAN_STG_DBGCTRL_BCM56624_A0r */
  12581         soc_block_list[5],
  12582         soc_genreg,
  12583         1,
  12584         0,
  12585         0x508011b,
  12586         0,
  12587         0,
  12588         1,
  12589         soc_CFAPMEMDEBUGr_fields,
  12590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12592         -1,
  12593         -1,
  12594     },
  12595 #endif /* chips */
  12596 
  12597 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  12598     { /* SOC_REG_INT_VLAN_STG_DBGCTRL_BCM56820_A0r */
  12599         soc_block_list[5],
  12600         soc_genreg,
  12601         1,
  12602         0,
  12603         0x5080c01,
  12604         0,
  12605         0,
  12606         2,
  12607         soc_CFAPMEMDEBUG_BCM56820_A0r_fields,
  12608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12609         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12610         -1,
  12611         -1,
  12612     },
  12613 #endif /* chips */
  12614 
  12615 #if defined(BCM_88732_A0)
  12616     { /* SOC_REG_INT_VLAN_STG_ECC_STATUSr */
  12617         soc_block_list[5],
  12618         soc_genreg,
  12619         1,
  12620         0,
  12621         0x5080159,
  12622         0,
  12623         0,
  12624         1,
  12625         soc_VLAN_STG_ECC_STATUSr_fields,
  12626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12628         -1,
  12629         -1,
  12630     },
  12631 #endif /* chips */
  12632 
  12633 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  12634     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  12635     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  12636     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROLr */
  12637         soc_block_list[5],
  12638         soc_genreg,
  12639         1,
  12640         0,
  12641         0x6080156,
  12642         0,
  12643         0,
  12644         1,
  12645         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  12646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12647         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12648         -1,
  12649         -1,
  12650     },
  12651 #endif /* chips */
  12652 
  12653 #if defined(BCM_53400_A0)
  12654     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM53400_A0r */
  12655         soc_block_list[5],
  12656         soc_genreg,
  12657         1,
  12658         0,
  12659         0x12010400,
  12660         0,
  12661         0,
  12662         1,
  12663         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  12664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12665         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12666         -1,
  12667         -1,
  12668     },
  12669 #endif /* chips */
  12670 
  12671 #if defined(BCM_53570_A0)
  12672     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM53570_A0r */
  12673         soc_block_list[5],
  12674         soc_genreg,
  12675         1,
  12676         0,
  12677         0x12010c00,
  12678         0,
  12679         0,
  12680         1,
  12681         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  12682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12683         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12684         -1,
  12685         -1,
  12686     },
  12687 #endif /* chips */
  12688 
  12689 #if defined(BCM_53570_B0)
  12690     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM53570_B0r */
  12691         soc_block_list[5],
  12692         soc_genreg,
  12693         1,
  12694         0,
  12695         0x12010d00,
  12696         0,
  12697         0,
  12698         1,
  12699         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  12700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12701         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12702         -1,
  12703         -1,
  12704     },
  12705 #endif /* chips */
  12706 
  12707 #if defined(BCM_56150_A0)
  12708     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM56150_A0r */
  12709         soc_block_list[5],
  12710         soc_genreg,
  12711         1,
  12712         0,
  12713         0x16010400,
  12714         0,
  12715         0,
  12716         1,
  12717         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  12718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12719         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12720         -1,
  12721         -1,
  12722     },
  12723 #endif /* chips */
  12724 
  12725 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  12726     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM56160_A0r */
  12727         soc_block_list[5],
  12728         soc_genreg,
  12729         1,
  12730         0,
  12731         0x12010500,
  12732         0,
  12733         0,
  12734         1,
  12735         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  12736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12737         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12738         -1,
  12739         -1,
  12740     },
  12741 #endif /* chips */
  12742 
  12743 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  12744     defined(BCM_56270_A0)
  12745     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM56260_A0r */
  12746         soc_block_list[5],
  12747         soc_genreg,
  12748         1,
  12749         0,
  12750         0x16010300,
  12751         0,
  12752         0,
  12753         1,
  12754         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  12755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12756         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12757         -1,
  12758         -1,
  12759     },
  12760 #endif /* chips */
  12761 
  12762 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  12763     defined(BCM_56334_B0)
  12764     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM56334_A0r */
  12765         soc_block_list[5],
  12766         soc_genreg,
  12767         1,
  12768         0,
  12769         0x5080131,
  12770         0,
  12771         0,
  12772         1,
  12773         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  12774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12775         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12776         -1,
  12777         -1,
  12778     },
  12779 #endif /* chips */
  12780 
  12781 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12782     defined(BCM_56450_B1)
  12783     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM56450_A0r */
  12784         soc_block_list[5],
  12785         soc_genreg,
  12786         1,
  12787         0,
  12788         0x16010400,
  12789         0,
  12790         0,
  12791         1,
  12792         soc_FT_CNTR_SER_CONTROLr_fields,
  12793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12794         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12795         -1,
  12796         -1,
  12797     },
  12798 #endif /* chips */
  12799 
  12800 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  12801     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  12802     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM56560_A0r */
  12803         soc_block_list[5],
  12804         soc_genreg,
  12805         1,
  12806         0,
  12807         0x17080000,
  12808         0,
  12809         0,
  12810         1,
  12811         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  12812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12813         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12814         -1,
  12815         -1,
  12816     },
  12817 #endif /* chips */
  12818 
  12819 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  12820     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  12821     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM56840_A0r */
  12822         soc_block_list[5],
  12823         soc_genreg,
  12824         1,
  12825         0,
  12826         0x5080d04,
  12827         0,
  12828         0,
  12829         1,
  12830         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  12831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12832         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12833         -1,
  12834         -1,
  12835     },
  12836 #endif /* chips */
  12837 
  12838 #if defined(BCM_56850_A0)
  12839     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM56850_A0r */
  12840         soc_block_list[5],
  12841         soc_genreg,
  12842         1,
  12843         0,
  12844         0x17050000,
  12845         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12846         0,
  12847         1,
  12848         soc_FT_CNTR_SER_CONTROLr_fields,
  12849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12850         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12851         -1,
  12852         -1,
  12853     },
  12854 #endif /* chips */
  12855 
  12856 #if defined(BCM_56860_A0)
  12857     { /* SOC_REG_INT_VLAN_STG_PARITY_CONTROL_BCM56860_A0r */
  12858         soc_block_list[5],
  12859         soc_genreg,
  12860         1,
  12861         0,
  12862         0x17080000,
  12863         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  12864         0,
  12865         1,
  12866         soc_FT_CNTR_SER_CONTROLr_fields,
  12867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12868         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12869         -1,
  12870         -1,
  12871     },
  12872 #endif /* chips */
  12873 
  12874 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  12875     defined(BCM_56334_B0)
  12876     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUSr */
  12877         soc_block_list[5],
  12878         soc_genreg,
  12879         1,
  12880         0,
  12881         0x5080132,
  12882         0,
  12883         0,
  12884         3,
  12885         soc_CPU_TS_PARITY_STATUS_INTRr_fields,
  12886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12887         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12888         -1,
  12889         -1,
  12890     },
  12891 #endif /* chips */
  12892 
  12893 #if defined(BCM_53400_A0)
  12894     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_BCM53400_A0r */
  12895         soc_block_list[5],
  12896         soc_genreg,
  12897         1,
  12898         0,
  12899         0x12010500,
  12900         0,
  12901         0,
  12902         3,
  12903         soc_EGR_MOD_MAP_PARITY_STATUSr_fields,
  12904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12905         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12906         -1,
  12907         -1,
  12908     },
  12909 #endif /* chips */
  12910 
  12911 #if defined(BCM_53540_A0)
  12912     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_BCM53540_A0r */
  12913         soc_block_list[5],
  12914         soc_genreg,
  12915         1,
  12916         0,
  12917         0x12010600,
  12918         0,
  12919         0,
  12920         3,
  12921         soc_EGR_XP0_DBITS_PARITY_STATUSr_fields,
  12922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12923         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  12924         -1,
  12925         -1,
  12926     },
  12927 #endif /* chips */
  12928 
  12929 #if defined(BCM_53570_A0)
  12930     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_BCM53570_A0r */
  12931         soc_block_list[5],
  12932         soc_genreg,
  12933         1,
  12934         0,
  12935         0x12010d00,
  12936         0,
  12937         0,
  12938         3,
  12939         soc_EGR_MOD_MAP_PARITY_STATUSr_fields,
  12940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12941         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12942         -1,
  12943         -1,
  12944     },
  12945 #endif /* chips */
  12946 
  12947 #if defined(BCM_53570_B0)
  12948     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_BCM53570_B0r */
  12949         soc_block_list[5],
  12950         soc_genreg,
  12951         1,
  12952         0,
  12953         0x12010e00,
  12954         0,
  12955         0,
  12956         3,
  12957         soc_EGR_MOD_MAP_PARITY_STATUSr_fields,
  12958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12959         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12960         -1,
  12961         -1,
  12962     },
  12963 #endif /* chips */
  12964 
  12965 #if defined(BCM_56150_A0)
  12966     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_BCM56150_A0r */
  12967         soc_block_list[5],
  12968         soc_genreg,
  12969         1,
  12970         0,
  12971         0x16010500,
  12972         0,
  12973         0,
  12974         3,
  12975         soc_FP_FIELD_SEL_PARITY_STATUS_INTRr_fields,
  12976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12977         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12978         -1,
  12979         -1,
  12980     },
  12981 #endif /* chips */
  12982 
  12983 #if defined(BCM_56160_A0)
  12984     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_BCM56160_A0r */
  12985         soc_block_list[5],
  12986         soc_genreg,
  12987         1,
  12988         0,
  12989         0x12010600,
  12990         0,
  12991         0,
  12992         3,
  12993         soc_EGR_MOD_MAP_PARITY_STATUSr_fields,
  12994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12995         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12996         -1,
  12997         -1,
  12998     },
  12999 #endif /* chips */
  13000 
  13001 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  13002     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  13003     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  13004     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_INTRr */
  13005         soc_block_list[5],
  13006         soc_genreg,
  13007         1,
  13008         0,
  13009         0x6080157,
  13010         0,
  13011         0,
  13012         3,
  13013         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_STATUSr_fields,
  13014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13015         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13016         -1,
  13017         -1,
  13018     },
  13019 #endif /* chips */
  13020 
  13021 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13022     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_INTR_BCM56440_A0r */
  13023         soc_block_list[5],
  13024         soc_genreg,
  13025         1,
  13026         0,
  13027         0x5080d05,
  13028         0,
  13029         0,
  13030         3,
  13031         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  13032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13033         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13034         -1,
  13035         -1,
  13036     },
  13037 #endif /* chips */
  13038 
  13039 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13040     defined(BCM_56450_B1)
  13041     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_INTR_BCM56450_A0r */
  13042         soc_block_list[5],
  13043         soc_genreg,
  13044         1,
  13045         0,
  13046         0x16010500,
  13047         0,
  13048         0,
  13049         3,
  13050         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  13051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13052         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13053         -1,
  13054         -1,
  13055     },
  13056 #endif /* chips */
  13057 
  13058 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  13059     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_INTR_BCM56840_A0r */
  13060         soc_block_list[5],
  13061         soc_genreg,
  13062         1,
  13063         0,
  13064         0x5080d05,
  13065         0,
  13066         0,
  13067         3,
  13068         soc_EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr_fields,
  13069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13070         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13071         -1,
  13072         -1,
  13073     },
  13074 #endif /* chips */
  13075 
  13076 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  13077     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  13078     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  13079     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_NACKr */
  13080         soc_block_list[5],
  13081         soc_genreg,
  13082         1,
  13083         0,
  13084         0x6080158,
  13085         0,
  13086         0,
  13087         3,
  13088         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_STATUSr_fields,
  13089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13090         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13091         -1,
  13092         -1,
  13093     },
  13094 #endif /* chips */
  13095 
  13096 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  13097     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_NACK_BCM56440_A0r */
  13098         soc_block_list[5],
  13099         soc_genreg,
  13100         1,
  13101         0,
  13102         0x5080d06,
  13103         0,
  13104         0,
  13105         3,
  13106         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  13107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13109         -1,
  13110         -1,
  13111     },
  13112 #endif /* chips */
  13113 
  13114 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13115     defined(BCM_56450_B1)
  13116     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_NACK_BCM56450_A0r */
  13117         soc_block_list[5],
  13118         soc_genreg,
  13119         1,
  13120         0,
  13121         0x16010600,
  13122         0,
  13123         0,
  13124         3,
  13125         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  13126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13127         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13128         -1,
  13129         -1,
  13130     },
  13131 #endif /* chips */
  13132 
  13133 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  13134     { /* SOC_REG_INT_VLAN_STG_PARITY_STATUS_NACK_BCM56840_A0r */
  13135         soc_block_list[5],
  13136         soc_genreg,
  13137         1,
  13138         0,
  13139         0x5080d06,
  13140         0,
  13141         0,
  13142         3,
  13143         soc_EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr_fields,
  13144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13145         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13146         -1,
  13147         -1,
  13148     },
  13149 #endif /* chips */
  13150 
  13151 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  13152     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  13153     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIGr */
  13154         soc_block_list[5],
  13155         soc_genreg,
  13156         1,
  13157         0,
  13158         0x408010b,
  13159         0,
  13160         0,
  13161         4,
  13162         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  13163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13164         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13165         -1,
  13166         -1,
  13167     },
  13168 #endif /* chips */
  13169 
  13170 #if defined(BCM_56970_A0)
  13171     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_64r */
  13172         soc_block_list[5],
  13173         soc_genreg,
  13174         1,
  13175         0,
  13176         0x57030000,
  13177         SOC_REG_FLAG_64_BITS |
  13178                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13179         0,
  13180         5,
  13181         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  13182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13183         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13184         -1,
  13185         -1,
  13186         0,
  13187     },
  13188 #endif /* chips */
  13189 
  13190 #if defined(BCM_56970_A0)
  13191     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE0r */
  13192         soc_block_list[5],
  13193         soc_genreg,
  13194         1,
  13195         0,
  13196         0x57030000,
  13197         SOC_REG_FLAG_64_BITS,
  13198         0,
  13199         5,
  13200         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  13201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13202         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13203         -1,
  13204         -1,
  13205         0,
  13206     },
  13207 #endif /* chips */
  13208 
  13209 #if defined(BCM_56970_A0)
  13210     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE1r */
  13211         soc_block_list[5],
  13212         soc_genreg,
  13213         1,
  13214         0,
  13215         0x57030000,
  13216         SOC_REG_FLAG_64_BITS |
  13217                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13218         0,
  13219         5,
  13220         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  13221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13222         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13223         -1,
  13224         -1,
  13225         0,
  13226     },
  13227 #endif /* chips */
  13228 
  13229 #if defined(BCM_56970_A0)
  13230     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE2r */
  13231         soc_block_list[5],
  13232         soc_genreg,
  13233         1,
  13234         0,
  13235         0x57030000,
  13236         SOC_REG_FLAG_64_BITS |
  13237                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13238         0,
  13239         5,
  13240         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  13241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13242         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13243         -1,
  13244         -1,
  13245         0,
  13246     },
  13247 #endif /* chips */
  13248 
  13249 #if defined(BCM_56970_A0)
  13250     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE3r */
  13251         soc_block_list[5],
  13252         soc_genreg,
  13253         1,
  13254         0,
  13255         0x57030000,
  13256         SOC_REG_FLAG_64_BITS |
  13257                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13258         0,
  13259         5,
  13260         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  13261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13262         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13263         -1,
  13264         -1,
  13265         0,
  13266     },
  13267 #endif /* chips */
  13268 
  13269 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13270     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13271     defined(BCM_56160_A0)
  13272     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM53400_A0r */
  13273         soc_block_list[5],
  13274         soc_genreg,
  13275         1,
  13276         0,
  13277         0xe010400,
  13278         0,
  13279         0,
  13280         4,
  13281         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  13282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13283         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13284         -1,
  13285         -1,
  13286     },
  13287 #endif /* chips */
  13288 
  13289 #if defined(BCM_56150_A0)
  13290     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56150_A0r */
  13291         soc_block_list[5],
  13292         soc_genreg,
  13293         1,
  13294         0,
  13295         0x12010400,
  13296         0,
  13297         0,
  13298         4,
  13299         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
  13300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13301         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13302         -1,
  13303         -1,
  13304     },
  13305 #endif /* chips */
  13306 
  13307 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  13308     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  13309     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56224_A0r */
  13310         soc_block_list[5],
  13311         soc_genreg,
  13312         1,
  13313         0,
  13314         0x4080002,
  13315         0,
  13316         0,
  13317         2,
  13318         soc_FP_CAM_BIST_CONFIGr_fields,
  13319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13320         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13321         -1,
  13322         -1,
  13323     },
  13324 #endif /* chips */
  13325 
  13326 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  13327     defined(BCM_56270_A0)
  13328     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56260_A0r */
  13329         soc_block_list[5],
  13330         soc_genreg,
  13331         1,
  13332         0,
  13333         0x12010200,
  13334         0,
  13335         0,
  13336         4,
  13337         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  13338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13339         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13340         -1,
  13341         -1,
  13342     },
  13343 #endif /* chips */
  13344 
  13345 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  13346     defined(BCM_56334_B0)
  13347     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56334_A0r */
  13348         soc_block_list[5],
  13349         soc_genreg,
  13350         1,
  13351         0,
  13352         0x4080113,
  13353         0,
  13354         0,
  13355         4,
  13356         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  13357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13358         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13359         -1,
  13360         -1,
  13361     },
  13362 #endif /* chips */
  13363 
  13364 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  13365     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56560_A0r */
  13366         soc_block_list[5],
  13367         soc_genreg,
  13368         1,
  13369         0,
  13370         0x13030000,
  13371         0,
  13372         0,
  13373         4,
  13374         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  13375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13376         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13377         -1,
  13378         -1,
  13379     },
  13380 #endif /* chips */
  13381 
  13382 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  13383     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  13384     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  13385     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56634_A0r */
  13386         soc_block_list[5],
  13387         soc_genreg,
  13388         1,
  13389         0,
  13390         0x4080137,
  13391         0,
  13392         0,
  13393         4,
  13394         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  13395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13396         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13397         -1,
  13398         -1,
  13399     },
  13400 #endif /* chips */
  13401 
  13402 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  13403     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  13404     defined(BCM_56640_A0)
  13405     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56640_A0r */
  13406         soc_block_list[5],
  13407         soc_genreg,
  13408         1,
  13409         0,
  13410         0x12010200,
  13411         0,
  13412         0,
  13413         4,
  13414         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
  13415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13416         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13417         -1,
  13418         -1,
  13419     },
  13420 #endif /* chips */
  13421 
  13422 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13423     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56670_A0r */
  13424         soc_block_list[5],
  13425         soc_genreg,
  13426         1,
  13427         0,
  13428         0x13040000,
  13429         0,
  13430         0,
  13431         4,
  13432         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  13433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13434         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13435         -1,
  13436         -1,
  13437     },
  13438 #endif /* chips */
  13439 
  13440 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  13441     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56820_A0r */
  13442         soc_block_list[5],
  13443         soc_genreg,
  13444         1,
  13445         0,
  13446         0x4080048,
  13447         0,
  13448         0,
  13449         4,
  13450         soc_VLAN_SUBNET_CAM_BIST_CONFIGr_fields,
  13451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13452         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13453         -1,
  13454         -1,
  13455     },
  13456 #endif /* chips */
  13457 
  13458 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  13459     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  13460     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56840_A0r */
  13461         soc_block_list[5],
  13462         soc_genreg,
  13463         1,
  13464         0,
  13465         0x4080d04,
  13466         0,
  13467         0,
  13468         4,
  13469         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  13470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13471         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13472         -1,
  13473         -1,
  13474     },
  13475 #endif /* chips */
  13476 
  13477 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  13478     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56850_A0r */
  13479         soc_block_list[5],
  13480         soc_genreg,
  13481         1,
  13482         0,
  13483         0x13030000,
  13484         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13485         0,
  13486         4,
  13487         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
  13488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13489         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13490         -1,
  13491         -1,
  13492     },
  13493 #endif /* chips */
  13494 
  13495 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13496     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM56960_A0r */
  13497         soc_block_list[5],
  13498         soc_genreg,
  13499         1,
  13500         0,
  13501         0x33030000,
  13502         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13503         0,
  13504         4,
  13505         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  13506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13507         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13508         -1,
  13509         -1,
  13510         0,
  13511     },
  13512 #endif /* chips */
  13513 
  13514 #if defined(BCM_88732_A0)
  13515     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_BCM88732_A0r */
  13516         soc_block_list[5],
  13517         soc_genreg,
  13518         1,
  13519         0,
  13520         0x4080172,
  13521         0,
  13522         0,
  13523         4,
  13524         soc_VLAN_SUBNET_CAM_BIST_CONFIG_BCM88732_A0r_fields,
  13525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13526         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13527         -1,
  13528         -1,
  13529     },
  13530 #endif /* chips */
  13531 
  13532 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13533     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_PIPE0r */
  13534         soc_block_list[5],
  13535         soc_genreg,
  13536         1,
  13537         0,
  13538         0x33030000,
  13539         0,
  13540         0,
  13541         4,
  13542         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  13543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13544         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13545         -1,
  13546         -1,
  13547         0,
  13548     },
  13549 #endif /* chips */
  13550 
  13551 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13552     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_PIPE1r */
  13553         soc_block_list[5],
  13554         soc_genreg,
  13555         1,
  13556         0,
  13557         0x33030000,
  13558         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13559         0,
  13560         4,
  13561         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  13562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13564         -1,
  13565         -1,
  13566         0,
  13567     },
  13568 #endif /* chips */
  13569 
  13570 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13571     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_PIPE2r */
  13572         soc_block_list[5],
  13573         soc_genreg,
  13574         1,
  13575         0,
  13576         0x33030000,
  13577         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13578         0,
  13579         4,
  13580         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  13581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13582         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13583         -1,
  13584         -1,
  13585         0,
  13586     },
  13587 #endif /* chips */
  13588 
  13589 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13590     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONFIG_PIPE3r */
  13591         soc_block_list[5],
  13592         soc_genreg,
  13593         1,
  13594         0,
  13595         0x33030000,
  13596         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13597         0,
  13598         4,
  13599         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  13600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13601         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13602         -1,
  13603         -1,
  13604         0,
  13605     },
  13606 #endif /* chips */
  13607 
  13608 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  13609     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  13610     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONTROLr */
  13611         soc_block_list[5],
  13612         soc_genreg,
  13613         1,
  13614         0,
  13615         0x4080000,
  13616         0,
  13617         0,
  13618         4,
  13619         soc_L3_DEFIP_128_CAM_BIST_CONTROLr_fields,
  13620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13621         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13622         -1,
  13623         -1,
  13624     },
  13625 #endif /* chips */
  13626 
  13627 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  13628     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONTROL_BCM56820_A0r */
  13629         soc_block_list[5],
  13630         soc_genreg,
  13631         1,
  13632         0,
  13633         0x4080046,
  13634         0,
  13635         0,
  13636         4,
  13637         soc_L3_DEFIP_128_CAM_BIST_CONTROLr_fields,
  13638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13639         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13640         -1,
  13641         -1,
  13642     },
  13643 #endif /* chips */
  13644 
  13645 #if defined(BCM_88732_A0)
  13646     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_CONTROL_BCM88732_A0r */
  13647         soc_block_list[5],
  13648         soc_genreg,
  13649         1,
  13650         0,
  13651         0x4080170,
  13652         0,
  13653         0,
  13654         4,
  13655         soc_VLAN_SUBNET_CAM_BIST_CONTROLr_fields,
  13656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13657         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13658         -1,
  13659         -1,
  13660     },
  13661 #endif /* chips */
  13662 
  13663 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  13664     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  13665     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATAr */
  13666         soc_block_list[5],
  13667         soc_genreg,
  13668         1,
  13669         0,
  13670         0x408010c,
  13671         SOC_REG_FLAG_WO,
  13672         0,
  13673         1,
  13674         soc_FP_CAM_DEBUG_DATA_0r_fields,
  13675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13676         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13677         -1,
  13678         -1,
  13679     },
  13680 #endif /* chips */
  13681 
  13682 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13683     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13684     defined(BCM_56160_A0)
  13685     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM53400_A0r */
  13686         soc_block_list[5],
  13687         soc_genreg,
  13688         1,
  13689         0,
  13690         0xe010500,
  13691         SOC_REG_FLAG_WO,
  13692         0,
  13693         1,
  13694         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  13695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13696         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13697         -1,
  13698         -1,
  13699     },
  13700 #endif /* chips */
  13701 
  13702 #if defined(BCM_56150_A0)
  13703     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56150_A0r */
  13704         soc_block_list[5],
  13705         soc_genreg,
  13706         1,
  13707         0,
  13708         0x12010500,
  13709         SOC_REG_FLAG_WO,
  13710         0,
  13711         1,
  13712         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
  13713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13714         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13715         -1,
  13716         -1,
  13717     },
  13718 #endif /* chips */
  13719 
  13720 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  13721     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  13722     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56224_A0r */
  13723         soc_block_list[5],
  13724         soc_genreg,
  13725         1,
  13726         0,
  13727         0x4080005,
  13728         0,
  13729         0,
  13730         1,
  13731         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  13732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13733         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13734         -1,
  13735         -1,
  13736     },
  13737 #endif /* chips */
  13738 
  13739 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  13740     defined(BCM_56270_A0)
  13741     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56260_A0r */
  13742         soc_block_list[5],
  13743         soc_genreg,
  13744         1,
  13745         0,
  13746         0x12010300,
  13747         SOC_REG_FLAG_WO,
  13748         0,
  13749         1,
  13750         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  13751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13752         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13753         -1,
  13754         -1,
  13755     },
  13756 #endif /* chips */
  13757 
  13758 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  13759     defined(BCM_56334_B0)
  13760     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56334_A0r */
  13761         soc_block_list[5],
  13762         soc_genreg,
  13763         1,
  13764         0,
  13765         0x4080114,
  13766         SOC_REG_FLAG_WO,
  13767         0,
  13768         1,
  13769         soc_FP_CAM_DEBUG_DATA_0r_fields,
  13770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13772         -1,
  13773         -1,
  13774     },
  13775 #endif /* chips */
  13776 
  13777 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  13778     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56560_A0r */
  13779         soc_block_list[5],
  13780         soc_genreg,
  13781         1,
  13782         0,
  13783         0x13040000,
  13784         SOC_REG_FLAG_WO,
  13785         0,
  13786         1,
  13787         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  13788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13790         -1,
  13791         -1,
  13792     },
  13793 #endif /* chips */
  13794 
  13795 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  13796     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  13797     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  13798     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56634_A0r */
  13799         soc_block_list[5],
  13800         soc_genreg,
  13801         1,
  13802         0,
  13803         0x4080138,
  13804         SOC_REG_FLAG_WO,
  13805         0,
  13806         1,
  13807         soc_FP_CAM_DEBUG_DATA_0r_fields,
  13808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13809         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13810         -1,
  13811         -1,
  13812     },
  13813 #endif /* chips */
  13814 
  13815 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  13816     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  13817     defined(BCM_56640_A0)
  13818     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56640_A0r */
  13819         soc_block_list[5],
  13820         soc_genreg,
  13821         1,
  13822         0,
  13823         0x12010300,
  13824         SOC_REG_FLAG_WO,
  13825         0,
  13826         1,
  13827         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
  13828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13829         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13830         -1,
  13831         -1,
  13832     },
  13833 #endif /* chips */
  13834 
  13835 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  13836     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56670_A0r */
  13837         soc_block_list[5],
  13838         soc_genreg,
  13839         1,
  13840         0,
  13841         0x13050000,
  13842         SOC_REG_FLAG_WO,
  13843         0,
  13844         1,
  13845         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  13846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13847         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13848         -1,
  13849         -1,
  13850     },
  13851 #endif /* chips */
  13852 
  13853 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  13854     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56820_A0r */
  13855         soc_block_list[5],
  13856         soc_genreg,
  13857         1,
  13858         0,
  13859         0x408004b,
  13860         0,
  13861         0,
  13862         1,
  13863         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  13864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13865         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13866         -1,
  13867         -1,
  13868     },
  13869 #endif /* chips */
  13870 
  13871 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  13872     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  13873     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56840_A0r */
  13874         soc_block_list[5],
  13875         soc_genreg,
  13876         1,
  13877         0,
  13878         0x4080d05,
  13879         SOC_REG_FLAG_WO,
  13880         0,
  13881         1,
  13882         soc_FP_CAM_DEBUG_DATA_0r_fields,
  13883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13884         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13885         -1,
  13886         -1,
  13887     },
  13888 #endif /* chips */
  13889 
  13890 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  13891     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56850_A0r */
  13892         soc_block_list[5],
  13893         soc_genreg,
  13894         1,
  13895         0,
  13896         0x13040000,
  13897         SOC_REG_FLAG_WO |
  13898                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13899         0,
  13900         1,
  13901         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
  13902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13903         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13904         -1,
  13905         -1,
  13906     },
  13907 #endif /* chips */
  13908 
  13909 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13910     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56960_A0r */
  13911         soc_block_list[5],
  13912         soc_genreg,
  13913         1,
  13914         0,
  13915         0x33040000,
  13916         SOC_REG_FLAG_WO |
  13917                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13918         0,
  13919         1,
  13920         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  13921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13922         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13923         -1,
  13924         -1,
  13925         0,
  13926     },
  13927 #endif /* chips */
  13928 
  13929 #if defined(BCM_56970_A0)
  13930     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM56970_A0r */
  13931         soc_block_list[5],
  13932         soc_genreg,
  13933         1,
  13934         0,
  13935         0x57040000,
  13936         SOC_REG_FLAG_WO |
  13937                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13938         0,
  13939         1,
  13940         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  13941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13942         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13943         -1,
  13944         -1,
  13945         0,
  13946     },
  13947 #endif /* chips */
  13948 
  13949 #if defined(BCM_88732_A0)
  13950     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_BCM88732_A0r */
  13951         soc_block_list[5],
  13952         soc_genreg,
  13953         1,
  13954         0,
  13955         0x4080173,
  13956         0,
  13957         0,
  13958         1,
  13959         soc_VLAN_SUBNET_CAM_BIST_DBG_DATAr_fields,
  13960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13961         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13962         -1,
  13963         -1,
  13964     },
  13965 #endif /* chips */
  13966 
  13967 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13968     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE0r */
  13969         soc_block_list[5],
  13970         soc_genreg,
  13971         1,
  13972         0,
  13973         0x33040000,
  13974         SOC_REG_FLAG_WO,
  13975         0,
  13976         1,
  13977         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  13978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13979         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13980         -1,
  13981         -1,
  13982         0,
  13983     },
  13984 #endif /* chips */
  13985 
  13986 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  13987     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE1r */
  13988         soc_block_list[5],
  13989         soc_genreg,
  13990         1,
  13991         0,
  13992         0x33040000,
  13993         SOC_REG_FLAG_WO |
  13994                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  13995         0,
  13996         1,
  13997         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  13998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13999         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14000         -1,
  14001         -1,
  14002         0,
  14003     },
  14004 #endif /* chips */
  14005 
  14006 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  14007     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE2r */
  14008         soc_block_list[5],
  14009         soc_genreg,
  14010         1,
  14011         0,
  14012         0x33040000,
  14013         SOC_REG_FLAG_WO |
  14014                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14015         0,
  14016         1,
  14017         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  14018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14019         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14020         -1,
  14021         -1,
  14022         0,
  14023     },
  14024 #endif /* chips */
  14025 
  14026 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  14027     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE3r */
  14028         soc_block_list[5],
  14029         soc_genreg,
  14030         1,
  14031         0,
  14032         0x33040000,
  14033         SOC_REG_FLAG_WO |
  14034                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14035         0,
  14036         1,
  14037         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  14038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14039         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14040         -1,
  14041         -1,
  14042         0,
  14043     },
  14044 #endif /* chips */
  14045 
  14046 #if defined(BCM_56970_A0)
  14047     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE0_BCM56970_A0r */
  14048         soc_block_list[5],
  14049         soc_genreg,
  14050         1,
  14051         0,
  14052         0x57040000,
  14053         SOC_REG_FLAG_WO,
  14054         0,
  14055         1,
  14056         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  14057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14058         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14059         -1,
  14060         -1,
  14061         0,
  14062     },
  14063 #endif /* chips */
  14064 
  14065 #if defined(BCM_56970_A0)
  14066     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE1_BCM56970_A0r */
  14067         soc_block_list[5],
  14068         soc_genreg,
  14069         1,
  14070         0,
  14071         0x57040000,
  14072         SOC_REG_FLAG_WO |
  14073                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14074         0,
  14075         1,
  14076         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  14077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14078         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14079         -1,
  14080         -1,
  14081         0,
  14082     },
  14083 #endif /* chips */
  14084 
  14085 #if defined(BCM_56970_A0)
  14086     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE2_BCM56970_A0r */
  14087         soc_block_list[5],
  14088         soc_genreg,
  14089         1,
  14090         0,
  14091         0x57040000,
  14092         SOC_REG_FLAG_WO |
  14093                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14094         0,
  14095         1,
  14096         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  14097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14098         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14099         -1,
  14100         -1,
  14101         0,
  14102     },
  14103 #endif /* chips */
  14104 
  14105 #if defined(BCM_56970_A0)
  14106     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE3_BCM56970_A0r */
  14107         soc_block_list[5],
  14108         soc_genreg,
  14109         1,
  14110         0,
  14111         0x57040000,
  14112         SOC_REG_FLAG_WO |
  14113                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14114         0,
  14115         1,
  14116         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  14117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14118         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14119         -1,
  14120         -1,
  14121         0,
  14122     },
  14123 #endif /* chips */
  14124 
  14125 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  14126     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  14127     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DEBUG_DATA_VALIDr */
  14128         soc_block_list[5],
  14129         soc_genreg,
  14130         1,
  14131         0,
  14132         0x4080004,
  14133         0,
  14134         0,
  14135         1,
  14136         soc_FP_CAM_BIST_DBG_DATA_VALIDr_fields,
  14137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14138         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14139         -1,
  14140         -1,
  14141     },
  14142 #endif /* chips */
  14143 
  14144 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  14145     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  14146     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_DEBUG_SENDr */
  14147         soc_block_list[5],
  14148         soc_genreg,
  14149         1,
  14150         0,
  14151         0x4080003,
  14152         0,
  14153         0,
  14154         1,
  14155         soc_VLAN_SUBNET_CAM_BIST_DEBUG_SENDr_fields,
  14156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14157         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14158         -1,
  14159         -1,
  14160     },
  14161 #endif /* chips */
  14162 
  14163 #if defined(BCM_56504_A0)
  14164     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S10_STATUSr */
  14165         soc_block_list[5],
  14166         soc_genreg,
  14167         1,
  14168         0,
  14169         0x4080007,
  14170         SOC_REG_FLAG_RO,
  14171         0,
  14172         2,
  14173         soc_FP_CAM_BIST_S10_STATUSr_fields,
  14174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14175         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14176         -1,
  14177         -1,
  14178     },
  14179 #endif /* chips */
  14180 
  14181 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  14182     defined(BCM_56514_A0)
  14183     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S10_STATUS_BCM56504_B0r */
  14184         soc_block_list[5],
  14185         soc_genreg,
  14186         1,
  14187         0,
  14188         0x4080007,
  14189         SOC_REG_FLAG_RO,
  14190         0,
  14191         1,
  14192         soc_L2_USER_ENTRY_CAM_BIST_S10_STATUSr_fields,
  14193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14194         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14195         -1,
  14196         -1,
  14197     },
  14198 #endif /* chips */
  14199 
  14200 #if defined(BCM_56800_A0)
  14201     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S10_STATUS_BCM56800_A0r */
  14202         soc_block_list[5],
  14203         soc_genreg,
  14204         1,
  14205         0,
  14206         0x4080c07,
  14207         SOC_REG_FLAG_RO,
  14208         0,
  14209         2,
  14210         soc_FP_CAM_BIST_S10_STATUSr_fields,
  14211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14212         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14213         -1,
  14214         -1,
  14215     },
  14216 #endif /* chips */
  14217 
  14218 #if defined(BCM_56504_A0)
  14219     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S2_STATUSr */
  14220         soc_block_list[5],
  14221         soc_genreg,
  14222         1,
  14223         0,
  14224         0x4080002,
  14225         SOC_REG_FLAG_RO,
  14226         0,
  14227         3,
  14228         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  14229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14230         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14231         -1,
  14232         -1,
  14233     },
  14234 #endif /* chips */
  14235 
  14236 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  14237     defined(BCM_56514_A0)
  14238     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S2_STATUS_BCM56504_B0r */
  14239         soc_block_list[5],
  14240         soc_genreg,
  14241         1,
  14242         0,
  14243         0x4080002,
  14244         SOC_REG_FLAG_RO,
  14245         0,
  14246         1,
  14247         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUS_BCM56504_B0r_fields,
  14248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14250         -1,
  14251         -1,
  14252     },
  14253 #endif /* chips */
  14254 
  14255 #if defined(BCM_56800_A0)
  14256     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S2_STATUS_BCM56800_A0r */
  14257         soc_block_list[5],
  14258         soc_genreg,
  14259         1,
  14260         0,
  14261         0x4080c02,
  14262         SOC_REG_FLAG_RO,
  14263         0,
  14264         3,
  14265         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  14266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14267         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14268         -1,
  14269         -1,
  14270     },
  14271 #endif /* chips */
  14272 
  14273 #if defined(BCM_56504_A0)
  14274     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S3_STATUSr */
  14275         soc_block_list[5],
  14276         soc_genreg,
  14277         1,
  14278         0,
  14279         0x4080003,
  14280         SOC_REG_FLAG_RO,
  14281         0,
  14282         4,
  14283         soc_FP_CAM_BIST_S12_STATUSr_fields,
  14284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14285         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14286         -1,
  14287         -1,
  14288     },
  14289 #endif /* chips */
  14290 
  14291 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  14292     defined(BCM_56514_A0)
  14293     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S3_STATUS_BCM56504_B0r */
  14294         soc_block_list[5],
  14295         soc_genreg,
  14296         1,
  14297         0,
  14298         0x4080003,
  14299         SOC_REG_FLAG_RO,
  14300         0,
  14301         1,
  14302         soc_L2_USER_ENTRY_CAM_BIST_S3_STATUSr_fields,
  14303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14304         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14305         -1,
  14306         -1,
  14307     },
  14308 #endif /* chips */
  14309 
  14310 #if defined(BCM_56800_A0)
  14311     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S3_STATUS_BCM56800_A0r */
  14312         soc_block_list[5],
  14313         soc_genreg,
  14314         1,
  14315         0,
  14316         0x4080c03,
  14317         SOC_REG_FLAG_RO,
  14318         0,
  14319         4,
  14320         soc_FP_CAM_BIST_S12_STATUSr_fields,
  14321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14322         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14323         -1,
  14324         -1,
  14325     },
  14326 #endif /* chips */
  14327 
  14328 #if defined(BCM_56504_A0)
  14329     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S5_STATUSr */
  14330         soc_block_list[5],
  14331         soc_genreg,
  14332         1,
  14333         0,
  14334         0x4080004,
  14335         SOC_REG_FLAG_RO,
  14336         0,
  14337         3,
  14338         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  14339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14340         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14341         -1,
  14342         -1,
  14343     },
  14344 #endif /* chips */
  14345 
  14346 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  14347     defined(BCM_56514_A0)
  14348     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S5_STATUS_BCM56504_B0r */
  14349         soc_block_list[5],
  14350         soc_genreg,
  14351         1,
  14352         0,
  14353         0x4080004,
  14354         SOC_REG_FLAG_RO,
  14355         0,
  14356         1,
  14357         soc_L2_USER_ENTRY_CAM_BIST_S5_STATUSr_fields,
  14358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14359         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14360         -1,
  14361         -1,
  14362     },
  14363 #endif /* chips */
  14364 
  14365 #if defined(BCM_56800_A0)
  14366     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S5_STATUS_BCM56800_A0r */
  14367         soc_block_list[5],
  14368         soc_genreg,
  14369         1,
  14370         0,
  14371         0x4080c04,
  14372         SOC_REG_FLAG_RO,
  14373         0,
  14374         3,
  14375         soc_L2_USER_ENTRY_CAM_BIST_S2_STATUSr_fields,
  14376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14377         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14378         -1,
  14379         -1,
  14380     },
  14381 #endif /* chips */
  14382 
  14383 #if defined(BCM_56504_A0)
  14384     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S6_STATUSr */
  14385         soc_block_list[5],
  14386         soc_genreg,
  14387         1,
  14388         0,
  14389         0x4080005,
  14390         SOC_REG_FLAG_RO,
  14391         0,
  14392         4,
  14393         soc_FP_CAM_BIST_S12_STATUSr_fields,
  14394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14395         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14396         -1,
  14397         -1,
  14398     },
  14399 #endif /* chips */
  14400 
  14401 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  14402     defined(BCM_56514_A0)
  14403     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S6_STATUS_BCM56504_B0r */
  14404         soc_block_list[5],
  14405         soc_genreg,
  14406         1,
  14407         0,
  14408         0x4080005,
  14409         SOC_REG_FLAG_RO,
  14410         0,
  14411         1,
  14412         soc_L2_USER_ENTRY_CAM_BIST_S6_STATUSr_fields,
  14413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14414         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14415         -1,
  14416         -1,
  14417     },
  14418 #endif /* chips */
  14419 
  14420 #if defined(BCM_56800_A0)
  14421     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S6_STATUS_BCM56800_A0r */
  14422         soc_block_list[5],
  14423         soc_genreg,
  14424         1,
  14425         0,
  14426         0x4080c05,
  14427         SOC_REG_FLAG_RO,
  14428         0,
  14429         4,
  14430         soc_FP_CAM_BIST_S12_STATUSr_fields,
  14431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14432         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14433         -1,
  14434         -1,
  14435     },
  14436 #endif /* chips */
  14437 
  14438 #if defined(BCM_56504_A0)
  14439     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S8_STATUSr */
  14440         soc_block_list[5],
  14441         soc_genreg,
  14442         1,
  14443         0,
  14444         0x4080006,
  14445         SOC_REG_FLAG_RO,
  14446         0,
  14447         4,
  14448         soc_FP_CAM_BIST_S12_STATUSr_fields,
  14449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14450         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14451         -1,
  14452         -1,
  14453     },
  14454 #endif /* chips */
  14455 
  14456 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  14457     defined(BCM_56514_A0)
  14458     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S8_STATUS_BCM56504_B0r */
  14459         soc_block_list[5],
  14460         soc_genreg,
  14461         1,
  14462         0,
  14463         0x4080006,
  14464         SOC_REG_FLAG_RO,
  14465         0,
  14466         1,
  14467         soc_L2_USER_ENTRY_CAM_BIST_S8_STATUSr_fields,
  14468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14469         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14470         -1,
  14471         -1,
  14472     },
  14473 #endif /* chips */
  14474 
  14475 #if defined(BCM_56800_A0)
  14476     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_S8_STATUS_BCM56800_A0r */
  14477         soc_block_list[5],
  14478         soc_genreg,
  14479         1,
  14480         0,
  14481         0x4080c06,
  14482         SOC_REG_FLAG_RO,
  14483         0,
  14484         4,
  14485         soc_FP_CAM_BIST_S12_STATUSr_fields,
  14486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14488         -1,
  14489         -1,
  14490     },
  14491 #endif /* chips */
  14492 
  14493 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  14494     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  14495     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUSr */
  14496         soc_block_list[5],
  14497         soc_genreg,
  14498         1,
  14499         0,
  14500         0x4080001,
  14501         0,
  14502         0,
  14503         2,
  14504         soc_L2_USER_ENTRY_CAM_BIST_STATUSr_fields,
  14505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14506         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14507         -1,
  14508         -1,
  14509     },
  14510 #endif /* chips */
  14511 
  14512 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14513     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14514     defined(BCM_56160_A0)
  14515     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM53400_A0r */
  14516         soc_block_list[5],
  14517         soc_genreg,
  14518         1,
  14519         0,
  14520         0xe010300,
  14521         SOC_REG_FLAG_RO,
  14522         0,
  14523         1,
  14524         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14526         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14527         -1,
  14528         -1,
  14529     },
  14530 #endif /* chips */
  14531 
  14532 #if defined(BCM_56150_A0)
  14533     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56150_A0r */
  14534         soc_block_list[5],
  14535         soc_genreg,
  14536         1,
  14537         0,
  14538         0x12010300,
  14539         SOC_REG_FLAG_RO,
  14540         0,
  14541         1,
  14542         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  14543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14544         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14545         -1,
  14546         -1,
  14547     },
  14548 #endif /* chips */
  14549 
  14550 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  14551     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  14552     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56224_A0r */
  14553         soc_block_list[5],
  14554         soc_genreg,
  14555         1,
  14556         0,
  14557         0x4080001,
  14558         SOC_REG_FLAG_RO,
  14559         0,
  14560         1,
  14561         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  14562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14563         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14564         -1,
  14565         -1,
  14566     },
  14567 #endif /* chips */
  14568 
  14569 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  14570     defined(BCM_56270_A0)
  14571     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56260_A0r */
  14572         soc_block_list[5],
  14573         soc_genreg,
  14574         1,
  14575         0,
  14576         0x12010100,
  14577         SOC_REG_FLAG_RO,
  14578         0,
  14579         1,
  14580         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14582         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14583         -1,
  14584         -1,
  14585     },
  14586 #endif /* chips */
  14587 
  14588 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  14589     defined(BCM_56334_B0)
  14590     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56334_A0r */
  14591         soc_block_list[5],
  14592         soc_genreg,
  14593         1,
  14594         0,
  14595         0x4080112,
  14596         SOC_REG_FLAG_RO,
  14597         0,
  14598         1,
  14599         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  14600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14601         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14602         -1,
  14603         -1,
  14604     },
  14605 #endif /* chips */
  14606 
  14607 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  14608     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56560_A0r */
  14609         soc_block_list[5],
  14610         soc_genreg,
  14611         1,
  14612         0,
  14613         0x13020000,
  14614         SOC_REG_FLAG_RO,
  14615         0,
  14616         1,
  14617         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14619         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14620         -1,
  14621         -1,
  14622     },
  14623 #endif /* chips */
  14624 
  14625 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  14626     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  14627     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56624_A0r */
  14628         soc_block_list[5],
  14629         soc_genreg,
  14630         1,
  14631         0,
  14632         0x408010a,
  14633         SOC_REG_FLAG_RO,
  14634         0,
  14635         1,
  14636         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  14637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14638         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14639         -1,
  14640         -1,
  14641     },
  14642 #endif /* chips */
  14643 
  14644 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  14645     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  14646     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  14647     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56634_A0r */
  14648         soc_block_list[5],
  14649         soc_genreg,
  14650         1,
  14651         0,
  14652         0x4080136,
  14653         SOC_REG_FLAG_RO,
  14654         0,
  14655         1,
  14656         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  14657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14658         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14659         -1,
  14660         -1,
  14661     },
  14662 #endif /* chips */
  14663 
  14664 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  14665     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  14666     defined(BCM_56640_A0)
  14667     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56640_A0r */
  14668         soc_block_list[5],
  14669         soc_genreg,
  14670         1,
  14671         0,
  14672         0x12010100,
  14673         SOC_REG_FLAG_RO,
  14674         0,
  14675         1,
  14676         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  14677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14678         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14679         -1,
  14680         -1,
  14681     },
  14682 #endif /* chips */
  14683 
  14684 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  14685     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56670_A0r */
  14686         soc_block_list[5],
  14687         soc_genreg,
  14688         1,
  14689         0,
  14690         0x13030000,
  14691         SOC_REG_FLAG_RO,
  14692         0,
  14693         1,
  14694         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14696         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14697         -1,
  14698         -1,
  14699     },
  14700 #endif /* chips */
  14701 
  14702 #if defined(BCM_56800_A0)
  14703     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56800_A0r */
  14704         soc_block_list[5],
  14705         soc_genreg,
  14706         1,
  14707         0,
  14708         0x4080c01,
  14709         0,
  14710         0,
  14711         2,
  14712         soc_L2_USER_ENTRY_CAM_BIST_STATUSr_fields,
  14713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14714         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14715         -1,
  14716         -1,
  14717     },
  14718 #endif /* chips */
  14719 
  14720 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  14721     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56820_A0r */
  14722         soc_block_list[5],
  14723         soc_genreg,
  14724         1,
  14725         0,
  14726         0x4080047,
  14727         SOC_REG_FLAG_RO,
  14728         0,
  14729         1,
  14730         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  14731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14732         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14733         -1,
  14734         -1,
  14735     },
  14736 #endif /* chips */
  14737 
  14738 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  14739     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  14740     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56840_A0r */
  14741         soc_block_list[5],
  14742         soc_genreg,
  14743         1,
  14744         0,
  14745         0x4080d03,
  14746         SOC_REG_FLAG_RO,
  14747         0,
  14748         1,
  14749         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  14750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14751         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14752         -1,
  14753         -1,
  14754     },
  14755 #endif /* chips */
  14756 
  14757 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  14758     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56850_A0r */
  14759         soc_block_list[5],
  14760         soc_genreg,
  14761         1,
  14762         0,
  14763         0x13020000,
  14764         SOC_REG_FLAG_RO |
  14765                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14766         0,
  14767         1,
  14768         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  14769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14770         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14771         -1,
  14772         -1,
  14773     },
  14774 #endif /* chips */
  14775 
  14776 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  14777     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56960_A0r */
  14778         soc_block_list[5],
  14779         soc_genreg,
  14780         1,
  14781         0,
  14782         0x33020000,
  14783         SOC_REG_FLAG_RO |
  14784                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14785         0,
  14786         1,
  14787         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14790         -1,
  14791         -1,
  14792         0,
  14793     },
  14794 #endif /* chips */
  14795 
  14796 #if defined(BCM_56970_A0)
  14797     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM56970_A0r */
  14798         soc_block_list[5],
  14799         soc_genreg,
  14800         1,
  14801         0,
  14802         0x57020000,
  14803         SOC_REG_FLAG_RO |
  14804                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14805         0,
  14806         1,
  14807         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14809         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14810         -1,
  14811         -1,
  14812         0,
  14813     },
  14814 #endif /* chips */
  14815 
  14816 #if defined(BCM_88732_A0)
  14817     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_BCM88732_A0r */
  14818         soc_block_list[5],
  14819         soc_genreg,
  14820         1,
  14821         0,
  14822         0x4080171,
  14823         SOC_REG_FLAG_RO,
  14824         0,
  14825         1,
  14826         soc_FP_CAM_BIST_STATUS_BCM88732_A0r_fields,
  14827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14828         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14829         -1,
  14830         -1,
  14831     },
  14832 #endif /* chips */
  14833 
  14834 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  14835     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_PIPE0r */
  14836         soc_block_list[5],
  14837         soc_genreg,
  14838         1,
  14839         0,
  14840         0x33020000,
  14841         SOC_REG_FLAG_RO,
  14842         0,
  14843         1,
  14844         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14846         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14847         -1,
  14848         -1,
  14849         0,
  14850     },
  14851 #endif /* chips */
  14852 
  14853 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  14854     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_PIPE1r */
  14855         soc_block_list[5],
  14856         soc_genreg,
  14857         1,
  14858         0,
  14859         0x33020000,
  14860         SOC_REG_FLAG_RO |
  14861                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14862         0,
  14863         1,
  14864         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14866         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14867         -1,
  14868         -1,
  14869         0,
  14870     },
  14871 #endif /* chips */
  14872 
  14873 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  14874     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_PIPE2r */
  14875         soc_block_list[5],
  14876         soc_genreg,
  14877         1,
  14878         0,
  14879         0x33020000,
  14880         SOC_REG_FLAG_RO |
  14881                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14882         0,
  14883         1,
  14884         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14886         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14887         -1,
  14888         -1,
  14889         0,
  14890     },
  14891 #endif /* chips */
  14892 
  14893 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  14894     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_PIPE3r */
  14895         soc_block_list[5],
  14896         soc_genreg,
  14897         1,
  14898         0,
  14899         0x33020000,
  14900         SOC_REG_FLAG_RO |
  14901                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14902         0,
  14903         1,
  14904         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14906         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14907         -1,
  14908         -1,
  14909         0,
  14910     },
  14911 #endif /* chips */
  14912 
  14913 #if defined(BCM_56970_A0)
  14914     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_PIPE0_BCM56970_A0r */
  14915         soc_block_list[5],
  14916         soc_genreg,
  14917         1,
  14918         0,
  14919         0x57020000,
  14920         SOC_REG_FLAG_RO,
  14921         0,
  14922         1,
  14923         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14926         -1,
  14927         -1,
  14928         0,
  14929     },
  14930 #endif /* chips */
  14931 
  14932 #if defined(BCM_56970_A0)
  14933     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_PIPE1_BCM56970_A0r */
  14934         soc_block_list[5],
  14935         soc_genreg,
  14936         1,
  14937         0,
  14938         0x57020000,
  14939         SOC_REG_FLAG_RO |
  14940                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14941         0,
  14942         1,
  14943         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14945         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14946         -1,
  14947         -1,
  14948         0,
  14949     },
  14950 #endif /* chips */
  14951 
  14952 #if defined(BCM_56970_A0)
  14953     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_PIPE2_BCM56970_A0r */
  14954         soc_block_list[5],
  14955         soc_genreg,
  14956         1,
  14957         0,
  14958         0x57020000,
  14959         SOC_REG_FLAG_RO |
  14960                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14961         0,
  14962         1,
  14963         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14965         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14966         -1,
  14967         -1,
  14968         0,
  14969     },
  14970 #endif /* chips */
  14971 
  14972 #if defined(BCM_56970_A0)
  14973     { /* SOC_REG_INT_VLAN_SUBNET_CAM_BIST_STATUS_PIPE3_BCM56970_A0r */
  14974         soc_block_list[5],
  14975         soc_genreg,
  14976         1,
  14977         0,
  14978         0x57020000,
  14979         SOC_REG_FLAG_RO |
  14980                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  14981         0,
  14982         1,
  14983         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  14984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14985         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14986         -1,
  14987         -1,
  14988         0,
  14989     },
  14990 #endif /* chips */
  14991 
  14992 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  14993     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  14994     { /* SOC_REG_INT_VLAN_SUBNET_CAM_CONTROLr */
  14995         soc_block_list[5],
  14996         soc_genreg,
  14997         1,
  14998         0,
  14999         0x4080000,
  15000         0,
  15001         0,
  15002         3,
  15003         soc_VLAN_SUBNET_CAM_CONTROLr_fields,
  15004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15006         -1,
  15007         -1,
  15008     },
  15009 #endif /* chips */
  15010 
  15011 #if defined(BCM_56800_A0)
  15012     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRLr */
  15013         soc_block_list[5],
  15014         soc_genreg,
  15015         1,
  15016         0,
  15017         0x4080c00,
  15018         0,
  15019         0,
  15020         3,
  15021         soc_VLAN_SUBNET_CAM_DBGCTRLr_fields,
  15022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15023         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15024         -1,
  15025         -1,
  15026     },
  15027 #endif /* chips */
  15028 
  15029 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15030     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15031     defined(BCM_56160_A0)
  15032     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM53400_A0r */
  15033         soc_block_list[5],
  15034         soc_genreg,
  15035         1,
  15036         0,
  15037         0xe010200,
  15038         0,
  15039         0,
  15040         3,
  15041         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM53400_A0r_fields,
  15042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15043         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15044         -1,
  15045         -1,
  15046     },
  15047 #endif /* chips */
  15048 
  15049 #if defined(BCM_56150_A0)
  15050     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56150_A0r */
  15051         soc_block_list[5],
  15052         soc_genreg,
  15053         1,
  15054         0,
  15055         0x12010200,
  15056         0,
  15057         0,
  15058         3,
  15059         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56640_A0r_fields,
  15060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15061         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15062         -1,
  15063         -1,
  15064     },
  15065 #endif /* chips */
  15066 
  15067 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  15068     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56260_A0r */
  15069         soc_block_list[5],
  15070         soc_genreg,
  15071         1,
  15072         0,
  15073         0x12010000,
  15074         0,
  15075         0,
  15076         3,
  15077         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56260_A0r_fields,
  15078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15079         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15080         -1,
  15081         -1,
  15082     },
  15083 #endif /* chips */
  15084 
  15085 #if defined(BCM_56270_A0)
  15086     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56270_A0r */
  15087         soc_block_list[5],
  15088         soc_genreg,
  15089         1,
  15090         0,
  15091         0x12010000,
  15092         0,
  15093         0,
  15094         3,
  15095         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM53400_A0r_fields,
  15096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15097         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15098         -1,
  15099         -1,
  15100     },
  15101 #endif /* chips */
  15102 
  15103 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  15104     defined(BCM_56334_B0)
  15105     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56334_A0r */
  15106         soc_block_list[5],
  15107         soc_genreg,
  15108         1,
  15109         0,
  15110         0x4080111,
  15111         0,
  15112         0,
  15113         3,
  15114         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56334_A0r_fields,
  15115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15116         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15117         -1,
  15118         -1,
  15119     },
  15120 #endif /* chips */
  15121 
  15122 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  15123     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56560_A0r */
  15124         soc_block_list[5],
  15125         soc_genreg,
  15126         1,
  15127         0,
  15128         0x13010000,
  15129         0,
  15130         0,
  15131         3,
  15132         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM53400_A0r_fields,
  15133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15134         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15135         -1,
  15136         -1,
  15137     },
  15138 #endif /* chips */
  15139 
  15140 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  15141     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  15142     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56624_A0r */
  15143         soc_block_list[5],
  15144         soc_genreg,
  15145         1,
  15146         0,
  15147         0x4080109,
  15148         0,
  15149         0,
  15150         3,
  15151         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56624_A0r_fields,
  15152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15153         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15154         -1,
  15155         -1,
  15156     },
  15157 #endif /* chips */
  15158 
  15159 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  15160     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  15161     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  15162     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56634_A0r */
  15163         soc_block_list[5],
  15164         soc_genreg,
  15165         1,
  15166         0,
  15167         0x4080135,
  15168         0,
  15169         0,
  15170         3,
  15171         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56624_A0r_fields,
  15172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15174         -1,
  15175         -1,
  15176     },
  15177 #endif /* chips */
  15178 
  15179 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  15180     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  15181     defined(BCM_56640_A0)
  15182     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56640_A0r */
  15183         soc_block_list[5],
  15184         soc_genreg,
  15185         1,
  15186         0,
  15187         0x12010000,
  15188         0,
  15189         0,
  15190         3,
  15191         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56640_A0r_fields,
  15192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15193         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15194         -1,
  15195         -1,
  15196     },
  15197 #endif /* chips */
  15198 
  15199 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  15200     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56670_A0r */
  15201         soc_block_list[5],
  15202         soc_genreg,
  15203         1,
  15204         0,
  15205         0x13020000,
  15206         0,
  15207         0,
  15208         3,
  15209         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM53400_A0r_fields,
  15210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15211         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15212         -1,
  15213         -1,
  15214     },
  15215 #endif /* chips */
  15216 
  15217 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  15218     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56820_A0r */
  15219         soc_block_list[5],
  15220         soc_genreg,
  15221         1,
  15222         0,
  15223         0x4080c40,
  15224         0,
  15225         0,
  15226         2,
  15227         soc_CBPCELLHDRMEMDEBUG_BCM56820_A0r_fields,
  15228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15229         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15230         -1,
  15231         -1,
  15232     },
  15233 #endif /* chips */
  15234 
  15235 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  15236     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  15237     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56840_A0r */
  15238         soc_block_list[5],
  15239         soc_genreg,
  15240         1,
  15241         0,
  15242         0x4080d02,
  15243         0,
  15244         0,
  15245         3,
  15246         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56840_A0r_fields,
  15247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15248         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15249         -1,
  15250         -1,
  15251     },
  15252 #endif /* chips */
  15253 
  15254 #if defined(BCM_56850_A0)
  15255     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56850_A0r */
  15256         soc_block_list[5],
  15257         soc_genreg,
  15258         1,
  15259         0,
  15260         0x13010000,
  15261         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15262         0,
  15263         3,
  15264         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56640_A0r_fields,
  15265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15266         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15267         -1,
  15268         -1,
  15269     },
  15270 #endif /* chips */
  15271 
  15272 #if defined(BCM_56860_A0)
  15273     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56860_A0r */
  15274         soc_block_list[5],
  15275         soc_genreg,
  15276         1,
  15277         0,
  15278         0x13010000,
  15279         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15280         0,
  15281         3,
  15282         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56860_A0r_fields,
  15283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15284         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15285         -1,
  15286         -1,
  15287     },
  15288 #endif /* chips */
  15289 
  15290 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  15291     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56960_A0r */
  15292         soc_block_list[5],
  15293         soc_genreg,
  15294         1,
  15295         0,
  15296         0x33010000,
  15297         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15298         0,
  15299         5,
  15300         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56960_A0r_fields,
  15301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15302         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15303         -1,
  15304         -1,
  15305         0,
  15306     },
  15307 #endif /* chips */
  15308 
  15309 #if defined(BCM_56970_A0)
  15310     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_BCM56970_A0r */
  15311         soc_block_list[5],
  15312         soc_genreg,
  15313         1,
  15314         0,
  15315         0x57010000,
  15316         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15317         0,
  15318         8,
  15319         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56970_A0r_fields,
  15320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15321         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15322         -1,
  15323         -1,
  15324         0,
  15325     },
  15326 #endif /* chips */
  15327 
  15328 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  15329     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_PIPE0r */
  15330         soc_block_list[5],
  15331         soc_genreg,
  15332         1,
  15333         0,
  15334         0x33010000,
  15335         0,
  15336         0,
  15337         5,
  15338         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56960_A0r_fields,
  15339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15340         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15341         -1,
  15342         -1,
  15343         0,
  15344     },
  15345 #endif /* chips */
  15346 
  15347 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  15348     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_PIPE1r */
  15349         soc_block_list[5],
  15350         soc_genreg,
  15351         1,
  15352         0,
  15353         0x33010000,
  15354         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15355         0,
  15356         5,
  15357         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56960_A0r_fields,
  15358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15359         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15360         -1,
  15361         -1,
  15362         0,
  15363     },
  15364 #endif /* chips */
  15365 
  15366 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  15367     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_PIPE2r */
  15368         soc_block_list[5],
  15369         soc_genreg,
  15370         1,
  15371         0,
  15372         0x33010000,
  15373         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15374         0,
  15375         5,
  15376         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56960_A0r_fields,
  15377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15378         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15379         -1,
  15380         -1,
  15381         0,
  15382     },
  15383 #endif /* chips */
  15384 
  15385 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  15386     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_PIPE3r */
  15387         soc_block_list[5],
  15388         soc_genreg,
  15389         1,
  15390         0,
  15391         0x33010000,
  15392         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15393         0,
  15394         5,
  15395         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56960_A0r_fields,
  15396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15397         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15398         -1,
  15399         -1,
  15400         0,
  15401     },
  15402 #endif /* chips */
  15403 
  15404 #if defined(BCM_56970_A0)
  15405     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_PIPE0_BCM56970_A0r */
  15406         soc_block_list[5],
  15407         soc_genreg,
  15408         1,
  15409         0,
  15410         0x57010000,
  15411         0,
  15412         0,
  15413         8,
  15414         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56970_A0r_fields,
  15415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15416         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15417         -1,
  15418         -1,
  15419         0,
  15420     },
  15421 #endif /* chips */
  15422 
  15423 #if defined(BCM_56970_A0)
  15424     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_PIPE1_BCM56970_A0r */
  15425         soc_block_list[5],
  15426         soc_genreg,
  15427         1,
  15428         0,
  15429         0x57010000,
  15430         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15431         0,
  15432         8,
  15433         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56970_A0r_fields,
  15434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15435         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15436         -1,
  15437         -1,
  15438         0,
  15439     },
  15440 #endif /* chips */
  15441 
  15442 #if defined(BCM_56970_A0)
  15443     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_PIPE2_BCM56970_A0r */
  15444         soc_block_list[5],
  15445         soc_genreg,
  15446         1,
  15447         0,
  15448         0x57010000,
  15449         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15450         0,
  15451         8,
  15452         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56970_A0r_fields,
  15453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15454         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15455         -1,
  15456         -1,
  15457         0,
  15458     },
  15459 #endif /* chips */
  15460 
  15461 #if defined(BCM_56970_A0)
  15462     { /* SOC_REG_INT_VLAN_SUBNET_CAM_DBGCTRL_PIPE3_BCM56970_A0r */
  15463         soc_block_list[5],
  15464         soc_genreg,
  15465         1,
  15466         0,
  15467         0x57010000,
  15468         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15469         0,
  15470         8,
  15471         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56970_A0r_fields,
  15472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15473         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15474         -1,
  15475         -1,
  15476         0,
  15477     },
  15478 #endif /* chips */
  15479 
  15480 #if defined(BCM_56800_A0)
  15481     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRLr */
  15482         soc_block_list[5],
  15483         soc_genreg,
  15484         1,
  15485         0,
  15486         0x4080c10,
  15487         0,
  15488         0,
  15489         1,
  15490         soc_CFAPMEMDEBUGr_fields,
  15491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15492         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15493         -1,
  15494         -1,
  15495     },
  15496 #endif /* chips */
  15497 
  15498 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15499     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15500     defined(BCM_56160_A0)
  15501     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM53400_A0r */
  15502         soc_block_list[5],
  15503         soc_genreg,
  15504         1,
  15505         0,
  15506         0xe010600,
  15507         0,
  15508         0,
  15509         1,
  15510         soc_DSCP_CONTROLr_fields,
  15511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15512         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15513         -1,
  15514         -1,
  15515     },
  15516 #endif /* chips */
  15517 
  15518 #if defined(BCM_56150_A0)
  15519     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56150_A0r */
  15520         soc_block_list[5],
  15521         soc_genreg,
  15522         1,
  15523         0,
  15524         0x12010600,
  15525         0,
  15526         0,
  15527         1,
  15528         soc_INTFO_QCN_SRAM_TMr_fields,
  15529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15530         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15531         -1,
  15532         -1,
  15533     },
  15534 #endif /* chips */
  15535 
  15536 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  15537     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56260_A0r */
  15538         soc_block_list[5],
  15539         soc_genreg,
  15540         1,
  15541         0,
  15542         0x12010400,
  15543         0,
  15544         0,
  15545         1,
  15546         soc_VFP_CAM_CONTROL_TM_7_THRU_0r_fields,
  15547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15548         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15549         -1,
  15550         -1,
  15551     },
  15552 #endif /* chips */
  15553 
  15554 #if defined(BCM_56270_A0)
  15555     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56270_A0r */
  15556         soc_block_list[5],
  15557         soc_genreg,
  15558         1,
  15559         0,
  15560         0x12010400,
  15561         0,
  15562         0,
  15563         1,
  15564         soc_E2EFC_MEM_TMr_fields,
  15565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15566         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15567         -1,
  15568         -1,
  15569     },
  15570 #endif /* chips */
  15571 
  15572 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  15573     defined(BCM_56334_B0)
  15574     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56334_A0r */
  15575         soc_block_list[5],
  15576         soc_genreg,
  15577         1,
  15578         0,
  15579         0x4080115,
  15580         0,
  15581         0,
  15582         1,
  15583         soc_CFAPMEMDEBUGr_fields,
  15584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15585         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15586         -1,
  15587         -1,
  15588     },
  15589 #endif /* chips */
  15590 
  15591 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  15592     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56560_A0r */
  15593         soc_block_list[5],
  15594         soc_genreg,
  15595         1,
  15596         0,
  15597         0x13050000,
  15598         0,
  15599         0,
  15600         1,
  15601         soc_DSCP_CONTROLr_fields,
  15602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15603         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15604         -1,
  15605         -1,
  15606     },
  15607 #endif /* chips */
  15608 
  15609 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  15610     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  15611     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56624_A0r */
  15612         soc_block_list[5],
  15613         soc_genreg,
  15614         1,
  15615         0,
  15616         0x408010d,
  15617         0,
  15618         0,
  15619         1,
  15620         soc_CFAPMEMDEBUGr_fields,
  15621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15622         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15623         -1,
  15624         -1,
  15625     },
  15626 #endif /* chips */
  15627 
  15628 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  15629     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  15630     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  15631     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56634_A0r */
  15632         soc_block_list[5],
  15633         soc_genreg,
  15634         1,
  15635         0,
  15636         0x4080139,
  15637         0,
  15638         0,
  15639         1,
  15640         soc_CFAPMEMDEBUGr_fields,
  15641         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15642         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15643         -1,
  15644         -1,
  15645     },
  15646 #endif /* chips */
  15647 
  15648 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  15649     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  15650     defined(BCM_56640_A0)
  15651     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56640_A0r */
  15652         soc_block_list[5],
  15653         soc_genreg,
  15654         1,
  15655         0,
  15656         0x12010400,
  15657         0,
  15658         0,
  15659         2,
  15660         soc_IFP_ING_DVP_2_CONTROL_BCM56640_A0r_fields,
  15661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15662         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15663         -1,
  15664         -1,
  15665     },
  15666 #endif /* chips */
  15667 
  15668 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  15669     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56820_A0r */
  15670         soc_block_list[5],
  15671         soc_genreg,
  15672         1,
  15673         0,
  15674         0x4080c41,
  15675         0,
  15676         0,
  15677         2,
  15678         soc_CFAPMEMDEBUG_BCM56820_A0r_fields,
  15679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15680         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15681         -1,
  15682         -1,
  15683     },
  15684 #endif /* chips */
  15685 
  15686 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  15687     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  15688     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56840_A0r */
  15689         soc_block_list[5],
  15690         soc_genreg,
  15691         1,
  15692         0,
  15693         0x4080d06,
  15694         0,
  15695         0,
  15696         2,
  15697         soc_IFP_ING_DVP_2_CONTROLr_fields,
  15698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15699         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15700         -1,
  15701         -1,
  15702     },
  15703 #endif /* chips */
  15704 
  15705 #if defined(BCM_56850_A0)
  15706     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56850_A0r */
  15707         soc_block_list[5],
  15708         soc_genreg,
  15709         1,
  15710         0,
  15711         0x13050000,
  15712         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15713         0,
  15714         2,
  15715         soc_IFP_ING_DVP_2_CONTROL_BCM56640_A0r_fields,
  15716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15718         -1,
  15719         -1,
  15720     },
  15721 #endif /* chips */
  15722 
  15723 #if defined(BCM_56860_A0)
  15724     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56860_A0r */
  15725         soc_block_list[5],
  15726         soc_genreg,
  15727         1,
  15728         0,
  15729         0x13050000,
  15730         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15731         0,
  15732         1,
  15733         soc_VFP_CAM_CONTROL_SLICE_3_0_BCM56640_A0r_fields,
  15734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15735         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15736         -1,
  15737         -1,
  15738     },
  15739 #endif /* chips */
  15740 
  15741 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  15742     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56960_A0r */
  15743         soc_block_list[5],
  15744         soc_genreg,
  15745         1,
  15746         0,
  15747         0x33050000,
  15748         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15749         0,
  15750         2,
  15751         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  15752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15753         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15754         -1,
  15755         -1,
  15756         0,
  15757     },
  15758 #endif /* chips */
  15759 
  15760 #if defined(BCM_56970_A0)
  15761     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_BCM56970_A0r */
  15762         soc_block_list[5],
  15763         soc_genreg,
  15764         1,
  15765         0,
  15766         0x57050000,
  15767         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15768         0,
  15769         2,
  15770         soc_VLAN_PROTOCOL_DATA_DBGCTRLr_fields,
  15771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15772         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15773         -1,
  15774         -1,
  15775         0,
  15776     },
  15777 #endif /* chips */
  15778 
  15779 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  15780     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_PIPE0r */
  15781         soc_block_list[5],
  15782         soc_genreg,
  15783         1,
  15784         0,
  15785         0x33050000,
  15786         0,
  15787         0,
  15788         2,
  15789         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  15790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15791         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15792         -1,
  15793         -1,
  15794         0,
  15795     },
  15796 #endif /* chips */
  15797 
  15798 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  15799     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_PIPE1r */
  15800         soc_block_list[5],
  15801         soc_genreg,
  15802         1,
  15803         0,
  15804         0x33050000,
  15805         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15806         0,
  15807         2,
  15808         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  15809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15810         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15811         -1,
  15812         -1,
  15813         0,
  15814     },
  15815 #endif /* chips */
  15816 
  15817 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  15818     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_PIPE2r */
  15819         soc_block_list[5],
  15820         soc_genreg,
  15821         1,
  15822         0,
  15823         0x33050000,
  15824         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15825         0,
  15826         2,
  15827         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  15828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15829         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15830         -1,
  15831         -1,
  15832         0,
  15833     },
  15834 #endif /* chips */
  15835 
  15836 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  15837     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_PIPE3r */
  15838         soc_block_list[5],
  15839         soc_genreg,
  15840         1,
  15841         0,
  15842         0x33050000,
  15843         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15844         0,
  15845         2,
  15846         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  15847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15848         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15849         -1,
  15850         -1,
  15851         0,
  15852     },
  15853 #endif /* chips */
  15854 
  15855 #if defined(BCM_56970_A0)
  15856     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_PIPE0_BCM56970_A0r */
  15857         soc_block_list[5],
  15858         soc_genreg,
  15859         1,
  15860         0,
  15861         0x57050000,
  15862         0,
  15863         0,
  15864         2,
  15865         soc_VLAN_PROTOCOL_DATA_DBGCTRLr_fields,
  15866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15867         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15868         -1,
  15869         -1,
  15870         0,
  15871     },
  15872 #endif /* chips */
  15873 
  15874 #if defined(BCM_56970_A0)
  15875     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_PIPE1_BCM56970_A0r */
  15876         soc_block_list[5],
  15877         soc_genreg,
  15878         1,
  15879         0,
  15880         0x57050000,
  15881         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15882         0,
  15883         2,
  15884         soc_VLAN_PROTOCOL_DATA_DBGCTRLr_fields,
  15885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15886         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15887         -1,
  15888         -1,
  15889         0,
  15890     },
  15891 #endif /* chips */
  15892 
  15893 #if defined(BCM_56970_A0)
  15894     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_PIPE2_BCM56970_A0r */
  15895         soc_block_list[5],
  15896         soc_genreg,
  15897         1,
  15898         0,
  15899         0x57050000,
  15900         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15901         0,
  15902         2,
  15903         soc_VLAN_PROTOCOL_DATA_DBGCTRLr_fields,
  15904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15905         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15906         -1,
  15907         -1,
  15908         0,
  15909     },
  15910 #endif /* chips */
  15911 
  15912 #if defined(BCM_56970_A0)
  15913     { /* SOC_REG_INT_VLAN_SUBNET_DATA_DBGCTRL_PIPE3_BCM56970_A0r */
  15914         soc_block_list[5],
  15915         soc_genreg,
  15916         1,
  15917         0,
  15918         0x57050000,
  15919         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  15920         0,
  15921         2,
  15922         soc_VLAN_PROTOCOL_DATA_DBGCTRLr_fields,
  15923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15924         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15925         -1,
  15926         -1,
  15927         0,
  15928     },
  15929 #endif /* chips */
  15930 
  15931 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  15932     defined(BCM_56334_B0)
  15933     { /* SOC_REG_INT_VLAN_SUBNET_DATA_PARITY_CONTROLr */
  15934         soc_block_list[5],
  15935         soc_genreg,
  15936         1,
  15937         0,
  15938         0x408011f,
  15939         0,
  15940         0,
  15941         1,
  15942         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  15943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15944         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  15945         -1,
  15946         -1,
  15947     },
  15948 #endif /* chips */
  15949 
  15950 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15951     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15952     defined(BCM_56160_A0)
  15953     { /* SOC_REG_INT_VLAN_SUBNET_DATA_PARITY_CONTROL_BCM53400_A0r */
  15954         soc_block_list[5],
  15955         soc_genreg,
  15956         1,
  15957         0,
  15958         0xe011200,
  15959         0,
  15960         0,
  15961         1,
  15962         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  15963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15964         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  15965         -1,
  15966         -1,
  15967     },
  15968 #endif /* chips */
  15969 
  15970 #if defined(BCM_56150_A0)
  15971     { /* SOC_REG_INT_VLAN_SUBNET_DATA_PARITY_CONTROL_BCM56150_A0r */
  15972         soc_block_list[5],
  15973         soc_genreg,
  15974         1,
  15975         0,
  15976         0x12010e00,
  15977         0,
  15978         0,
  15979         1,
  15980         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  15981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15982         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  15983         -1,
  15984         -1,
  15985     },
  15986 #endif /* chips */
  15987 
  15988 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  15989     defined(BCM_56334_B0)
  15990     { /* SOC_REG_INT_VLAN_SUBNET_DATA_PARITY_STATUSr */
  15991         soc_block_list[5],
  15992         soc_genreg,
  15993         1,
  15994         0,
  15995         0x4080120,
  15996         0,
  15997         0,
  15998         3,
  15999         soc_CPU_TS_PARITY_STATUS_INTRr_fields,
  16000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16001         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  16002         -1,
  16003         -1,
  16004     },
  16005 #endif /* chips */
  16006 
  16007 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16008     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16009     defined(BCM_56160_A0)
  16010     { /* SOC_REG_INT_VLAN_SUBNET_DATA_PARITY_STATUS_BCM53400_A0r */
  16011         soc_block_list[5],
  16012         soc_genreg,
  16013         1,
  16014         0,
  16015         0xe011300,
  16016         0,
  16017         0,
  16018         3,
  16019         soc_EGR_MOD_MAP_PARITY_STATUSr_fields,
  16020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16021         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  16022         -1,
  16023         -1,
  16024     },
  16025 #endif /* chips */
  16026 
  16027 #if defined(BCM_56150_A0)
  16028     { /* SOC_REG_INT_VLAN_SUBNET_DATA_PARITY_STATUS_BCM56150_A0r */
  16029         soc_block_list[5],
  16030         soc_genreg,
  16031         1,
  16032         0,
  16033         0x12010f00,
  16034         0,
  16035         0,
  16036         3,
  16037         soc_FP_FIELD_SEL_PARITY_STATUS_INTRr_fields,
  16038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16039         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  16040         -1,
  16041         -1,
  16042     },
  16043 #endif /* chips */
  16044 
  16045 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  16046     defined(BCM_56870_A0)
  16047     { /* SOC_REG_INT_VLAN_SUBNET_ONLY_BIST_CONFIG_64r */
  16048         soc_block_list[5],
  16049         soc_genreg,
  16050         1,
  16051         0,
  16052         0x63000000,
  16053         SOC_REG_FLAG_64_BITS |
  16054                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16055         0,
  16056         3,
  16057         soc_IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64r_fields,
  16058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16059         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16060         -1,
  16061         -1,
  16062         3,
  16063     },
  16064 #endif /* chips */
  16065 
  16066 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  16067     defined(BCM_56870_A0)
  16068     { /* SOC_REG_INT_VLAN_SUBNET_ONLY_BIST_CONFIG_64_PIPE0r */
  16069         soc_block_list[5],
  16070         soc_genreg,
  16071         1,
  16072         0,
  16073         0x63000000,
  16074         SOC_REG_FLAG_64_BITS,
  16075         0,
  16076         3,
  16077         soc_IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64r_fields,
  16078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16079         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16080         -1,
  16081         -1,
  16082         3,
  16083     },
  16084 #endif /* chips */
  16085 
  16086 #if defined(BCM_56870_A0)
  16087     { /* SOC_REG_INT_VLAN_SUBNET_ONLY_BIST_CONFIG_64_PIPE1r */
  16088         soc_block_list[5],
  16089         soc_genreg,
  16090         1,
  16091         0,
  16092         0x63000000,
  16093         SOC_REG_FLAG_64_BITS |
  16094                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16095         0,
  16096         3,
  16097         soc_IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64r_fields,
  16098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16099         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16100         -1,
  16101         -1,
  16102         3,
  16103     },
  16104 #endif /* chips */
  16105 
  16106 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  16107     defined(BCM_56870_A0)
  16108     { /* SOC_REG_INT_VLAN_SUBNET_ONLY_BIST_STATUSr */
  16109         soc_block_list[5],
  16110         soc_genreg,
  16111         1,
  16112         0,
  16113         0x63010000,
  16114         SOC_REG_FLAG_RO |
  16115                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16116         0,
  16117         1,
  16118         soc_SUBPORT_TAG_SGPP_MAP_CAM_BIST_STATUS_BCM56560_A0r_fields,
  16119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16120         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16121         -1,
  16122         -1,
  16123         3,
  16124     },
  16125 #endif /* chips */
  16126 
  16127 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  16128     defined(BCM_56870_A0)
  16129     { /* SOC_REG_INT_VLAN_SUBNET_ONLY_BIST_STATUS_PIPE0r */
  16130         soc_block_list[5],
  16131         soc_genreg,
  16132         1,
  16133         0,
  16134         0x63010000,
  16135         SOC_REG_FLAG_RO,
  16136         0,
  16137         1,
  16138         soc_SUBPORT_TAG_SGPP_MAP_CAM_BIST_STATUS_BCM56560_A0r_fields,
  16139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16140         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16141         -1,
  16142         -1,
  16143         3,
  16144     },
  16145 #endif /* chips */
  16146 
  16147 #if defined(BCM_56870_A0)
  16148     { /* SOC_REG_INT_VLAN_SUBNET_ONLY_BIST_STATUS_PIPE1r */
  16149         soc_block_list[5],
  16150         soc_genreg,
  16151         1,
  16152         0,
  16153         0x63010000,
  16154         SOC_REG_FLAG_RO |
  16155                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  16156         0,
  16157         1,
  16158         soc_SUBPORT_TAG_SGPP_MAP_CAM_BIST_STATUS_BCM56560_A0r_fields,
  16159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16160         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16161         -1,
  16162         -1,
  16163         3,
  16164     },
  16165 #endif /* chips */
  16166 
  16167 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  16168     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  16169     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  16170     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_CONTROLr */
  16171         soc_block_list[5],
  16172         soc_genreg,
  16173         1,
  16174         0,
  16175         0x408014f,
  16176         0,
  16177         0,
  16178         1,
  16179         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  16180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16181         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  16182         -1,
  16183         -1,
  16184     },
  16185 #endif /* chips */
  16186 
  16187 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  16188     defined(BCM_56270_A0)
  16189     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_CONTROL_BCM56260_A0r */
  16190         soc_block_list[5],
  16191         soc_genreg,
  16192         1,
  16193         0,
  16194         0x12011f00,
  16195         0,
  16196         0,
  16197         1,
  16198         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  16199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16200         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16201         -1,
  16202         -1,
  16203     },
  16204 #endif /* chips */
  16205 
  16206 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16207     defined(BCM_56450_B1)
  16208     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_CONTROL_BCM56450_A0r */
  16209         soc_block_list[5],
  16210         soc_genreg,
  16211         1,
  16212         0,
  16213         0x12011e00,
  16214         0,
  16215         0,
  16216         1,
  16217         soc_FT_CNTR_SER_CONTROLr_fields,
  16218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16219         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16220         -1,
  16221         -1,
  16222     },
  16223 #endif /* chips */
  16224 
  16225 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  16226     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  16227     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_CONTROL_BCM56840_A0r */
  16228         soc_block_list[5],
  16229         soc_genreg,
  16230         1,
  16231         0,
  16232         0x4080d1d,
  16233         0,
  16234         0,
  16235         1,
  16236         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  16237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16238         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16239         -1,
  16240         -1,
  16241     },
  16242 #endif /* chips */
  16243 
  16244 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  16245     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  16246     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  16247     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_STATUS_INTRr */
  16248         soc_block_list[5],
  16249         soc_genreg,
  16250         1,
  16251         0,
  16252         0x4080150,
  16253         0,
  16254         0,
  16255         3,
  16256         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_STATUSr_fields,
  16257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16258         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  16259         -1,
  16260         -1,
  16261     },
  16262 #endif /* chips */
  16263 
  16264 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  16265     defined(BCM_56270_A0)
  16266     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_STATUS_INTR_BCM56260_A0r */
  16267         soc_block_list[5],
  16268         soc_genreg,
  16269         1,
  16270         0,
  16271         0x12012000,
  16272         0,
  16273         0,
  16274         4,
  16275         soc_VLAN_SUBNET_PARITY_STATUS_INTR_BCM56260_A0r_fields,
  16276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16277         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16278         -1,
  16279         -1,
  16280     },
  16281 #endif /* chips */
  16282 
  16283 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  16284     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_STATUS_INTR_BCM56440_A0r */
  16285         soc_block_list[5],
  16286         soc_genreg,
  16287         1,
  16288         0,
  16289         0x4080d1e,
  16290         0,
  16291         0,
  16292         4,
  16293         soc_VLAN_SUBNET_PARITY_STATUS_INTRr_fields,
  16294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16295         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16296         -1,
  16297         -1,
  16298     },
  16299 #endif /* chips */
  16300 
  16301 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16302     defined(BCM_56450_B1)
  16303     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_STATUS_INTR_BCM56450_A0r */
  16304         soc_block_list[5],
  16305         soc_genreg,
  16306         1,
  16307         0,
  16308         0x12011f00,
  16309         0,
  16310         0,
  16311         4,
  16312         soc_VLAN_SUBNET_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  16313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16314         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16315         -1,
  16316         -1,
  16317     },
  16318 #endif /* chips */
  16319 
  16320 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  16321     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_STATUS_INTR_BCM56840_A0r */
  16322         soc_block_list[5],
  16323         soc_genreg,
  16324         1,
  16325         0,
  16326         0x4080d1e,
  16327         0,
  16328         0,
  16329         3,
  16330         soc_EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr_fields,
  16331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16332         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16333         -1,
  16334         -1,
  16335     },
  16336 #endif /* chips */
  16337 
  16338 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  16339     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  16340     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  16341     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_STATUS_NACKr */
  16342         soc_block_list[5],
  16343         soc_genreg,
  16344         1,
  16345         0,
  16346         0x4080151,
  16347         0,
  16348         0,
  16349         3,
  16350         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_STATUSr_fields,
  16351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16352         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  16353         -1,
  16354         -1,
  16355     },
  16356 #endif /* chips */
  16357 
  16358 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  16359     defined(BCM_56270_A0)
  16360     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_STATUS_NACK_BCM56260_A0r */
  16361         soc_block_list[5],
  16362         soc_genreg,
  16363         1,
  16364         0,
  16365         0x12012100,
  16366         0,
  16367         0,
  16368         4,
  16369         soc_VLAN_SUBNET_PARITY_STATUS_INTR_BCM56260_A0r_fields,
  16370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16372         -1,
  16373         -1,
  16374     },
  16375 #endif /* chips */
  16376 
  16377 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  16378     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_STATUS_NACK_BCM56440_A0r */
  16379         soc_block_list[5],
  16380         soc_genreg,
  16381         1,
  16382         0,
  16383         0x4080d1f,
  16384         0,
  16385         0,
  16386         4,
  16387         soc_VLAN_SUBNET_PARITY_STATUS_INTRr_fields,
  16388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16389         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16390         -1,
  16391         -1,
  16392     },
  16393 #endif /* chips */
  16394 
  16395 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16396     defined(BCM_56450_B1)
  16397     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_STATUS_NACK_BCM56450_A0r */
  16398         soc_block_list[5],
  16399         soc_genreg,
  16400         1,
  16401         0,
  16402         0x12012000,
  16403         0,
  16404         0,
  16405         4,
  16406         soc_VLAN_SUBNET_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  16407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16408         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16409         -1,
  16410         -1,
  16411     },
  16412 #endif /* chips */
  16413 
  16414 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  16415     { /* SOC_REG_INT_VLAN_SUBNET_PARITY_STATUS_NACK_BCM56840_A0r */
  16416         soc_block_list[5],
  16417         soc_genreg,
  16418         1,
  16419         0,
  16420         0x4080d1f,
  16421         0,
  16422         0,
  16423         3,
  16424         soc_EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr_fields,
  16425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16426         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16427         -1,
  16428         -1,
  16429     },
  16430 #endif /* chips */
  16431 
  16432 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  16433     { /* SOC_REG_INT_VLAN_TAG_ACTION_PROFILE_DBGCTRLr */
  16434         soc_block_list[5],
  16435         soc_genreg,
  16436         1,
  16437         0,
  16438         0x12010500,
  16439         0,
  16440         0,
  16441         2,
  16442         soc_IFP_ING_DVP_2_CONTROL_BCM56640_A0r_fields,
  16443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16444         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16445         -1,
  16446         -1,
  16447     },
  16448 #endif /* chips */
  16449 
  16450 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  16451     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  16452     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_CONFIGr */
  16453         soc_block_list[5],
  16454         soc_genreg,
  16455         1,
  16456         0,
  16457         0x4080008,
  16458         0,
  16459         0,
  16460         2,
  16461         soc_FP_CAM_BIST_CONFIGr_fields,
  16462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16463         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16464         -1,
  16465         -1,
  16466     },
  16467 #endif /* chips */
  16468 
  16469 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  16470     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  16471     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_CONTROLr */
  16472         soc_block_list[5],
  16473         soc_genreg,
  16474         1,
  16475         0,
  16476         0x4080006,
  16477         0,
  16478         0,
  16479         2,
  16480         soc_CPU_COS_CAM_DBGCTRLr_fields,
  16481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16482         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16483         -1,
  16484         -1,
  16485     },
  16486 #endif /* chips */
  16487 
  16488 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  16489     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  16490     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_DBG_DATAr */
  16491         soc_block_list[5],
  16492         soc_genreg,
  16493         1,
  16494         0,
  16495         0x408000b,
  16496         0,
  16497         0,
  16498         1,
  16499         soc_L2_USER_ENTRY_CAM_BIST_DBG_DATAr_fields,
  16500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16501         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16502         -1,
  16503         -1,
  16504     },
  16505 #endif /* chips */
  16506 
  16507 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  16508     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  16509     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_DEBUG_DATA_VALIDr */
  16510         soc_block_list[5],
  16511         soc_genreg,
  16512         1,
  16513         0,
  16514         0x408000a,
  16515         0,
  16516         0,
  16517         1,
  16518         soc_FP_CAM_BIST_DBG_DATA_VALIDr_fields,
  16519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16520         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16521         -1,
  16522         -1,
  16523     },
  16524 #endif /* chips */
  16525 
  16526 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  16527     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  16528     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_DEBUG_SENDr */
  16529         soc_block_list[5],
  16530         soc_genreg,
  16531         1,
  16532         0,
  16533         0x4080009,
  16534         0,
  16535         0,
  16536         1,
  16537         soc_VLAN_SUBNET_CAM_BIST_DEBUG_SENDr_fields,
  16538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16540         -1,
  16541         -1,
  16542     },
  16543 #endif /* chips */
  16544 
  16545 #if defined(BCM_56800_A0)
  16546     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S10_STATUSr */
  16547         soc_block_list[5],
  16548         soc_genreg,
  16549         1,
  16550         0,
  16551         0x4080c0f,
  16552         SOC_REG_FLAG_RO,
  16553         0,
  16554         2,
  16555         soc_EGR_VXLT_CAM_BIST_S8_STATUSr_fields,
  16556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16558         -1,
  16559         -1,
  16560     },
  16561 #endif /* chips */
  16562 
  16563 #if defined(BCM_56504_A0)
  16564     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S2_STATUSr */
  16565         soc_block_list[5],
  16566         soc_genreg,
  16567         1,
  16568         0,
  16569         0x408000a,
  16570         SOC_REG_FLAG_RO,
  16571         0,
  16572         3,
  16573         soc_EGR_VXLT_CAM_BIST_S2_STATUSr_fields,
  16574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16575         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16576         -1,
  16577         -1,
  16578     },
  16579 #endif /* chips */
  16580 
  16581 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  16582     defined(BCM_56514_A0)
  16583     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S2_STATUS_BCM56504_B0r */
  16584         soc_block_list[5],
  16585         soc_genreg,
  16586         1,
  16587         0,
  16588         0x408000a,
  16589         SOC_REG_FLAG_RO,
  16590         0,
  16591         1,
  16592         soc_EGR_VXLT_CAM_BIST_S2_STATUS_BCM56504_B0r_fields,
  16593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16594         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16595         -1,
  16596         -1,
  16597     },
  16598 #endif /* chips */
  16599 
  16600 #if defined(BCM_56800_A0)
  16601     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S2_STATUS_BCM56800_A0r */
  16602         soc_block_list[5],
  16603         soc_genreg,
  16604         1,
  16605         0,
  16606         0x4080c0a,
  16607         SOC_REG_FLAG_RO,
  16608         0,
  16609         3,
  16610         soc_EGR_VXLT_CAM_BIST_S2_STATUSr_fields,
  16611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16613         -1,
  16614         -1,
  16615     },
  16616 #endif /* chips */
  16617 
  16618 #if defined(BCM_56504_A0)
  16619     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S3_STATUSr */
  16620         soc_block_list[5],
  16621         soc_genreg,
  16622         1,
  16623         0,
  16624         0x408000b,
  16625         SOC_REG_FLAG_RO,
  16626         0,
  16627         4,
  16628         soc_EGR_VXLT_CAM_BIST_S3_STATUSr_fields,
  16629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16630         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16631         -1,
  16632         -1,
  16633     },
  16634 #endif /* chips */
  16635 
  16636 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  16637     defined(BCM_56514_A0)
  16638     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S3_STATUS_BCM56504_B0r */
  16639         soc_block_list[5],
  16640         soc_genreg,
  16641         1,
  16642         0,
  16643         0x408000b,
  16644         SOC_REG_FLAG_RO,
  16645         0,
  16646         1,
  16647         soc_EGR_VXLT_CAM_BIST_S3_STATUS_BCM56504_B0r_fields,
  16648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16649         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16650         -1,
  16651         -1,
  16652     },
  16653 #endif /* chips */
  16654 
  16655 #if defined(BCM_56800_A0)
  16656     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S3_STATUS_BCM56800_A0r */
  16657         soc_block_list[5],
  16658         soc_genreg,
  16659         1,
  16660         0,
  16661         0x4080c0b,
  16662         SOC_REG_FLAG_RO,
  16663         0,
  16664         4,
  16665         soc_EGR_VXLT_CAM_BIST_S3_STATUSr_fields,
  16666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16667         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16668         -1,
  16669         -1,
  16670     },
  16671 #endif /* chips */
  16672 
  16673 #if defined(BCM_56504_A0)
  16674     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S5_STATUSr */
  16675         soc_block_list[5],
  16676         soc_genreg,
  16677         1,
  16678         0,
  16679         0x408000c,
  16680         SOC_REG_FLAG_RO,
  16681         0,
  16682         3,
  16683         soc_EGR_VXLT_CAM_BIST_S2_STATUSr_fields,
  16684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16685         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16686         -1,
  16687         -1,
  16688     },
  16689 #endif /* chips */
  16690 
  16691 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  16692     defined(BCM_56514_A0)
  16693     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S5_STATUS_BCM56504_B0r */
  16694         soc_block_list[5],
  16695         soc_genreg,
  16696         1,
  16697         0,
  16698         0x408000c,
  16699         SOC_REG_FLAG_RO,
  16700         0,
  16701         1,
  16702         soc_EGR_VXLT_CAM_BIST_S5_STATUSr_fields,
  16703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16704         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16705         -1,
  16706         -1,
  16707     },
  16708 #endif /* chips */
  16709 
  16710 #if defined(BCM_56800_A0)
  16711     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S5_STATUS_BCM56800_A0r */
  16712         soc_block_list[5],
  16713         soc_genreg,
  16714         1,
  16715         0,
  16716         0x4080c0c,
  16717         SOC_REG_FLAG_RO,
  16718         0,
  16719         3,
  16720         soc_EGR_VXLT_CAM_BIST_S2_STATUSr_fields,
  16721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16722         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16723         -1,
  16724         -1,
  16725     },
  16726 #endif /* chips */
  16727 
  16728 #if defined(BCM_56504_A0)
  16729     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S6_STATUSr */
  16730         soc_block_list[5],
  16731         soc_genreg,
  16732         1,
  16733         0,
  16734         0x408000d,
  16735         SOC_REG_FLAG_RO,
  16736         0,
  16737         4,
  16738         soc_EGR_VXLT_CAM_BIST_S3_STATUSr_fields,
  16739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16740         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16741         -1,
  16742         -1,
  16743     },
  16744 #endif /* chips */
  16745 
  16746 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  16747     defined(BCM_56514_A0)
  16748     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S6_STATUS_BCM56504_B0r */
  16749         soc_block_list[5],
  16750         soc_genreg,
  16751         1,
  16752         0,
  16753         0x408000d,
  16754         SOC_REG_FLAG_RO,
  16755         0,
  16756         1,
  16757         soc_EGR_VXLT_CAM_BIST_S6_STATUSr_fields,
  16758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16760         -1,
  16761         -1,
  16762     },
  16763 #endif /* chips */
  16764 
  16765 #if defined(BCM_56800_A0)
  16766     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S6_STATUS_BCM56800_A0r */
  16767         soc_block_list[5],
  16768         soc_genreg,
  16769         1,
  16770         0,
  16771         0x4080c0d,
  16772         SOC_REG_FLAG_RO,
  16773         0,
  16774         4,
  16775         soc_EGR_VXLT_CAM_BIST_S3_STATUSr_fields,
  16776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16777         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16778         -1,
  16779         -1,
  16780     },
  16781 #endif /* chips */
  16782 
  16783 #if defined(BCM_56504_A0)
  16784     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S8_STATUSr */
  16785         soc_block_list[5],
  16786         soc_genreg,
  16787         1,
  16788         0,
  16789         0x408000e,
  16790         SOC_REG_FLAG_RO,
  16791         0,
  16792         2,
  16793         soc_EGR_VXLT_CAM_BIST_S8_STATUSr_fields,
  16794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16795         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16796         -1,
  16797         -1,
  16798     },
  16799 #endif /* chips */
  16800 
  16801 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  16802     defined(BCM_56514_A0)
  16803     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S8_STATUS_BCM56504_B0r */
  16804         soc_block_list[5],
  16805         soc_genreg,
  16806         1,
  16807         0,
  16808         0x408000e,
  16809         SOC_REG_FLAG_RO,
  16810         0,
  16811         1,
  16812         soc_EGR_VXLT_CAM_BIST_S8_STATUS_BCM56504_B0r_fields,
  16813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16814         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16815         -1,
  16816         -1,
  16817     },
  16818 #endif /* chips */
  16819 
  16820 #if defined(BCM_56800_A0)
  16821     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_S8_STATUS_BCM56800_A0r */
  16822         soc_block_list[5],
  16823         soc_genreg,
  16824         1,
  16825         0,
  16826         0x4080c0e,
  16827         SOC_REG_FLAG_RO,
  16828         0,
  16829         4,
  16830         soc_EGR_VXLT_CAM_BIST_S3_STATUSr_fields,
  16831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16832         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16833         -1,
  16834         -1,
  16835     },
  16836 #endif /* chips */
  16837 
  16838 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  16839     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  16840     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_STATUSr */
  16841         soc_block_list[5],
  16842         soc_genreg,
  16843         1,
  16844         0,
  16845         0x4080009,
  16846         0,
  16847         0,
  16848         2,
  16849         soc_L2_USER_ENTRY_CAM_BIST_STATUSr_fields,
  16850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16851         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16852         -1,
  16853         -1,
  16854     },
  16855 #endif /* chips */
  16856 
  16857 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  16858     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  16859     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_STATUS_BCM56224_A0r */
  16860         soc_block_list[5],
  16861         soc_genreg,
  16862         1,
  16863         0,
  16864         0x4080007,
  16865         SOC_REG_FLAG_RO,
  16866         0,
  16867         1,
  16868         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  16869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16870         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16871         -1,
  16872         -1,
  16873     },
  16874 #endif /* chips */
  16875 
  16876 #if defined(BCM_56800_A0)
  16877     { /* SOC_REG_INT_VLAN_XLATE_CAM_BIST_STATUS_BCM56800_A0r */
  16878         soc_block_list[5],
  16879         soc_genreg,
  16880         1,
  16881         0,
  16882         0x4080c09,
  16883         0,
  16884         0,
  16885         2,
  16886         soc_L2_USER_ENTRY_CAM_BIST_STATUSr_fields,
  16887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16888         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16889         -1,
  16890         -1,
  16891     },
  16892 #endif /* chips */
  16893 
  16894 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  16895     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  16896     { /* SOC_REG_INT_VLAN_XLATE_CAM_CONTROLr */
  16897         soc_block_list[5],
  16898         soc_genreg,
  16899         1,
  16900         0,
  16901         0x4080008,
  16902         0,
  16903         0,
  16904         2,
  16905         soc_EGR_VXLT_CAM_CONTROLr_fields,
  16906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16907         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16908         -1,
  16909         -1,
  16910     },
  16911 #endif /* chips */
  16912 
  16913 #if defined(BCM_56800_A0)
  16914     { /* SOC_REG_INT_VLAN_XLATE_CAM_DBGCTRLr */
  16915         soc_block_list[5],
  16916         soc_genreg,
  16917         1,
  16918         0,
  16919         0x4080c08,
  16920         0,
  16921         0,
  16922         2,
  16923         soc_EGR_VXLT_CAM_CONTROL_BCM56800_A0r_fields,
  16924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16926         -1,
  16927         -1,
  16928     },
  16929 #endif /* chips */
  16930 
  16931 #if defined(BCM_56800_A0)
  16932     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRLr */
  16933         soc_block_list[5],
  16934         soc_genreg,
  16935         1,
  16936         0,
  16937         0x4080c13,
  16938         0,
  16939         0,
  16940         1,
  16941         soc_CFAPMEMDEBUGr_fields,
  16942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16943         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16944         -1,
  16945         -1,
  16946     },
  16947 #endif /* chips */
  16948 
  16949 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  16950     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  16951     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_0r */
  16952         soc_block_list[5],
  16953         soc_genreg,
  16954         1,
  16955         0,
  16956         0x408010f,
  16957         0,
  16958         0,
  16959         4,
  16960         soc_VLAN_XLATE_DATA_DBGCTRL_0r_fields,
  16961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16962         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16963         -1,
  16964         -1,
  16965     },
  16966 #endif /* chips */
  16967 
  16968 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  16969     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  16970     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_1r */
  16971         soc_block_list[5],
  16972         soc_genreg,
  16973         1,
  16974         0,
  16975         0x4080110,
  16976         0,
  16977         0,
  16978         4,
  16979         soc_VLAN_XLATE_DATA_DBGCTRL_0r_fields,
  16980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16981         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16982         -1,
  16983         -1,
  16984     },
  16985 #endif /* chips */
  16986 
  16987 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  16988     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  16989     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_2r */
  16990         soc_block_list[5],
  16991         soc_genreg,
  16992         1,
  16993         0,
  16994         0x4080d0a,
  16995         0,
  16996         0,
  16997         4,
  16998         soc_VLAN_XLATE_DATA_DBGCTRL_2r_fields,
  16999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17000         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17001         -1,
  17002         -1,
  17003     },
  17004 #endif /* chips */
  17005 
  17006 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  17007     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  17008     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_3r */
  17009         soc_block_list[5],
  17010         soc_genreg,
  17011         1,
  17012         0,
  17013         0x4080d0b,
  17014         0,
  17015         0,
  17016         16,
  17017         soc_VLAN_XLATE_DATA_DBGCTRL_3r_fields,
  17018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17019         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17020         -1,
  17021         -1,
  17022     },
  17023 #endif /* chips */
  17024 
  17025 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17026     defined(BCM_56450_B1)
  17027     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_4r */
  17028         soc_block_list[5],
  17029         soc_genreg,
  17030         1,
  17031         0,
  17032         0x12010900,
  17033         0,
  17034         0,
  17035         3,
  17036         soc_VLAN_XLATE_DATA_DBGCTRL_4r_fields,
  17037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17038         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17039         -1,
  17040         -1,
  17041     },
  17042 #endif /* chips */
  17043 
  17044 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17045     defined(BCM_56450_B1)
  17046     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_5r */
  17047         soc_block_list[5],
  17048         soc_genreg,
  17049         1,
  17050         0,
  17051         0x12010a00,
  17052         0,
  17053         0,
  17054         3,
  17055         soc_VLAN_XLATE_DATA_DBGCTRL_5r_fields,
  17056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17057         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17058         -1,
  17059         -1,
  17060     },
  17061 #endif /* chips */
  17062 
  17063 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17064     defined(BCM_56450_B1)
  17065     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_6r */
  17066         soc_block_list[5],
  17067         soc_genreg,
  17068         1,
  17069         0,
  17070         0x12010b00,
  17071         0,
  17072         0,
  17073         2,
  17074         soc_VLAN_XLATE_DATA_DBGCTRL_6r_fields,
  17075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17076         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17077         -1,
  17078         -1,
  17079     },
  17080 #endif /* chips */
  17081 
  17082 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17083     defined(BCM_56450_B1)
  17084     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_7r */
  17085         soc_block_list[5],
  17086         soc_genreg,
  17087         1,
  17088         0,
  17089         0x12010c00,
  17090         0,
  17091         0,
  17092         16,
  17093         soc_VLAN_XLATE_DATA_DBGCTRL_7r_fields,
  17094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17095         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17096         -1,
  17097         -1,
  17098     },
  17099 #endif /* chips */
  17100 
  17101 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17102     defined(BCM_56160_A0)
  17103     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_0_BCM53400_A0r */
  17104         soc_block_list[5],
  17105         soc_genreg,
  17106         1,
  17107         0,
  17108         0xe010800,
  17109         SOC_REG_FLAG_64_BITS,
  17110         0,
  17111         2,
  17112         soc_VLAN_XLATE_DATA_DBGCTRL_0_BCM53400_A0r_fields,
  17113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17114         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17115         -1,
  17116         -1,
  17117     },
  17118 #endif /* chips */
  17119 
  17120 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17121     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_0_BCM53570_A0r */
  17122         soc_block_list[5],
  17123         soc_genreg,
  17124         1,
  17125         0,
  17126         0xe010800,
  17127         SOC_REG_FLAG_64_BITS,
  17128         0,
  17129         2,
  17130         soc_VLAN_XLATE_DATA_DBGCTRL_0_BCM53570_A0r_fields,
  17131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17132         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17133         -1,
  17134         -1,
  17135     },
  17136 #endif /* chips */
  17137 
  17138 #if defined(BCM_56150_A0)
  17139     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_0_BCM56150_A0r */
  17140         soc_block_list[5],
  17141         soc_genreg,
  17142         1,
  17143         0,
  17144         0x12010800,
  17145         0,
  17146         0,
  17147         2,
  17148         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0r_fields,
  17149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17150         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17151         -1,
  17152         -1,
  17153     },
  17154 #endif /* chips */
  17155 
  17156 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  17157     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_0_BCM56260_A0r */
  17158         soc_block_list[5],
  17159         soc_genreg,
  17160         1,
  17161         0,
  17162         0x12010600,
  17163         0,
  17164         0,
  17165         1,
  17166         soc_VLAN_XLATE_DATA_DBGCTRL_0_BCM56260_A0r_fields,
  17167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17169         -1,
  17170         -1,
  17171     },
  17172 #endif /* chips */
  17173 
  17174 #if defined(BCM_56270_A0)
  17175     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_0_BCM56270_A0r */
  17176         soc_block_list[5],
  17177         soc_genreg,
  17178         1,
  17179         0,
  17180         0x12010600,
  17181         0,
  17182         0,
  17183         1,
  17184         soc_VLAN_XLATE_DATA_DBGCTRL_0_BCM56270_A0r_fields,
  17185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17187         -1,
  17188         -1,
  17189     },
  17190 #endif /* chips */
  17191 
  17192 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  17193     defined(BCM_56334_B0)
  17194     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_0_BCM56334_A0r */
  17195         soc_block_list[5],
  17196         soc_genreg,
  17197         1,
  17198         0,
  17199         0x4080117,
  17200         0,
  17201         0,
  17202         4,
  17203         soc_VLAN_XLATE_DATA_DBGCTRL_0r_fields,
  17204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17205         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17206         -1,
  17207         -1,
  17208     },
  17209 #endif /* chips */
  17210 
  17211 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17212     defined(BCM_56450_B1)
  17213     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_0_BCM56450_A0r */
  17214         soc_block_list[5],
  17215         soc_genreg,
  17216         1,
  17217         0,
  17218         0x12010500,
  17219         0,
  17220         0,
  17221         3,
  17222         soc_IFP_METER_TABLE_TM_SLICE_0_2r_fields,
  17223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17224         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17225         -1,
  17226         -1,
  17227     },
  17228 #endif /* chips */
  17229 
  17230 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  17231     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  17232     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  17233     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_0_BCM56634_A0r */
  17234         soc_block_list[5],
  17235         soc_genreg,
  17236         1,
  17237         0,
  17238         0x408013b,
  17239         0,
  17240         0,
  17241         4,
  17242         soc_VLAN_XLATE_DATA_DBGCTRL_0r_fields,
  17243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17244         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17245         -1,
  17246         -1,
  17247     },
  17248 #endif /* chips */
  17249 
  17250 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  17251     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  17252     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_0_BCM56840_A0r */
  17253         soc_block_list[5],
  17254         soc_genreg,
  17255         1,
  17256         0,
  17257         0x4080d08,
  17258         0,
  17259         0,
  17260         3,
  17261         soc_VLAN_XLATE_DATA_DBGCTRL_0_BCM56840_A0r_fields,
  17262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17264         -1,
  17265         -1,
  17266     },
  17267 #endif /* chips */
  17268 
  17269 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17270     defined(BCM_56160_A0)
  17271     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_1_BCM53400_A0r */
  17272         soc_block_list[5],
  17273         soc_genreg,
  17274         1,
  17275         0,
  17276         0xe010900,
  17277         SOC_REG_FLAG_64_BITS,
  17278         0,
  17279         2,
  17280         soc_VLAN_XLATE_DATA_DBGCTRL_1_BCM53400_A0r_fields,
  17281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17282         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17283         -1,
  17284         -1,
  17285     },
  17286 #endif /* chips */
  17287 
  17288 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17289     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_1_BCM53570_A0r */
  17290         soc_block_list[5],
  17291         soc_genreg,
  17292         1,
  17293         0,
  17294         0xe010900,
  17295         SOC_REG_FLAG_64_BITS,
  17296         0,
  17297         2,
  17298         soc_VLAN_XLATE_DATA_DBGCTRL_1_BCM53570_A0r_fields,
  17299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17300         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17301         -1,
  17302         -1,
  17303     },
  17304 #endif /* chips */
  17305 
  17306 #if defined(BCM_56150_A0)
  17307     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_1_BCM56150_A0r */
  17308         soc_block_list[5],
  17309         soc_genreg,
  17310         1,
  17311         0,
  17312         0x12010900,
  17313         0,
  17314         0,
  17315         2,
  17316         soc_VLAN_XLATE_DATA_DBGCTRL_1_BCM56150_A0r_fields,
  17317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17318         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17319         -1,
  17320         -1,
  17321     },
  17322 #endif /* chips */
  17323 
  17324 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  17325     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_1_BCM56260_A0r */
  17326         soc_block_list[5],
  17327         soc_genreg,
  17328         1,
  17329         0,
  17330         0x12010700,
  17331         0,
  17332         0,
  17333         1,
  17334         soc_VLAN_XLATE_DATA_DBGCTRL_1_BCM56260_A0r_fields,
  17335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17336         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17337         -1,
  17338         -1,
  17339     },
  17340 #endif /* chips */
  17341 
  17342 #if defined(BCM_56270_A0)
  17343     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_1_BCM56270_A0r */
  17344         soc_block_list[5],
  17345         soc_genreg,
  17346         1,
  17347         0,
  17348         0x12010700,
  17349         0,
  17350         0,
  17351         1,
  17352         soc_VLAN_XLATE_DATA_DBGCTRL_1_BCM56270_A0r_fields,
  17353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17354         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17355         -1,
  17356         -1,
  17357     },
  17358 #endif /* chips */
  17359 
  17360 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  17361     defined(BCM_56334_B0)
  17362     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_1_BCM56334_A0r */
  17363         soc_block_list[5],
  17364         soc_genreg,
  17365         1,
  17366         0,
  17367         0x4080118,
  17368         0,
  17369         0,
  17370         4,
  17371         soc_VLAN_XLATE_DATA_DBGCTRL_0r_fields,
  17372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17373         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17374         -1,
  17375         -1,
  17376     },
  17377 #endif /* chips */
  17378 
  17379 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17380     defined(BCM_56450_B1)
  17381     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_1_BCM56450_A0r */
  17382         soc_block_list[5],
  17383         soc_genreg,
  17384         1,
  17385         0,
  17386         0x12010600,
  17387         0,
  17388         0,
  17389         3,
  17390         soc_IFP_METER_TABLE_TM_SLICE_3_5r_fields,
  17391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17392         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17393         -1,
  17394         -1,
  17395     },
  17396 #endif /* chips */
  17397 
  17398 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  17399     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  17400     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  17401     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_1_BCM56634_A0r */
  17402         soc_block_list[5],
  17403         soc_genreg,
  17404         1,
  17405         0,
  17406         0x408013c,
  17407         0,
  17408         0,
  17409         4,
  17410         soc_VLAN_XLATE_DATA_DBGCTRL_0r_fields,
  17411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17412         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17413         -1,
  17414         -1,
  17415     },
  17416 #endif /* chips */
  17417 
  17418 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  17419     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  17420     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_1_BCM56840_A0r */
  17421         soc_block_list[5],
  17422         soc_genreg,
  17423         1,
  17424         0,
  17425         0x4080d09,
  17426         0,
  17427         0,
  17428         3,
  17429         soc_VLAN_XLATE_DATA_DBGCTRL_1r_fields,
  17430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17431         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17432         -1,
  17433         -1,
  17434     },
  17435 #endif /* chips */
  17436 
  17437 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17438     defined(BCM_56160_A0)
  17439     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_2_BCM53400_A0r */
  17440         soc_block_list[5],
  17441         soc_genreg,
  17442         1,
  17443         0,
  17444         0xe010a00,
  17445         SOC_REG_FLAG_64_BITS,
  17446         0,
  17447         2,
  17448         soc_VLAN_XLATE_DATA_DBGCTRL_0_BCM53400_A0r_fields,
  17449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17450         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17451         -1,
  17452         -1,
  17453     },
  17454 #endif /* chips */
  17455 
  17456 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17457     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_2_BCM53570_A0r */
  17458         soc_block_list[5],
  17459         soc_genreg,
  17460         1,
  17461         0,
  17462         0xe010a00,
  17463         SOC_REG_FLAG_64_BITS,
  17464         0,
  17465         2,
  17466         soc_VLAN_XLATE_DATA_DBGCTRL_0_BCM53570_A0r_fields,
  17467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17468         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17469         -1,
  17470         -1,
  17471     },
  17472 #endif /* chips */
  17473 
  17474 #if defined(BCM_56150_A0)
  17475     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_2_BCM56150_A0r */
  17476         soc_block_list[5],
  17477         soc_genreg,
  17478         1,
  17479         0,
  17480         0x12010a00,
  17481         0,
  17482         0,
  17483         2,
  17484         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0r_fields,
  17485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17486         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17487         -1,
  17488         -1,
  17489     },
  17490 #endif /* chips */
  17491 
  17492 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  17493     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_2_BCM56260_A0r */
  17494         soc_block_list[5],
  17495         soc_genreg,
  17496         1,
  17497         0,
  17498         0x12010800,
  17499         0,
  17500         0,
  17501         3,
  17502         soc_VLAN_XLATE_DATA_DBGCTRL_2_BCM56260_A0r_fields,
  17503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17504         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17505         -1,
  17506         -1,
  17507     },
  17508 #endif /* chips */
  17509 
  17510 #if defined(BCM_56270_A0)
  17511     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_2_BCM56270_A0r */
  17512         soc_block_list[5],
  17513         soc_genreg,
  17514         1,
  17515         0,
  17516         0x12010800,
  17517         0,
  17518         0,
  17519         3,
  17520         soc_VLAN_XLATE_DATA_DBGCTRL_2_BCM56270_A0r_fields,
  17521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17522         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17523         -1,
  17524         -1,
  17525     },
  17526 #endif /* chips */
  17527 
  17528 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17529     defined(BCM_56450_B1)
  17530     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_2_BCM56450_A0r */
  17531         soc_block_list[5],
  17532         soc_genreg,
  17533         1,
  17534         0,
  17535         0x12010700,
  17536         0,
  17537         0,
  17538         2,
  17539         soc_VLAN_XLATE_DATA_DBGCTRL_2_BCM56450_A0r_fields,
  17540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17541         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17542         -1,
  17543         -1,
  17544     },
  17545 #endif /* chips */
  17546 
  17547 #if defined(BCM_56850_A0)
  17548     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_2_BCM56850_A0r */
  17549         soc_block_list[5],
  17550         soc_genreg,
  17551         1,
  17552         0,
  17553         0x13070000,
  17554         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17555         0,
  17556         5,
  17557         soc_ING_DNAT_ADDRESS_TYPE_B0_PDAr_fields,
  17558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17559         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17560         -1,
  17561         -1,
  17562     },
  17563 #endif /* chips */
  17564 
  17565 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17566     defined(BCM_56160_A0)
  17567     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_3_BCM53400_A0r */
  17568         soc_block_list[5],
  17569         soc_genreg,
  17570         1,
  17571         0,
  17572         0xe010b00,
  17573         SOC_REG_FLAG_64_BITS,
  17574         0,
  17575         2,
  17576         soc_VLAN_XLATE_DATA_DBGCTRL_1_BCM53400_A0r_fields,
  17577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17578         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17579         -1,
  17580         -1,
  17581     },
  17582 #endif /* chips */
  17583 
  17584 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  17585     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_3_BCM53570_A0r */
  17586         soc_block_list[5],
  17587         soc_genreg,
  17588         1,
  17589         0,
  17590         0xe010b00,
  17591         SOC_REG_FLAG_64_BITS,
  17592         0,
  17593         2,
  17594         soc_VLAN_XLATE_DATA_DBGCTRL_1_BCM53570_A0r_fields,
  17595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17596         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17597         -1,
  17598         -1,
  17599     },
  17600 #endif /* chips */
  17601 
  17602 #if defined(BCM_56150_A0)
  17603     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_3_BCM56150_A0r */
  17604         soc_block_list[5],
  17605         soc_genreg,
  17606         1,
  17607         0,
  17608         0x12010b00,
  17609         0,
  17610         0,
  17611         2,
  17612         soc_VLAN_XLATE_DATA_DBGCTRL_1_BCM56150_A0r_fields,
  17613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17614         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17615         -1,
  17616         -1,
  17617     },
  17618 #endif /* chips */
  17619 
  17620 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  17621     defined(BCM_56270_A0)
  17622     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_3_BCM56260_A0r */
  17623         soc_block_list[5],
  17624         soc_genreg,
  17625         1,
  17626         0,
  17627         0x12010900,
  17628         0,
  17629         0,
  17630         16,
  17631         soc_VLAN_XLATE_DATA_DBGCTRL_3_BCM56260_A0r_fields,
  17632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17634         -1,
  17635         -1,
  17636     },
  17637 #endif /* chips */
  17638 
  17639 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17640     defined(BCM_56450_B1)
  17641     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_3_BCM56450_A0r */
  17642         soc_block_list[5],
  17643         soc_genreg,
  17644         1,
  17645         0,
  17646         0x12010800,
  17647         0,
  17648         0,
  17649         16,
  17650         soc_VLAN_XLATE_DATA_DBGCTRL_3_BCM56450_A0r_fields,
  17651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17652         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17653         -1,
  17654         -1,
  17655     },
  17656 #endif /* chips */
  17657 
  17658 #if defined(BCM_56850_A0)
  17659     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_3_BCM56850_A0r */
  17660         soc_block_list[5],
  17661         soc_genreg,
  17662         1,
  17663         0,
  17664         0x13080000,
  17665         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17666         0,
  17667         5,
  17668         soc_ING_DNAT_ADDRESS_TYPE_B0_PDAr_fields,
  17669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17670         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17671         -1,
  17672         -1,
  17673     },
  17674 #endif /* chips */
  17675 
  17676 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  17677     defined(BCM_56270_A0)
  17678     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_4_BCM56260_A0r */
  17679         soc_block_list[5],
  17680         soc_genreg,
  17681         1,
  17682         0,
  17683         0x12010a00,
  17684         0,
  17685         0,
  17686         3,
  17687         soc_VLAN_XLATE_DATA_DBGCTRL_4_BCM56260_A0r_fields,
  17688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17689         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17690         -1,
  17691         -1,
  17692     },
  17693 #endif /* chips */
  17694 
  17695 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  17696     defined(BCM_56270_A0)
  17697     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_5_BCM56260_A0r */
  17698         soc_block_list[5],
  17699         soc_genreg,
  17700         1,
  17701         0,
  17702         0x12010b00,
  17703         0,
  17704         0,
  17705         3,
  17706         soc_VLAN_XLATE_DATA_DBGCTRL_5_BCM56260_A0r_fields,
  17707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17708         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17709         -1,
  17710         -1,
  17711     },
  17712 #endif /* chips */
  17713 
  17714 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  17715     defined(BCM_56270_A0)
  17716     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_6_BCM56260_A0r */
  17717         soc_block_list[5],
  17718         soc_genreg,
  17719         1,
  17720         0,
  17721         0x12010c00,
  17722         0,
  17723         0,
  17724         2,
  17725         soc_VLAN_XLATE_DATA_DBGCTRL_6_BCM56260_A0r_fields,
  17726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17727         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17728         -1,
  17729         -1,
  17730     },
  17731 #endif /* chips */
  17732 
  17733 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  17734     defined(BCM_56270_A0)
  17735     { /* SOC_REG_INT_VLAN_XLATE_DATA_DBGCTRL_7_BCM56260_A0r */
  17736         soc_block_list[5],
  17737         soc_genreg,
  17738         1,
  17739         0,
  17740         0x12010d00,
  17741         0,
  17742         0,
  17743         16,
  17744         soc_VLAN_XLATE_DATA_DBGCTRL_7_BCM56260_A0r_fields,
  17745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17746         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17747         -1,
  17748         -1,
  17749     },
  17750 #endif /* chips */
  17751 
  17752 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  17753     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRLr */
  17754         soc_block_list[5],
  17755         soc_genreg,
  17756         1,
  17757         0,
  17758         0x4080c43,
  17759         0,
  17760         0,
  17761         2,
  17762         soc_WREDMEMDEBUG_CFG_CELLr_fields,
  17763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17764         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17765         -1,
  17766         -1,
  17767     },
  17768 #endif /* chips */
  17769 
  17770 #if defined(BCM_56850_A0)
  17771     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0r */
  17772         soc_block_list[5],
  17773         soc_genreg,
  17774         1,
  17775         0,
  17776         0x13170000,
  17777         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17778         0,
  17779         8,
  17780         soc_VLAN_XLATE_DBGCTRL_0r_fields,
  17781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17782         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17783         -1,
  17784         -1,
  17785     },
  17786 #endif /* chips */
  17787 
  17788 #if defined(BCM_56850_A0)
  17789     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_1r */
  17790         soc_block_list[5],
  17791         soc_genreg,
  17792         1,
  17793         0,
  17794         0x13160000,
  17795         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17796         0,
  17797         5,
  17798         soc_VLAN_XLATE_DBGCTRL_1r_fields,
  17799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17800         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17801         -1,
  17802         -1,
  17803     },
  17804 #endif /* chips */
  17805 
  17806 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  17807     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_BCM56560_A0r */
  17808         soc_block_list[5],
  17809         soc_genreg,
  17810         1,
  17811         0,
  17812         0x13160000,
  17813         0,
  17814         0,
  17815         5,
  17816         soc_VLAN_XLATE_DBGCTRL_0_BCM56560_A0r_fields,
  17817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17818         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17819         -1,
  17820         -1,
  17821     },
  17822 #endif /* chips */
  17823 
  17824 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  17825     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_BCM56670_A0r */
  17826         soc_block_list[5],
  17827         soc_genreg,
  17828         1,
  17829         0,
  17830         0x13170000,
  17831         0,
  17832         0,
  17833         5,
  17834         soc_VLAN_XLATE_DBGCTRL_0_BCM56560_A0r_fields,
  17835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17836         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17837         -1,
  17838         -1,
  17839     },
  17840 #endif /* chips */
  17841 
  17842 #if defined(BCM_56860_A0)
  17843     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_BCM56860_A0r */
  17844         soc_block_list[5],
  17845         soc_genreg,
  17846         1,
  17847         0,
  17848         0x13150000,
  17849         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17850         0,
  17851         5,
  17852         soc_VLAN_XLATE_DBGCTRL_0_BCM56860_A0r_fields,
  17853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17854         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17855         -1,
  17856         -1,
  17857     },
  17858 #endif /* chips */
  17859 
  17860 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  17861     defined(BCM_56870_A0)
  17862     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_BCM56870_A0r */
  17863         soc_block_list[5],
  17864         soc_genreg,
  17865         1,
  17866         0,
  17867         0x570a0000,
  17868         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17869         0,
  17870         6,
  17871         soc_VLAN_XLATE_DBGCTRL_0_BCM56870_A0r_fields,
  17872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17873         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17874         -1,
  17875         -1,
  17876         0,
  17877     },
  17878 #endif /* chips */
  17879 
  17880 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17881     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_BCM56960_A0r */
  17882         soc_block_list[5],
  17883         soc_genreg,
  17884         1,
  17885         0,
  17886         0x33100000,
  17887         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17888         0,
  17889         5,
  17890         soc_VLAN_XLATE_DBGCTRL_0_BCM56960_A0r_fields,
  17891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17892         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17893         -1,
  17894         -1,
  17895         0,
  17896     },
  17897 #endif /* chips */
  17898 
  17899 #if defined(BCM_56970_A0)
  17900     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_BCM56970_A0r */
  17901         soc_block_list[5],
  17902         soc_genreg,
  17903         1,
  17904         0,
  17905         0x57130000,
  17906         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17907         0,
  17908         6,
  17909         soc_VLAN_XLATE_DBGCTRL_0_BCM56970_A0r_fields,
  17910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17911         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17912         -1,
  17913         -1,
  17914         0,
  17915     },
  17916 #endif /* chips */
  17917 
  17918 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17919     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_PIPE0r */
  17920         soc_block_list[5],
  17921         soc_genreg,
  17922         1,
  17923         0,
  17924         0x33100000,
  17925         0,
  17926         0,
  17927         5,
  17928         soc_VLAN_XLATE_DBGCTRL_0_BCM56960_A0r_fields,
  17929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17930         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17931         -1,
  17932         -1,
  17933         0,
  17934     },
  17935 #endif /* chips */
  17936 
  17937 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17938     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_PIPE1r */
  17939         soc_block_list[5],
  17940         soc_genreg,
  17941         1,
  17942         0,
  17943         0x33100000,
  17944         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17945         0,
  17946         5,
  17947         soc_VLAN_XLATE_DBGCTRL_0_BCM56960_A0r_fields,
  17948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17949         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17950         -1,
  17951         -1,
  17952         0,
  17953     },
  17954 #endif /* chips */
  17955 
  17956 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17957     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_PIPE2r */
  17958         soc_block_list[5],
  17959         soc_genreg,
  17960         1,
  17961         0,
  17962         0x33100000,
  17963         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17964         0,
  17965         5,
  17966         soc_VLAN_XLATE_DBGCTRL_0_BCM56960_A0r_fields,
  17967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17968         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17969         -1,
  17970         -1,
  17971         0,
  17972     },
  17973 #endif /* chips */
  17974 
  17975 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  17976     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_PIPE3r */
  17977         soc_block_list[5],
  17978         soc_genreg,
  17979         1,
  17980         0,
  17981         0x33100000,
  17982         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  17983         0,
  17984         5,
  17985         soc_VLAN_XLATE_DBGCTRL_0_BCM56960_A0r_fields,
  17986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17987         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17988         -1,
  17989         -1,
  17990         0,
  17991     },
  17992 #endif /* chips */
  17993 
  17994 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  17995     defined(BCM_56870_A0)
  17996     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_PIPE0_BCM56870_A0r */
  17997         soc_block_list[5],
  17998         soc_genreg,
  17999         1,
  18000         0,
  18001         0x570a0000,
  18002         0,
  18003         0,
  18004         6,
  18005         soc_VLAN_XLATE_DBGCTRL_0_BCM56870_A0r_fields,
  18006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18007         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18008         -1,
  18009         -1,
  18010         0,
  18011     },
  18012 #endif /* chips */
  18013 
  18014 #if defined(BCM_56970_A0)
  18015     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_PIPE0_BCM56970_A0r */
  18016         soc_block_list[5],
  18017         soc_genreg,
  18018         1,
  18019         0,
  18020         0x57130000,
  18021         0,
  18022         0,
  18023         6,
  18024         soc_VLAN_XLATE_DBGCTRL_0_BCM56970_A0r_fields,
  18025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18026         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18027         -1,
  18028         -1,
  18029         0,
  18030     },
  18031 #endif /* chips */
  18032 
  18033 #if defined(BCM_56870_A0)
  18034     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_PIPE1_BCM56870_A0r */
  18035         soc_block_list[5],
  18036         soc_genreg,
  18037         1,
  18038         0,
  18039         0x570a0000,
  18040         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18041         0,
  18042         6,
  18043         soc_VLAN_XLATE_DBGCTRL_0_BCM56870_A0r_fields,
  18044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18045         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18046         -1,
  18047         -1,
  18048         0,
  18049     },
  18050 #endif /* chips */
  18051 
  18052 #if defined(BCM_56970_A0)
  18053     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_PIPE1_BCM56970_A0r */
  18054         soc_block_list[5],
  18055         soc_genreg,
  18056         1,
  18057         0,
  18058         0x57130000,
  18059         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18060         0,
  18061         6,
  18062         soc_VLAN_XLATE_DBGCTRL_0_BCM56970_A0r_fields,
  18063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18064         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18065         -1,
  18066         -1,
  18067         0,
  18068     },
  18069 #endif /* chips */
  18070 
  18071 #if defined(BCM_56970_A0)
  18072     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_PIPE2_BCM56970_A0r */
  18073         soc_block_list[5],
  18074         soc_genreg,
  18075         1,
  18076         0,
  18077         0x57130000,
  18078         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18079         0,
  18080         6,
  18081         soc_VLAN_XLATE_DBGCTRL_0_BCM56970_A0r_fields,
  18082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18083         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18084         -1,
  18085         -1,
  18086         0,
  18087     },
  18088 #endif /* chips */
  18089 
  18090 #if defined(BCM_56970_A0)
  18091     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_0_PIPE3_BCM56970_A0r */
  18092         soc_block_list[5],
  18093         soc_genreg,
  18094         1,
  18095         0,
  18096         0x57130000,
  18097         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18098         0,
  18099         6,
  18100         soc_VLAN_XLATE_DBGCTRL_0_BCM56970_A0r_fields,
  18101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18102         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18103         -1,
  18104         -1,
  18105         0,
  18106     },
  18107 #endif /* chips */
  18108 
  18109 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  18110     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_1_BCM56560_A0r */
  18111         soc_block_list[5],
  18112         soc_genreg,
  18113         1,
  18114         0,
  18115         0x13150000,
  18116         0,
  18117         0,
  18118         1,
  18119         soc_VLAN_XLATE_DBGCTRL_1_BCM56560_A0r_fields,
  18120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18121         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18122         -1,
  18123         -1,
  18124     },
  18125 #endif /* chips */
  18126 
  18127 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  18128     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_1_BCM56670_A0r */
  18129         soc_block_list[5],
  18130         soc_genreg,
  18131         1,
  18132         0,
  18133         0x13160000,
  18134         0,
  18135         0,
  18136         1,
  18137         soc_VLAN_XLATE_DBGCTRL_1_BCM56560_A0r_fields,
  18138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18139         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18140         -1,
  18141         -1,
  18142     },
  18143 #endif /* chips */
  18144 
  18145 #if defined(BCM_56860_A0)
  18146     { /* SOC_REG_INT_VLAN_XLATE_DBGCTRL_1_BCM56860_A0r */
  18147         soc_block_list[5],
  18148         soc_genreg,
  18149         1,
  18150         0,
  18151         0x13140000,
  18152         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18153         0,
  18154         1,
  18155         soc_VLAN_XLATE_DBGCTRL_1_BCM56860_A0r_fields,
  18156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18157         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18158         -1,
  18159         -1,
  18160     },
  18161 #endif /* chips */
  18162 
  18163 #if defined(BCM_88732_A0)
  18164     { /* SOC_REG_INT_VLAN_XLATE_DEBUG_DATA_0r */
  18165         soc_block_list[5],
  18166         soc_genreg,
  18167         1,
  18168         0,
  18169         0x4080168,
  18170         SOC_REG_FLAG_64_BITS,
  18171         0,
  18172         1,
  18173         soc_VLAN_XLATE_DEBUG_DATA_0r_fields,
  18174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18175         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18176         -1,
  18177         -1,
  18178     },
  18179 #endif /* chips */
  18180 
  18181 #if defined(BCM_88732_A0)
  18182     { /* SOC_REG_INT_VLAN_XLATE_DEBUG_DATA_1r */
  18183         soc_block_list[5],
  18184         soc_genreg,
  18185         1,
  18186         0,
  18187         0x4080169,
  18188         SOC_REG_FLAG_64_BITS,
  18189         0,
  18190         1,
  18191         soc_VLAN_XLATE_DEBUG_DATA_1r_fields,
  18192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18193         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18194         -1,
  18195         -1,
  18196     },
  18197 #endif /* chips */
  18198 
  18199 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  18200     defined(BCM_56270_A0)
  18201     { /* SOC_REG_INT_VLAN_XLATE_ECC_CONTROLr */
  18202         soc_block_list[5],
  18203         soc_genreg,
  18204         1,
  18205         0,
  18206         0x12010e00,
  18207         0,
  18208         0,
  18209         2,
  18210         soc_EGR_MASK_ECC_CONTROLr_fields,
  18211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18212         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18213         -1,
  18214         -1,
  18215     },
  18216 #endif /* chips */
  18217 
  18218 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  18219     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  18220     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  18221     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  18222     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
  18223     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  18224     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROLr */
  18225         soc_block_list[5],
  18226         soc_genreg,
  18227         1,
  18228         0,
  18229         0x4080008,
  18230         0,
  18231         0,
  18232         2,
  18233         soc_EGR_VLAN_XLATE_HASH_CONTROLr_fields,
  18234         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18235         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  18236         -1,
  18237         -1,
  18238     },
  18239 #endif /* chips */
  18240 
  18241 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18242     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18243     defined(BCM_56160_A0)
  18244     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM53400_A0r */
  18245         soc_block_list[5],
  18246         soc_genreg,
  18247         1,
  18248         0,
  18249         0xe000000,
  18250         0,
  18251         0,
  18252         2,
  18253         soc_EGR_VLAN_XLATE_HASH_CONTROL_BCM53400_A0r_fields,
  18254         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18255         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  18256         -1,
  18257         -1,
  18258     },
  18259 #endif /* chips */
  18260 
  18261 #if defined(BCM_56142_A0)
  18262     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM56142_A0r */
  18263         soc_block_list[5],
  18264         soc_genreg,
  18265         1,
  18266         0,
  18267         0x4080008,
  18268         0,
  18269         0,
  18270         2,
  18271         soc_EGR_VLAN_XLATE_HASH_CONTROLr_fields,
  18272         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18273         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  18274         -1,
  18275         -1,
  18276     },
  18277 #endif /* chips */
  18278 
  18279 #if defined(BCM_56150_A0)
  18280     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM56150_A0r */
  18281         soc_block_list[5],
  18282         soc_genreg,
  18283         1,
  18284         0,
  18285         0x12000000,
  18286         0,
  18287         0,
  18288         2,
  18289         soc_EGR_VLAN_XLATE_HASH_CONTROL_BCM56850_A0r_fields,
  18290         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18291         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  18292         -1,
  18293         -1,
  18294     },
  18295 #endif /* chips */
  18296 
  18297 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  18298     defined(BCM_56270_A0)
  18299     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM56260_A0r */
  18300         soc_block_list[5],
  18301         soc_genreg,
  18302         1,
  18303         0,
  18304         0x12000100,
  18305         0,
  18306         0,
  18307         3,
  18308         soc_VLAN_XLATE_HASH_CONTROL_BCM56260_A0r_fields,
  18309         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18310         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  18311         -1,
  18312         -1,
  18313     },
  18314 #endif /* chips */
  18315 
  18316 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18317     defined(BCM_56450_B1)
  18318     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM56450_A0r */
  18319         soc_block_list[5],
  18320         soc_genreg,
  18321         1,
  18322         0,
  18323         0x12000100,
  18324         0,
  18325         0,
  18326         3,
  18327         soc_VLAN_XLATE_HASH_CONTROLr_fields,
  18328         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18329         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  18330         -1,
  18331         -1,
  18332     },
  18333 #endif /* chips */
  18334 
  18335 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  18336     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  18337     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM56560_A0r */
  18338         soc_block_list[5],
  18339         soc_genreg,
  18340         1,
  18341         0,
  18342         0x12000800,
  18343         0,
  18344         0,
  18345         2,
  18346         soc_EGR_VLAN_XLATE_HASH_CONTROL_BCM53400_A0r_fields,
  18347         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18348         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  18349         -1,
  18350         -1,
  18351     },
  18352 #endif /* chips */
  18353 
  18354 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  18355     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM56820_A0r */
  18356         soc_block_list[5],
  18357         soc_genreg,
  18358         1,
  18359         0,
  18360         0x4080600,
  18361         0,
  18362         0,
  18363         2,
  18364         soc_EGR_VLAN_XLATE_HASH_CONTROLr_fields,
  18365         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18366         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  18367         -1,
  18368         -1,
  18369     },
  18370 #endif /* chips */
  18371 
  18372 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  18373     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  18374     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM56840_A0r */
  18375         soc_block_list[5],
  18376         soc_genreg,
  18377         1,
  18378         0,
  18379         0x4080608,
  18380         0,
  18381         0,
  18382         2,
  18383         soc_EGR_VLAN_XLATE_HASH_CONTROLr_fields,
  18384         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18385         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  18386         -1,
  18387         -1,
  18388     },
  18389 #endif /* chips */
  18390 
  18391 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  18392     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM56850_A0r */
  18393         soc_block_list[5],
  18394         soc_genreg,
  18395         1,
  18396         0,
  18397         0x12000800,
  18398         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18399         0,
  18400         2,
  18401         soc_EGR_VLAN_XLATE_HASH_CONTROL_BCM56850_A0r_fields,
  18402         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18403         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  18404         -1,
  18405         -1,
  18406     },
  18407 #endif /* chips */
  18408 
  18409 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18410     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM56960_A0r */
  18411         soc_block_list[5],
  18412         soc_genreg,
  18413         1,
  18414         0,
  18415         0x32000100,
  18416         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18417         0,
  18418         3,
  18419         soc_EGR_VLAN_XLATE_HASH_CONTROL_BCM56960_A0r_fields,
  18420         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18421         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  18422         -1,
  18423         -1,
  18424         0,
  18425     },
  18426 #endif /* chips */
  18427 
  18428 #if defined(BCM_56970_A0)
  18429     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM56970_A0r */
  18430         soc_block_list[5],
  18431         soc_genreg,
  18432         1,
  18433         0,
  18434         0x56000100,
  18435         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18436         0,
  18437         3,
  18438         soc_EGR_VLAN_XLATE_HASH_CONTROL_BCM56960_A0r_fields,
  18439         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18440         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  18441         -1,
  18442         -1,
  18443         0,
  18444     },
  18445 #endif /* chips */
  18446 
  18447 #if defined(BCM_88732_A0)
  18448     { /* SOC_REG_INT_VLAN_XLATE_HASH_CONTROL_BCM88732_A0r */
  18449         soc_block_list[5],
  18450         soc_genreg,
  18451         1,
  18452         0,
  18453         0x408005f,
  18454         0,
  18455         0,
  18456         2,
  18457         soc_EGR_VLAN_XLATE_HASH_CONTROLr_fields,
  18458         SOC_RESET_VAL_DEC(0x0000000a, 0x00000000)
  18459         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  18460         -1,
  18461         -1,
  18462     },
  18463 #endif /* chips */
  18464 
  18465 #if defined(BCM_56850_A0)
  18466     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0r */
  18467         soc_block_list[5],
  18468         soc_genreg,
  18469         1,
  18470         0,
  18471         0x13090000,
  18472         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18473         0,
  18474         2,
  18475         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0r_fields,
  18476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18477         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18478         -1,
  18479         -1,
  18480     },
  18481 #endif /* chips */
  18482 
  18483 #if defined(BCM_56850_A0)
  18484     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_1r */
  18485         soc_block_list[5],
  18486         soc_genreg,
  18487         1,
  18488         0,
  18489         0x130a0000,
  18490         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18491         0,
  18492         2,
  18493         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0r_fields,
  18494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18495         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18496         -1,
  18497         -1,
  18498     },
  18499 #endif /* chips */
  18500 
  18501 #if defined(BCM_56850_A0)
  18502     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_2r */
  18503         soc_block_list[5],
  18504         soc_genreg,
  18505         1,
  18506         0,
  18507         0x130b0000,
  18508         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18509         0,
  18510         4,
  18511         soc_VLAN_XLATE_LP_DATA_DBGCTRL_2r_fields,
  18512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18514         -1,
  18515         -1,
  18516     },
  18517 #endif /* chips */
  18518 
  18519 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  18520     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56560_A0r */
  18521         soc_block_list[5],
  18522         soc_genreg,
  18523         1,
  18524         0,
  18525         0x13070000,
  18526         0,
  18527         0,
  18528         1,
  18529         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56560_A0r_fields,
  18530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18531         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18532         -1,
  18533         -1,
  18534     },
  18535 #endif /* chips */
  18536 
  18537 #if defined(BCM_56860_A0)
  18538     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56860_A0r */
  18539         soc_block_list[5],
  18540         soc_genreg,
  18541         1,
  18542         0,
  18543         0x13070000,
  18544         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18545         0,
  18546         1,
  18547         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56860_A0r_fields,
  18548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18549         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18550         -1,
  18551         -1,
  18552     },
  18553 #endif /* chips */
  18554 
  18555 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  18556     defined(BCM_56870_A0)
  18557     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56870_A0r */
  18558         soc_block_list[5],
  18559         soc_genreg,
  18560         1,
  18561         0,
  18562         0x57030000,
  18563         SOC_REG_FLAG_64_BITS |
  18564                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18565         0,
  18566         3,
  18567         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56870_A0r_fields,
  18568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18569         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18570         -1,
  18571         -1,
  18572         0,
  18573     },
  18574 #endif /* chips */
  18575 
  18576 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18577     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56960_A0r */
  18578         soc_block_list[5],
  18579         soc_genreg,
  18580         1,
  18581         0,
  18582         0x33070000,
  18583         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18584         0,
  18585         2,
  18586         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  18587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18588         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18589         -1,
  18590         -1,
  18591         0,
  18592     },
  18593 #endif /* chips */
  18594 
  18595 #if defined(BCM_56970_A0)
  18596     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56970_A0r */
  18597         soc_block_list[5],
  18598         soc_genreg,
  18599         1,
  18600         0,
  18601         0x57070000,
  18602         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18603         0,
  18604         2,
  18605         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  18606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18607         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18608         -1,
  18609         -1,
  18610         0,
  18611     },
  18612 #endif /* chips */
  18613 
  18614 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18615     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE0r */
  18616         soc_block_list[5],
  18617         soc_genreg,
  18618         1,
  18619         0,
  18620         0x33070000,
  18621         0,
  18622         0,
  18623         2,
  18624         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  18625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18626         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18627         -1,
  18628         -1,
  18629         0,
  18630     },
  18631 #endif /* chips */
  18632 
  18633 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18634     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE1r */
  18635         soc_block_list[5],
  18636         soc_genreg,
  18637         1,
  18638         0,
  18639         0x33070000,
  18640         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18641         0,
  18642         2,
  18643         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  18644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18646         -1,
  18647         -1,
  18648         0,
  18649     },
  18650 #endif /* chips */
  18651 
  18652 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18653     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE2r */
  18654         soc_block_list[5],
  18655         soc_genreg,
  18656         1,
  18657         0,
  18658         0x33070000,
  18659         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18660         0,
  18661         2,
  18662         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  18663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18664         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18665         -1,
  18666         -1,
  18667         0,
  18668     },
  18669 #endif /* chips */
  18670 
  18671 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  18672     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE3r */
  18673         soc_block_list[5],
  18674         soc_genreg,
  18675         1,
  18676         0,
  18677         0x33070000,
  18678         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18679         0,
  18680         2,
  18681         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  18682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18683         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18684         -1,
  18685         -1,
  18686         0,
  18687     },
  18688 #endif /* chips */
  18689 
  18690 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  18691     defined(BCM_56870_A0)
  18692     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE0_BCM56870_A0r */
  18693         soc_block_list[5],
  18694         soc_genreg,
  18695         1,
  18696         0,
  18697         0x57030000,
  18698         SOC_REG_FLAG_64_BITS,
  18699         0,
  18700         3,
  18701         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56870_A0r_fields,
  18702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18703         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18704         -1,
  18705         -1,
  18706         0,
  18707     },
  18708 #endif /* chips */
  18709 
  18710 #if defined(BCM_56970_A0)
  18711     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE0_BCM56970_A0r */
  18712         soc_block_list[5],
  18713         soc_genreg,
  18714         1,
  18715         0,
  18716         0x57070000,
  18717         0,
  18718         0,
  18719         2,
  18720         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  18721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18722         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18723         -1,
  18724         -1,
  18725         0,
  18726     },
  18727 #endif /* chips */
  18728 
  18729 #if defined(BCM_56870_A0)
  18730     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE1_BCM56870_A0r */
  18731         soc_block_list[5],
  18732         soc_genreg,
  18733         1,
  18734         0,
  18735         0x57030000,
  18736         SOC_REG_FLAG_64_BITS |
  18737                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18738         0,
  18739         3,
  18740         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56870_A0r_fields,
  18741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18742         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18743         -1,
  18744         -1,
  18745         0,
  18746     },
  18747 #endif /* chips */
  18748 
  18749 #if defined(BCM_56970_A0)
  18750     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE1_BCM56970_A0r */
  18751         soc_block_list[5],
  18752         soc_genreg,
  18753         1,
  18754         0,
  18755         0x57070000,
  18756         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18757         0,
  18758         2,
  18759         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  18760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18761         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18762         -1,
  18763         -1,
  18764         0,
  18765     },
  18766 #endif /* chips */
  18767 
  18768 #if defined(BCM_56970_A0)
  18769     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE2_BCM56970_A0r */
  18770         soc_block_list[5],
  18771         soc_genreg,
  18772         1,
  18773         0,
  18774         0x57070000,
  18775         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18776         0,
  18777         2,
  18778         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  18779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18780         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18781         -1,
  18782         -1,
  18783         0,
  18784     },
  18785 #endif /* chips */
  18786 
  18787 #if defined(BCM_56970_A0)
  18788     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE3_BCM56970_A0r */
  18789         soc_block_list[5],
  18790         soc_genreg,
  18791         1,
  18792         0,
  18793         0x57070000,
  18794         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18795         0,
  18796         2,
  18797         soc_MPLS_ENTRY_LP_DATA_DBGCTRL_0r_fields,
  18798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18799         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18800         -1,
  18801         -1,
  18802         0,
  18803     },
  18804 #endif /* chips */
  18805 
  18806 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  18807     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  18808     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_1_BCM56560_A0r */
  18809         soc_block_list[5],
  18810         soc_genreg,
  18811         1,
  18812         0,
  18813         0x13080000,
  18814         0,
  18815         0,
  18816         1,
  18817         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56560_A0r_fields,
  18818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18819         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18820         -1,
  18821         -1,
  18822     },
  18823 #endif /* chips */
  18824 
  18825 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  18826     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_1_BCM56670_A0r */
  18827         soc_block_list[5],
  18828         soc_genreg,
  18829         1,
  18830         0,
  18831         0x13090000,
  18832         0,
  18833         0,
  18834         1,
  18835         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56560_A0r_fields,
  18836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18837         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18838         -1,
  18839         -1,
  18840     },
  18841 #endif /* chips */
  18842 
  18843 #if defined(BCM_56860_A0)
  18844     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_1_BCM56860_A0r */
  18845         soc_block_list[5],
  18846         soc_genreg,
  18847         1,
  18848         0,
  18849         0x13080000,
  18850         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18851         0,
  18852         1,
  18853         soc_VLAN_XLATE_LP_DATA_DBGCTRL_0_BCM56860_A0r_fields,
  18854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18855         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18856         -1,
  18857         -1,
  18858     },
  18859 #endif /* chips */
  18860 
  18861 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  18862     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_2_BCM56560_A0r */
  18863         soc_block_list[5],
  18864         soc_genreg,
  18865         1,
  18866         0,
  18867         0x13090000,
  18868         0,
  18869         0,
  18870         4,
  18871         soc_VLAN_XLATE_LP_DATA_DBGCTRL_2_BCM56560_A0r_fields,
  18872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18873         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18874         -1,
  18875         -1,
  18876     },
  18877 #endif /* chips */
  18878 
  18879 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  18880     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_2_BCM56670_A0r */
  18881         soc_block_list[5],
  18882         soc_genreg,
  18883         1,
  18884         0,
  18885         0x130a0000,
  18886         0,
  18887         0,
  18888         4,
  18889         soc_VLAN_XLATE_LP_DATA_DBGCTRL_2_BCM56560_A0r_fields,
  18890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18892         -1,
  18893         -1,
  18894     },
  18895 #endif /* chips */
  18896 
  18897 #if defined(BCM_56860_A0)
  18898     { /* SOC_REG_INT_VLAN_XLATE_LP_DATA_DBGCTRL_2_BCM56860_A0r */
  18899         soc_block_list[5],
  18900         soc_genreg,
  18901         1,
  18902         0,
  18903         0x13090000,
  18904         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  18905         0,
  18906         4,
  18907         soc_VLAN_XLATE_LP_DATA_DBGCTRL_2r_fields,
  18908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18909         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18910         -1,
  18911         -1,
  18912     },
  18913 #endif /* chips */
  18914 
  18915 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  18916     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  18917     { /* SOC_REG_INT_VLAN_XLATE_PARITY_CONTROLr */
  18918         soc_block_list[5],
  18919         soc_genreg,
  18920         1,
  18921         0,
  18922         0x4080111,
  18923         0,
  18924         0,
  18925         1,
  18926         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  18927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18928         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  18929         -1,
  18930         -1,
  18931     },
  18932 #endif /* chips */
  18933 
  18934 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18935     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18936     defined(BCM_56160_A0)
  18937     { /* SOC_REG_INT_VLAN_XLATE_PARITY_CONTROL_BCM53400_A0r */
  18938         soc_block_list[5],
  18939         soc_genreg,
  18940         1,
  18941         0,
  18942         0xe011600,
  18943         0,
  18944         0,
  18945         1,
  18946         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  18947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18948         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  18949         -1,
  18950         -1,
  18951     },
  18952 #endif /* chips */
  18953 
  18954 #if defined(BCM_56150_A0)
  18955     { /* SOC_REG_INT_VLAN_XLATE_PARITY_CONTROL_BCM56150_A0r */
  18956         soc_block_list[5],
  18957         soc_genreg,
  18958         1,
  18959         0,
  18960         0x12011200,
  18961         0,
  18962         0,
  18963         1,
  18964         soc_DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr_fields,
  18965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18966         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  18967         -1,
  18968         -1,
  18969     },
  18970 #endif /* chips */
  18971 
  18972 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
  18973     defined(BCM_56334_B0)
  18974     { /* SOC_REG_INT_VLAN_XLATE_PARITY_CONTROL_BCM56334_A0r */
  18975         soc_block_list[5],
  18976         soc_genreg,
  18977         1,
  18978         0,
  18979         0x4080123,
  18980         0,
  18981         0,
  18982         1,
  18983         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  18984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18985         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  18986         -1,
  18987         -1,
  18988     },
  18989 #endif /* chips */
  18990 
  18991 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18992     defined(BCM_56450_B1)
  18993     { /* SOC_REG_INT_VLAN_XLATE_PARITY_CONTROL_BCM56450_A0r */
  18994         soc_block_list[5],
  18995         soc_genreg,
  18996         1,
  18997         0,
  18998         0x12010d00,
  18999         0,
  19000         0,
  19001         1,
  19002         soc_FT_CNTR_SER_CONTROLr_fields,
  19003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19004         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19005         -1,
  19006         -1,
  19007     },
  19008 #endif /* chips */
  19009 
  19010 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  19011     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  19012     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  19013     { /* SOC_REG_INT_VLAN_XLATE_PARITY_CONTROL_BCM56634_A0r */
  19014         soc_block_list[5],
  19015         soc_genreg,
  19016         1,
  19017         0,
  19018         0x408013d,
  19019         0,
  19020         0,
  19021         1,
  19022         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  19023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19024         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19025         -1,
  19026         -1,
  19027     },
  19028 #endif /* chips */
  19029 
  19030 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  19031     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19032     { /* SOC_REG_INT_VLAN_XLATE_PARITY_CONTROL_BCM56840_A0r */
  19033         soc_block_list[5],
  19034         soc_genreg,
  19035         1,
  19036         0,
  19037         0x4080d0c,
  19038         0,
  19039         0,
  19040         1,
  19041         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  19042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19043         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19044         -1,
  19045         -1,
  19046     },
  19047 #endif /* chips */
  19048 
  19049 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  19050     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  19051     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUSr */
  19052         soc_block_list[5],
  19053         soc_genreg,
  19054         1,
  19055         0,
  19056         0x4080112,
  19057         0,
  19058         0,
  19059         4,
  19060         soc_EGR_VLAN_XLATE_PARITY_STATUSr_fields,
  19061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19062         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  19063         -1,
  19064         -1,
  19065     },
  19066 #endif /* chips */
  19067 
  19068 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  19069     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_0r */
  19070         soc_block_list[5],
  19071         soc_genreg,
  19072         1,
  19073         0,
  19074         0x4080124,
  19075         0,
  19076         0,
  19077         3,
  19078         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0r_fields,
  19079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19080         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  19081         -1,
  19082         -1,
  19083     },
  19084 #endif /* chips */
  19085 
  19086 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  19087     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_1r */
  19088         soc_block_list[5],
  19089         soc_genreg,
  19090         1,
  19091         0,
  19092         0x4080125,
  19093         0,
  19094         0,
  19095         3,
  19096         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0r_fields,
  19097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19098         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  19099         -1,
  19100         -1,
  19101     },
  19102 #endif /* chips */
  19103 
  19104 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  19105     defined(BCM_56160_A0)
  19106     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_0_BCM53400_A0r */
  19107         soc_block_list[5],
  19108         soc_genreg,
  19109         1,
  19110         0,
  19111         0xe011700,
  19112         0,
  19113         0,
  19114         3,
  19115         soc_EGR_VLAN_XLATE_PARITY_STATUS_0_BCM53400_A0r_fields,
  19116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19117         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  19118         -1,
  19119         -1,
  19120     },
  19121 #endif /* chips */
  19122 
  19123 #if defined(BCM_53540_A0)
  19124     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_0_BCM53540_A0r */
  19125         soc_block_list[5],
  19126         soc_genreg,
  19127         1,
  19128         0,
  19129         0xe011700,
  19130         0,
  19131         0,
  19132         3,
  19133         soc_EGR_VLAN_XLATE_PARITY_STATUS_0_BCM53540_A0r_fields,
  19134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19135         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  19136         -1,
  19137         -1,
  19138     },
  19139 #endif /* chips */
  19140 
  19141 #if defined(BCM_53570_B0)
  19142     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_0_BCM53570_B0r */
  19143         soc_block_list[5],
  19144         soc_genreg,
  19145         1,
  19146         0,
  19147         0xe011700,
  19148         0,
  19149         0,
  19150         3,
  19151         soc_VLAN_XLATE_PARITY_STATUS_0r_fields,
  19152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19153         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  19154         -1,
  19155         -1,
  19156     },
  19157 #endif /* chips */
  19158 
  19159 #if defined(BCM_56142_A0)
  19160     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_0_BCM56142_A0r */
  19161         soc_block_list[5],
  19162         soc_genreg,
  19163         1,
  19164         0,
  19165         0x4080124,
  19166         0,
  19167         0,
  19168         3,
  19169         soc_EGR_VLAN_XLATE_PARITY_STATUS_0r_fields,
  19170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19171         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  19172         -1,
  19173         -1,
  19174     },
  19175 #endif /* chips */
  19176 
  19177 #if defined(BCM_56150_A0)
  19178     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_0_BCM56150_A0r */
  19179         soc_block_list[5],
  19180         soc_genreg,
  19181         1,
  19182         0,
  19183         0x12011300,
  19184         0,
  19185         0,
  19186         3,
  19187         soc_EGR_VLAN_XLATE_PARITY_STATUS_0_BCM56150_A0r_fields,
  19188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19189         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  19190         -1,
  19191         -1,
  19192     },
  19193 #endif /* chips */
  19194 
  19195 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  19196     defined(BCM_56160_A0)
  19197     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_1_BCM53400_A0r */
  19198         soc_block_list[5],
  19199         soc_genreg,
  19200         1,
  19201         0,
  19202         0xe011800,
  19203         0,
  19204         0,
  19205         3,
  19206         soc_EGR_VLAN_XLATE_PARITY_STATUS_0_BCM53400_A0r_fields,
  19207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19208         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  19209         -1,
  19210         -1,
  19211     },
  19212 #endif /* chips */
  19213 
  19214 #if defined(BCM_53540_A0)
  19215     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_1_BCM53540_A0r */
  19216         soc_block_list[5],
  19217         soc_genreg,
  19218         1,
  19219         0,
  19220         0xe011800,
  19221         0,
  19222         0,
  19223         3,
  19224         soc_EGR_VLAN_XLATE_PARITY_STATUS_0_BCM53540_A0r_fields,
  19225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19226         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  19227         -1,
  19228         -1,
  19229     },
  19230 #endif /* chips */
  19231 
  19232 #if defined(BCM_53570_B0)
  19233     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_1_BCM53570_B0r */
  19234         soc_block_list[5],
  19235         soc_genreg,
  19236         1,
  19237         0,
  19238         0xe011800,
  19239         0,
  19240         0,
  19241         3,
  19242         soc_VLAN_XLATE_PARITY_STATUS_0r_fields,
  19243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19244         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  19245         -1,
  19246         -1,
  19247     },
  19248 #endif /* chips */
  19249 
  19250 #if defined(BCM_56142_A0)
  19251     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_1_BCM56142_A0r */
  19252         soc_block_list[5],
  19253         soc_genreg,
  19254         1,
  19255         0,
  19256         0x4080125,
  19257         0,
  19258         0,
  19259         3,
  19260         soc_EGR_VLAN_XLATE_PARITY_STATUS_0r_fields,
  19261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19262         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  19263         -1,
  19264         -1,
  19265     },
  19266 #endif /* chips */
  19267 
  19268 #if defined(BCM_56150_A0)
  19269     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_1_BCM56150_A0r */
  19270         soc_block_list[5],
  19271         soc_genreg,
  19272         1,
  19273         0,
  19274         0x12011400,
  19275         0,
  19276         0,
  19277         3,
  19278         soc_EGR_VLAN_XLATE_PARITY_STATUS_0_BCM56150_A0r_fields,
  19279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19280         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  19281         -1,
  19282         -1,
  19283     },
  19284 #endif /* chips */
  19285 
  19286 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  19287     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  19288     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  19289     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_INTR_0r */
  19290         soc_block_list[5],
  19291         soc_genreg,
  19292         1,
  19293         0,
  19294         0x408013e,
  19295         0,
  19296         0,
  19297         3,
  19298         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0r_fields,
  19299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19300         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  19301         -1,
  19302         -1,
  19303     },
  19304 #endif /* chips */
  19305 
  19306 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  19307     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  19308     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  19309     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_INTR_1r */
  19310         soc_block_list[5],
  19311         soc_genreg,
  19312         1,
  19313         0,
  19314         0x408013f,
  19315         0,
  19316         0,
  19317         3,
  19318         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0r_fields,
  19319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19320         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  19321         -1,
  19322         -1,
  19323     },
  19324 #endif /* chips */
  19325 
  19326 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  19327     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_INTR_0_BCM56440_A0r */
  19328         soc_block_list[5],
  19329         soc_genreg,
  19330         1,
  19331         0,
  19332         0x4080d0d,
  19333         0,
  19334         0,
  19335         3,
  19336         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0_BCM56440_A0r_fields,
  19337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19338         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19339         -1,
  19340         -1,
  19341     },
  19342 #endif /* chips */
  19343 
  19344 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  19345     defined(BCM_56450_B1)
  19346     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_INTR_0_BCM56450_A0r */
  19347         soc_block_list[5],
  19348         soc_genreg,
  19349         1,
  19350         0,
  19351         0x12010e00,
  19352         0,
  19353         0,
  19354         3,
  19355         soc_VLAN_XLATE_PARITY_STATUS_INTR_0r_fields,
  19356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19357         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19358         -1,
  19359         -1,
  19360     },
  19361 #endif /* chips */
  19362 
  19363 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19364     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_INTR_0_BCM56840_A0r */
  19365         soc_block_list[5],
  19366         soc_genreg,
  19367         1,
  19368         0,
  19369         0x4080d0d,
  19370         0,
  19371         0,
  19372         3,
  19373         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
  19374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19375         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19376         -1,
  19377         -1,
  19378     },
  19379 #endif /* chips */
  19380 
  19381 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  19382     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_INTR_1_BCM56440_A0r */
  19383         soc_block_list[5],
  19384         soc_genreg,
  19385         1,
  19386         0,
  19387         0x4080d0e,
  19388         0,
  19389         0,
  19390         3,
  19391         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0_BCM56440_A0r_fields,
  19392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19393         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19394         -1,
  19395         -1,
  19396     },
  19397 #endif /* chips */
  19398 
  19399 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  19400     defined(BCM_56450_B1)
  19401     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_INTR_1_BCM56450_A0r */
  19402         soc_block_list[5],
  19403         soc_genreg,
  19404         1,
  19405         0,
  19406         0x12010f00,
  19407         0,
  19408         0,
  19409         3,
  19410         soc_VLAN_XLATE_PARITY_STATUS_INTR_0r_fields,
  19411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19412         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19413         -1,
  19414         -1,
  19415     },
  19416 #endif /* chips */
  19417 
  19418 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19419     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_INTR_1_BCM56840_A0r */
  19420         soc_block_list[5],
  19421         soc_genreg,
  19422         1,
  19423         0,
  19424         0x4080d0e,
  19425         0,
  19426         0,
  19427         3,
  19428         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
  19429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19430         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19431         -1,
  19432         -1,
  19433     },
  19434 #endif /* chips */
  19435 
  19436 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  19437     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  19438     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  19439     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_NACK_0r */
  19440         soc_block_list[5],
  19441         soc_genreg,
  19442         1,
  19443         0,
  19444         0x4080140,
  19445         0,
  19446         0,
  19447         3,
  19448         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0r_fields,
  19449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19450         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  19451         -1,
  19452         -1,
  19453     },
  19454 #endif /* chips */
  19455 
  19456 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  19457     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  19458     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  19459     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_NACK_1r */
  19460         soc_block_list[5],
  19461         soc_genreg,
  19462         1,
  19463         0,
  19464         0x4080141,
  19465         0,
  19466         0,
  19467         3,
  19468         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0r_fields,
  19469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19470         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  19471         -1,
  19472         -1,
  19473     },
  19474 #endif /* chips */
  19475 
  19476 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  19477     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_NACK_0_BCM56440_A0r */
  19478         soc_block_list[5],
  19479         soc_genreg,
  19480         1,
  19481         0,
  19482         0x4080d0f,
  19483         0,
  19484         0,
  19485         3,
  19486         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0_BCM56440_A0r_fields,
  19487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19488         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19489         -1,
  19490         -1,
  19491     },
  19492 #endif /* chips */
  19493 
  19494 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  19495     defined(BCM_56450_B1)
  19496     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_NACK_0_BCM56450_A0r */
  19497         soc_block_list[5],
  19498         soc_genreg,
  19499         1,
  19500         0,
  19501         0x12011000,
  19502         0,
  19503         0,
  19504         3,
  19505         soc_VLAN_XLATE_PARITY_STATUS_INTR_0r_fields,
  19506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19507         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19508         -1,
  19509         -1,
  19510     },
  19511 #endif /* chips */
  19512 
  19513 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19514     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_NACK_0_BCM56840_A0r */
  19515         soc_block_list[5],
  19516         soc_genreg,
  19517         1,
  19518         0,
  19519         0x4080d0f,
  19520         0,
  19521         0,
  19522         3,
  19523         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
  19524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19525         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19526         -1,
  19527         -1,
  19528     },
  19529 #endif /* chips */
  19530 
  19531 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  19532     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_NACK_1_BCM56440_A0r */
  19533         soc_block_list[5],
  19534         soc_genreg,
  19535         1,
  19536         0,
  19537         0x4080d10,
  19538         0,
  19539         0,
  19540         3,
  19541         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0_BCM56440_A0r_fields,
  19542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19543         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19544         -1,
  19545         -1,
  19546     },
  19547 #endif /* chips */
  19548 
  19549 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  19550     defined(BCM_56450_B1)
  19551     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_NACK_1_BCM56450_A0r */
  19552         soc_block_list[5],
  19553         soc_genreg,
  19554         1,
  19555         0,
  19556         0x12011100,
  19557         0,
  19558         0,
  19559         3,
  19560         soc_VLAN_XLATE_PARITY_STATUS_INTR_0r_fields,
  19561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19562         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19563         -1,
  19564         -1,
  19565     },
  19566 #endif /* chips */
  19567 
  19568 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19569     { /* SOC_REG_INT_VLAN_XLATE_PARITY_STATUS_NACK_1_BCM56840_A0r */
  19570         soc_block_list[5],
  19571         soc_genreg,
  19572         1,
  19573         0,
  19574         0x4080d10,
  19575         0,
  19576         0,
  19577         3,
  19578         soc_EGR_VLAN_XLATE_PARITY_STATUS_INTR_0_BCM56840_A0r_fields,
  19579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19580         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19581         -1,
  19582         -1,
  19583     },
  19584 #endif /* chips */
  19585 
  19586 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  19587     { /* SOC_REG_INT_VMON_ADC_CTRL0r */
  19588         soc_block_list[1],
  19589         soc_iprocreg,
  19590         1,
  19591         0,
  19592         0x1800f394,
  19593         0,
  19594         0,
  19595         8,
  19596         soc_VMON_ADC_CTRL0r_fields,
  19597         SOC_RESET_VAL_DEC(0x00003003, 0x00000000)
  19598         SOC_RESET_MASK_DEC(0x7ff777f3, 0x00000000)
  19599         -1,
  19600         -1,
  19601     },
  19602 #endif /* chips */
  19603 
  19604 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  19605     { /* SOC_REG_INT_VMON_CTRL0r */
  19606         soc_block_list[1],
  19607         soc_iprocreg,
  19608         1,
  19609         0,
  19610         0x1800f39c,
  19611         0,
  19612         0,
  19613         2,
  19614         soc_VMON_CTRL0r_fields,
  19615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19616         SOC_RESET_MASK_DEC(0x03ff03ff, 0x00000000)
  19617         -1,
  19618         -1,
  19619     },
  19620 #endif /* chips */
  19621 
  19622 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  19623     { /* SOC_REG_INT_VMON_CTRL1r */
  19624         soc_block_list[1],
  19625         soc_iprocreg,
  19626         1,
  19627         0,
  19628         0x1800f3a0,
  19629         0,
  19630         0,
  19631         3,
  19632         soc_VMON_CTRL1r_fields,
  19633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19634         SOC_RESET_MASK_DEC(0x8001ffff, 0x00000000)
  19635         -1,
  19636         -1,
  19637     },
  19638 #endif /* chips */
  19639 
  19640 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19641     { /* SOC_REG_INT_VOQFC_CNTr */
  19642         soc_block_list[4],
  19643         soc_genreg,
  19644         1,
  19645         0,
  19646         0x15080200,
  19647         0,
  19648         0,
  19649         1,
  19650         soc_VOQFC_CNTr_fields,
  19651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19652         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19653         -1,
  19654         -1,
  19655     },
  19656 #endif /* chips */
  19657 
  19658 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19659     { /* SOC_REG_INT_VOQFC_MSG_PORT_SEL0r */
  19660         soc_block_list[4],
  19661         soc_genreg,
  19662         16,
  19663         0,
  19664         0x15080080,
  19665         SOC_REG_FLAG_ARRAY,
  19666         0,
  19667         1,
  19668         soc_VOQFC_MSG_PORT_SEL0r_fields,
  19669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19670         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  19671         -1,
  19672         -1,
  19673     },
  19674 #endif /* chips */
  19675 
  19676 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19677     { /* SOC_REG_INT_VOQFC_MSG_PORT_SEL1r */
  19678         soc_block_list[4],
  19679         soc_genreg,
  19680         16,
  19681         0,
  19682         0x15080090,
  19683         SOC_REG_FLAG_ARRAY,
  19684         0,
  19685         1,
  19686         soc_VOQFC_MSG_PORT_SEL0r_fields,
  19687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19688         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  19689         -1,
  19690         -1,
  19691     },
  19692 #endif /* chips */
  19693 
  19694 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19695     { /* SOC_REG_INT_VOQFC_MSG_PORT_SEL2r */
  19696         soc_block_list[4],
  19697         soc_genreg,
  19698         16,
  19699         0,
  19700         0x150800a0,
  19701         SOC_REG_FLAG_ARRAY,
  19702         0,
  19703         1,
  19704         soc_VOQFC_MSG_PORT_SEL0r_fields,
  19705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19706         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  19707         -1,
  19708         -1,
  19709     },
  19710 #endif /* chips */
  19711 
  19712 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19713     { /* SOC_REG_INT_VOQFC_MSG_PORT_SEL3r */
  19714         soc_block_list[4],
  19715         soc_genreg,
  19716         16,
  19717         0,
  19718         0x150800b0,
  19719         SOC_REG_FLAG_ARRAY,
  19720         0,
  19721         1,
  19722         soc_VOQFC_MSG_PORT_SEL0r_fields,
  19723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19724         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  19725         -1,
  19726         -1,
  19727     },
  19728 #endif /* chips */
  19729 
  19730 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19731     { /* SOC_REG_INT_VOQFC_MSG_PORT_SEL4r */
  19732         soc_block_list[4],
  19733         soc_genreg,
  19734         16,
  19735         0,
  19736         0x150800c0,
  19737         SOC_REG_FLAG_ARRAY,
  19738         0,
  19739         1,
  19740         soc_VOQFC_MSG_PORT_SEL0r_fields,
  19741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19742         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  19743         -1,
  19744         -1,
  19745     },
  19746 #endif /* chips */
  19747 
  19748 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19749     { /* SOC_REG_INT_VOQFC_MSG_PORT_SEL5r */
  19750         soc_block_list[4],
  19751         soc_genreg,
  19752         16,
  19753         0,
  19754         0x150800d0,
  19755         SOC_REG_FLAG_ARRAY,
  19756         0,
  19757         1,
  19758         soc_VOQFC_MSG_PORT_SEL0r_fields,
  19759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19760         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  19761         -1,
  19762         -1,
  19763     },
  19764 #endif /* chips */
  19765 
  19766 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19767     { /* SOC_REG_INT_VOQFC_MSG_PORT_SEL6r */
  19768         soc_block_list[4],
  19769         soc_genreg,
  19770         16,
  19771         0,
  19772         0x150800e0,
  19773         SOC_REG_FLAG_ARRAY,
  19774         0,
  19775         1,
  19776         soc_VOQFC_MSG_PORT_SEL0r_fields,
  19777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19778         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  19779         -1,
  19780         -1,
  19781     },
  19782 #endif /* chips */
  19783 
  19784 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19785     { /* SOC_REG_INT_VOQFC_MSG_PORT_SEL7r */
  19786         soc_block_list[4],
  19787         soc_genreg,
  19788         16,
  19789         0,
  19790         0x150800f0,
  19791         SOC_REG_FLAG_ARRAY,
  19792         0,
  19793         1,
  19794         soc_VOQFC_MSG_PORT_SEL0r_fields,
  19795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19796         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  19797         -1,
  19798         -1,
  19799     },
  19800 #endif /* chips */
  19801 
  19802 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19803     { /* SOC_REG_INT_VOQFC_STATE_MERGE_GRP0r */
  19804         soc_block_list[4],
  19805         soc_genreg,
  19806         16,
  19807         0,
  19808         0x15080100,
  19809         SOC_REG_FLAG_ARRAY,
  19810         0,
  19811         1,
  19812         soc_VOQFC_STATE_MERGE_GRP0r_fields,
  19813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19814         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19815         -1,
  19816         -1,
  19817     },
  19818 #endif /* chips */
  19819 
  19820 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19821     { /* SOC_REG_INT_VOQFC_STATE_MERGE_GRP1r */
  19822         soc_block_list[4],
  19823         soc_genreg,
  19824         16,
  19825         0,
  19826         0x15080110,
  19827         SOC_REG_FLAG_ARRAY,
  19828         0,
  19829         1,
  19830         soc_VOQFC_STATE_MERGE_GRP0r_fields,
  19831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19832         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19833         -1,
  19834         -1,
  19835     },
  19836 #endif /* chips */
  19837 
  19838 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19839     { /* SOC_REG_INT_VOQFC_STATE_MERGE_GRP2r */
  19840         soc_block_list[4],
  19841         soc_genreg,
  19842         16,
  19843         0,
  19844         0x15080120,
  19845         SOC_REG_FLAG_ARRAY,
  19846         0,
  19847         1,
  19848         soc_VOQFC_STATE_MERGE_GRP0r_fields,
  19849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19850         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19851         -1,
  19852         -1,
  19853     },
  19854 #endif /* chips */
  19855 
  19856 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19857     { /* SOC_REG_INT_VOQFC_STATE_MERGE_GRP3r */
  19858         soc_block_list[4],
  19859         soc_genreg,
  19860         16,
  19861         0,
  19862         0x15080130,
  19863         SOC_REG_FLAG_ARRAY,
  19864         0,
  19865         1,
  19866         soc_VOQFC_STATE_MERGE_GRP0r_fields,
  19867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19868         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19869         -1,
  19870         -1,
  19871     },
  19872 #endif /* chips */
  19873 
  19874 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19875     { /* SOC_REG_INT_VOQFC_STATE_MERGE_GRP4r */
  19876         soc_block_list[4],
  19877         soc_genreg,
  19878         16,
  19879         0,
  19880         0x15080140,
  19881         SOC_REG_FLAG_ARRAY,
  19882         0,
  19883         1,
  19884         soc_VOQFC_STATE_MERGE_GRP0r_fields,
  19885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19886         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19887         -1,
  19888         -1,
  19889     },
  19890 #endif /* chips */
  19891 
  19892 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19893     { /* SOC_REG_INT_VOQFC_STATE_MERGE_GRP5r */
  19894         soc_block_list[4],
  19895         soc_genreg,
  19896         16,
  19897         0,
  19898         0x15080150,
  19899         SOC_REG_FLAG_ARRAY,
  19900         0,
  19901         1,
  19902         soc_VOQFC_STATE_MERGE_GRP0r_fields,
  19903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19904         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19905         -1,
  19906         -1,
  19907     },
  19908 #endif /* chips */
  19909 
  19910 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19911     { /* SOC_REG_INT_VOQFC_STATE_MERGE_GRP6r */
  19912         soc_block_list[4],
  19913         soc_genreg,
  19914         16,
  19915         0,
  19916         0x15080160,
  19917         SOC_REG_FLAG_ARRAY,
  19918         0,
  19919         1,
  19920         soc_VOQFC_STATE_MERGE_GRP0r_fields,
  19921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19922         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19923         -1,
  19924         -1,
  19925     },
  19926 #endif /* chips */
  19927 
  19928 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19929     { /* SOC_REG_INT_VOQFC_STATE_MERGE_GRP7r */
  19930         soc_block_list[4],
  19931         soc_genreg,
  19932         16,
  19933         0,
  19934         0x15080170,
  19935         SOC_REG_FLAG_ARRAY,
  19936         0,
  19937         1,
  19938         soc_VOQFC_STATE_MERGE_GRP0r_fields,
  19939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19940         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  19941         -1,
  19942         -1,
  19943     },
  19944 #endif /* chips */
  19945 
  19946 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19947     { /* SOC_REG_INT_VOQFC_STATE_PORT0_64r */
  19948         soc_block_list[4],
  19949         soc_genreg,
  19950         1,
  19951         0,
  19952         0x15080180,
  19953         SOC_REG_FLAG_64_BITS,
  19954         0,
  19955         1,
  19956         soc_VOQFC_STATE_PORT0_64r_fields,
  19957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19958         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  19959         -1,
  19960         -1,
  19961     },
  19962 #endif /* chips */
  19963 
  19964 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19965     { /* SOC_REG_INT_VOQFC_STATE_PORT1_64r */
  19966         soc_block_list[4],
  19967         soc_genreg,
  19968         1,
  19969         0,
  19970         0x15080181,
  19971         SOC_REG_FLAG_64_BITS,
  19972         0,
  19973         1,
  19974         soc_VOQFC_STATE_PORT0_64r_fields,
  19975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19976         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  19977         -1,
  19978         -1,
  19979     },
  19980 #endif /* chips */
  19981 
  19982 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19983     { /* SOC_REG_INT_VOQFC_STATE_PORT2_64r */
  19984         soc_block_list[4],
  19985         soc_genreg,
  19986         1,
  19987         0,
  19988         0x15080182,
  19989         SOC_REG_FLAG_64_BITS,
  19990         0,
  19991         1,
  19992         soc_VOQFC_STATE_PORT0_64r_fields,
  19993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19994         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  19995         -1,
  19996         -1,
  19997     },
  19998 #endif /* chips */
  19999 
  20000 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20001     { /* SOC_REG_INT_VOQFC_STATE_PORT3_64r */
  20002         soc_block_list[4],
  20003         soc_genreg,
  20004         1,
  20005         0,
  20006         0x15080183,
  20007         SOC_REG_FLAG_64_BITS,
  20008         0,
  20009         1,
  20010         soc_VOQFC_STATE_PORT0_64r_fields,
  20011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20012         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  20013         -1,
  20014         -1,
  20015     },
  20016 #endif /* chips */
  20017 
  20018 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20019     { /* SOC_REG_INT_VOQFC_STATE_PORT4_64r */
  20020         soc_block_list[4],
  20021         soc_genreg,
  20022         1,
  20023         0,
  20024         0x15080184,
  20025         SOC_REG_FLAG_64_BITS,
  20026         0,
  20027         1,
  20028         soc_VOQFC_STATE_PORT0_64r_fields,
  20029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20030         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  20031         -1,
  20032         -1,
  20033     },
  20034 #endif /* chips */
  20035 
  20036 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20037     { /* SOC_REG_INT_VOQFC_STATE_PORT5_64r */
  20038         soc_block_list[4],
  20039         soc_genreg,
  20040         1,
  20041         0,
  20042         0x15080185,
  20043         SOC_REG_FLAG_64_BITS,
  20044         0,
  20045         1,
  20046         soc_VOQFC_STATE_PORT0_64r_fields,
  20047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20048         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  20049         -1,
  20050         -1,
  20051     },
  20052 #endif /* chips */
  20053 
  20054 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20055     { /* SOC_REG_INT_VOQFC_STATE_PORT6_64r */
  20056         soc_block_list[4],
  20057         soc_genreg,
  20058         1,
  20059         0,
  20060         0x15080186,
  20061         SOC_REG_FLAG_64_BITS,
  20062         0,
  20063         1,
  20064         soc_VOQFC_STATE_PORT0_64r_fields,
  20065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20066         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  20067         -1,
  20068         -1,
  20069     },
  20070 #endif /* chips */
  20071 
  20072 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20073     { /* SOC_REG_INT_VOQFC_STATE_PORT7_64r */
  20074         soc_block_list[4],
  20075         soc_genreg,
  20076         1,
  20077         0,
  20078         0x15080187,
  20079         SOC_REG_FLAG_64_BITS,
  20080         0,
  20081         1,
  20082         soc_VOQFC_STATE_PORT0_64r_fields,
  20083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20084         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  20085         -1,
  20086         -1,
  20087     },
  20088 #endif /* chips */
  20089 
  20090 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20091     { /* SOC_REG_INT_VOQ_COS_MAP_PARITY_CONTROLr */
  20092         soc_block_list[5],
  20093         soc_genreg,
  20094         1,
  20095         0,
  20096         0xf080d4f,
  20097         0,
  20098         0,
  20099         1,
  20100         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  20101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20102         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20103         -1,
  20104         -1,
  20105     },
  20106 #endif /* chips */
  20107 
  20108 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20109     { /* SOC_REG_INT_VOQ_COS_MAP_PARITY_STATUS_INTRr */
  20110         soc_block_list[5],
  20111         soc_genreg,
  20112         1,
  20113         0,
  20114         0xf080d50,
  20115         0,
  20116         0,
  20117         3,
  20118         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  20119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20120         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20121         -1,
  20122         -1,
  20123     },
  20124 #endif /* chips */
  20125 
  20126 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20127     { /* SOC_REG_INT_VOQ_COS_MAP_PARITY_STATUS_NACKr */
  20128         soc_block_list[5],
  20129         soc_genreg,
  20130         1,
  20131         0,
  20132         0xf080d51,
  20133         0,
  20134         0,
  20135         3,
  20136         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  20137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20138         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20139         -1,
  20140         -1,
  20141     },
  20142 #endif /* chips */
  20143 
  20144 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20145     { /* SOC_REG_INT_VOQ_WRED_AVG_QSIZEr */
  20146         soc_block_list[4],
  20147         soc_portreg,
  20148         72,
  20149         0,
  20150         0x17000200,
  20151         SOC_REG_FLAG_ARRAY,
  20152         0,
  20153         3,
  20154         soc_GLOBAL_SP_WRED_AVG_QSIZEr_fields,
  20155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20157         -1,
  20158         45,
  20159     },
  20160 #endif /* chips */
  20161 
  20162 #if defined(BCM_56850_A0)
  20163     { /* SOC_REG_INT_VP_CAM_DBGCTRLr */
  20164         soc_block_list[5],
  20165         soc_genreg,
  20166         1,
  20167         0,
  20168         0x53000000,
  20169         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20170         0,
  20171         1,
  20172         soc_VP_CAM_DBGCTRLr_fields,
  20173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20174         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20175         -1,
  20176         -1,
  20177     },
  20178 #endif /* chips */
  20179 
  20180 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  20181     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  20182     { /* SOC_REG_INT_VP_CAM_DBGCTRL_BCM56560_A0r */
  20183         soc_block_list[5],
  20184         soc_genreg,
  20185         1,
  20186         0,
  20187         0x63000000,
  20188         0,
  20189         0,
  20190         2,
  20191         soc_VP_CAM_DBGCTRL_BCM56560_A0r_fields,
  20192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20193         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20194         -1,
  20195         -1,
  20196     },
  20197 #endif /* chips */
  20198 
  20199 #if defined(BCM_56860_A0)
  20200     { /* SOC_REG_INT_VP_CAM_DBGCTRL_BCM56860_A0r */
  20201         soc_block_list[5],
  20202         soc_genreg,
  20203         1,
  20204         0,
  20205         0x63000000,
  20206         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20207         0,
  20208         2,
  20209         soc_VP_CAM_DBGCTRL_BCM56860_A0r_fields,
  20210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20211         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20212         -1,
  20213         -1,
  20214     },
  20215 #endif /* chips */
  20216 
  20217 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  20218     defined(BCM_56870_A0)
  20219     { /* SOC_REG_INT_VP_CAM_DBGCTRL_BCM56870_A0r */
  20220         soc_block_list[5],
  20221         soc_genreg,
  20222         1,
  20223         0,
  20224         0x5b030000,
  20225         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20226         0,
  20227         2,
  20228         soc_VP_CAM_DBGCTRL_BCM56870_A0r_fields,
  20229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20230         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20231         -1,
  20232         -1,
  20233         0,
  20234     },
  20235 #endif /* chips */
  20236 
  20237 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20238     { /* SOC_REG_INT_VP_CAM_DBGCTRL_BCM56960_A0r */
  20239         soc_block_list[5],
  20240         soc_genreg,
  20241         1,
  20242         0,
  20243         0x37010000,
  20244         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20245         0,
  20246         2,
  20247         soc_VP_CAM_DBGCTRL_BCM56960_A0r_fields,
  20248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20250         -1,
  20251         -1,
  20252         0,
  20253     },
  20254 #endif /* chips */
  20255 
  20256 #if defined(BCM_56970_A0)
  20257     { /* SOC_REG_INT_VP_CAM_DBGCTRL_BCM56970_A0r */
  20258         soc_block_list[5],
  20259         soc_genreg,
  20260         1,
  20261         0,
  20262         0x5b010000,
  20263         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20264         0,
  20265         3,
  20266         soc_VP_CAM_DBGCTRL_BCM56970_A0r_fields,
  20267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20268         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20269         -1,
  20270         -1,
  20271         0,
  20272     },
  20273 #endif /* chips */
  20274 
  20275 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20276     { /* SOC_REG_INT_VP_CAM_DBGCTRL_PIPE0r */
  20277         soc_block_list[5],
  20278         soc_genreg,
  20279         1,
  20280         0,
  20281         0x37010000,
  20282         0,
  20283         0,
  20284         2,
  20285         soc_VP_CAM_DBGCTRL_BCM56960_A0r_fields,
  20286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20287         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20288         -1,
  20289         -1,
  20290         0,
  20291     },
  20292 #endif /* chips */
  20293 
  20294 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20295     { /* SOC_REG_INT_VP_CAM_DBGCTRL_PIPE1r */
  20296         soc_block_list[5],
  20297         soc_genreg,
  20298         1,
  20299         0,
  20300         0x37010000,
  20301         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20302         0,
  20303         2,
  20304         soc_VP_CAM_DBGCTRL_BCM56960_A0r_fields,
  20305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20307         -1,
  20308         -1,
  20309         0,
  20310     },
  20311 #endif /* chips */
  20312 
  20313 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20314     { /* SOC_REG_INT_VP_CAM_DBGCTRL_PIPE2r */
  20315         soc_block_list[5],
  20316         soc_genreg,
  20317         1,
  20318         0,
  20319         0x37010000,
  20320         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20321         0,
  20322         2,
  20323         soc_VP_CAM_DBGCTRL_BCM56960_A0r_fields,
  20324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20326         -1,
  20327         -1,
  20328         0,
  20329     },
  20330 #endif /* chips */
  20331 
  20332 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20333     { /* SOC_REG_INT_VP_CAM_DBGCTRL_PIPE3r */
  20334         soc_block_list[5],
  20335         soc_genreg,
  20336         1,
  20337         0,
  20338         0x37010000,
  20339         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20340         0,
  20341         2,
  20342         soc_VP_CAM_DBGCTRL_BCM56960_A0r_fields,
  20343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20344         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20345         -1,
  20346         -1,
  20347         0,
  20348     },
  20349 #endif /* chips */
  20350 
  20351 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  20352     defined(BCM_56870_A0)
  20353     { /* SOC_REG_INT_VP_CAM_DBGCTRL_PIPE0_BCM56870_A0r */
  20354         soc_block_list[5],
  20355         soc_genreg,
  20356         1,
  20357         0,
  20358         0x5b030000,
  20359         0,
  20360         0,
  20361         2,
  20362         soc_VP_CAM_DBGCTRL_BCM56870_A0r_fields,
  20363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20364         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20365         -1,
  20366         -1,
  20367         0,
  20368     },
  20369 #endif /* chips */
  20370 
  20371 #if defined(BCM_56970_A0)
  20372     { /* SOC_REG_INT_VP_CAM_DBGCTRL_PIPE0_BCM56970_A0r */
  20373         soc_block_list[5],
  20374         soc_genreg,
  20375         1,
  20376         0,
  20377         0x5b010000,
  20378         0,
  20379         0,
  20380         3,
  20381         soc_VP_CAM_DBGCTRL_BCM56970_A0r_fields,
  20382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20384         -1,
  20385         -1,
  20386         0,
  20387     },
  20388 #endif /* chips */
  20389 
  20390 #if defined(BCM_56870_A0)
  20391     { /* SOC_REG_INT_VP_CAM_DBGCTRL_PIPE1_BCM56870_A0r */
  20392         soc_block_list[5],
  20393         soc_genreg,
  20394         1,
  20395         0,
  20396         0x5b030000,
  20397         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20398         0,
  20399         2,
  20400         soc_VP_CAM_DBGCTRL_BCM56870_A0r_fields,
  20401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20402         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20403         -1,
  20404         -1,
  20405         0,
  20406     },
  20407 #endif /* chips */
  20408 
  20409 #if defined(BCM_56970_A0)
  20410     { /* SOC_REG_INT_VP_CAM_DBGCTRL_PIPE1_BCM56970_A0r */
  20411         soc_block_list[5],
  20412         soc_genreg,
  20413         1,
  20414         0,
  20415         0x5b010000,
  20416         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20417         0,
  20418         3,
  20419         soc_VP_CAM_DBGCTRL_BCM56970_A0r_fields,
  20420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20421         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20422         -1,
  20423         -1,
  20424         0,
  20425     },
  20426 #endif /* chips */
  20427 
  20428 #if defined(BCM_56970_A0)
  20429     { /* SOC_REG_INT_VP_CAM_DBGCTRL_PIPE2_BCM56970_A0r */
  20430         soc_block_list[5],
  20431         soc_genreg,
  20432         1,
  20433         0,
  20434         0x5b010000,
  20435         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20436         0,
  20437         3,
  20438         soc_VP_CAM_DBGCTRL_BCM56970_A0r_fields,
  20439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20440         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20441         -1,
  20442         -1,
  20443         0,
  20444     },
  20445 #endif /* chips */
  20446 
  20447 #if defined(BCM_56970_A0)
  20448     { /* SOC_REG_INT_VP_CAM_DBGCTRL_PIPE3_BCM56970_A0r */
  20449         soc_block_list[5],
  20450         soc_genreg,
  20451         1,
  20452         0,
  20453         0x5b010000,
  20454         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20455         0,
  20456         3,
  20457         soc_VP_CAM_DBGCTRL_BCM56970_A0r_fields,
  20458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20459         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20460         -1,
  20461         -1,
  20462         0,
  20463     },
  20464 #endif /* chips */
  20465 
  20466 #if defined(BCM_56860_A0)
  20467     { /* SOC_REG_INT_VP_GROUP_CHECK_ENABLEr */
  20468         soc_block_list[5],
  20469         soc_genreg,
  20470         1,
  20471         0,
  20472         0x16005800,
  20473         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20474         0,
  20475         1,
  20476         soc_VP_GROUP_CHECK_ENABLEr_fields,
  20477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20478         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20479         -1,
  20480         -1,
  20481     },
  20482 #endif /* chips */
  20483 
  20484 #if defined(BCM_56370_A0)
  20485     { /* SOC_REG_INT_VP_GROUP_CHECK_ENABLE_BCM56370_A0r */
  20486         soc_block_list[5],
  20487         soc_genreg,
  20488         1,
  20489         0,
  20490         0x66000700,
  20491         0,
  20492         0,
  20493         1,
  20494         soc_VP_GROUP_CHECK_ENABLE_BCM56560_A0r_fields,
  20495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20496         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20497         -1,
  20498         -1,
  20499         3,
  20500     },
  20501 #endif /* chips */
  20502 
  20503 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  20504     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  20505     { /* SOC_REG_INT_VP_GROUP_CHECK_ENABLE_BCM56560_A0r */
  20506         soc_block_list[5],
  20507         soc_genreg,
  20508         1,
  20509         0,
  20510         0x16005800,
  20511         0,
  20512         0,
  20513         1,
  20514         soc_VP_GROUP_CHECK_ENABLE_BCM56560_A0r_fields,
  20515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20516         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20517         -1,
  20518         -1,
  20519     },
  20520 #endif /* chips */
  20521 
  20522 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  20523     { /* SOC_REG_INT_VP_GROUP_CHECK_ENABLE_BCM56870_A0r */
  20524         soc_block_list[5],
  20525         soc_genreg,
  20526         1,
  20527         0,
  20528         0x66000600,
  20529         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20530         0,
  20531         1,
  20532         soc_VP_GROUP_CHECK_ENABLE_BCM56560_A0r_fields,
  20533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20534         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20535         -1,
  20536         -1,
  20537         3,
  20538     },
  20539 #endif /* chips */
  20540 
  20541 #if defined(BCM_56850_A0)
  20542     { /* SOC_REG_INT_VP_RAM_CONTROL_0r */
  20543         soc_block_list[5],
  20544         soc_genreg,
  20545         1,
  20546         0,
  20547         0x53060000,
  20548         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20549         0,
  20550         8,
  20551         soc_VP_RAM_CONTROL_0r_fields,
  20552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20553         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20554         -1,
  20555         -1,
  20556     },
  20557 #endif /* chips */
  20558 
  20559 #if defined(BCM_56850_A0)
  20560     { /* SOC_REG_INT_VP_RAM_CONTROL_1r */
  20561         soc_block_list[5],
  20562         soc_genreg,
  20563         1,
  20564         0,
  20565         0x53070000,
  20566         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20567         0,
  20568         10,
  20569         soc_VP_RAM_CONTROL_1r_fields,
  20570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20571         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20572         -1,
  20573         -1,
  20574     },
  20575 #endif /* chips */
  20576 
  20577 #if defined(BCM_56850_A0)
  20578     { /* SOC_REG_INT_VP_RAM_CONTROL_2r */
  20579         soc_block_list[5],
  20580         soc_genreg,
  20581         1,
  20582         0,
  20583         0x53080000,
  20584         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20585         0,
  20586         6,
  20587         soc_VP_RAM_CONTROL_2r_fields,
  20588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20589         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20590         -1,
  20591         -1,
  20592     },
  20593 #endif /* chips */
  20594 
  20595 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20596     { /* SOC_REG_INT_VP_RAM_CONTROL_3r */
  20597         soc_block_list[5],
  20598         soc_genreg,
  20599         1,
  20600         0,
  20601         0x37090000,
  20602         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20603         0,
  20604         3,
  20605         soc_VP_RAM_CONTROL_3r_fields,
  20606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20607         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20608         -1,
  20609         -1,
  20610         0,
  20611     },
  20612 #endif /* chips */
  20613 
  20614 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20615     { /* SOC_REG_INT_VP_RAM_CONTROL_4r */
  20616         soc_block_list[5],
  20617         soc_genreg,
  20618         1,
  20619         0,
  20620         0x370a0000,
  20621         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20622         0,
  20623         3,
  20624         soc_VP_RAM_CONTROL_4r_fields,
  20625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20626         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20627         -1,
  20628         -1,
  20629         0,
  20630     },
  20631 #endif /* chips */
  20632 
  20633 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20634     { /* SOC_REG_INT_VP_RAM_CONTROL_5r */
  20635         soc_block_list[5],
  20636         soc_genreg,
  20637         1,
  20638         0,
  20639         0x370b0000,
  20640         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20641         0,
  20642         1,
  20643         soc_VP_RAM_CONTROL_5r_fields,
  20644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20646         -1,
  20647         -1,
  20648         0,
  20649     },
  20650 #endif /* chips */
  20651 
  20652 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20653     { /* SOC_REG_INT_VP_RAM_CONTROL_6r */
  20654         soc_block_list[5],
  20655         soc_genreg,
  20656         1,
  20657         0,
  20658         0x370c0000,
  20659         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20660         0,
  20661         3,
  20662         soc_VP_RAM_CONTROL_6r_fields,
  20663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20664         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20665         -1,
  20666         -1,
  20667         0,
  20668     },
  20669 #endif /* chips */
  20670 
  20671 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20672     { /* SOC_REG_INT_VP_RAM_CONTROL_7r */
  20673         soc_block_list[5],
  20674         soc_genreg,
  20675         1,
  20676         0,
  20677         0x370d0000,
  20678         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20679         0,
  20680         2,
  20681         soc_VP_RAM_CONTROL_7r_fields,
  20682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20683         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20684         -1,
  20685         -1,
  20686         0,
  20687     },
  20688 #endif /* chips */
  20689 
  20690 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20691     { /* SOC_REG_INT_VP_RAM_CONTROL_8r */
  20692         soc_block_list[5],
  20693         soc_genreg,
  20694         1,
  20695         0,
  20696         0x370e0000,
  20697         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20698         0,
  20699         1,
  20700         soc_VP_RAM_CONTROL_8r_fields,
  20701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20702         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20703         -1,
  20704         -1,
  20705         0,
  20706     },
  20707 #endif /* chips */
  20708 
  20709 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  20710     { /* SOC_REG_INT_VP_RAM_CONTROL_0_BCM56560_A0r */
  20711         soc_block_list[5],
  20712         soc_genreg,
  20713         1,
  20714         0,
  20715         0x63060000,
  20716         SOC_REG_FLAG_64_BITS,
  20717         0,
  20718         8,
  20719         soc_VP_RAM_CONTROL_0_BCM56560_A0r_fields,
  20720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20721         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20722         -1,
  20723         -1,
  20724     },
  20725 #endif /* chips */
  20726 
  20727 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  20728     { /* SOC_REG_INT_VP_RAM_CONTROL_0_BCM56670_A0r */
  20729         soc_block_list[5],
  20730         soc_genreg,
  20731         1,
  20732         0,
  20733         0x63060000,
  20734         SOC_REG_FLAG_64_BITS,
  20735         0,
  20736         6,
  20737         soc_VP_RAM_CONTROL_0_BCM56670_A0r_fields,
  20738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20739         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20740         -1,
  20741         -1,
  20742     },
  20743 #endif /* chips */
  20744 
  20745 #if defined(BCM_56860_A0)
  20746     { /* SOC_REG_INT_VP_RAM_CONTROL_0_BCM56860_A0r */
  20747         soc_block_list[5],
  20748         soc_genreg,
  20749         1,
  20750         0,
  20751         0x63060000,
  20752         SOC_REG_FLAG_64_BITS |
  20753                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20754         0,
  20755         8,
  20756         soc_VP_RAM_CONTROL_0_BCM56860_A0r_fields,
  20757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20758         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20759         -1,
  20760         -1,
  20761     },
  20762 #endif /* chips */
  20763 
  20764 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20765     { /* SOC_REG_INT_VP_RAM_CONTROL_0_BCM56960_A0r */
  20766         soc_block_list[5],
  20767         soc_genreg,
  20768         1,
  20769         0,
  20770         0x37060000,
  20771         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20772         0,
  20773         3,
  20774         soc_VP_RAM_CONTROL_0_BCM56960_A0r_fields,
  20775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20776         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20777         -1,
  20778         -1,
  20779         0,
  20780     },
  20781 #endif /* chips */
  20782 
  20783 #if defined(BCM_56970_A0)
  20784     { /* SOC_REG_INT_VP_RAM_CONTROL_0_BCM56970_A0r */
  20785         soc_block_list[5],
  20786         soc_genreg,
  20787         1,
  20788         0,
  20789         0x5b060000,
  20790         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20791         0,
  20792         3,
  20793         soc_VP_RAM_CONTROL_0_BCM56970_A0r_fields,
  20794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20795         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20796         -1,
  20797         -1,
  20798         0,
  20799     },
  20800 #endif /* chips */
  20801 
  20802 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20803     { /* SOC_REG_INT_VP_RAM_CONTROL_0_PIPE0r */
  20804         soc_block_list[5],
  20805         soc_genreg,
  20806         1,
  20807         0,
  20808         0x37060000,
  20809         0,
  20810         0,
  20811         3,
  20812         soc_VP_RAM_CONTROL_0_BCM56960_A0r_fields,
  20813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20814         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20815         -1,
  20816         -1,
  20817         0,
  20818     },
  20819 #endif /* chips */
  20820 
  20821 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20822     { /* SOC_REG_INT_VP_RAM_CONTROL_0_PIPE1r */
  20823         soc_block_list[5],
  20824         soc_genreg,
  20825         1,
  20826         0,
  20827         0x37060000,
  20828         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20829         0,
  20830         3,
  20831         soc_VP_RAM_CONTROL_0_BCM56960_A0r_fields,
  20832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20833         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20834         -1,
  20835         -1,
  20836         0,
  20837     },
  20838 #endif /* chips */
  20839 
  20840 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20841     { /* SOC_REG_INT_VP_RAM_CONTROL_0_PIPE2r */
  20842         soc_block_list[5],
  20843         soc_genreg,
  20844         1,
  20845         0,
  20846         0x37060000,
  20847         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20848         0,
  20849         3,
  20850         soc_VP_RAM_CONTROL_0_BCM56960_A0r_fields,
  20851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20852         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20853         -1,
  20854         -1,
  20855         0,
  20856     },
  20857 #endif /* chips */
  20858 
  20859 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20860     { /* SOC_REG_INT_VP_RAM_CONTROL_0_PIPE3r */
  20861         soc_block_list[5],
  20862         soc_genreg,
  20863         1,
  20864         0,
  20865         0x37060000,
  20866         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20867         0,
  20868         3,
  20869         soc_VP_RAM_CONTROL_0_BCM56960_A0r_fields,
  20870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20871         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20872         -1,
  20873         -1,
  20874         0,
  20875     },
  20876 #endif /* chips */
  20877 
  20878 #if defined(BCM_56970_A0)
  20879     { /* SOC_REG_INT_VP_RAM_CONTROL_0_PIPE0_BCM56970_A0r */
  20880         soc_block_list[5],
  20881         soc_genreg,
  20882         1,
  20883         0,
  20884         0x5b060000,
  20885         0,
  20886         0,
  20887         3,
  20888         soc_VP_RAM_CONTROL_0_BCM56970_A0r_fields,
  20889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20890         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20891         -1,
  20892         -1,
  20893         0,
  20894     },
  20895 #endif /* chips */
  20896 
  20897 #if defined(BCM_56970_A0)
  20898     { /* SOC_REG_INT_VP_RAM_CONTROL_0_PIPE1_BCM56970_A0r */
  20899         soc_block_list[5],
  20900         soc_genreg,
  20901         1,
  20902         0,
  20903         0x5b060000,
  20904         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20905         0,
  20906         3,
  20907         soc_VP_RAM_CONTROL_0_BCM56970_A0r_fields,
  20908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20909         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20910         -1,
  20911         -1,
  20912         0,
  20913     },
  20914 #endif /* chips */
  20915 
  20916 #if defined(BCM_56970_A0)
  20917     { /* SOC_REG_INT_VP_RAM_CONTROL_0_PIPE2_BCM56970_A0r */
  20918         soc_block_list[5],
  20919         soc_genreg,
  20920         1,
  20921         0,
  20922         0x5b060000,
  20923         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20924         0,
  20925         3,
  20926         soc_VP_RAM_CONTROL_0_BCM56970_A0r_fields,
  20927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20928         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20929         -1,
  20930         -1,
  20931         0,
  20932     },
  20933 #endif /* chips */
  20934 
  20935 #if defined(BCM_56970_A0)
  20936     { /* SOC_REG_INT_VP_RAM_CONTROL_0_PIPE3_BCM56970_A0r */
  20937         soc_block_list[5],
  20938         soc_genreg,
  20939         1,
  20940         0,
  20941         0x5b060000,
  20942         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20943         0,
  20944         3,
  20945         soc_VP_RAM_CONTROL_0_BCM56970_A0r_fields,
  20946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20947         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20948         -1,
  20949         -1,
  20950         0,
  20951     },
  20952 #endif /* chips */
  20953 
  20954 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  20955     { /* SOC_REG_INT_VP_RAM_CONTROL_1_BCM56560_A0r */
  20956         soc_block_list[5],
  20957         soc_genreg,
  20958         1,
  20959         0,
  20960         0x63070000,
  20961         SOC_REG_FLAG_64_BITS,
  20962         0,
  20963         6,
  20964         soc_VP_RAM_CONTROL_1_BCM56560_A0r_fields,
  20965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20966         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20967         -1,
  20968         -1,
  20969     },
  20970 #endif /* chips */
  20971 
  20972 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  20973     { /* SOC_REG_INT_VP_RAM_CONTROL_1_BCM56670_A0r */
  20974         soc_block_list[5],
  20975         soc_genreg,
  20976         1,
  20977         0,
  20978         0x63070000,
  20979         SOC_REG_FLAG_64_BITS,
  20980         0,
  20981         4,
  20982         soc_VP_RAM_CONTROL_1_BCM56670_A0r_fields,
  20983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20984         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20985         -1,
  20986         -1,
  20987     },
  20988 #endif /* chips */
  20989 
  20990 #if defined(BCM_56860_A0)
  20991     { /* SOC_REG_INT_VP_RAM_CONTROL_1_BCM56860_A0r */
  20992         soc_block_list[5],
  20993         soc_genreg,
  20994         1,
  20995         0,
  20996         0x63070000,
  20997         SOC_REG_FLAG_64_BITS |
  20998                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20999         0,
  21000         6,
  21001         soc_VP_RAM_CONTROL_1_BCM56860_A0r_fields,
  21002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21003         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21004         -1,
  21005         -1,
  21006     },
  21007 #endif /* chips */
  21008 
  21009 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21010     { /* SOC_REG_INT_VP_RAM_CONTROL_1_BCM56960_A0r */
  21011         soc_block_list[5],
  21012         soc_genreg,
  21013         1,
  21014         0,
  21015         0x37070000,
  21016         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21017         0,
  21018         1,
  21019         soc_VP_RAM_CONTROL_1_BCM56960_A0r_fields,
  21020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21021         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21022         -1,
  21023         -1,
  21024         0,
  21025     },
  21026 #endif /* chips */
  21027 
  21028 #if defined(BCM_56970_A0)
  21029     { /* SOC_REG_INT_VP_RAM_CONTROL_1_BCM56970_A0r */
  21030         soc_block_list[5],
  21031         soc_genreg,
  21032         1,
  21033         0,
  21034         0x5b070000,
  21035         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21036         0,
  21037         1,
  21038         soc_VP_RAM_CONTROL_1_BCM56970_A0r_fields,
  21039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21040         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21041         -1,
  21042         -1,
  21043         0,
  21044     },
  21045 #endif /* chips */
  21046 
  21047 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21048     { /* SOC_REG_INT_VP_RAM_CONTROL_1_PIPE0r */
  21049         soc_block_list[5],
  21050         soc_genreg,
  21051         1,
  21052         0,
  21053         0x37070000,
  21054         0,
  21055         0,
  21056         1,
  21057         soc_VP_RAM_CONTROL_1_BCM56960_A0r_fields,
  21058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21059         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21060         -1,
  21061         -1,
  21062         0,
  21063     },
  21064 #endif /* chips */
  21065 
  21066 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21067     { /* SOC_REG_INT_VP_RAM_CONTROL_1_PIPE1r */
  21068         soc_block_list[5],
  21069         soc_genreg,
  21070         1,
  21071         0,
  21072         0x37070000,
  21073         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21074         0,
  21075         1,
  21076         soc_VP_RAM_CONTROL_1_BCM56960_A0r_fields,
  21077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21078         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21079         -1,
  21080         -1,
  21081         0,
  21082     },
  21083 #endif /* chips */
  21084 
  21085 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21086     { /* SOC_REG_INT_VP_RAM_CONTROL_1_PIPE2r */
  21087         soc_block_list[5],
  21088         soc_genreg,
  21089         1,
  21090         0,
  21091         0x37070000,
  21092         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21093         0,
  21094         1,
  21095         soc_VP_RAM_CONTROL_1_BCM56960_A0r_fields,
  21096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21097         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21098         -1,
  21099         -1,
  21100         0,
  21101     },
  21102 #endif /* chips */
  21103 
  21104 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21105     { /* SOC_REG_INT_VP_RAM_CONTROL_1_PIPE3r */
  21106         soc_block_list[5],
  21107         soc_genreg,
  21108         1,
  21109         0,
  21110         0x37070000,
  21111         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21112         0,
  21113         1,
  21114         soc_VP_RAM_CONTROL_1_BCM56960_A0r_fields,
  21115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21116         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21117         -1,
  21118         -1,
  21119         0,
  21120     },
  21121 #endif /* chips */
  21122 
  21123 #if defined(BCM_56970_A0)
  21124     { /* SOC_REG_INT_VP_RAM_CONTROL_1_PIPE0_BCM56970_A0r */
  21125         soc_block_list[5],
  21126         soc_genreg,
  21127         1,
  21128         0,
  21129         0x5b070000,
  21130         0,
  21131         0,
  21132         1,
  21133         soc_VP_RAM_CONTROL_1_BCM56970_A0r_fields,
  21134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21135         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21136         -1,
  21137         -1,
  21138         0,
  21139     },
  21140 #endif /* chips */
  21141 
  21142 #if defined(BCM_56970_A0)
  21143     { /* SOC_REG_INT_VP_RAM_CONTROL_1_PIPE1_BCM56970_A0r */
  21144         soc_block_list[5],
  21145         soc_genreg,
  21146         1,
  21147         0,
  21148         0x5b070000,
  21149         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21150         0,
  21151         1,
  21152         soc_VP_RAM_CONTROL_1_BCM56970_A0r_fields,
  21153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21154         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21155         -1,
  21156         -1,
  21157         0,
  21158     },
  21159 #endif /* chips */
  21160 
  21161 #if defined(BCM_56970_A0)
  21162     { /* SOC_REG_INT_VP_RAM_CONTROL_1_PIPE2_BCM56970_A0r */
  21163         soc_block_list[5],
  21164         soc_genreg,
  21165         1,
  21166         0,
  21167         0x5b070000,
  21168         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21169         0,
  21170         1,
  21171         soc_VP_RAM_CONTROL_1_BCM56970_A0r_fields,
  21172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21174         -1,
  21175         -1,
  21176         0,
  21177     },
  21178 #endif /* chips */
  21179 
  21180 #if defined(BCM_56970_A0)
  21181     { /* SOC_REG_INT_VP_RAM_CONTROL_1_PIPE3_BCM56970_A0r */
  21182         soc_block_list[5],
  21183         soc_genreg,
  21184         1,
  21185         0,
  21186         0x5b070000,
  21187         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21188         0,
  21189         1,
  21190         soc_VP_RAM_CONTROL_1_BCM56970_A0r_fields,
  21191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21192         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21193         -1,
  21194         -1,
  21195         0,
  21196     },
  21197 #endif /* chips */
  21198 
  21199 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21200     { /* SOC_REG_INT_VP_RAM_CONTROL_2_BCM56960_A0r */
  21201         soc_block_list[5],
  21202         soc_genreg,
  21203         1,
  21204         0,
  21205         0x37080000,
  21206         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21207         0,
  21208         2,
  21209         soc_VP_RAM_CONTROL_2_BCM56960_A0r_fields,
  21210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21211         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21212         -1,
  21213         -1,
  21214         0,
  21215     },
  21216 #endif /* chips */
  21217 
  21218 #if defined(BCM_56970_A0)
  21219     { /* SOC_REG_INT_VP_RAM_CONTROL_2_BCM56970_A0r */
  21220         soc_block_list[5],
  21221         soc_genreg,
  21222         1,
  21223         0,
  21224         0x5b080000,
  21225         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21226         0,
  21227         2,
  21228         soc_VP_RAM_CONTROL_2_BCM56970_A0r_fields,
  21229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21230         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21231         -1,
  21232         -1,
  21233         0,
  21234     },
  21235 #endif /* chips */
  21236 
  21237 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21238     { /* SOC_REG_INT_VP_RAM_CONTROL_2_PIPE0r */
  21239         soc_block_list[5],
  21240         soc_genreg,
  21241         1,
  21242         0,
  21243         0x37080000,
  21244         0,
  21245         0,
  21246         2,
  21247         soc_VP_RAM_CONTROL_2_BCM56960_A0r_fields,
  21248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21250         -1,
  21251         -1,
  21252         0,
  21253     },
  21254 #endif /* chips */
  21255 
  21256 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21257     { /* SOC_REG_INT_VP_RAM_CONTROL_2_PIPE1r */
  21258         soc_block_list[5],
  21259         soc_genreg,
  21260         1,
  21261         0,
  21262         0x37080000,
  21263         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21264         0,
  21265         2,
  21266         soc_VP_RAM_CONTROL_2_BCM56960_A0r_fields,
  21267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21268         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21269         -1,
  21270         -1,
  21271         0,
  21272     },
  21273 #endif /* chips */
  21274 
  21275 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21276     { /* SOC_REG_INT_VP_RAM_CONTROL_2_PIPE2r */
  21277         soc_block_list[5],
  21278         soc_genreg,
  21279         1,
  21280         0,
  21281         0x37080000,
  21282         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21283         0,
  21284         2,
  21285         soc_VP_RAM_CONTROL_2_BCM56960_A0r_fields,
  21286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21287         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21288         -1,
  21289         -1,
  21290         0,
  21291     },
  21292 #endif /* chips */
  21293 
  21294 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21295     { /* SOC_REG_INT_VP_RAM_CONTROL_2_PIPE3r */
  21296         soc_block_list[5],
  21297         soc_genreg,
  21298         1,
  21299         0,
  21300         0x37080000,
  21301         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21302         0,
  21303         2,
  21304         soc_VP_RAM_CONTROL_2_BCM56960_A0r_fields,
  21305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21307         -1,
  21308         -1,
  21309         0,
  21310     },
  21311 #endif /* chips */
  21312 
  21313 #if defined(BCM_56970_A0)
  21314     { /* SOC_REG_INT_VP_RAM_CONTROL_2_PIPE0_BCM56970_A0r */
  21315         soc_block_list[5],
  21316         soc_genreg,
  21317         1,
  21318         0,
  21319         0x5b080000,
  21320         0,
  21321         0,
  21322         2,
  21323         soc_VP_RAM_CONTROL_2_BCM56970_A0r_fields,
  21324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21326         -1,
  21327         -1,
  21328         0,
  21329     },
  21330 #endif /* chips */
  21331 
  21332 #if defined(BCM_56970_A0)
  21333     { /* SOC_REG_INT_VP_RAM_CONTROL_2_PIPE1_BCM56970_A0r */
  21334         soc_block_list[5],
  21335         soc_genreg,
  21336         1,
  21337         0,
  21338         0x5b080000,
  21339         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21340         0,
  21341         2,
  21342         soc_VP_RAM_CONTROL_2_BCM56970_A0r_fields,
  21343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21344         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21345         -1,
  21346         -1,
  21347         0,
  21348     },
  21349 #endif /* chips */
  21350 
  21351 #if defined(BCM_56970_A0)
  21352     { /* SOC_REG_INT_VP_RAM_CONTROL_2_PIPE2_BCM56970_A0r */
  21353         soc_block_list[5],
  21354         soc_genreg,
  21355         1,
  21356         0,
  21357         0x5b080000,
  21358         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21359         0,
  21360         2,
  21361         soc_VP_RAM_CONTROL_2_BCM56970_A0r_fields,
  21362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21363         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21364         -1,
  21365         -1,
  21366         0,
  21367     },
  21368 #endif /* chips */
  21369 
  21370 #if defined(BCM_56970_A0)
  21371     { /* SOC_REG_INT_VP_RAM_CONTROL_2_PIPE3_BCM56970_A0r */
  21372         soc_block_list[5],
  21373         soc_genreg,
  21374         1,
  21375         0,
  21376         0x5b080000,
  21377         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21378         0,
  21379         2,
  21380         soc_VP_RAM_CONTROL_2_BCM56970_A0r_fields,
  21381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21382         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21383         -1,
  21384         -1,
  21385         0,
  21386     },
  21387 #endif /* chips */
  21388 
  21389 #if defined(BCM_56970_A0)
  21390     { /* SOC_REG_INT_VP_RAM_CONTROL_3_BCM56970_A0r */
  21391         soc_block_list[5],
  21392         soc_genreg,
  21393         1,
  21394         0,
  21395         0x5b090000,
  21396         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21397         0,
  21398         3,
  21399         soc_VP_RAM_CONTROL_3r_fields,
  21400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21401         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21402         -1,
  21403         -1,
  21404         0,
  21405     },
  21406 #endif /* chips */
  21407 
  21408 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21409     { /* SOC_REG_INT_VP_RAM_CONTROL_3_PIPE0r */
  21410         soc_block_list[5],
  21411         soc_genreg,
  21412         1,
  21413         0,
  21414         0x37090000,
  21415         0,
  21416         0,
  21417         3,
  21418         soc_VP_RAM_CONTROL_3r_fields,
  21419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21420         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21421         -1,
  21422         -1,
  21423         0,
  21424     },
  21425 #endif /* chips */
  21426 
  21427 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21428     { /* SOC_REG_INT_VP_RAM_CONTROL_3_PIPE1r */
  21429         soc_block_list[5],
  21430         soc_genreg,
  21431         1,
  21432         0,
  21433         0x37090000,
  21434         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21435         0,
  21436         3,
  21437         soc_VP_RAM_CONTROL_3r_fields,
  21438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21439         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21440         -1,
  21441         -1,
  21442         0,
  21443     },
  21444 #endif /* chips */
  21445 
  21446 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21447     { /* SOC_REG_INT_VP_RAM_CONTROL_3_PIPE2r */
  21448         soc_block_list[5],
  21449         soc_genreg,
  21450         1,
  21451         0,
  21452         0x37090000,
  21453         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21454         0,
  21455         3,
  21456         soc_VP_RAM_CONTROL_3r_fields,
  21457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21458         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21459         -1,
  21460         -1,
  21461         0,
  21462     },
  21463 #endif /* chips */
  21464 
  21465 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21466     { /* SOC_REG_INT_VP_RAM_CONTROL_3_PIPE3r */
  21467         soc_block_list[5],
  21468         soc_genreg,
  21469         1,
  21470         0,
  21471         0x37090000,
  21472         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21473         0,
  21474         3,
  21475         soc_VP_RAM_CONTROL_3r_fields,
  21476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21477         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21478         -1,
  21479         -1,
  21480         0,
  21481     },
  21482 #endif /* chips */
  21483 
  21484 #if defined(BCM_56970_A0)
  21485     { /* SOC_REG_INT_VP_RAM_CONTROL_3_PIPE0_BCM56970_A0r */
  21486         soc_block_list[5],
  21487         soc_genreg,
  21488         1,
  21489         0,
  21490         0x5b090000,
  21491         0,
  21492         0,
  21493         3,
  21494         soc_VP_RAM_CONTROL_3r_fields,
  21495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21496         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21497         -1,
  21498         -1,
  21499         0,
  21500     },
  21501 #endif /* chips */
  21502 
  21503 #if defined(BCM_56970_A0)
  21504     { /* SOC_REG_INT_VP_RAM_CONTROL_3_PIPE1_BCM56970_A0r */
  21505         soc_block_list[5],
  21506         soc_genreg,
  21507         1,
  21508         0,
  21509         0x5b090000,
  21510         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21511         0,
  21512         3,
  21513         soc_VP_RAM_CONTROL_3r_fields,
  21514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21515         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21516         -1,
  21517         -1,
  21518         0,
  21519     },
  21520 #endif /* chips */
  21521 
  21522 #if defined(BCM_56970_A0)
  21523     { /* SOC_REG_INT_VP_RAM_CONTROL_3_PIPE2_BCM56970_A0r */
  21524         soc_block_list[5],
  21525         soc_genreg,
  21526         1,
  21527         0,
  21528         0x5b090000,
  21529         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21530         0,
  21531         3,
  21532         soc_VP_RAM_CONTROL_3r_fields,
  21533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21534         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21535         -1,
  21536         -1,
  21537         0,
  21538     },
  21539 #endif /* chips */
  21540 
  21541 #if defined(BCM_56970_A0)
  21542     { /* SOC_REG_INT_VP_RAM_CONTROL_3_PIPE3_BCM56970_A0r */
  21543         soc_block_list[5],
  21544         soc_genreg,
  21545         1,
  21546         0,
  21547         0x5b090000,
  21548         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21549         0,
  21550         3,
  21551         soc_VP_RAM_CONTROL_3r_fields,
  21552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21553         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21554         -1,
  21555         -1,
  21556         0,
  21557     },
  21558 #endif /* chips */
  21559 
  21560 #if defined(BCM_56970_A0)
  21561     { /* SOC_REG_INT_VP_RAM_CONTROL_4_BCM56970_A0r */
  21562         soc_block_list[5],
  21563         soc_genreg,
  21564         1,
  21565         0,
  21566         0x5b0a0000,
  21567         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21568         0,
  21569         3,
  21570         soc_VP_RAM_CONTROL_4r_fields,
  21571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21572         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21573         -1,
  21574         -1,
  21575         0,
  21576     },
  21577 #endif /* chips */
  21578 
  21579 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21580     { /* SOC_REG_INT_VP_RAM_CONTROL_4_PIPE0r */
  21581         soc_block_list[5],
  21582         soc_genreg,
  21583         1,
  21584         0,
  21585         0x370a0000,
  21586         0,
  21587         0,
  21588         3,
  21589         soc_VP_RAM_CONTROL_4r_fields,
  21590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21592         -1,
  21593         -1,
  21594         0,
  21595     },
  21596 #endif /* chips */
  21597 
  21598 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21599     { /* SOC_REG_INT_VP_RAM_CONTROL_4_PIPE1r */
  21600         soc_block_list[5],
  21601         soc_genreg,
  21602         1,
  21603         0,
  21604         0x370a0000,
  21605         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21606         0,
  21607         3,
  21608         soc_VP_RAM_CONTROL_4r_fields,
  21609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21610         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21611         -1,
  21612         -1,
  21613         0,
  21614     },
  21615 #endif /* chips */
  21616 
  21617 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21618     { /* SOC_REG_INT_VP_RAM_CONTROL_4_PIPE2r */
  21619         soc_block_list[5],
  21620         soc_genreg,
  21621         1,
  21622         0,
  21623         0x370a0000,
  21624         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21625         0,
  21626         3,
  21627         soc_VP_RAM_CONTROL_4r_fields,
  21628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21629         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21630         -1,
  21631         -1,
  21632         0,
  21633     },
  21634 #endif /* chips */
  21635 
  21636 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21637     { /* SOC_REG_INT_VP_RAM_CONTROL_4_PIPE3r */
  21638         soc_block_list[5],
  21639         soc_genreg,
  21640         1,
  21641         0,
  21642         0x370a0000,
  21643         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21644         0,
  21645         3,
  21646         soc_VP_RAM_CONTROL_4r_fields,
  21647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21649         -1,
  21650         -1,
  21651         0,
  21652     },
  21653 #endif /* chips */
  21654 
  21655 #if defined(BCM_56970_A0)
  21656     { /* SOC_REG_INT_VP_RAM_CONTROL_4_PIPE0_BCM56970_A0r */
  21657         soc_block_list[5],
  21658         soc_genreg,
  21659         1,
  21660         0,
  21661         0x5b0a0000,
  21662         0,
  21663         0,
  21664         3,
  21665         soc_VP_RAM_CONTROL_4r_fields,
  21666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21667         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21668         -1,
  21669         -1,
  21670         0,
  21671     },
  21672 #endif /* chips */
  21673 
  21674 #if defined(BCM_56970_A0)
  21675     { /* SOC_REG_INT_VP_RAM_CONTROL_4_PIPE1_BCM56970_A0r */
  21676         soc_block_list[5],
  21677         soc_genreg,
  21678         1,
  21679         0,
  21680         0x5b0a0000,
  21681         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21682         0,
  21683         3,
  21684         soc_VP_RAM_CONTROL_4r_fields,
  21685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21686         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21687         -1,
  21688         -1,
  21689         0,
  21690     },
  21691 #endif /* chips */
  21692 
  21693 #if defined(BCM_56970_A0)
  21694     { /* SOC_REG_INT_VP_RAM_CONTROL_4_PIPE2_BCM56970_A0r */
  21695         soc_block_list[5],
  21696         soc_genreg,
  21697         1,
  21698         0,
  21699         0x5b0a0000,
  21700         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21701         0,
  21702         3,
  21703         soc_VP_RAM_CONTROL_4r_fields,
  21704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21706         -1,
  21707         -1,
  21708         0,
  21709     },
  21710 #endif /* chips */
  21711 
  21712 #if defined(BCM_56970_A0)
  21713     { /* SOC_REG_INT_VP_RAM_CONTROL_4_PIPE3_BCM56970_A0r */
  21714         soc_block_list[5],
  21715         soc_genreg,
  21716         1,
  21717         0,
  21718         0x5b0a0000,
  21719         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21720         0,
  21721         3,
  21722         soc_VP_RAM_CONTROL_4r_fields,
  21723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21724         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21725         -1,
  21726         -1,
  21727         0,
  21728     },
  21729 #endif /* chips */
  21730 
  21731 #if defined(BCM_56970_A0)
  21732     { /* SOC_REG_INT_VP_RAM_CONTROL_5_BCM56970_A0r */
  21733         soc_block_list[5],
  21734         soc_genreg,
  21735         1,
  21736         0,
  21737         0x5b0b0000,
  21738         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21739         0,
  21740         1,
  21741         soc_VP_RAM_CONTROL_5_BCM56970_A0r_fields,
  21742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21743         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21744         -1,
  21745         -1,
  21746         0,
  21747     },
  21748 #endif /* chips */
  21749 
  21750 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21751     { /* SOC_REG_INT_VP_RAM_CONTROL_5_PIPE0r */
  21752         soc_block_list[5],
  21753         soc_genreg,
  21754         1,
  21755         0,
  21756         0x370b0000,
  21757         0,
  21758         0,
  21759         1,
  21760         soc_VP_RAM_CONTROL_5r_fields,
  21761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21762         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21763         -1,
  21764         -1,
  21765         0,
  21766     },
  21767 #endif /* chips */
  21768 
  21769 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21770     { /* SOC_REG_INT_VP_RAM_CONTROL_5_PIPE1r */
  21771         soc_block_list[5],
  21772         soc_genreg,
  21773         1,
  21774         0,
  21775         0x370b0000,
  21776         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21777         0,
  21778         1,
  21779         soc_VP_RAM_CONTROL_5r_fields,
  21780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21782         -1,
  21783         -1,
  21784         0,
  21785     },
  21786 #endif /* chips */
  21787 
  21788 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21789     { /* SOC_REG_INT_VP_RAM_CONTROL_5_PIPE2r */
  21790         soc_block_list[5],
  21791         soc_genreg,
  21792         1,
  21793         0,
  21794         0x370b0000,
  21795         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21796         0,
  21797         1,
  21798         soc_VP_RAM_CONTROL_5r_fields,
  21799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21800         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21801         -1,
  21802         -1,
  21803         0,
  21804     },
  21805 #endif /* chips */
  21806 
  21807 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21808     { /* SOC_REG_INT_VP_RAM_CONTROL_5_PIPE3r */
  21809         soc_block_list[5],
  21810         soc_genreg,
  21811         1,
  21812         0,
  21813         0x370b0000,
  21814         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21815         0,
  21816         1,
  21817         soc_VP_RAM_CONTROL_5r_fields,
  21818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21819         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21820         -1,
  21821         -1,
  21822         0,
  21823     },
  21824 #endif /* chips */
  21825 
  21826 #if defined(BCM_56970_A0)
  21827     { /* SOC_REG_INT_VP_RAM_CONTROL_5_PIPE0_BCM56970_A0r */
  21828         soc_block_list[5],
  21829         soc_genreg,
  21830         1,
  21831         0,
  21832         0x5b0b0000,
  21833         0,
  21834         0,
  21835         1,
  21836         soc_VP_RAM_CONTROL_5_BCM56970_A0r_fields,
  21837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21838         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21839         -1,
  21840         -1,
  21841         0,
  21842     },
  21843 #endif /* chips */
  21844 
  21845 #if defined(BCM_56970_A0)
  21846     { /* SOC_REG_INT_VP_RAM_CONTROL_5_PIPE1_BCM56970_A0r */
  21847         soc_block_list[5],
  21848         soc_genreg,
  21849         1,
  21850         0,
  21851         0x5b0b0000,
  21852         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21853         0,
  21854         1,
  21855         soc_VP_RAM_CONTROL_5_BCM56970_A0r_fields,
  21856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21857         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21858         -1,
  21859         -1,
  21860         0,
  21861     },
  21862 #endif /* chips */
  21863 
  21864 #if defined(BCM_56970_A0)
  21865     { /* SOC_REG_INT_VP_RAM_CONTROL_5_PIPE2_BCM56970_A0r */
  21866         soc_block_list[5],
  21867         soc_genreg,
  21868         1,
  21869         0,
  21870         0x5b0b0000,
  21871         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21872         0,
  21873         1,
  21874         soc_VP_RAM_CONTROL_5_BCM56970_A0r_fields,
  21875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21876         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21877         -1,
  21878         -1,
  21879         0,
  21880     },
  21881 #endif /* chips */
  21882 
  21883 #if defined(BCM_56970_A0)
  21884     { /* SOC_REG_INT_VP_RAM_CONTROL_5_PIPE3_BCM56970_A0r */
  21885         soc_block_list[5],
  21886         soc_genreg,
  21887         1,
  21888         0,
  21889         0x5b0b0000,
  21890         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21891         0,
  21892         1,
  21893         soc_VP_RAM_CONTROL_5_BCM56970_A0r_fields,
  21894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21895         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21896         -1,
  21897         -1,
  21898         0,
  21899     },
  21900 #endif /* chips */
  21901 
  21902 #if defined(BCM_56970_A0)
  21903     { /* SOC_REG_INT_VP_RAM_CONTROL_6_BCM56970_A0r */
  21904         soc_block_list[5],
  21905         soc_genreg,
  21906         1,
  21907         0,
  21908         0x5b0c0000,
  21909         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21910         0,
  21911         3,
  21912         soc_VP_RAM_CONTROL_6_BCM56970_A0r_fields,
  21913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21914         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21915         -1,
  21916         -1,
  21917         0,
  21918     },
  21919 #endif /* chips */
  21920 
  21921 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21922     { /* SOC_REG_INT_VP_RAM_CONTROL_6_PIPE0r */
  21923         soc_block_list[5],
  21924         soc_genreg,
  21925         1,
  21926         0,
  21927         0x370c0000,
  21928         0,
  21929         0,
  21930         3,
  21931         soc_VP_RAM_CONTROL_6r_fields,
  21932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21933         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21934         -1,
  21935         -1,
  21936         0,
  21937     },
  21938 #endif /* chips */
  21939 
  21940 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21941     { /* SOC_REG_INT_VP_RAM_CONTROL_6_PIPE1r */
  21942         soc_block_list[5],
  21943         soc_genreg,
  21944         1,
  21945         0,
  21946         0x370c0000,
  21947         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21948         0,
  21949         3,
  21950         soc_VP_RAM_CONTROL_6r_fields,
  21951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21952         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21953         -1,
  21954         -1,
  21955         0,
  21956     },
  21957 #endif /* chips */
  21958 
  21959 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21960     { /* SOC_REG_INT_VP_RAM_CONTROL_6_PIPE2r */
  21961         soc_block_list[5],
  21962         soc_genreg,
  21963         1,
  21964         0,
  21965         0x370c0000,
  21966         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21967         0,
  21968         3,
  21969         soc_VP_RAM_CONTROL_6r_fields,
  21970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21971         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21972         -1,
  21973         -1,
  21974         0,
  21975     },
  21976 #endif /* chips */
  21977 
  21978 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  21979     { /* SOC_REG_INT_VP_RAM_CONTROL_6_PIPE3r */
  21980         soc_block_list[5],
  21981         soc_genreg,
  21982         1,
  21983         0,
  21984         0x370c0000,
  21985         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  21986         0,
  21987         3,
  21988         soc_VP_RAM_CONTROL_6r_fields,
  21989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21990         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21991         -1,
  21992         -1,
  21993         0,
  21994     },
  21995 #endif /* chips */
  21996 
  21997 #if defined(BCM_56970_A0)
  21998     { /* SOC_REG_INT_VP_RAM_CONTROL_6_PIPE0_BCM56970_A0r */
  21999         soc_block_list[5],
  22000         soc_genreg,
  22001         1,
  22002         0,
  22003         0x5b0c0000,
  22004         0,
  22005         0,
  22006         3,
  22007         soc_VP_RAM_CONTROL_6_BCM56970_A0r_fields,
  22008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22009         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22010         -1,
  22011         -1,
  22012         0,
  22013     },
  22014 #endif /* chips */
  22015 
  22016 #if defined(BCM_56970_A0)
  22017     { /* SOC_REG_INT_VP_RAM_CONTROL_6_PIPE1_BCM56970_A0r */
  22018         soc_block_list[5],
  22019         soc_genreg,
  22020         1,
  22021         0,
  22022         0x5b0c0000,
  22023         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22024         0,
  22025         3,
  22026         soc_VP_RAM_CONTROL_6_BCM56970_A0r_fields,
  22027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22028         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22029         -1,
  22030         -1,
  22031         0,
  22032     },
  22033 #endif /* chips */
  22034 
  22035 #if defined(BCM_56970_A0)
  22036     { /* SOC_REG_INT_VP_RAM_CONTROL_6_PIPE2_BCM56970_A0r */
  22037         soc_block_list[5],
  22038         soc_genreg,
  22039         1,
  22040         0,
  22041         0x5b0c0000,
  22042         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22043         0,
  22044         3,
  22045         soc_VP_RAM_CONTROL_6_BCM56970_A0r_fields,
  22046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22048         -1,
  22049         -1,
  22050         0,
  22051     },
  22052 #endif /* chips */
  22053 
  22054 #if defined(BCM_56970_A0)
  22055     { /* SOC_REG_INT_VP_RAM_CONTROL_6_PIPE3_BCM56970_A0r */
  22056         soc_block_list[5],
  22057         soc_genreg,
  22058         1,
  22059         0,
  22060         0x5b0c0000,
  22061         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22062         0,
  22063         3,
  22064         soc_VP_RAM_CONTROL_6_BCM56970_A0r_fields,
  22065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22066         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22067         -1,
  22068         -1,
  22069         0,
  22070     },
  22071 #endif /* chips */
  22072 
  22073 #if defined(BCM_56970_A0)
  22074     { /* SOC_REG_INT_VP_RAM_CONTROL_7_BCM56970_A0r */
  22075         soc_block_list[5],
  22076         soc_genreg,
  22077         1,
  22078         0,
  22079         0x5b0d0000,
  22080         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22081         0,
  22082         2,
  22083         soc_VP_RAM_CONTROL_7_BCM56970_A0r_fields,
  22084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22085         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22086         -1,
  22087         -1,
  22088         0,
  22089     },
  22090 #endif /* chips */
  22091 
  22092 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22093     { /* SOC_REG_INT_VP_RAM_CONTROL_7_PIPE0r */
  22094         soc_block_list[5],
  22095         soc_genreg,
  22096         1,
  22097         0,
  22098         0x370d0000,
  22099         0,
  22100         0,
  22101         2,
  22102         soc_VP_RAM_CONTROL_7r_fields,
  22103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22105         -1,
  22106         -1,
  22107         0,
  22108     },
  22109 #endif /* chips */
  22110 
  22111 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22112     { /* SOC_REG_INT_VP_RAM_CONTROL_7_PIPE1r */
  22113         soc_block_list[5],
  22114         soc_genreg,
  22115         1,
  22116         0,
  22117         0x370d0000,
  22118         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22119         0,
  22120         2,
  22121         soc_VP_RAM_CONTROL_7r_fields,
  22122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22123         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22124         -1,
  22125         -1,
  22126         0,
  22127     },
  22128 #endif /* chips */
  22129 
  22130 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22131     { /* SOC_REG_INT_VP_RAM_CONTROL_7_PIPE2r */
  22132         soc_block_list[5],
  22133         soc_genreg,
  22134         1,
  22135         0,
  22136         0x370d0000,
  22137         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22138         0,
  22139         2,
  22140         soc_VP_RAM_CONTROL_7r_fields,
  22141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22142         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22143         -1,
  22144         -1,
  22145         0,
  22146     },
  22147 #endif /* chips */
  22148 
  22149 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22150     { /* SOC_REG_INT_VP_RAM_CONTROL_7_PIPE3r */
  22151         soc_block_list[5],
  22152         soc_genreg,
  22153         1,
  22154         0,
  22155         0x370d0000,
  22156         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22157         0,
  22158         2,
  22159         soc_VP_RAM_CONTROL_7r_fields,
  22160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22161         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22162         -1,
  22163         -1,
  22164         0,
  22165     },
  22166 #endif /* chips */
  22167 
  22168 #if defined(BCM_56970_A0)
  22169     { /* SOC_REG_INT_VP_RAM_CONTROL_7_PIPE0_BCM56970_A0r */
  22170         soc_block_list[5],
  22171         soc_genreg,
  22172         1,
  22173         0,
  22174         0x5b0d0000,
  22175         0,
  22176         0,
  22177         2,
  22178         soc_VP_RAM_CONTROL_7_BCM56970_A0r_fields,
  22179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22180         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22181         -1,
  22182         -1,
  22183         0,
  22184     },
  22185 #endif /* chips */
  22186 
  22187 #if defined(BCM_56970_A0)
  22188     { /* SOC_REG_INT_VP_RAM_CONTROL_7_PIPE1_BCM56970_A0r */
  22189         soc_block_list[5],
  22190         soc_genreg,
  22191         1,
  22192         0,
  22193         0x5b0d0000,
  22194         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22195         0,
  22196         2,
  22197         soc_VP_RAM_CONTROL_7_BCM56970_A0r_fields,
  22198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22199         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22200         -1,
  22201         -1,
  22202         0,
  22203     },
  22204 #endif /* chips */
  22205 
  22206 #if defined(BCM_56970_A0)
  22207     { /* SOC_REG_INT_VP_RAM_CONTROL_7_PIPE2_BCM56970_A0r */
  22208         soc_block_list[5],
  22209         soc_genreg,
  22210         1,
  22211         0,
  22212         0x5b0d0000,
  22213         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22214         0,
  22215         2,
  22216         soc_VP_RAM_CONTROL_7_BCM56970_A0r_fields,
  22217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22218         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22219         -1,
  22220         -1,
  22221         0,
  22222     },
  22223 #endif /* chips */
  22224 
  22225 #if defined(BCM_56970_A0)
  22226     { /* SOC_REG_INT_VP_RAM_CONTROL_7_PIPE3_BCM56970_A0r */
  22227         soc_block_list[5],
  22228         soc_genreg,
  22229         1,
  22230         0,
  22231         0x5b0d0000,
  22232         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22233         0,
  22234         2,
  22235         soc_VP_RAM_CONTROL_7_BCM56970_A0r_fields,
  22236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22237         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22238         -1,
  22239         -1,
  22240         0,
  22241     },
  22242 #endif /* chips */
  22243 
  22244 #if defined(BCM_56970_A0)
  22245     { /* SOC_REG_INT_VP_RAM_CONTROL_8_BCM56970_A0r */
  22246         soc_block_list[5],
  22247         soc_genreg,
  22248         1,
  22249         0,
  22250         0x5b0e0000,
  22251         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22252         0,
  22253         1,
  22254         soc_VP_RAM_CONTROL_8_BCM56970_A0r_fields,
  22255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22256         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22257         -1,
  22258         -1,
  22259         0,
  22260     },
  22261 #endif /* chips */
  22262 
  22263 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22264     { /* SOC_REG_INT_VP_RAM_CONTROL_8_PIPE0r */
  22265         soc_block_list[5],
  22266         soc_genreg,
  22267         1,
  22268         0,
  22269         0x370e0000,
  22270         0,
  22271         0,
  22272         1,
  22273         soc_VP_RAM_CONTROL_8r_fields,
  22274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22275         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22276         -1,
  22277         -1,
  22278         0,
  22279     },
  22280 #endif /* chips */
  22281 
  22282 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22283     { /* SOC_REG_INT_VP_RAM_CONTROL_8_PIPE1r */
  22284         soc_block_list[5],
  22285         soc_genreg,
  22286         1,
  22287         0,
  22288         0x370e0000,
  22289         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22290         0,
  22291         1,
  22292         soc_VP_RAM_CONTROL_8r_fields,
  22293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22294         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22295         -1,
  22296         -1,
  22297         0,
  22298     },
  22299 #endif /* chips */
  22300 
  22301 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22302     { /* SOC_REG_INT_VP_RAM_CONTROL_8_PIPE2r */
  22303         soc_block_list[5],
  22304         soc_genreg,
  22305         1,
  22306         0,
  22307         0x370e0000,
  22308         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22309         0,
  22310         1,
  22311         soc_VP_RAM_CONTROL_8r_fields,
  22312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22313         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22314         -1,
  22315         -1,
  22316         0,
  22317     },
  22318 #endif /* chips */
  22319 
  22320 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22321     { /* SOC_REG_INT_VP_RAM_CONTROL_8_PIPE3r */
  22322         soc_block_list[5],
  22323         soc_genreg,
  22324         1,
  22325         0,
  22326         0x370e0000,
  22327         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22328         0,
  22329         1,
  22330         soc_VP_RAM_CONTROL_8r_fields,
  22331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22332         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22333         -1,
  22334         -1,
  22335         0,
  22336     },
  22337 #endif /* chips */
  22338 
  22339 #if defined(BCM_56970_A0)
  22340     { /* SOC_REG_INT_VP_RAM_CONTROL_8_PIPE0_BCM56970_A0r */
  22341         soc_block_list[5],
  22342         soc_genreg,
  22343         1,
  22344         0,
  22345         0x5b0e0000,
  22346         0,
  22347         0,
  22348         1,
  22349         soc_VP_RAM_CONTROL_8_BCM56970_A0r_fields,
  22350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22351         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22352         -1,
  22353         -1,
  22354         0,
  22355     },
  22356 #endif /* chips */
  22357 
  22358 #if defined(BCM_56970_A0)
  22359     { /* SOC_REG_INT_VP_RAM_CONTROL_8_PIPE1_BCM56970_A0r */
  22360         soc_block_list[5],
  22361         soc_genreg,
  22362         1,
  22363         0,
  22364         0x5b0e0000,
  22365         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22366         0,
  22367         1,
  22368         soc_VP_RAM_CONTROL_8_BCM56970_A0r_fields,
  22369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22370         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22371         -1,
  22372         -1,
  22373         0,
  22374     },
  22375 #endif /* chips */
  22376 
  22377 #if defined(BCM_56970_A0)
  22378     { /* SOC_REG_INT_VP_RAM_CONTROL_8_PIPE2_BCM56970_A0r */
  22379         soc_block_list[5],
  22380         soc_genreg,
  22381         1,
  22382         0,
  22383         0x5b0e0000,
  22384         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22385         0,
  22386         1,
  22387         soc_VP_RAM_CONTROL_8_BCM56970_A0r_fields,
  22388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22389         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22390         -1,
  22391         -1,
  22392         0,
  22393     },
  22394 #endif /* chips */
  22395 
  22396 #if defined(BCM_56970_A0)
  22397     { /* SOC_REG_INT_VP_RAM_CONTROL_8_PIPE3_BCM56970_A0r */
  22398         soc_block_list[5],
  22399         soc_genreg,
  22400         1,
  22401         0,
  22402         0x5b0e0000,
  22403         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22404         0,
  22405         1,
  22406         soc_VP_RAM_CONTROL_8_BCM56970_A0r_fields,
  22407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22408         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22409         -1,
  22410         -1,
  22411         0,
  22412     },
  22413 #endif /* chips */
  22414 
  22415 #if defined(BCM_56850_A0)
  22416     { /* SOC_REG_INT_VP_SER_CONTROLr */
  22417         soc_block_list[5],
  22418         soc_genreg,
  22419         1,
  22420         0,
  22421         0x53090000,
  22422         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22423         0,
  22424         16,
  22425         soc_VP_SER_CONTROLr_fields,
  22426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22427         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22428         -1,
  22429         -1,
  22430     },
  22431 #endif /* chips */
  22432 
  22433 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
  22434     { /* SOC_REG_INT_VP_SER_CONTROL_BCM56560_A0r */
  22435         soc_block_list[5],
  22436         soc_genreg,
  22437         1,
  22438         0,
  22439         0x63080000,
  22440         0,
  22441         0,
  22442         9,
  22443         soc_VP_SER_CONTROL_BCM56560_A0r_fields,
  22444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22445         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22446         -1,
  22447         -1,
  22448     },
  22449 #endif /* chips */
  22450 
  22451 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  22452     { /* SOC_REG_INT_VP_SER_CONTROL_BCM56670_A0r */
  22453         soc_block_list[5],
  22454         soc_genreg,
  22455         1,
  22456         0,
  22457         0x63080000,
  22458         0,
  22459         0,
  22460         7,
  22461         soc_VP_SER_CONTROL_BCM56670_A0r_fields,
  22462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22463         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22464         -1,
  22465         -1,
  22466     },
  22467 #endif /* chips */
  22468 
  22469 #if defined(BCM_56860_A0)
  22470     { /* SOC_REG_INT_VP_SER_CONTROL_BCM56860_A0r */
  22471         soc_block_list[5],
  22472         soc_genreg,
  22473         1,
  22474         0,
  22475         0x63080000,
  22476         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22477         0,
  22478         9,
  22479         soc_VP_SER_CONTROL_BCM56860_A0r_fields,
  22480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22481         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22482         -1,
  22483         -1,
  22484     },
  22485 #endif /* chips */
  22486 
  22487 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22488     { /* SOC_REG_INT_VP_SER_CONTROL_BCM56960_A0r */
  22489         soc_block_list[5],
  22490         soc_genreg,
  22491         1,
  22492         0,
  22493         0x370f0000,
  22494         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22495         0,
  22496         10,
  22497         soc_VP_SER_CONTROL_BCM56960_A0r_fields,
  22498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22499         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22500         -1,
  22501         -1,
  22502         0,
  22503     },
  22504 #endif /* chips */
  22505 
  22506 #if defined(BCM_56970_A0)
  22507     { /* SOC_REG_INT_VP_SER_CONTROL_BCM56970_A0r */
  22508         soc_block_list[5],
  22509         soc_genreg,
  22510         1,
  22511         0,
  22512         0x5b0f0000,
  22513         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22514         0,
  22515         9,
  22516         soc_VP_SER_CONTROL_BCM56970_A0r_fields,
  22517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22518         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22519         -1,
  22520         -1,
  22521         0,
  22522     },
  22523 #endif /* chips */
  22524 
  22525 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  22526     defined(BCM_56870_A0)
  22527     { /* SOC_REG_INT_VRF_CONTROLr */
  22528         soc_block_list[115],
  22529         soc_genreg,
  22530         1,
  22531         0,
  22532         0x2002700,
  22533         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22534         SOC_REG_FLAG_CCH,
  22535         2,
  22536         soc_VRF_CONTROLr_fields,
  22537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22539         -1,
  22540         -1,
  22541         3,
  22542     },
  22543 #endif /* chips */
  22544 
  22545 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  22546     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  22547     { /* SOC_REG_INT_VRF_MASKr */
  22548         soc_block_list[5],
  22549         soc_genreg,
  22550         1,
  22551         0,
  22552         0x608000b,
  22553         0,
  22554         0,
  22555         1,
  22556         soc_VRF_MASKr_fields,
  22557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22558         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22559         -1,
  22560         -1,
  22561     },
  22562 #endif /* chips */
  22563 
  22564 #if defined(BCM_53570_A0)
  22565     { /* SOC_REG_INT_VRF_MASK_BCM53570_A0r */
  22566         soc_block_list[5],
  22567         soc_genreg,
  22568         1,
  22569         0,
  22570         0x12000200,
  22571         0,
  22572         0,
  22573         1,
  22574         soc_CFAP_ARBITER_MASK_BCM56960_A0r_fields,
  22575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22576         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  22577         -1,
  22578         -1,
  22579     },
  22580 #endif /* chips */
  22581 
  22582 #if defined(BCM_53570_B0)
  22583     { /* SOC_REG_INT_VRF_MASK_BCM53570_B0r */
  22584         soc_block_list[5],
  22585         soc_genreg,
  22586         1,
  22587         0,
  22588         0x12000200,
  22589         0,
  22590         0,
  22591         1,
  22592         soc_VRF_MASK_BCM56560_A0r_fields,
  22593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22594         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  22595         -1,
  22596         -1,
  22597     },
  22598 #endif /* chips */
  22599 
  22600 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  22601     defined(BCM_56270_A0)
  22602     { /* SOC_REG_INT_VRF_MASK_BCM56260_A0r */
  22603         soc_block_list[5],
  22604         soc_genreg,
  22605         1,
  22606         0,
  22607         0x16000a00,
  22608         0,
  22609         0,
  22610         1,
  22611         soc_VRF_MASK_BCM56260_A0r_fields,
  22612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22613         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  22614         -1,
  22615         -1,
  22616     },
  22617 #endif /* chips */
  22618 
  22619 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  22620     { /* SOC_REG_INT_VRF_MASK_BCM56334_A0r */
  22621         soc_block_list[5],
  22622         soc_genreg,
  22623         1,
  22624         0,
  22625         0x608000b,
  22626         0,
  22627         0,
  22628         1,
  22629         soc_VRF_MASK_BCM56334_A0r_fields,
  22630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22631         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  22632         -1,
  22633         -1,
  22634     },
  22635 #endif /* chips */
  22636 
  22637 #if defined(BCM_56340_A0)
  22638     { /* SOC_REG_INT_VRF_MASK_BCM56340_A0r */
  22639         soc_block_list[5],
  22640         soc_genreg,
  22641         1,
  22642         0,
  22643         0x16000900,
  22644         0,
  22645         0,
  22646         1,
  22647         soc_VRF_MASK_BCM56340_A0r_fields,
  22648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22649         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22650         -1,
  22651         -1,
  22652     },
  22653 #endif /* chips */
  22654 
  22655 #if defined(BCM_56370_A0)
  22656     { /* SOC_REG_INT_VRF_MASK_BCM56370_A0r */
  22657         soc_block_list[5],
  22658         soc_genreg,
  22659         1,
  22660         0,
  22661         0x66000300,
  22662         0,
  22663         0,
  22664         1,
  22665         soc_VRF_MASK_BCM56560_A0r_fields,
  22666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22667         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  22668         -1,
  22669         -1,
  22670         0,
  22671     },
  22672 #endif /* chips */
  22673 
  22674 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  22675     { /* SOC_REG_INT_VRF_MASK_BCM56440_A0r */
  22676         soc_block_list[5],
  22677         soc_genreg,
  22678         1,
  22679         0,
  22680         0x508060b,
  22681         0,
  22682         0,
  22683         1,
  22684         soc_VRF_MASK_BCM56334_A0r_fields,
  22685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22686         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  22687         -1,
  22688         -1,
  22689     },
  22690 #endif /* chips */
  22691 
  22692 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  22693     defined(BCM_56450_B1)
  22694     { /* SOC_REG_INT_VRF_MASK_BCM56450_A0r */
  22695         soc_block_list[5],
  22696         soc_genreg,
  22697         1,
  22698         0,
  22699         0x16000a00,
  22700         0,
  22701         0,
  22702         1,
  22703         soc_VRF_MASK_BCM56450_A0r_fields,
  22704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22705         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  22706         -1,
  22707         -1,
  22708     },
  22709 #endif /* chips */
  22710 
  22711 #if defined(BCM_56560_A0) || defined(BCM_56670_A0) || \
  22712     defined(BCM_56670_B0)
  22713     { /* SOC_REG_INT_VRF_MASK_BCM56560_A0r */
  22714         soc_block_list[5],
  22715         soc_genreg,
  22716         1,
  22717         0,
  22718         0x16000b00,
  22719         0,
  22720         0,
  22721         1,
  22722         soc_VRF_MASK_BCM56560_A0r_fields,
  22723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22724         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  22725         -1,
  22726         -1,
  22727     },
  22728 #endif /* chips */
  22729 
  22730 #if defined(BCM_56560_B0)
  22731     { /* SOC_REG_INT_VRF_MASK_BCM56560_B0r */
  22732         soc_block_list[5],
  22733         soc_genreg,
  22734         1,
  22735         0,
  22736         0x16000b00,
  22737         0,
  22738         0,
  22739         2,
  22740         soc_VRF_MASK_BCM56560_B0r_fields,
  22741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22742         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  22743         -1,
  22744         -1,
  22745     },
  22746 #endif /* chips */
  22747 
  22748 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  22749     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  22750     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  22751     { /* SOC_REG_INT_VRF_MASK_BCM56634_A0r */
  22752         soc_block_list[5],
  22753         soc_genreg,
  22754         1,
  22755         0,
  22756         0x508000b,
  22757         0,
  22758         0,
  22759         1,
  22760         soc_VRF_MASKr_fields,
  22761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22762         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22763         -1,
  22764         -1,
  22765     },
  22766 #endif /* chips */
  22767 
  22768 #if defined(BCM_56640_A0)
  22769     { /* SOC_REG_INT_VRF_MASK_BCM56640_A0r */
  22770         soc_block_list[5],
  22771         soc_genreg,
  22772         1,
  22773         0,
  22774         0x16000900,
  22775         0,
  22776         0,
  22777         1,
  22778         soc_VRF_MASK_BCM56640_A0r_fields,
  22779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22780         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  22781         -1,
  22782         -1,
  22783     },
  22784 #endif /* chips */
  22785 
  22786 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  22787     { /* SOC_REG_INT_VRF_MASK_BCM56820_A0r */
  22788         soc_block_list[5],
  22789         soc_genreg,
  22790         1,
  22791         0,
  22792         0x5080604,
  22793         0,
  22794         0,
  22795         1,
  22796         soc_L2_ENTRY_ADDR_MASK_BCM56224_A0r_fields,
  22797         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  22798         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22799         -1,
  22800         -1,
  22801     },
  22802 #endif /* chips */
  22803 
  22804 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  22805     { /* SOC_REG_INT_VRF_MASK_BCM56840_A0r */
  22806         soc_block_list[5],
  22807         soc_genreg,
  22808         1,
  22809         0,
  22810         0x508060b,
  22811         0,
  22812         0,
  22813         1,
  22814         soc_VRF_MASK_BCM56840_A0r_fields,
  22815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22816         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  22817         -1,
  22818         -1,
  22819     },
  22820 #endif /* chips */
  22821 
  22822 #if defined(BCM_56850_A0)
  22823     { /* SOC_REG_INT_VRF_MASK_BCM56850_A0r */
  22824         soc_block_list[5],
  22825         soc_genreg,
  22826         1,
  22827         0,
  22828         0x16000b00,
  22829         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22830         0,
  22831         1,
  22832         soc_VRF_MASK_BCM56850_A0r_fields,
  22833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22834         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  22835         -1,
  22836         -1,
  22837     },
  22838 #endif /* chips */
  22839 
  22840 #if defined(BCM_56860_A0)
  22841     { /* SOC_REG_INT_VRF_MASK_BCM56860_A0r */
  22842         soc_block_list[5],
  22843         soc_genreg,
  22844         1,
  22845         0,
  22846         0x16000b00,
  22847         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22848         0,
  22849         1,
  22850         soc_VRF_MASK_BCM56860_A0r_fields,
  22851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22852         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  22853         -1,
  22854         -1,
  22855     },
  22856 #endif /* chips */
  22857 
  22858 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  22859     { /* SOC_REG_INT_VRF_MASK_BCM56870_A0r */
  22860         soc_block_list[5],
  22861         soc_genreg,
  22862         1,
  22863         0,
  22864         0x66000200,
  22865         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22866         0,
  22867         1,
  22868         soc_VRF_MASK_BCM56560_A0r_fields,
  22869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22870         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  22871         -1,
  22872         -1,
  22873         0,
  22874     },
  22875 #endif /* chips */
  22876 
  22877 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  22878     { /* SOC_REG_INT_VRF_MASK_BCM56960_A0r */
  22879         soc_block_list[5],
  22880         soc_genreg,
  22881         1,
  22882         0,
  22883         0x36000900,
  22884         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22885         0,
  22886         1,
  22887         soc_VRF_MASK_BCM56960_A0r_fields,
  22888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22889         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22890         -1,
  22891         -1,
  22892         0,
  22893     },
  22894 #endif /* chips */
  22895 
  22896 #if defined(BCM_56970_A0)
  22897     { /* SOC_REG_INT_VRF_MASK_BCM56970_A0r */
  22898         soc_block_list[5],
  22899         soc_genreg,
  22900         1,
  22901         0,
  22902         0x5a000800,
  22903         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22904         0,
  22905         1,
  22906         soc_VRF_MASK_BCM56960_A0r_fields,
  22907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22908         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22909         -1,
  22910         -1,
  22911         0,
  22912     },
  22913 #endif /* chips */
  22914 
  22915 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  22916     { /* SOC_REG_INT_VRF_MASK_BCM56980_A0r */
  22917         soc_block_list[5],
  22918         soc_genreg,
  22919         1,
  22920         0,
  22921         0xa000600,
  22922         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  22923         0,
  22924         1,
  22925         soc_VRF_MASK_BCM56960_A0r_fields,
  22926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22927         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22928         -1,
  22929         -1,
  22930         3,
  22931     },
  22932 #endif /* chips */
  22933 
  22934 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  22935     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  22936     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  22937     { /* SOC_REG_INT_VRF_PARITY_CONTROLr */
  22938         soc_block_list[5],
  22939         soc_genreg,
  22940         1,
  22941         0,
  22942         0x5080175,
  22943         0,
  22944         0,
  22945         1,
  22946         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  22947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22948         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22949         -1,
  22950         -1,
  22951     },
  22952 #endif /* chips */
  22953 
  22954 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  22955     defined(BCM_56270_A0)
  22956     { /* SOC_REG_INT_VRF_PARITY_CONTROL_BCM56260_A0r */
  22957         soc_block_list[5],
  22958         soc_genreg,
  22959         1,
  22960         0,
  22961         0x16011c00,
  22962         0,
  22963         0,
  22964         1,
  22965         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  22966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22967         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22968         -1,
  22969         -1,
  22970     },
  22971 #endif /* chips */
  22972 
  22973 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  22974     defined(BCM_56450_B1)
  22975     { /* SOC_REG_INT_VRF_PARITY_CONTROL_BCM56450_A0r */
  22976         soc_block_list[5],
  22977         soc_genreg,
  22978         1,
  22979         0,
  22980         0x16011b00,
  22981         0,
  22982         0,
  22983         1,
  22984         soc_FT_CNTR_SER_CONTROLr_fields,
  22985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22986         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22987         -1,
  22988         -1,
  22989     },
  22990 #endif /* chips */
  22991 
  22992 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  22993     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  22994     { /* SOC_REG_INT_VRF_PARITY_CONTROL_BCM56560_A0r */
  22995         soc_block_list[5],
  22996         soc_genreg,
  22997         1,
  22998         0,
  22999         0x170a0000,
  23000         0,
  23001         0,
  23002         1,
  23003         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  23004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23005         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23006         -1,
  23007         -1,
  23008     },
  23009 #endif /* chips */
  23010 
  23011 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  23012     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  23013     { /* SOC_REG_INT_VRF_PARITY_CONTROL_BCM56840_A0r */
  23014         soc_block_list[5],
  23015         soc_genreg,
  23016         1,
  23017         0,
  23018         0x5080d1b,
  23019         0,
  23020         0,
  23021         1,
  23022         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  23023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23024         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23025         -1,
  23026         -1,
  23027     },
  23028 #endif /* chips */
  23029 
  23030 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  23031     { /* SOC_REG_INT_VRF_PARITY_CONTROL_BCM56850_A0r */
  23032         soc_block_list[5],
  23033         soc_genreg,
  23034         1,
  23035         0,
  23036         0x17070000,
  23037         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23038         0,
  23039         1,
  23040         soc_FT_CNTR_SER_CONTROLr_fields,
  23041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23042         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23043         -1,
  23044         -1,
  23045     },
  23046 #endif /* chips */
  23047 
  23048 #if defined(BCM_56860_A0)
  23049     { /* SOC_REG_INT_VRF_PARITY_CONTROL_BCM56860_A0r */
  23050         soc_block_list[5],
  23051         soc_genreg,
  23052         1,
  23053         0,
  23054         0x170a0000,
  23055         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23056         0,
  23057         1,
  23058         soc_FT_CNTR_SER_CONTROLr_fields,
  23059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23060         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23061         -1,
  23062         -1,
  23063     },
  23064 #endif /* chips */
  23065 
  23066 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  23067     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  23068     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  23069     { /* SOC_REG_INT_VRF_PARITY_STATUS_INTRr */
  23070         soc_block_list[5],
  23071         soc_genreg,
  23072         1,
  23073         0,
  23074         0x5080176,
  23075         0,
  23076         0,
  23077         3,
  23078         soc_EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr_fields,
  23079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23080         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  23081         -1,
  23082         -1,
  23083     },
  23084 #endif /* chips */
  23085 
  23086 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  23087     { /* SOC_REG_INT_VRF_PARITY_STATUS_INTR_BCM56440_A0r */
  23088         soc_block_list[5],
  23089         soc_genreg,
  23090         1,
  23091         0,
  23092         0x5080d1c,
  23093         0,
  23094         0,
  23095         3,
  23096         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  23097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23098         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23099         -1,
  23100         -1,
  23101     },
  23102 #endif /* chips */
  23103 
  23104 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23105     defined(BCM_56450_B1)
  23106     { /* SOC_REG_INT_VRF_PARITY_STATUS_INTR_BCM56450_A0r */
  23107         soc_block_list[5],
  23108         soc_genreg,
  23109         1,
  23110         0,
  23111         0x16011c00,
  23112         0,
  23113         0,
  23114         3,
  23115         soc_EFP_METER_PARITY_STATUS_INTRr_fields,
  23116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23117         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23118         -1,
  23119         -1,
  23120     },
  23121 #endif /* chips */
  23122 
  23123 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  23124     { /* SOC_REG_INT_VRF_PARITY_STATUS_INTR_BCM56840_A0r */
  23125         soc_block_list[5],
  23126         soc_genreg,
  23127         1,
  23128         0,
  23129         0x5080d1c,
  23130         0,
  23131         0,
  23132         3,
  23133         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
  23134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23135         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23136         -1,
  23137         -1,
  23138     },
  23139 #endif /* chips */
  23140 
  23141 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  23142     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  23143     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  23144     { /* SOC_REG_INT_VRF_PARITY_STATUS_NACKr */
  23145         soc_block_list[5],
  23146         soc_genreg,
  23147         1,
  23148         0,
  23149         0x5080177,
  23150         0,
  23151         0,
  23152         3,
  23153         soc_EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr_fields,
  23154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23155         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  23156         -1,
  23157         -1,
  23158     },
  23159 #endif /* chips */
  23160 
  23161 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  23162     { /* SOC_REG_INT_VRF_PARITY_STATUS_NACK_BCM56440_A0r */
  23163         soc_block_list[5],
  23164         soc_genreg,
  23165         1,
  23166         0,
  23167         0x5080d1d,
  23168         0,
  23169         0,
  23170         3,
  23171         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  23172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23174         -1,
  23175         -1,
  23176     },
  23177 #endif /* chips */
  23178 
  23179 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23180     defined(BCM_56450_B1)
  23181     { /* SOC_REG_INT_VRF_PARITY_STATUS_NACK_BCM56450_A0r */
  23182         soc_block_list[5],
  23183         soc_genreg,
  23184         1,
  23185         0,
  23186         0x16011d00,
  23187         0,
  23188         0,
  23189         3,
  23190         soc_EFP_METER_PARITY_STATUS_INTRr_fields,
  23191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23192         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23193         -1,
  23194         -1,
  23195     },
  23196 #endif /* chips */
  23197 
  23198 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  23199     { /* SOC_REG_INT_VRF_PARITY_STATUS_NACK_BCM56840_A0r */
  23200         soc_block_list[5],
  23201         soc_genreg,
  23202         1,
  23203         0,
  23204         0x5080d1d,
  23205         0,
  23206         0,
  23207         3,
  23208         soc_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr_fields,
  23209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23210         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23211         -1,
  23212         -1,
  23213     },
  23214 #endif /* chips */
  23215 
  23216 #if defined(BCM_56640_A0)
  23217     { /* SOC_REG_INT_VRF_PDA_CONTROLr */
  23218         soc_block_list[5],
  23219         soc_genreg,
  23220         1,
  23221         0,
  23222         0x16010e00,
  23223         0,
  23224         0,
  23225         1,
  23226         soc_VRF_PDA_CONTROLr_fields,
  23227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23228         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23229         -1,
  23230         -1,
  23231     },
  23232 #endif /* chips */
  23233 
  23234 #if defined(BCM_56340_A0)
  23235     { /* SOC_REG_INT_VRF_PDA_CONTROL_BCM56340_A0r */
  23236         soc_block_list[5],
  23237         soc_genreg,
  23238         1,
  23239         0,
  23240         0x16010e00,
  23241         0,
  23242         0,
  23243         1,
  23244         soc_VRF_PDA_CONTROL_BCM56340_A0r_fields,
  23245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23246         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23247         -1,
  23248         -1,
  23249     },
  23250 #endif /* chips */
  23251 
  23252 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  23253     { /* SOC_REG_INT_VXLAN_CONTROLr */
  23254         soc_block_list[5],
  23255         soc_genreg,
  23256         1,
  23257         0,
  23258         0xa00a100,
  23259         SOC_REG_FLAG_64_BITS |
  23260                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23261         0,
  23262         4,
  23263         soc_VXLAN_CONTROLr_fields,
  23264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23265         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  23266         -1,
  23267         -1,
  23268     },
  23269 #endif /* chips */
  23270 
  23271 #if defined(BCM_56370_A0)
  23272     { /* SOC_REG_INT_VXLAN_CONTROL_BCM56370_A0r */
  23273         soc_block_list[5],
  23274         soc_genreg,
  23275         1,
  23276         0,
  23277         0x52000200,
  23278         SOC_REG_FLAG_64_BITS,
  23279         SOC_REG_FLAG_CCH,
  23280         5,
  23281         soc_VXLAN_CONTROL_BCM56870_A0r_fields,
  23282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23283         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  23284         -1,
  23285         -1,
  23286         0,
  23287     },
  23288 #endif /* chips */
  23289 
  23290 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  23291     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  23292     { /* SOC_REG_INT_VXLAN_CONTROL_BCM56560_A0r */
  23293         soc_block_list[5],
  23294         soc_genreg,
  23295         1,
  23296         0,
  23297         0xa00a100,
  23298         SOC_REG_FLAG_64_BITS,
  23299         0,
  23300         4,
  23301         soc_VXLAN_CONTROL_BCM56960_A0r_fields,
  23302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23303         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  23304         -1,
  23305         -1,
  23306     },
  23307 #endif /* chips */
  23308 
  23309 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  23310     { /* SOC_REG_INT_VXLAN_CONTROL_BCM56870_A0r */
  23311         soc_block_list[5],
  23312         soc_genreg,
  23313         1,
  23314         0,
  23315         0x52000200,
  23316         SOC_REG_FLAG_64_BITS |
  23317                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23318         SOC_REG_FLAG_CCH,
  23319         5,
  23320         soc_VXLAN_CONTROL_BCM56870_A0r_fields,
  23321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23322         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  23323         -1,
  23324         -1,
  23325         0,
  23326     },
  23327 #endif /* chips */
  23328 
  23329 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  23330     { /* SOC_REG_INT_VXLAN_CONTROL_BCM56960_A0r */
  23331         soc_block_list[5],
  23332         soc_genreg,
  23333         1,
  23334         0,
  23335         0x2e002000,
  23336         SOC_REG_FLAG_64_BITS |
  23337                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23338         0,
  23339         4,
  23340         soc_VXLAN_CONTROL_BCM56960_A0r_fields,
  23341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23342         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  23343         -1,
  23344         -1,
  23345         0,
  23346     },
  23347 #endif /* chips */
  23348 
  23349 #if defined(BCM_56970_A0)
  23350     { /* SOC_REG_INT_VXLAN_CONTROL_BCM56970_A0r */
  23351         soc_block_list[5],
  23352         soc_genreg,
  23353         1,
  23354         0,
  23355         0x52002000,
  23356         SOC_REG_FLAG_64_BITS |
  23357                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23358         0,
  23359         4,
  23360         soc_VXLAN_CONTROL_BCM56960_A0r_fields,
  23361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23362         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  23363         -1,
  23364         -1,
  23365         0,
  23366     },
  23367 #endif /* chips */
  23368 
  23369 #if defined(BCM_56850_A0)
  23370     { /* SOC_REG_INT_VXLAN_DEFAULT_NETWORK_SVPr */
  23371         soc_block_list[5],
  23372         soc_genreg,
  23373         1,
  23374         0,
  23375         0x52000300,
  23376         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23377         0,
  23378         1,
  23379         soc_MIM_DEFAULT_NETWORK_SVP_BCM56640_A0r_fields,
  23380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23381         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23382         -1,
  23383         -1,
  23384     },
  23385 #endif /* chips */
  23386 
  23387 #if defined(BCM_56370_A0)
  23388     { /* SOC_REG_INT_VXLAN_DEFAULT_NETWORK_SVP_BCM56370_A0r */
  23389         soc_block_list[115],
  23390         soc_genreg,
  23391         1,
  23392         0,
  23393         0x2003700,
  23394         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23395         SOC_REG_FLAG_CCH,
  23396         1,
  23397         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
  23398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23399         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23400         -1,
  23401         -1,
  23402         3,
  23403     },
  23404 #endif /* chips */
  23405 
  23406 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  23407     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  23408     { /* SOC_REG_INT_VXLAN_DEFAULT_NETWORK_SVP_BCM56560_A0r */
  23409         soc_block_list[5],
  23410         soc_genreg,
  23411         1,
  23412         0,
  23413         0x62000300,
  23414         0,
  23415         0,
  23416         1,
  23417         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
  23418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23419         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23420         -1,
  23421         -1,
  23422     },
  23423 #endif /* chips */
  23424 
  23425 #if defined(BCM_56860_A0)
  23426     { /* SOC_REG_INT_VXLAN_DEFAULT_NETWORK_SVP_BCM56860_A0r */
  23427         soc_block_list[5],
  23428         soc_genreg,
  23429         1,
  23430         0,
  23431         0x62000300,
  23432         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23433         0,
  23434         1,
  23435         soc_MIM_DEFAULT_NETWORK_SVP_BCM56640_A0r_fields,
  23436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23437         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23438         -1,
  23439         -1,
  23440     },
  23441 #endif /* chips */
  23442 
  23443 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  23444     { /* SOC_REG_INT_VXLAN_DEFAULT_NETWORK_SVP_BCM56870_A0r */
  23445         soc_block_list[115],
  23446         soc_genreg,
  23447         1,
  23448         0,
  23449         0x2003a00,
  23450         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23451         SOC_REG_FLAG_CCH,
  23452         1,
  23453         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
  23454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23455         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23456         -1,
  23457         -1,
  23458         3,
  23459     },
  23460 #endif /* chips */
  23461 
  23462 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  23463     { /* SOC_REG_INT_VXLAN_DEFAULT_NETWORK_SVP_BCM56960_A0r */
  23464         soc_block_list[5],
  23465         soc_genreg,
  23466         1,
  23467         0,
  23468         0x36000300,
  23469         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23470         0,
  23471         1,
  23472         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
  23473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23474         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23475         -1,
  23476         -1,
  23477         0,
  23478     },
  23479 #endif /* chips */
  23480 
  23481 #if defined(BCM_56970_A0)
  23482     { /* SOC_REG_INT_VXLAN_DEFAULT_NETWORK_SVP_BCM56970_A0r */
  23483         soc_block_list[5],
  23484         soc_genreg,
  23485         1,
  23486         0,
  23487         0x5a000200,
  23488         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23489         0,
  23490         1,
  23491         soc_L2GRE_DEFAULT_NETWORK_SVPr_fields,
  23492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23493         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23494         -1,
  23495         -1,
  23496         0,
  23497     },
  23498 #endif /* chips */
  23499 
  23500 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  23501     defined(BCM_56870_A0)
  23502     { /* SOC_REG_INT_VXLAN_EVPN_CONTROLr */
  23503         soc_block_list[115],
  23504         soc_genreg,
  23505         1,
  23506         0,
  23507         0x2002c00,
  23508         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23509         SOC_REG_FLAG_CCH,
  23510         3,
  23511         soc_VXLAN_EVPN_CONTROLr_fields,
  23512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23513         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  23514         -1,
  23515         -1,
  23516         3,
  23517     },
  23518 #endif /* chips */
  23519 
  23520 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  23521     defined(BCM_56870_A0)
  23522     { /* SOC_REG_INT_VXLAN_IPV6_CONTROLr */
  23523         soc_block_list[115],
  23524         soc_genreg,
  23525         1,
  23526         0,
  23527         0x2002100,
  23528         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23529         SOC_REG_FLAG_CCH,
  23530         1,
  23531         soc_GPE_GENEVE_IPV6_CONTROLr_fields,
  23532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23533         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  23534         -1,
  23535         -1,
  23536         3,
  23537     },
  23538 #endif /* chips */
  23539 
  23540 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  23541     defined(BCM_56870_A0)
  23542     { /* SOC_REG_INT_VXLT1_MISS_TOCPU_DROPr */
  23543         soc_block_list[115],
  23544         soc_genreg,
  23545         1,
  23546         0,
  23547         0x2002800,
  23548         SOC_REG_FLAG_64_BITS |
  23549                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23550         SOC_REG_FLAG_CCH,
  23551         19,
  23552         soc_VXLT1_MISS_TOCPU_DROPr_fields,
  23553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23554         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23555         -1,
  23556         -1,
  23557         3,
  23558     },
  23559 #endif /* chips */
  23560 
  23561 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  23562     defined(BCM_56870_A0)
  23563     { /* SOC_REG_INT_VXLT2_MISS_TOCPU_DROPr */
  23564         soc_block_list[115],
  23565         soc_genreg,
  23566         1,
  23567         0,
  23568         0x2002900,
  23569         SOC_REG_FLAG_64_BITS |
  23570                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  23571         SOC_REG_FLAG_CCH,
  23572         19,
  23573         soc_VXLT1_MISS_TOCPU_DROPr_fields,
  23574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23575         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23576         -1,
  23577         -1,
  23578         3,
  23579     },
  23580 #endif /* chips */
  23581 
  23582 #if defined(BCM_88732_A0)
  23583     { /* SOC_REG_INT_VXLT_DEBUG_CONTROL_0r */
  23584         soc_block_list[5],
  23585         soc_genreg,
  23586         1,
  23587         0,
  23588         0x408015f,
  23589         SOC_REG_FLAG_64_BITS,
  23590         0,
  23591         12,
  23592         soc_VXLT_DEBUG_CONTROL_0r_fields,
  23593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23594         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23595         -1,
  23596         -1,
  23597     },
  23598 #endif /* chips */
  23599 
  23600 #if defined(BCM_88732_A0)
  23601     { /* SOC_REG_INT_VXLT_DEBUG_CONTROL_1r */
  23602         soc_block_list[5],
  23603         soc_genreg,
  23604         1,
  23605         0,
  23606         0x4080160,
  23607         0,
  23608         0,
  23609         18,
  23610         soc_VXLT_DEBUG_CONTROL_1r_fields,
  23611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23613         -1,
  23614         -1,
  23615     },
  23616 #endif /* chips */
  23617 
  23618 #if defined(BCM_88732_A0)
  23619     { /* SOC_REG_INT_VXLT_DEBUG_EVENTr */
  23620         soc_block_list[5],
  23621         soc_genreg,
  23622         1,
  23623         0,
  23624         0x4080161,
  23625         SOC_REG_FLAG_64_BITS,
  23626         0,
  23627         42,
  23628         soc_VXLT_DEBUG_EVENTr_fields,
  23629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23630         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23631         -1,
  23632         -1,
  23633     },
  23634 #endif /* chips */
  23635 
  23636 #if defined(BCM_88732_A0)
  23637     { /* SOC_REG_INT_VXLT_DEBUG_EVENT_MASKr */
  23638         soc_block_list[5],
  23639         soc_genreg,
  23640         1,
  23641         0,
  23642         0x4080162,
  23643         SOC_REG_FLAG_64_BITS,
  23644         0,
  23645         42,
  23646         soc_VXLT_DEBUG_EVENT_MASKr_fields,
  23647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23649         -1,
  23650         -1,
  23651     },
  23652 #endif /* chips */
  23653 
  23654 #if defined(BCM_88732_A0)
  23655     { /* SOC_REG_INT_VXLT_DEBUG_STATUSr */
  23656         soc_block_list[5],
  23657         soc_genreg,
  23658         1,
  23659         0,
  23660         0x4080163,
  23661         0,
  23662         0,
  23663         3,
  23664         soc_VXLT_DEBUG_STATUSr_fields,
  23665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23666         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23667         -1,
  23668         -1,
  23669     },
  23670 #endif /* chips */
  23671 
  23672 #if defined(BCM_88732_A0)
  23673     { /* SOC_REG_INT_VXLT_DEBUG_STATUS_XLATE_0_Ar */
  23674         soc_block_list[5],
  23675         soc_genreg,
  23676         1,
  23677         0,
  23678         0x4080164,
  23679         SOC_REG_FLAG_64_BITS,
  23680         0,
  23681         7,
  23682         soc_VXLT_DEBUG_STATUS_XLATE_0_Ar_fields,
  23683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23684         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23685         -1,
  23686         -1,
  23687     },
  23688 #endif /* chips */
  23689 
  23690 #if defined(BCM_88732_A0)
  23691     { /* SOC_REG_INT_VXLT_DEBUG_STATUS_XLATE_0_Br */
  23692         soc_block_list[5],
  23693         soc_genreg,
  23694         1,
  23695         0,
  23696         0x4080166,
  23697         SOC_REG_FLAG_64_BITS,
  23698         0,
  23699         7,
  23700         soc_VXLT_DEBUG_STATUS_XLATE_0_Ar_fields,
  23701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23702         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23703         -1,
  23704         -1,
  23705     },
  23706 #endif /* chips */
  23707 
  23708 #if defined(BCM_88732_A0)
  23709     { /* SOC_REG_INT_VXLT_DEBUG_STATUS_XLATE_1_Ar */
  23710         soc_block_list[5],
  23711         soc_genreg,
  23712         1,
  23713         0,
  23714         0x4080165,
  23715         0,
  23716         0,
  23717         1,
  23718         soc_VXLT_DEBUG_STATUS_XLATE_1_Ar_fields,
  23719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23720         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23721         -1,
  23722         -1,
  23723     },
  23724 #endif /* chips */
  23725 
  23726 #if defined(BCM_88732_A0)
  23727     { /* SOC_REG_INT_VXLT_DEBUG_STATUS_XLATE_1_Br */
  23728         soc_block_list[5],
  23729         soc_genreg,
  23730         1,
  23731         0,
  23732         0x4080167,
  23733         0,
  23734         0,
  23735         1,
  23736         soc_VXLT_DEBUG_STATUS_XLATE_1_Ar_fields,
  23737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23738         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23739         -1,
  23740         -1,
  23741     },
  23742 #endif /* chips */
  23743 
  23744 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  23745     { /* SOC_REG_INT_VXLT_FLEX_COUNTER_STRENGTHr */
  23746         soc_block_list[5],
  23747         soc_genreg,
  23748         1,
  23749         0,
  23750         0x12004500,
  23751         0,
  23752         0,
  23753         1,
  23754         soc_L2_ENTRY_FLEX_COUNTER_STRENGTHr_fields,
  23755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23756         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23757         -1,
  23758         -1,
  23759     },
  23760 #endif /* chips */
  23761 
  23762 #if defined(BCM_88732_A0)
  23763     { /* SOC_REG_INT_VXLT_PROTOCOL_INIT_DATA_DBGCTRLr */
  23764         soc_block_list[5],
  23765         soc_genreg,
  23766         1,
  23767         0,
  23768         0x408016f,
  23769         SOC_REG_FLAG_64_BITS,
  23770         0,
  23771         1,
  23772         soc_VXLT_PROTOCOL_INIT_DATA_DBGCTRLr_fields,
  23773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23774         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23775         -1,
  23776         -1,
  23777     },
  23778 #endif /* chips */
  23779 
  23780 #if defined(BCM_88732_A0)
  23781     { /* SOC_REG_INT_VXLT_RAM_CONTROL_DBGCTRLr */
  23782         soc_block_list[5],
  23783         soc_genreg,
  23784         1,
  23785         0,
  23786         0x408016a,
  23787         SOC_REG_FLAG_64_BITS,
  23788         0,
  23789         7,
  23790         soc_VXLT_RAM_CONTROL_DBGCTRLr_fields,
  23791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23792         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23793         -1,
  23794         -1,
  23795     },
  23796 #endif /* chips */
  23797 
  23798 #if defined(BCM_88732_A0)
  23799     { /* SOC_REG_INT_VXLT_SUBNET_DATA_RAM_DBGCTRLr */
  23800         soc_block_list[5],
  23801         soc_genreg,
  23802         1,
  23803         0,
  23804         0x408016c,
  23805         SOC_REG_FLAG_64_BITS,
  23806         0,
  23807         1,
  23808         soc_VXLT_PROTOCOL_INIT_DATA_DBGCTRLr_fields,
  23809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23810         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23811         -1,
  23812         -1,
  23813     },
  23814 #endif /* chips */
  23815 
  23816 #if defined(BCM_88732_A0)
  23817     { /* SOC_REG_INT_VXLT_SUBNET_ECC_RAM_DBGCTRLr */
  23818         soc_block_list[5],
  23819         soc_genreg,
  23820         1,
  23821         0,
  23822         0x408016b,
  23823         0,
  23824         0,
  23825         1,
  23826         soc_VXLT_SUBNET_ECC_RAM_DBGCTRLr_fields,
  23827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23828         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23829         -1,
  23830         -1,
  23831     },
  23832 #endif /* chips */
  23833 
  23834 #if defined(BCM_88732_A0)
  23835     { /* SOC_REG_INT_VXLT_XLATE_INIT_DATA_0_DBGCTRLr */
  23836         soc_block_list[5],
  23837         soc_genreg,
  23838         1,
  23839         0,
  23840         0x408016d,
  23841         SOC_REG_FLAG_64_BITS,
  23842         0,
  23843         1,
  23844         soc_VXLT_XLATE_INIT_DATA_0_DBGCTRLr_fields,
  23845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23846         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23847         -1,
  23848         -1,
  23849     },
  23850 #endif /* chips */
  23851 
  23852 #if defined(BCM_88732_A0)
  23853     { /* SOC_REG_INT_VXLT_XLATE_INIT_DATA_1_DBGCTRLr */
  23854         soc_block_list[5],
  23855         soc_genreg,
  23856         1,
  23857         0,
  23858         0x408016e,
  23859         0,
  23860         0,
  23861         1,
  23862         soc_VXLT_XLATE_INIT_DATA_1_DBGCTRLr_fields,
  23863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23864         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23865         -1,
  23866         -1,
  23867     },
  23868 #endif /* chips */
  23869
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