openbcm

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allregs_u.i (982998B)

      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_u.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_88790_A0)
     16     { /* SOC_REG_INT_U0_LED_ACCU_CTRLr */
     17         soc_block_list[61],
     18         soc_iprocreg,
     19         1,
     20         0,
     21         0x130b00c,
     22         0,
     23         0,
     24         4,
     25         soc_U0_LED_ACCU_CTRLr_fields,
     26         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
     27         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
     28         -1,
     29         -1,
     30     },
     31 #endif /* chips */
     32 
     33 #if defined(BCM_56370_A0)
     34     { /* SOC_REG_INT_U0_LED_ACCU_CTRL_BCM56370_A0r */
     35         soc_block_list[61],
     36         soc_iprocreg,
     37         1,
     38         0,
     39         0x1000b00c,
     40         0,
     41         0,
     42         4,
     43         soc_U0_LED_ACCU_CTRL_BCM56870_A0r_fields,
     44         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
     45         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
     46         -1,
     47         -1,
     48         3,
     49     },
     50 #endif /* chips */
     51 
     52 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
     53     defined(BCM_56980_A0) || defined(BCM_56980_B0)
     54     { /* SOC_REG_INT_U0_LED_ACCU_CTRL_BCM56870_A0r */
     55         soc_block_list[61],
     56         soc_iprocreg,
     57         1,
     58         0,
     59         0x130b00c,
     60         0,
     61         0,
     62         4,
     63         soc_U0_LED_ACCU_CTRL_BCM56870_A0r_fields,
     64         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
     65         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
     66         -1,
     67         -1,
     68         3,
     69     },
     70 #endif /* chips */
     71 
     72 #if defined(BCM_88690_A0)
     73     { /* SOC_REG_INT_U0_LED_ACCU_CTRL_BCM88690_A0r */
     74         soc_block_list[61],
     75         soc_iprocreg,
     76         1,
     77         0,
     78         0x130b00c,
     79         0,
     80         0,
     81         4,
     82         soc_U0_LED_ACCU_CTRL_BCM88690_A0r_fields,
     83         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
     84         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
     85         -1,
     86         -1,
     87     },
     88 #endif /* chips */
     89 
     90 #if defined(BCM_88690_B0)
     91     { /* SOC_REG_INT_U0_LED_ACCU_CTRL_BCM88690_B0r */
     92         soc_block_list[61],
     93         soc_iprocreg,
     94         1,
     95         0,
     96         0x130b00c,
     97         0,
     98         0,
     99         4,
    100         soc_U0_LED_ACCU_CTRL_BCM88690_B0r_fields,
    101         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
    102         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
    103         -1,
    104         -1,
    105     },
    106 #endif /* chips */
    107 
    108 #if defined(BCM_88790_A0)
    109     { /* SOC_REG_INT_U0_LED_ACCU_STATUSr */
    110         soc_block_list[61],
    111         soc_iprocreg,
    112         1,
    113         0,
    114         0x130b030,
    115         0,
    116         0,
    117         1,
    118         soc_U0_LED_ACCU_STATUSr_fields,
    119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    120         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    121         -1,
    122         -1,
    123     },
    124 #endif /* chips */
    125 
    126 #if defined(BCM_56370_A0)
    127     { /* SOC_REG_INT_U0_LED_ACCU_STATUS_BCM56370_A0r */
    128         soc_block_list[61],
    129         soc_iprocreg,
    130         1,
    131         0,
    132         0x1000b030,
    133         0,
    134         0,
    135         1,
    136         soc_U0_LED_ACCU_STATUS_BCM56870_A0r_fields,
    137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    138         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    139         -1,
    140         -1,
    141         3,
    142     },
    143 #endif /* chips */
    144 
    145 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
    146     defined(BCM_56980_A0) || defined(BCM_56980_B0)
    147     { /* SOC_REG_INT_U0_LED_ACCU_STATUS_BCM56870_A0r */
    148         soc_block_list[61],
    149         soc_iprocreg,
    150         1,
    151         0,
    152         0x130b030,
    153         0,
    154         0,
    155         1,
    156         soc_U0_LED_ACCU_STATUS_BCM56870_A0r_fields,
    157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    158         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    159         -1,
    160         -1,
    161         3,
    162     },
    163 #endif /* chips */
    164 
    165 #if defined(BCM_88690_A0)
    166     { /* SOC_REG_INT_U0_LED_ACCU_STATUS_BCM88690_A0r */
    167         soc_block_list[61],
    168         soc_iprocreg,
    169         1,
    170         0,
    171         0x130b030,
    172         0,
    173         0,
    174         1,
    175         soc_U0_LED_ACCU_STATUS_BCM88690_A0r_fields,
    176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    177         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    178         -1,
    179         -1,
    180     },
    181 #endif /* chips */
    182 
    183 #if defined(BCM_88690_B0)
    184     { /* SOC_REG_INT_U0_LED_ACCU_STATUS_BCM88690_B0r */
    185         soc_block_list[61],
    186         soc_iprocreg,
    187         1,
    188         0,
    189         0x130b030,
    190         0,
    191         0,
    192         1,
    193         soc_U0_LED_ACCU_STATUS_BCM88690_B0r_fields,
    194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    195         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    196         -1,
    197         -1,
    198     },
    199 #endif /* chips */
    200 
    201 #if defined(BCM_88790_A0)
    202     { /* SOC_REG_INT_U0_LED_CLK_DIV_CTRLr */
    203         soc_block_list[61],
    204         soc_iprocreg,
    205         1,
    206         0,
    207         0x130b014,
    208         0,
    209         0,
    210         1,
    211         soc_U0_LED_CLK_DIV_CTRLr_fields,
    212         SOC_RESET_VAL_DEC(0x00000064, 0x00000000)
    213         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    214         -1,
    215         -1,
    216     },
    217 #endif /* chips */
    218 
    219 #if defined(BCM_56370_A0)
    220     { /* SOC_REG_INT_U0_LED_CLK_DIV_CTRL_BCM56370_A0r */
    221         soc_block_list[61],
    222         soc_iprocreg,
    223         1,
    224         0,
    225         0x1000b014,
    226         0,
    227         0,
    228         1,
    229         soc_CMIC_LEDUP0_CLK_DIV_BCM88950_A0r_fields,
    230         SOC_RESET_VAL_DEC(0x00000064, 0x00000000)
    231         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    232         -1,
    233         -1,
    234         3,
    235     },
    236 #endif /* chips */
    237 
    238 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
    239     defined(BCM_56980_A0) || defined(BCM_56980_B0)
    240     { /* SOC_REG_INT_U0_LED_CLK_DIV_CTRL_BCM56870_A0r */
    241         soc_block_list[61],
    242         soc_iprocreg,
    243         1,
    244         0,
    245         0x130b014,
    246         0,
    247         0,
    248         1,
    249         soc_CMIC_LEDUP0_CLK_DIV_BCM88950_A0r_fields,
    250         SOC_RESET_VAL_DEC(0x00000064, 0x00000000)
    251         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    252         -1,
    253         -1,
    254         3,
    255     },
    256 #endif /* chips */
    257 
    258 #if defined(BCM_88690_A0)
    259     { /* SOC_REG_INT_U0_LED_CLK_DIV_CTRL_BCM88690_A0r */
    260         soc_block_list[61],
    261         soc_iprocreg,
    262         1,
    263         0,
    264         0x130b014,
    265         0,
    266         0,
    267         1,
    268         soc_U0_LED_CLK_DIV_CTRL_BCM88690_A0r_fields,
    269         SOC_RESET_VAL_DEC(0x00000064, 0x00000000)
    270         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    271         -1,
    272         -1,
    273     },
    274 #endif /* chips */
    275 
    276 #if defined(BCM_88690_B0)
    277     { /* SOC_REG_INT_U0_LED_CLK_DIV_CTRL_BCM88690_B0r */
    278         soc_block_list[61],
    279         soc_iprocreg,
    280         1,
    281         0,
    282         0x130b014,
    283         0,
    284         0,
    285         1,
    286         soc_U0_LED_CLK_DIV_CTRL_BCM88690_B0r_fields,
    287         SOC_RESET_VAL_DEC(0x00000064, 0x00000000)
    288         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    289         -1,
    290         -1,
    291     },
    292 #endif /* chips */
    293 
    294 #if defined(BCM_88790_A0)
    295     { /* SOC_REG_INT_U0_LED_INTR_ENABLEr */
    296         soc_block_list[61],
    297         soc_iprocreg,
    298         1,
    299         0,
    300         0x130b038,
    301         0,
    302         0,
    303         6,
    304         soc_U0_LED_INTR_ENABLEr_fields,
    305         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
    306         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
    307         -1,
    308         -1,
    309     },
    310 #endif /* chips */
    311 
    312 #if defined(BCM_56370_A0)
    313     { /* SOC_REG_INT_U0_LED_INTR_ENABLE_BCM56370_A0r */
    314         soc_block_list[61],
    315         soc_iprocreg,
    316         1,
    317         0,
    318         0x1000b038,
    319         0,
    320         0,
    321         6,
    322         soc_U0_LED_INTR_ENABLE_BCM56870_A0r_fields,
    323         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
    324         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
    325         -1,
    326         -1,
    327         3,
    328     },
    329 #endif /* chips */
    330 
    331 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
    332     defined(BCM_56980_A0) || defined(BCM_56980_B0)
    333     { /* SOC_REG_INT_U0_LED_INTR_ENABLE_BCM56870_A0r */
    334         soc_block_list[61],
    335         soc_iprocreg,
    336         1,
    337         0,
    338         0x130b038,
    339         0,
    340         0,
    341         6,
    342         soc_U0_LED_INTR_ENABLE_BCM56870_A0r_fields,
    343         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
    344         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
    345         -1,
    346         -1,
    347         3,
    348     },
    349 #endif /* chips */
    350 
    351 #if defined(BCM_88690_A0)
    352     { /* SOC_REG_INT_U0_LED_INTR_ENABLE_BCM88690_A0r */
    353         soc_block_list[61],
    354         soc_iprocreg,
    355         1,
    356         0,
    357         0x130b038,
    358         0,
    359         0,
    360         6,
    361         soc_U0_LED_INTR_ENABLE_BCM88690_A0r_fields,
    362         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
    363         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
    364         -1,
    365         -1,
    366     },
    367 #endif /* chips */
    368 
    369 #if defined(BCM_88690_B0)
    370     { /* SOC_REG_INT_U0_LED_INTR_ENABLE_BCM88690_B0r */
    371         soc_block_list[61],
    372         soc_iprocreg,
    373         1,
    374         0,
    375         0x130b038,
    376         0,
    377         0,
    378         6,
    379         soc_U0_LED_INTR_ENABLE_BCM88690_B0r_fields,
    380         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
    381         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
    382         -1,
    383         -1,
    384     },
    385 #endif /* chips */
    386 
    387 #if defined(BCM_88790_A0)
    388     { /* SOC_REG_INT_U0_LED_REFRESH_CTRLr */
    389         soc_block_list[61],
    390         soc_iprocreg,
    391         1,
    392         0,
    393         0x130b010,
    394         0,
    395         0,
    396         1,
    397         soc_U0_LED_REFRESH_CTRLr_fields,
    398         SOC_RESET_VAL_DEC(0x01851960, 0x00000000)
    399         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    400         -1,
    401         -1,
    402     },
    403 #endif /* chips */
    404 
    405 #if defined(BCM_56370_A0)
    406     { /* SOC_REG_INT_U0_LED_REFRESH_CTRL_BCM56370_A0r */
    407         soc_block_list[61],
    408         soc_iprocreg,
    409         1,
    410         0,
    411         0x1000b010,
    412         0,
    413         0,
    414         1,
    415         soc_U0_LED_REFRESH_CTRL_BCM56870_A0r_fields,
    416         SOC_RESET_VAL_DEC(0x01851960, 0x00000000)
    417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    418         -1,
    419         -1,
    420         3,
    421     },
    422 #endif /* chips */
    423 
    424 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
    425     defined(BCM_56980_A0) || defined(BCM_56980_B0)
    426     { /* SOC_REG_INT_U0_LED_REFRESH_CTRL_BCM56870_A0r */
    427         soc_block_list[61],
    428         soc_iprocreg,
    429         1,
    430         0,
    431         0x130b010,
    432         0,
    433         0,
    434         1,
    435         soc_U0_LED_REFRESH_CTRL_BCM56870_A0r_fields,
    436         SOC_RESET_VAL_DEC(0x01851960, 0x00000000)
    437         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    438         -1,
    439         -1,
    440         3,
    441     },
    442 #endif /* chips */
    443 
    444 #if defined(BCM_88690_A0)
    445     { /* SOC_REG_INT_U0_LED_REFRESH_CTRL_BCM88690_A0r */
    446         soc_block_list[61],
    447         soc_iprocreg,
    448         1,
    449         0,
    450         0x130b010,
    451         0,
    452         0,
    453         1,
    454         soc_U0_LED_REFRESH_CTRL_BCM88690_A0r_fields,
    455         SOC_RESET_VAL_DEC(0x01851960, 0x00000000)
    456         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    457         -1,
    458         -1,
    459     },
    460 #endif /* chips */
    461 
    462 #if defined(BCM_88690_B0)
    463     { /* SOC_REG_INT_U0_LED_REFRESH_CTRL_BCM88690_B0r */
    464         soc_block_list[61],
    465         soc_iprocreg,
    466         1,
    467         0,
    468         0x130b010,
    469         0,
    470         0,
    471         1,
    472         soc_U0_LED_REFRESH_CTRL_BCM88690_B0r_fields,
    473         SOC_RESET_VAL_DEC(0x01851960, 0x00000000)
    474         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    475         -1,
    476         -1,
    477     },
    478 #endif /* chips */
    479 
    480 #if defined(BCM_88790_A0)
    481     { /* SOC_REG_INT_U0_LED_SEND_CTRLr */
    482         soc_block_list[61],
    483         soc_iprocreg,
    484         1,
    485         0,
    486         0x130b018,
    487         0,
    488         0,
    489         1,
    490         soc_U0_LED_SEND_CTRLr_fields,
    491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    492         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
    493         -1,
    494         -1,
    495     },
    496 #endif /* chips */
    497 
    498 #if defined(BCM_88790_A0)
    499     { /* SOC_REG_INT_U0_LED_SEND_CTRL_0r */
    500         soc_block_list[61],
    501         soc_iprocreg,
    502         1,
    503         0,
    504         0x130b01c,
    505         0,
    506         0,
    507         3,
    508         soc_U0_LED_SEND_CTRL_0r_fields,
    509         SOC_RESET_VAL_DEC(0x04066000, 0x00000000)
    510         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    511         -1,
    512         -1,
    513     },
    514 #endif /* chips */
    515 
    516 #if defined(BCM_88790_A0)
    517     { /* SOC_REG_INT_U0_LED_SEND_CTRL_1r */
    518         soc_block_list[61],
    519         soc_iprocreg,
    520         1,
    521         0,
    522         0x130b020,
    523         0,
    524         0,
    525         3,
    526         soc_U0_LED_SEND_CTRL_1r_fields,
    527         SOC_RESET_VAL_DEC(0x04066198, 0x00000000)
    528         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    529         -1,
    530         -1,
    531     },
    532 #endif /* chips */
    533 
    534 #if defined(BCM_88790_A0)
    535     { /* SOC_REG_INT_U0_LED_SEND_CTRL_2r */
    536         soc_block_list[61],
    537         soc_iprocreg,
    538         1,
    539         0,
    540         0x130b024,
    541         0,
    542         0,
    543         3,
    544         soc_U0_LED_SEND_CTRL_2r_fields,
    545         SOC_RESET_VAL_DEC(0x04066330, 0x00000000)
    546         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    547         -1,
    548         -1,
    549     },
    550 #endif /* chips */
    551 
    552 #if defined(BCM_88790_A0)
    553     { /* SOC_REG_INT_U0_LED_SEND_CTRL_3r */
    554         soc_block_list[61],
    555         soc_iprocreg,
    556         1,
    557         0,
    558         0x130b028,
    559         0,
    560         0,
    561         3,
    562         soc_U0_LED_SEND_CTRL_3r_fields,
    563         SOC_RESET_VAL_DEC(0x040664c8, 0x00000000)
    564         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    565         -1,
    566         -1,
    567     },
    568 #endif /* chips */
    569 
    570 #if defined(BCM_88790_A0)
    571     { /* SOC_REG_INT_U0_LED_SEND_CTRL_4r */
    572         soc_block_list[61],
    573         soc_iprocreg,
    574         1,
    575         0,
    576         0x130b02c,
    577         0,
    578         0,
    579         3,
    580         soc_U0_LED_SEND_CTRL_4r_fields,
    581         SOC_RESET_VAL_DEC(0x04066660, 0x00000000)
    582         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    583         -1,
    584         -1,
    585     },
    586 #endif /* chips */
    587 
    588 #if defined(BCM_56370_A0)
    589     { /* SOC_REG_INT_U0_LED_SEND_CTRL_0_BCM56370_A0r */
    590         soc_block_list[61],
    591         soc_iprocreg,
    592         1,
    593         0,
    594         0x1000b01c,
    595         0,
    596         0,
    597         3,
    598         soc_U0_LED_SEND_CTRL_0_BCM56870_A0r_fields,
    599         SOC_RESET_VAL_DEC(0x04066000, 0x00000000)
    600         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    601         -1,
    602         -1,
    603         3,
    604     },
    605 #endif /* chips */
    606 
    607 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
    608     defined(BCM_56980_A0) || defined(BCM_56980_B0)
    609     { /* SOC_REG_INT_U0_LED_SEND_CTRL_0_BCM56870_A0r */
    610         soc_block_list[61],
    611         soc_iprocreg,
    612         1,
    613         0,
    614         0x130b01c,
    615         0,
    616         0,
    617         3,
    618         soc_U0_LED_SEND_CTRL_0_BCM56870_A0r_fields,
    619         SOC_RESET_VAL_DEC(0x04066000, 0x00000000)
    620         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    621         -1,
    622         -1,
    623         3,
    624     },
    625 #endif /* chips */
    626 
    627 #if defined(BCM_88690_A0)
    628     { /* SOC_REG_INT_U0_LED_SEND_CTRL_0_BCM88690_A0r */
    629         soc_block_list[61],
    630         soc_iprocreg,
    631         1,
    632         0,
    633         0x130b01c,
    634         0,
    635         0,
    636         3,
    637         soc_U0_LED_SEND_CTRL_0_BCM88690_A0r_fields,
    638         SOC_RESET_VAL_DEC(0x04066000, 0x00000000)
    639         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    640         -1,
    641         -1,
    642     },
    643 #endif /* chips */
    644 
    645 #if defined(BCM_88690_B0)
    646     { /* SOC_REG_INT_U0_LED_SEND_CTRL_0_BCM88690_B0r */
    647         soc_block_list[61],
    648         soc_iprocreg,
    649         1,
    650         0,
    651         0x130b01c,
    652         0,
    653         0,
    654         3,
    655         soc_U0_LED_SEND_CTRL_0_BCM88690_B0r_fields,
    656         SOC_RESET_VAL_DEC(0x04066000, 0x00000000)
    657         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    658         -1,
    659         -1,
    660     },
    661 #endif /* chips */
    662 
    663 #if defined(BCM_56370_A0)
    664     { /* SOC_REG_INT_U0_LED_SEND_CTRL_1_BCM56370_A0r */
    665         soc_block_list[61],
    666         soc_iprocreg,
    667         1,
    668         0,
    669         0x1000b020,
    670         0,
    671         0,
    672         3,
    673         soc_U0_LED_SEND_CTRL_1_BCM56870_A0r_fields,
    674         SOC_RESET_VAL_DEC(0x04066198, 0x00000000)
    675         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    676         -1,
    677         -1,
    678         3,
    679     },
    680 #endif /* chips */
    681 
    682 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
    683     defined(BCM_56980_A0) || defined(BCM_56980_B0)
    684     { /* SOC_REG_INT_U0_LED_SEND_CTRL_1_BCM56870_A0r */
    685         soc_block_list[61],
    686         soc_iprocreg,
    687         1,
    688         0,
    689         0x130b020,
    690         0,
    691         0,
    692         3,
    693         soc_U0_LED_SEND_CTRL_1_BCM56870_A0r_fields,
    694         SOC_RESET_VAL_DEC(0x04066198, 0x00000000)
    695         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    696         -1,
    697         -1,
    698         3,
    699     },
    700 #endif /* chips */
    701 
    702 #if defined(BCM_88690_A0)
    703     { /* SOC_REG_INT_U0_LED_SEND_CTRL_1_BCM88690_A0r */
    704         soc_block_list[61],
    705         soc_iprocreg,
    706         1,
    707         0,
    708         0x130b020,
    709         0,
    710         0,
    711         3,
    712         soc_U0_LED_SEND_CTRL_1_BCM88690_A0r_fields,
    713         SOC_RESET_VAL_DEC(0x04066198, 0x00000000)
    714         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    715         -1,
    716         -1,
    717     },
    718 #endif /* chips */
    719 
    720 #if defined(BCM_88690_B0)
    721     { /* SOC_REG_INT_U0_LED_SEND_CTRL_1_BCM88690_B0r */
    722         soc_block_list[61],
    723         soc_iprocreg,
    724         1,
    725         0,
    726         0x130b020,
    727         0,
    728         0,
    729         3,
    730         soc_U0_LED_SEND_CTRL_1_BCM88690_B0r_fields,
    731         SOC_RESET_VAL_DEC(0x04066198, 0x00000000)
    732         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    733         -1,
    734         -1,
    735     },
    736 #endif /* chips */
    737 
    738 #if defined(BCM_56370_A0)
    739     { /* SOC_REG_INT_U0_LED_SEND_CTRL_2_BCM56370_A0r */
    740         soc_block_list[61],
    741         soc_iprocreg,
    742         1,
    743         0,
    744         0x1000b024,
    745         0,
    746         0,
    747         3,
    748         soc_U0_LED_SEND_CTRL_2_BCM56870_A0r_fields,
    749         SOC_RESET_VAL_DEC(0x04066330, 0x00000000)
    750         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    751         -1,
    752         -1,
    753         3,
    754     },
    755 #endif /* chips */
    756 
    757 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
    758     defined(BCM_56980_A0) || defined(BCM_56980_B0)
    759     { /* SOC_REG_INT_U0_LED_SEND_CTRL_2_BCM56870_A0r */
    760         soc_block_list[61],
    761         soc_iprocreg,
    762         1,
    763         0,
    764         0x130b024,
    765         0,
    766         0,
    767         3,
    768         soc_U0_LED_SEND_CTRL_2_BCM56870_A0r_fields,
    769         SOC_RESET_VAL_DEC(0x04066330, 0x00000000)
    770         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    771         -1,
    772         -1,
    773         3,
    774     },
    775 #endif /* chips */
    776 
    777 #if defined(BCM_88690_A0)
    778     { /* SOC_REG_INT_U0_LED_SEND_CTRL_2_BCM88690_A0r */
    779         soc_block_list[61],
    780         soc_iprocreg,
    781         1,
    782         0,
    783         0x130b024,
    784         0,
    785         0,
    786         3,
    787         soc_U0_LED_SEND_CTRL_2_BCM88690_A0r_fields,
    788         SOC_RESET_VAL_DEC(0x04066330, 0x00000000)
    789         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    790         -1,
    791         -1,
    792     },
    793 #endif /* chips */
    794 
    795 #if defined(BCM_88690_B0)
    796     { /* SOC_REG_INT_U0_LED_SEND_CTRL_2_BCM88690_B0r */
    797         soc_block_list[61],
    798         soc_iprocreg,
    799         1,
    800         0,
    801         0x130b024,
    802         0,
    803         0,
    804         3,
    805         soc_U0_LED_SEND_CTRL_2_BCM88690_B0r_fields,
    806         SOC_RESET_VAL_DEC(0x04066330, 0x00000000)
    807         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    808         -1,
    809         -1,
    810     },
    811 #endif /* chips */
    812 
    813 #if defined(BCM_56370_A0)
    814     { /* SOC_REG_INT_U0_LED_SEND_CTRL_3_BCM56370_A0r */
    815         soc_block_list[61],
    816         soc_iprocreg,
    817         1,
    818         0,
    819         0x1000b028,
    820         0,
    821         0,
    822         3,
    823         soc_U0_LED_SEND_CTRL_3_BCM56870_A0r_fields,
    824         SOC_RESET_VAL_DEC(0x040664c8, 0x00000000)
    825         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    826         -1,
    827         -1,
    828         3,
    829     },
    830 #endif /* chips */
    831 
    832 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
    833     defined(BCM_56980_A0) || defined(BCM_56980_B0)
    834     { /* SOC_REG_INT_U0_LED_SEND_CTRL_3_BCM56870_A0r */
    835         soc_block_list[61],
    836         soc_iprocreg,
    837         1,
    838         0,
    839         0x130b028,
    840         0,
    841         0,
    842         3,
    843         soc_U0_LED_SEND_CTRL_3_BCM56870_A0r_fields,
    844         SOC_RESET_VAL_DEC(0x040664c8, 0x00000000)
    845         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    846         -1,
    847         -1,
    848         3,
    849     },
    850 #endif /* chips */
    851 
    852 #if defined(BCM_88690_A0)
    853     { /* SOC_REG_INT_U0_LED_SEND_CTRL_3_BCM88690_A0r */
    854         soc_block_list[61],
    855         soc_iprocreg,
    856         1,
    857         0,
    858         0x130b028,
    859         0,
    860         0,
    861         3,
    862         soc_U0_LED_SEND_CTRL_3_BCM88690_A0r_fields,
    863         SOC_RESET_VAL_DEC(0x040664c8, 0x00000000)
    864         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    865         -1,
    866         -1,
    867     },
    868 #endif /* chips */
    869 
    870 #if defined(BCM_88690_B0)
    871     { /* SOC_REG_INT_U0_LED_SEND_CTRL_3_BCM88690_B0r */
    872         soc_block_list[61],
    873         soc_iprocreg,
    874         1,
    875         0,
    876         0x130b028,
    877         0,
    878         0,
    879         3,
    880         soc_U0_LED_SEND_CTRL_3_BCM88690_B0r_fields,
    881         SOC_RESET_VAL_DEC(0x040664c8, 0x00000000)
    882         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    883         -1,
    884         -1,
    885     },
    886 #endif /* chips */
    887 
    888 #if defined(BCM_56370_A0)
    889     { /* SOC_REG_INT_U0_LED_SEND_CTRL_4_BCM56370_A0r */
    890         soc_block_list[61],
    891         soc_iprocreg,
    892         1,
    893         0,
    894         0x1000b02c,
    895         0,
    896         0,
    897         3,
    898         soc_U0_LED_SEND_CTRL_4_BCM56870_A0r_fields,
    899         SOC_RESET_VAL_DEC(0x04066660, 0x00000000)
    900         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    901         -1,
    902         -1,
    903         3,
    904     },
    905 #endif /* chips */
    906 
    907 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
    908     defined(BCM_56980_A0) || defined(BCM_56980_B0)
    909     { /* SOC_REG_INT_U0_LED_SEND_CTRL_4_BCM56870_A0r */
    910         soc_block_list[61],
    911         soc_iprocreg,
    912         1,
    913         0,
    914         0x130b02c,
    915         0,
    916         0,
    917         3,
    918         soc_U0_LED_SEND_CTRL_4_BCM56870_A0r_fields,
    919         SOC_RESET_VAL_DEC(0x04066660, 0x00000000)
    920         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    921         -1,
    922         -1,
    923         3,
    924     },
    925 #endif /* chips */
    926 
    927 #if defined(BCM_88690_A0)
    928     { /* SOC_REG_INT_U0_LED_SEND_CTRL_4_BCM88690_A0r */
    929         soc_block_list[61],
    930         soc_iprocreg,
    931         1,
    932         0,
    933         0x130b02c,
    934         0,
    935         0,
    936         3,
    937         soc_U0_LED_SEND_CTRL_4_BCM88690_A0r_fields,
    938         SOC_RESET_VAL_DEC(0x04066660, 0x00000000)
    939         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    940         -1,
    941         -1,
    942     },
    943 #endif /* chips */
    944 
    945 #if defined(BCM_88690_B0)
    946     { /* SOC_REG_INT_U0_LED_SEND_CTRL_4_BCM88690_B0r */
    947         soc_block_list[61],
    948         soc_iprocreg,
    949         1,
    950         0,
    951         0x130b02c,
    952         0,
    953         0,
    954         3,
    955         soc_U0_LED_SEND_CTRL_4_BCM88690_B0r_fields,
    956         SOC_RESET_VAL_DEC(0x04066660, 0x00000000)
    957         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
    958         -1,
    959         -1,
    960     },
    961 #endif /* chips */
    962 
    963 #if defined(BCM_56370_A0)
    964     { /* SOC_REG_INT_U0_LED_SEND_CTRL_BCM56370_A0r */
    965         soc_block_list[61],
    966         soc_iprocreg,
    967         1,
    968         0,
    969         0x1000b018,
    970         0,
    971         0,
    972         1,
    973         soc_U0_LED_SEND_CTRL_BCM56870_A0r_fields,
    974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    975         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
    976         -1,
    977         -1,
    978         3,
    979     },
    980 #endif /* chips */
    981 
    982 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
    983     defined(BCM_56980_A0) || defined(BCM_56980_B0)
    984     { /* SOC_REG_INT_U0_LED_SEND_CTRL_BCM56870_A0r */
    985         soc_block_list[61],
    986         soc_iprocreg,
    987         1,
    988         0,
    989         0x130b018,
    990         0,
    991         0,
    992         1,
    993         soc_U0_LED_SEND_CTRL_BCM56870_A0r_fields,
    994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    995         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
    996         -1,
    997         -1,
    998         3,
    999     },
   1000 #endif /* chips */
   1001 
   1002 #if defined(BCM_88690_A0)
   1003     { /* SOC_REG_INT_U0_LED_SEND_CTRL_BCM88690_A0r */
   1004         soc_block_list[61],
   1005         soc_iprocreg,
   1006         1,
   1007         0,
   1008         0x130b018,
   1009         0,
   1010         0,
   1011         1,
   1012         soc_U0_LED_SEND_CTRL_BCM88690_A0r_fields,
   1013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1014         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   1015         -1,
   1016         -1,
   1017     },
   1018 #endif /* chips */
   1019 
   1020 #if defined(BCM_88690_B0)
   1021     { /* SOC_REG_INT_U0_LED_SEND_CTRL_BCM88690_B0r */
   1022         soc_block_list[61],
   1023         soc_iprocreg,
   1024         1,
   1025         0,
   1026         0x130b018,
   1027         0,
   1028         0,
   1029         1,
   1030         soc_U0_LED_SEND_CTRL_BCM88690_B0r_fields,
   1031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1032         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   1033         -1,
   1034         -1,
   1035     },
   1036 #endif /* chips */
   1037 
   1038 #if defined(BCM_88790_A0)
   1039     { /* SOC_REG_INT_U0_LED_SEND_STATUSr */
   1040         soc_block_list[61],
   1041         soc_iprocreg,
   1042         1,
   1043         0,
   1044         0x130b034,
   1045         0,
   1046         0,
   1047         1,
   1048         soc_U0_LED_SEND_STATUSr_fields,
   1049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1050         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1051         -1,
   1052         -1,
   1053     },
   1054 #endif /* chips */
   1055 
   1056 #if defined(BCM_56370_A0)
   1057     { /* SOC_REG_INT_U0_LED_SEND_STATUS_BCM56370_A0r */
   1058         soc_block_list[61],
   1059         soc_iprocreg,
   1060         1,
   1061         0,
   1062         0x1000b034,
   1063         0,
   1064         0,
   1065         1,
   1066         soc_U0_LED_SEND_STATUS_BCM56870_A0r_fields,
   1067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1068         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1069         -1,
   1070         -1,
   1071         3,
   1072     },
   1073 #endif /* chips */
   1074 
   1075 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1076     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1077     { /* SOC_REG_INT_U0_LED_SEND_STATUS_BCM56870_A0r */
   1078         soc_block_list[61],
   1079         soc_iprocreg,
   1080         1,
   1081         0,
   1082         0x130b034,
   1083         0,
   1084         0,
   1085         1,
   1086         soc_U0_LED_SEND_STATUS_BCM56870_A0r_fields,
   1087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1088         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1089         -1,
   1090         -1,
   1091         3,
   1092     },
   1093 #endif /* chips */
   1094 
   1095 #if defined(BCM_88690_A0)
   1096     { /* SOC_REG_INT_U0_LED_SEND_STATUS_BCM88690_A0r */
   1097         soc_block_list[61],
   1098         soc_iprocreg,
   1099         1,
   1100         0,
   1101         0x130b034,
   1102         0,
   1103         0,
   1104         1,
   1105         soc_U0_LED_SEND_STATUS_BCM88690_A0r_fields,
   1106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1107         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1108         -1,
   1109         -1,
   1110     },
   1111 #endif /* chips */
   1112 
   1113 #if defined(BCM_88690_B0)
   1114     { /* SOC_REG_INT_U0_LED_SEND_STATUS_BCM88690_B0r */
   1115         soc_block_list[61],
   1116         soc_iprocreg,
   1117         1,
   1118         0,
   1119         0x130b034,
   1120         0,
   1121         0,
   1122         1,
   1123         soc_U0_LED_SEND_STATUS_BCM88690_B0r_fields,
   1124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1125         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1126         -1,
   1127         -1,
   1128     },
   1129 #endif /* chips */
   1130 
   1131 #if defined(BCM_88790_A0)
   1132     { /* SOC_REG_INT_U0_LED_SRAM_CTRLr */
   1133         soc_block_list[61],
   1134         soc_iprocreg,
   1135         1,
   1136         0,
   1137         0x130b000,
   1138         0,
   1139         0,
   1140         1,
   1141         soc_U0_LED_SRAM_CTRLr_fields,
   1142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1143         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   1144         -1,
   1145         -1,
   1146     },
   1147 #endif /* chips */
   1148 
   1149 #if defined(BCM_56370_A0)
   1150     { /* SOC_REG_INT_U0_LED_SRAM_CTRL_BCM56370_A0r */
   1151         soc_block_list[61],
   1152         soc_iprocreg,
   1153         1,
   1154         0,
   1155         0x1000b000,
   1156         0,
   1157         0,
   1158         1,
   1159         soc_U0_LED_SRAM_CTRL_BCM56870_A0r_fields,
   1160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1161         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1162         -1,
   1163         -1,
   1164         3,
   1165     },
   1166 #endif /* chips */
   1167 
   1168 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1169     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1170     { /* SOC_REG_INT_U0_LED_SRAM_CTRL_BCM56870_A0r */
   1171         soc_block_list[61],
   1172         soc_iprocreg,
   1173         1,
   1174         0,
   1175         0x130b000,
   1176         0,
   1177         0,
   1178         1,
   1179         soc_U0_LED_SRAM_CTRL_BCM56870_A0r_fields,
   1180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1182         -1,
   1183         -1,
   1184         3,
   1185     },
   1186 #endif /* chips */
   1187 
   1188 #if defined(BCM_88690_A0)
   1189     { /* SOC_REG_INT_U0_LED_SRAM_CTRL_BCM88690_A0r */
   1190         soc_block_list[61],
   1191         soc_iprocreg,
   1192         1,
   1193         0,
   1194         0x130b000,
   1195         0,
   1196         0,
   1197         1,
   1198         soc_U0_LED_SRAM_CTRL_BCM88690_A0r_fields,
   1199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1200         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   1201         -1,
   1202         -1,
   1203     },
   1204 #endif /* chips */
   1205 
   1206 #if defined(BCM_88690_B0)
   1207     { /* SOC_REG_INT_U0_LED_SRAM_CTRL_BCM88690_B0r */
   1208         soc_block_list[61],
   1209         soc_iprocreg,
   1210         1,
   1211         0,
   1212         0x130b000,
   1213         0,
   1214         0,
   1215         1,
   1216         soc_U0_LED_SRAM_CTRL_BCM88690_B0r_fields,
   1217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1218         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   1219         -1,
   1220         -1,
   1221     },
   1222 #endif /* chips */
   1223 
   1224 #if defined(BCM_88790_A0)
   1225     { /* SOC_REG_INT_U0_LED_SRAM_ECC_CTRLr */
   1226         soc_block_list[61],
   1227         soc_iprocreg,
   1228         1,
   1229         0,
   1230         0x130b004,
   1231         0,
   1232         0,
   1233         3,
   1234         soc_U0_LED_SRAM_ECC_CTRLr_fields,
   1235         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   1236         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   1237         -1,
   1238         -1,
   1239     },
   1240 #endif /* chips */
   1241 
   1242 #if defined(BCM_56370_A0)
   1243     { /* SOC_REG_INT_U0_LED_SRAM_ECC_CTRL_BCM56370_A0r */
   1244         soc_block_list[61],
   1245         soc_iprocreg,
   1246         1,
   1247         0,
   1248         0x1000b004,
   1249         0,
   1250         0,
   1251         3,
   1252         soc_U0_LED_SRAM_ECC_CTRL_BCM56870_A0r_fields,
   1253         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   1254         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   1255         -1,
   1256         -1,
   1257         3,
   1258     },
   1259 #endif /* chips */
   1260 
   1261 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1262     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1263     { /* SOC_REG_INT_U0_LED_SRAM_ECC_CTRL_BCM56870_A0r */
   1264         soc_block_list[61],
   1265         soc_iprocreg,
   1266         1,
   1267         0,
   1268         0x130b004,
   1269         0,
   1270         0,
   1271         3,
   1272         soc_U0_LED_SRAM_ECC_CTRL_BCM56870_A0r_fields,
   1273         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   1274         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   1275         -1,
   1276         -1,
   1277         3,
   1278     },
   1279 #endif /* chips */
   1280 
   1281 #if defined(BCM_88690_A0)
   1282     { /* SOC_REG_INT_U0_LED_SRAM_ECC_CTRL_BCM88690_A0r */
   1283         soc_block_list[61],
   1284         soc_iprocreg,
   1285         1,
   1286         0,
   1287         0x130b004,
   1288         0,
   1289         0,
   1290         3,
   1291         soc_U0_LED_SRAM_ECC_CTRL_BCM88690_A0r_fields,
   1292         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   1293         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   1294         -1,
   1295         -1,
   1296     },
   1297 #endif /* chips */
   1298 
   1299 #if defined(BCM_88690_B0)
   1300     { /* SOC_REG_INT_U0_LED_SRAM_ECC_CTRL_BCM88690_B0r */
   1301         soc_block_list[61],
   1302         soc_iprocreg,
   1303         1,
   1304         0,
   1305         0x130b004,
   1306         0,
   1307         0,
   1308         3,
   1309         soc_U0_LED_SRAM_ECC_CTRL_BCM88690_B0r_fields,
   1310         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   1311         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   1312         -1,
   1313         -1,
   1314     },
   1315 #endif /* chips */
   1316 
   1317 #if defined(BCM_88790_A0)
   1318     { /* SOC_REG_INT_U0_LED_SRAM_ECC_STATUSr */
   1319         soc_block_list[61],
   1320         soc_iprocreg,
   1321         1,
   1322         0,
   1323         0x130b008,
   1324         0,
   1325         0,
   1326         8,
   1327         soc_U0_LED_SRAM_ECC_STATUSr_fields,
   1328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1329         SOC_RESET_MASK_DEC(0x1fff1fff, 0x00000000)
   1330         -1,
   1331         -1,
   1332     },
   1333 #endif /* chips */
   1334 
   1335 #if defined(BCM_56370_A0)
   1336     { /* SOC_REG_INT_U0_LED_SRAM_ECC_STATUS_BCM56370_A0r */
   1337         soc_block_list[61],
   1338         soc_iprocreg,
   1339         1,
   1340         0,
   1341         0x1000b008,
   1342         0,
   1343         0,
   1344         8,
   1345         soc_U0_LED_SRAM_ECC_STATUS_BCM56870_A0r_fields,
   1346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1347         SOC_RESET_MASK_DEC(0x1fff1fff, 0x00000000)
   1348         -1,
   1349         -1,
   1350         3,
   1351     },
   1352 #endif /* chips */
   1353 
   1354 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1355     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1356     { /* SOC_REG_INT_U0_LED_SRAM_ECC_STATUS_BCM56870_A0r */
   1357         soc_block_list[61],
   1358         soc_iprocreg,
   1359         1,
   1360         0,
   1361         0x130b008,
   1362         0,
   1363         0,
   1364         8,
   1365         soc_U0_LED_SRAM_ECC_STATUS_BCM56870_A0r_fields,
   1366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1367         SOC_RESET_MASK_DEC(0x1fff1fff, 0x00000000)
   1368         -1,
   1369         -1,
   1370         3,
   1371     },
   1372 #endif /* chips */
   1373 
   1374 #if defined(BCM_88690_A0)
   1375     { /* SOC_REG_INT_U0_LED_SRAM_ECC_STATUS_BCM88690_A0r */
   1376         soc_block_list[61],
   1377         soc_iprocreg,
   1378         1,
   1379         0,
   1380         0x130b008,
   1381         0,
   1382         0,
   1383         8,
   1384         soc_U0_LED_SRAM_ECC_STATUS_BCM88690_A0r_fields,
   1385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1386         SOC_RESET_MASK_DEC(0x1fff1fff, 0x00000000)
   1387         -1,
   1388         -1,
   1389     },
   1390 #endif /* chips */
   1391 
   1392 #if defined(BCM_88690_B0)
   1393     { /* SOC_REG_INT_U0_LED_SRAM_ECC_STATUS_BCM88690_B0r */
   1394         soc_block_list[61],
   1395         soc_iprocreg,
   1396         1,
   1397         0,
   1398         0x130b008,
   1399         0,
   1400         0,
   1401         8,
   1402         soc_U0_LED_SRAM_ECC_STATUS_BCM88690_B0r_fields,
   1403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1404         SOC_RESET_MASK_DEC(0x1fff1fff, 0x00000000)
   1405         -1,
   1406         -1,
   1407     },
   1408 #endif /* chips */
   1409 
   1410 #if defined(BCM_88790_A0)
   1411     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_1023_992r */
   1412         soc_block_list[61],
   1413         soc_iprocreg,
   1414         1,
   1415         0,
   1416         0x130b0b8,
   1417         0,
   1418         0,
   1419         1,
   1420         soc_U0_LED_SW_CNFG_LINK_1023_992r_fields,
   1421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1422         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1423         -1,
   1424         -1,
   1425     },
   1426 #endif /* chips */
   1427 
   1428 #if defined(BCM_56370_A0)
   1429     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_1023_992_BCM56370_A0r */
   1430         soc_block_list[61],
   1431         soc_iprocreg,
   1432         1,
   1433         0,
   1434         0x1000b0b8,
   1435         0,
   1436         0,
   1437         1,
   1438         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1440         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1441         -1,
   1442         -1,
   1443         3,
   1444     },
   1445 #endif /* chips */
   1446 
   1447 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1448     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1449     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_1023_992_BCM56870_A0r */
   1450         soc_block_list[61],
   1451         soc_iprocreg,
   1452         1,
   1453         0,
   1454         0x130b0b8,
   1455         0,
   1456         0,
   1457         1,
   1458         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1460         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1461         -1,
   1462         -1,
   1463         3,
   1464     },
   1465 #endif /* chips */
   1466 
   1467 #if defined(BCM_88690_A0)
   1468     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_1023_992_BCM88690_A0r */
   1469         soc_block_list[61],
   1470         soc_iprocreg,
   1471         1,
   1472         0,
   1473         0x130b0b8,
   1474         0,
   1475         0,
   1476         1,
   1477         soc_U0_LED_SW_CNFG_LINK_1023_992_BCM88690_A0r_fields,
   1478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1479         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1480         -1,
   1481         -1,
   1482     },
   1483 #endif /* chips */
   1484 
   1485 #if defined(BCM_88690_B0)
   1486     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_1023_992_BCM88690_B0r */
   1487         soc_block_list[61],
   1488         soc_iprocreg,
   1489         1,
   1490         0,
   1491         0x130b0b8,
   1492         0,
   1493         0,
   1494         1,
   1495         soc_U0_LED_SW_CNFG_LINK_1023_992_BCM88690_B0r_fields,
   1496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1498         -1,
   1499         -1,
   1500     },
   1501 #endif /* chips */
   1502 
   1503 #if defined(BCM_88790_A0)
   1504     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_127_96r */
   1505         soc_block_list[61],
   1506         soc_iprocreg,
   1507         1,
   1508         0,
   1509         0x130b048,
   1510         0,
   1511         0,
   1512         1,
   1513         soc_U0_LED_SW_CNFG_LINK_127_96r_fields,
   1514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1516         -1,
   1517         -1,
   1518     },
   1519 #endif /* chips */
   1520 
   1521 #if defined(BCM_56370_A0)
   1522     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_127_96_BCM56370_A0r */
   1523         soc_block_list[61],
   1524         soc_iprocreg,
   1525         1,
   1526         0,
   1527         0x1000b048,
   1528         0,
   1529         0,
   1530         1,
   1531         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1534         -1,
   1535         -1,
   1536         3,
   1537     },
   1538 #endif /* chips */
   1539 
   1540 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1541     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1542     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_127_96_BCM56870_A0r */
   1543         soc_block_list[61],
   1544         soc_iprocreg,
   1545         1,
   1546         0,
   1547         0x130b048,
   1548         0,
   1549         0,
   1550         1,
   1551         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1553         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1554         -1,
   1555         -1,
   1556         3,
   1557     },
   1558 #endif /* chips */
   1559 
   1560 #if defined(BCM_88690_A0)
   1561     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_127_96_BCM88690_A0r */
   1562         soc_block_list[61],
   1563         soc_iprocreg,
   1564         1,
   1565         0,
   1566         0x130b048,
   1567         0,
   1568         0,
   1569         1,
   1570         soc_U0_LED_SW_CNFG_LINK_127_96_BCM88690_A0r_fields,
   1571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1572         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1573         -1,
   1574         -1,
   1575     },
   1576 #endif /* chips */
   1577 
   1578 #if defined(BCM_88690_B0)
   1579     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_127_96_BCM88690_B0r */
   1580         soc_block_list[61],
   1581         soc_iprocreg,
   1582         1,
   1583         0,
   1584         0x130b048,
   1585         0,
   1586         0,
   1587         1,
   1588         soc_U0_LED_SW_CNFG_LINK_127_96_BCM88690_B0r_fields,
   1589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1590         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1591         -1,
   1592         -1,
   1593     },
   1594 #endif /* chips */
   1595 
   1596 #if defined(BCM_88790_A0)
   1597     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_159_128r */
   1598         soc_block_list[61],
   1599         soc_iprocreg,
   1600         1,
   1601         0,
   1602         0x130b04c,
   1603         0,
   1604         0,
   1605         1,
   1606         soc_U0_LED_SW_CNFG_LINK_159_128r_fields,
   1607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1608         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1609         -1,
   1610         -1,
   1611     },
   1612 #endif /* chips */
   1613 
   1614 #if defined(BCM_56370_A0)
   1615     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_159_128_BCM56370_A0r */
   1616         soc_block_list[61],
   1617         soc_iprocreg,
   1618         1,
   1619         0,
   1620         0x1000b04c,
   1621         0,
   1622         0,
   1623         1,
   1624         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1626         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1627         -1,
   1628         -1,
   1629         3,
   1630     },
   1631 #endif /* chips */
   1632 
   1633 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1634     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1635     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_159_128_BCM56870_A0r */
   1636         soc_block_list[61],
   1637         soc_iprocreg,
   1638         1,
   1639         0,
   1640         0x130b04c,
   1641         0,
   1642         0,
   1643         1,
   1644         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1646         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1647         -1,
   1648         -1,
   1649         3,
   1650     },
   1651 #endif /* chips */
   1652 
   1653 #if defined(BCM_88690_A0)
   1654     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_159_128_BCM88690_A0r */
   1655         soc_block_list[61],
   1656         soc_iprocreg,
   1657         1,
   1658         0,
   1659         0x130b04c,
   1660         0,
   1661         0,
   1662         1,
   1663         soc_U0_LED_SW_CNFG_LINK_159_128_BCM88690_A0r_fields,
   1664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1665         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1666         -1,
   1667         -1,
   1668     },
   1669 #endif /* chips */
   1670 
   1671 #if defined(BCM_88690_B0)
   1672     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_159_128_BCM88690_B0r */
   1673         soc_block_list[61],
   1674         soc_iprocreg,
   1675         1,
   1676         0,
   1677         0x130b04c,
   1678         0,
   1679         0,
   1680         1,
   1681         soc_U0_LED_SW_CNFG_LINK_159_128_BCM88690_B0r_fields,
   1682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1683         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1684         -1,
   1685         -1,
   1686     },
   1687 #endif /* chips */
   1688 
   1689 #if defined(BCM_88790_A0)
   1690     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_191_160r */
   1691         soc_block_list[61],
   1692         soc_iprocreg,
   1693         1,
   1694         0,
   1695         0x130b050,
   1696         0,
   1697         0,
   1698         1,
   1699         soc_U0_LED_SW_CNFG_LINK_191_160r_fields,
   1700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1701         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1702         -1,
   1703         -1,
   1704     },
   1705 #endif /* chips */
   1706 
   1707 #if defined(BCM_56370_A0)
   1708     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_191_160_BCM56370_A0r */
   1709         soc_block_list[61],
   1710         soc_iprocreg,
   1711         1,
   1712         0,
   1713         0x1000b050,
   1714         0,
   1715         0,
   1716         1,
   1717         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1719         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1720         -1,
   1721         -1,
   1722         3,
   1723     },
   1724 #endif /* chips */
   1725 
   1726 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1727     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1728     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_191_160_BCM56870_A0r */
   1729         soc_block_list[61],
   1730         soc_iprocreg,
   1731         1,
   1732         0,
   1733         0x130b050,
   1734         0,
   1735         0,
   1736         1,
   1737         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1739         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1740         -1,
   1741         -1,
   1742         3,
   1743     },
   1744 #endif /* chips */
   1745 
   1746 #if defined(BCM_88690_A0)
   1747     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_191_160_BCM88690_A0r */
   1748         soc_block_list[61],
   1749         soc_iprocreg,
   1750         1,
   1751         0,
   1752         0x130b050,
   1753         0,
   1754         0,
   1755         1,
   1756         soc_U0_LED_SW_CNFG_LINK_191_160_BCM88690_A0r_fields,
   1757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1758         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1759         -1,
   1760         -1,
   1761     },
   1762 #endif /* chips */
   1763 
   1764 #if defined(BCM_88690_B0)
   1765     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_191_160_BCM88690_B0r */
   1766         soc_block_list[61],
   1767         soc_iprocreg,
   1768         1,
   1769         0,
   1770         0x130b050,
   1771         0,
   1772         0,
   1773         1,
   1774         soc_U0_LED_SW_CNFG_LINK_191_160_BCM88690_B0r_fields,
   1775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1776         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1777         -1,
   1778         -1,
   1779     },
   1780 #endif /* chips */
   1781 
   1782 #if defined(BCM_88790_A0)
   1783     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_223_192r */
   1784         soc_block_list[61],
   1785         soc_iprocreg,
   1786         1,
   1787         0,
   1788         0x130b054,
   1789         0,
   1790         0,
   1791         1,
   1792         soc_U0_LED_SW_CNFG_LINK_223_192r_fields,
   1793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1794         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1795         -1,
   1796         -1,
   1797     },
   1798 #endif /* chips */
   1799 
   1800 #if defined(BCM_56370_A0)
   1801     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_223_192_BCM56370_A0r */
   1802         soc_block_list[61],
   1803         soc_iprocreg,
   1804         1,
   1805         0,
   1806         0x1000b054,
   1807         0,
   1808         0,
   1809         1,
   1810         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1812         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1813         -1,
   1814         -1,
   1815         3,
   1816     },
   1817 #endif /* chips */
   1818 
   1819 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1820     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1821     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_223_192_BCM56870_A0r */
   1822         soc_block_list[61],
   1823         soc_iprocreg,
   1824         1,
   1825         0,
   1826         0x130b054,
   1827         0,
   1828         0,
   1829         1,
   1830         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1832         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1833         -1,
   1834         -1,
   1835         3,
   1836     },
   1837 #endif /* chips */
   1838 
   1839 #if defined(BCM_88690_A0)
   1840     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_223_192_BCM88690_A0r */
   1841         soc_block_list[61],
   1842         soc_iprocreg,
   1843         1,
   1844         0,
   1845         0x130b054,
   1846         0,
   1847         0,
   1848         1,
   1849         soc_U0_LED_SW_CNFG_LINK_223_192_BCM88690_A0r_fields,
   1850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1851         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1852         -1,
   1853         -1,
   1854     },
   1855 #endif /* chips */
   1856 
   1857 #if defined(BCM_88690_B0)
   1858     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_223_192_BCM88690_B0r */
   1859         soc_block_list[61],
   1860         soc_iprocreg,
   1861         1,
   1862         0,
   1863         0x130b054,
   1864         0,
   1865         0,
   1866         1,
   1867         soc_U0_LED_SW_CNFG_LINK_223_192_BCM88690_B0r_fields,
   1868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1869         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1870         -1,
   1871         -1,
   1872     },
   1873 #endif /* chips */
   1874 
   1875 #if defined(BCM_88790_A0)
   1876     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_255_224r */
   1877         soc_block_list[61],
   1878         soc_iprocreg,
   1879         1,
   1880         0,
   1881         0x130b058,
   1882         0,
   1883         0,
   1884         1,
   1885         soc_U0_LED_SW_CNFG_LINK_255_224r_fields,
   1886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1887         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1888         -1,
   1889         -1,
   1890     },
   1891 #endif /* chips */
   1892 
   1893 #if defined(BCM_56370_A0)
   1894     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_255_224_BCM56370_A0r */
   1895         soc_block_list[61],
   1896         soc_iprocreg,
   1897         1,
   1898         0,
   1899         0x1000b058,
   1900         0,
   1901         0,
   1902         1,
   1903         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1905         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1906         -1,
   1907         -1,
   1908         3,
   1909     },
   1910 #endif /* chips */
   1911 
   1912 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   1913     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   1914     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_255_224_BCM56870_A0r */
   1915         soc_block_list[61],
   1916         soc_iprocreg,
   1917         1,
   1918         0,
   1919         0x130b058,
   1920         0,
   1921         0,
   1922         1,
   1923         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1925         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1926         -1,
   1927         -1,
   1928         3,
   1929     },
   1930 #endif /* chips */
   1931 
   1932 #if defined(BCM_88690_A0)
   1933     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_255_224_BCM88690_A0r */
   1934         soc_block_list[61],
   1935         soc_iprocreg,
   1936         1,
   1937         0,
   1938         0x130b058,
   1939         0,
   1940         0,
   1941         1,
   1942         soc_U0_LED_SW_CNFG_LINK_255_224_BCM88690_A0r_fields,
   1943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1944         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1945         -1,
   1946         -1,
   1947     },
   1948 #endif /* chips */
   1949 
   1950 #if defined(BCM_88690_B0)
   1951     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_255_224_BCM88690_B0r */
   1952         soc_block_list[61],
   1953         soc_iprocreg,
   1954         1,
   1955         0,
   1956         0x130b058,
   1957         0,
   1958         0,
   1959         1,
   1960         soc_U0_LED_SW_CNFG_LINK_255_224_BCM88690_B0r_fields,
   1961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1962         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1963         -1,
   1964         -1,
   1965     },
   1966 #endif /* chips */
   1967 
   1968 #if defined(BCM_88790_A0)
   1969     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_287_256r */
   1970         soc_block_list[61],
   1971         soc_iprocreg,
   1972         1,
   1973         0,
   1974         0x130b05c,
   1975         0,
   1976         0,
   1977         1,
   1978         soc_U0_LED_SW_CNFG_LINK_287_256r_fields,
   1979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1980         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1981         -1,
   1982         -1,
   1983     },
   1984 #endif /* chips */
   1985 
   1986 #if defined(BCM_56370_A0)
   1987     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_287_256_BCM56370_A0r */
   1988         soc_block_list[61],
   1989         soc_iprocreg,
   1990         1,
   1991         0,
   1992         0x1000b05c,
   1993         0,
   1994         0,
   1995         1,
   1996         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   1997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1998         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1999         -1,
   2000         -1,
   2001         3,
   2002     },
   2003 #endif /* chips */
   2004 
   2005 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   2006     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2007     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_287_256_BCM56870_A0r */
   2008         soc_block_list[61],
   2009         soc_iprocreg,
   2010         1,
   2011         0,
   2012         0x130b05c,
   2013         0,
   2014         0,
   2015         1,
   2016         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2018         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2019         -1,
   2020         -1,
   2021         3,
   2022     },
   2023 #endif /* chips */
   2024 
   2025 #if defined(BCM_88690_A0)
   2026     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_287_256_BCM88690_A0r */
   2027         soc_block_list[61],
   2028         soc_iprocreg,
   2029         1,
   2030         0,
   2031         0x130b05c,
   2032         0,
   2033         0,
   2034         1,
   2035         soc_U0_LED_SW_CNFG_LINK_287_256_BCM88690_A0r_fields,
   2036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2037         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2038         -1,
   2039         -1,
   2040     },
   2041 #endif /* chips */
   2042 
   2043 #if defined(BCM_88690_B0)
   2044     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_287_256_BCM88690_B0r */
   2045         soc_block_list[61],
   2046         soc_iprocreg,
   2047         1,
   2048         0,
   2049         0x130b05c,
   2050         0,
   2051         0,
   2052         1,
   2053         soc_U0_LED_SW_CNFG_LINK_287_256_BCM88690_B0r_fields,
   2054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2055         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2056         -1,
   2057         -1,
   2058     },
   2059 #endif /* chips */
   2060 
   2061 #if defined(BCM_88790_A0)
   2062     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_319_288r */
   2063         soc_block_list[61],
   2064         soc_iprocreg,
   2065         1,
   2066         0,
   2067         0x130b060,
   2068         0,
   2069         0,
   2070         1,
   2071         soc_U0_LED_SW_CNFG_LINK_319_288r_fields,
   2072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2073         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2074         -1,
   2075         -1,
   2076     },
   2077 #endif /* chips */
   2078 
   2079 #if defined(BCM_56370_A0)
   2080     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_319_288_BCM56370_A0r */
   2081         soc_block_list[61],
   2082         soc_iprocreg,
   2083         1,
   2084         0,
   2085         0x1000b060,
   2086         0,
   2087         0,
   2088         1,
   2089         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2091         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2092         -1,
   2093         -1,
   2094         3,
   2095     },
   2096 #endif /* chips */
   2097 
   2098 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   2099     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2100     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_319_288_BCM56870_A0r */
   2101         soc_block_list[61],
   2102         soc_iprocreg,
   2103         1,
   2104         0,
   2105         0x130b060,
   2106         0,
   2107         0,
   2108         1,
   2109         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2111         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2112         -1,
   2113         -1,
   2114         3,
   2115     },
   2116 #endif /* chips */
   2117 
   2118 #if defined(BCM_88690_A0)
   2119     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_319_288_BCM88690_A0r */
   2120         soc_block_list[61],
   2121         soc_iprocreg,
   2122         1,
   2123         0,
   2124         0x130b060,
   2125         0,
   2126         0,
   2127         1,
   2128         soc_U0_LED_SW_CNFG_LINK_319_288_BCM88690_A0r_fields,
   2129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2130         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2131         -1,
   2132         -1,
   2133     },
   2134 #endif /* chips */
   2135 
   2136 #if defined(BCM_88690_B0)
   2137     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_319_288_BCM88690_B0r */
   2138         soc_block_list[61],
   2139         soc_iprocreg,
   2140         1,
   2141         0,
   2142         0x130b060,
   2143         0,
   2144         0,
   2145         1,
   2146         soc_U0_LED_SW_CNFG_LINK_319_288_BCM88690_B0r_fields,
   2147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2148         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2149         -1,
   2150         -1,
   2151     },
   2152 #endif /* chips */
   2153 
   2154 #if defined(BCM_88790_A0)
   2155     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_31_0r */
   2156         soc_block_list[61],
   2157         soc_iprocreg,
   2158         1,
   2159         0,
   2160         0x130b03c,
   2161         0,
   2162         0,
   2163         1,
   2164         soc_U0_LED_SW_CNFG_LINK_31_0r_fields,
   2165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2166         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2167         -1,
   2168         -1,
   2169     },
   2170 #endif /* chips */
   2171 
   2172 #if defined(BCM_56370_A0)
   2173     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_31_0_BCM56370_A0r */
   2174         soc_block_list[61],
   2175         soc_iprocreg,
   2176         1,
   2177         0,
   2178         0x1000b03c,
   2179         0,
   2180         0,
   2181         1,
   2182         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2184         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2185         -1,
   2186         -1,
   2187         3,
   2188     },
   2189 #endif /* chips */
   2190 
   2191 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   2192     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2193     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_31_0_BCM56870_A0r */
   2194         soc_block_list[61],
   2195         soc_iprocreg,
   2196         1,
   2197         0,
   2198         0x130b03c,
   2199         0,
   2200         0,
   2201         1,
   2202         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2204         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2205         -1,
   2206         -1,
   2207         3,
   2208     },
   2209 #endif /* chips */
   2210 
   2211 #if defined(BCM_88690_A0)
   2212     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_31_0_BCM88690_A0r */
   2213         soc_block_list[61],
   2214         soc_iprocreg,
   2215         1,
   2216         0,
   2217         0x130b03c,
   2218         0,
   2219         0,
   2220         1,
   2221         soc_U0_LED_SW_CNFG_LINK_31_0_BCM88690_A0r_fields,
   2222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2223         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2224         -1,
   2225         -1,
   2226     },
   2227 #endif /* chips */
   2228 
   2229 #if defined(BCM_88690_B0)
   2230     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_31_0_BCM88690_B0r */
   2231         soc_block_list[61],
   2232         soc_iprocreg,
   2233         1,
   2234         0,
   2235         0x130b03c,
   2236         0,
   2237         0,
   2238         1,
   2239         soc_U0_LED_SW_CNFG_LINK_31_0_BCM88690_B0r_fields,
   2240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2241         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2242         -1,
   2243         -1,
   2244     },
   2245 #endif /* chips */
   2246 
   2247 #if defined(BCM_88790_A0)
   2248     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_351_320r */
   2249         soc_block_list[61],
   2250         soc_iprocreg,
   2251         1,
   2252         0,
   2253         0x130b064,
   2254         0,
   2255         0,
   2256         1,
   2257         soc_U0_LED_SW_CNFG_LINK_351_320r_fields,
   2258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2259         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2260         -1,
   2261         -1,
   2262     },
   2263 #endif /* chips */
   2264 
   2265 #if defined(BCM_56370_A0)
   2266     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_351_320_BCM56370_A0r */
   2267         soc_block_list[61],
   2268         soc_iprocreg,
   2269         1,
   2270         0,
   2271         0x1000b064,
   2272         0,
   2273         0,
   2274         1,
   2275         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2277         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2278         -1,
   2279         -1,
   2280         3,
   2281     },
   2282 #endif /* chips */
   2283 
   2284 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   2285     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2286     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_351_320_BCM56870_A0r */
   2287         soc_block_list[61],
   2288         soc_iprocreg,
   2289         1,
   2290         0,
   2291         0x130b064,
   2292         0,
   2293         0,
   2294         1,
   2295         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2298         -1,
   2299         -1,
   2300         3,
   2301     },
   2302 #endif /* chips */
   2303 
   2304 #if defined(BCM_88690_A0)
   2305     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_351_320_BCM88690_A0r */
   2306         soc_block_list[61],
   2307         soc_iprocreg,
   2308         1,
   2309         0,
   2310         0x130b064,
   2311         0,
   2312         0,
   2313         1,
   2314         soc_U0_LED_SW_CNFG_LINK_351_320_BCM88690_A0r_fields,
   2315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2316         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2317         -1,
   2318         -1,
   2319     },
   2320 #endif /* chips */
   2321 
   2322 #if defined(BCM_88690_B0)
   2323     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_351_320_BCM88690_B0r */
   2324         soc_block_list[61],
   2325         soc_iprocreg,
   2326         1,
   2327         0,
   2328         0x130b064,
   2329         0,
   2330         0,
   2331         1,
   2332         soc_U0_LED_SW_CNFG_LINK_351_320_BCM88690_B0r_fields,
   2333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2334         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2335         -1,
   2336         -1,
   2337     },
   2338 #endif /* chips */
   2339 
   2340 #if defined(BCM_88790_A0)
   2341     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_383_352r */
   2342         soc_block_list[61],
   2343         soc_iprocreg,
   2344         1,
   2345         0,
   2346         0x130b068,
   2347         0,
   2348         0,
   2349         1,
   2350         soc_U0_LED_SW_CNFG_LINK_383_352r_fields,
   2351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2352         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2353         -1,
   2354         -1,
   2355     },
   2356 #endif /* chips */
   2357 
   2358 #if defined(BCM_56370_A0)
   2359     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_383_352_BCM56370_A0r */
   2360         soc_block_list[61],
   2361         soc_iprocreg,
   2362         1,
   2363         0,
   2364         0x1000b068,
   2365         0,
   2366         0,
   2367         1,
   2368         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2370         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2371         -1,
   2372         -1,
   2373         3,
   2374     },
   2375 #endif /* chips */
   2376 
   2377 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   2378     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2379     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_383_352_BCM56870_A0r */
   2380         soc_block_list[61],
   2381         soc_iprocreg,
   2382         1,
   2383         0,
   2384         0x130b068,
   2385         0,
   2386         0,
   2387         1,
   2388         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2390         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2391         -1,
   2392         -1,
   2393         3,
   2394     },
   2395 #endif /* chips */
   2396 
   2397 #if defined(BCM_88690_A0)
   2398     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_383_352_BCM88690_A0r */
   2399         soc_block_list[61],
   2400         soc_iprocreg,
   2401         1,
   2402         0,
   2403         0x130b068,
   2404         0,
   2405         0,
   2406         1,
   2407         soc_U0_LED_SW_CNFG_LINK_383_352_BCM88690_A0r_fields,
   2408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2409         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2410         -1,
   2411         -1,
   2412     },
   2413 #endif /* chips */
   2414 
   2415 #if defined(BCM_88690_B0)
   2416     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_383_352_BCM88690_B0r */
   2417         soc_block_list[61],
   2418         soc_iprocreg,
   2419         1,
   2420         0,
   2421         0x130b068,
   2422         0,
   2423         0,
   2424         1,
   2425         soc_U0_LED_SW_CNFG_LINK_383_352_BCM88690_B0r_fields,
   2426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2428         -1,
   2429         -1,
   2430     },
   2431 #endif /* chips */
   2432 
   2433 #if defined(BCM_88790_A0)
   2434     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_415_384r */
   2435         soc_block_list[61],
   2436         soc_iprocreg,
   2437         1,
   2438         0,
   2439         0x130b06c,
   2440         0,
   2441         0,
   2442         1,
   2443         soc_U0_LED_SW_CNFG_LINK_415_384r_fields,
   2444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2446         -1,
   2447         -1,
   2448     },
   2449 #endif /* chips */
   2450 
   2451 #if defined(BCM_56370_A0)
   2452     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_415_384_BCM56370_A0r */
   2453         soc_block_list[61],
   2454         soc_iprocreg,
   2455         1,
   2456         0,
   2457         0x1000b06c,
   2458         0,
   2459         0,
   2460         1,
   2461         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2463         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2464         -1,
   2465         -1,
   2466         3,
   2467     },
   2468 #endif /* chips */
   2469 
   2470 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   2471     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2472     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_415_384_BCM56870_A0r */
   2473         soc_block_list[61],
   2474         soc_iprocreg,
   2475         1,
   2476         0,
   2477         0x130b06c,
   2478         0,
   2479         0,
   2480         1,
   2481         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2483         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2484         -1,
   2485         -1,
   2486         3,
   2487     },
   2488 #endif /* chips */
   2489 
   2490 #if defined(BCM_88690_A0)
   2491     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_415_384_BCM88690_A0r */
   2492         soc_block_list[61],
   2493         soc_iprocreg,
   2494         1,
   2495         0,
   2496         0x130b06c,
   2497         0,
   2498         0,
   2499         1,
   2500         soc_U0_LED_SW_CNFG_LINK_415_384_BCM88690_A0r_fields,
   2501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2502         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2503         -1,
   2504         -1,
   2505     },
   2506 #endif /* chips */
   2507 
   2508 #if defined(BCM_88690_B0)
   2509     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_415_384_BCM88690_B0r */
   2510         soc_block_list[61],
   2511         soc_iprocreg,
   2512         1,
   2513         0,
   2514         0x130b06c,
   2515         0,
   2516         0,
   2517         1,
   2518         soc_U0_LED_SW_CNFG_LINK_415_384_BCM88690_B0r_fields,
   2519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2520         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2521         -1,
   2522         -1,
   2523     },
   2524 #endif /* chips */
   2525 
   2526 #if defined(BCM_88790_A0)
   2527     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_447_416r */
   2528         soc_block_list[61],
   2529         soc_iprocreg,
   2530         1,
   2531         0,
   2532         0x130b070,
   2533         0,
   2534         0,
   2535         1,
   2536         soc_U0_LED_SW_CNFG_LINK_447_416r_fields,
   2537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2538         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2539         -1,
   2540         -1,
   2541     },
   2542 #endif /* chips */
   2543 
   2544 #if defined(BCM_56370_A0)
   2545     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_447_416_BCM56370_A0r */
   2546         soc_block_list[61],
   2547         soc_iprocreg,
   2548         1,
   2549         0,
   2550         0x1000b070,
   2551         0,
   2552         0,
   2553         1,
   2554         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2556         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2557         -1,
   2558         -1,
   2559         3,
   2560     },
   2561 #endif /* chips */
   2562 
   2563 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   2564     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2565     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_447_416_BCM56870_A0r */
   2566         soc_block_list[61],
   2567         soc_iprocreg,
   2568         1,
   2569         0,
   2570         0x130b070,
   2571         0,
   2572         0,
   2573         1,
   2574         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2576         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2577         -1,
   2578         -1,
   2579         3,
   2580     },
   2581 #endif /* chips */
   2582 
   2583 #if defined(BCM_88690_A0)
   2584     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_447_416_BCM88690_A0r */
   2585         soc_block_list[61],
   2586         soc_iprocreg,
   2587         1,
   2588         0,
   2589         0x130b070,
   2590         0,
   2591         0,
   2592         1,
   2593         soc_U0_LED_SW_CNFG_LINK_447_416_BCM88690_A0r_fields,
   2594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2596         -1,
   2597         -1,
   2598     },
   2599 #endif /* chips */
   2600 
   2601 #if defined(BCM_88690_B0)
   2602     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_447_416_BCM88690_B0r */
   2603         soc_block_list[61],
   2604         soc_iprocreg,
   2605         1,
   2606         0,
   2607         0x130b070,
   2608         0,
   2609         0,
   2610         1,
   2611         soc_U0_LED_SW_CNFG_LINK_447_416_BCM88690_B0r_fields,
   2612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2613         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2614         -1,
   2615         -1,
   2616     },
   2617 #endif /* chips */
   2618 
   2619 #if defined(BCM_88790_A0)
   2620     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_479_448r */
   2621         soc_block_list[61],
   2622         soc_iprocreg,
   2623         1,
   2624         0,
   2625         0x130b074,
   2626         0,
   2627         0,
   2628         1,
   2629         soc_U0_LED_SW_CNFG_LINK_479_448r_fields,
   2630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2631         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2632         -1,
   2633         -1,
   2634     },
   2635 #endif /* chips */
   2636 
   2637 #if defined(BCM_56370_A0)
   2638     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_479_448_BCM56370_A0r */
   2639         soc_block_list[61],
   2640         soc_iprocreg,
   2641         1,
   2642         0,
   2643         0x1000b074,
   2644         0,
   2645         0,
   2646         1,
   2647         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2649         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2650         -1,
   2651         -1,
   2652         3,
   2653     },
   2654 #endif /* chips */
   2655 
   2656 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   2657     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2658     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_479_448_BCM56870_A0r */
   2659         soc_block_list[61],
   2660         soc_iprocreg,
   2661         1,
   2662         0,
   2663         0x130b074,
   2664         0,
   2665         0,
   2666         1,
   2667         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2670         -1,
   2671         -1,
   2672         3,
   2673     },
   2674 #endif /* chips */
   2675 
   2676 #if defined(BCM_88690_A0)
   2677     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_479_448_BCM88690_A0r */
   2678         soc_block_list[61],
   2679         soc_iprocreg,
   2680         1,
   2681         0,
   2682         0x130b074,
   2683         0,
   2684         0,
   2685         1,
   2686         soc_U0_LED_SW_CNFG_LINK_479_448_BCM88690_A0r_fields,
   2687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2689         -1,
   2690         -1,
   2691     },
   2692 #endif /* chips */
   2693 
   2694 #if defined(BCM_88690_B0)
   2695     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_479_448_BCM88690_B0r */
   2696         soc_block_list[61],
   2697         soc_iprocreg,
   2698         1,
   2699         0,
   2700         0x130b074,
   2701         0,
   2702         0,
   2703         1,
   2704         soc_U0_LED_SW_CNFG_LINK_479_448_BCM88690_B0r_fields,
   2705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2706         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2707         -1,
   2708         -1,
   2709     },
   2710 #endif /* chips */
   2711 
   2712 #if defined(BCM_88790_A0)
   2713     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_511_480r */
   2714         soc_block_list[61],
   2715         soc_iprocreg,
   2716         1,
   2717         0,
   2718         0x130b078,
   2719         0,
   2720         0,
   2721         1,
   2722         soc_U0_LED_SW_CNFG_LINK_511_480r_fields,
   2723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2724         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2725         -1,
   2726         -1,
   2727     },
   2728 #endif /* chips */
   2729 
   2730 #if defined(BCM_56370_A0)
   2731     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_511_480_BCM56370_A0r */
   2732         soc_block_list[61],
   2733         soc_iprocreg,
   2734         1,
   2735         0,
   2736         0x1000b078,
   2737         0,
   2738         0,
   2739         1,
   2740         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2742         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2743         -1,
   2744         -1,
   2745         3,
   2746     },
   2747 #endif /* chips */
   2748 
   2749 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   2750     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2751     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_511_480_BCM56870_A0r */
   2752         soc_block_list[61],
   2753         soc_iprocreg,
   2754         1,
   2755         0,
   2756         0x130b078,
   2757         0,
   2758         0,
   2759         1,
   2760         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2762         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2763         -1,
   2764         -1,
   2765         3,
   2766     },
   2767 #endif /* chips */
   2768 
   2769 #if defined(BCM_88690_A0)
   2770     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_511_480_BCM88690_A0r */
   2771         soc_block_list[61],
   2772         soc_iprocreg,
   2773         1,
   2774         0,
   2775         0x130b078,
   2776         0,
   2777         0,
   2778         1,
   2779         soc_U0_LED_SW_CNFG_LINK_511_480_BCM88690_A0r_fields,
   2780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2781         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2782         -1,
   2783         -1,
   2784     },
   2785 #endif /* chips */
   2786 
   2787 #if defined(BCM_88690_B0)
   2788     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_511_480_BCM88690_B0r */
   2789         soc_block_list[61],
   2790         soc_iprocreg,
   2791         1,
   2792         0,
   2793         0x130b078,
   2794         0,
   2795         0,
   2796         1,
   2797         soc_U0_LED_SW_CNFG_LINK_511_480_BCM88690_B0r_fields,
   2798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2799         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2800         -1,
   2801         -1,
   2802     },
   2803 #endif /* chips */
   2804 
   2805 #if defined(BCM_88790_A0)
   2806     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_543_512r */
   2807         soc_block_list[61],
   2808         soc_iprocreg,
   2809         1,
   2810         0,
   2811         0x130b07c,
   2812         0,
   2813         0,
   2814         1,
   2815         soc_U0_LED_SW_CNFG_LINK_543_512r_fields,
   2816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2817         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2818         -1,
   2819         -1,
   2820     },
   2821 #endif /* chips */
   2822 
   2823 #if defined(BCM_56370_A0)
   2824     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_543_512_BCM56370_A0r */
   2825         soc_block_list[61],
   2826         soc_iprocreg,
   2827         1,
   2828         0,
   2829         0x1000b07c,
   2830         0,
   2831         0,
   2832         1,
   2833         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2835         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2836         -1,
   2837         -1,
   2838         3,
   2839     },
   2840 #endif /* chips */
   2841 
   2842 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   2843     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2844     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_543_512_BCM56870_A0r */
   2845         soc_block_list[61],
   2846         soc_iprocreg,
   2847         1,
   2848         0,
   2849         0x130b07c,
   2850         0,
   2851         0,
   2852         1,
   2853         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2855         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2856         -1,
   2857         -1,
   2858         3,
   2859     },
   2860 #endif /* chips */
   2861 
   2862 #if defined(BCM_88690_A0)
   2863     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_543_512_BCM88690_A0r */
   2864         soc_block_list[61],
   2865         soc_iprocreg,
   2866         1,
   2867         0,
   2868         0x130b07c,
   2869         0,
   2870         0,
   2871         1,
   2872         soc_U0_LED_SW_CNFG_LINK_543_512_BCM88690_A0r_fields,
   2873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2874         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2875         -1,
   2876         -1,
   2877     },
   2878 #endif /* chips */
   2879 
   2880 #if defined(BCM_88690_B0)
   2881     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_543_512_BCM88690_B0r */
   2882         soc_block_list[61],
   2883         soc_iprocreg,
   2884         1,
   2885         0,
   2886         0x130b07c,
   2887         0,
   2888         0,
   2889         1,
   2890         soc_U0_LED_SW_CNFG_LINK_543_512_BCM88690_B0r_fields,
   2891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2893         -1,
   2894         -1,
   2895     },
   2896 #endif /* chips */
   2897 
   2898 #if defined(BCM_88790_A0)
   2899     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_575_544r */
   2900         soc_block_list[61],
   2901         soc_iprocreg,
   2902         1,
   2903         0,
   2904         0x130b080,
   2905         0,
   2906         0,
   2907         1,
   2908         soc_U0_LED_SW_CNFG_LINK_575_544r_fields,
   2909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2910         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2911         -1,
   2912         -1,
   2913     },
   2914 #endif /* chips */
   2915 
   2916 #if defined(BCM_56370_A0)
   2917     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_575_544_BCM56370_A0r */
   2918         soc_block_list[61],
   2919         soc_iprocreg,
   2920         1,
   2921         0,
   2922         0x1000b080,
   2923         0,
   2924         0,
   2925         1,
   2926         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2928         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2929         -1,
   2930         -1,
   2931         3,
   2932     },
   2933 #endif /* chips */
   2934 
   2935 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   2936     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2937     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_575_544_BCM56870_A0r */
   2938         soc_block_list[61],
   2939         soc_iprocreg,
   2940         1,
   2941         0,
   2942         0x130b080,
   2943         0,
   2944         0,
   2945         1,
   2946         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   2947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2948         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2949         -1,
   2950         -1,
   2951         3,
   2952     },
   2953 #endif /* chips */
   2954 
   2955 #if defined(BCM_88690_A0)
   2956     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_575_544_BCM88690_A0r */
   2957         soc_block_list[61],
   2958         soc_iprocreg,
   2959         1,
   2960         0,
   2961         0x130b080,
   2962         0,
   2963         0,
   2964         1,
   2965         soc_U0_LED_SW_CNFG_LINK_575_544_BCM88690_A0r_fields,
   2966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2967         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2968         -1,
   2969         -1,
   2970     },
   2971 #endif /* chips */
   2972 
   2973 #if defined(BCM_88690_B0)
   2974     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_575_544_BCM88690_B0r */
   2975         soc_block_list[61],
   2976         soc_iprocreg,
   2977         1,
   2978         0,
   2979         0x130b080,
   2980         0,
   2981         0,
   2982         1,
   2983         soc_U0_LED_SW_CNFG_LINK_575_544_BCM88690_B0r_fields,
   2984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2985         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2986         -1,
   2987         -1,
   2988     },
   2989 #endif /* chips */
   2990 
   2991 #if defined(BCM_88790_A0)
   2992     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_607_576r */
   2993         soc_block_list[61],
   2994         soc_iprocreg,
   2995         1,
   2996         0,
   2997         0x130b084,
   2998         0,
   2999         0,
   3000         1,
   3001         soc_U0_LED_SW_CNFG_LINK_607_576r_fields,
   3002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3003         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3004         -1,
   3005         -1,
   3006     },
   3007 #endif /* chips */
   3008 
   3009 #if defined(BCM_56370_A0)
   3010     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_607_576_BCM56370_A0r */
   3011         soc_block_list[61],
   3012         soc_iprocreg,
   3013         1,
   3014         0,
   3015         0x1000b084,
   3016         0,
   3017         0,
   3018         1,
   3019         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3021         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3022         -1,
   3023         -1,
   3024         3,
   3025     },
   3026 #endif /* chips */
   3027 
   3028 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3029     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3030     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_607_576_BCM56870_A0r */
   3031         soc_block_list[61],
   3032         soc_iprocreg,
   3033         1,
   3034         0,
   3035         0x130b084,
   3036         0,
   3037         0,
   3038         1,
   3039         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3041         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3042         -1,
   3043         -1,
   3044         3,
   3045     },
   3046 #endif /* chips */
   3047 
   3048 #if defined(BCM_88690_A0)
   3049     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_607_576_BCM88690_A0r */
   3050         soc_block_list[61],
   3051         soc_iprocreg,
   3052         1,
   3053         0,
   3054         0x130b084,
   3055         0,
   3056         0,
   3057         1,
   3058         soc_U0_LED_SW_CNFG_LINK_607_576_BCM88690_A0r_fields,
   3059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3060         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3061         -1,
   3062         -1,
   3063     },
   3064 #endif /* chips */
   3065 
   3066 #if defined(BCM_88690_B0)
   3067     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_607_576_BCM88690_B0r */
   3068         soc_block_list[61],
   3069         soc_iprocreg,
   3070         1,
   3071         0,
   3072         0x130b084,
   3073         0,
   3074         0,
   3075         1,
   3076         soc_U0_LED_SW_CNFG_LINK_607_576_BCM88690_B0r_fields,
   3077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3078         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3079         -1,
   3080         -1,
   3081     },
   3082 #endif /* chips */
   3083 
   3084 #if defined(BCM_88790_A0)
   3085     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_639_608r */
   3086         soc_block_list[61],
   3087         soc_iprocreg,
   3088         1,
   3089         0,
   3090         0x130b088,
   3091         0,
   3092         0,
   3093         1,
   3094         soc_U0_LED_SW_CNFG_LINK_639_608r_fields,
   3095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3096         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3097         -1,
   3098         -1,
   3099     },
   3100 #endif /* chips */
   3101 
   3102 #if defined(BCM_56370_A0)
   3103     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_639_608_BCM56370_A0r */
   3104         soc_block_list[61],
   3105         soc_iprocreg,
   3106         1,
   3107         0,
   3108         0x1000b088,
   3109         0,
   3110         0,
   3111         1,
   3112         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3114         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3115         -1,
   3116         -1,
   3117         3,
   3118     },
   3119 #endif /* chips */
   3120 
   3121 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3122     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3123     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_639_608_BCM56870_A0r */
   3124         soc_block_list[61],
   3125         soc_iprocreg,
   3126         1,
   3127         0,
   3128         0x130b088,
   3129         0,
   3130         0,
   3131         1,
   3132         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3134         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3135         -1,
   3136         -1,
   3137         3,
   3138     },
   3139 #endif /* chips */
   3140 
   3141 #if defined(BCM_88690_A0)
   3142     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_639_608_BCM88690_A0r */
   3143         soc_block_list[61],
   3144         soc_iprocreg,
   3145         1,
   3146         0,
   3147         0x130b088,
   3148         0,
   3149         0,
   3150         1,
   3151         soc_U0_LED_SW_CNFG_LINK_639_608_BCM88690_A0r_fields,
   3152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3153         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3154         -1,
   3155         -1,
   3156     },
   3157 #endif /* chips */
   3158 
   3159 #if defined(BCM_88690_B0)
   3160     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_639_608_BCM88690_B0r */
   3161         soc_block_list[61],
   3162         soc_iprocreg,
   3163         1,
   3164         0,
   3165         0x130b088,
   3166         0,
   3167         0,
   3168         1,
   3169         soc_U0_LED_SW_CNFG_LINK_639_608_BCM88690_B0r_fields,
   3170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3171         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3172         -1,
   3173         -1,
   3174     },
   3175 #endif /* chips */
   3176 
   3177 #if defined(BCM_88790_A0)
   3178     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_63_32r */
   3179         soc_block_list[61],
   3180         soc_iprocreg,
   3181         1,
   3182         0,
   3183         0x130b040,
   3184         0,
   3185         0,
   3186         1,
   3187         soc_U0_LED_SW_CNFG_LINK_63_32r_fields,
   3188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3189         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3190         -1,
   3191         -1,
   3192     },
   3193 #endif /* chips */
   3194 
   3195 #if defined(BCM_56370_A0)
   3196     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_63_32_BCM56370_A0r */
   3197         soc_block_list[61],
   3198         soc_iprocreg,
   3199         1,
   3200         0,
   3201         0x1000b040,
   3202         0,
   3203         0,
   3204         1,
   3205         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3207         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3208         -1,
   3209         -1,
   3210         3,
   3211     },
   3212 #endif /* chips */
   3213 
   3214 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3215     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3216     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_63_32_BCM56870_A0r */
   3217         soc_block_list[61],
   3218         soc_iprocreg,
   3219         1,
   3220         0,
   3221         0x130b040,
   3222         0,
   3223         0,
   3224         1,
   3225         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3227         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3228         -1,
   3229         -1,
   3230         3,
   3231     },
   3232 #endif /* chips */
   3233 
   3234 #if defined(BCM_88690_A0)
   3235     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_63_32_BCM88690_A0r */
   3236         soc_block_list[61],
   3237         soc_iprocreg,
   3238         1,
   3239         0,
   3240         0x130b040,
   3241         0,
   3242         0,
   3243         1,
   3244         soc_U0_LED_SW_CNFG_LINK_63_32_BCM88690_A0r_fields,
   3245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3246         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3247         -1,
   3248         -1,
   3249     },
   3250 #endif /* chips */
   3251 
   3252 #if defined(BCM_88690_B0)
   3253     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_63_32_BCM88690_B0r */
   3254         soc_block_list[61],
   3255         soc_iprocreg,
   3256         1,
   3257         0,
   3258         0x130b040,
   3259         0,
   3260         0,
   3261         1,
   3262         soc_U0_LED_SW_CNFG_LINK_63_32_BCM88690_B0r_fields,
   3263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3264         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3265         -1,
   3266         -1,
   3267     },
   3268 #endif /* chips */
   3269 
   3270 #if defined(BCM_88790_A0)
   3271     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_671_640r */
   3272         soc_block_list[61],
   3273         soc_iprocreg,
   3274         1,
   3275         0,
   3276         0x130b08c,
   3277         0,
   3278         0,
   3279         1,
   3280         soc_U0_LED_SW_CNFG_LINK_671_640r_fields,
   3281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3282         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3283         -1,
   3284         -1,
   3285     },
   3286 #endif /* chips */
   3287 
   3288 #if defined(BCM_56370_A0)
   3289     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_671_640_BCM56370_A0r */
   3290         soc_block_list[61],
   3291         soc_iprocreg,
   3292         1,
   3293         0,
   3294         0x1000b08c,
   3295         0,
   3296         0,
   3297         1,
   3298         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3300         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3301         -1,
   3302         -1,
   3303         3,
   3304     },
   3305 #endif /* chips */
   3306 
   3307 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3308     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3309     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_671_640_BCM56870_A0r */
   3310         soc_block_list[61],
   3311         soc_iprocreg,
   3312         1,
   3313         0,
   3314         0x130b08c,
   3315         0,
   3316         0,
   3317         1,
   3318         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3320         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3321         -1,
   3322         -1,
   3323         3,
   3324     },
   3325 #endif /* chips */
   3326 
   3327 #if defined(BCM_88690_A0)
   3328     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_671_640_BCM88690_A0r */
   3329         soc_block_list[61],
   3330         soc_iprocreg,
   3331         1,
   3332         0,
   3333         0x130b08c,
   3334         0,
   3335         0,
   3336         1,
   3337         soc_U0_LED_SW_CNFG_LINK_671_640_BCM88690_A0r_fields,
   3338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3339         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3340         -1,
   3341         -1,
   3342     },
   3343 #endif /* chips */
   3344 
   3345 #if defined(BCM_88690_B0)
   3346     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_671_640_BCM88690_B0r */
   3347         soc_block_list[61],
   3348         soc_iprocreg,
   3349         1,
   3350         0,
   3351         0x130b08c,
   3352         0,
   3353         0,
   3354         1,
   3355         soc_U0_LED_SW_CNFG_LINK_671_640_BCM88690_B0r_fields,
   3356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3357         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3358         -1,
   3359         -1,
   3360     },
   3361 #endif /* chips */
   3362 
   3363 #if defined(BCM_88790_A0)
   3364     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_703_672r */
   3365         soc_block_list[61],
   3366         soc_iprocreg,
   3367         1,
   3368         0,
   3369         0x130b090,
   3370         0,
   3371         0,
   3372         1,
   3373         soc_U0_LED_SW_CNFG_LINK_703_672r_fields,
   3374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3375         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3376         -1,
   3377         -1,
   3378     },
   3379 #endif /* chips */
   3380 
   3381 #if defined(BCM_56370_A0)
   3382     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_703_672_BCM56370_A0r */
   3383         soc_block_list[61],
   3384         soc_iprocreg,
   3385         1,
   3386         0,
   3387         0x1000b090,
   3388         0,
   3389         0,
   3390         1,
   3391         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3393         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3394         -1,
   3395         -1,
   3396         3,
   3397     },
   3398 #endif /* chips */
   3399 
   3400 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3401     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3402     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_703_672_BCM56870_A0r */
   3403         soc_block_list[61],
   3404         soc_iprocreg,
   3405         1,
   3406         0,
   3407         0x130b090,
   3408         0,
   3409         0,
   3410         1,
   3411         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3413         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3414         -1,
   3415         -1,
   3416         3,
   3417     },
   3418 #endif /* chips */
   3419 
   3420 #if defined(BCM_88690_A0)
   3421     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_703_672_BCM88690_A0r */
   3422         soc_block_list[61],
   3423         soc_iprocreg,
   3424         1,
   3425         0,
   3426         0x130b090,
   3427         0,
   3428         0,
   3429         1,
   3430         soc_U0_LED_SW_CNFG_LINK_703_672_BCM88690_A0r_fields,
   3431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3433         -1,
   3434         -1,
   3435     },
   3436 #endif /* chips */
   3437 
   3438 #if defined(BCM_88690_B0)
   3439     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_703_672_BCM88690_B0r */
   3440         soc_block_list[61],
   3441         soc_iprocreg,
   3442         1,
   3443         0,
   3444         0x130b090,
   3445         0,
   3446         0,
   3447         1,
   3448         soc_U0_LED_SW_CNFG_LINK_703_672_BCM88690_B0r_fields,
   3449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3451         -1,
   3452         -1,
   3453     },
   3454 #endif /* chips */
   3455 
   3456 #if defined(BCM_88790_A0)
   3457     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_735_704r */
   3458         soc_block_list[61],
   3459         soc_iprocreg,
   3460         1,
   3461         0,
   3462         0x130b094,
   3463         0,
   3464         0,
   3465         1,
   3466         soc_U0_LED_SW_CNFG_LINK_735_704r_fields,
   3467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3469         -1,
   3470         -1,
   3471     },
   3472 #endif /* chips */
   3473 
   3474 #if defined(BCM_56370_A0)
   3475     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_735_704_BCM56370_A0r */
   3476         soc_block_list[61],
   3477         soc_iprocreg,
   3478         1,
   3479         0,
   3480         0x1000b094,
   3481         0,
   3482         0,
   3483         1,
   3484         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3486         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3487         -1,
   3488         -1,
   3489         3,
   3490     },
   3491 #endif /* chips */
   3492 
   3493 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3494     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3495     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_735_704_BCM56870_A0r */
   3496         soc_block_list[61],
   3497         soc_iprocreg,
   3498         1,
   3499         0,
   3500         0x130b094,
   3501         0,
   3502         0,
   3503         1,
   3504         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3506         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3507         -1,
   3508         -1,
   3509         3,
   3510     },
   3511 #endif /* chips */
   3512 
   3513 #if defined(BCM_88690_A0)
   3514     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_735_704_BCM88690_A0r */
   3515         soc_block_list[61],
   3516         soc_iprocreg,
   3517         1,
   3518         0,
   3519         0x130b094,
   3520         0,
   3521         0,
   3522         1,
   3523         soc_U0_LED_SW_CNFG_LINK_735_704_BCM88690_A0r_fields,
   3524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3526         -1,
   3527         -1,
   3528     },
   3529 #endif /* chips */
   3530 
   3531 #if defined(BCM_88690_B0)
   3532     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_735_704_BCM88690_B0r */
   3533         soc_block_list[61],
   3534         soc_iprocreg,
   3535         1,
   3536         0,
   3537         0x130b094,
   3538         0,
   3539         0,
   3540         1,
   3541         soc_U0_LED_SW_CNFG_LINK_735_704_BCM88690_B0r_fields,
   3542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3544         -1,
   3545         -1,
   3546     },
   3547 #endif /* chips */
   3548 
   3549 #if defined(BCM_88790_A0)
   3550     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_767_736r */
   3551         soc_block_list[61],
   3552         soc_iprocreg,
   3553         1,
   3554         0,
   3555         0x130b098,
   3556         0,
   3557         0,
   3558         1,
   3559         soc_U0_LED_SW_CNFG_LINK_767_736r_fields,
   3560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3561         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3562         -1,
   3563         -1,
   3564     },
   3565 #endif /* chips */
   3566 
   3567 #if defined(BCM_56370_A0)
   3568     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_767_736_BCM56370_A0r */
   3569         soc_block_list[61],
   3570         soc_iprocreg,
   3571         1,
   3572         0,
   3573         0x1000b098,
   3574         0,
   3575         0,
   3576         1,
   3577         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3579         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3580         -1,
   3581         -1,
   3582         3,
   3583     },
   3584 #endif /* chips */
   3585 
   3586 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3587     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3588     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_767_736_BCM56870_A0r */
   3589         soc_block_list[61],
   3590         soc_iprocreg,
   3591         1,
   3592         0,
   3593         0x130b098,
   3594         0,
   3595         0,
   3596         1,
   3597         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3599         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3600         -1,
   3601         -1,
   3602         3,
   3603     },
   3604 #endif /* chips */
   3605 
   3606 #if defined(BCM_88690_A0)
   3607     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_767_736_BCM88690_A0r */
   3608         soc_block_list[61],
   3609         soc_iprocreg,
   3610         1,
   3611         0,
   3612         0x130b098,
   3613         0,
   3614         0,
   3615         1,
   3616         soc_U0_LED_SW_CNFG_LINK_767_736_BCM88690_A0r_fields,
   3617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3618         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3619         -1,
   3620         -1,
   3621     },
   3622 #endif /* chips */
   3623 
   3624 #if defined(BCM_88690_B0)
   3625     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_767_736_BCM88690_B0r */
   3626         soc_block_list[61],
   3627         soc_iprocreg,
   3628         1,
   3629         0,
   3630         0x130b098,
   3631         0,
   3632         0,
   3633         1,
   3634         soc_U0_LED_SW_CNFG_LINK_767_736_BCM88690_B0r_fields,
   3635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3636         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3637         -1,
   3638         -1,
   3639     },
   3640 #endif /* chips */
   3641 
   3642 #if defined(BCM_88790_A0)
   3643     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_799_768r */
   3644         soc_block_list[61],
   3645         soc_iprocreg,
   3646         1,
   3647         0,
   3648         0x130b09c,
   3649         0,
   3650         0,
   3651         1,
   3652         soc_U0_LED_SW_CNFG_LINK_799_768r_fields,
   3653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3654         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3655         -1,
   3656         -1,
   3657     },
   3658 #endif /* chips */
   3659 
   3660 #if defined(BCM_56370_A0)
   3661     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_799_768_BCM56370_A0r */
   3662         soc_block_list[61],
   3663         soc_iprocreg,
   3664         1,
   3665         0,
   3666         0x1000b09c,
   3667         0,
   3668         0,
   3669         1,
   3670         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3672         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3673         -1,
   3674         -1,
   3675         3,
   3676     },
   3677 #endif /* chips */
   3678 
   3679 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3680     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3681     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_799_768_BCM56870_A0r */
   3682         soc_block_list[61],
   3683         soc_iprocreg,
   3684         1,
   3685         0,
   3686         0x130b09c,
   3687         0,
   3688         0,
   3689         1,
   3690         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3692         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3693         -1,
   3694         -1,
   3695         3,
   3696     },
   3697 #endif /* chips */
   3698 
   3699 #if defined(BCM_88690_A0)
   3700     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_799_768_BCM88690_A0r */
   3701         soc_block_list[61],
   3702         soc_iprocreg,
   3703         1,
   3704         0,
   3705         0x130b09c,
   3706         0,
   3707         0,
   3708         1,
   3709         soc_U0_LED_SW_CNFG_LINK_799_768_BCM88690_A0r_fields,
   3710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3711         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3712         -1,
   3713         -1,
   3714     },
   3715 #endif /* chips */
   3716 
   3717 #if defined(BCM_88690_B0)
   3718     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_799_768_BCM88690_B0r */
   3719         soc_block_list[61],
   3720         soc_iprocreg,
   3721         1,
   3722         0,
   3723         0x130b09c,
   3724         0,
   3725         0,
   3726         1,
   3727         soc_U0_LED_SW_CNFG_LINK_799_768_BCM88690_B0r_fields,
   3728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3729         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3730         -1,
   3731         -1,
   3732     },
   3733 #endif /* chips */
   3734 
   3735 #if defined(BCM_88790_A0)
   3736     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_831_800r */
   3737         soc_block_list[61],
   3738         soc_iprocreg,
   3739         1,
   3740         0,
   3741         0x130b0a0,
   3742         0,
   3743         0,
   3744         1,
   3745         soc_U0_LED_SW_CNFG_LINK_831_800r_fields,
   3746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3747         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3748         -1,
   3749         -1,
   3750     },
   3751 #endif /* chips */
   3752 
   3753 #if defined(BCM_56370_A0)
   3754     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_831_800_BCM56370_A0r */
   3755         soc_block_list[61],
   3756         soc_iprocreg,
   3757         1,
   3758         0,
   3759         0x1000b0a0,
   3760         0,
   3761         0,
   3762         1,
   3763         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3765         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3766         -1,
   3767         -1,
   3768         3,
   3769     },
   3770 #endif /* chips */
   3771 
   3772 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3773     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3774     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_831_800_BCM56870_A0r */
   3775         soc_block_list[61],
   3776         soc_iprocreg,
   3777         1,
   3778         0,
   3779         0x130b0a0,
   3780         0,
   3781         0,
   3782         1,
   3783         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3785         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3786         -1,
   3787         -1,
   3788         3,
   3789     },
   3790 #endif /* chips */
   3791 
   3792 #if defined(BCM_88690_A0)
   3793     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_831_800_BCM88690_A0r */
   3794         soc_block_list[61],
   3795         soc_iprocreg,
   3796         1,
   3797         0,
   3798         0x130b0a0,
   3799         0,
   3800         0,
   3801         1,
   3802         soc_U0_LED_SW_CNFG_LINK_831_800_BCM88690_A0r_fields,
   3803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3804         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3805         -1,
   3806         -1,
   3807     },
   3808 #endif /* chips */
   3809 
   3810 #if defined(BCM_88690_B0)
   3811     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_831_800_BCM88690_B0r */
   3812         soc_block_list[61],
   3813         soc_iprocreg,
   3814         1,
   3815         0,
   3816         0x130b0a0,
   3817         0,
   3818         0,
   3819         1,
   3820         soc_U0_LED_SW_CNFG_LINK_831_800_BCM88690_B0r_fields,
   3821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3822         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3823         -1,
   3824         -1,
   3825     },
   3826 #endif /* chips */
   3827 
   3828 #if defined(BCM_88790_A0)
   3829     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_863_832r */
   3830         soc_block_list[61],
   3831         soc_iprocreg,
   3832         1,
   3833         0,
   3834         0x130b0a4,
   3835         0,
   3836         0,
   3837         1,
   3838         soc_U0_LED_SW_CNFG_LINK_863_832r_fields,
   3839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3840         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3841         -1,
   3842         -1,
   3843     },
   3844 #endif /* chips */
   3845 
   3846 #if defined(BCM_56370_A0)
   3847     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_863_832_BCM56370_A0r */
   3848         soc_block_list[61],
   3849         soc_iprocreg,
   3850         1,
   3851         0,
   3852         0x1000b0a4,
   3853         0,
   3854         0,
   3855         1,
   3856         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3858         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3859         -1,
   3860         -1,
   3861         3,
   3862     },
   3863 #endif /* chips */
   3864 
   3865 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3866     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3867     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_863_832_BCM56870_A0r */
   3868         soc_block_list[61],
   3869         soc_iprocreg,
   3870         1,
   3871         0,
   3872         0x130b0a4,
   3873         0,
   3874         0,
   3875         1,
   3876         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3878         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3879         -1,
   3880         -1,
   3881         3,
   3882     },
   3883 #endif /* chips */
   3884 
   3885 #if defined(BCM_88690_A0)
   3886     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_863_832_BCM88690_A0r */
   3887         soc_block_list[61],
   3888         soc_iprocreg,
   3889         1,
   3890         0,
   3891         0x130b0a4,
   3892         0,
   3893         0,
   3894         1,
   3895         soc_U0_LED_SW_CNFG_LINK_863_832_BCM88690_A0r_fields,
   3896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3898         -1,
   3899         -1,
   3900     },
   3901 #endif /* chips */
   3902 
   3903 #if defined(BCM_88690_B0)
   3904     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_863_832_BCM88690_B0r */
   3905         soc_block_list[61],
   3906         soc_iprocreg,
   3907         1,
   3908         0,
   3909         0x130b0a4,
   3910         0,
   3911         0,
   3912         1,
   3913         soc_U0_LED_SW_CNFG_LINK_863_832_BCM88690_B0r_fields,
   3914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3916         -1,
   3917         -1,
   3918     },
   3919 #endif /* chips */
   3920 
   3921 #if defined(BCM_88790_A0)
   3922     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_895_864r */
   3923         soc_block_list[61],
   3924         soc_iprocreg,
   3925         1,
   3926         0,
   3927         0x130b0a8,
   3928         0,
   3929         0,
   3930         1,
   3931         soc_U0_LED_SW_CNFG_LINK_895_864r_fields,
   3932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3933         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3934         -1,
   3935         -1,
   3936     },
   3937 #endif /* chips */
   3938 
   3939 #if defined(BCM_56370_A0)
   3940     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_895_864_BCM56370_A0r */
   3941         soc_block_list[61],
   3942         soc_iprocreg,
   3943         1,
   3944         0,
   3945         0x1000b0a8,
   3946         0,
   3947         0,
   3948         1,
   3949         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3952         -1,
   3953         -1,
   3954         3,
   3955     },
   3956 #endif /* chips */
   3957 
   3958 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3959     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3960     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_895_864_BCM56870_A0r */
   3961         soc_block_list[61],
   3962         soc_iprocreg,
   3963         1,
   3964         0,
   3965         0x130b0a8,
   3966         0,
   3967         0,
   3968         1,
   3969         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   3970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3971         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3972         -1,
   3973         -1,
   3974         3,
   3975     },
   3976 #endif /* chips */
   3977 
   3978 #if defined(BCM_88690_A0)
   3979     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_895_864_BCM88690_A0r */
   3980         soc_block_list[61],
   3981         soc_iprocreg,
   3982         1,
   3983         0,
   3984         0x130b0a8,
   3985         0,
   3986         0,
   3987         1,
   3988         soc_U0_LED_SW_CNFG_LINK_895_864_BCM88690_A0r_fields,
   3989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3990         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3991         -1,
   3992         -1,
   3993     },
   3994 #endif /* chips */
   3995 
   3996 #if defined(BCM_88690_B0)
   3997     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_895_864_BCM88690_B0r */
   3998         soc_block_list[61],
   3999         soc_iprocreg,
   4000         1,
   4001         0,
   4002         0x130b0a8,
   4003         0,
   4004         0,
   4005         1,
   4006         soc_U0_LED_SW_CNFG_LINK_895_864_BCM88690_B0r_fields,
   4007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4008         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4009         -1,
   4010         -1,
   4011     },
   4012 #endif /* chips */
   4013 
   4014 #if defined(BCM_88790_A0)
   4015     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_927_896r */
   4016         soc_block_list[61],
   4017         soc_iprocreg,
   4018         1,
   4019         0,
   4020         0x130b0ac,
   4021         0,
   4022         0,
   4023         1,
   4024         soc_U0_LED_SW_CNFG_LINK_927_896r_fields,
   4025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4026         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4027         -1,
   4028         -1,
   4029     },
   4030 #endif /* chips */
   4031 
   4032 #if defined(BCM_56370_A0)
   4033     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_927_896_BCM56370_A0r */
   4034         soc_block_list[61],
   4035         soc_iprocreg,
   4036         1,
   4037         0,
   4038         0x1000b0ac,
   4039         0,
   4040         0,
   4041         1,
   4042         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   4043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4044         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4045         -1,
   4046         -1,
   4047         3,
   4048     },
   4049 #endif /* chips */
   4050 
   4051 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   4052     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4053     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_927_896_BCM56870_A0r */
   4054         soc_block_list[61],
   4055         soc_iprocreg,
   4056         1,
   4057         0,
   4058         0x130b0ac,
   4059         0,
   4060         0,
   4061         1,
   4062         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   4063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4064         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4065         -1,
   4066         -1,
   4067         3,
   4068     },
   4069 #endif /* chips */
   4070 
   4071 #if defined(BCM_88690_A0)
   4072     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_927_896_BCM88690_A0r */
   4073         soc_block_list[61],
   4074         soc_iprocreg,
   4075         1,
   4076         0,
   4077         0x130b0ac,
   4078         0,
   4079         0,
   4080         1,
   4081         soc_U0_LED_SW_CNFG_LINK_927_896_BCM88690_A0r_fields,
   4082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4083         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4084         -1,
   4085         -1,
   4086     },
   4087 #endif /* chips */
   4088 
   4089 #if defined(BCM_88690_B0)
   4090     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_927_896_BCM88690_B0r */
   4091         soc_block_list[61],
   4092         soc_iprocreg,
   4093         1,
   4094         0,
   4095         0x130b0ac,
   4096         0,
   4097         0,
   4098         1,
   4099         soc_U0_LED_SW_CNFG_LINK_927_896_BCM88690_B0r_fields,
   4100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4101         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4102         -1,
   4103         -1,
   4104     },
   4105 #endif /* chips */
   4106 
   4107 #if defined(BCM_88790_A0)
   4108     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_959_928r */
   4109         soc_block_list[61],
   4110         soc_iprocreg,
   4111         1,
   4112         0,
   4113         0x130b0b0,
   4114         0,
   4115         0,
   4116         1,
   4117         soc_U0_LED_SW_CNFG_LINK_959_928r_fields,
   4118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4119         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4120         -1,
   4121         -1,
   4122     },
   4123 #endif /* chips */
   4124 
   4125 #if defined(BCM_56370_A0)
   4126     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_959_928_BCM56370_A0r */
   4127         soc_block_list[61],
   4128         soc_iprocreg,
   4129         1,
   4130         0,
   4131         0x1000b0b0,
   4132         0,
   4133         0,
   4134         1,
   4135         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   4136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4138         -1,
   4139         -1,
   4140         3,
   4141     },
   4142 #endif /* chips */
   4143 
   4144 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   4145     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4146     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_959_928_BCM56870_A0r */
   4147         soc_block_list[61],
   4148         soc_iprocreg,
   4149         1,
   4150         0,
   4151         0x130b0b0,
   4152         0,
   4153         0,
   4154         1,
   4155         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   4156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4157         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4158         -1,
   4159         -1,
   4160         3,
   4161     },
   4162 #endif /* chips */
   4163 
   4164 #if defined(BCM_88690_A0)
   4165     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_959_928_BCM88690_A0r */
   4166         soc_block_list[61],
   4167         soc_iprocreg,
   4168         1,
   4169         0,
   4170         0x130b0b0,
   4171         0,
   4172         0,
   4173         1,
   4174         soc_U0_LED_SW_CNFG_LINK_959_928_BCM88690_A0r_fields,
   4175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4176         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4177         -1,
   4178         -1,
   4179     },
   4180 #endif /* chips */
   4181 
   4182 #if defined(BCM_88690_B0)
   4183     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_959_928_BCM88690_B0r */
   4184         soc_block_list[61],
   4185         soc_iprocreg,
   4186         1,
   4187         0,
   4188         0x130b0b0,
   4189         0,
   4190         0,
   4191         1,
   4192         soc_U0_LED_SW_CNFG_LINK_959_928_BCM88690_B0r_fields,
   4193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4194         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4195         -1,
   4196         -1,
   4197     },
   4198 #endif /* chips */
   4199 
   4200 #if defined(BCM_88790_A0)
   4201     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_95_64r */
   4202         soc_block_list[61],
   4203         soc_iprocreg,
   4204         1,
   4205         0,
   4206         0x130b044,
   4207         0,
   4208         0,
   4209         1,
   4210         soc_U0_LED_SW_CNFG_LINK_95_64r_fields,
   4211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4212         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4213         -1,
   4214         -1,
   4215     },
   4216 #endif /* chips */
   4217 
   4218 #if defined(BCM_56370_A0)
   4219     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_95_64_BCM56370_A0r */
   4220         soc_block_list[61],
   4221         soc_iprocreg,
   4222         1,
   4223         0,
   4224         0x1000b044,
   4225         0,
   4226         0,
   4227         1,
   4228         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   4229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4230         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4231         -1,
   4232         -1,
   4233         3,
   4234     },
   4235 #endif /* chips */
   4236 
   4237 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   4238     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4239     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_95_64_BCM56870_A0r */
   4240         soc_block_list[61],
   4241         soc_iprocreg,
   4242         1,
   4243         0,
   4244         0x130b044,
   4245         0,
   4246         0,
   4247         1,
   4248         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   4249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4250         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4251         -1,
   4252         -1,
   4253         3,
   4254     },
   4255 #endif /* chips */
   4256 
   4257 #if defined(BCM_88690_A0)
   4258     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_95_64_BCM88690_A0r */
   4259         soc_block_list[61],
   4260         soc_iprocreg,
   4261         1,
   4262         0,
   4263         0x130b044,
   4264         0,
   4265         0,
   4266         1,
   4267         soc_U0_LED_SW_CNFG_LINK_95_64_BCM88690_A0r_fields,
   4268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4269         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4270         -1,
   4271         -1,
   4272     },
   4273 #endif /* chips */
   4274 
   4275 #if defined(BCM_88690_B0)
   4276     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_95_64_BCM88690_B0r */
   4277         soc_block_list[61],
   4278         soc_iprocreg,
   4279         1,
   4280         0,
   4281         0x130b044,
   4282         0,
   4283         0,
   4284         1,
   4285         soc_U0_LED_SW_CNFG_LINK_95_64_BCM88690_B0r_fields,
   4286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4287         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4288         -1,
   4289         -1,
   4290     },
   4291 #endif /* chips */
   4292 
   4293 #if defined(BCM_88790_A0)
   4294     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_991_960r */
   4295         soc_block_list[61],
   4296         soc_iprocreg,
   4297         1,
   4298         0,
   4299         0x130b0b4,
   4300         0,
   4301         0,
   4302         1,
   4303         soc_U0_LED_SW_CNFG_LINK_991_960r_fields,
   4304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4305         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4306         -1,
   4307         -1,
   4308     },
   4309 #endif /* chips */
   4310 
   4311 #if defined(BCM_56370_A0)
   4312     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_991_960_BCM56370_A0r */
   4313         soc_block_list[61],
   4314         soc_iprocreg,
   4315         1,
   4316         0,
   4317         0x1000b0b4,
   4318         0,
   4319         0,
   4320         1,
   4321         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   4322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4323         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4324         -1,
   4325         -1,
   4326         3,
   4327     },
   4328 #endif /* chips */
   4329 
   4330 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   4331     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4332     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_991_960_BCM56870_A0r */
   4333         soc_block_list[61],
   4334         soc_iprocreg,
   4335         1,
   4336         0,
   4337         0x130b0b4,
   4338         0,
   4339         0,
   4340         1,
   4341         soc_PAXB_0_PCIE_SYS_EP_INT_CSR0_BCM88950_A0r_fields,
   4342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4343         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4344         -1,
   4345         -1,
   4346         3,
   4347     },
   4348 #endif /* chips */
   4349 
   4350 #if defined(BCM_88690_A0)
   4351     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_991_960_BCM88690_A0r */
   4352         soc_block_list[61],
   4353         soc_iprocreg,
   4354         1,
   4355         0,
   4356         0x130b0b4,
   4357         0,
   4358         0,
   4359         1,
   4360         soc_U0_LED_SW_CNFG_LINK_991_960_BCM88690_A0r_fields,
   4361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4362         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4363         -1,
   4364         -1,
   4365     },
   4366 #endif /* chips */
   4367 
   4368 #if defined(BCM_88690_B0)
   4369     { /* SOC_REG_INT_U0_LED_SW_CNFG_LINK_991_960_BCM88690_B0r */
   4370         soc_block_list[61],
   4371         soc_iprocreg,
   4372         1,
   4373         0,
   4374         0x130b0b4,
   4375         0,
   4376         0,
   4377         1,
   4378         soc_U0_LED_SW_CNFG_LINK_991_960_BCM88690_B0r_fields,
   4379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4380         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4381         -1,
   4382         -1,
   4383     },
   4384 #endif /* chips */
   4385 
   4386 #if defined(BCM_56370_A0)
   4387     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_0_LSBr */
   4388         soc_block_list[61],
   4389         soc_iprocreg,
   4390         1,
   4391         0,
   4392         0x10060004,
   4393         0,
   4394         0,
   4395         1,
   4396         soc_U0_M0SSQ_ADDR_REMAP_WINDOW_0_LSBr_fields,
   4397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4398         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4399         -1,
   4400         -1,
   4401         3,
   4402     },
   4403 #endif /* chips */
   4404 
   4405 #if defined(BCM_56370_A0)
   4406     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_0_MSBr */
   4407         soc_block_list[61],
   4408         soc_iprocreg,
   4409         1,
   4410         0,
   4411         0x10060008,
   4412         0,
   4413         0,
   4414         1,
   4415         soc_NS_GDPLL_M7_ERROR_INFOr_fields,
   4416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4418         -1,
   4419         -1,
   4420         3,
   4421     },
   4422 #endif /* chips */
   4423 
   4424 #if defined(BCM_56370_A0)
   4425     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_1_LSBr */
   4426         soc_block_list[61],
   4427         soc_iprocreg,
   4428         1,
   4429         0,
   4430         0x1006000c,
   4431         0,
   4432         0,
   4433         1,
   4434         soc_U0_M0SSQ_ADDR_REMAP_WINDOW_0_LSBr_fields,
   4435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4436         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4437         -1,
   4438         -1,
   4439         3,
   4440     },
   4441 #endif /* chips */
   4442 
   4443 #if defined(BCM_56370_A0)
   4444     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_1_MSBr */
   4445         soc_block_list[61],
   4446         soc_iprocreg,
   4447         1,
   4448         0,
   4449         0x10060010,
   4450         0,
   4451         0,
   4452         1,
   4453         soc_NS_GDPLL_M7_ERROR_INFOr_fields,
   4454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4455         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4456         -1,
   4457         -1,
   4458         3,
   4459     },
   4460 #endif /* chips */
   4461 
   4462 #if defined(BCM_56370_A0)
   4463     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_2_LSBr */
   4464         soc_block_list[61],
   4465         soc_iprocreg,
   4466         1,
   4467         0,
   4468         0x10060014,
   4469         0,
   4470         0,
   4471         1,
   4472         soc_U0_M0SSQ_ADDR_REMAP_WINDOW_0_LSBr_fields,
   4473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4474         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4475         -1,
   4476         -1,
   4477         3,
   4478     },
   4479 #endif /* chips */
   4480 
   4481 #if defined(BCM_56370_A0)
   4482     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_2_MSBr */
   4483         soc_block_list[61],
   4484         soc_iprocreg,
   4485         1,
   4486         0,
   4487         0x10060018,
   4488         0,
   4489         0,
   4490         1,
   4491         soc_NS_GDPLL_M7_ERROR_INFOr_fields,
   4492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4493         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4494         -1,
   4495         -1,
   4496         3,
   4497     },
   4498 #endif /* chips */
   4499 
   4500 #if defined(BCM_56370_A0)
   4501     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_3_LSBr */
   4502         soc_block_list[61],
   4503         soc_iprocreg,
   4504         1,
   4505         0,
   4506         0x1006001c,
   4507         0,
   4508         0,
   4509         1,
   4510         soc_U0_M0SSQ_ADDR_REMAP_WINDOW_0_LSBr_fields,
   4511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4512         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4513         -1,
   4514         -1,
   4515         3,
   4516     },
   4517 #endif /* chips */
   4518 
   4519 #if defined(BCM_56370_A0)
   4520     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_3_MSBr */
   4521         soc_block_list[61],
   4522         soc_iprocreg,
   4523         1,
   4524         0,
   4525         0x10060020,
   4526         0,
   4527         0,
   4528         1,
   4529         soc_NS_GDPLL_M7_ERROR_INFOr_fields,
   4530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4531         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4532         -1,
   4533         -1,
   4534         3,
   4535     },
   4536 #endif /* chips */
   4537 
   4538 #if defined(BCM_56370_A0)
   4539     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_4_LSBr */
   4540         soc_block_list[61],
   4541         soc_iprocreg,
   4542         1,
   4543         0,
   4544         0x10060024,
   4545         0,
   4546         0,
   4547         1,
   4548         soc_U0_M0SSQ_ADDR_REMAP_WINDOW_0_LSBr_fields,
   4549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4550         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4551         -1,
   4552         -1,
   4553         3,
   4554     },
   4555 #endif /* chips */
   4556 
   4557 #if defined(BCM_56370_A0)
   4558     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_4_MSBr */
   4559         soc_block_list[61],
   4560         soc_iprocreg,
   4561         1,
   4562         0,
   4563         0x10060028,
   4564         0,
   4565         0,
   4566         1,
   4567         soc_NS_GDPLL_M7_ERROR_INFOr_fields,
   4568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4569         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4570         -1,
   4571         -1,
   4572         3,
   4573     },
   4574 #endif /* chips */
   4575 
   4576 #if defined(BCM_56370_A0)
   4577     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_5_LSBr */
   4578         soc_block_list[61],
   4579         soc_iprocreg,
   4580         1,
   4581         0,
   4582         0x1006002c,
   4583         0,
   4584         0,
   4585         1,
   4586         soc_U0_M0SSQ_ADDR_REMAP_WINDOW_0_LSBr_fields,
   4587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4588         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4589         -1,
   4590         -1,
   4591         3,
   4592     },
   4593 #endif /* chips */
   4594 
   4595 #if defined(BCM_56370_A0)
   4596     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_5_MSBr */
   4597         soc_block_list[61],
   4598         soc_iprocreg,
   4599         1,
   4600         0,
   4601         0x10060030,
   4602         0,
   4603         0,
   4604         1,
   4605         soc_NS_GDPLL_M7_ERROR_INFOr_fields,
   4606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4607         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4608         -1,
   4609         -1,
   4610         3,
   4611     },
   4612 #endif /* chips */
   4613 
   4614 #if defined(BCM_56370_A0)
   4615     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_6_LSBr */
   4616         soc_block_list[61],
   4617         soc_iprocreg,
   4618         1,
   4619         0,
   4620         0x10060034,
   4621         0,
   4622         0,
   4623         1,
   4624         soc_U0_M0SSQ_ADDR_REMAP_WINDOW_0_LSBr_fields,
   4625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4626         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4627         -1,
   4628         -1,
   4629         3,
   4630     },
   4631 #endif /* chips */
   4632 
   4633 #if defined(BCM_56370_A0)
   4634     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_6_MSBr */
   4635         soc_block_list[61],
   4636         soc_iprocreg,
   4637         1,
   4638         0,
   4639         0x10060038,
   4640         0,
   4641         0,
   4642         1,
   4643         soc_NS_GDPLL_M7_ERROR_INFOr_fields,
   4644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4646         -1,
   4647         -1,
   4648         3,
   4649     },
   4650 #endif /* chips */
   4651 
   4652 #if defined(BCM_56370_A0)
   4653     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_7_LSBr */
   4654         soc_block_list[61],
   4655         soc_iprocreg,
   4656         1,
   4657         0,
   4658         0x1006003c,
   4659         0,
   4660         0,
   4661         1,
   4662         soc_U0_M0SSQ_ADDR_REMAP_WINDOW_0_LSBr_fields,
   4663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4664         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   4665         -1,
   4666         -1,
   4667         3,
   4668     },
   4669 #endif /* chips */
   4670 
   4671 #if defined(BCM_56370_A0)
   4672     { /* SOC_REG_INT_U0_M0SSQ_ADDR_REMAP_WINDOW_7_MSBr */
   4673         soc_block_list[61],
   4674         soc_iprocreg,
   4675         1,
   4676         0,
   4677         0x10060040,
   4678         0,
   4679         0,
   4680         1,
   4681         soc_NS_GDPLL_M7_ERROR_INFOr_fields,
   4682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4683         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4684         -1,
   4685         -1,
   4686         3,
   4687     },
   4688 #endif /* chips */
   4689 
   4690 #if defined(BCM_88790_A0)
   4691     { /* SOC_REG_INT_U0_M0SSQ_CTRLr */
   4692         soc_block_list[61],
   4693         soc_iprocreg,
   4694         1,
   4695         0,
   4696         0x1360000,
   4697         0,
   4698         0,
   4699         5,
   4700         soc_U0_M0SSQ_CTRLr_fields,
   4701         SOC_RESET_VAL_DEC(0x00000f80, 0x00000000)
   4702         SOC_RESET_MASK_DEC(0x000f8fff, 0x00000000)
   4703         -1,
   4704         -1,
   4705     },
   4706 #endif /* chips */
   4707 
   4708 #if defined(BCM_56370_A0)
   4709     { /* SOC_REG_INT_U0_M0SSQ_CTRL_BCM56370_A0r */
   4710         soc_block_list[61],
   4711         soc_iprocreg,
   4712         1,
   4713         0,
   4714         0x10060000,
   4715         0,
   4716         0,
   4717         4,
   4718         soc_U0_M0SSQ_CTRL_BCM56370_A0r_fields,
   4719         SOC_RESET_VAL_DEC(0x00000f80, 0x00000000)
   4720         SOC_RESET_MASK_DEC(0x000f8f80, 0x00000000)
   4721         -1,
   4722         -1,
   4723         3,
   4724     },
   4725 #endif /* chips */
   4726 
   4727 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   4728     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4729     { /* SOC_REG_INT_U0_M0SSQ_CTRL_BCM56870_A0r */
   4730         soc_block_list[61],
   4731         soc_iprocreg,
   4732         1,
   4733         0,
   4734         0x1360000,
   4735         0,
   4736         0,
   4737         5,
   4738         soc_U0_M0SSQ_CTRL_BCM56870_A0r_fields,
   4739         SOC_RESET_VAL_DEC(0x00000f80, 0x00000000)
   4740         SOC_RESET_MASK_DEC(0x000f8f80, 0x00000000)
   4741         -1,
   4742         -1,
   4743         3,
   4744     },
   4745 #endif /* chips */
   4746 
   4747 #if defined(BCM_88690_A0)
   4748     { /* SOC_REG_INT_U0_M0SSQ_CTRL_BCM88690_A0r */
   4749         soc_block_list[61],
   4750         soc_iprocreg,
   4751         1,
   4752         0,
   4753         0x1360000,
   4754         0,
   4755         0,
   4756         5,
   4757         soc_U0_M0SSQ_CTRL_BCM88690_A0r_fields,
   4758         SOC_RESET_VAL_DEC(0x00000f80, 0x00000000)
   4759         SOC_RESET_MASK_DEC(0x000f8fff, 0x00000000)
   4760         -1,
   4761         -1,
   4762     },
   4763 #endif /* chips */
   4764 
   4765 #if defined(BCM_88690_B0)
   4766     { /* SOC_REG_INT_U0_M0SSQ_CTRL_BCM88690_B0r */
   4767         soc_block_list[61],
   4768         soc_iprocreg,
   4769         1,
   4770         0,
   4771         0x1360000,
   4772         0,
   4773         0,
   4774         5,
   4775         soc_U0_M0SSQ_CTRL_BCM88690_B0r_fields,
   4776         SOC_RESET_VAL_DEC(0x00000f80, 0x00000000)
   4777         SOC_RESET_MASK_DEC(0x000f8fff, 0x00000000)
   4778         -1,
   4779         -1,
   4780     },
   4781 #endif /* chips */
   4782 
   4783 #if defined(BCM_88790_A0)
   4784     { /* SOC_REG_INT_U0_M0SSQ_ECC_CTRLr */
   4785         soc_block_list[61],
   4786         soc_iprocreg,
   4787         1,
   4788         0,
   4789         0x1360004,
   4790         0,
   4791         0,
   4792         3,
   4793         soc_U0_M0SSQ_ECC_CTRLr_fields,
   4794         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   4795         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4796         -1,
   4797         -1,
   4798     },
   4799 #endif /* chips */
   4800 
   4801 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   4802     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4803     { /* SOC_REG_INT_U0_M0SSQ_ECC_CTRL_BCM56870_A0r */
   4804         soc_block_list[61],
   4805         soc_iprocreg,
   4806         1,
   4807         0,
   4808         0x1360004,
   4809         0,
   4810         0,
   4811         3,
   4812         soc_U0_M0SSQ_ECC_CTRL_BCM56870_A0r_fields,
   4813         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   4814         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4815         -1,
   4816         -1,
   4817         3,
   4818     },
   4819 #endif /* chips */
   4820 
   4821 #if defined(BCM_88690_A0)
   4822     { /* SOC_REG_INT_U0_M0SSQ_ECC_CTRL_BCM88690_A0r */
   4823         soc_block_list[61],
   4824         soc_iprocreg,
   4825         1,
   4826         0,
   4827         0x1360004,
   4828         0,
   4829         0,
   4830         3,
   4831         soc_U0_M0SSQ_ECC_CTRL_BCM88690_A0r_fields,
   4832         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   4833         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4834         -1,
   4835         -1,
   4836     },
   4837 #endif /* chips */
   4838 
   4839 #if defined(BCM_88690_B0)
   4840     { /* SOC_REG_INT_U0_M0SSQ_ECC_CTRL_BCM88690_B0r */
   4841         soc_block_list[61],
   4842         soc_iprocreg,
   4843         1,
   4844         0,
   4845         0x1360004,
   4846         0,
   4847         0,
   4848         3,
   4849         soc_U0_M0SSQ_ECC_CTRL_BCM88690_B0r_fields,
   4850         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   4851         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   4852         -1,
   4853         -1,
   4854     },
   4855 #endif /* chips */
   4856 
   4857 #if defined(BCM_88790_A0)
   4858     { /* SOC_REG_INT_U0_M0SSQ_ECC_STATUSr */
   4859         soc_block_list[61],
   4860         soc_iprocreg,
   4861         1,
   4862         0,
   4863         0x1360008,
   4864         0,
   4865         0,
   4866         4,
   4867         soc_U0_M0SSQ_ECC_STATUSr_fields,
   4868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4869         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   4870         -1,
   4871         -1,
   4872     },
   4873 #endif /* chips */
   4874 
   4875 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   4876     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4877     { /* SOC_REG_INT_U0_M0SSQ_ECC_STATUS_BCM56870_A0r */
   4878         soc_block_list[61],
   4879         soc_iprocreg,
   4880         1,
   4881         0,
   4882         0x1360008,
   4883         0,
   4884         0,
   4885         4,
   4886         soc_U0_M0SSQ_ECC_STATUS_BCM56870_A0r_fields,
   4887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4888         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   4889         -1,
   4890         -1,
   4891         3,
   4892     },
   4893 #endif /* chips */
   4894 
   4895 #if defined(BCM_88690_A0)
   4896     { /* SOC_REG_INT_U0_M0SSQ_ECC_STATUS_BCM88690_A0r */
   4897         soc_block_list[61],
   4898         soc_iprocreg,
   4899         1,
   4900         0,
   4901         0x1360008,
   4902         0,
   4903         0,
   4904         4,
   4905         soc_U0_M0SSQ_ECC_STATUS_BCM88690_A0r_fields,
   4906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4907         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   4908         -1,
   4909         -1,
   4910     },
   4911 #endif /* chips */
   4912 
   4913 #if defined(BCM_88690_B0)
   4914     { /* SOC_REG_INT_U0_M0SSQ_ECC_STATUS_BCM88690_B0r */
   4915         soc_block_list[61],
   4916         soc_iprocreg,
   4917         1,
   4918         0,
   4919         0x1360008,
   4920         0,
   4921         0,
   4922         4,
   4923         soc_U0_M0SSQ_ECC_STATUS_BCM88690_B0r_fields,
   4924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4925         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   4926         -1,
   4927         -1,
   4928     },
   4929 #endif /* chips */
   4930 
   4931 #if defined(BCM_88790_A0)
   4932     { /* SOC_REG_INT_U0_M0SSQ_INTR_ENABLEr */
   4933         soc_block_list[61],
   4934         soc_iprocreg,
   4935         1,
   4936         0,
   4937         0x136000c,
   4938         0,
   4939         0,
   4940         2,
   4941         soc_U0_M0SSQ_INTR_ENABLEr_fields,
   4942         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   4943         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4944         -1,
   4945         -1,
   4946     },
   4947 #endif /* chips */
   4948 
   4949 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   4950     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   4951     { /* SOC_REG_INT_U0_M0SSQ_INTR_ENABLE_BCM56870_A0r */
   4952         soc_block_list[61],
   4953         soc_iprocreg,
   4954         1,
   4955         0,
   4956         0x136000c,
   4957         0,
   4958         0,
   4959         2,
   4960         soc_U0_M0SSQ_INTR_ENABLE_BCM56870_A0r_fields,
   4961         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   4962         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4963         -1,
   4964         -1,
   4965         3,
   4966     },
   4967 #endif /* chips */
   4968 
   4969 #if defined(BCM_88690_A0)
   4970     { /* SOC_REG_INT_U0_M0SSQ_INTR_ENABLE_BCM88690_A0r */
   4971         soc_block_list[61],
   4972         soc_iprocreg,
   4973         1,
   4974         0,
   4975         0x136000c,
   4976         0,
   4977         0,
   4978         2,
   4979         soc_U0_M0SSQ_INTR_ENABLE_BCM88690_A0r_fields,
   4980         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   4981         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   4982         -1,
   4983         -1,
   4984     },
   4985 #endif /* chips */
   4986 
   4987 #if defined(BCM_88690_B0)
   4988     { /* SOC_REG_INT_U0_M0SSQ_INTR_ENABLE_BCM88690_B0r */
   4989         soc_block_list[61],
   4990         soc_iprocreg,
   4991         1,
   4992         0,
   4993         0x136000c,
   4994         0,
   4995         0,
   4996         2,
   4997         soc_U0_M0SSQ_INTR_ENABLE_BCM88690_B0r_fields,
   4998         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   4999         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5000         -1,
   5001         -1,
   5002     },
   5003 #endif /* chips */
   5004 
   5005 #if defined(BCM_88790_A0)
   5006     { /* SOC_REG_INT_U0_M0SS_CONTROLr */
   5007         soc_block_list[61],
   5008         soc_iprocreg,
   5009         1,
   5010         0,
   5011         0x1308000,
   5012         0,
   5013         0,
   5014         3,
   5015         soc_U0_M0SS_CONTROLr_fields,
   5016         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   5017         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   5018         -1,
   5019         -1,
   5020     },
   5021 #endif /* chips */
   5022 
   5023 #if defined(BCM_56370_A0)
   5024     { /* SOC_REG_INT_U0_M0SS_CONTROL_BCM56370_A0r */
   5025         soc_block_list[61],
   5026         soc_iprocreg,
   5027         1,
   5028         0,
   5029         0x10008000,
   5030         0,
   5031         0,
   5032         3,
   5033         soc_U0_M0SS_CONTROL_BCM56870_A0r_fields,
   5034         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   5035         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   5036         -1,
   5037         -1,
   5038         3,
   5039     },
   5040 #endif /* chips */
   5041 
   5042 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5043     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5044     { /* SOC_REG_INT_U0_M0SS_CONTROL_BCM56870_A0r */
   5045         soc_block_list[61],
   5046         soc_iprocreg,
   5047         1,
   5048         0,
   5049         0x1308000,
   5050         0,
   5051         0,
   5052         3,
   5053         soc_U0_M0SS_CONTROL_BCM56870_A0r_fields,
   5054         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   5055         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   5056         -1,
   5057         -1,
   5058         3,
   5059     },
   5060 #endif /* chips */
   5061 
   5062 #if defined(BCM_88690_A0)
   5063     { /* SOC_REG_INT_U0_M0SS_CONTROL_BCM88690_A0r */
   5064         soc_block_list[61],
   5065         soc_iprocreg,
   5066         1,
   5067         0,
   5068         0x1308000,
   5069         0,
   5070         0,
   5071         3,
   5072         soc_U0_M0SS_CONTROL_BCM88690_A0r_fields,
   5073         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   5074         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   5075         -1,
   5076         -1,
   5077     },
   5078 #endif /* chips */
   5079 
   5080 #if defined(BCM_88690_B0)
   5081     { /* SOC_REG_INT_U0_M0SS_CONTROL_BCM88690_B0r */
   5082         soc_block_list[61],
   5083         soc_iprocreg,
   5084         1,
   5085         0,
   5086         0x1308000,
   5087         0,
   5088         0,
   5089         3,
   5090         soc_U0_M0SS_CONTROL_BCM88690_B0r_fields,
   5091         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   5092         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   5093         -1,
   5094         -1,
   5095     },
   5096 #endif /* chips */
   5097 
   5098 #if defined(BCM_88790_A0)
   5099     { /* SOC_REG_INT_U0_M0SS_DEBUG_CONTROLr */
   5100         soc_block_list[61],
   5101         soc_iprocreg,
   5102         1,
   5103         0,
   5104         0x130800c,
   5105         0,
   5106         0,
   5107         2,
   5108         soc_U0_M0SS_DEBUG_CONTROLr_fields,
   5109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5110         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5111         -1,
   5112         -1,
   5113     },
   5114 #endif /* chips */
   5115 
   5116 #if defined(BCM_56370_A0)
   5117     { /* SOC_REG_INT_U0_M0SS_DEBUG_CONTROL_BCM56370_A0r */
   5118         soc_block_list[61],
   5119         soc_iprocreg,
   5120         1,
   5121         0,
   5122         0x1000800c,
   5123         0,
   5124         0,
   5125         2,
   5126         soc_U0_M0SS_DEBUG_CONTROL_BCM56870_A0r_fields,
   5127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5128         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5129         -1,
   5130         -1,
   5131         3,
   5132     },
   5133 #endif /* chips */
   5134 
   5135 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5136     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5137     { /* SOC_REG_INT_U0_M0SS_DEBUG_CONTROL_BCM56870_A0r */
   5138         soc_block_list[61],
   5139         soc_iprocreg,
   5140         1,
   5141         0,
   5142         0x130800c,
   5143         0,
   5144         0,
   5145         2,
   5146         soc_U0_M0SS_DEBUG_CONTROL_BCM56870_A0r_fields,
   5147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5148         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5149         -1,
   5150         -1,
   5151         3,
   5152     },
   5153 #endif /* chips */
   5154 
   5155 #if defined(BCM_88690_A0)
   5156     { /* SOC_REG_INT_U0_M0SS_DEBUG_CONTROL_BCM88690_A0r */
   5157         soc_block_list[61],
   5158         soc_iprocreg,
   5159         1,
   5160         0,
   5161         0x130800c,
   5162         0,
   5163         0,
   5164         2,
   5165         soc_U0_M0SS_DEBUG_CONTROL_BCM88690_A0r_fields,
   5166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5167         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5168         -1,
   5169         -1,
   5170     },
   5171 #endif /* chips */
   5172 
   5173 #if defined(BCM_88690_B0)
   5174     { /* SOC_REG_INT_U0_M0SS_DEBUG_CONTROL_BCM88690_B0r */
   5175         soc_block_list[61],
   5176         soc_iprocreg,
   5177         1,
   5178         0,
   5179         0x130800c,
   5180         0,
   5181         0,
   5182         2,
   5183         soc_U0_M0SS_DEBUG_CONTROL_BCM88690_B0r_fields,
   5184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5185         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5186         -1,
   5187         -1,
   5188     },
   5189 #endif /* chips */
   5190 
   5191 #if defined(BCM_88790_A0)
   5192     { /* SOC_REG_INT_U0_M0SS_ECC_CTRLr */
   5193         soc_block_list[61],
   5194         soc_iprocreg,
   5195         1,
   5196         0,
   5197         0x1308018,
   5198         0,
   5199         0,
   5200         3,
   5201         soc_U0_M0SS_ECC_CTRLr_fields,
   5202         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   5203         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5204         -1,
   5205         -1,
   5206     },
   5207 #endif /* chips */
   5208 
   5209 #if defined(BCM_56370_A0)
   5210     { /* SOC_REG_INT_U0_M0SS_ECC_CTRL_BCM56370_A0r */
   5211         soc_block_list[61],
   5212         soc_iprocreg,
   5213         1,
   5214         0,
   5215         0x10008018,
   5216         0,
   5217         0,
   5218         3,
   5219         soc_U0_M0SSQ_ECC_CTRL_BCM56870_A0r_fields,
   5220         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   5221         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5222         -1,
   5223         -1,
   5224         3,
   5225     },
   5226 #endif /* chips */
   5227 
   5228 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5229     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5230     { /* SOC_REG_INT_U0_M0SS_ECC_CTRL_BCM56870_A0r */
   5231         soc_block_list[61],
   5232         soc_iprocreg,
   5233         1,
   5234         0,
   5235         0x1308018,
   5236         0,
   5237         0,
   5238         3,
   5239         soc_U0_M0SSQ_ECC_CTRL_BCM56870_A0r_fields,
   5240         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   5241         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5242         -1,
   5243         -1,
   5244         3,
   5245     },
   5246 #endif /* chips */
   5247 
   5248 #if defined(BCM_88690_A0)
   5249     { /* SOC_REG_INT_U0_M0SS_ECC_CTRL_BCM88690_A0r */
   5250         soc_block_list[61],
   5251         soc_iprocreg,
   5252         1,
   5253         0,
   5254         0x1308018,
   5255         0,
   5256         0,
   5257         3,
   5258         soc_U0_M0SS_ECC_CTRL_BCM88690_A0r_fields,
   5259         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   5260         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5261         -1,
   5262         -1,
   5263     },
   5264 #endif /* chips */
   5265 
   5266 #if defined(BCM_88690_B0)
   5267     { /* SOC_REG_INT_U0_M0SS_ECC_CTRL_BCM88690_B0r */
   5268         soc_block_list[61],
   5269         soc_iprocreg,
   5270         1,
   5271         0,
   5272         0x1308018,
   5273         0,
   5274         0,
   5275         3,
   5276         soc_U0_M0SS_ECC_CTRL_BCM88690_B0r_fields,
   5277         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   5278         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   5279         -1,
   5280         -1,
   5281     },
   5282 #endif /* chips */
   5283 
   5284 #if defined(BCM_88790_A0)
   5285     { /* SOC_REG_INT_U0_M0SS_ECC_STATUSr */
   5286         soc_block_list[61],
   5287         soc_iprocreg,
   5288         1,
   5289         0,
   5290         0x130801c,
   5291         0,
   5292         0,
   5293         4,
   5294         soc_U0_M0SS_ECC_STATUSr_fields,
   5295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5296         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5297         -1,
   5298         -1,
   5299     },
   5300 #endif /* chips */
   5301 
   5302 #if defined(BCM_56370_A0)
   5303     { /* SOC_REG_INT_U0_M0SS_ECC_STATUS_BCM56370_A0r */
   5304         soc_block_list[61],
   5305         soc_iprocreg,
   5306         1,
   5307         0,
   5308         0x1000801c,
   5309         0,
   5310         0,
   5311         4,
   5312         soc_U0_M0SS_ECC_STATUS_BCM56870_A0r_fields,
   5313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5314         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5315         -1,
   5316         -1,
   5317         3,
   5318     },
   5319 #endif /* chips */
   5320 
   5321 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5322     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5323     { /* SOC_REG_INT_U0_M0SS_ECC_STATUS_BCM56870_A0r */
   5324         soc_block_list[61],
   5325         soc_iprocreg,
   5326         1,
   5327         0,
   5328         0x130801c,
   5329         0,
   5330         0,
   5331         4,
   5332         soc_U0_M0SS_ECC_STATUS_BCM56870_A0r_fields,
   5333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5334         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5335         -1,
   5336         -1,
   5337         3,
   5338     },
   5339 #endif /* chips */
   5340 
   5341 #if defined(BCM_88690_A0)
   5342     { /* SOC_REG_INT_U0_M0SS_ECC_STATUS_BCM88690_A0r */
   5343         soc_block_list[61],
   5344         soc_iprocreg,
   5345         1,
   5346         0,
   5347         0x130801c,
   5348         0,
   5349         0,
   5350         4,
   5351         soc_U0_M0SS_ECC_STATUS_BCM88690_A0r_fields,
   5352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5353         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5354         -1,
   5355         -1,
   5356     },
   5357 #endif /* chips */
   5358 
   5359 #if defined(BCM_88690_B0)
   5360     { /* SOC_REG_INT_U0_M0SS_ECC_STATUS_BCM88690_B0r */
   5361         soc_block_list[61],
   5362         soc_iprocreg,
   5363         1,
   5364         0,
   5365         0x130801c,
   5366         0,
   5367         0,
   5368         4,
   5369         soc_U0_M0SS_ECC_STATUS_BCM88690_B0r_fields,
   5370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5371         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   5372         -1,
   5373         -1,
   5374     },
   5375 #endif /* chips */
   5376 
   5377 #if defined(BCM_88790_A0)
   5378     { /* SOC_REG_INT_U0_M0SS_ECOr */
   5379         soc_block_list[61],
   5380         soc_iprocreg,
   5381         1,
   5382         0,
   5383         0x1308008,
   5384         0,
   5385         0,
   5386         1,
   5387         soc_U0_M0SS_ECOr_fields,
   5388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5389         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5390         -1,
   5391         -1,
   5392     },
   5393 #endif /* chips */
   5394 
   5395 #if defined(BCM_56370_A0)
   5396     { /* SOC_REG_INT_U0_M0SS_ECO_BCM56370_A0r */
   5397         soc_block_list[61],
   5398         soc_iprocreg,
   5399         1,
   5400         0,
   5401         0x10008008,
   5402         0,
   5403         0,
   5404         1,
   5405         soc_U0_M0SS_ECO_BCM56870_A0r_fields,
   5406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5407         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5408         -1,
   5409         -1,
   5410         3,
   5411     },
   5412 #endif /* chips */
   5413 
   5414 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5415     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5416     { /* SOC_REG_INT_U0_M0SS_ECO_BCM56870_A0r */
   5417         soc_block_list[61],
   5418         soc_iprocreg,
   5419         1,
   5420         0,
   5421         0x1308008,
   5422         0,
   5423         0,
   5424         1,
   5425         soc_U0_M0SS_ECO_BCM56870_A0r_fields,
   5426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5427         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5428         -1,
   5429         -1,
   5430         3,
   5431     },
   5432 #endif /* chips */
   5433 
   5434 #if defined(BCM_88690_A0)
   5435     { /* SOC_REG_INT_U0_M0SS_ECO_BCM88690_A0r */
   5436         soc_block_list[61],
   5437         soc_iprocreg,
   5438         1,
   5439         0,
   5440         0x1308008,
   5441         0,
   5442         0,
   5443         1,
   5444         soc_U0_M0SS_ECO_BCM88690_A0r_fields,
   5445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5446         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5447         -1,
   5448         -1,
   5449     },
   5450 #endif /* chips */
   5451 
   5452 #if defined(BCM_88690_B0)
   5453     { /* SOC_REG_INT_U0_M0SS_ECO_BCM88690_B0r */
   5454         soc_block_list[61],
   5455         soc_iprocreg,
   5456         1,
   5457         0,
   5458         0x1308008,
   5459         0,
   5460         0,
   5461         1,
   5462         soc_U0_M0SS_ECO_BCM88690_B0r_fields,
   5463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5464         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5465         -1,
   5466         -1,
   5467     },
   5468 #endif /* chips */
   5469 
   5470 #if defined(BCM_88790_A0)
   5471     { /* SOC_REG_INT_U0_M0SS_INTR_127_96r */
   5472         soc_block_list[61],
   5473         soc_iprocreg,
   5474         1,
   5475         0,
   5476         0x1308070,
   5477         SOC_REG_FLAG_RO,
   5478         0,
   5479         1,
   5480         soc_U0_M0SS_INTR_127_96r_fields,
   5481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5482         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5483         -1,
   5484         -1,
   5485     },
   5486 #endif /* chips */
   5487 
   5488 #if defined(BCM_56370_A0)
   5489     { /* SOC_REG_INT_U0_M0SS_INTR_127_96_BCM56370_A0r */
   5490         soc_block_list[61],
   5491         soc_iprocreg,
   5492         1,
   5493         0,
   5494         0x10008070,
   5495         SOC_REG_FLAG_RO,
   5496         0,
   5497         1,
   5498         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5500         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5501         -1,
   5502         -1,
   5503         3,
   5504     },
   5505 #endif /* chips */
   5506 
   5507 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5508     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5509     { /* SOC_REG_INT_U0_M0SS_INTR_127_96_BCM56870_A0r */
   5510         soc_block_list[61],
   5511         soc_iprocreg,
   5512         1,
   5513         0,
   5514         0x1308070,
   5515         SOC_REG_FLAG_RO,
   5516         0,
   5517         1,
   5518         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5520         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5521         -1,
   5522         -1,
   5523         3,
   5524     },
   5525 #endif /* chips */
   5526 
   5527 #if defined(BCM_88690_A0)
   5528     { /* SOC_REG_INT_U0_M0SS_INTR_127_96_BCM88690_A0r */
   5529         soc_block_list[61],
   5530         soc_iprocreg,
   5531         1,
   5532         0,
   5533         0x1308070,
   5534         SOC_REG_FLAG_RO,
   5535         0,
   5536         1,
   5537         soc_U0_M0SS_INTR_127_96_BCM88690_A0r_fields,
   5538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5539         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5540         -1,
   5541         -1,
   5542     },
   5543 #endif /* chips */
   5544 
   5545 #if defined(BCM_88690_B0)
   5546     { /* SOC_REG_INT_U0_M0SS_INTR_127_96_BCM88690_B0r */
   5547         soc_block_list[61],
   5548         soc_iprocreg,
   5549         1,
   5550         0,
   5551         0x1308070,
   5552         SOC_REG_FLAG_RO,
   5553         0,
   5554         1,
   5555         soc_U0_M0SS_INTR_127_96_BCM88690_B0r_fields,
   5556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5557         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5558         -1,
   5559         -1,
   5560     },
   5561 #endif /* chips */
   5562 
   5563 #if defined(BCM_88790_A0)
   5564     { /* SOC_REG_INT_U0_M0SS_INTR_159_128r */
   5565         soc_block_list[61],
   5566         soc_iprocreg,
   5567         1,
   5568         0,
   5569         0x1308074,
   5570         SOC_REG_FLAG_RO,
   5571         0,
   5572         1,
   5573         soc_U0_M0SS_INTR_159_128r_fields,
   5574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5575         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5576         -1,
   5577         -1,
   5578     },
   5579 #endif /* chips */
   5580 
   5581 #if defined(BCM_56370_A0)
   5582     { /* SOC_REG_INT_U0_M0SS_INTR_159_128_BCM56370_A0r */
   5583         soc_block_list[61],
   5584         soc_iprocreg,
   5585         1,
   5586         0,
   5587         0x10008074,
   5588         SOC_REG_FLAG_RO,
   5589         0,
   5590         1,
   5591         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5593         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5594         -1,
   5595         -1,
   5596         3,
   5597     },
   5598 #endif /* chips */
   5599 
   5600 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5601     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5602     { /* SOC_REG_INT_U0_M0SS_INTR_159_128_BCM56870_A0r */
   5603         soc_block_list[61],
   5604         soc_iprocreg,
   5605         1,
   5606         0,
   5607         0x1308074,
   5608         SOC_REG_FLAG_RO,
   5609         0,
   5610         1,
   5611         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5613         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5614         -1,
   5615         -1,
   5616         3,
   5617     },
   5618 #endif /* chips */
   5619 
   5620 #if defined(BCM_88690_A0)
   5621     { /* SOC_REG_INT_U0_M0SS_INTR_159_128_BCM88690_A0r */
   5622         soc_block_list[61],
   5623         soc_iprocreg,
   5624         1,
   5625         0,
   5626         0x1308074,
   5627         SOC_REG_FLAG_RO,
   5628         0,
   5629         1,
   5630         soc_U0_M0SS_INTR_159_128_BCM88690_A0r_fields,
   5631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5632         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5633         -1,
   5634         -1,
   5635     },
   5636 #endif /* chips */
   5637 
   5638 #if defined(BCM_88690_B0)
   5639     { /* SOC_REG_INT_U0_M0SS_INTR_159_128_BCM88690_B0r */
   5640         soc_block_list[61],
   5641         soc_iprocreg,
   5642         1,
   5643         0,
   5644         0x1308074,
   5645         SOC_REG_FLAG_RO,
   5646         0,
   5647         1,
   5648         soc_U0_M0SS_INTR_159_128_BCM88690_B0r_fields,
   5649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5651         -1,
   5652         -1,
   5653     },
   5654 #endif /* chips */
   5655 
   5656 #if defined(BCM_88790_A0)
   5657     { /* SOC_REG_INT_U0_M0SS_INTR_191_160r */
   5658         soc_block_list[61],
   5659         soc_iprocreg,
   5660         1,
   5661         0,
   5662         0x1308078,
   5663         SOC_REG_FLAG_RO,
   5664         0,
   5665         1,
   5666         soc_U0_M0SS_INTR_191_160r_fields,
   5667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5668         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5669         -1,
   5670         -1,
   5671     },
   5672 #endif /* chips */
   5673 
   5674 #if defined(BCM_56370_A0)
   5675     { /* SOC_REG_INT_U0_M0SS_INTR_191_160_BCM56370_A0r */
   5676         soc_block_list[61],
   5677         soc_iprocreg,
   5678         1,
   5679         0,
   5680         0x10008078,
   5681         SOC_REG_FLAG_RO,
   5682         0,
   5683         1,
   5684         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5686         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5687         -1,
   5688         -1,
   5689         3,
   5690     },
   5691 #endif /* chips */
   5692 
   5693 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5694     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5695     { /* SOC_REG_INT_U0_M0SS_INTR_191_160_BCM56870_A0r */
   5696         soc_block_list[61],
   5697         soc_iprocreg,
   5698         1,
   5699         0,
   5700         0x1308078,
   5701         SOC_REG_FLAG_RO,
   5702         0,
   5703         1,
   5704         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5706         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5707         -1,
   5708         -1,
   5709         3,
   5710     },
   5711 #endif /* chips */
   5712 
   5713 #if defined(BCM_88690_A0)
   5714     { /* SOC_REG_INT_U0_M0SS_INTR_191_160_BCM88690_A0r */
   5715         soc_block_list[61],
   5716         soc_iprocreg,
   5717         1,
   5718         0,
   5719         0x1308078,
   5720         SOC_REG_FLAG_RO,
   5721         0,
   5722         1,
   5723         soc_U0_M0SS_INTR_191_160_BCM88690_A0r_fields,
   5724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5726         -1,
   5727         -1,
   5728     },
   5729 #endif /* chips */
   5730 
   5731 #if defined(BCM_88690_B0)
   5732     { /* SOC_REG_INT_U0_M0SS_INTR_191_160_BCM88690_B0r */
   5733         soc_block_list[61],
   5734         soc_iprocreg,
   5735         1,
   5736         0,
   5737         0x1308078,
   5738         SOC_REG_FLAG_RO,
   5739         0,
   5740         1,
   5741         soc_U0_M0SS_INTR_191_160_BCM88690_B0r_fields,
   5742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5744         -1,
   5745         -1,
   5746     },
   5747 #endif /* chips */
   5748 
   5749 #if defined(BCM_88790_A0)
   5750     { /* SOC_REG_INT_U0_M0SS_INTR_223_192r */
   5751         soc_block_list[61],
   5752         soc_iprocreg,
   5753         1,
   5754         0,
   5755         0x130807c,
   5756         SOC_REG_FLAG_RO,
   5757         0,
   5758         1,
   5759         soc_U0_M0SS_INTR_223_192r_fields,
   5760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5762         -1,
   5763         -1,
   5764     },
   5765 #endif /* chips */
   5766 
   5767 #if defined(BCM_56370_A0)
   5768     { /* SOC_REG_INT_U0_M0SS_INTR_223_192_BCM56370_A0r */
   5769         soc_block_list[61],
   5770         soc_iprocreg,
   5771         1,
   5772         0,
   5773         0x1000807c,
   5774         SOC_REG_FLAG_RO,
   5775         0,
   5776         1,
   5777         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5779         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5780         -1,
   5781         -1,
   5782         3,
   5783     },
   5784 #endif /* chips */
   5785 
   5786 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5787     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5788     { /* SOC_REG_INT_U0_M0SS_INTR_223_192_BCM56870_A0r */
   5789         soc_block_list[61],
   5790         soc_iprocreg,
   5791         1,
   5792         0,
   5793         0x130807c,
   5794         SOC_REG_FLAG_RO,
   5795         0,
   5796         1,
   5797         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5799         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5800         -1,
   5801         -1,
   5802         3,
   5803     },
   5804 #endif /* chips */
   5805 
   5806 #if defined(BCM_88690_A0)
   5807     { /* SOC_REG_INT_U0_M0SS_INTR_223_192_BCM88690_A0r */
   5808         soc_block_list[61],
   5809         soc_iprocreg,
   5810         1,
   5811         0,
   5812         0x130807c,
   5813         SOC_REG_FLAG_RO,
   5814         0,
   5815         1,
   5816         soc_U0_M0SS_INTR_223_192_BCM88690_A0r_fields,
   5817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5818         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5819         -1,
   5820         -1,
   5821     },
   5822 #endif /* chips */
   5823 
   5824 #if defined(BCM_88690_B0)
   5825     { /* SOC_REG_INT_U0_M0SS_INTR_223_192_BCM88690_B0r */
   5826         soc_block_list[61],
   5827         soc_iprocreg,
   5828         1,
   5829         0,
   5830         0x130807c,
   5831         SOC_REG_FLAG_RO,
   5832         0,
   5833         1,
   5834         soc_U0_M0SS_INTR_223_192_BCM88690_B0r_fields,
   5835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5837         -1,
   5838         -1,
   5839     },
   5840 #endif /* chips */
   5841 
   5842 #if defined(BCM_88790_A0)
   5843     { /* SOC_REG_INT_U0_M0SS_INTR_255_224r */
   5844         soc_block_list[61],
   5845         soc_iprocreg,
   5846         1,
   5847         0,
   5848         0x1308080,
   5849         SOC_REG_FLAG_RO,
   5850         0,
   5851         1,
   5852         soc_U0_M0SS_INTR_255_224r_fields,
   5853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5854         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5855         -1,
   5856         -1,
   5857     },
   5858 #endif /* chips */
   5859 
   5860 #if defined(BCM_56370_A0)
   5861     { /* SOC_REG_INT_U0_M0SS_INTR_255_224_BCM56370_A0r */
   5862         soc_block_list[61],
   5863         soc_iprocreg,
   5864         1,
   5865         0,
   5866         0x10008080,
   5867         SOC_REG_FLAG_RO,
   5868         0,
   5869         1,
   5870         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5872         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5873         -1,
   5874         -1,
   5875         3,
   5876     },
   5877 #endif /* chips */
   5878 
   5879 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5880     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5881     { /* SOC_REG_INT_U0_M0SS_INTR_255_224_BCM56870_A0r */
   5882         soc_block_list[61],
   5883         soc_iprocreg,
   5884         1,
   5885         0,
   5886         0x1308080,
   5887         SOC_REG_FLAG_RO,
   5888         0,
   5889         1,
   5890         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5893         -1,
   5894         -1,
   5895         3,
   5896     },
   5897 #endif /* chips */
   5898 
   5899 #if defined(BCM_88690_A0)
   5900     { /* SOC_REG_INT_U0_M0SS_INTR_255_224_BCM88690_A0r */
   5901         soc_block_list[61],
   5902         soc_iprocreg,
   5903         1,
   5904         0,
   5905         0x1308080,
   5906         SOC_REG_FLAG_RO,
   5907         0,
   5908         1,
   5909         soc_U0_M0SS_INTR_255_224_BCM88690_A0r_fields,
   5910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5912         -1,
   5913         -1,
   5914     },
   5915 #endif /* chips */
   5916 
   5917 #if defined(BCM_88690_B0)
   5918     { /* SOC_REG_INT_U0_M0SS_INTR_255_224_BCM88690_B0r */
   5919         soc_block_list[61],
   5920         soc_iprocreg,
   5921         1,
   5922         0,
   5923         0x1308080,
   5924         SOC_REG_FLAG_RO,
   5925         0,
   5926         1,
   5927         soc_U0_M0SS_INTR_255_224_BCM88690_B0r_fields,
   5928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5929         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5930         -1,
   5931         -1,
   5932     },
   5933 #endif /* chips */
   5934 
   5935 #if defined(BCM_88790_A0)
   5936     { /* SOC_REG_INT_U0_M0SS_INTR_31_0r */
   5937         soc_block_list[61],
   5938         soc_iprocreg,
   5939         1,
   5940         0,
   5941         0x1308064,
   5942         SOC_REG_FLAG_RO,
   5943         0,
   5944         1,
   5945         soc_U0_M0SS_INTR_31_0r_fields,
   5946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5947         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5948         -1,
   5949         -1,
   5950     },
   5951 #endif /* chips */
   5952 
   5953 #if defined(BCM_56370_A0)
   5954     { /* SOC_REG_INT_U0_M0SS_INTR_31_0_BCM56370_A0r */
   5955         soc_block_list[61],
   5956         soc_iprocreg,
   5957         1,
   5958         0,
   5959         0x10008064,
   5960         SOC_REG_FLAG_RO,
   5961         0,
   5962         1,
   5963         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5965         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5966         -1,
   5967         -1,
   5968         3,
   5969     },
   5970 #endif /* chips */
   5971 
   5972 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5973     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   5974     { /* SOC_REG_INT_U0_M0SS_INTR_31_0_BCM56870_A0r */
   5975         soc_block_list[61],
   5976         soc_iprocreg,
   5977         1,
   5978         0,
   5979         0x1308064,
   5980         SOC_REG_FLAG_RO,
   5981         0,
   5982         1,
   5983         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   5984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5985         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5986         -1,
   5987         -1,
   5988         3,
   5989     },
   5990 #endif /* chips */
   5991 
   5992 #if defined(BCM_88690_A0)
   5993     { /* SOC_REG_INT_U0_M0SS_INTR_31_0_BCM88690_A0r */
   5994         soc_block_list[61],
   5995         soc_iprocreg,
   5996         1,
   5997         0,
   5998         0x1308064,
   5999         SOC_REG_FLAG_RO,
   6000         0,
   6001         1,
   6002         soc_U0_M0SS_INTR_31_0_BCM88690_A0r_fields,
   6003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6004         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6005         -1,
   6006         -1,
   6007     },
   6008 #endif /* chips */
   6009 
   6010 #if defined(BCM_88690_B0)
   6011     { /* SOC_REG_INT_U0_M0SS_INTR_31_0_BCM88690_B0r */
   6012         soc_block_list[61],
   6013         soc_iprocreg,
   6014         1,
   6015         0,
   6016         0x1308064,
   6017         SOC_REG_FLAG_RO,
   6018         0,
   6019         1,
   6020         soc_U0_M0SS_INTR_31_0_BCM88690_B0r_fields,
   6021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6023         -1,
   6024         -1,
   6025     },
   6026 #endif /* chips */
   6027 
   6028 #if defined(BCM_88790_A0)
   6029     { /* SOC_REG_INT_U0_M0SS_INTR_63_32r */
   6030         soc_block_list[61],
   6031         soc_iprocreg,
   6032         1,
   6033         0,
   6034         0x1308068,
   6035         SOC_REG_FLAG_RO,
   6036         0,
   6037         1,
   6038         soc_U0_M0SS_INTR_63_32r_fields,
   6039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6040         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6041         -1,
   6042         -1,
   6043     },
   6044 #endif /* chips */
   6045 
   6046 #if defined(BCM_56370_A0)
   6047     { /* SOC_REG_INT_U0_M0SS_INTR_63_32_BCM56370_A0r */
   6048         soc_block_list[61],
   6049         soc_iprocreg,
   6050         1,
   6051         0,
   6052         0x10008068,
   6053         SOC_REG_FLAG_RO,
   6054         0,
   6055         1,
   6056         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   6057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6058         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6059         -1,
   6060         -1,
   6061         3,
   6062     },
   6063 #endif /* chips */
   6064 
   6065 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6066     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6067     { /* SOC_REG_INT_U0_M0SS_INTR_63_32_BCM56870_A0r */
   6068         soc_block_list[61],
   6069         soc_iprocreg,
   6070         1,
   6071         0,
   6072         0x1308068,
   6073         SOC_REG_FLAG_RO,
   6074         0,
   6075         1,
   6076         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   6077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6078         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6079         -1,
   6080         -1,
   6081         3,
   6082     },
   6083 #endif /* chips */
   6084 
   6085 #if defined(BCM_88690_A0)
   6086     { /* SOC_REG_INT_U0_M0SS_INTR_63_32_BCM88690_A0r */
   6087         soc_block_list[61],
   6088         soc_iprocreg,
   6089         1,
   6090         0,
   6091         0x1308068,
   6092         SOC_REG_FLAG_RO,
   6093         0,
   6094         1,
   6095         soc_U0_M0SS_INTR_63_32_BCM88690_A0r_fields,
   6096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6098         -1,
   6099         -1,
   6100     },
   6101 #endif /* chips */
   6102 
   6103 #if defined(BCM_88690_B0)
   6104     { /* SOC_REG_INT_U0_M0SS_INTR_63_32_BCM88690_B0r */
   6105         soc_block_list[61],
   6106         soc_iprocreg,
   6107         1,
   6108         0,
   6109         0x1308068,
   6110         SOC_REG_FLAG_RO,
   6111         0,
   6112         1,
   6113         soc_U0_M0SS_INTR_63_32_BCM88690_B0r_fields,
   6114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6116         -1,
   6117         -1,
   6118     },
   6119 #endif /* chips */
   6120 
   6121 #if defined(BCM_88790_A0)
   6122     { /* SOC_REG_INT_U0_M0SS_INTR_95_64r */
   6123         soc_block_list[61],
   6124         soc_iprocreg,
   6125         1,
   6126         0,
   6127         0x130806c,
   6128         SOC_REG_FLAG_RO,
   6129         0,
   6130         1,
   6131         soc_U0_M0SS_INTR_95_64r_fields,
   6132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6133         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6134         -1,
   6135         -1,
   6136     },
   6137 #endif /* chips */
   6138 
   6139 #if defined(BCM_56370_A0)
   6140     { /* SOC_REG_INT_U0_M0SS_INTR_95_64_BCM56370_A0r */
   6141         soc_block_list[61],
   6142         soc_iprocreg,
   6143         1,
   6144         0,
   6145         0x1000806c,
   6146         SOC_REG_FLAG_RO,
   6147         0,
   6148         1,
   6149         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   6150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6151         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6152         -1,
   6153         -1,
   6154         3,
   6155     },
   6156 #endif /* chips */
   6157 
   6158 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6159     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6160     { /* SOC_REG_INT_U0_M0SS_INTR_95_64_BCM56870_A0r */
   6161         soc_block_list[61],
   6162         soc_iprocreg,
   6163         1,
   6164         0,
   6165         0x130806c,
   6166         SOC_REG_FLAG_RO,
   6167         0,
   6168         1,
   6169         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   6170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6171         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6172         -1,
   6173         -1,
   6174         3,
   6175     },
   6176 #endif /* chips */
   6177 
   6178 #if defined(BCM_88690_A0)
   6179     { /* SOC_REG_INT_U0_M0SS_INTR_95_64_BCM88690_A0r */
   6180         soc_block_list[61],
   6181         soc_iprocreg,
   6182         1,
   6183         0,
   6184         0x130806c,
   6185         SOC_REG_FLAG_RO,
   6186         0,
   6187         1,
   6188         soc_U0_M0SS_INTR_95_64_BCM88690_A0r_fields,
   6189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6190         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6191         -1,
   6192         -1,
   6193     },
   6194 #endif /* chips */
   6195 
   6196 #if defined(BCM_88690_B0)
   6197     { /* SOC_REG_INT_U0_M0SS_INTR_95_64_BCM88690_B0r */
   6198         soc_block_list[61],
   6199         soc_iprocreg,
   6200         1,
   6201         0,
   6202         0x130806c,
   6203         SOC_REG_FLAG_RO,
   6204         0,
   6205         1,
   6206         soc_U0_M0SS_INTR_95_64_BCM88690_B0r_fields,
   6207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6208         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6209         -1,
   6210         -1,
   6211     },
   6212 #endif /* chips */
   6213 
   6214 #if defined(BCM_88790_A0)
   6215     { /* SOC_REG_INT_U0_M0SS_INTR_CONTROLr */
   6216         soc_block_list[61],
   6217         soc_iprocreg,
   6218         1,
   6219         0,
   6220         0x1308004,
   6221         0,
   6222         0,
   6223         3,
   6224         soc_U0_M0SS_INTR_CONTROLr_fields,
   6225         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
   6226         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6227         -1,
   6228         -1,
   6229     },
   6230 #endif /* chips */
   6231 
   6232 #if defined(BCM_56370_A0)
   6233     { /* SOC_REG_INT_U0_M0SS_INTR_CONTROL_BCM56370_A0r */
   6234         soc_block_list[61],
   6235         soc_iprocreg,
   6236         1,
   6237         0,
   6238         0x10008004,
   6239         0,
   6240         0,
   6241         3,
   6242         soc_U0_M0SS_INTR_CONTROL_BCM56870_A0r_fields,
   6243         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
   6244         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6245         -1,
   6246         -1,
   6247         3,
   6248     },
   6249 #endif /* chips */
   6250 
   6251 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6252     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6253     { /* SOC_REG_INT_U0_M0SS_INTR_CONTROL_BCM56870_A0r */
   6254         soc_block_list[61],
   6255         soc_iprocreg,
   6256         1,
   6257         0,
   6258         0x1308004,
   6259         0,
   6260         0,
   6261         3,
   6262         soc_U0_M0SS_INTR_CONTROL_BCM56870_A0r_fields,
   6263         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
   6264         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6265         -1,
   6266         -1,
   6267         3,
   6268     },
   6269 #endif /* chips */
   6270 
   6271 #if defined(BCM_88690_A0)
   6272     { /* SOC_REG_INT_U0_M0SS_INTR_CONTROL_BCM88690_A0r */
   6273         soc_block_list[61],
   6274         soc_iprocreg,
   6275         1,
   6276         0,
   6277         0x1308004,
   6278         0,
   6279         0,
   6280         3,
   6281         soc_U0_M0SS_INTR_CONTROL_BCM88690_A0r_fields,
   6282         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
   6283         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6284         -1,
   6285         -1,
   6286     },
   6287 #endif /* chips */
   6288 
   6289 #if defined(BCM_88690_B0)
   6290     { /* SOC_REG_INT_U0_M0SS_INTR_CONTROL_BCM88690_B0r */
   6291         soc_block_list[61],
   6292         soc_iprocreg,
   6293         1,
   6294         0,
   6295         0x1308004,
   6296         0,
   6297         0,
   6298         3,
   6299         soc_U0_M0SS_INTR_CONTROL_BCM88690_B0r_fields,
   6300         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
   6301         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   6302         -1,
   6303         -1,
   6304     },
   6305 #endif /* chips */
   6306 
   6307 #if defined(BCM_88790_A0)
   6308     { /* SOC_REG_INT_U0_M0SS_INTR_ENABLEr */
   6309         soc_block_list[61],
   6310         soc_iprocreg,
   6311         1,
   6312         0,
   6313         0x1308020,
   6314         0,
   6315         0,
   6316         2,
   6317         soc_U0_M0SS_INTR_ENABLEr_fields,
   6318         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6319         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6320         -1,
   6321         -1,
   6322     },
   6323 #endif /* chips */
   6324 
   6325 #if defined(BCM_56370_A0)
   6326     { /* SOC_REG_INT_U0_M0SS_INTR_ENABLE_BCM56370_A0r */
   6327         soc_block_list[61],
   6328         soc_iprocreg,
   6329         1,
   6330         0,
   6331         0x10008020,
   6332         0,
   6333         0,
   6334         2,
   6335         soc_U0_M0SSQ_INTR_ENABLE_BCM56870_A0r_fields,
   6336         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6337         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6338         -1,
   6339         -1,
   6340         3,
   6341     },
   6342 #endif /* chips */
   6343 
   6344 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6345     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6346     { /* SOC_REG_INT_U0_M0SS_INTR_ENABLE_BCM56870_A0r */
   6347         soc_block_list[61],
   6348         soc_iprocreg,
   6349         1,
   6350         0,
   6351         0x1308020,
   6352         0,
   6353         0,
   6354         2,
   6355         soc_U0_M0SSQ_INTR_ENABLE_BCM56870_A0r_fields,
   6356         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6357         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6358         -1,
   6359         -1,
   6360         3,
   6361     },
   6362 #endif /* chips */
   6363 
   6364 #if defined(BCM_88690_A0)
   6365     { /* SOC_REG_INT_U0_M0SS_INTR_ENABLE_BCM88690_A0r */
   6366         soc_block_list[61],
   6367         soc_iprocreg,
   6368         1,
   6369         0,
   6370         0x1308020,
   6371         0,
   6372         0,
   6373         2,
   6374         soc_U0_M0SS_INTR_ENABLE_BCM88690_A0r_fields,
   6375         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6376         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6377         -1,
   6378         -1,
   6379     },
   6380 #endif /* chips */
   6381 
   6382 #if defined(BCM_88690_B0)
   6383     { /* SOC_REG_INT_U0_M0SS_INTR_ENABLE_BCM88690_B0r */
   6384         soc_block_list[61],
   6385         soc_iprocreg,
   6386         1,
   6387         0,
   6388         0x1308020,
   6389         0,
   6390         0,
   6391         2,
   6392         soc_U0_M0SS_INTR_ENABLE_BCM88690_B0r_fields,
   6393         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6394         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6395         -1,
   6396         -1,
   6397     },
   6398 #endif /* chips */
   6399 
   6400 #if defined(BCM_88790_A0)
   6401     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_127_96r */
   6402         soc_block_list[61],
   6403         soc_iprocreg,
   6404         1,
   6405         0,
   6406         0x1308050,
   6407         0,
   6408         0,
   6409         1,
   6410         soc_U0_M0SS_INTR_MASK_127_96r_fields,
   6411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6412         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6413         -1,
   6414         -1,
   6415     },
   6416 #endif /* chips */
   6417 
   6418 #if defined(BCM_56370_A0)
   6419     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_127_96_BCM56370_A0r */
   6420         soc_block_list[61],
   6421         soc_iprocreg,
   6422         1,
   6423         0,
   6424         0x10008050,
   6425         0,
   6426         0,
   6427         1,
   6428         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6430         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6431         -1,
   6432         -1,
   6433         3,
   6434     },
   6435 #endif /* chips */
   6436 
   6437 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6438     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6439     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r */
   6440         soc_block_list[61],
   6441         soc_iprocreg,
   6442         1,
   6443         0,
   6444         0x1308050,
   6445         0,
   6446         0,
   6447         1,
   6448         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6451         -1,
   6452         -1,
   6453         3,
   6454     },
   6455 #endif /* chips */
   6456 
   6457 #if defined(BCM_88690_A0)
   6458     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_127_96_BCM88690_A0r */
   6459         soc_block_list[61],
   6460         soc_iprocreg,
   6461         1,
   6462         0,
   6463         0x1308050,
   6464         0,
   6465         0,
   6466         1,
   6467         soc_U0_M0SS_INTR_MASK_127_96_BCM88690_A0r_fields,
   6468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6469         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6470         -1,
   6471         -1,
   6472     },
   6473 #endif /* chips */
   6474 
   6475 #if defined(BCM_88690_B0)
   6476     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_127_96_BCM88690_B0r */
   6477         soc_block_list[61],
   6478         soc_iprocreg,
   6479         1,
   6480         0,
   6481         0x1308050,
   6482         0,
   6483         0,
   6484         1,
   6485         soc_U0_M0SS_INTR_MASK_127_96_BCM88690_B0r_fields,
   6486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6487         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6488         -1,
   6489         -1,
   6490     },
   6491 #endif /* chips */
   6492 
   6493 #if defined(BCM_88790_A0)
   6494     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_159_128r */
   6495         soc_block_list[61],
   6496         soc_iprocreg,
   6497         1,
   6498         0,
   6499         0x1308054,
   6500         0,
   6501         0,
   6502         1,
   6503         soc_U0_M0SS_INTR_MASK_159_128r_fields,
   6504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6505         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6506         -1,
   6507         -1,
   6508     },
   6509 #endif /* chips */
   6510 
   6511 #if defined(BCM_56370_A0)
   6512     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_159_128_BCM56370_A0r */
   6513         soc_block_list[61],
   6514         soc_iprocreg,
   6515         1,
   6516         0,
   6517         0x10008054,
   6518         0,
   6519         0,
   6520         1,
   6521         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6523         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6524         -1,
   6525         -1,
   6526         3,
   6527     },
   6528 #endif /* chips */
   6529 
   6530 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6531     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6532     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_159_128_BCM56870_A0r */
   6533         soc_block_list[61],
   6534         soc_iprocreg,
   6535         1,
   6536         0,
   6537         0x1308054,
   6538         0,
   6539         0,
   6540         1,
   6541         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6544         -1,
   6545         -1,
   6546         3,
   6547     },
   6548 #endif /* chips */
   6549 
   6550 #if defined(BCM_88690_A0)
   6551     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_159_128_BCM88690_A0r */
   6552         soc_block_list[61],
   6553         soc_iprocreg,
   6554         1,
   6555         0,
   6556         0x1308054,
   6557         0,
   6558         0,
   6559         1,
   6560         soc_U0_M0SS_INTR_MASK_159_128_BCM88690_A0r_fields,
   6561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6562         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6563         -1,
   6564         -1,
   6565     },
   6566 #endif /* chips */
   6567 
   6568 #if defined(BCM_88690_B0)
   6569     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_159_128_BCM88690_B0r */
   6570         soc_block_list[61],
   6571         soc_iprocreg,
   6572         1,
   6573         0,
   6574         0x1308054,
   6575         0,
   6576         0,
   6577         1,
   6578         soc_U0_M0SS_INTR_MASK_159_128_BCM88690_B0r_fields,
   6579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6580         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6581         -1,
   6582         -1,
   6583     },
   6584 #endif /* chips */
   6585 
   6586 #if defined(BCM_88790_A0)
   6587     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_191_160r */
   6588         soc_block_list[61],
   6589         soc_iprocreg,
   6590         1,
   6591         0,
   6592         0x1308058,
   6593         0,
   6594         0,
   6595         1,
   6596         soc_U0_M0SS_INTR_MASK_191_160r_fields,
   6597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6598         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6599         -1,
   6600         -1,
   6601     },
   6602 #endif /* chips */
   6603 
   6604 #if defined(BCM_56370_A0)
   6605     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_191_160_BCM56370_A0r */
   6606         soc_block_list[61],
   6607         soc_iprocreg,
   6608         1,
   6609         0,
   6610         0x10008058,
   6611         0,
   6612         0,
   6613         1,
   6614         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6616         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6617         -1,
   6618         -1,
   6619         3,
   6620     },
   6621 #endif /* chips */
   6622 
   6623 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6624     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6625     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_191_160_BCM56870_A0r */
   6626         soc_block_list[61],
   6627         soc_iprocreg,
   6628         1,
   6629         0,
   6630         0x1308058,
   6631         0,
   6632         0,
   6633         1,
   6634         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6636         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6637         -1,
   6638         -1,
   6639         3,
   6640     },
   6641 #endif /* chips */
   6642 
   6643 #if defined(BCM_88690_A0)
   6644     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_191_160_BCM88690_A0r */
   6645         soc_block_list[61],
   6646         soc_iprocreg,
   6647         1,
   6648         0,
   6649         0x1308058,
   6650         0,
   6651         0,
   6652         1,
   6653         soc_U0_M0SS_INTR_MASK_191_160_BCM88690_A0r_fields,
   6654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6655         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6656         -1,
   6657         -1,
   6658     },
   6659 #endif /* chips */
   6660 
   6661 #if defined(BCM_88690_B0)
   6662     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_191_160_BCM88690_B0r */
   6663         soc_block_list[61],
   6664         soc_iprocreg,
   6665         1,
   6666         0,
   6667         0x1308058,
   6668         0,
   6669         0,
   6670         1,
   6671         soc_U0_M0SS_INTR_MASK_191_160_BCM88690_B0r_fields,
   6672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6673         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6674         -1,
   6675         -1,
   6676     },
   6677 #endif /* chips */
   6678 
   6679 #if defined(BCM_88790_A0)
   6680     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_223_192r */
   6681         soc_block_list[61],
   6682         soc_iprocreg,
   6683         1,
   6684         0,
   6685         0x130805c,
   6686         0,
   6687         0,
   6688         1,
   6689         soc_U0_M0SS_INTR_MASK_223_192r_fields,
   6690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6691         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6692         -1,
   6693         -1,
   6694     },
   6695 #endif /* chips */
   6696 
   6697 #if defined(BCM_56370_A0)
   6698     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_223_192_BCM56370_A0r */
   6699         soc_block_list[61],
   6700         soc_iprocreg,
   6701         1,
   6702         0,
   6703         0x1000805c,
   6704         0,
   6705         0,
   6706         1,
   6707         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6709         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6710         -1,
   6711         -1,
   6712         3,
   6713     },
   6714 #endif /* chips */
   6715 
   6716 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6717     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6718     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_223_192_BCM56870_A0r */
   6719         soc_block_list[61],
   6720         soc_iprocreg,
   6721         1,
   6722         0,
   6723         0x130805c,
   6724         0,
   6725         0,
   6726         1,
   6727         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6729         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6730         -1,
   6731         -1,
   6732         3,
   6733     },
   6734 #endif /* chips */
   6735 
   6736 #if defined(BCM_88690_A0)
   6737     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_223_192_BCM88690_A0r */
   6738         soc_block_list[61],
   6739         soc_iprocreg,
   6740         1,
   6741         0,
   6742         0x130805c,
   6743         0,
   6744         0,
   6745         1,
   6746         soc_U0_M0SS_INTR_MASK_223_192_BCM88690_A0r_fields,
   6747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6748         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6749         -1,
   6750         -1,
   6751     },
   6752 #endif /* chips */
   6753 
   6754 #if defined(BCM_88690_B0)
   6755     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_223_192_BCM88690_B0r */
   6756         soc_block_list[61],
   6757         soc_iprocreg,
   6758         1,
   6759         0,
   6760         0x130805c,
   6761         0,
   6762         0,
   6763         1,
   6764         soc_U0_M0SS_INTR_MASK_223_192_BCM88690_B0r_fields,
   6765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6766         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6767         -1,
   6768         -1,
   6769     },
   6770 #endif /* chips */
   6771 
   6772 #if defined(BCM_88790_A0)
   6773     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_255_224r */
   6774         soc_block_list[61],
   6775         soc_iprocreg,
   6776         1,
   6777         0,
   6778         0x1308060,
   6779         0,
   6780         0,
   6781         1,
   6782         soc_U0_M0SS_INTR_MASK_255_224r_fields,
   6783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6784         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6785         -1,
   6786         -1,
   6787     },
   6788 #endif /* chips */
   6789 
   6790 #if defined(BCM_56370_A0)
   6791     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_255_224_BCM56370_A0r */
   6792         soc_block_list[61],
   6793         soc_iprocreg,
   6794         1,
   6795         0,
   6796         0x10008060,
   6797         0,
   6798         0,
   6799         1,
   6800         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6802         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6803         -1,
   6804         -1,
   6805         3,
   6806     },
   6807 #endif /* chips */
   6808 
   6809 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6810     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6811     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_255_224_BCM56870_A0r */
   6812         soc_block_list[61],
   6813         soc_iprocreg,
   6814         1,
   6815         0,
   6816         0x1308060,
   6817         0,
   6818         0,
   6819         1,
   6820         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6822         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6823         -1,
   6824         -1,
   6825         3,
   6826     },
   6827 #endif /* chips */
   6828 
   6829 #if defined(BCM_88690_A0)
   6830     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_255_224_BCM88690_A0r */
   6831         soc_block_list[61],
   6832         soc_iprocreg,
   6833         1,
   6834         0,
   6835         0x1308060,
   6836         0,
   6837         0,
   6838         1,
   6839         soc_U0_M0SS_INTR_MASK_255_224_BCM88690_A0r_fields,
   6840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6842         -1,
   6843         -1,
   6844     },
   6845 #endif /* chips */
   6846 
   6847 #if defined(BCM_88690_B0)
   6848     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_255_224_BCM88690_B0r */
   6849         soc_block_list[61],
   6850         soc_iprocreg,
   6851         1,
   6852         0,
   6853         0x1308060,
   6854         0,
   6855         0,
   6856         1,
   6857         soc_U0_M0SS_INTR_MASK_255_224_BCM88690_B0r_fields,
   6858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6859         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6860         -1,
   6861         -1,
   6862     },
   6863 #endif /* chips */
   6864 
   6865 #if defined(BCM_88790_A0)
   6866     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_31_0r */
   6867         soc_block_list[61],
   6868         soc_iprocreg,
   6869         1,
   6870         0,
   6871         0x1308044,
   6872         0,
   6873         0,
   6874         1,
   6875         soc_U0_M0SS_INTR_MASK_31_0r_fields,
   6876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6878         -1,
   6879         -1,
   6880     },
   6881 #endif /* chips */
   6882 
   6883 #if defined(BCM_56370_A0)
   6884     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_31_0_BCM56370_A0r */
   6885         soc_block_list[61],
   6886         soc_iprocreg,
   6887         1,
   6888         0,
   6889         0x10008044,
   6890         0,
   6891         0,
   6892         1,
   6893         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6895         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6896         -1,
   6897         -1,
   6898         3,
   6899     },
   6900 #endif /* chips */
   6901 
   6902 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6903     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6904     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_31_0_BCM56870_A0r */
   6905         soc_block_list[61],
   6906         soc_iprocreg,
   6907         1,
   6908         0,
   6909         0x1308044,
   6910         0,
   6911         0,
   6912         1,
   6913         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6916         -1,
   6917         -1,
   6918         3,
   6919     },
   6920 #endif /* chips */
   6921 
   6922 #if defined(BCM_88690_A0)
   6923     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_31_0_BCM88690_A0r */
   6924         soc_block_list[61],
   6925         soc_iprocreg,
   6926         1,
   6927         0,
   6928         0x1308044,
   6929         0,
   6930         0,
   6931         1,
   6932         soc_U0_M0SS_INTR_MASK_31_0_BCM88690_A0r_fields,
   6933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6934         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6935         -1,
   6936         -1,
   6937     },
   6938 #endif /* chips */
   6939 
   6940 #if defined(BCM_88690_B0)
   6941     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_31_0_BCM88690_B0r */
   6942         soc_block_list[61],
   6943         soc_iprocreg,
   6944         1,
   6945         0,
   6946         0x1308044,
   6947         0,
   6948         0,
   6949         1,
   6950         soc_U0_M0SS_INTR_MASK_31_0_BCM88690_B0r_fields,
   6951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6952         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6953         -1,
   6954         -1,
   6955     },
   6956 #endif /* chips */
   6957 
   6958 #if defined(BCM_88790_A0)
   6959     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_63_32r */
   6960         soc_block_list[61],
   6961         soc_iprocreg,
   6962         1,
   6963         0,
   6964         0x1308048,
   6965         0,
   6966         0,
   6967         1,
   6968         soc_U0_M0SS_INTR_MASK_63_32r_fields,
   6969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6970         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6971         -1,
   6972         -1,
   6973     },
   6974 #endif /* chips */
   6975 
   6976 #if defined(BCM_56370_A0)
   6977     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_63_32_BCM56370_A0r */
   6978         soc_block_list[61],
   6979         soc_iprocreg,
   6980         1,
   6981         0,
   6982         0x10008048,
   6983         0,
   6984         0,
   6985         1,
   6986         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   6987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6988         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6989         -1,
   6990         -1,
   6991         3,
   6992     },
   6993 #endif /* chips */
   6994 
   6995 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6996     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   6997     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_63_32_BCM56870_A0r */
   6998         soc_block_list[61],
   6999         soc_iprocreg,
   7000         1,
   7001         0,
   7002         0x1308048,
   7003         0,
   7004         0,
   7005         1,
   7006         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   7007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7008         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7009         -1,
   7010         -1,
   7011         3,
   7012     },
   7013 #endif /* chips */
   7014 
   7015 #if defined(BCM_88690_A0)
   7016     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_63_32_BCM88690_A0r */
   7017         soc_block_list[61],
   7018         soc_iprocreg,
   7019         1,
   7020         0,
   7021         0x1308048,
   7022         0,
   7023         0,
   7024         1,
   7025         soc_U0_M0SS_INTR_MASK_63_32_BCM88690_A0r_fields,
   7026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7028         -1,
   7029         -1,
   7030     },
   7031 #endif /* chips */
   7032 
   7033 #if defined(BCM_88690_B0)
   7034     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_63_32_BCM88690_B0r */
   7035         soc_block_list[61],
   7036         soc_iprocreg,
   7037         1,
   7038         0,
   7039         0x1308048,
   7040         0,
   7041         0,
   7042         1,
   7043         soc_U0_M0SS_INTR_MASK_63_32_BCM88690_B0r_fields,
   7044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7045         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7046         -1,
   7047         -1,
   7048     },
   7049 #endif /* chips */
   7050 
   7051 #if defined(BCM_88790_A0)
   7052     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_95_64r */
   7053         soc_block_list[61],
   7054         soc_iprocreg,
   7055         1,
   7056         0,
   7057         0x130804c,
   7058         0,
   7059         0,
   7060         1,
   7061         soc_U0_M0SS_INTR_MASK_95_64r_fields,
   7062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7063         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7064         -1,
   7065         -1,
   7066     },
   7067 #endif /* chips */
   7068 
   7069 #if defined(BCM_56370_A0)
   7070     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_95_64_BCM56370_A0r */
   7071         soc_block_list[61],
   7072         soc_iprocreg,
   7073         1,
   7074         0,
   7075         0x1000804c,
   7076         0,
   7077         0,
   7078         1,
   7079         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   7080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7081         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7082         -1,
   7083         -1,
   7084         3,
   7085     },
   7086 #endif /* chips */
   7087 
   7088 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7089     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7090     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_95_64_BCM56870_A0r */
   7091         soc_block_list[61],
   7092         soc_iprocreg,
   7093         1,
   7094         0,
   7095         0x130804c,
   7096         0,
   7097         0,
   7098         1,
   7099         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   7100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7101         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7102         -1,
   7103         -1,
   7104         3,
   7105     },
   7106 #endif /* chips */
   7107 
   7108 #if defined(BCM_88690_A0)
   7109     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_95_64_BCM88690_A0r */
   7110         soc_block_list[61],
   7111         soc_iprocreg,
   7112         1,
   7113         0,
   7114         0x130804c,
   7115         0,
   7116         0,
   7117         1,
   7118         soc_U0_M0SS_INTR_MASK_95_64_BCM88690_A0r_fields,
   7119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7120         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7121         -1,
   7122         -1,
   7123     },
   7124 #endif /* chips */
   7125 
   7126 #if defined(BCM_88690_B0)
   7127     { /* SOC_REG_INT_U0_M0SS_INTR_MASK_95_64_BCM88690_B0r */
   7128         soc_block_list[61],
   7129         soc_iprocreg,
   7130         1,
   7131         0,
   7132         0x130804c,
   7133         0,
   7134         0,
   7135         1,
   7136         soc_U0_M0SS_INTR_MASK_95_64_BCM88690_B0r_fields,
   7137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7138         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7139         -1,
   7140         -1,
   7141     },
   7142 #endif /* chips */
   7143 
   7144 #if defined(BCM_88790_A0)
   7145     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_127_96r */
   7146         soc_block_list[61],
   7147         soc_iprocreg,
   7148         1,
   7149         0,
   7150         0x1308030,
   7151         SOC_REG_FLAG_RO,
   7152         0,
   7153         1,
   7154         soc_U0_M0SS_RAW_INTR_127_96r_fields,
   7155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7157         -1,
   7158         -1,
   7159     },
   7160 #endif /* chips */
   7161 
   7162 #if defined(BCM_56370_A0)
   7163     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_127_96_BCM56370_A0r */
   7164         soc_block_list[61],
   7165         soc_iprocreg,
   7166         1,
   7167         0,
   7168         0x10008030,
   7169         SOC_REG_FLAG_RO,
   7170         0,
   7171         1,
   7172         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7174         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7175         -1,
   7176         -1,
   7177         3,
   7178     },
   7179 #endif /* chips */
   7180 
   7181 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7182     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7183     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_127_96_BCM56870_A0r */
   7184         soc_block_list[61],
   7185         soc_iprocreg,
   7186         1,
   7187         0,
   7188         0x1308030,
   7189         SOC_REG_FLAG_RO,
   7190         0,
   7191         1,
   7192         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7194         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7195         -1,
   7196         -1,
   7197         3,
   7198     },
   7199 #endif /* chips */
   7200 
   7201 #if defined(BCM_88690_A0)
   7202     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_127_96_BCM88690_A0r */
   7203         soc_block_list[61],
   7204         soc_iprocreg,
   7205         1,
   7206         0,
   7207         0x1308030,
   7208         SOC_REG_FLAG_RO,
   7209         0,
   7210         1,
   7211         soc_U0_M0SS_RAW_INTR_127_96_BCM88690_A0r_fields,
   7212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7213         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7214         -1,
   7215         -1,
   7216     },
   7217 #endif /* chips */
   7218 
   7219 #if defined(BCM_88690_B0)
   7220     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_127_96_BCM88690_B0r */
   7221         soc_block_list[61],
   7222         soc_iprocreg,
   7223         1,
   7224         0,
   7225         0x1308030,
   7226         SOC_REG_FLAG_RO,
   7227         0,
   7228         1,
   7229         soc_U0_M0SS_RAW_INTR_127_96_BCM88690_B0r_fields,
   7230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7231         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7232         -1,
   7233         -1,
   7234     },
   7235 #endif /* chips */
   7236 
   7237 #if defined(BCM_88790_A0)
   7238     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_159_128r */
   7239         soc_block_list[61],
   7240         soc_iprocreg,
   7241         1,
   7242         0,
   7243         0x1308034,
   7244         SOC_REG_FLAG_RO,
   7245         0,
   7246         1,
   7247         soc_U0_M0SS_RAW_INTR_159_128r_fields,
   7248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7249         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7250         -1,
   7251         -1,
   7252     },
   7253 #endif /* chips */
   7254 
   7255 #if defined(BCM_56370_A0)
   7256     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_159_128_BCM56370_A0r */
   7257         soc_block_list[61],
   7258         soc_iprocreg,
   7259         1,
   7260         0,
   7261         0x10008034,
   7262         SOC_REG_FLAG_RO,
   7263         0,
   7264         1,
   7265         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7267         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7268         -1,
   7269         -1,
   7270         3,
   7271     },
   7272 #endif /* chips */
   7273 
   7274 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7275     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7276     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_159_128_BCM56870_A0r */
   7277         soc_block_list[61],
   7278         soc_iprocreg,
   7279         1,
   7280         0,
   7281         0x1308034,
   7282         SOC_REG_FLAG_RO,
   7283         0,
   7284         1,
   7285         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7287         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7288         -1,
   7289         -1,
   7290         3,
   7291     },
   7292 #endif /* chips */
   7293 
   7294 #if defined(BCM_88690_A0)
   7295     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_159_128_BCM88690_A0r */
   7296         soc_block_list[61],
   7297         soc_iprocreg,
   7298         1,
   7299         0,
   7300         0x1308034,
   7301         SOC_REG_FLAG_RO,
   7302         0,
   7303         1,
   7304         soc_U0_M0SS_RAW_INTR_159_128_BCM88690_A0r_fields,
   7305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7306         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7307         -1,
   7308         -1,
   7309     },
   7310 #endif /* chips */
   7311 
   7312 #if defined(BCM_88690_B0)
   7313     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_159_128_BCM88690_B0r */
   7314         soc_block_list[61],
   7315         soc_iprocreg,
   7316         1,
   7317         0,
   7318         0x1308034,
   7319         SOC_REG_FLAG_RO,
   7320         0,
   7321         1,
   7322         soc_U0_M0SS_RAW_INTR_159_128_BCM88690_B0r_fields,
   7323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7324         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7325         -1,
   7326         -1,
   7327     },
   7328 #endif /* chips */
   7329 
   7330 #if defined(BCM_88790_A0)
   7331     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_191_160r */
   7332         soc_block_list[61],
   7333         soc_iprocreg,
   7334         1,
   7335         0,
   7336         0x1308038,
   7337         SOC_REG_FLAG_RO,
   7338         0,
   7339         1,
   7340         soc_U0_M0SS_RAW_INTR_191_160r_fields,
   7341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7342         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7343         -1,
   7344         -1,
   7345     },
   7346 #endif /* chips */
   7347 
   7348 #if defined(BCM_56370_A0)
   7349     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_191_160_BCM56370_A0r */
   7350         soc_block_list[61],
   7351         soc_iprocreg,
   7352         1,
   7353         0,
   7354         0x10008038,
   7355         SOC_REG_FLAG_RO,
   7356         0,
   7357         1,
   7358         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7360         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7361         -1,
   7362         -1,
   7363         3,
   7364     },
   7365 #endif /* chips */
   7366 
   7367 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7368     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7369     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_191_160_BCM56870_A0r */
   7370         soc_block_list[61],
   7371         soc_iprocreg,
   7372         1,
   7373         0,
   7374         0x1308038,
   7375         SOC_REG_FLAG_RO,
   7376         0,
   7377         1,
   7378         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7380         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7381         -1,
   7382         -1,
   7383         3,
   7384     },
   7385 #endif /* chips */
   7386 
   7387 #if defined(BCM_88690_A0)
   7388     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_191_160_BCM88690_A0r */
   7389         soc_block_list[61],
   7390         soc_iprocreg,
   7391         1,
   7392         0,
   7393         0x1308038,
   7394         SOC_REG_FLAG_RO,
   7395         0,
   7396         1,
   7397         soc_U0_M0SS_RAW_INTR_191_160_BCM88690_A0r_fields,
   7398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7399         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7400         -1,
   7401         -1,
   7402     },
   7403 #endif /* chips */
   7404 
   7405 #if defined(BCM_88690_B0)
   7406     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_191_160_BCM88690_B0r */
   7407         soc_block_list[61],
   7408         soc_iprocreg,
   7409         1,
   7410         0,
   7411         0x1308038,
   7412         SOC_REG_FLAG_RO,
   7413         0,
   7414         1,
   7415         soc_U0_M0SS_RAW_INTR_191_160_BCM88690_B0r_fields,
   7416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7418         -1,
   7419         -1,
   7420     },
   7421 #endif /* chips */
   7422 
   7423 #if defined(BCM_88790_A0)
   7424     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_223_192r */
   7425         soc_block_list[61],
   7426         soc_iprocreg,
   7427         1,
   7428         0,
   7429         0x130803c,
   7430         SOC_REG_FLAG_RO,
   7431         0,
   7432         1,
   7433         soc_U0_M0SS_RAW_INTR_223_192r_fields,
   7434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7435         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7436         -1,
   7437         -1,
   7438     },
   7439 #endif /* chips */
   7440 
   7441 #if defined(BCM_56370_A0)
   7442     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_223_192_BCM56370_A0r */
   7443         soc_block_list[61],
   7444         soc_iprocreg,
   7445         1,
   7446         0,
   7447         0x1000803c,
   7448         SOC_REG_FLAG_RO,
   7449         0,
   7450         1,
   7451         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7454         -1,
   7455         -1,
   7456         3,
   7457     },
   7458 #endif /* chips */
   7459 
   7460 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7461     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7462     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_223_192_BCM56870_A0r */
   7463         soc_block_list[61],
   7464         soc_iprocreg,
   7465         1,
   7466         0,
   7467         0x130803c,
   7468         SOC_REG_FLAG_RO,
   7469         0,
   7470         1,
   7471         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7473         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7474         -1,
   7475         -1,
   7476         3,
   7477     },
   7478 #endif /* chips */
   7479 
   7480 #if defined(BCM_88690_A0)
   7481     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_223_192_BCM88690_A0r */
   7482         soc_block_list[61],
   7483         soc_iprocreg,
   7484         1,
   7485         0,
   7486         0x130803c,
   7487         SOC_REG_FLAG_RO,
   7488         0,
   7489         1,
   7490         soc_U0_M0SS_RAW_INTR_223_192_BCM88690_A0r_fields,
   7491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7492         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7493         -1,
   7494         -1,
   7495     },
   7496 #endif /* chips */
   7497 
   7498 #if defined(BCM_88690_B0)
   7499     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_223_192_BCM88690_B0r */
   7500         soc_block_list[61],
   7501         soc_iprocreg,
   7502         1,
   7503         0,
   7504         0x130803c,
   7505         SOC_REG_FLAG_RO,
   7506         0,
   7507         1,
   7508         soc_U0_M0SS_RAW_INTR_223_192_BCM88690_B0r_fields,
   7509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7510         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7511         -1,
   7512         -1,
   7513     },
   7514 #endif /* chips */
   7515 
   7516 #if defined(BCM_88790_A0)
   7517     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_255_224r */
   7518         soc_block_list[61],
   7519         soc_iprocreg,
   7520         1,
   7521         0,
   7522         0x1308040,
   7523         SOC_REG_FLAG_RO,
   7524         0,
   7525         1,
   7526         soc_U0_M0SS_RAW_INTR_255_224r_fields,
   7527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7528         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7529         -1,
   7530         -1,
   7531     },
   7532 #endif /* chips */
   7533 
   7534 #if defined(BCM_56370_A0)
   7535     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_255_224_BCM56370_A0r */
   7536         soc_block_list[61],
   7537         soc_iprocreg,
   7538         1,
   7539         0,
   7540         0x10008040,
   7541         SOC_REG_FLAG_RO,
   7542         0,
   7543         1,
   7544         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7546         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7547         -1,
   7548         -1,
   7549         3,
   7550     },
   7551 #endif /* chips */
   7552 
   7553 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7554     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7555     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_255_224_BCM56870_A0r */
   7556         soc_block_list[61],
   7557         soc_iprocreg,
   7558         1,
   7559         0,
   7560         0x1308040,
   7561         SOC_REG_FLAG_RO,
   7562         0,
   7563         1,
   7564         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7566         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7567         -1,
   7568         -1,
   7569         3,
   7570     },
   7571 #endif /* chips */
   7572 
   7573 #if defined(BCM_88690_A0)
   7574     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_255_224_BCM88690_A0r */
   7575         soc_block_list[61],
   7576         soc_iprocreg,
   7577         1,
   7578         0,
   7579         0x1308040,
   7580         SOC_REG_FLAG_RO,
   7581         0,
   7582         1,
   7583         soc_U0_M0SS_RAW_INTR_255_224_BCM88690_A0r_fields,
   7584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7585         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7586         -1,
   7587         -1,
   7588     },
   7589 #endif /* chips */
   7590 
   7591 #if defined(BCM_88690_B0)
   7592     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_255_224_BCM88690_B0r */
   7593         soc_block_list[61],
   7594         soc_iprocreg,
   7595         1,
   7596         0,
   7597         0x1308040,
   7598         SOC_REG_FLAG_RO,
   7599         0,
   7600         1,
   7601         soc_U0_M0SS_RAW_INTR_255_224_BCM88690_B0r_fields,
   7602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7603         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7604         -1,
   7605         -1,
   7606     },
   7607 #endif /* chips */
   7608 
   7609 #if defined(BCM_88790_A0)
   7610     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_31_0r */
   7611         soc_block_list[61],
   7612         soc_iprocreg,
   7613         1,
   7614         0,
   7615         0x1308024,
   7616         SOC_REG_FLAG_RO,
   7617         0,
   7618         1,
   7619         soc_U0_M0SS_RAW_INTR_31_0r_fields,
   7620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7621         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7622         -1,
   7623         -1,
   7624     },
   7625 #endif /* chips */
   7626 
   7627 #if defined(BCM_56370_A0)
   7628     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_31_0_BCM56370_A0r */
   7629         soc_block_list[61],
   7630         soc_iprocreg,
   7631         1,
   7632         0,
   7633         0x10008024,
   7634         SOC_REG_FLAG_RO,
   7635         0,
   7636         1,
   7637         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7639         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7640         -1,
   7641         -1,
   7642         3,
   7643     },
   7644 #endif /* chips */
   7645 
   7646 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7647     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7648     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_31_0_BCM56870_A0r */
   7649         soc_block_list[61],
   7650         soc_iprocreg,
   7651         1,
   7652         0,
   7653         0x1308024,
   7654         SOC_REG_FLAG_RO,
   7655         0,
   7656         1,
   7657         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7659         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7660         -1,
   7661         -1,
   7662         3,
   7663     },
   7664 #endif /* chips */
   7665 
   7666 #if defined(BCM_88690_A0)
   7667     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_31_0_BCM88690_A0r */
   7668         soc_block_list[61],
   7669         soc_iprocreg,
   7670         1,
   7671         0,
   7672         0x1308024,
   7673         SOC_REG_FLAG_RO,
   7674         0,
   7675         1,
   7676         soc_U0_M0SS_RAW_INTR_31_0_BCM88690_A0r_fields,
   7677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7678         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7679         -1,
   7680         -1,
   7681     },
   7682 #endif /* chips */
   7683 
   7684 #if defined(BCM_88690_B0)
   7685     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_31_0_BCM88690_B0r */
   7686         soc_block_list[61],
   7687         soc_iprocreg,
   7688         1,
   7689         0,
   7690         0x1308024,
   7691         SOC_REG_FLAG_RO,
   7692         0,
   7693         1,
   7694         soc_U0_M0SS_RAW_INTR_31_0_BCM88690_B0r_fields,
   7695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7696         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7697         -1,
   7698         -1,
   7699     },
   7700 #endif /* chips */
   7701 
   7702 #if defined(BCM_88790_A0)
   7703     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_63_32r */
   7704         soc_block_list[61],
   7705         soc_iprocreg,
   7706         1,
   7707         0,
   7708         0x1308028,
   7709         SOC_REG_FLAG_RO,
   7710         0,
   7711         1,
   7712         soc_U0_M0SS_RAW_INTR_63_32r_fields,
   7713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7714         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7715         -1,
   7716         -1,
   7717     },
   7718 #endif /* chips */
   7719 
   7720 #if defined(BCM_56370_A0)
   7721     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_63_32_BCM56370_A0r */
   7722         soc_block_list[61],
   7723         soc_iprocreg,
   7724         1,
   7725         0,
   7726         0x10008028,
   7727         SOC_REG_FLAG_RO,
   7728         0,
   7729         1,
   7730         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7732         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7733         -1,
   7734         -1,
   7735         3,
   7736     },
   7737 #endif /* chips */
   7738 
   7739 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7740     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7741     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_63_32_BCM56870_A0r */
   7742         soc_block_list[61],
   7743         soc_iprocreg,
   7744         1,
   7745         0,
   7746         0x1308028,
   7747         SOC_REG_FLAG_RO,
   7748         0,
   7749         1,
   7750         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7752         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7753         -1,
   7754         -1,
   7755         3,
   7756     },
   7757 #endif /* chips */
   7758 
   7759 #if defined(BCM_88690_A0)
   7760     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_63_32_BCM88690_A0r */
   7761         soc_block_list[61],
   7762         soc_iprocreg,
   7763         1,
   7764         0,
   7765         0x1308028,
   7766         SOC_REG_FLAG_RO,
   7767         0,
   7768         1,
   7769         soc_U0_M0SS_RAW_INTR_63_32_BCM88690_A0r_fields,
   7770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7771         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7772         -1,
   7773         -1,
   7774     },
   7775 #endif /* chips */
   7776 
   7777 #if defined(BCM_88690_B0)
   7778     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_63_32_BCM88690_B0r */
   7779         soc_block_list[61],
   7780         soc_iprocreg,
   7781         1,
   7782         0,
   7783         0x1308028,
   7784         SOC_REG_FLAG_RO,
   7785         0,
   7786         1,
   7787         soc_U0_M0SS_RAW_INTR_63_32_BCM88690_B0r_fields,
   7788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7789         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7790         -1,
   7791         -1,
   7792     },
   7793 #endif /* chips */
   7794 
   7795 #if defined(BCM_88790_A0)
   7796     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_95_64r */
   7797         soc_block_list[61],
   7798         soc_iprocreg,
   7799         1,
   7800         0,
   7801         0x130802c,
   7802         SOC_REG_FLAG_RO,
   7803         0,
   7804         1,
   7805         soc_U0_M0SS_RAW_INTR_95_64r_fields,
   7806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7807         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7808         -1,
   7809         -1,
   7810     },
   7811 #endif /* chips */
   7812 
   7813 #if defined(BCM_56370_A0)
   7814     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_95_64_BCM56370_A0r */
   7815         soc_block_list[61],
   7816         soc_iprocreg,
   7817         1,
   7818         0,
   7819         0x1000802c,
   7820         SOC_REG_FLAG_RO,
   7821         0,
   7822         1,
   7823         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7825         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7826         -1,
   7827         -1,
   7828         3,
   7829     },
   7830 #endif /* chips */
   7831 
   7832 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7833     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7834     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_95_64_BCM56870_A0r */
   7835         soc_block_list[61],
   7836         soc_iprocreg,
   7837         1,
   7838         0,
   7839         0x130802c,
   7840         SOC_REG_FLAG_RO,
   7841         0,
   7842         1,
   7843         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   7844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7845         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7846         -1,
   7847         -1,
   7848         3,
   7849     },
   7850 #endif /* chips */
   7851 
   7852 #if defined(BCM_88690_A0)
   7853     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_95_64_BCM88690_A0r */
   7854         soc_block_list[61],
   7855         soc_iprocreg,
   7856         1,
   7857         0,
   7858         0x130802c,
   7859         SOC_REG_FLAG_RO,
   7860         0,
   7861         1,
   7862         soc_U0_M0SS_RAW_INTR_95_64_BCM88690_A0r_fields,
   7863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7864         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7865         -1,
   7866         -1,
   7867     },
   7868 #endif /* chips */
   7869 
   7870 #if defined(BCM_88690_B0)
   7871     { /* SOC_REG_INT_U0_M0SS_RAW_INTR_95_64_BCM88690_B0r */
   7872         soc_block_list[61],
   7873         soc_iprocreg,
   7874         1,
   7875         0,
   7876         0x130802c,
   7877         SOC_REG_FLAG_RO,
   7878         0,
   7879         1,
   7880         soc_U0_M0SS_RAW_INTR_95_64_BCM88690_B0r_fields,
   7881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7882         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7883         -1,
   7884         -1,
   7885     },
   7886 #endif /* chips */
   7887 
   7888 #if defined(BCM_88790_A0)
   7889     { /* SOC_REG_INT_U0_M0SS_STATUSr */
   7890         soc_block_list[61],
   7891         soc_iprocreg,
   7892         1,
   7893         0,
   7894         0x1308010,
   7895         0,
   7896         0,
   7897         10,
   7898         soc_U0_M0SS_STATUSr_fields,
   7899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7900         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
   7901         -1,
   7902         -1,
   7903     },
   7904 #endif /* chips */
   7905 
   7906 #if defined(BCM_56370_A0)
   7907     { /* SOC_REG_INT_U0_M0SS_STATUS_BCM56370_A0r */
   7908         soc_block_list[61],
   7909         soc_iprocreg,
   7910         1,
   7911         0,
   7912         0x10008010,
   7913         0,
   7914         0,
   7915         10,
   7916         soc_U0_M0SS_STATUS_BCM56870_A0r_fields,
   7917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7918         SOC_RESET_MASK_DEC(0xffff001f, 0x00000000)
   7919         -1,
   7920         -1,
   7921         3,
   7922     },
   7923 #endif /* chips */
   7924 
   7925 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7926     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   7927     { /* SOC_REG_INT_U0_M0SS_STATUS_BCM56870_A0r */
   7928         soc_block_list[61],
   7929         soc_iprocreg,
   7930         1,
   7931         0,
   7932         0x1308010,
   7933         0,
   7934         0,
   7935         10,
   7936         soc_U0_M0SS_STATUS_BCM56870_A0r_fields,
   7937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7938         SOC_RESET_MASK_DEC(0xffff001f, 0x00000000)
   7939         -1,
   7940         -1,
   7941         3,
   7942     },
   7943 #endif /* chips */
   7944 
   7945 #if defined(BCM_88690_A0)
   7946     { /* SOC_REG_INT_U0_M0SS_STATUS_BCM88690_A0r */
   7947         soc_block_list[61],
   7948         soc_iprocreg,
   7949         1,
   7950         0,
   7951         0x1308010,
   7952         0,
   7953         0,
   7954         10,
   7955         soc_U0_M0SS_STATUS_BCM88690_A0r_fields,
   7956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7957         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
   7958         -1,
   7959         -1,
   7960     },
   7961 #endif /* chips */
   7962 
   7963 #if defined(BCM_88690_B0)
   7964     { /* SOC_REG_INT_U0_M0SS_STATUS_BCM88690_B0r */
   7965         soc_block_list[61],
   7966         soc_iprocreg,
   7967         1,
   7968         0,
   7969         0x1308010,
   7970         0,
   7971         0,
   7972         10,
   7973         soc_U0_M0SS_STATUS_BCM88690_B0r_fields,
   7974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7975         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
   7976         -1,
   7977         -1,
   7978     },
   7979 #endif /* chips */
   7980 
   7981 #if defined(BCM_88790_A0)
   7982     { /* SOC_REG_INT_U0_M0SS_TCM_CTRLr */
   7983         soc_block_list[61],
   7984         soc_iprocreg,
   7985         1,
   7986         0,
   7987         0x1308014,
   7988         0,
   7989         0,
   7990         1,
   7991         soc_U0_M0SS_TCM_CTRLr_fields,
   7992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7993         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   7994         -1,
   7995         -1,
   7996     },
   7997 #endif /* chips */
   7998 
   7999 #if defined(BCM_56370_A0)
   8000     { /* SOC_REG_INT_U0_M0SS_TCM_CTRL_BCM56370_A0r */
   8001         soc_block_list[61],
   8002         soc_iprocreg,
   8003         1,
   8004         0,
   8005         0x10008014,
   8006         0,
   8007         0,
   8008         1,
   8009         soc_U0_M0SS_TCM_CTRL_BCM56870_A0r_fields,
   8010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8011         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8012         -1,
   8013         -1,
   8014         3,
   8015     },
   8016 #endif /* chips */
   8017 
   8018 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8019     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8020     { /* SOC_REG_INT_U0_M0SS_TCM_CTRL_BCM56870_A0r */
   8021         soc_block_list[61],
   8022         soc_iprocreg,
   8023         1,
   8024         0,
   8025         0x1308014,
   8026         0,
   8027         0,
   8028         1,
   8029         soc_U0_M0SS_TCM_CTRL_BCM56870_A0r_fields,
   8030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8031         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   8032         -1,
   8033         -1,
   8034         3,
   8035     },
   8036 #endif /* chips */
   8037 
   8038 #if defined(BCM_88690_A0)
   8039     { /* SOC_REG_INT_U0_M0SS_TCM_CTRL_BCM88690_A0r */
   8040         soc_block_list[61],
   8041         soc_iprocreg,
   8042         1,
   8043         0,
   8044         0x1308014,
   8045         0,
   8046         0,
   8047         1,
   8048         soc_U0_M0SS_TCM_CTRL_BCM88690_A0r_fields,
   8049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8050         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   8051         -1,
   8052         -1,
   8053     },
   8054 #endif /* chips */
   8055 
   8056 #if defined(BCM_88690_B0)
   8057     { /* SOC_REG_INT_U0_M0SS_TCM_CTRL_BCM88690_B0r */
   8058         soc_block_list[61],
   8059         soc_iprocreg,
   8060         1,
   8061         0,
   8062         0x1308014,
   8063         0,
   8064         0,
   8065         1,
   8066         soc_U0_M0SS_TCM_CTRL_BCM88690_B0r_fields,
   8067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8068         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   8069         -1,
   8070         -1,
   8071     },
   8072 #endif /* chips */
   8073 
   8074 #if defined(BCM_56370_A0)
   8075     { /* SOC_REG_INT_U0_SW_PROG_INTR_CLRr */
   8076         soc_block_list[61],
   8077         soc_iprocreg,
   8078         1,
   8079         0,
   8080         0x10008090,
   8081         0,
   8082         0,
   8083         1,
   8084         soc_PAXB_0_SW_PROG_INTR_CLRr_fields,
   8085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8086         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8087         -1,
   8088         -1,
   8089         3,
   8090     },
   8091 #endif /* chips */
   8092 
   8093 #if defined(BCM_56370_A0)
   8094     { /* SOC_REG_INT_U0_SW_PROG_INTR_ENABLEr */
   8095         soc_block_list[61],
   8096         soc_iprocreg,
   8097         1,
   8098         0,
   8099         0x10008084,
   8100         0,
   8101         0,
   8102         1,
   8103         soc_MIIM_DMA_CH0_DST_HOST_ADDRESS_BCM56870_A0r_fields,
   8104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8105         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8106         -1,
   8107         -1,
   8108         3,
   8109     },
   8110 #endif /* chips */
   8111 
   8112 #if defined(BCM_56370_A0)
   8113     { /* SOC_REG_INT_U0_SW_PROG_INTR_SETr */
   8114         soc_block_list[61],
   8115         soc_iprocreg,
   8116         1,
   8117         0,
   8118         0x1000808c,
   8119         0,
   8120         0,
   8121         1,
   8122         soc_PAXB_0_SW_PROG_INTR_CLRr_fields,
   8123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8124         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8125         -1,
   8126         -1,
   8127         3,
   8128     },
   8129 #endif /* chips */
   8130 
   8131 #if defined(BCM_56370_A0)
   8132     { /* SOC_REG_INT_U0_SW_PROG_INTR_STATUSr */
   8133         soc_block_list[61],
   8134         soc_iprocreg,
   8135         1,
   8136         0,
   8137         0x10008088,
   8138         SOC_REG_FLAG_RO,
   8139         0,
   8140         1,
   8141         soc_MIIM_DMA_CH0_CURR_DST_HOST_ADDRESS_BCM56870_A0r_fields,
   8142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8143         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8144         -1,
   8145         -1,
   8146         3,
   8147     },
   8148 #endif /* chips */
   8149 
   8150 #if defined(BCM_88790_A0)
   8151     { /* SOC_REG_INT_U1_M0SS_CONTROLr */
   8152         soc_block_list[61],
   8153         soc_iprocreg,
   8154         1,
   8155         0,
   8156         0x1318000,
   8157         0,
   8158         0,
   8159         3,
   8160         soc_U1_M0SS_CONTROLr_fields,
   8161         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8162         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   8163         -1,
   8164         -1,
   8165     },
   8166 #endif /* chips */
   8167 
   8168 #if defined(BCM_56370_A0)
   8169     { /* SOC_REG_INT_U1_M0SS_CONTROL_BCM56370_A0r */
   8170         soc_block_list[61],
   8171         soc_iprocreg,
   8172         1,
   8173         0,
   8174         0x10018000,
   8175         0,
   8176         0,
   8177         3,
   8178         soc_U0_M0SS_CONTROL_BCM56870_A0r_fields,
   8179         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8180         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   8181         -1,
   8182         -1,
   8183         3,
   8184     },
   8185 #endif /* chips */
   8186 
   8187 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8188     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8189     { /* SOC_REG_INT_U1_M0SS_CONTROL_BCM56870_A0r */
   8190         soc_block_list[61],
   8191         soc_iprocreg,
   8192         1,
   8193         0,
   8194         0x1318000,
   8195         0,
   8196         0,
   8197         3,
   8198         soc_U0_M0SS_CONTROL_BCM56870_A0r_fields,
   8199         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8200         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   8201         -1,
   8202         -1,
   8203         3,
   8204     },
   8205 #endif /* chips */
   8206 
   8207 #if defined(BCM_88690_A0)
   8208     { /* SOC_REG_INT_U1_M0SS_CONTROL_BCM88690_A0r */
   8209         soc_block_list[61],
   8210         soc_iprocreg,
   8211         1,
   8212         0,
   8213         0x1318000,
   8214         0,
   8215         0,
   8216         3,
   8217         soc_U1_M0SS_CONTROL_BCM88690_A0r_fields,
   8218         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8219         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   8220         -1,
   8221         -1,
   8222     },
   8223 #endif /* chips */
   8224 
   8225 #if defined(BCM_88690_B0)
   8226     { /* SOC_REG_INT_U1_M0SS_CONTROL_BCM88690_B0r */
   8227         soc_block_list[61],
   8228         soc_iprocreg,
   8229         1,
   8230         0,
   8231         0x1318000,
   8232         0,
   8233         0,
   8234         3,
   8235         soc_U1_M0SS_CONTROL_BCM88690_B0r_fields,
   8236         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8237         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   8238         -1,
   8239         -1,
   8240     },
   8241 #endif /* chips */
   8242 
   8243 #if defined(BCM_88790_A0)
   8244     { /* SOC_REG_INT_U1_M0SS_DEBUG_CONTROLr */
   8245         soc_block_list[61],
   8246         soc_iprocreg,
   8247         1,
   8248         0,
   8249         0x131800c,
   8250         0,
   8251         0,
   8252         2,
   8253         soc_U1_M0SS_DEBUG_CONTROLr_fields,
   8254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8255         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   8256         -1,
   8257         -1,
   8258     },
   8259 #endif /* chips */
   8260 
   8261 #if defined(BCM_56370_A0)
   8262     { /* SOC_REG_INT_U1_M0SS_DEBUG_CONTROL_BCM56370_A0r */
   8263         soc_block_list[61],
   8264         soc_iprocreg,
   8265         1,
   8266         0,
   8267         0x1001800c,
   8268         0,
   8269         0,
   8270         2,
   8271         soc_U0_M0SS_DEBUG_CONTROL_BCM56870_A0r_fields,
   8272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8273         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   8274         -1,
   8275         -1,
   8276         3,
   8277     },
   8278 #endif /* chips */
   8279 
   8280 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8281     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8282     { /* SOC_REG_INT_U1_M0SS_DEBUG_CONTROL_BCM56870_A0r */
   8283         soc_block_list[61],
   8284         soc_iprocreg,
   8285         1,
   8286         0,
   8287         0x131800c,
   8288         0,
   8289         0,
   8290         2,
   8291         soc_U0_M0SS_DEBUG_CONTROL_BCM56870_A0r_fields,
   8292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8293         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   8294         -1,
   8295         -1,
   8296         3,
   8297     },
   8298 #endif /* chips */
   8299 
   8300 #if defined(BCM_88690_A0)
   8301     { /* SOC_REG_INT_U1_M0SS_DEBUG_CONTROL_BCM88690_A0r */
   8302         soc_block_list[61],
   8303         soc_iprocreg,
   8304         1,
   8305         0,
   8306         0x131800c,
   8307         0,
   8308         0,
   8309         2,
   8310         soc_U1_M0SS_DEBUG_CONTROL_BCM88690_A0r_fields,
   8311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8312         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   8313         -1,
   8314         -1,
   8315     },
   8316 #endif /* chips */
   8317 
   8318 #if defined(BCM_88690_B0)
   8319     { /* SOC_REG_INT_U1_M0SS_DEBUG_CONTROL_BCM88690_B0r */
   8320         soc_block_list[61],
   8321         soc_iprocreg,
   8322         1,
   8323         0,
   8324         0x131800c,
   8325         0,
   8326         0,
   8327         2,
   8328         soc_U1_M0SS_DEBUG_CONTROL_BCM88690_B0r_fields,
   8329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8330         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   8331         -1,
   8332         -1,
   8333     },
   8334 #endif /* chips */
   8335 
   8336 #if defined(BCM_88790_A0)
   8337     { /* SOC_REG_INT_U1_M0SS_ECC_CTRLr */
   8338         soc_block_list[61],
   8339         soc_iprocreg,
   8340         1,
   8341         0,
   8342         0x1318018,
   8343         0,
   8344         0,
   8345         3,
   8346         soc_U1_M0SS_ECC_CTRLr_fields,
   8347         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8348         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8349         -1,
   8350         -1,
   8351     },
   8352 #endif /* chips */
   8353 
   8354 #if defined(BCM_56370_A0)
   8355     { /* SOC_REG_INT_U1_M0SS_ECC_CTRL_BCM56370_A0r */
   8356         soc_block_list[61],
   8357         soc_iprocreg,
   8358         1,
   8359         0,
   8360         0x10018018,
   8361         0,
   8362         0,
   8363         3,
   8364         soc_U0_M0SSQ_ECC_CTRL_BCM56870_A0r_fields,
   8365         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8366         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8367         -1,
   8368         -1,
   8369         3,
   8370     },
   8371 #endif /* chips */
   8372 
   8373 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8374     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8375     { /* SOC_REG_INT_U1_M0SS_ECC_CTRL_BCM56870_A0r */
   8376         soc_block_list[61],
   8377         soc_iprocreg,
   8378         1,
   8379         0,
   8380         0x1318018,
   8381         0,
   8382         0,
   8383         3,
   8384         soc_U0_M0SSQ_ECC_CTRL_BCM56870_A0r_fields,
   8385         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8386         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8387         -1,
   8388         -1,
   8389         3,
   8390     },
   8391 #endif /* chips */
   8392 
   8393 #if defined(BCM_88690_A0)
   8394     { /* SOC_REG_INT_U1_M0SS_ECC_CTRL_BCM88690_A0r */
   8395         soc_block_list[61],
   8396         soc_iprocreg,
   8397         1,
   8398         0,
   8399         0x1318018,
   8400         0,
   8401         0,
   8402         3,
   8403         soc_U1_M0SS_ECC_CTRL_BCM88690_A0r_fields,
   8404         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8405         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8406         -1,
   8407         -1,
   8408     },
   8409 #endif /* chips */
   8410 
   8411 #if defined(BCM_88690_B0)
   8412     { /* SOC_REG_INT_U1_M0SS_ECC_CTRL_BCM88690_B0r */
   8413         soc_block_list[61],
   8414         soc_iprocreg,
   8415         1,
   8416         0,
   8417         0x1318018,
   8418         0,
   8419         0,
   8420         3,
   8421         soc_U1_M0SS_ECC_CTRL_BCM88690_B0r_fields,
   8422         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8423         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8424         -1,
   8425         -1,
   8426     },
   8427 #endif /* chips */
   8428 
   8429 #if defined(BCM_88790_A0)
   8430     { /* SOC_REG_INT_U1_M0SS_ECC_STATUSr */
   8431         soc_block_list[61],
   8432         soc_iprocreg,
   8433         1,
   8434         0,
   8435         0x131801c,
   8436         0,
   8437         0,
   8438         4,
   8439         soc_U1_M0SS_ECC_STATUSr_fields,
   8440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8441         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8442         -1,
   8443         -1,
   8444     },
   8445 #endif /* chips */
   8446 
   8447 #if defined(BCM_56370_A0)
   8448     { /* SOC_REG_INT_U1_M0SS_ECC_STATUS_BCM56370_A0r */
   8449         soc_block_list[61],
   8450         soc_iprocreg,
   8451         1,
   8452         0,
   8453         0x1001801c,
   8454         0,
   8455         0,
   8456         4,
   8457         soc_U0_M0SS_ECC_STATUS_BCM56870_A0r_fields,
   8458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8459         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8460         -1,
   8461         -1,
   8462         3,
   8463     },
   8464 #endif /* chips */
   8465 
   8466 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8467     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8468     { /* SOC_REG_INT_U1_M0SS_ECC_STATUS_BCM56870_A0r */
   8469         soc_block_list[61],
   8470         soc_iprocreg,
   8471         1,
   8472         0,
   8473         0x131801c,
   8474         0,
   8475         0,
   8476         4,
   8477         soc_U0_M0SS_ECC_STATUS_BCM56870_A0r_fields,
   8478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8479         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8480         -1,
   8481         -1,
   8482         3,
   8483     },
   8484 #endif /* chips */
   8485 
   8486 #if defined(BCM_88690_A0)
   8487     { /* SOC_REG_INT_U1_M0SS_ECC_STATUS_BCM88690_A0r */
   8488         soc_block_list[61],
   8489         soc_iprocreg,
   8490         1,
   8491         0,
   8492         0x131801c,
   8493         0,
   8494         0,
   8495         4,
   8496         soc_U1_M0SS_ECC_STATUS_BCM88690_A0r_fields,
   8497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8498         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8499         -1,
   8500         -1,
   8501     },
   8502 #endif /* chips */
   8503 
   8504 #if defined(BCM_88690_B0)
   8505     { /* SOC_REG_INT_U1_M0SS_ECC_STATUS_BCM88690_B0r */
   8506         soc_block_list[61],
   8507         soc_iprocreg,
   8508         1,
   8509         0,
   8510         0x131801c,
   8511         0,
   8512         0,
   8513         4,
   8514         soc_U1_M0SS_ECC_STATUS_BCM88690_B0r_fields,
   8515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8516         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8517         -1,
   8518         -1,
   8519     },
   8520 #endif /* chips */
   8521 
   8522 #if defined(BCM_88790_A0)
   8523     { /* SOC_REG_INT_U1_M0SS_ECOr */
   8524         soc_block_list[61],
   8525         soc_iprocreg,
   8526         1,
   8527         0,
   8528         0x1318008,
   8529         0,
   8530         0,
   8531         1,
   8532         soc_U1_M0SS_ECOr_fields,
   8533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8534         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   8535         -1,
   8536         -1,
   8537     },
   8538 #endif /* chips */
   8539 
   8540 #if defined(BCM_56370_A0)
   8541     { /* SOC_REG_INT_U1_M0SS_ECO_BCM56370_A0r */
   8542         soc_block_list[61],
   8543         soc_iprocreg,
   8544         1,
   8545         0,
   8546         0x10018008,
   8547         0,
   8548         0,
   8549         1,
   8550         soc_U0_M0SS_ECO_BCM56870_A0r_fields,
   8551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8552         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   8553         -1,
   8554         -1,
   8555         3,
   8556     },
   8557 #endif /* chips */
   8558 
   8559 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8560     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8561     { /* SOC_REG_INT_U1_M0SS_ECO_BCM56870_A0r */
   8562         soc_block_list[61],
   8563         soc_iprocreg,
   8564         1,
   8565         0,
   8566         0x1318008,
   8567         0,
   8568         0,
   8569         1,
   8570         soc_U0_M0SS_ECO_BCM56870_A0r_fields,
   8571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8572         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   8573         -1,
   8574         -1,
   8575         3,
   8576     },
   8577 #endif /* chips */
   8578 
   8579 #if defined(BCM_88690_A0)
   8580     { /* SOC_REG_INT_U1_M0SS_ECO_BCM88690_A0r */
   8581         soc_block_list[61],
   8582         soc_iprocreg,
   8583         1,
   8584         0,
   8585         0x1318008,
   8586         0,
   8587         0,
   8588         1,
   8589         soc_U1_M0SS_ECO_BCM88690_A0r_fields,
   8590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8591         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   8592         -1,
   8593         -1,
   8594     },
   8595 #endif /* chips */
   8596 
   8597 #if defined(BCM_88690_B0)
   8598     { /* SOC_REG_INT_U1_M0SS_ECO_BCM88690_B0r */
   8599         soc_block_list[61],
   8600         soc_iprocreg,
   8601         1,
   8602         0,
   8603         0x1318008,
   8604         0,
   8605         0,
   8606         1,
   8607         soc_U1_M0SS_ECO_BCM88690_B0r_fields,
   8608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8609         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   8610         -1,
   8611         -1,
   8612     },
   8613 #endif /* chips */
   8614 
   8615 #if defined(BCM_88790_A0)
   8616     { /* SOC_REG_INT_U1_M0SS_INTR_127_96r */
   8617         soc_block_list[61],
   8618         soc_iprocreg,
   8619         1,
   8620         0,
   8621         0x1318070,
   8622         SOC_REG_FLAG_RO,
   8623         0,
   8624         1,
   8625         soc_U1_M0SS_INTR_127_96r_fields,
   8626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8627         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8628         -1,
   8629         -1,
   8630     },
   8631 #endif /* chips */
   8632 
   8633 #if defined(BCM_56370_A0)
   8634     { /* SOC_REG_INT_U1_M0SS_INTR_127_96_BCM56370_A0r */
   8635         soc_block_list[61],
   8636         soc_iprocreg,
   8637         1,
   8638         0,
   8639         0x10018070,
   8640         SOC_REG_FLAG_RO,
   8641         0,
   8642         1,
   8643         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   8644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8646         -1,
   8647         -1,
   8648         3,
   8649     },
   8650 #endif /* chips */
   8651 
   8652 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8653     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8654     { /* SOC_REG_INT_U1_M0SS_INTR_127_96_BCM56870_A0r */
   8655         soc_block_list[61],
   8656         soc_iprocreg,
   8657         1,
   8658         0,
   8659         0x1318070,
   8660         SOC_REG_FLAG_RO,
   8661         0,
   8662         1,
   8663         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   8664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8665         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8666         -1,
   8667         -1,
   8668         3,
   8669     },
   8670 #endif /* chips */
   8671 
   8672 #if defined(BCM_88690_A0)
   8673     { /* SOC_REG_INT_U1_M0SS_INTR_127_96_BCM88690_A0r */
   8674         soc_block_list[61],
   8675         soc_iprocreg,
   8676         1,
   8677         0,
   8678         0x1318070,
   8679         SOC_REG_FLAG_RO,
   8680         0,
   8681         1,
   8682         soc_U1_M0SS_INTR_127_96_BCM88690_A0r_fields,
   8683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8685         -1,
   8686         -1,
   8687     },
   8688 #endif /* chips */
   8689 
   8690 #if defined(BCM_88690_B0)
   8691     { /* SOC_REG_INT_U1_M0SS_INTR_127_96_BCM88690_B0r */
   8692         soc_block_list[61],
   8693         soc_iprocreg,
   8694         1,
   8695         0,
   8696         0x1318070,
   8697         SOC_REG_FLAG_RO,
   8698         0,
   8699         1,
   8700         soc_U1_M0SS_INTR_127_96_BCM88690_B0r_fields,
   8701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8703         -1,
   8704         -1,
   8705     },
   8706 #endif /* chips */
   8707 
   8708 #if defined(BCM_88790_A0)
   8709     { /* SOC_REG_INT_U1_M0SS_INTR_159_128r */
   8710         soc_block_list[61],
   8711         soc_iprocreg,
   8712         1,
   8713         0,
   8714         0x1318074,
   8715         SOC_REG_FLAG_RO,
   8716         0,
   8717         1,
   8718         soc_U1_M0SS_INTR_159_128r_fields,
   8719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8720         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8721         -1,
   8722         -1,
   8723     },
   8724 #endif /* chips */
   8725 
   8726 #if defined(BCM_56370_A0)
   8727     { /* SOC_REG_INT_U1_M0SS_INTR_159_128_BCM56370_A0r */
   8728         soc_block_list[61],
   8729         soc_iprocreg,
   8730         1,
   8731         0,
   8732         0x10018074,
   8733         SOC_REG_FLAG_RO,
   8734         0,
   8735         1,
   8736         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   8737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8738         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8739         -1,
   8740         -1,
   8741         3,
   8742     },
   8743 #endif /* chips */
   8744 
   8745 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8746     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8747     { /* SOC_REG_INT_U1_M0SS_INTR_159_128_BCM56870_A0r */
   8748         soc_block_list[61],
   8749         soc_iprocreg,
   8750         1,
   8751         0,
   8752         0x1318074,
   8753         SOC_REG_FLAG_RO,
   8754         0,
   8755         1,
   8756         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   8757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8758         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8759         -1,
   8760         -1,
   8761         3,
   8762     },
   8763 #endif /* chips */
   8764 
   8765 #if defined(BCM_88690_A0)
   8766     { /* SOC_REG_INT_U1_M0SS_INTR_159_128_BCM88690_A0r */
   8767         soc_block_list[61],
   8768         soc_iprocreg,
   8769         1,
   8770         0,
   8771         0x1318074,
   8772         SOC_REG_FLAG_RO,
   8773         0,
   8774         1,
   8775         soc_U1_M0SS_INTR_159_128_BCM88690_A0r_fields,
   8776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8778         -1,
   8779         -1,
   8780     },
   8781 #endif /* chips */
   8782 
   8783 #if defined(BCM_88690_B0)
   8784     { /* SOC_REG_INT_U1_M0SS_INTR_159_128_BCM88690_B0r */
   8785         soc_block_list[61],
   8786         soc_iprocreg,
   8787         1,
   8788         0,
   8789         0x1318074,
   8790         SOC_REG_FLAG_RO,
   8791         0,
   8792         1,
   8793         soc_U1_M0SS_INTR_159_128_BCM88690_B0r_fields,
   8794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8796         -1,
   8797         -1,
   8798     },
   8799 #endif /* chips */
   8800 
   8801 #if defined(BCM_88790_A0)
   8802     { /* SOC_REG_INT_U1_M0SS_INTR_191_160r */
   8803         soc_block_list[61],
   8804         soc_iprocreg,
   8805         1,
   8806         0,
   8807         0x1318078,
   8808         SOC_REG_FLAG_RO,
   8809         0,
   8810         1,
   8811         soc_U1_M0SS_INTR_191_160r_fields,
   8812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8813         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8814         -1,
   8815         -1,
   8816     },
   8817 #endif /* chips */
   8818 
   8819 #if defined(BCM_56370_A0)
   8820     { /* SOC_REG_INT_U1_M0SS_INTR_191_160_BCM56370_A0r */
   8821         soc_block_list[61],
   8822         soc_iprocreg,
   8823         1,
   8824         0,
   8825         0x10018078,
   8826         SOC_REG_FLAG_RO,
   8827         0,
   8828         1,
   8829         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   8830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8831         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8832         -1,
   8833         -1,
   8834         3,
   8835     },
   8836 #endif /* chips */
   8837 
   8838 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8839     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8840     { /* SOC_REG_INT_U1_M0SS_INTR_191_160_BCM56870_A0r */
   8841         soc_block_list[61],
   8842         soc_iprocreg,
   8843         1,
   8844         0,
   8845         0x1318078,
   8846         SOC_REG_FLAG_RO,
   8847         0,
   8848         1,
   8849         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   8850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8851         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8852         -1,
   8853         -1,
   8854         3,
   8855     },
   8856 #endif /* chips */
   8857 
   8858 #if defined(BCM_88690_A0)
   8859     { /* SOC_REG_INT_U1_M0SS_INTR_191_160_BCM88690_A0r */
   8860         soc_block_list[61],
   8861         soc_iprocreg,
   8862         1,
   8863         0,
   8864         0x1318078,
   8865         SOC_REG_FLAG_RO,
   8866         0,
   8867         1,
   8868         soc_U1_M0SS_INTR_191_160_BCM88690_A0r_fields,
   8869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8870         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8871         -1,
   8872         -1,
   8873     },
   8874 #endif /* chips */
   8875 
   8876 #if defined(BCM_88690_B0)
   8877     { /* SOC_REG_INT_U1_M0SS_INTR_191_160_BCM88690_B0r */
   8878         soc_block_list[61],
   8879         soc_iprocreg,
   8880         1,
   8881         0,
   8882         0x1318078,
   8883         SOC_REG_FLAG_RO,
   8884         0,
   8885         1,
   8886         soc_U1_M0SS_INTR_191_160_BCM88690_B0r_fields,
   8887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8889         -1,
   8890         -1,
   8891     },
   8892 #endif /* chips */
   8893 
   8894 #if defined(BCM_88790_A0)
   8895     { /* SOC_REG_INT_U1_M0SS_INTR_223_192r */
   8896         soc_block_list[61],
   8897         soc_iprocreg,
   8898         1,
   8899         0,
   8900         0x131807c,
   8901         SOC_REG_FLAG_RO,
   8902         0,
   8903         1,
   8904         soc_U1_M0SS_INTR_223_192r_fields,
   8905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8906         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8907         -1,
   8908         -1,
   8909     },
   8910 #endif /* chips */
   8911 
   8912 #if defined(BCM_56370_A0)
   8913     { /* SOC_REG_INT_U1_M0SS_INTR_223_192_BCM56370_A0r */
   8914         soc_block_list[61],
   8915         soc_iprocreg,
   8916         1,
   8917         0,
   8918         0x1001807c,
   8919         SOC_REG_FLAG_RO,
   8920         0,
   8921         1,
   8922         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   8923         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8924         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8925         -1,
   8926         -1,
   8927         3,
   8928     },
   8929 #endif /* chips */
   8930 
   8931 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8932     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   8933     { /* SOC_REG_INT_U1_M0SS_INTR_223_192_BCM56870_A0r */
   8934         soc_block_list[61],
   8935         soc_iprocreg,
   8936         1,
   8937         0,
   8938         0x131807c,
   8939         SOC_REG_FLAG_RO,
   8940         0,
   8941         1,
   8942         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   8943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8944         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8945         -1,
   8946         -1,
   8947         3,
   8948     },
   8949 #endif /* chips */
   8950 
   8951 #if defined(BCM_88690_A0)
   8952     { /* SOC_REG_INT_U1_M0SS_INTR_223_192_BCM88690_A0r */
   8953         soc_block_list[61],
   8954         soc_iprocreg,
   8955         1,
   8956         0,
   8957         0x131807c,
   8958         SOC_REG_FLAG_RO,
   8959         0,
   8960         1,
   8961         soc_U1_M0SS_INTR_223_192_BCM88690_A0r_fields,
   8962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8964         -1,
   8965         -1,
   8966     },
   8967 #endif /* chips */
   8968 
   8969 #if defined(BCM_88690_B0)
   8970     { /* SOC_REG_INT_U1_M0SS_INTR_223_192_BCM88690_B0r */
   8971         soc_block_list[61],
   8972         soc_iprocreg,
   8973         1,
   8974         0,
   8975         0x131807c,
   8976         SOC_REG_FLAG_RO,
   8977         0,
   8978         1,
   8979         soc_U1_M0SS_INTR_223_192_BCM88690_B0r_fields,
   8980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8981         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8982         -1,
   8983         -1,
   8984     },
   8985 #endif /* chips */
   8986 
   8987 #if defined(BCM_88790_A0)
   8988     { /* SOC_REG_INT_U1_M0SS_INTR_255_224r */
   8989         soc_block_list[61],
   8990         soc_iprocreg,
   8991         1,
   8992         0,
   8993         0x1318080,
   8994         SOC_REG_FLAG_RO,
   8995         0,
   8996         1,
   8997         soc_U1_M0SS_INTR_255_224r_fields,
   8998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8999         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9000         -1,
   9001         -1,
   9002     },
   9003 #endif /* chips */
   9004 
   9005 #if defined(BCM_56370_A0)
   9006     { /* SOC_REG_INT_U1_M0SS_INTR_255_224_BCM56370_A0r */
   9007         soc_block_list[61],
   9008         soc_iprocreg,
   9009         1,
   9010         0,
   9011         0x10018080,
   9012         SOC_REG_FLAG_RO,
   9013         0,
   9014         1,
   9015         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   9016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9018         -1,
   9019         -1,
   9020         3,
   9021     },
   9022 #endif /* chips */
   9023 
   9024 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9025     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9026     { /* SOC_REG_INT_U1_M0SS_INTR_255_224_BCM56870_A0r */
   9027         soc_block_list[61],
   9028         soc_iprocreg,
   9029         1,
   9030         0,
   9031         0x1318080,
   9032         SOC_REG_FLAG_RO,
   9033         0,
   9034         1,
   9035         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   9036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9037         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9038         -1,
   9039         -1,
   9040         3,
   9041     },
   9042 #endif /* chips */
   9043 
   9044 #if defined(BCM_88690_A0)
   9045     { /* SOC_REG_INT_U1_M0SS_INTR_255_224_BCM88690_A0r */
   9046         soc_block_list[61],
   9047         soc_iprocreg,
   9048         1,
   9049         0,
   9050         0x1318080,
   9051         SOC_REG_FLAG_RO,
   9052         0,
   9053         1,
   9054         soc_U1_M0SS_INTR_255_224_BCM88690_A0r_fields,
   9055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9056         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9057         -1,
   9058         -1,
   9059     },
   9060 #endif /* chips */
   9061 
   9062 #if defined(BCM_88690_B0)
   9063     { /* SOC_REG_INT_U1_M0SS_INTR_255_224_BCM88690_B0r */
   9064         soc_block_list[61],
   9065         soc_iprocreg,
   9066         1,
   9067         0,
   9068         0x1318080,
   9069         SOC_REG_FLAG_RO,
   9070         0,
   9071         1,
   9072         soc_U1_M0SS_INTR_255_224_BCM88690_B0r_fields,
   9073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9074         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9075         -1,
   9076         -1,
   9077     },
   9078 #endif /* chips */
   9079 
   9080 #if defined(BCM_88790_A0)
   9081     { /* SOC_REG_INT_U1_M0SS_INTR_31_0r */
   9082         soc_block_list[61],
   9083         soc_iprocreg,
   9084         1,
   9085         0,
   9086         0x1318064,
   9087         SOC_REG_FLAG_RO,
   9088         0,
   9089         1,
   9090         soc_U1_M0SS_INTR_31_0r_fields,
   9091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9092         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9093         -1,
   9094         -1,
   9095     },
   9096 #endif /* chips */
   9097 
   9098 #if defined(BCM_56370_A0)
   9099     { /* SOC_REG_INT_U1_M0SS_INTR_31_0_BCM56370_A0r */
   9100         soc_block_list[61],
   9101         soc_iprocreg,
   9102         1,
   9103         0,
   9104         0x10018064,
   9105         SOC_REG_FLAG_RO,
   9106         0,
   9107         1,
   9108         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   9109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9110         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9111         -1,
   9112         -1,
   9113         3,
   9114     },
   9115 #endif /* chips */
   9116 
   9117 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9118     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9119     { /* SOC_REG_INT_U1_M0SS_INTR_31_0_BCM56870_A0r */
   9120         soc_block_list[61],
   9121         soc_iprocreg,
   9122         1,
   9123         0,
   9124         0x1318064,
   9125         SOC_REG_FLAG_RO,
   9126         0,
   9127         1,
   9128         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   9129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9130         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9131         -1,
   9132         -1,
   9133         3,
   9134     },
   9135 #endif /* chips */
   9136 
   9137 #if defined(BCM_88690_A0)
   9138     { /* SOC_REG_INT_U1_M0SS_INTR_31_0_BCM88690_A0r */
   9139         soc_block_list[61],
   9140         soc_iprocreg,
   9141         1,
   9142         0,
   9143         0x1318064,
   9144         SOC_REG_FLAG_RO,
   9145         0,
   9146         1,
   9147         soc_U1_M0SS_INTR_31_0_BCM88690_A0r_fields,
   9148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9149         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9150         -1,
   9151         -1,
   9152     },
   9153 #endif /* chips */
   9154 
   9155 #if defined(BCM_88690_B0)
   9156     { /* SOC_REG_INT_U1_M0SS_INTR_31_0_BCM88690_B0r */
   9157         soc_block_list[61],
   9158         soc_iprocreg,
   9159         1,
   9160         0,
   9161         0x1318064,
   9162         SOC_REG_FLAG_RO,
   9163         0,
   9164         1,
   9165         soc_U1_M0SS_INTR_31_0_BCM88690_B0r_fields,
   9166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9168         -1,
   9169         -1,
   9170     },
   9171 #endif /* chips */
   9172 
   9173 #if defined(BCM_88790_A0)
   9174     { /* SOC_REG_INT_U1_M0SS_INTR_63_32r */
   9175         soc_block_list[61],
   9176         soc_iprocreg,
   9177         1,
   9178         0,
   9179         0x1318068,
   9180         SOC_REG_FLAG_RO,
   9181         0,
   9182         1,
   9183         soc_U1_M0SS_INTR_63_32r_fields,
   9184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9186         -1,
   9187         -1,
   9188     },
   9189 #endif /* chips */
   9190 
   9191 #if defined(BCM_56370_A0)
   9192     { /* SOC_REG_INT_U1_M0SS_INTR_63_32_BCM56370_A0r */
   9193         soc_block_list[61],
   9194         soc_iprocreg,
   9195         1,
   9196         0,
   9197         0x10018068,
   9198         SOC_REG_FLAG_RO,
   9199         0,
   9200         1,
   9201         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   9202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9203         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9204         -1,
   9205         -1,
   9206         3,
   9207     },
   9208 #endif /* chips */
   9209 
   9210 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9211     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9212     { /* SOC_REG_INT_U1_M0SS_INTR_63_32_BCM56870_A0r */
   9213         soc_block_list[61],
   9214         soc_iprocreg,
   9215         1,
   9216         0,
   9217         0x1318068,
   9218         SOC_REG_FLAG_RO,
   9219         0,
   9220         1,
   9221         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   9222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9223         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9224         -1,
   9225         -1,
   9226         3,
   9227     },
   9228 #endif /* chips */
   9229 
   9230 #if defined(BCM_88690_A0)
   9231     { /* SOC_REG_INT_U1_M0SS_INTR_63_32_BCM88690_A0r */
   9232         soc_block_list[61],
   9233         soc_iprocreg,
   9234         1,
   9235         0,
   9236         0x1318068,
   9237         SOC_REG_FLAG_RO,
   9238         0,
   9239         1,
   9240         soc_U1_M0SS_INTR_63_32_BCM88690_A0r_fields,
   9241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9242         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9243         -1,
   9244         -1,
   9245     },
   9246 #endif /* chips */
   9247 
   9248 #if defined(BCM_88690_B0)
   9249     { /* SOC_REG_INT_U1_M0SS_INTR_63_32_BCM88690_B0r */
   9250         soc_block_list[61],
   9251         soc_iprocreg,
   9252         1,
   9253         0,
   9254         0x1318068,
   9255         SOC_REG_FLAG_RO,
   9256         0,
   9257         1,
   9258         soc_U1_M0SS_INTR_63_32_BCM88690_B0r_fields,
   9259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9260         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9261         -1,
   9262         -1,
   9263     },
   9264 #endif /* chips */
   9265 
   9266 #if defined(BCM_88790_A0)
   9267     { /* SOC_REG_INT_U1_M0SS_INTR_95_64r */
   9268         soc_block_list[61],
   9269         soc_iprocreg,
   9270         1,
   9271         0,
   9272         0x131806c,
   9273         SOC_REG_FLAG_RO,
   9274         0,
   9275         1,
   9276         soc_U1_M0SS_INTR_95_64r_fields,
   9277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9278         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9279         -1,
   9280         -1,
   9281     },
   9282 #endif /* chips */
   9283 
   9284 #if defined(BCM_56370_A0)
   9285     { /* SOC_REG_INT_U1_M0SS_INTR_95_64_BCM56370_A0r */
   9286         soc_block_list[61],
   9287         soc_iprocreg,
   9288         1,
   9289         0,
   9290         0x1001806c,
   9291         SOC_REG_FLAG_RO,
   9292         0,
   9293         1,
   9294         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   9295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9296         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9297         -1,
   9298         -1,
   9299         3,
   9300     },
   9301 #endif /* chips */
   9302 
   9303 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9304     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9305     { /* SOC_REG_INT_U1_M0SS_INTR_95_64_BCM56870_A0r */
   9306         soc_block_list[61],
   9307         soc_iprocreg,
   9308         1,
   9309         0,
   9310         0x131806c,
   9311         SOC_REG_FLAG_RO,
   9312         0,
   9313         1,
   9314         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
   9315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9316         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9317         -1,
   9318         -1,
   9319         3,
   9320     },
   9321 #endif /* chips */
   9322 
   9323 #if defined(BCM_88690_A0)
   9324     { /* SOC_REG_INT_U1_M0SS_INTR_95_64_BCM88690_A0r */
   9325         soc_block_list[61],
   9326         soc_iprocreg,
   9327         1,
   9328         0,
   9329         0x131806c,
   9330         SOC_REG_FLAG_RO,
   9331         0,
   9332         1,
   9333         soc_U1_M0SS_INTR_95_64_BCM88690_A0r_fields,
   9334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9335         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9336         -1,
   9337         -1,
   9338     },
   9339 #endif /* chips */
   9340 
   9341 #if defined(BCM_88690_B0)
   9342     { /* SOC_REG_INT_U1_M0SS_INTR_95_64_BCM88690_B0r */
   9343         soc_block_list[61],
   9344         soc_iprocreg,
   9345         1,
   9346         0,
   9347         0x131806c,
   9348         SOC_REG_FLAG_RO,
   9349         0,
   9350         1,
   9351         soc_U1_M0SS_INTR_95_64_BCM88690_B0r_fields,
   9352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9353         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9354         -1,
   9355         -1,
   9356     },
   9357 #endif /* chips */
   9358 
   9359 #if defined(BCM_88790_A0)
   9360     { /* SOC_REG_INT_U1_M0SS_INTR_CONTROLr */
   9361         soc_block_list[61],
   9362         soc_iprocreg,
   9363         1,
   9364         0,
   9365         0x1318004,
   9366         0,
   9367         0,
   9368         3,
   9369         soc_U1_M0SS_INTR_CONTROLr_fields,
   9370         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
   9371         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   9372         -1,
   9373         -1,
   9374     },
   9375 #endif /* chips */
   9376 
   9377 #if defined(BCM_56370_A0)
   9378     { /* SOC_REG_INT_U1_M0SS_INTR_CONTROL_BCM56370_A0r */
   9379         soc_block_list[61],
   9380         soc_iprocreg,
   9381         1,
   9382         0,
   9383         0x10018004,
   9384         0,
   9385         0,
   9386         3,
   9387         soc_U0_M0SS_INTR_CONTROL_BCM56870_A0r_fields,
   9388         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
   9389         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   9390         -1,
   9391         -1,
   9392         3,
   9393     },
   9394 #endif /* chips */
   9395 
   9396 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9397     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9398     { /* SOC_REG_INT_U1_M0SS_INTR_CONTROL_BCM56870_A0r */
   9399         soc_block_list[61],
   9400         soc_iprocreg,
   9401         1,
   9402         0,
   9403         0x1318004,
   9404         0,
   9405         0,
   9406         3,
   9407         soc_U0_M0SS_INTR_CONTROL_BCM56870_A0r_fields,
   9408         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
   9409         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   9410         -1,
   9411         -1,
   9412         3,
   9413     },
   9414 #endif /* chips */
   9415 
   9416 #if defined(BCM_88690_A0)
   9417     { /* SOC_REG_INT_U1_M0SS_INTR_CONTROL_BCM88690_A0r */
   9418         soc_block_list[61],
   9419         soc_iprocreg,
   9420         1,
   9421         0,
   9422         0x1318004,
   9423         0,
   9424         0,
   9425         3,
   9426         soc_U1_M0SS_INTR_CONTROL_BCM88690_A0r_fields,
   9427         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
   9428         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   9429         -1,
   9430         -1,
   9431     },
   9432 #endif /* chips */
   9433 
   9434 #if defined(BCM_88690_B0)
   9435     { /* SOC_REG_INT_U1_M0SS_INTR_CONTROL_BCM88690_B0r */
   9436         soc_block_list[61],
   9437         soc_iprocreg,
   9438         1,
   9439         0,
   9440         0x1318004,
   9441         0,
   9442         0,
   9443         3,
   9444         soc_U1_M0SS_INTR_CONTROL_BCM88690_B0r_fields,
   9445         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
   9446         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   9447         -1,
   9448         -1,
   9449     },
   9450 #endif /* chips */
   9451 
   9452 #if defined(BCM_88790_A0)
   9453     { /* SOC_REG_INT_U1_M0SS_INTR_ENABLEr */
   9454         soc_block_list[61],
   9455         soc_iprocreg,
   9456         1,
   9457         0,
   9458         0x1318020,
   9459         0,
   9460         0,
   9461         2,
   9462         soc_U1_M0SS_INTR_ENABLEr_fields,
   9463         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   9464         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   9465         -1,
   9466         -1,
   9467     },
   9468 #endif /* chips */
   9469 
   9470 #if defined(BCM_56370_A0)
   9471     { /* SOC_REG_INT_U1_M0SS_INTR_ENABLE_BCM56370_A0r */
   9472         soc_block_list[61],
   9473         soc_iprocreg,
   9474         1,
   9475         0,
   9476         0x10018020,
   9477         0,
   9478         0,
   9479         2,
   9480         soc_U0_M0SSQ_INTR_ENABLE_BCM56870_A0r_fields,
   9481         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   9482         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   9483         -1,
   9484         -1,
   9485         3,
   9486     },
   9487 #endif /* chips */
   9488 
   9489 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9490     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9491     { /* SOC_REG_INT_U1_M0SS_INTR_ENABLE_BCM56870_A0r */
   9492         soc_block_list[61],
   9493         soc_iprocreg,
   9494         1,
   9495         0,
   9496         0x1318020,
   9497         0,
   9498         0,
   9499         2,
   9500         soc_U0_M0SSQ_INTR_ENABLE_BCM56870_A0r_fields,
   9501         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   9502         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   9503         -1,
   9504         -1,
   9505         3,
   9506     },
   9507 #endif /* chips */
   9508 
   9509 #if defined(BCM_88690_A0)
   9510     { /* SOC_REG_INT_U1_M0SS_INTR_ENABLE_BCM88690_A0r */
   9511         soc_block_list[61],
   9512         soc_iprocreg,
   9513         1,
   9514         0,
   9515         0x1318020,
   9516         0,
   9517         0,
   9518         2,
   9519         soc_U1_M0SS_INTR_ENABLE_BCM88690_A0r_fields,
   9520         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   9521         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   9522         -1,
   9523         -1,
   9524     },
   9525 #endif /* chips */
   9526 
   9527 #if defined(BCM_88690_B0)
   9528     { /* SOC_REG_INT_U1_M0SS_INTR_ENABLE_BCM88690_B0r */
   9529         soc_block_list[61],
   9530         soc_iprocreg,
   9531         1,
   9532         0,
   9533         0x1318020,
   9534         0,
   9535         0,
   9536         2,
   9537         soc_U1_M0SS_INTR_ENABLE_BCM88690_B0r_fields,
   9538         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   9539         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   9540         -1,
   9541         -1,
   9542     },
   9543 #endif /* chips */
   9544 
   9545 #if defined(BCM_88790_A0)
   9546     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_127_96r */
   9547         soc_block_list[61],
   9548         soc_iprocreg,
   9549         1,
   9550         0,
   9551         0x1318050,
   9552         0,
   9553         0,
   9554         1,
   9555         soc_U1_M0SS_INTR_MASK_127_96r_fields,
   9556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9557         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9558         -1,
   9559         -1,
   9560     },
   9561 #endif /* chips */
   9562 
   9563 #if defined(BCM_56370_A0)
   9564     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_127_96_BCM56370_A0r */
   9565         soc_block_list[61],
   9566         soc_iprocreg,
   9567         1,
   9568         0,
   9569         0x10018050,
   9570         0,
   9571         0,
   9572         1,
   9573         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   9574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9575         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9576         -1,
   9577         -1,
   9578         3,
   9579     },
   9580 #endif /* chips */
   9581 
   9582 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9583     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9584     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_127_96_BCM56870_A0r */
   9585         soc_block_list[61],
   9586         soc_iprocreg,
   9587         1,
   9588         0,
   9589         0x1318050,
   9590         0,
   9591         0,
   9592         1,
   9593         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   9594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9596         -1,
   9597         -1,
   9598         3,
   9599     },
   9600 #endif /* chips */
   9601 
   9602 #if defined(BCM_88690_A0)
   9603     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_127_96_BCM88690_A0r */
   9604         soc_block_list[61],
   9605         soc_iprocreg,
   9606         1,
   9607         0,
   9608         0x1318050,
   9609         0,
   9610         0,
   9611         1,
   9612         soc_U1_M0SS_INTR_MASK_127_96_BCM88690_A0r_fields,
   9613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9614         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9615         -1,
   9616         -1,
   9617     },
   9618 #endif /* chips */
   9619 
   9620 #if defined(BCM_88690_B0)
   9621     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_127_96_BCM88690_B0r */
   9622         soc_block_list[61],
   9623         soc_iprocreg,
   9624         1,
   9625         0,
   9626         0x1318050,
   9627         0,
   9628         0,
   9629         1,
   9630         soc_U1_M0SS_INTR_MASK_127_96_BCM88690_B0r_fields,
   9631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9632         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9633         -1,
   9634         -1,
   9635     },
   9636 #endif /* chips */
   9637 
   9638 #if defined(BCM_88790_A0)
   9639     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_159_128r */
   9640         soc_block_list[61],
   9641         soc_iprocreg,
   9642         1,
   9643         0,
   9644         0x1318054,
   9645         0,
   9646         0,
   9647         1,
   9648         soc_U1_M0SS_INTR_MASK_159_128r_fields,
   9649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9651         -1,
   9652         -1,
   9653     },
   9654 #endif /* chips */
   9655 
   9656 #if defined(BCM_56370_A0)
   9657     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_159_128_BCM56370_A0r */
   9658         soc_block_list[61],
   9659         soc_iprocreg,
   9660         1,
   9661         0,
   9662         0x10018054,
   9663         0,
   9664         0,
   9665         1,
   9666         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   9667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9668         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9669         -1,
   9670         -1,
   9671         3,
   9672     },
   9673 #endif /* chips */
   9674 
   9675 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9676     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9677     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_159_128_BCM56870_A0r */
   9678         soc_block_list[61],
   9679         soc_iprocreg,
   9680         1,
   9681         0,
   9682         0x1318054,
   9683         0,
   9684         0,
   9685         1,
   9686         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   9687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9689         -1,
   9690         -1,
   9691         3,
   9692     },
   9693 #endif /* chips */
   9694 
   9695 #if defined(BCM_88690_A0)
   9696     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_159_128_BCM88690_A0r */
   9697         soc_block_list[61],
   9698         soc_iprocreg,
   9699         1,
   9700         0,
   9701         0x1318054,
   9702         0,
   9703         0,
   9704         1,
   9705         soc_U1_M0SS_INTR_MASK_159_128_BCM88690_A0r_fields,
   9706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9708         -1,
   9709         -1,
   9710     },
   9711 #endif /* chips */
   9712 
   9713 #if defined(BCM_88690_B0)
   9714     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_159_128_BCM88690_B0r */
   9715         soc_block_list[61],
   9716         soc_iprocreg,
   9717         1,
   9718         0,
   9719         0x1318054,
   9720         0,
   9721         0,
   9722         1,
   9723         soc_U1_M0SS_INTR_MASK_159_128_BCM88690_B0r_fields,
   9724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9726         -1,
   9727         -1,
   9728     },
   9729 #endif /* chips */
   9730 
   9731 #if defined(BCM_88790_A0)
   9732     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_191_160r */
   9733         soc_block_list[61],
   9734         soc_iprocreg,
   9735         1,
   9736         0,
   9737         0x1318058,
   9738         0,
   9739         0,
   9740         1,
   9741         soc_U1_M0SS_INTR_MASK_191_160r_fields,
   9742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9744         -1,
   9745         -1,
   9746     },
   9747 #endif /* chips */
   9748 
   9749 #if defined(BCM_56370_A0)
   9750     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_191_160_BCM56370_A0r */
   9751         soc_block_list[61],
   9752         soc_iprocreg,
   9753         1,
   9754         0,
   9755         0x10018058,
   9756         0,
   9757         0,
   9758         1,
   9759         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   9760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9762         -1,
   9763         -1,
   9764         3,
   9765     },
   9766 #endif /* chips */
   9767 
   9768 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9769     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9770     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_191_160_BCM56870_A0r */
   9771         soc_block_list[61],
   9772         soc_iprocreg,
   9773         1,
   9774         0,
   9775         0x1318058,
   9776         0,
   9777         0,
   9778         1,
   9779         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   9780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9781         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9782         -1,
   9783         -1,
   9784         3,
   9785     },
   9786 #endif /* chips */
   9787 
   9788 #if defined(BCM_88690_A0)
   9789     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_191_160_BCM88690_A0r */
   9790         soc_block_list[61],
   9791         soc_iprocreg,
   9792         1,
   9793         0,
   9794         0x1318058,
   9795         0,
   9796         0,
   9797         1,
   9798         soc_U1_M0SS_INTR_MASK_191_160_BCM88690_A0r_fields,
   9799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9800         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9801         -1,
   9802         -1,
   9803     },
   9804 #endif /* chips */
   9805 
   9806 #if defined(BCM_88690_B0)
   9807     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_191_160_BCM88690_B0r */
   9808         soc_block_list[61],
   9809         soc_iprocreg,
   9810         1,
   9811         0,
   9812         0x1318058,
   9813         0,
   9814         0,
   9815         1,
   9816         soc_U1_M0SS_INTR_MASK_191_160_BCM88690_B0r_fields,
   9817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9818         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9819         -1,
   9820         -1,
   9821     },
   9822 #endif /* chips */
   9823 
   9824 #if defined(BCM_88790_A0)
   9825     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_223_192r */
   9826         soc_block_list[61],
   9827         soc_iprocreg,
   9828         1,
   9829         0,
   9830         0x131805c,
   9831         0,
   9832         0,
   9833         1,
   9834         soc_U1_M0SS_INTR_MASK_223_192r_fields,
   9835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9837         -1,
   9838         -1,
   9839     },
   9840 #endif /* chips */
   9841 
   9842 #if defined(BCM_56370_A0)
   9843     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_223_192_BCM56370_A0r */
   9844         soc_block_list[61],
   9845         soc_iprocreg,
   9846         1,
   9847         0,
   9848         0x1001805c,
   9849         0,
   9850         0,
   9851         1,
   9852         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   9853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9854         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9855         -1,
   9856         -1,
   9857         3,
   9858     },
   9859 #endif /* chips */
   9860 
   9861 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9862     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9863     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_223_192_BCM56870_A0r */
   9864         soc_block_list[61],
   9865         soc_iprocreg,
   9866         1,
   9867         0,
   9868         0x131805c,
   9869         0,
   9870         0,
   9871         1,
   9872         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   9873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9874         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9875         -1,
   9876         -1,
   9877         3,
   9878     },
   9879 #endif /* chips */
   9880 
   9881 #if defined(BCM_88690_A0)
   9882     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_223_192_BCM88690_A0r */
   9883         soc_block_list[61],
   9884         soc_iprocreg,
   9885         1,
   9886         0,
   9887         0x131805c,
   9888         0,
   9889         0,
   9890         1,
   9891         soc_U1_M0SS_INTR_MASK_223_192_BCM88690_A0r_fields,
   9892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9893         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9894         -1,
   9895         -1,
   9896     },
   9897 #endif /* chips */
   9898 
   9899 #if defined(BCM_88690_B0)
   9900     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_223_192_BCM88690_B0r */
   9901         soc_block_list[61],
   9902         soc_iprocreg,
   9903         1,
   9904         0,
   9905         0x131805c,
   9906         0,
   9907         0,
   9908         1,
   9909         soc_U1_M0SS_INTR_MASK_223_192_BCM88690_B0r_fields,
   9910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9912         -1,
   9913         -1,
   9914     },
   9915 #endif /* chips */
   9916 
   9917 #if defined(BCM_88790_A0)
   9918     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_255_224r */
   9919         soc_block_list[61],
   9920         soc_iprocreg,
   9921         1,
   9922         0,
   9923         0x1318060,
   9924         0,
   9925         0,
   9926         1,
   9927         soc_U1_M0SS_INTR_MASK_255_224r_fields,
   9928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9929         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9930         -1,
   9931         -1,
   9932     },
   9933 #endif /* chips */
   9934 
   9935 #if defined(BCM_56370_A0)
   9936     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_255_224_BCM56370_A0r */
   9937         soc_block_list[61],
   9938         soc_iprocreg,
   9939         1,
   9940         0,
   9941         0x10018060,
   9942         0,
   9943         0,
   9944         1,
   9945         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   9946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9947         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9948         -1,
   9949         -1,
   9950         3,
   9951     },
   9952 #endif /* chips */
   9953 
   9954 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9955     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9956     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_255_224_BCM56870_A0r */
   9957         soc_block_list[61],
   9958         soc_iprocreg,
   9959         1,
   9960         0,
   9961         0x1318060,
   9962         0,
   9963         0,
   9964         1,
   9965         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
   9966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9967         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9968         -1,
   9969         -1,
   9970         3,
   9971     },
   9972 #endif /* chips */
   9973 
   9974 #if defined(BCM_88690_A0)
   9975     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_255_224_BCM88690_A0r */
   9976         soc_block_list[61],
   9977         soc_iprocreg,
   9978         1,
   9979         0,
   9980         0x1318060,
   9981         0,
   9982         0,
   9983         1,
   9984         soc_U1_M0SS_INTR_MASK_255_224_BCM88690_A0r_fields,
   9985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9986         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9987         -1,
   9988         -1,
   9989     },
   9990 #endif /* chips */
   9991 
   9992 #if defined(BCM_88690_B0)
   9993     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_255_224_BCM88690_B0r */
   9994         soc_block_list[61],
   9995         soc_iprocreg,
   9996         1,
   9997         0,
   9998         0x1318060,
   9999         0,
  10000         0,
  10001         1,
  10002         soc_U1_M0SS_INTR_MASK_255_224_BCM88690_B0r_fields,
  10003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10004         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10005         -1,
  10006         -1,
  10007     },
  10008 #endif /* chips */
  10009 
  10010 #if defined(BCM_88790_A0)
  10011     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_31_0r */
  10012         soc_block_list[61],
  10013         soc_iprocreg,
  10014         1,
  10015         0,
  10016         0x1318044,
  10017         0,
  10018         0,
  10019         1,
  10020         soc_U1_M0SS_INTR_MASK_31_0r_fields,
  10021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10023         -1,
  10024         -1,
  10025     },
  10026 #endif /* chips */
  10027 
  10028 #if defined(BCM_56370_A0)
  10029     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_31_0_BCM56370_A0r */
  10030         soc_block_list[61],
  10031         soc_iprocreg,
  10032         1,
  10033         0,
  10034         0x10018044,
  10035         0,
  10036         0,
  10037         1,
  10038         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  10039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10040         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10041         -1,
  10042         -1,
  10043         3,
  10044     },
  10045 #endif /* chips */
  10046 
  10047 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10048     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10049     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_31_0_BCM56870_A0r */
  10050         soc_block_list[61],
  10051         soc_iprocreg,
  10052         1,
  10053         0,
  10054         0x1318044,
  10055         0,
  10056         0,
  10057         1,
  10058         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  10059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10060         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10061         -1,
  10062         -1,
  10063         3,
  10064     },
  10065 #endif /* chips */
  10066 
  10067 #if defined(BCM_88690_A0)
  10068     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_31_0_BCM88690_A0r */
  10069         soc_block_list[61],
  10070         soc_iprocreg,
  10071         1,
  10072         0,
  10073         0x1318044,
  10074         0,
  10075         0,
  10076         1,
  10077         soc_U1_M0SS_INTR_MASK_31_0_BCM88690_A0r_fields,
  10078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10079         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10080         -1,
  10081         -1,
  10082     },
  10083 #endif /* chips */
  10084 
  10085 #if defined(BCM_88690_B0)
  10086     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_31_0_BCM88690_B0r */
  10087         soc_block_list[61],
  10088         soc_iprocreg,
  10089         1,
  10090         0,
  10091         0x1318044,
  10092         0,
  10093         0,
  10094         1,
  10095         soc_U1_M0SS_INTR_MASK_31_0_BCM88690_B0r_fields,
  10096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10098         -1,
  10099         -1,
  10100     },
  10101 #endif /* chips */
  10102 
  10103 #if defined(BCM_88790_A0)
  10104     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_63_32r */
  10105         soc_block_list[61],
  10106         soc_iprocreg,
  10107         1,
  10108         0,
  10109         0x1318048,
  10110         0,
  10111         0,
  10112         1,
  10113         soc_U1_M0SS_INTR_MASK_63_32r_fields,
  10114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10116         -1,
  10117         -1,
  10118     },
  10119 #endif /* chips */
  10120 
  10121 #if defined(BCM_56370_A0)
  10122     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_63_32_BCM56370_A0r */
  10123         soc_block_list[61],
  10124         soc_iprocreg,
  10125         1,
  10126         0,
  10127         0x10018048,
  10128         0,
  10129         0,
  10130         1,
  10131         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  10132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10133         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10134         -1,
  10135         -1,
  10136         3,
  10137     },
  10138 #endif /* chips */
  10139 
  10140 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10141     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10142     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_63_32_BCM56870_A0r */
  10143         soc_block_list[61],
  10144         soc_iprocreg,
  10145         1,
  10146         0,
  10147         0x1318048,
  10148         0,
  10149         0,
  10150         1,
  10151         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  10152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10153         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10154         -1,
  10155         -1,
  10156         3,
  10157     },
  10158 #endif /* chips */
  10159 
  10160 #if defined(BCM_88690_A0)
  10161     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_63_32_BCM88690_A0r */
  10162         soc_block_list[61],
  10163         soc_iprocreg,
  10164         1,
  10165         0,
  10166         0x1318048,
  10167         0,
  10168         0,
  10169         1,
  10170         soc_U1_M0SS_INTR_MASK_63_32_BCM88690_A0r_fields,
  10171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10172         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10173         -1,
  10174         -1,
  10175     },
  10176 #endif /* chips */
  10177 
  10178 #if defined(BCM_88690_B0)
  10179     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_63_32_BCM88690_B0r */
  10180         soc_block_list[61],
  10181         soc_iprocreg,
  10182         1,
  10183         0,
  10184         0x1318048,
  10185         0,
  10186         0,
  10187         1,
  10188         soc_U1_M0SS_INTR_MASK_63_32_BCM88690_B0r_fields,
  10189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10190         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10191         -1,
  10192         -1,
  10193     },
  10194 #endif /* chips */
  10195 
  10196 #if defined(BCM_88790_A0)
  10197     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_95_64r */
  10198         soc_block_list[61],
  10199         soc_iprocreg,
  10200         1,
  10201         0,
  10202         0x131804c,
  10203         0,
  10204         0,
  10205         1,
  10206         soc_U1_M0SS_INTR_MASK_95_64r_fields,
  10207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10208         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10209         -1,
  10210         -1,
  10211     },
  10212 #endif /* chips */
  10213 
  10214 #if defined(BCM_56370_A0)
  10215     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_95_64_BCM56370_A0r */
  10216         soc_block_list[61],
  10217         soc_iprocreg,
  10218         1,
  10219         0,
  10220         0x1001804c,
  10221         0,
  10222         0,
  10223         1,
  10224         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  10225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10226         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10227         -1,
  10228         -1,
  10229         3,
  10230     },
  10231 #endif /* chips */
  10232 
  10233 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10234     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10235     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_95_64_BCM56870_A0r */
  10236         soc_block_list[61],
  10237         soc_iprocreg,
  10238         1,
  10239         0,
  10240         0x131804c,
  10241         0,
  10242         0,
  10243         1,
  10244         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  10245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10246         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10247         -1,
  10248         -1,
  10249         3,
  10250     },
  10251 #endif /* chips */
  10252 
  10253 #if defined(BCM_88690_A0)
  10254     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_95_64_BCM88690_A0r */
  10255         soc_block_list[61],
  10256         soc_iprocreg,
  10257         1,
  10258         0,
  10259         0x131804c,
  10260         0,
  10261         0,
  10262         1,
  10263         soc_U1_M0SS_INTR_MASK_95_64_BCM88690_A0r_fields,
  10264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10265         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10266         -1,
  10267         -1,
  10268     },
  10269 #endif /* chips */
  10270 
  10271 #if defined(BCM_88690_B0)
  10272     { /* SOC_REG_INT_U1_M0SS_INTR_MASK_95_64_BCM88690_B0r */
  10273         soc_block_list[61],
  10274         soc_iprocreg,
  10275         1,
  10276         0,
  10277         0x131804c,
  10278         0,
  10279         0,
  10280         1,
  10281         soc_U1_M0SS_INTR_MASK_95_64_BCM88690_B0r_fields,
  10282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10283         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10284         -1,
  10285         -1,
  10286     },
  10287 #endif /* chips */
  10288 
  10289 #if defined(BCM_88790_A0)
  10290     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_127_96r */
  10291         soc_block_list[61],
  10292         soc_iprocreg,
  10293         1,
  10294         0,
  10295         0x1318030,
  10296         SOC_REG_FLAG_RO,
  10297         0,
  10298         1,
  10299         soc_U1_M0SS_RAW_INTR_127_96r_fields,
  10300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10301         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10302         -1,
  10303         -1,
  10304     },
  10305 #endif /* chips */
  10306 
  10307 #if defined(BCM_56370_A0)
  10308     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_127_96_BCM56370_A0r */
  10309         soc_block_list[61],
  10310         soc_iprocreg,
  10311         1,
  10312         0,
  10313         0x10018030,
  10314         SOC_REG_FLAG_RO,
  10315         0,
  10316         1,
  10317         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10319         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10320         -1,
  10321         -1,
  10322         3,
  10323     },
  10324 #endif /* chips */
  10325 
  10326 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10327     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10328     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_127_96_BCM56870_A0r */
  10329         soc_block_list[61],
  10330         soc_iprocreg,
  10331         1,
  10332         0,
  10333         0x1318030,
  10334         SOC_REG_FLAG_RO,
  10335         0,
  10336         1,
  10337         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10339         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10340         -1,
  10341         -1,
  10342         3,
  10343     },
  10344 #endif /* chips */
  10345 
  10346 #if defined(BCM_88690_A0)
  10347     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_127_96_BCM88690_A0r */
  10348         soc_block_list[61],
  10349         soc_iprocreg,
  10350         1,
  10351         0,
  10352         0x1318030,
  10353         SOC_REG_FLAG_RO,
  10354         0,
  10355         1,
  10356         soc_U1_M0SS_RAW_INTR_127_96_BCM88690_A0r_fields,
  10357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10358         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10359         -1,
  10360         -1,
  10361     },
  10362 #endif /* chips */
  10363 
  10364 #if defined(BCM_88690_B0)
  10365     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_127_96_BCM88690_B0r */
  10366         soc_block_list[61],
  10367         soc_iprocreg,
  10368         1,
  10369         0,
  10370         0x1318030,
  10371         SOC_REG_FLAG_RO,
  10372         0,
  10373         1,
  10374         soc_U1_M0SS_RAW_INTR_127_96_BCM88690_B0r_fields,
  10375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10376         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10377         -1,
  10378         -1,
  10379     },
  10380 #endif /* chips */
  10381 
  10382 #if defined(BCM_88790_A0)
  10383     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_159_128r */
  10384         soc_block_list[61],
  10385         soc_iprocreg,
  10386         1,
  10387         0,
  10388         0x1318034,
  10389         SOC_REG_FLAG_RO,
  10390         0,
  10391         1,
  10392         soc_U1_M0SS_RAW_INTR_159_128r_fields,
  10393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10394         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10395         -1,
  10396         -1,
  10397     },
  10398 #endif /* chips */
  10399 
  10400 #if defined(BCM_56370_A0)
  10401     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_159_128_BCM56370_A0r */
  10402         soc_block_list[61],
  10403         soc_iprocreg,
  10404         1,
  10405         0,
  10406         0x10018034,
  10407         SOC_REG_FLAG_RO,
  10408         0,
  10409         1,
  10410         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10412         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10413         -1,
  10414         -1,
  10415         3,
  10416     },
  10417 #endif /* chips */
  10418 
  10419 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10420     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10421     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_159_128_BCM56870_A0r */
  10422         soc_block_list[61],
  10423         soc_iprocreg,
  10424         1,
  10425         0,
  10426         0x1318034,
  10427         SOC_REG_FLAG_RO,
  10428         0,
  10429         1,
  10430         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10433         -1,
  10434         -1,
  10435         3,
  10436     },
  10437 #endif /* chips */
  10438 
  10439 #if defined(BCM_88690_A0)
  10440     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_159_128_BCM88690_A0r */
  10441         soc_block_list[61],
  10442         soc_iprocreg,
  10443         1,
  10444         0,
  10445         0x1318034,
  10446         SOC_REG_FLAG_RO,
  10447         0,
  10448         1,
  10449         soc_U1_M0SS_RAW_INTR_159_128_BCM88690_A0r_fields,
  10450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10451         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10452         -1,
  10453         -1,
  10454     },
  10455 #endif /* chips */
  10456 
  10457 #if defined(BCM_88690_B0)
  10458     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_159_128_BCM88690_B0r */
  10459         soc_block_list[61],
  10460         soc_iprocreg,
  10461         1,
  10462         0,
  10463         0x1318034,
  10464         SOC_REG_FLAG_RO,
  10465         0,
  10466         1,
  10467         soc_U1_M0SS_RAW_INTR_159_128_BCM88690_B0r_fields,
  10468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10469         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10470         -1,
  10471         -1,
  10472     },
  10473 #endif /* chips */
  10474 
  10475 #if defined(BCM_88790_A0)
  10476     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_191_160r */
  10477         soc_block_list[61],
  10478         soc_iprocreg,
  10479         1,
  10480         0,
  10481         0x1318038,
  10482         SOC_REG_FLAG_RO,
  10483         0,
  10484         1,
  10485         soc_U1_M0SS_RAW_INTR_191_160r_fields,
  10486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10487         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10488         -1,
  10489         -1,
  10490     },
  10491 #endif /* chips */
  10492 
  10493 #if defined(BCM_56370_A0)
  10494     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_191_160_BCM56370_A0r */
  10495         soc_block_list[61],
  10496         soc_iprocreg,
  10497         1,
  10498         0,
  10499         0x10018038,
  10500         SOC_REG_FLAG_RO,
  10501         0,
  10502         1,
  10503         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10505         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10506         -1,
  10507         -1,
  10508         3,
  10509     },
  10510 #endif /* chips */
  10511 
  10512 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10513     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10514     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_191_160_BCM56870_A0r */
  10515         soc_block_list[61],
  10516         soc_iprocreg,
  10517         1,
  10518         0,
  10519         0x1318038,
  10520         SOC_REG_FLAG_RO,
  10521         0,
  10522         1,
  10523         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10526         -1,
  10527         -1,
  10528         3,
  10529     },
  10530 #endif /* chips */
  10531 
  10532 #if defined(BCM_88690_A0)
  10533     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_191_160_BCM88690_A0r */
  10534         soc_block_list[61],
  10535         soc_iprocreg,
  10536         1,
  10537         0,
  10538         0x1318038,
  10539         SOC_REG_FLAG_RO,
  10540         0,
  10541         1,
  10542         soc_U1_M0SS_RAW_INTR_191_160_BCM88690_A0r_fields,
  10543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10544         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10545         -1,
  10546         -1,
  10547     },
  10548 #endif /* chips */
  10549 
  10550 #if defined(BCM_88690_B0)
  10551     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_191_160_BCM88690_B0r */
  10552         soc_block_list[61],
  10553         soc_iprocreg,
  10554         1,
  10555         0,
  10556         0x1318038,
  10557         SOC_REG_FLAG_RO,
  10558         0,
  10559         1,
  10560         soc_U1_M0SS_RAW_INTR_191_160_BCM88690_B0r_fields,
  10561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10562         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10563         -1,
  10564         -1,
  10565     },
  10566 #endif /* chips */
  10567 
  10568 #if defined(BCM_88790_A0)
  10569     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_223_192r */
  10570         soc_block_list[61],
  10571         soc_iprocreg,
  10572         1,
  10573         0,
  10574         0x131803c,
  10575         SOC_REG_FLAG_RO,
  10576         0,
  10577         1,
  10578         soc_U1_M0SS_RAW_INTR_223_192r_fields,
  10579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10580         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10581         -1,
  10582         -1,
  10583     },
  10584 #endif /* chips */
  10585 
  10586 #if defined(BCM_56370_A0)
  10587     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_223_192_BCM56370_A0r */
  10588         soc_block_list[61],
  10589         soc_iprocreg,
  10590         1,
  10591         0,
  10592         0x1001803c,
  10593         SOC_REG_FLAG_RO,
  10594         0,
  10595         1,
  10596         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10598         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10599         -1,
  10600         -1,
  10601         3,
  10602     },
  10603 #endif /* chips */
  10604 
  10605 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10606     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10607     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_223_192_BCM56870_A0r */
  10608         soc_block_list[61],
  10609         soc_iprocreg,
  10610         1,
  10611         0,
  10612         0x131803c,
  10613         SOC_REG_FLAG_RO,
  10614         0,
  10615         1,
  10616         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10618         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10619         -1,
  10620         -1,
  10621         3,
  10622     },
  10623 #endif /* chips */
  10624 
  10625 #if defined(BCM_88690_A0)
  10626     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_223_192_BCM88690_A0r */
  10627         soc_block_list[61],
  10628         soc_iprocreg,
  10629         1,
  10630         0,
  10631         0x131803c,
  10632         SOC_REG_FLAG_RO,
  10633         0,
  10634         1,
  10635         soc_U1_M0SS_RAW_INTR_223_192_BCM88690_A0r_fields,
  10636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10637         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10638         -1,
  10639         -1,
  10640     },
  10641 #endif /* chips */
  10642 
  10643 #if defined(BCM_88690_B0)
  10644     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_223_192_BCM88690_B0r */
  10645         soc_block_list[61],
  10646         soc_iprocreg,
  10647         1,
  10648         0,
  10649         0x131803c,
  10650         SOC_REG_FLAG_RO,
  10651         0,
  10652         1,
  10653         soc_U1_M0SS_RAW_INTR_223_192_BCM88690_B0r_fields,
  10654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10655         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10656         -1,
  10657         -1,
  10658     },
  10659 #endif /* chips */
  10660 
  10661 #if defined(BCM_88790_A0)
  10662     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_255_224r */
  10663         soc_block_list[61],
  10664         soc_iprocreg,
  10665         1,
  10666         0,
  10667         0x1318040,
  10668         SOC_REG_FLAG_RO,
  10669         0,
  10670         1,
  10671         soc_U1_M0SS_RAW_INTR_255_224r_fields,
  10672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10673         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10674         -1,
  10675         -1,
  10676     },
  10677 #endif /* chips */
  10678 
  10679 #if defined(BCM_56370_A0)
  10680     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_255_224_BCM56370_A0r */
  10681         soc_block_list[61],
  10682         soc_iprocreg,
  10683         1,
  10684         0,
  10685         0x10018040,
  10686         SOC_REG_FLAG_RO,
  10687         0,
  10688         1,
  10689         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10691         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10692         -1,
  10693         -1,
  10694         3,
  10695     },
  10696 #endif /* chips */
  10697 
  10698 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10699     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10700     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_255_224_BCM56870_A0r */
  10701         soc_block_list[61],
  10702         soc_iprocreg,
  10703         1,
  10704         0,
  10705         0x1318040,
  10706         SOC_REG_FLAG_RO,
  10707         0,
  10708         1,
  10709         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10711         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10712         -1,
  10713         -1,
  10714         3,
  10715     },
  10716 #endif /* chips */
  10717 
  10718 #if defined(BCM_88690_A0)
  10719     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_255_224_BCM88690_A0r */
  10720         soc_block_list[61],
  10721         soc_iprocreg,
  10722         1,
  10723         0,
  10724         0x1318040,
  10725         SOC_REG_FLAG_RO,
  10726         0,
  10727         1,
  10728         soc_U1_M0SS_RAW_INTR_255_224_BCM88690_A0r_fields,
  10729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10730         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10731         -1,
  10732         -1,
  10733     },
  10734 #endif /* chips */
  10735 
  10736 #if defined(BCM_88690_B0)
  10737     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_255_224_BCM88690_B0r */
  10738         soc_block_list[61],
  10739         soc_iprocreg,
  10740         1,
  10741         0,
  10742         0x1318040,
  10743         SOC_REG_FLAG_RO,
  10744         0,
  10745         1,
  10746         soc_U1_M0SS_RAW_INTR_255_224_BCM88690_B0r_fields,
  10747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10748         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10749         -1,
  10750         -1,
  10751     },
  10752 #endif /* chips */
  10753 
  10754 #if defined(BCM_88790_A0)
  10755     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_31_0r */
  10756         soc_block_list[61],
  10757         soc_iprocreg,
  10758         1,
  10759         0,
  10760         0x1318024,
  10761         SOC_REG_FLAG_RO,
  10762         0,
  10763         1,
  10764         soc_U1_M0SS_RAW_INTR_31_0r_fields,
  10765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10766         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10767         -1,
  10768         -1,
  10769     },
  10770 #endif /* chips */
  10771 
  10772 #if defined(BCM_56370_A0)
  10773     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_31_0_BCM56370_A0r */
  10774         soc_block_list[61],
  10775         soc_iprocreg,
  10776         1,
  10777         0,
  10778         0x10018024,
  10779         SOC_REG_FLAG_RO,
  10780         0,
  10781         1,
  10782         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10784         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10785         -1,
  10786         -1,
  10787         3,
  10788     },
  10789 #endif /* chips */
  10790 
  10791 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10792     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10793     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_31_0_BCM56870_A0r */
  10794         soc_block_list[61],
  10795         soc_iprocreg,
  10796         1,
  10797         0,
  10798         0x1318024,
  10799         SOC_REG_FLAG_RO,
  10800         0,
  10801         1,
  10802         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10804         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10805         -1,
  10806         -1,
  10807         3,
  10808     },
  10809 #endif /* chips */
  10810 
  10811 #if defined(BCM_88690_A0)
  10812     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_31_0_BCM88690_A0r */
  10813         soc_block_list[61],
  10814         soc_iprocreg,
  10815         1,
  10816         0,
  10817         0x1318024,
  10818         SOC_REG_FLAG_RO,
  10819         0,
  10820         1,
  10821         soc_U1_M0SS_RAW_INTR_31_0_BCM88690_A0r_fields,
  10822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10823         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10824         -1,
  10825         -1,
  10826     },
  10827 #endif /* chips */
  10828 
  10829 #if defined(BCM_88690_B0)
  10830     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_31_0_BCM88690_B0r */
  10831         soc_block_list[61],
  10832         soc_iprocreg,
  10833         1,
  10834         0,
  10835         0x1318024,
  10836         SOC_REG_FLAG_RO,
  10837         0,
  10838         1,
  10839         soc_U1_M0SS_RAW_INTR_31_0_BCM88690_B0r_fields,
  10840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10842         -1,
  10843         -1,
  10844     },
  10845 #endif /* chips */
  10846 
  10847 #if defined(BCM_88790_A0)
  10848     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_63_32r */
  10849         soc_block_list[61],
  10850         soc_iprocreg,
  10851         1,
  10852         0,
  10853         0x1318028,
  10854         SOC_REG_FLAG_RO,
  10855         0,
  10856         1,
  10857         soc_U1_M0SS_RAW_INTR_63_32r_fields,
  10858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10859         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10860         -1,
  10861         -1,
  10862     },
  10863 #endif /* chips */
  10864 
  10865 #if defined(BCM_56370_A0)
  10866     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_63_32_BCM56370_A0r */
  10867         soc_block_list[61],
  10868         soc_iprocreg,
  10869         1,
  10870         0,
  10871         0x10018028,
  10872         SOC_REG_FLAG_RO,
  10873         0,
  10874         1,
  10875         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10878         -1,
  10879         -1,
  10880         3,
  10881     },
  10882 #endif /* chips */
  10883 
  10884 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10885     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10886     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_63_32_BCM56870_A0r */
  10887         soc_block_list[61],
  10888         soc_iprocreg,
  10889         1,
  10890         0,
  10891         0x1318028,
  10892         SOC_REG_FLAG_RO,
  10893         0,
  10894         1,
  10895         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10898         -1,
  10899         -1,
  10900         3,
  10901     },
  10902 #endif /* chips */
  10903 
  10904 #if defined(BCM_88690_A0)
  10905     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_63_32_BCM88690_A0r */
  10906         soc_block_list[61],
  10907         soc_iprocreg,
  10908         1,
  10909         0,
  10910         0x1318028,
  10911         SOC_REG_FLAG_RO,
  10912         0,
  10913         1,
  10914         soc_U1_M0SS_RAW_INTR_63_32_BCM88690_A0r_fields,
  10915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10916         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10917         -1,
  10918         -1,
  10919     },
  10920 #endif /* chips */
  10921 
  10922 #if defined(BCM_88690_B0)
  10923     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_63_32_BCM88690_B0r */
  10924         soc_block_list[61],
  10925         soc_iprocreg,
  10926         1,
  10927         0,
  10928         0x1318028,
  10929         SOC_REG_FLAG_RO,
  10930         0,
  10931         1,
  10932         soc_U1_M0SS_RAW_INTR_63_32_BCM88690_B0r_fields,
  10933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10934         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10935         -1,
  10936         -1,
  10937     },
  10938 #endif /* chips */
  10939 
  10940 #if defined(BCM_88790_A0)
  10941     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_95_64r */
  10942         soc_block_list[61],
  10943         soc_iprocreg,
  10944         1,
  10945         0,
  10946         0x131802c,
  10947         SOC_REG_FLAG_RO,
  10948         0,
  10949         1,
  10950         soc_U1_M0SS_RAW_INTR_95_64r_fields,
  10951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10952         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10953         -1,
  10954         -1,
  10955     },
  10956 #endif /* chips */
  10957 
  10958 #if defined(BCM_56370_A0)
  10959     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_95_64_BCM56370_A0r */
  10960         soc_block_list[61],
  10961         soc_iprocreg,
  10962         1,
  10963         0,
  10964         0x1001802c,
  10965         SOC_REG_FLAG_RO,
  10966         0,
  10967         1,
  10968         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10970         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10971         -1,
  10972         -1,
  10973         3,
  10974     },
  10975 #endif /* chips */
  10976 
  10977 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10978     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  10979     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_95_64_BCM56870_A0r */
  10980         soc_block_list[61],
  10981         soc_iprocreg,
  10982         1,
  10983         0,
  10984         0x131802c,
  10985         SOC_REG_FLAG_RO,
  10986         0,
  10987         1,
  10988         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  10989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10990         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10991         -1,
  10992         -1,
  10993         3,
  10994     },
  10995 #endif /* chips */
  10996 
  10997 #if defined(BCM_88690_A0)
  10998     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_95_64_BCM88690_A0r */
  10999         soc_block_list[61],
  11000         soc_iprocreg,
  11001         1,
  11002         0,
  11003         0x131802c,
  11004         SOC_REG_FLAG_RO,
  11005         0,
  11006         1,
  11007         soc_U1_M0SS_RAW_INTR_95_64_BCM88690_A0r_fields,
  11008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11009         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11010         -1,
  11011         -1,
  11012     },
  11013 #endif /* chips */
  11014 
  11015 #if defined(BCM_88690_B0)
  11016     { /* SOC_REG_INT_U1_M0SS_RAW_INTR_95_64_BCM88690_B0r */
  11017         soc_block_list[61],
  11018         soc_iprocreg,
  11019         1,
  11020         0,
  11021         0x131802c,
  11022         SOC_REG_FLAG_RO,
  11023         0,
  11024         1,
  11025         soc_U1_M0SS_RAW_INTR_95_64_BCM88690_B0r_fields,
  11026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11028         -1,
  11029         -1,
  11030     },
  11031 #endif /* chips */
  11032 
  11033 #if defined(BCM_88790_A0)
  11034     { /* SOC_REG_INT_U1_M0SS_STATUSr */
  11035         soc_block_list[61],
  11036         soc_iprocreg,
  11037         1,
  11038         0,
  11039         0x1318010,
  11040         0,
  11041         0,
  11042         10,
  11043         soc_U1_M0SS_STATUSr_fields,
  11044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11045         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
  11046         -1,
  11047         -1,
  11048     },
  11049 #endif /* chips */
  11050 
  11051 #if defined(BCM_56370_A0)
  11052     { /* SOC_REG_INT_U1_M0SS_STATUS_BCM56370_A0r */
  11053         soc_block_list[61],
  11054         soc_iprocreg,
  11055         1,
  11056         0,
  11057         0x10018010,
  11058         0,
  11059         0,
  11060         10,
  11061         soc_U0_M0SS_STATUS_BCM56870_A0r_fields,
  11062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11063         SOC_RESET_MASK_DEC(0xffff001f, 0x00000000)
  11064         -1,
  11065         -1,
  11066         3,
  11067     },
  11068 #endif /* chips */
  11069 
  11070 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11071     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11072     { /* SOC_REG_INT_U1_M0SS_STATUS_BCM56870_A0r */
  11073         soc_block_list[61],
  11074         soc_iprocreg,
  11075         1,
  11076         0,
  11077         0x1318010,
  11078         0,
  11079         0,
  11080         10,
  11081         soc_U0_M0SS_STATUS_BCM56870_A0r_fields,
  11082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11083         SOC_RESET_MASK_DEC(0xffff001f, 0x00000000)
  11084         -1,
  11085         -1,
  11086         3,
  11087     },
  11088 #endif /* chips */
  11089 
  11090 #if defined(BCM_88690_A0)
  11091     { /* SOC_REG_INT_U1_M0SS_STATUS_BCM88690_A0r */
  11092         soc_block_list[61],
  11093         soc_iprocreg,
  11094         1,
  11095         0,
  11096         0x1318010,
  11097         0,
  11098         0,
  11099         10,
  11100         soc_U1_M0SS_STATUS_BCM88690_A0r_fields,
  11101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11102         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
  11103         -1,
  11104         -1,
  11105     },
  11106 #endif /* chips */
  11107 
  11108 #if defined(BCM_88690_B0)
  11109     { /* SOC_REG_INT_U1_M0SS_STATUS_BCM88690_B0r */
  11110         soc_block_list[61],
  11111         soc_iprocreg,
  11112         1,
  11113         0,
  11114         0x1318010,
  11115         0,
  11116         0,
  11117         10,
  11118         soc_U1_M0SS_STATUS_BCM88690_B0r_fields,
  11119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11120         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
  11121         -1,
  11122         -1,
  11123     },
  11124 #endif /* chips */
  11125 
  11126 #if defined(BCM_88790_A0)
  11127     { /* SOC_REG_INT_U1_M0SS_TCM_CTRLr */
  11128         soc_block_list[61],
  11129         soc_iprocreg,
  11130         1,
  11131         0,
  11132         0x1318014,
  11133         0,
  11134         0,
  11135         1,
  11136         soc_U1_M0SS_TCM_CTRLr_fields,
  11137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11138         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  11139         -1,
  11140         -1,
  11141     },
  11142 #endif /* chips */
  11143 
  11144 #if defined(BCM_56370_A0)
  11145     { /* SOC_REG_INT_U1_M0SS_TCM_CTRL_BCM56370_A0r */
  11146         soc_block_list[61],
  11147         soc_iprocreg,
  11148         1,
  11149         0,
  11150         0x10018014,
  11151         0,
  11152         0,
  11153         1,
  11154         soc_U0_M0SS_TCM_CTRL_BCM56870_A0r_fields,
  11155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11156         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11157         -1,
  11158         -1,
  11159         3,
  11160     },
  11161 #endif /* chips */
  11162 
  11163 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11164     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11165     { /* SOC_REG_INT_U1_M0SS_TCM_CTRL_BCM56870_A0r */
  11166         soc_block_list[61],
  11167         soc_iprocreg,
  11168         1,
  11169         0,
  11170         0x1318014,
  11171         0,
  11172         0,
  11173         1,
  11174         soc_U0_M0SS_TCM_CTRL_BCM56870_A0r_fields,
  11175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11176         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11177         -1,
  11178         -1,
  11179         3,
  11180     },
  11181 #endif /* chips */
  11182 
  11183 #if defined(BCM_88690_A0)
  11184     { /* SOC_REG_INT_U1_M0SS_TCM_CTRL_BCM88690_A0r */
  11185         soc_block_list[61],
  11186         soc_iprocreg,
  11187         1,
  11188         0,
  11189         0x1318014,
  11190         0,
  11191         0,
  11192         1,
  11193         soc_U1_M0SS_TCM_CTRL_BCM88690_A0r_fields,
  11194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11195         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  11196         -1,
  11197         -1,
  11198     },
  11199 #endif /* chips */
  11200 
  11201 #if defined(BCM_88690_B0)
  11202     { /* SOC_REG_INT_U1_M0SS_TCM_CTRL_BCM88690_B0r */
  11203         soc_block_list[61],
  11204         soc_iprocreg,
  11205         1,
  11206         0,
  11207         0x1318014,
  11208         0,
  11209         0,
  11210         1,
  11211         soc_U1_M0SS_TCM_CTRL_BCM88690_B0r_fields,
  11212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11213         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  11214         -1,
  11215         -1,
  11216     },
  11217 #endif /* chips */
  11218 
  11219 #if defined(BCM_56370_A0)
  11220     { /* SOC_REG_INT_U1_SW_PROG_INTR_CLRr */
  11221         soc_block_list[61],
  11222         soc_iprocreg,
  11223         1,
  11224         0,
  11225         0x10018090,
  11226         0,
  11227         0,
  11228         1,
  11229         soc_PAXB_0_SW_PROG_INTR_CLRr_fields,
  11230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11231         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11232         -1,
  11233         -1,
  11234         3,
  11235     },
  11236 #endif /* chips */
  11237 
  11238 #if defined(BCM_56370_A0)
  11239     { /* SOC_REG_INT_U1_SW_PROG_INTR_ENABLEr */
  11240         soc_block_list[61],
  11241         soc_iprocreg,
  11242         1,
  11243         0,
  11244         0x10018084,
  11245         0,
  11246         0,
  11247         1,
  11248         soc_MIIM_DMA_CH0_DST_HOST_ADDRESS_BCM56870_A0r_fields,
  11249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11250         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11251         -1,
  11252         -1,
  11253         3,
  11254     },
  11255 #endif /* chips */
  11256 
  11257 #if defined(BCM_56370_A0)
  11258     { /* SOC_REG_INT_U1_SW_PROG_INTR_SETr */
  11259         soc_block_list[61],
  11260         soc_iprocreg,
  11261         1,
  11262         0,
  11263         0x1001808c,
  11264         0,
  11265         0,
  11266         1,
  11267         soc_PAXB_0_SW_PROG_INTR_CLRr_fields,
  11268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11269         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11270         -1,
  11271         -1,
  11272         3,
  11273     },
  11274 #endif /* chips */
  11275 
  11276 #if defined(BCM_56370_A0)
  11277     { /* SOC_REG_INT_U1_SW_PROG_INTR_STATUSr */
  11278         soc_block_list[61],
  11279         soc_iprocreg,
  11280         1,
  11281         0,
  11282         0x10018088,
  11283         SOC_REG_FLAG_RO,
  11284         0,
  11285         1,
  11286         soc_MIIM_DMA_CH0_CURR_DST_HOST_ADDRESS_BCM56870_A0r_fields,
  11287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11288         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11289         -1,
  11290         -1,
  11291         3,
  11292     },
  11293 #endif /* chips */
  11294 
  11295 #if defined(BCM_88790_A0)
  11296     { /* SOC_REG_INT_U2_M0SS_CONTROLr */
  11297         soc_block_list[61],
  11298         soc_iprocreg,
  11299         1,
  11300         0,
  11301         0x1328000,
  11302         0,
  11303         0,
  11304         3,
  11305         soc_U2_M0SS_CONTROLr_fields,
  11306         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  11307         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  11308         -1,
  11309         -1,
  11310     },
  11311 #endif /* chips */
  11312 
  11313 #if defined(BCM_56370_A0)
  11314     { /* SOC_REG_INT_U2_M0SS_CONTROL_BCM56370_A0r */
  11315         soc_block_list[61],
  11316         soc_iprocreg,
  11317         1,
  11318         0,
  11319         0x10028000,
  11320         0,
  11321         0,
  11322         3,
  11323         soc_U0_M0SS_CONTROL_BCM56870_A0r_fields,
  11324         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  11325         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  11326         -1,
  11327         -1,
  11328         3,
  11329     },
  11330 #endif /* chips */
  11331 
  11332 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11333     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11334     { /* SOC_REG_INT_U2_M0SS_CONTROL_BCM56870_A0r */
  11335         soc_block_list[61],
  11336         soc_iprocreg,
  11337         1,
  11338         0,
  11339         0x1328000,
  11340         0,
  11341         0,
  11342         3,
  11343         soc_U0_M0SS_CONTROL_BCM56870_A0r_fields,
  11344         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  11345         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  11346         -1,
  11347         -1,
  11348         3,
  11349     },
  11350 #endif /* chips */
  11351 
  11352 #if defined(BCM_88690_A0)
  11353     { /* SOC_REG_INT_U2_M0SS_CONTROL_BCM88690_A0r */
  11354         soc_block_list[61],
  11355         soc_iprocreg,
  11356         1,
  11357         0,
  11358         0x1328000,
  11359         0,
  11360         0,
  11361         3,
  11362         soc_U2_M0SS_CONTROL_BCM88690_A0r_fields,
  11363         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  11364         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  11365         -1,
  11366         -1,
  11367     },
  11368 #endif /* chips */
  11369 
  11370 #if defined(BCM_88690_B0)
  11371     { /* SOC_REG_INT_U2_M0SS_CONTROL_BCM88690_B0r */
  11372         soc_block_list[61],
  11373         soc_iprocreg,
  11374         1,
  11375         0,
  11376         0x1328000,
  11377         0,
  11378         0,
  11379         3,
  11380         soc_U2_M0SS_CONTROL_BCM88690_B0r_fields,
  11381         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  11382         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  11383         -1,
  11384         -1,
  11385     },
  11386 #endif /* chips */
  11387 
  11388 #if defined(BCM_88790_A0)
  11389     { /* SOC_REG_INT_U2_M0SS_DEBUG_CONTROLr */
  11390         soc_block_list[61],
  11391         soc_iprocreg,
  11392         1,
  11393         0,
  11394         0x132800c,
  11395         0,
  11396         0,
  11397         2,
  11398         soc_U2_M0SS_DEBUG_CONTROLr_fields,
  11399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11400         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11401         -1,
  11402         -1,
  11403     },
  11404 #endif /* chips */
  11405 
  11406 #if defined(BCM_56370_A0)
  11407     { /* SOC_REG_INT_U2_M0SS_DEBUG_CONTROL_BCM56370_A0r */
  11408         soc_block_list[61],
  11409         soc_iprocreg,
  11410         1,
  11411         0,
  11412         0x1002800c,
  11413         0,
  11414         0,
  11415         2,
  11416         soc_U0_M0SS_DEBUG_CONTROL_BCM56870_A0r_fields,
  11417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11418         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11419         -1,
  11420         -1,
  11421         3,
  11422     },
  11423 #endif /* chips */
  11424 
  11425 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11426     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11427     { /* SOC_REG_INT_U2_M0SS_DEBUG_CONTROL_BCM56870_A0r */
  11428         soc_block_list[61],
  11429         soc_iprocreg,
  11430         1,
  11431         0,
  11432         0x132800c,
  11433         0,
  11434         0,
  11435         2,
  11436         soc_U0_M0SS_DEBUG_CONTROL_BCM56870_A0r_fields,
  11437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11438         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11439         -1,
  11440         -1,
  11441         3,
  11442     },
  11443 #endif /* chips */
  11444 
  11445 #if defined(BCM_88690_A0)
  11446     { /* SOC_REG_INT_U2_M0SS_DEBUG_CONTROL_BCM88690_A0r */
  11447         soc_block_list[61],
  11448         soc_iprocreg,
  11449         1,
  11450         0,
  11451         0x132800c,
  11452         0,
  11453         0,
  11454         2,
  11455         soc_U2_M0SS_DEBUG_CONTROL_BCM88690_A0r_fields,
  11456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11457         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11458         -1,
  11459         -1,
  11460     },
  11461 #endif /* chips */
  11462 
  11463 #if defined(BCM_88690_B0)
  11464     { /* SOC_REG_INT_U2_M0SS_DEBUG_CONTROL_BCM88690_B0r */
  11465         soc_block_list[61],
  11466         soc_iprocreg,
  11467         1,
  11468         0,
  11469         0x132800c,
  11470         0,
  11471         0,
  11472         2,
  11473         soc_U2_M0SS_DEBUG_CONTROL_BCM88690_B0r_fields,
  11474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11475         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11476         -1,
  11477         -1,
  11478     },
  11479 #endif /* chips */
  11480 
  11481 #if defined(BCM_88790_A0)
  11482     { /* SOC_REG_INT_U2_M0SS_ECC_CTRLr */
  11483         soc_block_list[61],
  11484         soc_iprocreg,
  11485         1,
  11486         0,
  11487         0x1328018,
  11488         0,
  11489         0,
  11490         3,
  11491         soc_U2_M0SS_ECC_CTRLr_fields,
  11492         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  11493         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  11494         -1,
  11495         -1,
  11496     },
  11497 #endif /* chips */
  11498 
  11499 #if defined(BCM_56370_A0)
  11500     { /* SOC_REG_INT_U2_M0SS_ECC_CTRL_BCM56370_A0r */
  11501         soc_block_list[61],
  11502         soc_iprocreg,
  11503         1,
  11504         0,
  11505         0x10028018,
  11506         0,
  11507         0,
  11508         3,
  11509         soc_U0_M0SSQ_ECC_CTRL_BCM56870_A0r_fields,
  11510         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  11511         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  11512         -1,
  11513         -1,
  11514         3,
  11515     },
  11516 #endif /* chips */
  11517 
  11518 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11519     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11520     { /* SOC_REG_INT_U2_M0SS_ECC_CTRL_BCM56870_A0r */
  11521         soc_block_list[61],
  11522         soc_iprocreg,
  11523         1,
  11524         0,
  11525         0x1328018,
  11526         0,
  11527         0,
  11528         3,
  11529         soc_U0_M0SSQ_ECC_CTRL_BCM56870_A0r_fields,
  11530         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  11531         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  11532         -1,
  11533         -1,
  11534         3,
  11535     },
  11536 #endif /* chips */
  11537 
  11538 #if defined(BCM_88690_A0)
  11539     { /* SOC_REG_INT_U2_M0SS_ECC_CTRL_BCM88690_A0r */
  11540         soc_block_list[61],
  11541         soc_iprocreg,
  11542         1,
  11543         0,
  11544         0x1328018,
  11545         0,
  11546         0,
  11547         3,
  11548         soc_U2_M0SS_ECC_CTRL_BCM88690_A0r_fields,
  11549         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  11550         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  11551         -1,
  11552         -1,
  11553     },
  11554 #endif /* chips */
  11555 
  11556 #if defined(BCM_88690_B0)
  11557     { /* SOC_REG_INT_U2_M0SS_ECC_CTRL_BCM88690_B0r */
  11558         soc_block_list[61],
  11559         soc_iprocreg,
  11560         1,
  11561         0,
  11562         0x1328018,
  11563         0,
  11564         0,
  11565         3,
  11566         soc_U2_M0SS_ECC_CTRL_BCM88690_B0r_fields,
  11567         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  11568         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  11569         -1,
  11570         -1,
  11571     },
  11572 #endif /* chips */
  11573 
  11574 #if defined(BCM_88790_A0)
  11575     { /* SOC_REG_INT_U2_M0SS_ECC_STATUSr */
  11576         soc_block_list[61],
  11577         soc_iprocreg,
  11578         1,
  11579         0,
  11580         0x132801c,
  11581         0,
  11582         0,
  11583         4,
  11584         soc_U2_M0SS_ECC_STATUSr_fields,
  11585         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11586         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  11587         -1,
  11588         -1,
  11589     },
  11590 #endif /* chips */
  11591 
  11592 #if defined(BCM_56370_A0)
  11593     { /* SOC_REG_INT_U2_M0SS_ECC_STATUS_BCM56370_A0r */
  11594         soc_block_list[61],
  11595         soc_iprocreg,
  11596         1,
  11597         0,
  11598         0x1002801c,
  11599         0,
  11600         0,
  11601         4,
  11602         soc_U0_M0SS_ECC_STATUS_BCM56870_A0r_fields,
  11603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11604         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  11605         -1,
  11606         -1,
  11607         3,
  11608     },
  11609 #endif /* chips */
  11610 
  11611 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11612     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11613     { /* SOC_REG_INT_U2_M0SS_ECC_STATUS_BCM56870_A0r */
  11614         soc_block_list[61],
  11615         soc_iprocreg,
  11616         1,
  11617         0,
  11618         0x132801c,
  11619         0,
  11620         0,
  11621         4,
  11622         soc_U0_M0SS_ECC_STATUS_BCM56870_A0r_fields,
  11623         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11624         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  11625         -1,
  11626         -1,
  11627         3,
  11628     },
  11629 #endif /* chips */
  11630 
  11631 #if defined(BCM_88690_A0)
  11632     { /* SOC_REG_INT_U2_M0SS_ECC_STATUS_BCM88690_A0r */
  11633         soc_block_list[61],
  11634         soc_iprocreg,
  11635         1,
  11636         0,
  11637         0x132801c,
  11638         0,
  11639         0,
  11640         4,
  11641         soc_U2_M0SS_ECC_STATUS_BCM88690_A0r_fields,
  11642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11643         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  11644         -1,
  11645         -1,
  11646     },
  11647 #endif /* chips */
  11648 
  11649 #if defined(BCM_88690_B0)
  11650     { /* SOC_REG_INT_U2_M0SS_ECC_STATUS_BCM88690_B0r */
  11651         soc_block_list[61],
  11652         soc_iprocreg,
  11653         1,
  11654         0,
  11655         0x132801c,
  11656         0,
  11657         0,
  11658         4,
  11659         soc_U2_M0SS_ECC_STATUS_BCM88690_B0r_fields,
  11660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11661         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  11662         -1,
  11663         -1,
  11664     },
  11665 #endif /* chips */
  11666 
  11667 #if defined(BCM_88790_A0)
  11668     { /* SOC_REG_INT_U2_M0SS_ECOr */
  11669         soc_block_list[61],
  11670         soc_iprocreg,
  11671         1,
  11672         0,
  11673         0x1328008,
  11674         0,
  11675         0,
  11676         1,
  11677         soc_U2_M0SS_ECOr_fields,
  11678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11679         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11680         -1,
  11681         -1,
  11682     },
  11683 #endif /* chips */
  11684 
  11685 #if defined(BCM_56370_A0)
  11686     { /* SOC_REG_INT_U2_M0SS_ECO_BCM56370_A0r */
  11687         soc_block_list[61],
  11688         soc_iprocreg,
  11689         1,
  11690         0,
  11691         0x10028008,
  11692         0,
  11693         0,
  11694         1,
  11695         soc_U0_M0SS_ECO_BCM56870_A0r_fields,
  11696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11697         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11698         -1,
  11699         -1,
  11700         3,
  11701     },
  11702 #endif /* chips */
  11703 
  11704 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11705     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11706     { /* SOC_REG_INT_U2_M0SS_ECO_BCM56870_A0r */
  11707         soc_block_list[61],
  11708         soc_iprocreg,
  11709         1,
  11710         0,
  11711         0x1328008,
  11712         0,
  11713         0,
  11714         1,
  11715         soc_U0_M0SS_ECO_BCM56870_A0r_fields,
  11716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11717         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11718         -1,
  11719         -1,
  11720         3,
  11721     },
  11722 #endif /* chips */
  11723 
  11724 #if defined(BCM_88690_A0)
  11725     { /* SOC_REG_INT_U2_M0SS_ECO_BCM88690_A0r */
  11726         soc_block_list[61],
  11727         soc_iprocreg,
  11728         1,
  11729         0,
  11730         0x1328008,
  11731         0,
  11732         0,
  11733         1,
  11734         soc_U2_M0SS_ECO_BCM88690_A0r_fields,
  11735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11736         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11737         -1,
  11738         -1,
  11739     },
  11740 #endif /* chips */
  11741 
  11742 #if defined(BCM_88690_B0)
  11743     { /* SOC_REG_INT_U2_M0SS_ECO_BCM88690_B0r */
  11744         soc_block_list[61],
  11745         soc_iprocreg,
  11746         1,
  11747         0,
  11748         0x1328008,
  11749         0,
  11750         0,
  11751         1,
  11752         soc_U2_M0SS_ECO_BCM88690_B0r_fields,
  11753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11754         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  11755         -1,
  11756         -1,
  11757     },
  11758 #endif /* chips */
  11759 
  11760 #if defined(BCM_88790_A0)
  11761     { /* SOC_REG_INT_U2_M0SS_INTR_127_96r */
  11762         soc_block_list[61],
  11763         soc_iprocreg,
  11764         1,
  11765         0,
  11766         0x1328070,
  11767         SOC_REG_FLAG_RO,
  11768         0,
  11769         1,
  11770         soc_U2_M0SS_INTR_127_96r_fields,
  11771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11772         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11773         -1,
  11774         -1,
  11775     },
  11776 #endif /* chips */
  11777 
  11778 #if defined(BCM_56370_A0)
  11779     { /* SOC_REG_INT_U2_M0SS_INTR_127_96_BCM56370_A0r */
  11780         soc_block_list[61],
  11781         soc_iprocreg,
  11782         1,
  11783         0,
  11784         0x10028070,
  11785         SOC_REG_FLAG_RO,
  11786         0,
  11787         1,
  11788         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  11789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11790         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11791         -1,
  11792         -1,
  11793         3,
  11794     },
  11795 #endif /* chips */
  11796 
  11797 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11798     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11799     { /* SOC_REG_INT_U2_M0SS_INTR_127_96_BCM56870_A0r */
  11800         soc_block_list[61],
  11801         soc_iprocreg,
  11802         1,
  11803         0,
  11804         0x1328070,
  11805         SOC_REG_FLAG_RO,
  11806         0,
  11807         1,
  11808         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  11809         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11810         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11811         -1,
  11812         -1,
  11813         3,
  11814     },
  11815 #endif /* chips */
  11816 
  11817 #if defined(BCM_88690_A0)
  11818     { /* SOC_REG_INT_U2_M0SS_INTR_127_96_BCM88690_A0r */
  11819         soc_block_list[61],
  11820         soc_iprocreg,
  11821         1,
  11822         0,
  11823         0x1328070,
  11824         SOC_REG_FLAG_RO,
  11825         0,
  11826         1,
  11827         soc_U2_M0SS_INTR_127_96_BCM88690_A0r_fields,
  11828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11829         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11830         -1,
  11831         -1,
  11832     },
  11833 #endif /* chips */
  11834 
  11835 #if defined(BCM_88690_B0)
  11836     { /* SOC_REG_INT_U2_M0SS_INTR_127_96_BCM88690_B0r */
  11837         soc_block_list[61],
  11838         soc_iprocreg,
  11839         1,
  11840         0,
  11841         0x1328070,
  11842         SOC_REG_FLAG_RO,
  11843         0,
  11844         1,
  11845         soc_U2_M0SS_INTR_127_96_BCM88690_B0r_fields,
  11846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11847         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11848         -1,
  11849         -1,
  11850     },
  11851 #endif /* chips */
  11852 
  11853 #if defined(BCM_88790_A0)
  11854     { /* SOC_REG_INT_U2_M0SS_INTR_159_128r */
  11855         soc_block_list[61],
  11856         soc_iprocreg,
  11857         1,
  11858         0,
  11859         0x1328074,
  11860         SOC_REG_FLAG_RO,
  11861         0,
  11862         1,
  11863         soc_U2_M0SS_INTR_159_128r_fields,
  11864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11865         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11866         -1,
  11867         -1,
  11868     },
  11869 #endif /* chips */
  11870 
  11871 #if defined(BCM_56370_A0)
  11872     { /* SOC_REG_INT_U2_M0SS_INTR_159_128_BCM56370_A0r */
  11873         soc_block_list[61],
  11874         soc_iprocreg,
  11875         1,
  11876         0,
  11877         0x10028074,
  11878         SOC_REG_FLAG_RO,
  11879         0,
  11880         1,
  11881         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  11882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11883         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11884         -1,
  11885         -1,
  11886         3,
  11887     },
  11888 #endif /* chips */
  11889 
  11890 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11891     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11892     { /* SOC_REG_INT_U2_M0SS_INTR_159_128_BCM56870_A0r */
  11893         soc_block_list[61],
  11894         soc_iprocreg,
  11895         1,
  11896         0,
  11897         0x1328074,
  11898         SOC_REG_FLAG_RO,
  11899         0,
  11900         1,
  11901         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  11902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11903         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11904         -1,
  11905         -1,
  11906         3,
  11907     },
  11908 #endif /* chips */
  11909 
  11910 #if defined(BCM_88690_A0)
  11911     { /* SOC_REG_INT_U2_M0SS_INTR_159_128_BCM88690_A0r */
  11912         soc_block_list[61],
  11913         soc_iprocreg,
  11914         1,
  11915         0,
  11916         0x1328074,
  11917         SOC_REG_FLAG_RO,
  11918         0,
  11919         1,
  11920         soc_U2_M0SS_INTR_159_128_BCM88690_A0r_fields,
  11921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11922         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11923         -1,
  11924         -1,
  11925     },
  11926 #endif /* chips */
  11927 
  11928 #if defined(BCM_88690_B0)
  11929     { /* SOC_REG_INT_U2_M0SS_INTR_159_128_BCM88690_B0r */
  11930         soc_block_list[61],
  11931         soc_iprocreg,
  11932         1,
  11933         0,
  11934         0x1328074,
  11935         SOC_REG_FLAG_RO,
  11936         0,
  11937         1,
  11938         soc_U2_M0SS_INTR_159_128_BCM88690_B0r_fields,
  11939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11940         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11941         -1,
  11942         -1,
  11943     },
  11944 #endif /* chips */
  11945 
  11946 #if defined(BCM_88790_A0)
  11947     { /* SOC_REG_INT_U2_M0SS_INTR_191_160r */
  11948         soc_block_list[61],
  11949         soc_iprocreg,
  11950         1,
  11951         0,
  11952         0x1328078,
  11953         SOC_REG_FLAG_RO,
  11954         0,
  11955         1,
  11956         soc_U2_M0SS_INTR_191_160r_fields,
  11957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11958         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11959         -1,
  11960         -1,
  11961     },
  11962 #endif /* chips */
  11963 
  11964 #if defined(BCM_56370_A0)
  11965     { /* SOC_REG_INT_U2_M0SS_INTR_191_160_BCM56370_A0r */
  11966         soc_block_list[61],
  11967         soc_iprocreg,
  11968         1,
  11969         0,
  11970         0x10028078,
  11971         SOC_REG_FLAG_RO,
  11972         0,
  11973         1,
  11974         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  11975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11976         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11977         -1,
  11978         -1,
  11979         3,
  11980     },
  11981 #endif /* chips */
  11982 
  11983 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11984     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11985     { /* SOC_REG_INT_U2_M0SS_INTR_191_160_BCM56870_A0r */
  11986         soc_block_list[61],
  11987         soc_iprocreg,
  11988         1,
  11989         0,
  11990         0x1328078,
  11991         SOC_REG_FLAG_RO,
  11992         0,
  11993         1,
  11994         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  11995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11997         -1,
  11998         -1,
  11999         3,
  12000     },
  12001 #endif /* chips */
  12002 
  12003 #if defined(BCM_88690_A0)
  12004     { /* SOC_REG_INT_U2_M0SS_INTR_191_160_BCM88690_A0r */
  12005         soc_block_list[61],
  12006         soc_iprocreg,
  12007         1,
  12008         0,
  12009         0x1328078,
  12010         SOC_REG_FLAG_RO,
  12011         0,
  12012         1,
  12013         soc_U2_M0SS_INTR_191_160_BCM88690_A0r_fields,
  12014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12016         -1,
  12017         -1,
  12018     },
  12019 #endif /* chips */
  12020 
  12021 #if defined(BCM_88690_B0)
  12022     { /* SOC_REG_INT_U2_M0SS_INTR_191_160_BCM88690_B0r */
  12023         soc_block_list[61],
  12024         soc_iprocreg,
  12025         1,
  12026         0,
  12027         0x1328078,
  12028         SOC_REG_FLAG_RO,
  12029         0,
  12030         1,
  12031         soc_U2_M0SS_INTR_191_160_BCM88690_B0r_fields,
  12032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12034         -1,
  12035         -1,
  12036     },
  12037 #endif /* chips */
  12038 
  12039 #if defined(BCM_88790_A0)
  12040     { /* SOC_REG_INT_U2_M0SS_INTR_223_192r */
  12041         soc_block_list[61],
  12042         soc_iprocreg,
  12043         1,
  12044         0,
  12045         0x132807c,
  12046         SOC_REG_FLAG_RO,
  12047         0,
  12048         1,
  12049         soc_U2_M0SS_INTR_223_192r_fields,
  12050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12051         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12052         -1,
  12053         -1,
  12054     },
  12055 #endif /* chips */
  12056 
  12057 #if defined(BCM_56370_A0)
  12058     { /* SOC_REG_INT_U2_M0SS_INTR_223_192_BCM56370_A0r */
  12059         soc_block_list[61],
  12060         soc_iprocreg,
  12061         1,
  12062         0,
  12063         0x1002807c,
  12064         SOC_REG_FLAG_RO,
  12065         0,
  12066         1,
  12067         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  12068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12069         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12070         -1,
  12071         -1,
  12072         3,
  12073     },
  12074 #endif /* chips */
  12075 
  12076 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12077     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12078     { /* SOC_REG_INT_U2_M0SS_INTR_223_192_BCM56870_A0r */
  12079         soc_block_list[61],
  12080         soc_iprocreg,
  12081         1,
  12082         0,
  12083         0x132807c,
  12084         SOC_REG_FLAG_RO,
  12085         0,
  12086         1,
  12087         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  12088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12089         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12090         -1,
  12091         -1,
  12092         3,
  12093     },
  12094 #endif /* chips */
  12095 
  12096 #if defined(BCM_88690_A0)
  12097     { /* SOC_REG_INT_U2_M0SS_INTR_223_192_BCM88690_A0r */
  12098         soc_block_list[61],
  12099         soc_iprocreg,
  12100         1,
  12101         0,
  12102         0x132807c,
  12103         SOC_REG_FLAG_RO,
  12104         0,
  12105         1,
  12106         soc_U2_M0SS_INTR_223_192_BCM88690_A0r_fields,
  12107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12108         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12109         -1,
  12110         -1,
  12111     },
  12112 #endif /* chips */
  12113 
  12114 #if defined(BCM_88690_B0)
  12115     { /* SOC_REG_INT_U2_M0SS_INTR_223_192_BCM88690_B0r */
  12116         soc_block_list[61],
  12117         soc_iprocreg,
  12118         1,
  12119         0,
  12120         0x132807c,
  12121         SOC_REG_FLAG_RO,
  12122         0,
  12123         1,
  12124         soc_U2_M0SS_INTR_223_192_BCM88690_B0r_fields,
  12125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12126         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12127         -1,
  12128         -1,
  12129     },
  12130 #endif /* chips */
  12131 
  12132 #if defined(BCM_88790_A0)
  12133     { /* SOC_REG_INT_U2_M0SS_INTR_255_224r */
  12134         soc_block_list[61],
  12135         soc_iprocreg,
  12136         1,
  12137         0,
  12138         0x1328080,
  12139         SOC_REG_FLAG_RO,
  12140         0,
  12141         1,
  12142         soc_U2_M0SS_INTR_255_224r_fields,
  12143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12144         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12145         -1,
  12146         -1,
  12147     },
  12148 #endif /* chips */
  12149 
  12150 #if defined(BCM_56370_A0)
  12151     { /* SOC_REG_INT_U2_M0SS_INTR_255_224_BCM56370_A0r */
  12152         soc_block_list[61],
  12153         soc_iprocreg,
  12154         1,
  12155         0,
  12156         0x10028080,
  12157         SOC_REG_FLAG_RO,
  12158         0,
  12159         1,
  12160         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  12161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12162         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12163         -1,
  12164         -1,
  12165         3,
  12166     },
  12167 #endif /* chips */
  12168 
  12169 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12170     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12171     { /* SOC_REG_INT_U2_M0SS_INTR_255_224_BCM56870_A0r */
  12172         soc_block_list[61],
  12173         soc_iprocreg,
  12174         1,
  12175         0,
  12176         0x1328080,
  12177         SOC_REG_FLAG_RO,
  12178         0,
  12179         1,
  12180         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  12181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12182         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12183         -1,
  12184         -1,
  12185         3,
  12186     },
  12187 #endif /* chips */
  12188 
  12189 #if defined(BCM_88690_A0)
  12190     { /* SOC_REG_INT_U2_M0SS_INTR_255_224_BCM88690_A0r */
  12191         soc_block_list[61],
  12192         soc_iprocreg,
  12193         1,
  12194         0,
  12195         0x1328080,
  12196         SOC_REG_FLAG_RO,
  12197         0,
  12198         1,
  12199         soc_U2_M0SS_INTR_255_224_BCM88690_A0r_fields,
  12200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12201         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12202         -1,
  12203         -1,
  12204     },
  12205 #endif /* chips */
  12206 
  12207 #if defined(BCM_88690_B0)
  12208     { /* SOC_REG_INT_U2_M0SS_INTR_255_224_BCM88690_B0r */
  12209         soc_block_list[61],
  12210         soc_iprocreg,
  12211         1,
  12212         0,
  12213         0x1328080,
  12214         SOC_REG_FLAG_RO,
  12215         0,
  12216         1,
  12217         soc_U2_M0SS_INTR_255_224_BCM88690_B0r_fields,
  12218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12219         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12220         -1,
  12221         -1,
  12222     },
  12223 #endif /* chips */
  12224 
  12225 #if defined(BCM_88790_A0)
  12226     { /* SOC_REG_INT_U2_M0SS_INTR_31_0r */
  12227         soc_block_list[61],
  12228         soc_iprocreg,
  12229         1,
  12230         0,
  12231         0x1328064,
  12232         SOC_REG_FLAG_RO,
  12233         0,
  12234         1,
  12235         soc_U2_M0SS_INTR_31_0r_fields,
  12236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12237         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12238         -1,
  12239         -1,
  12240     },
  12241 #endif /* chips */
  12242 
  12243 #if defined(BCM_56370_A0)
  12244     { /* SOC_REG_INT_U2_M0SS_INTR_31_0_BCM56370_A0r */
  12245         soc_block_list[61],
  12246         soc_iprocreg,
  12247         1,
  12248         0,
  12249         0x10028064,
  12250         SOC_REG_FLAG_RO,
  12251         0,
  12252         1,
  12253         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  12254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12255         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12256         -1,
  12257         -1,
  12258         3,
  12259     },
  12260 #endif /* chips */
  12261 
  12262 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12263     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12264     { /* SOC_REG_INT_U2_M0SS_INTR_31_0_BCM56870_A0r */
  12265         soc_block_list[61],
  12266         soc_iprocreg,
  12267         1,
  12268         0,
  12269         0x1328064,
  12270         SOC_REG_FLAG_RO,
  12271         0,
  12272         1,
  12273         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  12274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12276         -1,
  12277         -1,
  12278         3,
  12279     },
  12280 #endif /* chips */
  12281 
  12282 #if defined(BCM_88690_A0)
  12283     { /* SOC_REG_INT_U2_M0SS_INTR_31_0_BCM88690_A0r */
  12284         soc_block_list[61],
  12285         soc_iprocreg,
  12286         1,
  12287         0,
  12288         0x1328064,
  12289         SOC_REG_FLAG_RO,
  12290         0,
  12291         1,
  12292         soc_U2_M0SS_INTR_31_0_BCM88690_A0r_fields,
  12293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12294         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12295         -1,
  12296         -1,
  12297     },
  12298 #endif /* chips */
  12299 
  12300 #if defined(BCM_88690_B0)
  12301     { /* SOC_REG_INT_U2_M0SS_INTR_31_0_BCM88690_B0r */
  12302         soc_block_list[61],
  12303         soc_iprocreg,
  12304         1,
  12305         0,
  12306         0x1328064,
  12307         SOC_REG_FLAG_RO,
  12308         0,
  12309         1,
  12310         soc_U2_M0SS_INTR_31_0_BCM88690_B0r_fields,
  12311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12312         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12313         -1,
  12314         -1,
  12315     },
  12316 #endif /* chips */
  12317 
  12318 #if defined(BCM_88790_A0)
  12319     { /* SOC_REG_INT_U2_M0SS_INTR_63_32r */
  12320         soc_block_list[61],
  12321         soc_iprocreg,
  12322         1,
  12323         0,
  12324         0x1328068,
  12325         SOC_REG_FLAG_RO,
  12326         0,
  12327         1,
  12328         soc_U2_M0SS_INTR_63_32r_fields,
  12329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12330         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12331         -1,
  12332         -1,
  12333     },
  12334 #endif /* chips */
  12335 
  12336 #if defined(BCM_56370_A0)
  12337     { /* SOC_REG_INT_U2_M0SS_INTR_63_32_BCM56370_A0r */
  12338         soc_block_list[61],
  12339         soc_iprocreg,
  12340         1,
  12341         0,
  12342         0x10028068,
  12343         SOC_REG_FLAG_RO,
  12344         0,
  12345         1,
  12346         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  12347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12348         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12349         -1,
  12350         -1,
  12351         3,
  12352     },
  12353 #endif /* chips */
  12354 
  12355 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12356     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12357     { /* SOC_REG_INT_U2_M0SS_INTR_63_32_BCM56870_A0r */
  12358         soc_block_list[61],
  12359         soc_iprocreg,
  12360         1,
  12361         0,
  12362         0x1328068,
  12363         SOC_REG_FLAG_RO,
  12364         0,
  12365         1,
  12366         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  12367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12368         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12369         -1,
  12370         -1,
  12371         3,
  12372     },
  12373 #endif /* chips */
  12374 
  12375 #if defined(BCM_88690_A0)
  12376     { /* SOC_REG_INT_U2_M0SS_INTR_63_32_BCM88690_A0r */
  12377         soc_block_list[61],
  12378         soc_iprocreg,
  12379         1,
  12380         0,
  12381         0x1328068,
  12382         SOC_REG_FLAG_RO,
  12383         0,
  12384         1,
  12385         soc_U2_M0SS_INTR_63_32_BCM88690_A0r_fields,
  12386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12387         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12388         -1,
  12389         -1,
  12390     },
  12391 #endif /* chips */
  12392 
  12393 #if defined(BCM_88690_B0)
  12394     { /* SOC_REG_INT_U2_M0SS_INTR_63_32_BCM88690_B0r */
  12395         soc_block_list[61],
  12396         soc_iprocreg,
  12397         1,
  12398         0,
  12399         0x1328068,
  12400         SOC_REG_FLAG_RO,
  12401         0,
  12402         1,
  12403         soc_U2_M0SS_INTR_63_32_BCM88690_B0r_fields,
  12404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12405         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12406         -1,
  12407         -1,
  12408     },
  12409 #endif /* chips */
  12410 
  12411 #if defined(BCM_88790_A0)
  12412     { /* SOC_REG_INT_U2_M0SS_INTR_95_64r */
  12413         soc_block_list[61],
  12414         soc_iprocreg,
  12415         1,
  12416         0,
  12417         0x132806c,
  12418         SOC_REG_FLAG_RO,
  12419         0,
  12420         1,
  12421         soc_U2_M0SS_INTR_95_64r_fields,
  12422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12423         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12424         -1,
  12425         -1,
  12426     },
  12427 #endif /* chips */
  12428 
  12429 #if defined(BCM_56370_A0)
  12430     { /* SOC_REG_INT_U2_M0SS_INTR_95_64_BCM56370_A0r */
  12431         soc_block_list[61],
  12432         soc_iprocreg,
  12433         1,
  12434         0,
  12435         0x1002806c,
  12436         SOC_REG_FLAG_RO,
  12437         0,
  12438         1,
  12439         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  12440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12441         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12442         -1,
  12443         -1,
  12444         3,
  12445     },
  12446 #endif /* chips */
  12447 
  12448 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12449     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12450     { /* SOC_REG_INT_U2_M0SS_INTR_95_64_BCM56870_A0r */
  12451         soc_block_list[61],
  12452         soc_iprocreg,
  12453         1,
  12454         0,
  12455         0x132806c,
  12456         SOC_REG_FLAG_RO,
  12457         0,
  12458         1,
  12459         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  12460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12462         -1,
  12463         -1,
  12464         3,
  12465     },
  12466 #endif /* chips */
  12467 
  12468 #if defined(BCM_88690_A0)
  12469     { /* SOC_REG_INT_U2_M0SS_INTR_95_64_BCM88690_A0r */
  12470         soc_block_list[61],
  12471         soc_iprocreg,
  12472         1,
  12473         0,
  12474         0x132806c,
  12475         SOC_REG_FLAG_RO,
  12476         0,
  12477         1,
  12478         soc_U2_M0SS_INTR_95_64_BCM88690_A0r_fields,
  12479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12480         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12481         -1,
  12482         -1,
  12483     },
  12484 #endif /* chips */
  12485 
  12486 #if defined(BCM_88690_B0)
  12487     { /* SOC_REG_INT_U2_M0SS_INTR_95_64_BCM88690_B0r */
  12488         soc_block_list[61],
  12489         soc_iprocreg,
  12490         1,
  12491         0,
  12492         0x132806c,
  12493         SOC_REG_FLAG_RO,
  12494         0,
  12495         1,
  12496         soc_U2_M0SS_INTR_95_64_BCM88690_B0r_fields,
  12497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12498         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12499         -1,
  12500         -1,
  12501     },
  12502 #endif /* chips */
  12503 
  12504 #if defined(BCM_88790_A0)
  12505     { /* SOC_REG_INT_U2_M0SS_INTR_CONTROLr */
  12506         soc_block_list[61],
  12507         soc_iprocreg,
  12508         1,
  12509         0,
  12510         0x1328004,
  12511         0,
  12512         0,
  12513         3,
  12514         soc_U2_M0SS_INTR_CONTROLr_fields,
  12515         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  12516         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12517         -1,
  12518         -1,
  12519     },
  12520 #endif /* chips */
  12521 
  12522 #if defined(BCM_56370_A0)
  12523     { /* SOC_REG_INT_U2_M0SS_INTR_CONTROL_BCM56370_A0r */
  12524         soc_block_list[61],
  12525         soc_iprocreg,
  12526         1,
  12527         0,
  12528         0x10028004,
  12529         0,
  12530         0,
  12531         3,
  12532         soc_U0_M0SS_INTR_CONTROL_BCM56870_A0r_fields,
  12533         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  12534         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12535         -1,
  12536         -1,
  12537         3,
  12538     },
  12539 #endif /* chips */
  12540 
  12541 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12542     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12543     { /* SOC_REG_INT_U2_M0SS_INTR_CONTROL_BCM56870_A0r */
  12544         soc_block_list[61],
  12545         soc_iprocreg,
  12546         1,
  12547         0,
  12548         0x1328004,
  12549         0,
  12550         0,
  12551         3,
  12552         soc_U0_M0SS_INTR_CONTROL_BCM56870_A0r_fields,
  12553         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  12554         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12555         -1,
  12556         -1,
  12557         3,
  12558     },
  12559 #endif /* chips */
  12560 
  12561 #if defined(BCM_88690_A0)
  12562     { /* SOC_REG_INT_U2_M0SS_INTR_CONTROL_BCM88690_A0r */
  12563         soc_block_list[61],
  12564         soc_iprocreg,
  12565         1,
  12566         0,
  12567         0x1328004,
  12568         0,
  12569         0,
  12570         3,
  12571         soc_U2_M0SS_INTR_CONTROL_BCM88690_A0r_fields,
  12572         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  12573         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12574         -1,
  12575         -1,
  12576     },
  12577 #endif /* chips */
  12578 
  12579 #if defined(BCM_88690_B0)
  12580     { /* SOC_REG_INT_U2_M0SS_INTR_CONTROL_BCM88690_B0r */
  12581         soc_block_list[61],
  12582         soc_iprocreg,
  12583         1,
  12584         0,
  12585         0x1328004,
  12586         0,
  12587         0,
  12588         3,
  12589         soc_U2_M0SS_INTR_CONTROL_BCM88690_B0r_fields,
  12590         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  12591         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  12592         -1,
  12593         -1,
  12594     },
  12595 #endif /* chips */
  12596 
  12597 #if defined(BCM_88790_A0)
  12598     { /* SOC_REG_INT_U2_M0SS_INTR_ENABLEr */
  12599         soc_block_list[61],
  12600         soc_iprocreg,
  12601         1,
  12602         0,
  12603         0x1328020,
  12604         0,
  12605         0,
  12606         2,
  12607         soc_U2_M0SS_INTR_ENABLEr_fields,
  12608         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  12609         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12610         -1,
  12611         -1,
  12612     },
  12613 #endif /* chips */
  12614 
  12615 #if defined(BCM_56370_A0)
  12616     { /* SOC_REG_INT_U2_M0SS_INTR_ENABLE_BCM56370_A0r */
  12617         soc_block_list[61],
  12618         soc_iprocreg,
  12619         1,
  12620         0,
  12621         0x10028020,
  12622         0,
  12623         0,
  12624         2,
  12625         soc_U0_M0SSQ_INTR_ENABLE_BCM56870_A0r_fields,
  12626         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  12627         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12628         -1,
  12629         -1,
  12630         3,
  12631     },
  12632 #endif /* chips */
  12633 
  12634 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12635     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12636     { /* SOC_REG_INT_U2_M0SS_INTR_ENABLE_BCM56870_A0r */
  12637         soc_block_list[61],
  12638         soc_iprocreg,
  12639         1,
  12640         0,
  12641         0x1328020,
  12642         0,
  12643         0,
  12644         2,
  12645         soc_U0_M0SSQ_INTR_ENABLE_BCM56870_A0r_fields,
  12646         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  12647         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12648         -1,
  12649         -1,
  12650         3,
  12651     },
  12652 #endif /* chips */
  12653 
  12654 #if defined(BCM_88690_A0)
  12655     { /* SOC_REG_INT_U2_M0SS_INTR_ENABLE_BCM88690_A0r */
  12656         soc_block_list[61],
  12657         soc_iprocreg,
  12658         1,
  12659         0,
  12660         0x1328020,
  12661         0,
  12662         0,
  12663         2,
  12664         soc_U2_M0SS_INTR_ENABLE_BCM88690_A0r_fields,
  12665         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  12666         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12667         -1,
  12668         -1,
  12669     },
  12670 #endif /* chips */
  12671 
  12672 #if defined(BCM_88690_B0)
  12673     { /* SOC_REG_INT_U2_M0SS_INTR_ENABLE_BCM88690_B0r */
  12674         soc_block_list[61],
  12675         soc_iprocreg,
  12676         1,
  12677         0,
  12678         0x1328020,
  12679         0,
  12680         0,
  12681         2,
  12682         soc_U2_M0SS_INTR_ENABLE_BCM88690_B0r_fields,
  12683         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  12684         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  12685         -1,
  12686         -1,
  12687     },
  12688 #endif /* chips */
  12689 
  12690 #if defined(BCM_88790_A0)
  12691     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_127_96r */
  12692         soc_block_list[61],
  12693         soc_iprocreg,
  12694         1,
  12695         0,
  12696         0x1328050,
  12697         0,
  12698         0,
  12699         1,
  12700         soc_U2_M0SS_INTR_MASK_127_96r_fields,
  12701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12703         -1,
  12704         -1,
  12705     },
  12706 #endif /* chips */
  12707 
  12708 #if defined(BCM_56370_A0)
  12709     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_127_96_BCM56370_A0r */
  12710         soc_block_list[61],
  12711         soc_iprocreg,
  12712         1,
  12713         0,
  12714         0x10028050,
  12715         0,
  12716         0,
  12717         1,
  12718         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  12719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12720         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12721         -1,
  12722         -1,
  12723         3,
  12724     },
  12725 #endif /* chips */
  12726 
  12727 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12728     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12729     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_127_96_BCM56870_A0r */
  12730         soc_block_list[61],
  12731         soc_iprocreg,
  12732         1,
  12733         0,
  12734         0x1328050,
  12735         0,
  12736         0,
  12737         1,
  12738         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  12739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12740         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12741         -1,
  12742         -1,
  12743         3,
  12744     },
  12745 #endif /* chips */
  12746 
  12747 #if defined(BCM_88690_A0)
  12748     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_127_96_BCM88690_A0r */
  12749         soc_block_list[61],
  12750         soc_iprocreg,
  12751         1,
  12752         0,
  12753         0x1328050,
  12754         0,
  12755         0,
  12756         1,
  12757         soc_U2_M0SS_INTR_MASK_127_96_BCM88690_A0r_fields,
  12758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12760         -1,
  12761         -1,
  12762     },
  12763 #endif /* chips */
  12764 
  12765 #if defined(BCM_88690_B0)
  12766     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_127_96_BCM88690_B0r */
  12767         soc_block_list[61],
  12768         soc_iprocreg,
  12769         1,
  12770         0,
  12771         0x1328050,
  12772         0,
  12773         0,
  12774         1,
  12775         soc_U2_M0SS_INTR_MASK_127_96_BCM88690_B0r_fields,
  12776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12778         -1,
  12779         -1,
  12780     },
  12781 #endif /* chips */
  12782 
  12783 #if defined(BCM_88790_A0)
  12784     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_159_128r */
  12785         soc_block_list[61],
  12786         soc_iprocreg,
  12787         1,
  12788         0,
  12789         0x1328054,
  12790         0,
  12791         0,
  12792         1,
  12793         soc_U2_M0SS_INTR_MASK_159_128r_fields,
  12794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12796         -1,
  12797         -1,
  12798     },
  12799 #endif /* chips */
  12800 
  12801 #if defined(BCM_56370_A0)
  12802     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_159_128_BCM56370_A0r */
  12803         soc_block_list[61],
  12804         soc_iprocreg,
  12805         1,
  12806         0,
  12807         0x10028054,
  12808         0,
  12809         0,
  12810         1,
  12811         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  12812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12813         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12814         -1,
  12815         -1,
  12816         3,
  12817     },
  12818 #endif /* chips */
  12819 
  12820 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12821     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12822     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_159_128_BCM56870_A0r */
  12823         soc_block_list[61],
  12824         soc_iprocreg,
  12825         1,
  12826         0,
  12827         0x1328054,
  12828         0,
  12829         0,
  12830         1,
  12831         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  12832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12833         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12834         -1,
  12835         -1,
  12836         3,
  12837     },
  12838 #endif /* chips */
  12839 
  12840 #if defined(BCM_88690_A0)
  12841     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_159_128_BCM88690_A0r */
  12842         soc_block_list[61],
  12843         soc_iprocreg,
  12844         1,
  12845         0,
  12846         0x1328054,
  12847         0,
  12848         0,
  12849         1,
  12850         soc_U2_M0SS_INTR_MASK_159_128_BCM88690_A0r_fields,
  12851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12852         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12853         -1,
  12854         -1,
  12855     },
  12856 #endif /* chips */
  12857 
  12858 #if defined(BCM_88690_B0)
  12859     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_159_128_BCM88690_B0r */
  12860         soc_block_list[61],
  12861         soc_iprocreg,
  12862         1,
  12863         0,
  12864         0x1328054,
  12865         0,
  12866         0,
  12867         1,
  12868         soc_U2_M0SS_INTR_MASK_159_128_BCM88690_B0r_fields,
  12869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12870         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12871         -1,
  12872         -1,
  12873     },
  12874 #endif /* chips */
  12875 
  12876 #if defined(BCM_88790_A0)
  12877     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_191_160r */
  12878         soc_block_list[61],
  12879         soc_iprocreg,
  12880         1,
  12881         0,
  12882         0x1328058,
  12883         0,
  12884         0,
  12885         1,
  12886         soc_U2_M0SS_INTR_MASK_191_160r_fields,
  12887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12889         -1,
  12890         -1,
  12891     },
  12892 #endif /* chips */
  12893 
  12894 #if defined(BCM_56370_A0)
  12895     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_191_160_BCM56370_A0r */
  12896         soc_block_list[61],
  12897         soc_iprocreg,
  12898         1,
  12899         0,
  12900         0x10028058,
  12901         0,
  12902         0,
  12903         1,
  12904         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  12905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12906         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12907         -1,
  12908         -1,
  12909         3,
  12910     },
  12911 #endif /* chips */
  12912 
  12913 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12914     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  12915     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_191_160_BCM56870_A0r */
  12916         soc_block_list[61],
  12917         soc_iprocreg,
  12918         1,
  12919         0,
  12920         0x1328058,
  12921         0,
  12922         0,
  12923         1,
  12924         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  12925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12926         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12927         -1,
  12928         -1,
  12929         3,
  12930     },
  12931 #endif /* chips */
  12932 
  12933 #if defined(BCM_88690_A0)
  12934     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_191_160_BCM88690_A0r */
  12935         soc_block_list[61],
  12936         soc_iprocreg,
  12937         1,
  12938         0,
  12939         0x1328058,
  12940         0,
  12941         0,
  12942         1,
  12943         soc_U2_M0SS_INTR_MASK_191_160_BCM88690_A0r_fields,
  12944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12946         -1,
  12947         -1,
  12948     },
  12949 #endif /* chips */
  12950 
  12951 #if defined(BCM_88690_B0)
  12952     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_191_160_BCM88690_B0r */
  12953         soc_block_list[61],
  12954         soc_iprocreg,
  12955         1,
  12956         0,
  12957         0x1328058,
  12958         0,
  12959         0,
  12960         1,
  12961         soc_U2_M0SS_INTR_MASK_191_160_BCM88690_B0r_fields,
  12962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12964         -1,
  12965         -1,
  12966     },
  12967 #endif /* chips */
  12968 
  12969 #if defined(BCM_88790_A0)
  12970     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_223_192r */
  12971         soc_block_list[61],
  12972         soc_iprocreg,
  12973         1,
  12974         0,
  12975         0x132805c,
  12976         0,
  12977         0,
  12978         1,
  12979         soc_U2_M0SS_INTR_MASK_223_192r_fields,
  12980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12981         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12982         -1,
  12983         -1,
  12984     },
  12985 #endif /* chips */
  12986 
  12987 #if defined(BCM_56370_A0)
  12988     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_223_192_BCM56370_A0r */
  12989         soc_block_list[61],
  12990         soc_iprocreg,
  12991         1,
  12992         0,
  12993         0x1002805c,
  12994         0,
  12995         0,
  12996         1,
  12997         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  12998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12999         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13000         -1,
  13001         -1,
  13002         3,
  13003     },
  13004 #endif /* chips */
  13005 
  13006 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13007     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13008     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_223_192_BCM56870_A0r */
  13009         soc_block_list[61],
  13010         soc_iprocreg,
  13011         1,
  13012         0,
  13013         0x132805c,
  13014         0,
  13015         0,
  13016         1,
  13017         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  13018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13019         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13020         -1,
  13021         -1,
  13022         3,
  13023     },
  13024 #endif /* chips */
  13025 
  13026 #if defined(BCM_88690_A0)
  13027     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_223_192_BCM88690_A0r */
  13028         soc_block_list[61],
  13029         soc_iprocreg,
  13030         1,
  13031         0,
  13032         0x132805c,
  13033         0,
  13034         0,
  13035         1,
  13036         soc_U2_M0SS_INTR_MASK_223_192_BCM88690_A0r_fields,
  13037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13038         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13039         -1,
  13040         -1,
  13041     },
  13042 #endif /* chips */
  13043 
  13044 #if defined(BCM_88690_B0)
  13045     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_223_192_BCM88690_B0r */
  13046         soc_block_list[61],
  13047         soc_iprocreg,
  13048         1,
  13049         0,
  13050         0x132805c,
  13051         0,
  13052         0,
  13053         1,
  13054         soc_U2_M0SS_INTR_MASK_223_192_BCM88690_B0r_fields,
  13055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13056         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13057         -1,
  13058         -1,
  13059     },
  13060 #endif /* chips */
  13061 
  13062 #if defined(BCM_88790_A0)
  13063     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_255_224r */
  13064         soc_block_list[61],
  13065         soc_iprocreg,
  13066         1,
  13067         0,
  13068         0x1328060,
  13069         0,
  13070         0,
  13071         1,
  13072         soc_U2_M0SS_INTR_MASK_255_224r_fields,
  13073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13074         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13075         -1,
  13076         -1,
  13077     },
  13078 #endif /* chips */
  13079 
  13080 #if defined(BCM_56370_A0)
  13081     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_255_224_BCM56370_A0r */
  13082         soc_block_list[61],
  13083         soc_iprocreg,
  13084         1,
  13085         0,
  13086         0x10028060,
  13087         0,
  13088         0,
  13089         1,
  13090         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  13091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13092         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13093         -1,
  13094         -1,
  13095         3,
  13096     },
  13097 #endif /* chips */
  13098 
  13099 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13100     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13101     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_255_224_BCM56870_A0r */
  13102         soc_block_list[61],
  13103         soc_iprocreg,
  13104         1,
  13105         0,
  13106         0x1328060,
  13107         0,
  13108         0,
  13109         1,
  13110         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  13111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13112         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13113         -1,
  13114         -1,
  13115         3,
  13116     },
  13117 #endif /* chips */
  13118 
  13119 #if defined(BCM_88690_A0)
  13120     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_255_224_BCM88690_A0r */
  13121         soc_block_list[61],
  13122         soc_iprocreg,
  13123         1,
  13124         0,
  13125         0x1328060,
  13126         0,
  13127         0,
  13128         1,
  13129         soc_U2_M0SS_INTR_MASK_255_224_BCM88690_A0r_fields,
  13130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13132         -1,
  13133         -1,
  13134     },
  13135 #endif /* chips */
  13136 
  13137 #if defined(BCM_88690_B0)
  13138     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_255_224_BCM88690_B0r */
  13139         soc_block_list[61],
  13140         soc_iprocreg,
  13141         1,
  13142         0,
  13143         0x1328060,
  13144         0,
  13145         0,
  13146         1,
  13147         soc_U2_M0SS_INTR_MASK_255_224_BCM88690_B0r_fields,
  13148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13149         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13150         -1,
  13151         -1,
  13152     },
  13153 #endif /* chips */
  13154 
  13155 #if defined(BCM_88790_A0)
  13156     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_31_0r */
  13157         soc_block_list[61],
  13158         soc_iprocreg,
  13159         1,
  13160         0,
  13161         0x1328044,
  13162         0,
  13163         0,
  13164         1,
  13165         soc_U2_M0SS_INTR_MASK_31_0r_fields,
  13166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13168         -1,
  13169         -1,
  13170     },
  13171 #endif /* chips */
  13172 
  13173 #if defined(BCM_56370_A0)
  13174     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_31_0_BCM56370_A0r */
  13175         soc_block_list[61],
  13176         soc_iprocreg,
  13177         1,
  13178         0,
  13179         0x10028044,
  13180         0,
  13181         0,
  13182         1,
  13183         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  13184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13186         -1,
  13187         -1,
  13188         3,
  13189     },
  13190 #endif /* chips */
  13191 
  13192 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13193     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13194     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_31_0_BCM56870_A0r */
  13195         soc_block_list[61],
  13196         soc_iprocreg,
  13197         1,
  13198         0,
  13199         0x1328044,
  13200         0,
  13201         0,
  13202         1,
  13203         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  13204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13205         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13206         -1,
  13207         -1,
  13208         3,
  13209     },
  13210 #endif /* chips */
  13211 
  13212 #if defined(BCM_88690_A0)
  13213     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_31_0_BCM88690_A0r */
  13214         soc_block_list[61],
  13215         soc_iprocreg,
  13216         1,
  13217         0,
  13218         0x1328044,
  13219         0,
  13220         0,
  13221         1,
  13222         soc_U2_M0SS_INTR_MASK_31_0_BCM88690_A0r_fields,
  13223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13224         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13225         -1,
  13226         -1,
  13227     },
  13228 #endif /* chips */
  13229 
  13230 #if defined(BCM_88690_B0)
  13231     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_31_0_BCM88690_B0r */
  13232         soc_block_list[61],
  13233         soc_iprocreg,
  13234         1,
  13235         0,
  13236         0x1328044,
  13237         0,
  13238         0,
  13239         1,
  13240         soc_U2_M0SS_INTR_MASK_31_0_BCM88690_B0r_fields,
  13241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13242         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13243         -1,
  13244         -1,
  13245     },
  13246 #endif /* chips */
  13247 
  13248 #if defined(BCM_88790_A0)
  13249     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_63_32r */
  13250         soc_block_list[61],
  13251         soc_iprocreg,
  13252         1,
  13253         0,
  13254         0x1328048,
  13255         0,
  13256         0,
  13257         1,
  13258         soc_U2_M0SS_INTR_MASK_63_32r_fields,
  13259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13260         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13261         -1,
  13262         -1,
  13263     },
  13264 #endif /* chips */
  13265 
  13266 #if defined(BCM_56370_A0)
  13267     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_63_32_BCM56370_A0r */
  13268         soc_block_list[61],
  13269         soc_iprocreg,
  13270         1,
  13271         0,
  13272         0x10028048,
  13273         0,
  13274         0,
  13275         1,
  13276         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  13277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13278         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13279         -1,
  13280         -1,
  13281         3,
  13282     },
  13283 #endif /* chips */
  13284 
  13285 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13286     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13287     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_63_32_BCM56870_A0r */
  13288         soc_block_list[61],
  13289         soc_iprocreg,
  13290         1,
  13291         0,
  13292         0x1328048,
  13293         0,
  13294         0,
  13295         1,
  13296         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  13297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13298         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13299         -1,
  13300         -1,
  13301         3,
  13302     },
  13303 #endif /* chips */
  13304 
  13305 #if defined(BCM_88690_A0)
  13306     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_63_32_BCM88690_A0r */
  13307         soc_block_list[61],
  13308         soc_iprocreg,
  13309         1,
  13310         0,
  13311         0x1328048,
  13312         0,
  13313         0,
  13314         1,
  13315         soc_U2_M0SS_INTR_MASK_63_32_BCM88690_A0r_fields,
  13316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13318         -1,
  13319         -1,
  13320     },
  13321 #endif /* chips */
  13322 
  13323 #if defined(BCM_88690_B0)
  13324     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_63_32_BCM88690_B0r */
  13325         soc_block_list[61],
  13326         soc_iprocreg,
  13327         1,
  13328         0,
  13329         0x1328048,
  13330         0,
  13331         0,
  13332         1,
  13333         soc_U2_M0SS_INTR_MASK_63_32_BCM88690_B0r_fields,
  13334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13335         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13336         -1,
  13337         -1,
  13338     },
  13339 #endif /* chips */
  13340 
  13341 #if defined(BCM_88790_A0)
  13342     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_95_64r */
  13343         soc_block_list[61],
  13344         soc_iprocreg,
  13345         1,
  13346         0,
  13347         0x132804c,
  13348         0,
  13349         0,
  13350         1,
  13351         soc_U2_M0SS_INTR_MASK_95_64r_fields,
  13352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13353         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13354         -1,
  13355         -1,
  13356     },
  13357 #endif /* chips */
  13358 
  13359 #if defined(BCM_56370_A0)
  13360     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_95_64_BCM56370_A0r */
  13361         soc_block_list[61],
  13362         soc_iprocreg,
  13363         1,
  13364         0,
  13365         0x1002804c,
  13366         0,
  13367         0,
  13368         1,
  13369         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  13370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13371         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13372         -1,
  13373         -1,
  13374         3,
  13375     },
  13376 #endif /* chips */
  13377 
  13378 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13379     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13380     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_95_64_BCM56870_A0r */
  13381         soc_block_list[61],
  13382         soc_iprocreg,
  13383         1,
  13384         0,
  13385         0x132804c,
  13386         0,
  13387         0,
  13388         1,
  13389         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  13390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13391         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13392         -1,
  13393         -1,
  13394         3,
  13395     },
  13396 #endif /* chips */
  13397 
  13398 #if defined(BCM_88690_A0)
  13399     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_95_64_BCM88690_A0r */
  13400         soc_block_list[61],
  13401         soc_iprocreg,
  13402         1,
  13403         0,
  13404         0x132804c,
  13405         0,
  13406         0,
  13407         1,
  13408         soc_U2_M0SS_INTR_MASK_95_64_BCM88690_A0r_fields,
  13409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13410         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13411         -1,
  13412         -1,
  13413     },
  13414 #endif /* chips */
  13415 
  13416 #if defined(BCM_88690_B0)
  13417     { /* SOC_REG_INT_U2_M0SS_INTR_MASK_95_64_BCM88690_B0r */
  13418         soc_block_list[61],
  13419         soc_iprocreg,
  13420         1,
  13421         0,
  13422         0x132804c,
  13423         0,
  13424         0,
  13425         1,
  13426         soc_U2_M0SS_INTR_MASK_95_64_BCM88690_B0r_fields,
  13427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13428         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13429         -1,
  13430         -1,
  13431     },
  13432 #endif /* chips */
  13433 
  13434 #if defined(BCM_88790_A0)
  13435     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_127_96r */
  13436         soc_block_list[61],
  13437         soc_iprocreg,
  13438         1,
  13439         0,
  13440         0x1328030,
  13441         SOC_REG_FLAG_RO,
  13442         0,
  13443         1,
  13444         soc_U2_M0SS_RAW_INTR_127_96r_fields,
  13445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13446         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13447         -1,
  13448         -1,
  13449     },
  13450 #endif /* chips */
  13451 
  13452 #if defined(BCM_56370_A0)
  13453     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_127_96_BCM56370_A0r */
  13454         soc_block_list[61],
  13455         soc_iprocreg,
  13456         1,
  13457         0,
  13458         0x10028030,
  13459         SOC_REG_FLAG_RO,
  13460         0,
  13461         1,
  13462         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13464         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13465         -1,
  13466         -1,
  13467         3,
  13468     },
  13469 #endif /* chips */
  13470 
  13471 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13472     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13473     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_127_96_BCM56870_A0r */
  13474         soc_block_list[61],
  13475         soc_iprocreg,
  13476         1,
  13477         0,
  13478         0x1328030,
  13479         SOC_REG_FLAG_RO,
  13480         0,
  13481         1,
  13482         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13484         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13485         -1,
  13486         -1,
  13487         3,
  13488     },
  13489 #endif /* chips */
  13490 
  13491 #if defined(BCM_88690_A0)
  13492     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_127_96_BCM88690_A0r */
  13493         soc_block_list[61],
  13494         soc_iprocreg,
  13495         1,
  13496         0,
  13497         0x1328030,
  13498         SOC_REG_FLAG_RO,
  13499         0,
  13500         1,
  13501         soc_U2_M0SS_RAW_INTR_127_96_BCM88690_A0r_fields,
  13502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13503         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13504         -1,
  13505         -1,
  13506     },
  13507 #endif /* chips */
  13508 
  13509 #if defined(BCM_88690_B0)
  13510     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_127_96_BCM88690_B0r */
  13511         soc_block_list[61],
  13512         soc_iprocreg,
  13513         1,
  13514         0,
  13515         0x1328030,
  13516         SOC_REG_FLAG_RO,
  13517         0,
  13518         1,
  13519         soc_U2_M0SS_RAW_INTR_127_96_BCM88690_B0r_fields,
  13520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13521         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13522         -1,
  13523         -1,
  13524     },
  13525 #endif /* chips */
  13526 
  13527 #if defined(BCM_88790_A0)
  13528     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_159_128r */
  13529         soc_block_list[61],
  13530         soc_iprocreg,
  13531         1,
  13532         0,
  13533         0x1328034,
  13534         SOC_REG_FLAG_RO,
  13535         0,
  13536         1,
  13537         soc_U2_M0SS_RAW_INTR_159_128r_fields,
  13538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13539         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13540         -1,
  13541         -1,
  13542     },
  13543 #endif /* chips */
  13544 
  13545 #if defined(BCM_56370_A0)
  13546     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_159_128_BCM56370_A0r */
  13547         soc_block_list[61],
  13548         soc_iprocreg,
  13549         1,
  13550         0,
  13551         0x10028034,
  13552         SOC_REG_FLAG_RO,
  13553         0,
  13554         1,
  13555         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13557         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13558         -1,
  13559         -1,
  13560         3,
  13561     },
  13562 #endif /* chips */
  13563 
  13564 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13565     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13566     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_159_128_BCM56870_A0r */
  13567         soc_block_list[61],
  13568         soc_iprocreg,
  13569         1,
  13570         0,
  13571         0x1328034,
  13572         SOC_REG_FLAG_RO,
  13573         0,
  13574         1,
  13575         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13577         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13578         -1,
  13579         -1,
  13580         3,
  13581     },
  13582 #endif /* chips */
  13583 
  13584 #if defined(BCM_88690_A0)
  13585     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_159_128_BCM88690_A0r */
  13586         soc_block_list[61],
  13587         soc_iprocreg,
  13588         1,
  13589         0,
  13590         0x1328034,
  13591         SOC_REG_FLAG_RO,
  13592         0,
  13593         1,
  13594         soc_U2_M0SS_RAW_INTR_159_128_BCM88690_A0r_fields,
  13595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13596         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13597         -1,
  13598         -1,
  13599     },
  13600 #endif /* chips */
  13601 
  13602 #if defined(BCM_88690_B0)
  13603     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_159_128_BCM88690_B0r */
  13604         soc_block_list[61],
  13605         soc_iprocreg,
  13606         1,
  13607         0,
  13608         0x1328034,
  13609         SOC_REG_FLAG_RO,
  13610         0,
  13611         1,
  13612         soc_U2_M0SS_RAW_INTR_159_128_BCM88690_B0r_fields,
  13613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13614         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13615         -1,
  13616         -1,
  13617     },
  13618 #endif /* chips */
  13619 
  13620 #if defined(BCM_88790_A0)
  13621     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_191_160r */
  13622         soc_block_list[61],
  13623         soc_iprocreg,
  13624         1,
  13625         0,
  13626         0x1328038,
  13627         SOC_REG_FLAG_RO,
  13628         0,
  13629         1,
  13630         soc_U2_M0SS_RAW_INTR_191_160r_fields,
  13631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13632         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13633         -1,
  13634         -1,
  13635     },
  13636 #endif /* chips */
  13637 
  13638 #if defined(BCM_56370_A0)
  13639     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_191_160_BCM56370_A0r */
  13640         soc_block_list[61],
  13641         soc_iprocreg,
  13642         1,
  13643         0,
  13644         0x10028038,
  13645         SOC_REG_FLAG_RO,
  13646         0,
  13647         1,
  13648         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13651         -1,
  13652         -1,
  13653         3,
  13654     },
  13655 #endif /* chips */
  13656 
  13657 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13658     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13659     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_191_160_BCM56870_A0r */
  13660         soc_block_list[61],
  13661         soc_iprocreg,
  13662         1,
  13663         0,
  13664         0x1328038,
  13665         SOC_REG_FLAG_RO,
  13666         0,
  13667         1,
  13668         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13670         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13671         -1,
  13672         -1,
  13673         3,
  13674     },
  13675 #endif /* chips */
  13676 
  13677 #if defined(BCM_88690_A0)
  13678     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_191_160_BCM88690_A0r */
  13679         soc_block_list[61],
  13680         soc_iprocreg,
  13681         1,
  13682         0,
  13683         0x1328038,
  13684         SOC_REG_FLAG_RO,
  13685         0,
  13686         1,
  13687         soc_U2_M0SS_RAW_INTR_191_160_BCM88690_A0r_fields,
  13688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13690         -1,
  13691         -1,
  13692     },
  13693 #endif /* chips */
  13694 
  13695 #if defined(BCM_88690_B0)
  13696     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_191_160_BCM88690_B0r */
  13697         soc_block_list[61],
  13698         soc_iprocreg,
  13699         1,
  13700         0,
  13701         0x1328038,
  13702         SOC_REG_FLAG_RO,
  13703         0,
  13704         1,
  13705         soc_U2_M0SS_RAW_INTR_191_160_BCM88690_B0r_fields,
  13706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13708         -1,
  13709         -1,
  13710     },
  13711 #endif /* chips */
  13712 
  13713 #if defined(BCM_88790_A0)
  13714     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_223_192r */
  13715         soc_block_list[61],
  13716         soc_iprocreg,
  13717         1,
  13718         0,
  13719         0x132803c,
  13720         SOC_REG_FLAG_RO,
  13721         0,
  13722         1,
  13723         soc_U2_M0SS_RAW_INTR_223_192r_fields,
  13724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13726         -1,
  13727         -1,
  13728     },
  13729 #endif /* chips */
  13730 
  13731 #if defined(BCM_56370_A0)
  13732     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_223_192_BCM56370_A0r */
  13733         soc_block_list[61],
  13734         soc_iprocreg,
  13735         1,
  13736         0,
  13737         0x1002803c,
  13738         SOC_REG_FLAG_RO,
  13739         0,
  13740         1,
  13741         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13744         -1,
  13745         -1,
  13746         3,
  13747     },
  13748 #endif /* chips */
  13749 
  13750 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13751     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13752     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_223_192_BCM56870_A0r */
  13753         soc_block_list[61],
  13754         soc_iprocreg,
  13755         1,
  13756         0,
  13757         0x132803c,
  13758         SOC_REG_FLAG_RO,
  13759         0,
  13760         1,
  13761         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13763         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13764         -1,
  13765         -1,
  13766         3,
  13767     },
  13768 #endif /* chips */
  13769 
  13770 #if defined(BCM_88690_A0)
  13771     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_223_192_BCM88690_A0r */
  13772         soc_block_list[61],
  13773         soc_iprocreg,
  13774         1,
  13775         0,
  13776         0x132803c,
  13777         SOC_REG_FLAG_RO,
  13778         0,
  13779         1,
  13780         soc_U2_M0SS_RAW_INTR_223_192_BCM88690_A0r_fields,
  13781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13782         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13783         -1,
  13784         -1,
  13785     },
  13786 #endif /* chips */
  13787 
  13788 #if defined(BCM_88690_B0)
  13789     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_223_192_BCM88690_B0r */
  13790         soc_block_list[61],
  13791         soc_iprocreg,
  13792         1,
  13793         0,
  13794         0x132803c,
  13795         SOC_REG_FLAG_RO,
  13796         0,
  13797         1,
  13798         soc_U2_M0SS_RAW_INTR_223_192_BCM88690_B0r_fields,
  13799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13800         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13801         -1,
  13802         -1,
  13803     },
  13804 #endif /* chips */
  13805 
  13806 #if defined(BCM_88790_A0)
  13807     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_255_224r */
  13808         soc_block_list[61],
  13809         soc_iprocreg,
  13810         1,
  13811         0,
  13812         0x1328040,
  13813         SOC_REG_FLAG_RO,
  13814         0,
  13815         1,
  13816         soc_U2_M0SS_RAW_INTR_255_224r_fields,
  13817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13818         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13819         -1,
  13820         -1,
  13821     },
  13822 #endif /* chips */
  13823 
  13824 #if defined(BCM_56370_A0)
  13825     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_255_224_BCM56370_A0r */
  13826         soc_block_list[61],
  13827         soc_iprocreg,
  13828         1,
  13829         0,
  13830         0x10028040,
  13831         SOC_REG_FLAG_RO,
  13832         0,
  13833         1,
  13834         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13837         -1,
  13838         -1,
  13839         3,
  13840     },
  13841 #endif /* chips */
  13842 
  13843 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13844     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13845     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_255_224_BCM56870_A0r */
  13846         soc_block_list[61],
  13847         soc_iprocreg,
  13848         1,
  13849         0,
  13850         0x1328040,
  13851         SOC_REG_FLAG_RO,
  13852         0,
  13853         1,
  13854         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13856         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13857         -1,
  13858         -1,
  13859         3,
  13860     },
  13861 #endif /* chips */
  13862 
  13863 #if defined(BCM_88690_A0)
  13864     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_255_224_BCM88690_A0r */
  13865         soc_block_list[61],
  13866         soc_iprocreg,
  13867         1,
  13868         0,
  13869         0x1328040,
  13870         SOC_REG_FLAG_RO,
  13871         0,
  13872         1,
  13873         soc_U2_M0SS_RAW_INTR_255_224_BCM88690_A0r_fields,
  13874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13875         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13876         -1,
  13877         -1,
  13878     },
  13879 #endif /* chips */
  13880 
  13881 #if defined(BCM_88690_B0)
  13882     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_255_224_BCM88690_B0r */
  13883         soc_block_list[61],
  13884         soc_iprocreg,
  13885         1,
  13886         0,
  13887         0x1328040,
  13888         SOC_REG_FLAG_RO,
  13889         0,
  13890         1,
  13891         soc_U2_M0SS_RAW_INTR_255_224_BCM88690_B0r_fields,
  13892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13893         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13894         -1,
  13895         -1,
  13896     },
  13897 #endif /* chips */
  13898 
  13899 #if defined(BCM_88790_A0)
  13900     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_31_0r */
  13901         soc_block_list[61],
  13902         soc_iprocreg,
  13903         1,
  13904         0,
  13905         0x1328024,
  13906         SOC_REG_FLAG_RO,
  13907         0,
  13908         1,
  13909         soc_U2_M0SS_RAW_INTR_31_0r_fields,
  13910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13912         -1,
  13913         -1,
  13914     },
  13915 #endif /* chips */
  13916 
  13917 #if defined(BCM_56370_A0)
  13918     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_31_0_BCM56370_A0r */
  13919         soc_block_list[61],
  13920         soc_iprocreg,
  13921         1,
  13922         0,
  13923         0x10028024,
  13924         SOC_REG_FLAG_RO,
  13925         0,
  13926         1,
  13927         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13929         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13930         -1,
  13931         -1,
  13932         3,
  13933     },
  13934 #endif /* chips */
  13935 
  13936 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13937     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  13938     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_31_0_BCM56870_A0r */
  13939         soc_block_list[61],
  13940         soc_iprocreg,
  13941         1,
  13942         0,
  13943         0x1328024,
  13944         SOC_REG_FLAG_RO,
  13945         0,
  13946         1,
  13947         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  13948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13949         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13950         -1,
  13951         -1,
  13952         3,
  13953     },
  13954 #endif /* chips */
  13955 
  13956 #if defined(BCM_88690_A0)
  13957     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_31_0_BCM88690_A0r */
  13958         soc_block_list[61],
  13959         soc_iprocreg,
  13960         1,
  13961         0,
  13962         0x1328024,
  13963         SOC_REG_FLAG_RO,
  13964         0,
  13965         1,
  13966         soc_U2_M0SS_RAW_INTR_31_0_BCM88690_A0r_fields,
  13967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13968         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13969         -1,
  13970         -1,
  13971     },
  13972 #endif /* chips */
  13973 
  13974 #if defined(BCM_88690_B0)
  13975     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_31_0_BCM88690_B0r */
  13976         soc_block_list[61],
  13977         soc_iprocreg,
  13978         1,
  13979         0,
  13980         0x1328024,
  13981         SOC_REG_FLAG_RO,
  13982         0,
  13983         1,
  13984         soc_U2_M0SS_RAW_INTR_31_0_BCM88690_B0r_fields,
  13985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13986         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13987         -1,
  13988         -1,
  13989     },
  13990 #endif /* chips */
  13991 
  13992 #if defined(BCM_88790_A0)
  13993     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_63_32r */
  13994         soc_block_list[61],
  13995         soc_iprocreg,
  13996         1,
  13997         0,
  13998         0x1328028,
  13999         SOC_REG_FLAG_RO,
  14000         0,
  14001         1,
  14002         soc_U2_M0SS_RAW_INTR_63_32r_fields,
  14003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14004         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14005         -1,
  14006         -1,
  14007     },
  14008 #endif /* chips */
  14009 
  14010 #if defined(BCM_56370_A0)
  14011     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_63_32_BCM56370_A0r */
  14012         soc_block_list[61],
  14013         soc_iprocreg,
  14014         1,
  14015         0,
  14016         0x10028028,
  14017         SOC_REG_FLAG_RO,
  14018         0,
  14019         1,
  14020         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  14021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14023         -1,
  14024         -1,
  14025         3,
  14026     },
  14027 #endif /* chips */
  14028 
  14029 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14030     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  14031     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_63_32_BCM56870_A0r */
  14032         soc_block_list[61],
  14033         soc_iprocreg,
  14034         1,
  14035         0,
  14036         0x1328028,
  14037         SOC_REG_FLAG_RO,
  14038         0,
  14039         1,
  14040         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  14041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14042         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14043         -1,
  14044         -1,
  14045         3,
  14046     },
  14047 #endif /* chips */
  14048 
  14049 #if defined(BCM_88690_A0)
  14050     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_63_32_BCM88690_A0r */
  14051         soc_block_list[61],
  14052         soc_iprocreg,
  14053         1,
  14054         0,
  14055         0x1328028,
  14056         SOC_REG_FLAG_RO,
  14057         0,
  14058         1,
  14059         soc_U2_M0SS_RAW_INTR_63_32_BCM88690_A0r_fields,
  14060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14061         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14062         -1,
  14063         -1,
  14064     },
  14065 #endif /* chips */
  14066 
  14067 #if defined(BCM_88690_B0)
  14068     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_63_32_BCM88690_B0r */
  14069         soc_block_list[61],
  14070         soc_iprocreg,
  14071         1,
  14072         0,
  14073         0x1328028,
  14074         SOC_REG_FLAG_RO,
  14075         0,
  14076         1,
  14077         soc_U2_M0SS_RAW_INTR_63_32_BCM88690_B0r_fields,
  14078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14079         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14080         -1,
  14081         -1,
  14082     },
  14083 #endif /* chips */
  14084 
  14085 #if defined(BCM_88790_A0)
  14086     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_95_64r */
  14087         soc_block_list[61],
  14088         soc_iprocreg,
  14089         1,
  14090         0,
  14091         0x132802c,
  14092         SOC_REG_FLAG_RO,
  14093         0,
  14094         1,
  14095         soc_U2_M0SS_RAW_INTR_95_64r_fields,
  14096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14098         -1,
  14099         -1,
  14100     },
  14101 #endif /* chips */
  14102 
  14103 #if defined(BCM_56370_A0)
  14104     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_95_64_BCM56370_A0r */
  14105         soc_block_list[61],
  14106         soc_iprocreg,
  14107         1,
  14108         0,
  14109         0x1002802c,
  14110         SOC_REG_FLAG_RO,
  14111         0,
  14112         1,
  14113         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  14114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14116         -1,
  14117         -1,
  14118         3,
  14119     },
  14120 #endif /* chips */
  14121 
  14122 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14123     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  14124     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_95_64_BCM56870_A0r */
  14125         soc_block_list[61],
  14126         soc_iprocreg,
  14127         1,
  14128         0,
  14129         0x132802c,
  14130         SOC_REG_FLAG_RO,
  14131         0,
  14132         1,
  14133         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  14134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14135         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14136         -1,
  14137         -1,
  14138         3,
  14139     },
  14140 #endif /* chips */
  14141 
  14142 #if defined(BCM_88690_A0)
  14143     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_95_64_BCM88690_A0r */
  14144         soc_block_list[61],
  14145         soc_iprocreg,
  14146         1,
  14147         0,
  14148         0x132802c,
  14149         SOC_REG_FLAG_RO,
  14150         0,
  14151         1,
  14152         soc_U2_M0SS_RAW_INTR_95_64_BCM88690_A0r_fields,
  14153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14154         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14155         -1,
  14156         -1,
  14157     },
  14158 #endif /* chips */
  14159 
  14160 #if defined(BCM_88690_B0)
  14161     { /* SOC_REG_INT_U2_M0SS_RAW_INTR_95_64_BCM88690_B0r */
  14162         soc_block_list[61],
  14163         soc_iprocreg,
  14164         1,
  14165         0,
  14166         0x132802c,
  14167         SOC_REG_FLAG_RO,
  14168         0,
  14169         1,
  14170         soc_U2_M0SS_RAW_INTR_95_64_BCM88690_B0r_fields,
  14171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14172         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14173         -1,
  14174         -1,
  14175     },
  14176 #endif /* chips */
  14177 
  14178 #if defined(BCM_88790_A0)
  14179     { /* SOC_REG_INT_U2_M0SS_STATUSr */
  14180         soc_block_list[61],
  14181         soc_iprocreg,
  14182         1,
  14183         0,
  14184         0x1328010,
  14185         0,
  14186         0,
  14187         10,
  14188         soc_U2_M0SS_STATUSr_fields,
  14189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14190         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
  14191         -1,
  14192         -1,
  14193     },
  14194 #endif /* chips */
  14195 
  14196 #if defined(BCM_56370_A0)
  14197     { /* SOC_REG_INT_U2_M0SS_STATUS_BCM56370_A0r */
  14198         soc_block_list[61],
  14199         soc_iprocreg,
  14200         1,
  14201         0,
  14202         0x10028010,
  14203         0,
  14204         0,
  14205         10,
  14206         soc_U0_M0SS_STATUS_BCM56870_A0r_fields,
  14207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14208         SOC_RESET_MASK_DEC(0xffff001f, 0x00000000)
  14209         -1,
  14210         -1,
  14211         3,
  14212     },
  14213 #endif /* chips */
  14214 
  14215 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14216     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  14217     { /* SOC_REG_INT_U2_M0SS_STATUS_BCM56870_A0r */
  14218         soc_block_list[61],
  14219         soc_iprocreg,
  14220         1,
  14221         0,
  14222         0x1328010,
  14223         0,
  14224         0,
  14225         10,
  14226         soc_U0_M0SS_STATUS_BCM56870_A0r_fields,
  14227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14228         SOC_RESET_MASK_DEC(0xffff001f, 0x00000000)
  14229         -1,
  14230         -1,
  14231         3,
  14232     },
  14233 #endif /* chips */
  14234 
  14235 #if defined(BCM_88690_A0)
  14236     { /* SOC_REG_INT_U2_M0SS_STATUS_BCM88690_A0r */
  14237         soc_block_list[61],
  14238         soc_iprocreg,
  14239         1,
  14240         0,
  14241         0x1328010,
  14242         0,
  14243         0,
  14244         10,
  14245         soc_U2_M0SS_STATUS_BCM88690_A0r_fields,
  14246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14247         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
  14248         -1,
  14249         -1,
  14250     },
  14251 #endif /* chips */
  14252 
  14253 #if defined(BCM_88690_B0)
  14254     { /* SOC_REG_INT_U2_M0SS_STATUS_BCM88690_B0r */
  14255         soc_block_list[61],
  14256         soc_iprocreg,
  14257         1,
  14258         0,
  14259         0x1328010,
  14260         0,
  14261         0,
  14262         10,
  14263         soc_U2_M0SS_STATUS_BCM88690_B0r_fields,
  14264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14265         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
  14266         -1,
  14267         -1,
  14268     },
  14269 #endif /* chips */
  14270 
  14271 #if defined(BCM_88790_A0)
  14272     { /* SOC_REG_INT_U2_M0SS_TCM_CTRLr */
  14273         soc_block_list[61],
  14274         soc_iprocreg,
  14275         1,
  14276         0,
  14277         0x1328014,
  14278         0,
  14279         0,
  14280         1,
  14281         soc_U2_M0SS_TCM_CTRLr_fields,
  14282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14283         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  14284         -1,
  14285         -1,
  14286     },
  14287 #endif /* chips */
  14288 
  14289 #if defined(BCM_56370_A0)
  14290     { /* SOC_REG_INT_U2_M0SS_TCM_CTRL_BCM56370_A0r */
  14291         soc_block_list[61],
  14292         soc_iprocreg,
  14293         1,
  14294         0,
  14295         0x10028014,
  14296         0,
  14297         0,
  14298         1,
  14299         soc_U0_M0SS_TCM_CTRL_BCM56870_A0r_fields,
  14300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14301         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14302         -1,
  14303         -1,
  14304         3,
  14305     },
  14306 #endif /* chips */
  14307 
  14308 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14309     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  14310     { /* SOC_REG_INT_U2_M0SS_TCM_CTRL_BCM56870_A0r */
  14311         soc_block_list[61],
  14312         soc_iprocreg,
  14313         1,
  14314         0,
  14315         0x1328014,
  14316         0,
  14317         0,
  14318         1,
  14319         soc_U0_M0SS_TCM_CTRL_BCM56870_A0r_fields,
  14320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14321         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14322         -1,
  14323         -1,
  14324         3,
  14325     },
  14326 #endif /* chips */
  14327 
  14328 #if defined(BCM_88690_A0)
  14329     { /* SOC_REG_INT_U2_M0SS_TCM_CTRL_BCM88690_A0r */
  14330         soc_block_list[61],
  14331         soc_iprocreg,
  14332         1,
  14333         0,
  14334         0x1328014,
  14335         0,
  14336         0,
  14337         1,
  14338         soc_U2_M0SS_TCM_CTRL_BCM88690_A0r_fields,
  14339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14340         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  14341         -1,
  14342         -1,
  14343     },
  14344 #endif /* chips */
  14345 
  14346 #if defined(BCM_88690_B0)
  14347     { /* SOC_REG_INT_U2_M0SS_TCM_CTRL_BCM88690_B0r */
  14348         soc_block_list[61],
  14349         soc_iprocreg,
  14350         1,
  14351         0,
  14352         0x1328014,
  14353         0,
  14354         0,
  14355         1,
  14356         soc_U2_M0SS_TCM_CTRL_BCM88690_B0r_fields,
  14357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14358         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  14359         -1,
  14360         -1,
  14361     },
  14362 #endif /* chips */
  14363 
  14364 #if defined(BCM_56370_A0)
  14365     { /* SOC_REG_INT_U2_SW_PROG_INTR_CLRr */
  14366         soc_block_list[61],
  14367         soc_iprocreg,
  14368         1,
  14369         0,
  14370         0x10028090,
  14371         0,
  14372         0,
  14373         1,
  14374         soc_PAXB_0_SW_PROG_INTR_CLRr_fields,
  14375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14376         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14377         -1,
  14378         -1,
  14379         3,
  14380     },
  14381 #endif /* chips */
  14382 
  14383 #if defined(BCM_56370_A0)
  14384     { /* SOC_REG_INT_U2_SW_PROG_INTR_ENABLEr */
  14385         soc_block_list[61],
  14386         soc_iprocreg,
  14387         1,
  14388         0,
  14389         0x10028084,
  14390         0,
  14391         0,
  14392         1,
  14393         soc_MIIM_DMA_CH0_DST_HOST_ADDRESS_BCM56870_A0r_fields,
  14394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14395         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14396         -1,
  14397         -1,
  14398         3,
  14399     },
  14400 #endif /* chips */
  14401 
  14402 #if defined(BCM_56370_A0)
  14403     { /* SOC_REG_INT_U2_SW_PROG_INTR_SETr */
  14404         soc_block_list[61],
  14405         soc_iprocreg,
  14406         1,
  14407         0,
  14408         0x1002808c,
  14409         0,
  14410         0,
  14411         1,
  14412         soc_PAXB_0_SW_PROG_INTR_CLRr_fields,
  14413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14414         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14415         -1,
  14416         -1,
  14417         3,
  14418     },
  14419 #endif /* chips */
  14420 
  14421 #if defined(BCM_56370_A0)
  14422     { /* SOC_REG_INT_U2_SW_PROG_INTR_STATUSr */
  14423         soc_block_list[61],
  14424         soc_iprocreg,
  14425         1,
  14426         0,
  14427         0x10028088,
  14428         SOC_REG_FLAG_RO,
  14429         0,
  14430         1,
  14431         soc_MIIM_DMA_CH0_CURR_DST_HOST_ADDRESS_BCM56870_A0r_fields,
  14432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14433         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14434         -1,
  14435         -1,
  14436         3,
  14437     },
  14438 #endif /* chips */
  14439 
  14440 #if defined(BCM_88790_A0)
  14441     { /* SOC_REG_INT_U3_M0SS_CONTROLr */
  14442         soc_block_list[61],
  14443         soc_iprocreg,
  14444         1,
  14445         0,
  14446         0x1338000,
  14447         0,
  14448         0,
  14449         3,
  14450         soc_U3_M0SS_CONTROLr_fields,
  14451         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  14452         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  14453         -1,
  14454         -1,
  14455     },
  14456 #endif /* chips */
  14457 
  14458 #if defined(BCM_56370_A0)
  14459     { /* SOC_REG_INT_U3_M0SS_CONTROL_BCM56370_A0r */
  14460         soc_block_list[61],
  14461         soc_iprocreg,
  14462         1,
  14463         0,
  14464         0x10038000,
  14465         0,
  14466         0,
  14467         3,
  14468         soc_U0_M0SS_CONTROL_BCM56870_A0r_fields,
  14469         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  14470         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  14471         -1,
  14472         -1,
  14473         3,
  14474     },
  14475 #endif /* chips */
  14476 
  14477 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14478     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  14479     { /* SOC_REG_INT_U3_M0SS_CONTROL_BCM56870_A0r */
  14480         soc_block_list[61],
  14481         soc_iprocreg,
  14482         1,
  14483         0,
  14484         0x1338000,
  14485         0,
  14486         0,
  14487         3,
  14488         soc_U0_M0SS_CONTROL_BCM56870_A0r_fields,
  14489         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  14490         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  14491         -1,
  14492         -1,
  14493         3,
  14494     },
  14495 #endif /* chips */
  14496 
  14497 #if defined(BCM_88690_A0)
  14498     { /* SOC_REG_INT_U3_M0SS_CONTROL_BCM88690_A0r */
  14499         soc_block_list[61],
  14500         soc_iprocreg,
  14501         1,
  14502         0,
  14503         0x1338000,
  14504         0,
  14505         0,
  14506         3,
  14507         soc_U3_M0SS_CONTROL_BCM88690_A0r_fields,
  14508         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  14509         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  14510         -1,
  14511         -1,
  14512     },
  14513 #endif /* chips */
  14514 
  14515 #if defined(BCM_88690_B0)
  14516     { /* SOC_REG_INT_U3_M0SS_CONTROL_BCM88690_B0r */
  14517         soc_block_list[61],
  14518         soc_iprocreg,
  14519         1,
  14520         0,
  14521         0x1338000,
  14522         0,
  14523         0,
  14524         3,
  14525         soc_U3_M0SS_CONTROL_BCM88690_B0r_fields,
  14526         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  14527         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  14528         -1,
  14529         -1,
  14530     },
  14531 #endif /* chips */
  14532 
  14533 #if defined(BCM_88790_A0)
  14534     { /* SOC_REG_INT_U3_M0SS_DEBUG_CONTROLr */
  14535         soc_block_list[61],
  14536         soc_iprocreg,
  14537         1,
  14538         0,
  14539         0x133800c,
  14540         0,
  14541         0,
  14542         2,
  14543         soc_U3_M0SS_DEBUG_CONTROLr_fields,
  14544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14545         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  14546         -1,
  14547         -1,
  14548     },
  14549 #endif /* chips */
  14550 
  14551 #if defined(BCM_56370_A0)
  14552     { /* SOC_REG_INT_U3_M0SS_DEBUG_CONTROL_BCM56370_A0r */
  14553         soc_block_list[61],
  14554         soc_iprocreg,
  14555         1,
  14556         0,
  14557         0x1003800c,
  14558         0,
  14559         0,
  14560         2,
  14561         soc_U0_M0SS_DEBUG_CONTROL_BCM56870_A0r_fields,
  14562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14563         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  14564         -1,
  14565         -1,
  14566         3,
  14567     },
  14568 #endif /* chips */
  14569 
  14570 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14571     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  14572     { /* SOC_REG_INT_U3_M0SS_DEBUG_CONTROL_BCM56870_A0r */
  14573         soc_block_list[61],
  14574         soc_iprocreg,
  14575         1,
  14576         0,
  14577         0x133800c,
  14578         0,
  14579         0,
  14580         2,
  14581         soc_U0_M0SS_DEBUG_CONTROL_BCM56870_A0r_fields,
  14582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14583         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  14584         -1,
  14585         -1,
  14586         3,
  14587     },
  14588 #endif /* chips */
  14589 
  14590 #if defined(BCM_88690_A0)
  14591     { /* SOC_REG_INT_U3_M0SS_DEBUG_CONTROL_BCM88690_A0r */
  14592         soc_block_list[61],
  14593         soc_iprocreg,
  14594         1,
  14595         0,
  14596         0x133800c,
  14597         0,
  14598         0,
  14599         2,
  14600         soc_U3_M0SS_DEBUG_CONTROL_BCM88690_A0r_fields,
  14601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14602         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  14603         -1,
  14604         -1,
  14605     },
  14606 #endif /* chips */
  14607 
  14608 #if defined(BCM_88690_B0)
  14609     { /* SOC_REG_INT_U3_M0SS_DEBUG_CONTROL_BCM88690_B0r */
  14610         soc_block_list[61],
  14611         soc_iprocreg,
  14612         1,
  14613         0,
  14614         0x133800c,
  14615         0,
  14616         0,
  14617         2,
  14618         soc_U3_M0SS_DEBUG_CONTROL_BCM88690_B0r_fields,
  14619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14620         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  14621         -1,
  14622         -1,
  14623     },
  14624 #endif /* chips */
  14625 
  14626 #if defined(BCM_88790_A0)
  14627     { /* SOC_REG_INT_U3_M0SS_ECC_CTRLr */
  14628         soc_block_list[61],
  14629         soc_iprocreg,
  14630         1,
  14631         0,
  14632         0x1338018,
  14633         0,
  14634         0,
  14635         3,
  14636         soc_U3_M0SS_ECC_CTRLr_fields,
  14637         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  14638         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  14639         -1,
  14640         -1,
  14641     },
  14642 #endif /* chips */
  14643 
  14644 #if defined(BCM_56370_A0)
  14645     { /* SOC_REG_INT_U3_M0SS_ECC_CTRL_BCM56370_A0r */
  14646         soc_block_list[61],
  14647         soc_iprocreg,
  14648         1,
  14649         0,
  14650         0x10038018,
  14651         0,
  14652         0,
  14653         3,
  14654         soc_U0_M0SSQ_ECC_CTRL_BCM56870_A0r_fields,
  14655         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  14656         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  14657         -1,
  14658         -1,
  14659         3,
  14660     },
  14661 #endif /* chips */
  14662 
  14663 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14664     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  14665     { /* SOC_REG_INT_U3_M0SS_ECC_CTRL_BCM56870_A0r */
  14666         soc_block_list[61],
  14667         soc_iprocreg,
  14668         1,
  14669         0,
  14670         0x1338018,
  14671         0,
  14672         0,
  14673         3,
  14674         soc_U0_M0SSQ_ECC_CTRL_BCM56870_A0r_fields,
  14675         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  14676         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  14677         -1,
  14678         -1,
  14679         3,
  14680     },
  14681 #endif /* chips */
  14682 
  14683 #if defined(BCM_88690_A0)
  14684     { /* SOC_REG_INT_U3_M0SS_ECC_CTRL_BCM88690_A0r */
  14685         soc_block_list[61],
  14686         soc_iprocreg,
  14687         1,
  14688         0,
  14689         0x1338018,
  14690         0,
  14691         0,
  14692         3,
  14693         soc_U3_M0SS_ECC_CTRL_BCM88690_A0r_fields,
  14694         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  14695         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  14696         -1,
  14697         -1,
  14698     },
  14699 #endif /* chips */
  14700 
  14701 #if defined(BCM_88690_B0)
  14702     { /* SOC_REG_INT_U3_M0SS_ECC_CTRL_BCM88690_B0r */
  14703         soc_block_list[61],
  14704         soc_iprocreg,
  14705         1,
  14706         0,
  14707         0x1338018,
  14708         0,
  14709         0,
  14710         3,
  14711         soc_U3_M0SS_ECC_CTRL_BCM88690_B0r_fields,
  14712         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  14713         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  14714         -1,
  14715         -1,
  14716     },
  14717 #endif /* chips */
  14718 
  14719 #if defined(BCM_88790_A0)
  14720     { /* SOC_REG_INT_U3_M0SS_ECC_STATUSr */
  14721         soc_block_list[61],
  14722         soc_iprocreg,
  14723         1,
  14724         0,
  14725         0x133801c,
  14726         0,
  14727         0,
  14728         4,
  14729         soc_U3_M0SS_ECC_STATUSr_fields,
  14730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14731         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  14732         -1,
  14733         -1,
  14734     },
  14735 #endif /* chips */
  14736 
  14737 #if defined(BCM_56370_A0)
  14738     { /* SOC_REG_INT_U3_M0SS_ECC_STATUS_BCM56370_A0r */
  14739         soc_block_list[61],
  14740         soc_iprocreg,
  14741         1,
  14742         0,
  14743         0x1003801c,
  14744         0,
  14745         0,
  14746         4,
  14747         soc_U0_M0SS_ECC_STATUS_BCM56870_A0r_fields,
  14748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14749         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  14750         -1,
  14751         -1,
  14752         3,
  14753     },
  14754 #endif /* chips */
  14755 
  14756 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14757     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  14758     { /* SOC_REG_INT_U3_M0SS_ECC_STATUS_BCM56870_A0r */
  14759         soc_block_list[61],
  14760         soc_iprocreg,
  14761         1,
  14762         0,
  14763         0x133801c,
  14764         0,
  14765         0,
  14766         4,
  14767         soc_U0_M0SS_ECC_STATUS_BCM56870_A0r_fields,
  14768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14769         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  14770         -1,
  14771         -1,
  14772         3,
  14773     },
  14774 #endif /* chips */
  14775 
  14776 #if defined(BCM_88690_A0)
  14777     { /* SOC_REG_INT_U3_M0SS_ECC_STATUS_BCM88690_A0r */
  14778         soc_block_list[61],
  14779         soc_iprocreg,
  14780         1,
  14781         0,
  14782         0x133801c,
  14783         0,
  14784         0,
  14785         4,
  14786         soc_U3_M0SS_ECC_STATUS_BCM88690_A0r_fields,
  14787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14788         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  14789         -1,
  14790         -1,
  14791     },
  14792 #endif /* chips */
  14793 
  14794 #if defined(BCM_88690_B0)
  14795     { /* SOC_REG_INT_U3_M0SS_ECC_STATUS_BCM88690_B0r */
  14796         soc_block_list[61],
  14797         soc_iprocreg,
  14798         1,
  14799         0,
  14800         0x133801c,
  14801         0,
  14802         0,
  14803         4,
  14804         soc_U3_M0SS_ECC_STATUS_BCM88690_B0r_fields,
  14805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14806         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  14807         -1,
  14808         -1,
  14809     },
  14810 #endif /* chips */
  14811 
  14812 #if defined(BCM_88790_A0)
  14813     { /* SOC_REG_INT_U3_M0SS_ECOr */
  14814         soc_block_list[61],
  14815         soc_iprocreg,
  14816         1,
  14817         0,
  14818         0x1338008,
  14819         0,
  14820         0,
  14821         1,
  14822         soc_U3_M0SS_ECOr_fields,
  14823         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14824         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  14825         -1,
  14826         -1,
  14827     },
  14828 #endif /* chips */
  14829 
  14830 #if defined(BCM_56370_A0)
  14831     { /* SOC_REG_INT_U3_M0SS_ECO_BCM56370_A0r */
  14832         soc_block_list[61],
  14833         soc_iprocreg,
  14834         1,
  14835         0,
  14836         0x10038008,
  14837         0,
  14838         0,
  14839         1,
  14840         soc_U0_M0SS_ECO_BCM56870_A0r_fields,
  14841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14842         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  14843         -1,
  14844         -1,
  14845         3,
  14846     },
  14847 #endif /* chips */
  14848 
  14849 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14850     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  14851     { /* SOC_REG_INT_U3_M0SS_ECO_BCM56870_A0r */
  14852         soc_block_list[61],
  14853         soc_iprocreg,
  14854         1,
  14855         0,
  14856         0x1338008,
  14857         0,
  14858         0,
  14859         1,
  14860         soc_U0_M0SS_ECO_BCM56870_A0r_fields,
  14861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14862         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  14863         -1,
  14864         -1,
  14865         3,
  14866     },
  14867 #endif /* chips */
  14868 
  14869 #if defined(BCM_88690_A0)
  14870     { /* SOC_REG_INT_U3_M0SS_ECO_BCM88690_A0r */
  14871         soc_block_list[61],
  14872         soc_iprocreg,
  14873         1,
  14874         0,
  14875         0x1338008,
  14876         0,
  14877         0,
  14878         1,
  14879         soc_U3_M0SS_ECO_BCM88690_A0r_fields,
  14880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14881         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  14882         -1,
  14883         -1,
  14884     },
  14885 #endif /* chips */
  14886 
  14887 #if defined(BCM_88690_B0)
  14888     { /* SOC_REG_INT_U3_M0SS_ECO_BCM88690_B0r */
  14889         soc_block_list[61],
  14890         soc_iprocreg,
  14891         1,
  14892         0,
  14893         0x1338008,
  14894         0,
  14895         0,
  14896         1,
  14897         soc_U3_M0SS_ECO_BCM88690_B0r_fields,
  14898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14899         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  14900         -1,
  14901         -1,
  14902     },
  14903 #endif /* chips */
  14904 
  14905 #if defined(BCM_88790_A0)
  14906     { /* SOC_REG_INT_U3_M0SS_INTR_127_96r */
  14907         soc_block_list[61],
  14908         soc_iprocreg,
  14909         1,
  14910         0,
  14911         0x1338070,
  14912         SOC_REG_FLAG_RO,
  14913         0,
  14914         1,
  14915         soc_U3_M0SS_INTR_127_96r_fields,
  14916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14917         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14918         -1,
  14919         -1,
  14920     },
  14921 #endif /* chips */
  14922 
  14923 #if defined(BCM_56370_A0)
  14924     { /* SOC_REG_INT_U3_M0SS_INTR_127_96_BCM56370_A0r */
  14925         soc_block_list[61],
  14926         soc_iprocreg,
  14927         1,
  14928         0,
  14929         0x10038070,
  14930         SOC_REG_FLAG_RO,
  14931         0,
  14932         1,
  14933         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  14934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14935         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14936         -1,
  14937         -1,
  14938         3,
  14939     },
  14940 #endif /* chips */
  14941 
  14942 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14943     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  14944     { /* SOC_REG_INT_U3_M0SS_INTR_127_96_BCM56870_A0r */
  14945         soc_block_list[61],
  14946         soc_iprocreg,
  14947         1,
  14948         0,
  14949         0x1338070,
  14950         SOC_REG_FLAG_RO,
  14951         0,
  14952         1,
  14953         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  14954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14956         -1,
  14957         -1,
  14958         3,
  14959     },
  14960 #endif /* chips */
  14961 
  14962 #if defined(BCM_88690_A0)
  14963     { /* SOC_REG_INT_U3_M0SS_INTR_127_96_BCM88690_A0r */
  14964         soc_block_list[61],
  14965         soc_iprocreg,
  14966         1,
  14967         0,
  14968         0x1338070,
  14969         SOC_REG_FLAG_RO,
  14970         0,
  14971         1,
  14972         soc_U3_M0SS_INTR_127_96_BCM88690_A0r_fields,
  14973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14974         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14975         -1,
  14976         -1,
  14977     },
  14978 #endif /* chips */
  14979 
  14980 #if defined(BCM_88690_B0)
  14981     { /* SOC_REG_INT_U3_M0SS_INTR_127_96_BCM88690_B0r */
  14982         soc_block_list[61],
  14983         soc_iprocreg,
  14984         1,
  14985         0,
  14986         0x1338070,
  14987         SOC_REG_FLAG_RO,
  14988         0,
  14989         1,
  14990         soc_U3_M0SS_INTR_127_96_BCM88690_B0r_fields,
  14991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14992         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14993         -1,
  14994         -1,
  14995     },
  14996 #endif /* chips */
  14997 
  14998 #if defined(BCM_88790_A0)
  14999     { /* SOC_REG_INT_U3_M0SS_INTR_159_128r */
  15000         soc_block_list[61],
  15001         soc_iprocreg,
  15002         1,
  15003         0,
  15004         0x1338074,
  15005         SOC_REG_FLAG_RO,
  15006         0,
  15007         1,
  15008         soc_U3_M0SS_INTR_159_128r_fields,
  15009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15010         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15011         -1,
  15012         -1,
  15013     },
  15014 #endif /* chips */
  15015 
  15016 #if defined(BCM_56370_A0)
  15017     { /* SOC_REG_INT_U3_M0SS_INTR_159_128_BCM56370_A0r */
  15018         soc_block_list[61],
  15019         soc_iprocreg,
  15020         1,
  15021         0,
  15022         0x10038074,
  15023         SOC_REG_FLAG_RO,
  15024         0,
  15025         1,
  15026         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15028         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15029         -1,
  15030         -1,
  15031         3,
  15032     },
  15033 #endif /* chips */
  15034 
  15035 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15036     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  15037     { /* SOC_REG_INT_U3_M0SS_INTR_159_128_BCM56870_A0r */
  15038         soc_block_list[61],
  15039         soc_iprocreg,
  15040         1,
  15041         0,
  15042         0x1338074,
  15043         SOC_REG_FLAG_RO,
  15044         0,
  15045         1,
  15046         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15048         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15049         -1,
  15050         -1,
  15051         3,
  15052     },
  15053 #endif /* chips */
  15054 
  15055 #if defined(BCM_88690_A0)
  15056     { /* SOC_REG_INT_U3_M0SS_INTR_159_128_BCM88690_A0r */
  15057         soc_block_list[61],
  15058         soc_iprocreg,
  15059         1,
  15060         0,
  15061         0x1338074,
  15062         SOC_REG_FLAG_RO,
  15063         0,
  15064         1,
  15065         soc_U3_M0SS_INTR_159_128_BCM88690_A0r_fields,
  15066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15067         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15068         -1,
  15069         -1,
  15070     },
  15071 #endif /* chips */
  15072 
  15073 #if defined(BCM_88690_B0)
  15074     { /* SOC_REG_INT_U3_M0SS_INTR_159_128_BCM88690_B0r */
  15075         soc_block_list[61],
  15076         soc_iprocreg,
  15077         1,
  15078         0,
  15079         0x1338074,
  15080         SOC_REG_FLAG_RO,
  15081         0,
  15082         1,
  15083         soc_U3_M0SS_INTR_159_128_BCM88690_B0r_fields,
  15084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15085         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15086         -1,
  15087         -1,
  15088     },
  15089 #endif /* chips */
  15090 
  15091 #if defined(BCM_88790_A0)
  15092     { /* SOC_REG_INT_U3_M0SS_INTR_191_160r */
  15093         soc_block_list[61],
  15094         soc_iprocreg,
  15095         1,
  15096         0,
  15097         0x1338078,
  15098         SOC_REG_FLAG_RO,
  15099         0,
  15100         1,
  15101         soc_U3_M0SS_INTR_191_160r_fields,
  15102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15103         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15104         -1,
  15105         -1,
  15106     },
  15107 #endif /* chips */
  15108 
  15109 #if defined(BCM_56370_A0)
  15110     { /* SOC_REG_INT_U3_M0SS_INTR_191_160_BCM56370_A0r */
  15111         soc_block_list[61],
  15112         soc_iprocreg,
  15113         1,
  15114         0,
  15115         0x10038078,
  15116         SOC_REG_FLAG_RO,
  15117         0,
  15118         1,
  15119         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15121         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15122         -1,
  15123         -1,
  15124         3,
  15125     },
  15126 #endif /* chips */
  15127 
  15128 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15129     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  15130     { /* SOC_REG_INT_U3_M0SS_INTR_191_160_BCM56870_A0r */
  15131         soc_block_list[61],
  15132         soc_iprocreg,
  15133         1,
  15134         0,
  15135         0x1338078,
  15136         SOC_REG_FLAG_RO,
  15137         0,
  15138         1,
  15139         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15141         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15142         -1,
  15143         -1,
  15144         3,
  15145     },
  15146 #endif /* chips */
  15147 
  15148 #if defined(BCM_88690_A0)
  15149     { /* SOC_REG_INT_U3_M0SS_INTR_191_160_BCM88690_A0r */
  15150         soc_block_list[61],
  15151         soc_iprocreg,
  15152         1,
  15153         0,
  15154         0x1338078,
  15155         SOC_REG_FLAG_RO,
  15156         0,
  15157         1,
  15158         soc_U3_M0SS_INTR_191_160_BCM88690_A0r_fields,
  15159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15160         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15161         -1,
  15162         -1,
  15163     },
  15164 #endif /* chips */
  15165 
  15166 #if defined(BCM_88690_B0)
  15167     { /* SOC_REG_INT_U3_M0SS_INTR_191_160_BCM88690_B0r */
  15168         soc_block_list[61],
  15169         soc_iprocreg,
  15170         1,
  15171         0,
  15172         0x1338078,
  15173         SOC_REG_FLAG_RO,
  15174         0,
  15175         1,
  15176         soc_U3_M0SS_INTR_191_160_BCM88690_B0r_fields,
  15177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15178         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15179         -1,
  15180         -1,
  15181     },
  15182 #endif /* chips */
  15183 
  15184 #if defined(BCM_88790_A0)
  15185     { /* SOC_REG_INT_U3_M0SS_INTR_223_192r */
  15186         soc_block_list[61],
  15187         soc_iprocreg,
  15188         1,
  15189         0,
  15190         0x133807c,
  15191         SOC_REG_FLAG_RO,
  15192         0,
  15193         1,
  15194         soc_U3_M0SS_INTR_223_192r_fields,
  15195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15196         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15197         -1,
  15198         -1,
  15199     },
  15200 #endif /* chips */
  15201 
  15202 #if defined(BCM_56370_A0)
  15203     { /* SOC_REG_INT_U3_M0SS_INTR_223_192_BCM56370_A0r */
  15204         soc_block_list[61],
  15205         soc_iprocreg,
  15206         1,
  15207         0,
  15208         0x1003807c,
  15209         SOC_REG_FLAG_RO,
  15210         0,
  15211         1,
  15212         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15214         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15215         -1,
  15216         -1,
  15217         3,
  15218     },
  15219 #endif /* chips */
  15220 
  15221 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15222     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  15223     { /* SOC_REG_INT_U3_M0SS_INTR_223_192_BCM56870_A0r */
  15224         soc_block_list[61],
  15225         soc_iprocreg,
  15226         1,
  15227         0,
  15228         0x133807c,
  15229         SOC_REG_FLAG_RO,
  15230         0,
  15231         1,
  15232         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15234         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15235         -1,
  15236         -1,
  15237         3,
  15238     },
  15239 #endif /* chips */
  15240 
  15241 #if defined(BCM_88690_A0)
  15242     { /* SOC_REG_INT_U3_M0SS_INTR_223_192_BCM88690_A0r */
  15243         soc_block_list[61],
  15244         soc_iprocreg,
  15245         1,
  15246         0,
  15247         0x133807c,
  15248         SOC_REG_FLAG_RO,
  15249         0,
  15250         1,
  15251         soc_U3_M0SS_INTR_223_192_BCM88690_A0r_fields,
  15252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15253         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15254         -1,
  15255         -1,
  15256     },
  15257 #endif /* chips */
  15258 
  15259 #if defined(BCM_88690_B0)
  15260     { /* SOC_REG_INT_U3_M0SS_INTR_223_192_BCM88690_B0r */
  15261         soc_block_list[61],
  15262         soc_iprocreg,
  15263         1,
  15264         0,
  15265         0x133807c,
  15266         SOC_REG_FLAG_RO,
  15267         0,
  15268         1,
  15269         soc_U3_M0SS_INTR_223_192_BCM88690_B0r_fields,
  15270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15271         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15272         -1,
  15273         -1,
  15274     },
  15275 #endif /* chips */
  15276 
  15277 #if defined(BCM_88790_A0)
  15278     { /* SOC_REG_INT_U3_M0SS_INTR_255_224r */
  15279         soc_block_list[61],
  15280         soc_iprocreg,
  15281         1,
  15282         0,
  15283         0x1338080,
  15284         SOC_REG_FLAG_RO,
  15285         0,
  15286         1,
  15287         soc_U3_M0SS_INTR_255_224r_fields,
  15288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15289         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15290         -1,
  15291         -1,
  15292     },
  15293 #endif /* chips */
  15294 
  15295 #if defined(BCM_56370_A0)
  15296     { /* SOC_REG_INT_U3_M0SS_INTR_255_224_BCM56370_A0r */
  15297         soc_block_list[61],
  15298         soc_iprocreg,
  15299         1,
  15300         0,
  15301         0x10038080,
  15302         SOC_REG_FLAG_RO,
  15303         0,
  15304         1,
  15305         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15307         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15308         -1,
  15309         -1,
  15310         3,
  15311     },
  15312 #endif /* chips */
  15313 
  15314 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15315     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  15316     { /* SOC_REG_INT_U3_M0SS_INTR_255_224_BCM56870_A0r */
  15317         soc_block_list[61],
  15318         soc_iprocreg,
  15319         1,
  15320         0,
  15321         0x1338080,
  15322         SOC_REG_FLAG_RO,
  15323         0,
  15324         1,
  15325         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15327         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15328         -1,
  15329         -1,
  15330         3,
  15331     },
  15332 #endif /* chips */
  15333 
  15334 #if defined(BCM_88690_A0)
  15335     { /* SOC_REG_INT_U3_M0SS_INTR_255_224_BCM88690_A0r */
  15336         soc_block_list[61],
  15337         soc_iprocreg,
  15338         1,
  15339         0,
  15340         0x1338080,
  15341         SOC_REG_FLAG_RO,
  15342         0,
  15343         1,
  15344         soc_U3_M0SS_INTR_255_224_BCM88690_A0r_fields,
  15345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15346         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15347         -1,
  15348         -1,
  15349     },
  15350 #endif /* chips */
  15351 
  15352 #if defined(BCM_88690_B0)
  15353     { /* SOC_REG_INT_U3_M0SS_INTR_255_224_BCM88690_B0r */
  15354         soc_block_list[61],
  15355         soc_iprocreg,
  15356         1,
  15357         0,
  15358         0x1338080,
  15359         SOC_REG_FLAG_RO,
  15360         0,
  15361         1,
  15362         soc_U3_M0SS_INTR_255_224_BCM88690_B0r_fields,
  15363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15364         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15365         -1,
  15366         -1,
  15367     },
  15368 #endif /* chips */
  15369 
  15370 #if defined(BCM_88790_A0)
  15371     { /* SOC_REG_INT_U3_M0SS_INTR_31_0r */
  15372         soc_block_list[61],
  15373         soc_iprocreg,
  15374         1,
  15375         0,
  15376         0x1338064,
  15377         SOC_REG_FLAG_RO,
  15378         0,
  15379         1,
  15380         soc_U3_M0SS_INTR_31_0r_fields,
  15381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15382         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15383         -1,
  15384         -1,
  15385     },
  15386 #endif /* chips */
  15387 
  15388 #if defined(BCM_56370_A0)
  15389     { /* SOC_REG_INT_U3_M0SS_INTR_31_0_BCM56370_A0r */
  15390         soc_block_list[61],
  15391         soc_iprocreg,
  15392         1,
  15393         0,
  15394         0x10038064,
  15395         SOC_REG_FLAG_RO,
  15396         0,
  15397         1,
  15398         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15400         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15401         -1,
  15402         -1,
  15403         3,
  15404     },
  15405 #endif /* chips */
  15406 
  15407 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15408     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  15409     { /* SOC_REG_INT_U3_M0SS_INTR_31_0_BCM56870_A0r */
  15410         soc_block_list[61],
  15411         soc_iprocreg,
  15412         1,
  15413         0,
  15414         0x1338064,
  15415         SOC_REG_FLAG_RO,
  15416         0,
  15417         1,
  15418         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15420         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15421         -1,
  15422         -1,
  15423         3,
  15424     },
  15425 #endif /* chips */
  15426 
  15427 #if defined(BCM_88690_A0)
  15428     { /* SOC_REG_INT_U3_M0SS_INTR_31_0_BCM88690_A0r */
  15429         soc_block_list[61],
  15430         soc_iprocreg,
  15431         1,
  15432         0,
  15433         0x1338064,
  15434         SOC_REG_FLAG_RO,
  15435         0,
  15436         1,
  15437         soc_U3_M0SS_INTR_31_0_BCM88690_A0r_fields,
  15438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15439         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15440         -1,
  15441         -1,
  15442     },
  15443 #endif /* chips */
  15444 
  15445 #if defined(BCM_88690_B0)
  15446     { /* SOC_REG_INT_U3_M0SS_INTR_31_0_BCM88690_B0r */
  15447         soc_block_list[61],
  15448         soc_iprocreg,
  15449         1,
  15450         0,
  15451         0x1338064,
  15452         SOC_REG_FLAG_RO,
  15453         0,
  15454         1,
  15455         soc_U3_M0SS_INTR_31_0_BCM88690_B0r_fields,
  15456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15457         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15458         -1,
  15459         -1,
  15460     },
  15461 #endif /* chips */
  15462 
  15463 #if defined(BCM_88790_A0)
  15464     { /* SOC_REG_INT_U3_M0SS_INTR_63_32r */
  15465         soc_block_list[61],
  15466         soc_iprocreg,
  15467         1,
  15468         0,
  15469         0x1338068,
  15470         SOC_REG_FLAG_RO,
  15471         0,
  15472         1,
  15473         soc_U3_M0SS_INTR_63_32r_fields,
  15474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15475         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15476         -1,
  15477         -1,
  15478     },
  15479 #endif /* chips */
  15480 
  15481 #if defined(BCM_56370_A0)
  15482     { /* SOC_REG_INT_U3_M0SS_INTR_63_32_BCM56370_A0r */
  15483         soc_block_list[61],
  15484         soc_iprocreg,
  15485         1,
  15486         0,
  15487         0x10038068,
  15488         SOC_REG_FLAG_RO,
  15489         0,
  15490         1,
  15491         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15493         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15494         -1,
  15495         -1,
  15496         3,
  15497     },
  15498 #endif /* chips */
  15499 
  15500 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15501     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  15502     { /* SOC_REG_INT_U3_M0SS_INTR_63_32_BCM56870_A0r */
  15503         soc_block_list[61],
  15504         soc_iprocreg,
  15505         1,
  15506         0,
  15507         0x1338068,
  15508         SOC_REG_FLAG_RO,
  15509         0,
  15510         1,
  15511         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15513         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15514         -1,
  15515         -1,
  15516         3,
  15517     },
  15518 #endif /* chips */
  15519 
  15520 #if defined(BCM_88690_A0)
  15521     { /* SOC_REG_INT_U3_M0SS_INTR_63_32_BCM88690_A0r */
  15522         soc_block_list[61],
  15523         soc_iprocreg,
  15524         1,
  15525         0,
  15526         0x1338068,
  15527         SOC_REG_FLAG_RO,
  15528         0,
  15529         1,
  15530         soc_U3_M0SS_INTR_63_32_BCM88690_A0r_fields,
  15531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15532         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15533         -1,
  15534         -1,
  15535     },
  15536 #endif /* chips */
  15537 
  15538 #if defined(BCM_88690_B0)
  15539     { /* SOC_REG_INT_U3_M0SS_INTR_63_32_BCM88690_B0r */
  15540         soc_block_list[61],
  15541         soc_iprocreg,
  15542         1,
  15543         0,
  15544         0x1338068,
  15545         SOC_REG_FLAG_RO,
  15546         0,
  15547         1,
  15548         soc_U3_M0SS_INTR_63_32_BCM88690_B0r_fields,
  15549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15550         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15551         -1,
  15552         -1,
  15553     },
  15554 #endif /* chips */
  15555 
  15556 #if defined(BCM_88790_A0)
  15557     { /* SOC_REG_INT_U3_M0SS_INTR_95_64r */
  15558         soc_block_list[61],
  15559         soc_iprocreg,
  15560         1,
  15561         0,
  15562         0x133806c,
  15563         SOC_REG_FLAG_RO,
  15564         0,
  15565         1,
  15566         soc_U3_M0SS_INTR_95_64r_fields,
  15567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15568         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15569         -1,
  15570         -1,
  15571     },
  15572 #endif /* chips */
  15573 
  15574 #if defined(BCM_56370_A0)
  15575     { /* SOC_REG_INT_U3_M0SS_INTR_95_64_BCM56370_A0r */
  15576         soc_block_list[61],
  15577         soc_iprocreg,
  15578         1,
  15579         0,
  15580         0x1003806c,
  15581         SOC_REG_FLAG_RO,
  15582         0,
  15583         1,
  15584         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15585         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15586         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15587         -1,
  15588         -1,
  15589         3,
  15590     },
  15591 #endif /* chips */
  15592 
  15593 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15594     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  15595     { /* SOC_REG_INT_U3_M0SS_INTR_95_64_BCM56870_A0r */
  15596         soc_block_list[61],
  15597         soc_iprocreg,
  15598         1,
  15599         0,
  15600         0x133806c,
  15601         SOC_REG_FLAG_RO,
  15602         0,
  15603         1,
  15604         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  15605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15606         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15607         -1,
  15608         -1,
  15609         3,
  15610     },
  15611 #endif /* chips */
  15612 
  15613 #if defined(BCM_88690_A0)
  15614     { /* SOC_REG_INT_U3_M0SS_INTR_95_64_BCM88690_A0r */
  15615         soc_block_list[61],
  15616         soc_iprocreg,
  15617         1,
  15618         0,
  15619         0x133806c,
  15620         SOC_REG_FLAG_RO,
  15621         0,
  15622         1,
  15623         soc_U3_M0SS_INTR_95_64_BCM88690_A0r_fields,
  15624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15625         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15626         -1,
  15627         -1,
  15628     },
  15629 #endif /* chips */
  15630 
  15631 #if defined(BCM_88690_B0)
  15632     { /* SOC_REG_INT_U3_M0SS_INTR_95_64_BCM88690_B0r */
  15633         soc_block_list[61],
  15634         soc_iprocreg,
  15635         1,
  15636         0,
  15637         0x133806c,
  15638         SOC_REG_FLAG_RO,
  15639         0,
  15640         1,
  15641         soc_U3_M0SS_INTR_95_64_BCM88690_B0r_fields,
  15642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15643         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15644         -1,
  15645         -1,
  15646     },
  15647 #endif /* chips */
  15648 
  15649 #if defined(BCM_88790_A0)
  15650     { /* SOC_REG_INT_U3_M0SS_INTR_CONTROLr */
  15651         soc_block_list[61],
  15652         soc_iprocreg,
  15653         1,
  15654         0,
  15655         0x1338004,
  15656         0,
  15657         0,
  15658         3,
  15659         soc_U3_M0SS_INTR_CONTROLr_fields,
  15660         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  15661         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  15662         -1,
  15663         -1,
  15664     },
  15665 #endif /* chips */
  15666 
  15667 #if defined(BCM_56370_A0)
  15668     { /* SOC_REG_INT_U3_M0SS_INTR_CONTROL_BCM56370_A0r */
  15669         soc_block_list[61],
  15670         soc_iprocreg,
  15671         1,
  15672         0,
  15673         0x10038004,
  15674         0,
  15675         0,
  15676         3,
  15677         soc_U0_M0SS_INTR_CONTROL_BCM56870_A0r_fields,
  15678         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  15679         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  15680         -1,
  15681         -1,
  15682         3,
  15683     },
  15684 #endif /* chips */
  15685 
  15686 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15687     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  15688     { /* SOC_REG_INT_U3_M0SS_INTR_CONTROL_BCM56870_A0r */
  15689         soc_block_list[61],
  15690         soc_iprocreg,
  15691         1,
  15692         0,
  15693         0x1338004,
  15694         0,
  15695         0,
  15696         3,
  15697         soc_U0_M0SS_INTR_CONTROL_BCM56870_A0r_fields,
  15698         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  15699         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  15700         -1,
  15701         -1,
  15702         3,
  15703     },
  15704 #endif /* chips */
  15705 
  15706 #if defined(BCM_88690_A0)
  15707     { /* SOC_REG_INT_U3_M0SS_INTR_CONTROL_BCM88690_A0r */
  15708         soc_block_list[61],
  15709         soc_iprocreg,
  15710         1,
  15711         0,
  15712         0x1338004,
  15713         0,
  15714         0,
  15715         3,
  15716         soc_U3_M0SS_INTR_CONTROL_BCM88690_A0r_fields,
  15717         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  15718         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  15719         -1,
  15720         -1,
  15721     },
  15722 #endif /* chips */
  15723 
  15724 #if defined(BCM_88690_B0)
  15725     { /* SOC_REG_INT_U3_M0SS_INTR_CONTROL_BCM88690_B0r */
  15726         soc_block_list[61],
  15727         soc_iprocreg,
  15728         1,
  15729         0,
  15730         0x1338004,
  15731         0,
  15732         0,
  15733         3,
  15734         soc_U3_M0SS_INTR_CONTROL_BCM88690_B0r_fields,
  15735         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  15736         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  15737         -1,
  15738         -1,
  15739     },
  15740 #endif /* chips */
  15741 
  15742 #if defined(BCM_88790_A0)
  15743     { /* SOC_REG_INT_U3_M0SS_INTR_ENABLEr */
  15744         soc_block_list[61],
  15745         soc_iprocreg,
  15746         1,
  15747         0,
  15748         0x1338020,
  15749         0,
  15750         0,
  15751         2,
  15752         soc_U3_M0SS_INTR_ENABLEr_fields,
  15753         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  15754         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15755         -1,
  15756         -1,
  15757     },
  15758 #endif /* chips */
  15759 
  15760 #if defined(BCM_56370_A0)
  15761     { /* SOC_REG_INT_U3_M0SS_INTR_ENABLE_BCM56370_A0r */
  15762         soc_block_list[61],
  15763         soc_iprocreg,
  15764         1,
  15765         0,
  15766         0x10038020,
  15767         0,
  15768         0,
  15769         2,
  15770         soc_U0_M0SSQ_INTR_ENABLE_BCM56870_A0r_fields,
  15771         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  15772         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15773         -1,
  15774         -1,
  15775         3,
  15776     },
  15777 #endif /* chips */
  15778 
  15779 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15780     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  15781     { /* SOC_REG_INT_U3_M0SS_INTR_ENABLE_BCM56870_A0r */
  15782         soc_block_list[61],
  15783         soc_iprocreg,
  15784         1,
  15785         0,
  15786         0x1338020,
  15787         0,
  15788         0,
  15789         2,
  15790         soc_U0_M0SSQ_INTR_ENABLE_BCM56870_A0r_fields,
  15791         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  15792         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15793         -1,
  15794         -1,
  15795         3,
  15796     },
  15797 #endif /* chips */
  15798 
  15799 #if defined(BCM_88690_A0)
  15800     { /* SOC_REG_INT_U3_M0SS_INTR_ENABLE_BCM88690_A0r */
  15801         soc_block_list[61],
  15802         soc_iprocreg,
  15803         1,
  15804         0,
  15805         0x1338020,
  15806         0,
  15807         0,
  15808         2,
  15809         soc_U3_M0SS_INTR_ENABLE_BCM88690_A0r_fields,
  15810         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  15811         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15812         -1,
  15813         -1,
  15814     },
  15815 #endif /* chips */
  15816 
  15817 #if defined(BCM_88690_B0)
  15818     { /* SOC_REG_INT_U3_M0SS_INTR_ENABLE_BCM88690_B0r */
  15819         soc_block_list[61],
  15820         soc_iprocreg,
  15821         1,
  15822         0,
  15823         0x1338020,
  15824         0,
  15825         0,
  15826         2,
  15827         soc_U3_M0SS_INTR_ENABLE_BCM88690_B0r_fields,
  15828         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  15829         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15830         -1,
  15831         -1,
  15832     },
  15833 #endif /* chips */
  15834 
  15835 #if defined(BCM_88790_A0)
  15836     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_127_96r */
  15837         soc_block_list[61],
  15838         soc_iprocreg,
  15839         1,
  15840         0,
  15841         0x1338050,
  15842         0,
  15843         0,
  15844         1,
  15845         soc_U3_M0SS_INTR_MASK_127_96r_fields,
  15846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15847         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15848         -1,
  15849         -1,
  15850     },
  15851 #endif /* chips */
  15852 
  15853 #if defined(BCM_56370_A0)
  15854     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_127_96_BCM56370_A0r */
  15855         soc_block_list[61],
  15856         soc_iprocreg,
  15857         1,
  15858         0,
  15859         0x10038050,
  15860         0,
  15861         0,
  15862         1,
  15863         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  15864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15865         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15866         -1,
  15867         -1,
  15868         3,
  15869     },
  15870 #endif /* chips */
  15871 
  15872 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15873     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  15874     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_127_96_BCM56870_A0r */
  15875         soc_block_list[61],
  15876         soc_iprocreg,
  15877         1,
  15878         0,
  15879         0x1338050,
  15880         0,
  15881         0,
  15882         1,
  15883         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  15884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15885         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15886         -1,
  15887         -1,
  15888         3,
  15889     },
  15890 #endif /* chips */
  15891 
  15892 #if defined(BCM_88690_A0)
  15893     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_127_96_BCM88690_A0r */
  15894         soc_block_list[61],
  15895         soc_iprocreg,
  15896         1,
  15897         0,
  15898         0x1338050,
  15899         0,
  15900         0,
  15901         1,
  15902         soc_U3_M0SS_INTR_MASK_127_96_BCM88690_A0r_fields,
  15903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15904         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15905         -1,
  15906         -1,
  15907     },
  15908 #endif /* chips */
  15909 
  15910 #if defined(BCM_88690_B0)
  15911     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_127_96_BCM88690_B0r */
  15912         soc_block_list[61],
  15913         soc_iprocreg,
  15914         1,
  15915         0,
  15916         0x1338050,
  15917         0,
  15918         0,
  15919         1,
  15920         soc_U3_M0SS_INTR_MASK_127_96_BCM88690_B0r_fields,
  15921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15922         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15923         -1,
  15924         -1,
  15925     },
  15926 #endif /* chips */
  15927 
  15928 #if defined(BCM_88790_A0)
  15929     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_159_128r */
  15930         soc_block_list[61],
  15931         soc_iprocreg,
  15932         1,
  15933         0,
  15934         0x1338054,
  15935         0,
  15936         0,
  15937         1,
  15938         soc_U3_M0SS_INTR_MASK_159_128r_fields,
  15939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15940         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15941         -1,
  15942         -1,
  15943     },
  15944 #endif /* chips */
  15945 
  15946 #if defined(BCM_56370_A0)
  15947     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_159_128_BCM56370_A0r */
  15948         soc_block_list[61],
  15949         soc_iprocreg,
  15950         1,
  15951         0,
  15952         0x10038054,
  15953         0,
  15954         0,
  15955         1,
  15956         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  15957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15958         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15959         -1,
  15960         -1,
  15961         3,
  15962     },
  15963 #endif /* chips */
  15964 
  15965 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15966     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  15967     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_159_128_BCM56870_A0r */
  15968         soc_block_list[61],
  15969         soc_iprocreg,
  15970         1,
  15971         0,
  15972         0x1338054,
  15973         0,
  15974         0,
  15975         1,
  15976         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  15977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15978         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15979         -1,
  15980         -1,
  15981         3,
  15982     },
  15983 #endif /* chips */
  15984 
  15985 #if defined(BCM_88690_A0)
  15986     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_159_128_BCM88690_A0r */
  15987         soc_block_list[61],
  15988         soc_iprocreg,
  15989         1,
  15990         0,
  15991         0x1338054,
  15992         0,
  15993         0,
  15994         1,
  15995         soc_U3_M0SS_INTR_MASK_159_128_BCM88690_A0r_fields,
  15996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15997         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15998         -1,
  15999         -1,
  16000     },
  16001 #endif /* chips */
  16002 
  16003 #if defined(BCM_88690_B0)
  16004     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_159_128_BCM88690_B0r */
  16005         soc_block_list[61],
  16006         soc_iprocreg,
  16007         1,
  16008         0,
  16009         0x1338054,
  16010         0,
  16011         0,
  16012         1,
  16013         soc_U3_M0SS_INTR_MASK_159_128_BCM88690_B0r_fields,
  16014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16016         -1,
  16017         -1,
  16018     },
  16019 #endif /* chips */
  16020 
  16021 #if defined(BCM_88790_A0)
  16022     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_191_160r */
  16023         soc_block_list[61],
  16024         soc_iprocreg,
  16025         1,
  16026         0,
  16027         0x1338058,
  16028         0,
  16029         0,
  16030         1,
  16031         soc_U3_M0SS_INTR_MASK_191_160r_fields,
  16032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16034         -1,
  16035         -1,
  16036     },
  16037 #endif /* chips */
  16038 
  16039 #if defined(BCM_56370_A0)
  16040     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_191_160_BCM56370_A0r */
  16041         soc_block_list[61],
  16042         soc_iprocreg,
  16043         1,
  16044         0,
  16045         0x10038058,
  16046         0,
  16047         0,
  16048         1,
  16049         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16051         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16052         -1,
  16053         -1,
  16054         3,
  16055     },
  16056 #endif /* chips */
  16057 
  16058 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16059     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16060     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_191_160_BCM56870_A0r */
  16061         soc_block_list[61],
  16062         soc_iprocreg,
  16063         1,
  16064         0,
  16065         0x1338058,
  16066         0,
  16067         0,
  16068         1,
  16069         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16071         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16072         -1,
  16073         -1,
  16074         3,
  16075     },
  16076 #endif /* chips */
  16077 
  16078 #if defined(BCM_88690_A0)
  16079     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_191_160_BCM88690_A0r */
  16080         soc_block_list[61],
  16081         soc_iprocreg,
  16082         1,
  16083         0,
  16084         0x1338058,
  16085         0,
  16086         0,
  16087         1,
  16088         soc_U3_M0SS_INTR_MASK_191_160_BCM88690_A0r_fields,
  16089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16090         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16091         -1,
  16092         -1,
  16093     },
  16094 #endif /* chips */
  16095 
  16096 #if defined(BCM_88690_B0)
  16097     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_191_160_BCM88690_B0r */
  16098         soc_block_list[61],
  16099         soc_iprocreg,
  16100         1,
  16101         0,
  16102         0x1338058,
  16103         0,
  16104         0,
  16105         1,
  16106         soc_U3_M0SS_INTR_MASK_191_160_BCM88690_B0r_fields,
  16107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16108         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16109         -1,
  16110         -1,
  16111     },
  16112 #endif /* chips */
  16113 
  16114 #if defined(BCM_88790_A0)
  16115     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_223_192r */
  16116         soc_block_list[61],
  16117         soc_iprocreg,
  16118         1,
  16119         0,
  16120         0x133805c,
  16121         0,
  16122         0,
  16123         1,
  16124         soc_U3_M0SS_INTR_MASK_223_192r_fields,
  16125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16126         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16127         -1,
  16128         -1,
  16129     },
  16130 #endif /* chips */
  16131 
  16132 #if defined(BCM_56370_A0)
  16133     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_223_192_BCM56370_A0r */
  16134         soc_block_list[61],
  16135         soc_iprocreg,
  16136         1,
  16137         0,
  16138         0x1003805c,
  16139         0,
  16140         0,
  16141         1,
  16142         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16144         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16145         -1,
  16146         -1,
  16147         3,
  16148     },
  16149 #endif /* chips */
  16150 
  16151 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16152     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16153     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_223_192_BCM56870_A0r */
  16154         soc_block_list[61],
  16155         soc_iprocreg,
  16156         1,
  16157         0,
  16158         0x133805c,
  16159         0,
  16160         0,
  16161         1,
  16162         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16164         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16165         -1,
  16166         -1,
  16167         3,
  16168     },
  16169 #endif /* chips */
  16170 
  16171 #if defined(BCM_88690_A0)
  16172     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_223_192_BCM88690_A0r */
  16173         soc_block_list[61],
  16174         soc_iprocreg,
  16175         1,
  16176         0,
  16177         0x133805c,
  16178         0,
  16179         0,
  16180         1,
  16181         soc_U3_M0SS_INTR_MASK_223_192_BCM88690_A0r_fields,
  16182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16183         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16184         -1,
  16185         -1,
  16186     },
  16187 #endif /* chips */
  16188 
  16189 #if defined(BCM_88690_B0)
  16190     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_223_192_BCM88690_B0r */
  16191         soc_block_list[61],
  16192         soc_iprocreg,
  16193         1,
  16194         0,
  16195         0x133805c,
  16196         0,
  16197         0,
  16198         1,
  16199         soc_U3_M0SS_INTR_MASK_223_192_BCM88690_B0r_fields,
  16200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16201         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16202         -1,
  16203         -1,
  16204     },
  16205 #endif /* chips */
  16206 
  16207 #if defined(BCM_88790_A0)
  16208     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_255_224r */
  16209         soc_block_list[61],
  16210         soc_iprocreg,
  16211         1,
  16212         0,
  16213         0x1338060,
  16214         0,
  16215         0,
  16216         1,
  16217         soc_U3_M0SS_INTR_MASK_255_224r_fields,
  16218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16219         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16220         -1,
  16221         -1,
  16222     },
  16223 #endif /* chips */
  16224 
  16225 #if defined(BCM_56370_A0)
  16226     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_255_224_BCM56370_A0r */
  16227         soc_block_list[61],
  16228         soc_iprocreg,
  16229         1,
  16230         0,
  16231         0x10038060,
  16232         0,
  16233         0,
  16234         1,
  16235         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16237         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16238         -1,
  16239         -1,
  16240         3,
  16241     },
  16242 #endif /* chips */
  16243 
  16244 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16245     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16246     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_255_224_BCM56870_A0r */
  16247         soc_block_list[61],
  16248         soc_iprocreg,
  16249         1,
  16250         0,
  16251         0x1338060,
  16252         0,
  16253         0,
  16254         1,
  16255         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16258         -1,
  16259         -1,
  16260         3,
  16261     },
  16262 #endif /* chips */
  16263 
  16264 #if defined(BCM_88690_A0)
  16265     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_255_224_BCM88690_A0r */
  16266         soc_block_list[61],
  16267         soc_iprocreg,
  16268         1,
  16269         0,
  16270         0x1338060,
  16271         0,
  16272         0,
  16273         1,
  16274         soc_U3_M0SS_INTR_MASK_255_224_BCM88690_A0r_fields,
  16275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16276         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16277         -1,
  16278         -1,
  16279     },
  16280 #endif /* chips */
  16281 
  16282 #if defined(BCM_88690_B0)
  16283     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_255_224_BCM88690_B0r */
  16284         soc_block_list[61],
  16285         soc_iprocreg,
  16286         1,
  16287         0,
  16288         0x1338060,
  16289         0,
  16290         0,
  16291         1,
  16292         soc_U3_M0SS_INTR_MASK_255_224_BCM88690_B0r_fields,
  16293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16294         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16295         -1,
  16296         -1,
  16297     },
  16298 #endif /* chips */
  16299 
  16300 #if defined(BCM_88790_A0)
  16301     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_31_0r */
  16302         soc_block_list[61],
  16303         soc_iprocreg,
  16304         1,
  16305         0,
  16306         0x1338044,
  16307         0,
  16308         0,
  16309         1,
  16310         soc_U3_M0SS_INTR_MASK_31_0r_fields,
  16311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16312         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16313         -1,
  16314         -1,
  16315     },
  16316 #endif /* chips */
  16317 
  16318 #if defined(BCM_56370_A0)
  16319     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_31_0_BCM56370_A0r */
  16320         soc_block_list[61],
  16321         soc_iprocreg,
  16322         1,
  16323         0,
  16324         0x10038044,
  16325         0,
  16326         0,
  16327         1,
  16328         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16330         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16331         -1,
  16332         -1,
  16333         3,
  16334     },
  16335 #endif /* chips */
  16336 
  16337 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16338     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16339     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_31_0_BCM56870_A0r */
  16340         soc_block_list[61],
  16341         soc_iprocreg,
  16342         1,
  16343         0,
  16344         0x1338044,
  16345         0,
  16346         0,
  16347         1,
  16348         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16350         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16351         -1,
  16352         -1,
  16353         3,
  16354     },
  16355 #endif /* chips */
  16356 
  16357 #if defined(BCM_88690_A0)
  16358     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_31_0_BCM88690_A0r */
  16359         soc_block_list[61],
  16360         soc_iprocreg,
  16361         1,
  16362         0,
  16363         0x1338044,
  16364         0,
  16365         0,
  16366         1,
  16367         soc_U3_M0SS_INTR_MASK_31_0_BCM88690_A0r_fields,
  16368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16369         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16370         -1,
  16371         -1,
  16372     },
  16373 #endif /* chips */
  16374 
  16375 #if defined(BCM_88690_B0)
  16376     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_31_0_BCM88690_B0r */
  16377         soc_block_list[61],
  16378         soc_iprocreg,
  16379         1,
  16380         0,
  16381         0x1338044,
  16382         0,
  16383         0,
  16384         1,
  16385         soc_U3_M0SS_INTR_MASK_31_0_BCM88690_B0r_fields,
  16386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16387         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16388         -1,
  16389         -1,
  16390     },
  16391 #endif /* chips */
  16392 
  16393 #if defined(BCM_88790_A0)
  16394     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_63_32r */
  16395         soc_block_list[61],
  16396         soc_iprocreg,
  16397         1,
  16398         0,
  16399         0x1338048,
  16400         0,
  16401         0,
  16402         1,
  16403         soc_U3_M0SS_INTR_MASK_63_32r_fields,
  16404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16405         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16406         -1,
  16407         -1,
  16408     },
  16409 #endif /* chips */
  16410 
  16411 #if defined(BCM_56370_A0)
  16412     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_63_32_BCM56370_A0r */
  16413         soc_block_list[61],
  16414         soc_iprocreg,
  16415         1,
  16416         0,
  16417         0x10038048,
  16418         0,
  16419         0,
  16420         1,
  16421         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16423         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16424         -1,
  16425         -1,
  16426         3,
  16427     },
  16428 #endif /* chips */
  16429 
  16430 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16431     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16432     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_63_32_BCM56870_A0r */
  16433         soc_block_list[61],
  16434         soc_iprocreg,
  16435         1,
  16436         0,
  16437         0x1338048,
  16438         0,
  16439         0,
  16440         1,
  16441         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16444         -1,
  16445         -1,
  16446         3,
  16447     },
  16448 #endif /* chips */
  16449 
  16450 #if defined(BCM_88690_A0)
  16451     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_63_32_BCM88690_A0r */
  16452         soc_block_list[61],
  16453         soc_iprocreg,
  16454         1,
  16455         0,
  16456         0x1338048,
  16457         0,
  16458         0,
  16459         1,
  16460         soc_U3_M0SS_INTR_MASK_63_32_BCM88690_A0r_fields,
  16461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16462         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16463         -1,
  16464         -1,
  16465     },
  16466 #endif /* chips */
  16467 
  16468 #if defined(BCM_88690_B0)
  16469     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_63_32_BCM88690_B0r */
  16470         soc_block_list[61],
  16471         soc_iprocreg,
  16472         1,
  16473         0,
  16474         0x1338048,
  16475         0,
  16476         0,
  16477         1,
  16478         soc_U3_M0SS_INTR_MASK_63_32_BCM88690_B0r_fields,
  16479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16480         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16481         -1,
  16482         -1,
  16483     },
  16484 #endif /* chips */
  16485 
  16486 #if defined(BCM_88790_A0)
  16487     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_95_64r */
  16488         soc_block_list[61],
  16489         soc_iprocreg,
  16490         1,
  16491         0,
  16492         0x133804c,
  16493         0,
  16494         0,
  16495         1,
  16496         soc_U3_M0SS_INTR_MASK_95_64r_fields,
  16497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16498         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16499         -1,
  16500         -1,
  16501     },
  16502 #endif /* chips */
  16503 
  16504 #if defined(BCM_56370_A0)
  16505     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_95_64_BCM56370_A0r */
  16506         soc_block_list[61],
  16507         soc_iprocreg,
  16508         1,
  16509         0,
  16510         0x1003804c,
  16511         0,
  16512         0,
  16513         1,
  16514         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16516         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16517         -1,
  16518         -1,
  16519         3,
  16520     },
  16521 #endif /* chips */
  16522 
  16523 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16524     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16525     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_95_64_BCM56870_A0r */
  16526         soc_block_list[61],
  16527         soc_iprocreg,
  16528         1,
  16529         0,
  16530         0x133804c,
  16531         0,
  16532         0,
  16533         1,
  16534         soc_U0_M0SS_INTR_MASK_127_96_BCM56870_A0r_fields,
  16535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16536         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16537         -1,
  16538         -1,
  16539         3,
  16540     },
  16541 #endif /* chips */
  16542 
  16543 #if defined(BCM_88690_A0)
  16544     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_95_64_BCM88690_A0r */
  16545         soc_block_list[61],
  16546         soc_iprocreg,
  16547         1,
  16548         0,
  16549         0x133804c,
  16550         0,
  16551         0,
  16552         1,
  16553         soc_U3_M0SS_INTR_MASK_95_64_BCM88690_A0r_fields,
  16554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16555         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16556         -1,
  16557         -1,
  16558     },
  16559 #endif /* chips */
  16560 
  16561 #if defined(BCM_88690_B0)
  16562     { /* SOC_REG_INT_U3_M0SS_INTR_MASK_95_64_BCM88690_B0r */
  16563         soc_block_list[61],
  16564         soc_iprocreg,
  16565         1,
  16566         0,
  16567         0x133804c,
  16568         0,
  16569         0,
  16570         1,
  16571         soc_U3_M0SS_INTR_MASK_95_64_BCM88690_B0r_fields,
  16572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16573         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16574         -1,
  16575         -1,
  16576     },
  16577 #endif /* chips */
  16578 
  16579 #if defined(BCM_88790_A0)
  16580     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_127_96r */
  16581         soc_block_list[61],
  16582         soc_iprocreg,
  16583         1,
  16584         0,
  16585         0x1338030,
  16586         SOC_REG_FLAG_RO,
  16587         0,
  16588         1,
  16589         soc_U3_M0SS_RAW_INTR_127_96r_fields,
  16590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16591         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16592         -1,
  16593         -1,
  16594     },
  16595 #endif /* chips */
  16596 
  16597 #if defined(BCM_56370_A0)
  16598     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_127_96_BCM56370_A0r */
  16599         soc_block_list[61],
  16600         soc_iprocreg,
  16601         1,
  16602         0,
  16603         0x10038030,
  16604         SOC_REG_FLAG_RO,
  16605         0,
  16606         1,
  16607         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  16608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16609         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16610         -1,
  16611         -1,
  16612         3,
  16613     },
  16614 #endif /* chips */
  16615 
  16616 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16617     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16618     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_127_96_BCM56870_A0r */
  16619         soc_block_list[61],
  16620         soc_iprocreg,
  16621         1,
  16622         0,
  16623         0x1338030,
  16624         SOC_REG_FLAG_RO,
  16625         0,
  16626         1,
  16627         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  16628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16629         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16630         -1,
  16631         -1,
  16632         3,
  16633     },
  16634 #endif /* chips */
  16635 
  16636 #if defined(BCM_88690_A0)
  16637     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_127_96_BCM88690_A0r */
  16638         soc_block_list[61],
  16639         soc_iprocreg,
  16640         1,
  16641         0,
  16642         0x1338030,
  16643         SOC_REG_FLAG_RO,
  16644         0,
  16645         1,
  16646         soc_U3_M0SS_RAW_INTR_127_96_BCM88690_A0r_fields,
  16647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16648         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16649         -1,
  16650         -1,
  16651     },
  16652 #endif /* chips */
  16653 
  16654 #if defined(BCM_88690_B0)
  16655     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_127_96_BCM88690_B0r */
  16656         soc_block_list[61],
  16657         soc_iprocreg,
  16658         1,
  16659         0,
  16660         0x1338030,
  16661         SOC_REG_FLAG_RO,
  16662         0,
  16663         1,
  16664         soc_U3_M0SS_RAW_INTR_127_96_BCM88690_B0r_fields,
  16665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16666         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16667         -1,
  16668         -1,
  16669     },
  16670 #endif /* chips */
  16671 
  16672 #if defined(BCM_88790_A0)
  16673     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_159_128r */
  16674         soc_block_list[61],
  16675         soc_iprocreg,
  16676         1,
  16677         0,
  16678         0x1338034,
  16679         SOC_REG_FLAG_RO,
  16680         0,
  16681         1,
  16682         soc_U3_M0SS_RAW_INTR_159_128r_fields,
  16683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16685         -1,
  16686         -1,
  16687     },
  16688 #endif /* chips */
  16689 
  16690 #if defined(BCM_56370_A0)
  16691     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_159_128_BCM56370_A0r */
  16692         soc_block_list[61],
  16693         soc_iprocreg,
  16694         1,
  16695         0,
  16696         0x10038034,
  16697         SOC_REG_FLAG_RO,
  16698         0,
  16699         1,
  16700         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  16701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16703         -1,
  16704         -1,
  16705         3,
  16706     },
  16707 #endif /* chips */
  16708 
  16709 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16710     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16711     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_159_128_BCM56870_A0r */
  16712         soc_block_list[61],
  16713         soc_iprocreg,
  16714         1,
  16715         0,
  16716         0x1338034,
  16717         SOC_REG_FLAG_RO,
  16718         0,
  16719         1,
  16720         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  16721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16722         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16723         -1,
  16724         -1,
  16725         3,
  16726     },
  16727 #endif /* chips */
  16728 
  16729 #if defined(BCM_88690_A0)
  16730     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_159_128_BCM88690_A0r */
  16731         soc_block_list[61],
  16732         soc_iprocreg,
  16733         1,
  16734         0,
  16735         0x1338034,
  16736         SOC_REG_FLAG_RO,
  16737         0,
  16738         1,
  16739         soc_U3_M0SS_RAW_INTR_159_128_BCM88690_A0r_fields,
  16740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16741         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16742         -1,
  16743         -1,
  16744     },
  16745 #endif /* chips */
  16746 
  16747 #if defined(BCM_88690_B0)
  16748     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_159_128_BCM88690_B0r */
  16749         soc_block_list[61],
  16750         soc_iprocreg,
  16751         1,
  16752         0,
  16753         0x1338034,
  16754         SOC_REG_FLAG_RO,
  16755         0,
  16756         1,
  16757         soc_U3_M0SS_RAW_INTR_159_128_BCM88690_B0r_fields,
  16758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16760         -1,
  16761         -1,
  16762     },
  16763 #endif /* chips */
  16764 
  16765 #if defined(BCM_88790_A0)
  16766     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_191_160r */
  16767         soc_block_list[61],
  16768         soc_iprocreg,
  16769         1,
  16770         0,
  16771         0x1338038,
  16772         SOC_REG_FLAG_RO,
  16773         0,
  16774         1,
  16775         soc_U3_M0SS_RAW_INTR_191_160r_fields,
  16776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16778         -1,
  16779         -1,
  16780     },
  16781 #endif /* chips */
  16782 
  16783 #if defined(BCM_56370_A0)
  16784     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_191_160_BCM56370_A0r */
  16785         soc_block_list[61],
  16786         soc_iprocreg,
  16787         1,
  16788         0,
  16789         0x10038038,
  16790         SOC_REG_FLAG_RO,
  16791         0,
  16792         1,
  16793         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  16794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16796         -1,
  16797         -1,
  16798         3,
  16799     },
  16800 #endif /* chips */
  16801 
  16802 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16803     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16804     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_191_160_BCM56870_A0r */
  16805         soc_block_list[61],
  16806         soc_iprocreg,
  16807         1,
  16808         0,
  16809         0x1338038,
  16810         SOC_REG_FLAG_RO,
  16811         0,
  16812         1,
  16813         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  16814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16815         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16816         -1,
  16817         -1,
  16818         3,
  16819     },
  16820 #endif /* chips */
  16821 
  16822 #if defined(BCM_88690_A0)
  16823     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_191_160_BCM88690_A0r */
  16824         soc_block_list[61],
  16825         soc_iprocreg,
  16826         1,
  16827         0,
  16828         0x1338038,
  16829         SOC_REG_FLAG_RO,
  16830         0,
  16831         1,
  16832         soc_U3_M0SS_RAW_INTR_191_160_BCM88690_A0r_fields,
  16833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16834         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16835         -1,
  16836         -1,
  16837     },
  16838 #endif /* chips */
  16839 
  16840 #if defined(BCM_88690_B0)
  16841     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_191_160_BCM88690_B0r */
  16842         soc_block_list[61],
  16843         soc_iprocreg,
  16844         1,
  16845         0,
  16846         0x1338038,
  16847         SOC_REG_FLAG_RO,
  16848         0,
  16849         1,
  16850         soc_U3_M0SS_RAW_INTR_191_160_BCM88690_B0r_fields,
  16851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16852         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16853         -1,
  16854         -1,
  16855     },
  16856 #endif /* chips */
  16857 
  16858 #if defined(BCM_88790_A0)
  16859     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_223_192r */
  16860         soc_block_list[61],
  16861         soc_iprocreg,
  16862         1,
  16863         0,
  16864         0x133803c,
  16865         SOC_REG_FLAG_RO,
  16866         0,
  16867         1,
  16868         soc_U3_M0SS_RAW_INTR_223_192r_fields,
  16869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16870         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16871         -1,
  16872         -1,
  16873     },
  16874 #endif /* chips */
  16875 
  16876 #if defined(BCM_56370_A0)
  16877     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_223_192_BCM56370_A0r */
  16878         soc_block_list[61],
  16879         soc_iprocreg,
  16880         1,
  16881         0,
  16882         0x1003803c,
  16883         SOC_REG_FLAG_RO,
  16884         0,
  16885         1,
  16886         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  16887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16889         -1,
  16890         -1,
  16891         3,
  16892     },
  16893 #endif /* chips */
  16894 
  16895 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16896     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16897     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_223_192_BCM56870_A0r */
  16898         soc_block_list[61],
  16899         soc_iprocreg,
  16900         1,
  16901         0,
  16902         0x133803c,
  16903         SOC_REG_FLAG_RO,
  16904         0,
  16905         1,
  16906         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  16907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16908         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16909         -1,
  16910         -1,
  16911         3,
  16912     },
  16913 #endif /* chips */
  16914 
  16915 #if defined(BCM_88690_A0)
  16916     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_223_192_BCM88690_A0r */
  16917         soc_block_list[61],
  16918         soc_iprocreg,
  16919         1,
  16920         0,
  16921         0x133803c,
  16922         SOC_REG_FLAG_RO,
  16923         0,
  16924         1,
  16925         soc_U3_M0SS_RAW_INTR_223_192_BCM88690_A0r_fields,
  16926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16927         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16928         -1,
  16929         -1,
  16930     },
  16931 #endif /* chips */
  16932 
  16933 #if defined(BCM_88690_B0)
  16934     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_223_192_BCM88690_B0r */
  16935         soc_block_list[61],
  16936         soc_iprocreg,
  16937         1,
  16938         0,
  16939         0x133803c,
  16940         SOC_REG_FLAG_RO,
  16941         0,
  16942         1,
  16943         soc_U3_M0SS_RAW_INTR_223_192_BCM88690_B0r_fields,
  16944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16946         -1,
  16947         -1,
  16948     },
  16949 #endif /* chips */
  16950 
  16951 #if defined(BCM_88790_A0)
  16952     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_255_224r */
  16953         soc_block_list[61],
  16954         soc_iprocreg,
  16955         1,
  16956         0,
  16957         0x1338040,
  16958         SOC_REG_FLAG_RO,
  16959         0,
  16960         1,
  16961         soc_U3_M0SS_RAW_INTR_255_224r_fields,
  16962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16964         -1,
  16965         -1,
  16966     },
  16967 #endif /* chips */
  16968 
  16969 #if defined(BCM_56370_A0)
  16970     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_255_224_BCM56370_A0r */
  16971         soc_block_list[61],
  16972         soc_iprocreg,
  16973         1,
  16974         0,
  16975         0x10038040,
  16976         SOC_REG_FLAG_RO,
  16977         0,
  16978         1,
  16979         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  16980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16981         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16982         -1,
  16983         -1,
  16984         3,
  16985     },
  16986 #endif /* chips */
  16987 
  16988 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16989     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  16990     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_255_224_BCM56870_A0r */
  16991         soc_block_list[61],
  16992         soc_iprocreg,
  16993         1,
  16994         0,
  16995         0x1338040,
  16996         SOC_REG_FLAG_RO,
  16997         0,
  16998         1,
  16999         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  17000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17001         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17002         -1,
  17003         -1,
  17004         3,
  17005     },
  17006 #endif /* chips */
  17007 
  17008 #if defined(BCM_88690_A0)
  17009     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_255_224_BCM88690_A0r */
  17010         soc_block_list[61],
  17011         soc_iprocreg,
  17012         1,
  17013         0,
  17014         0x1338040,
  17015         SOC_REG_FLAG_RO,
  17016         0,
  17017         1,
  17018         soc_U3_M0SS_RAW_INTR_255_224_BCM88690_A0r_fields,
  17019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17020         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17021         -1,
  17022         -1,
  17023     },
  17024 #endif /* chips */
  17025 
  17026 #if defined(BCM_88690_B0)
  17027     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_255_224_BCM88690_B0r */
  17028         soc_block_list[61],
  17029         soc_iprocreg,
  17030         1,
  17031         0,
  17032         0x1338040,
  17033         SOC_REG_FLAG_RO,
  17034         0,
  17035         1,
  17036         soc_U3_M0SS_RAW_INTR_255_224_BCM88690_B0r_fields,
  17037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17038         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17039         -1,
  17040         -1,
  17041     },
  17042 #endif /* chips */
  17043 
  17044 #if defined(BCM_88790_A0)
  17045     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_31_0r */
  17046         soc_block_list[61],
  17047         soc_iprocreg,
  17048         1,
  17049         0,
  17050         0x1338024,
  17051         SOC_REG_FLAG_RO,
  17052         0,
  17053         1,
  17054         soc_U3_M0SS_RAW_INTR_31_0r_fields,
  17055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17056         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17057         -1,
  17058         -1,
  17059     },
  17060 #endif /* chips */
  17061 
  17062 #if defined(BCM_56370_A0)
  17063     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_31_0_BCM56370_A0r */
  17064         soc_block_list[61],
  17065         soc_iprocreg,
  17066         1,
  17067         0,
  17068         0x10038024,
  17069         SOC_REG_FLAG_RO,
  17070         0,
  17071         1,
  17072         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  17073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17074         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17075         -1,
  17076         -1,
  17077         3,
  17078     },
  17079 #endif /* chips */
  17080 
  17081 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  17082     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  17083     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_31_0_BCM56870_A0r */
  17084         soc_block_list[61],
  17085         soc_iprocreg,
  17086         1,
  17087         0,
  17088         0x1338024,
  17089         SOC_REG_FLAG_RO,
  17090         0,
  17091         1,
  17092         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  17093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17094         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17095         -1,
  17096         -1,
  17097         3,
  17098     },
  17099 #endif /* chips */
  17100 
  17101 #if defined(BCM_88690_A0)
  17102     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_31_0_BCM88690_A0r */
  17103         soc_block_list[61],
  17104         soc_iprocreg,
  17105         1,
  17106         0,
  17107         0x1338024,
  17108         SOC_REG_FLAG_RO,
  17109         0,
  17110         1,
  17111         soc_U3_M0SS_RAW_INTR_31_0_BCM88690_A0r_fields,
  17112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17113         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17114         -1,
  17115         -1,
  17116     },
  17117 #endif /* chips */
  17118 
  17119 #if defined(BCM_88690_B0)
  17120     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_31_0_BCM88690_B0r */
  17121         soc_block_list[61],
  17122         soc_iprocreg,
  17123         1,
  17124         0,
  17125         0x1338024,
  17126         SOC_REG_FLAG_RO,
  17127         0,
  17128         1,
  17129         soc_U3_M0SS_RAW_INTR_31_0_BCM88690_B0r_fields,
  17130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17132         -1,
  17133         -1,
  17134     },
  17135 #endif /* chips */
  17136 
  17137 #if defined(BCM_88790_A0)
  17138     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_63_32r */
  17139         soc_block_list[61],
  17140         soc_iprocreg,
  17141         1,
  17142         0,
  17143         0x1338028,
  17144         SOC_REG_FLAG_RO,
  17145         0,
  17146         1,
  17147         soc_U3_M0SS_RAW_INTR_63_32r_fields,
  17148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17149         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17150         -1,
  17151         -1,
  17152     },
  17153 #endif /* chips */
  17154 
  17155 #if defined(BCM_56370_A0)
  17156     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_63_32_BCM56370_A0r */
  17157         soc_block_list[61],
  17158         soc_iprocreg,
  17159         1,
  17160         0,
  17161         0x10038028,
  17162         SOC_REG_FLAG_RO,
  17163         0,
  17164         1,
  17165         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  17166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17168         -1,
  17169         -1,
  17170         3,
  17171     },
  17172 #endif /* chips */
  17173 
  17174 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  17175     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  17176     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_63_32_BCM56870_A0r */
  17177         soc_block_list[61],
  17178         soc_iprocreg,
  17179         1,
  17180         0,
  17181         0x1338028,
  17182         SOC_REG_FLAG_RO,
  17183         0,
  17184         1,
  17185         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  17186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17187         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17188         -1,
  17189         -1,
  17190         3,
  17191     },
  17192 #endif /* chips */
  17193 
  17194 #if defined(BCM_88690_A0)
  17195     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_63_32_BCM88690_A0r */
  17196         soc_block_list[61],
  17197         soc_iprocreg,
  17198         1,
  17199         0,
  17200         0x1338028,
  17201         SOC_REG_FLAG_RO,
  17202         0,
  17203         1,
  17204         soc_U3_M0SS_RAW_INTR_63_32_BCM88690_A0r_fields,
  17205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17206         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17207         -1,
  17208         -1,
  17209     },
  17210 #endif /* chips */
  17211 
  17212 #if defined(BCM_88690_B0)
  17213     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_63_32_BCM88690_B0r */
  17214         soc_block_list[61],
  17215         soc_iprocreg,
  17216         1,
  17217         0,
  17218         0x1338028,
  17219         SOC_REG_FLAG_RO,
  17220         0,
  17221         1,
  17222         soc_U3_M0SS_RAW_INTR_63_32_BCM88690_B0r_fields,
  17223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17224         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17225         -1,
  17226         -1,
  17227     },
  17228 #endif /* chips */
  17229 
  17230 #if defined(BCM_88790_A0)
  17231     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_95_64r */
  17232         soc_block_list[61],
  17233         soc_iprocreg,
  17234         1,
  17235         0,
  17236         0x133802c,
  17237         SOC_REG_FLAG_RO,
  17238         0,
  17239         1,
  17240         soc_U3_M0SS_RAW_INTR_95_64r_fields,
  17241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17242         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17243         -1,
  17244         -1,
  17245     },
  17246 #endif /* chips */
  17247 
  17248 #if defined(BCM_56370_A0)
  17249     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_95_64_BCM56370_A0r */
  17250         soc_block_list[61],
  17251         soc_iprocreg,
  17252         1,
  17253         0,
  17254         0x1003802c,
  17255         SOC_REG_FLAG_RO,
  17256         0,
  17257         1,
  17258         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  17259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17260         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17261         -1,
  17262         -1,
  17263         3,
  17264     },
  17265 #endif /* chips */
  17266 
  17267 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  17268     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  17269     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_95_64_BCM56870_A0r */
  17270         soc_block_list[61],
  17271         soc_iprocreg,
  17272         1,
  17273         0,
  17274         0x133802c,
  17275         SOC_REG_FLAG_RO,
  17276         0,
  17277         1,
  17278         soc_DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_fields,
  17279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17280         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17281         -1,
  17282         -1,
  17283         3,
  17284     },
  17285 #endif /* chips */
  17286 
  17287 #if defined(BCM_88690_A0)
  17288     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_95_64_BCM88690_A0r */
  17289         soc_block_list[61],
  17290         soc_iprocreg,
  17291         1,
  17292         0,
  17293         0x133802c,
  17294         SOC_REG_FLAG_RO,
  17295         0,
  17296         1,
  17297         soc_U3_M0SS_RAW_INTR_95_64_BCM88690_A0r_fields,
  17298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17300         -1,
  17301         -1,
  17302     },
  17303 #endif /* chips */
  17304 
  17305 #if defined(BCM_88690_B0)
  17306     { /* SOC_REG_INT_U3_M0SS_RAW_INTR_95_64_BCM88690_B0r */
  17307         soc_block_list[61],
  17308         soc_iprocreg,
  17309         1,
  17310         0,
  17311         0x133802c,
  17312         SOC_REG_FLAG_RO,
  17313         0,
  17314         1,
  17315         soc_U3_M0SS_RAW_INTR_95_64_BCM88690_B0r_fields,
  17316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17318         -1,
  17319         -1,
  17320     },
  17321 #endif /* chips */
  17322 
  17323 #if defined(BCM_88790_A0)
  17324     { /* SOC_REG_INT_U3_M0SS_STATUSr */
  17325         soc_block_list[61],
  17326         soc_iprocreg,
  17327         1,
  17328         0,
  17329         0x1338010,
  17330         0,
  17331         0,
  17332         10,
  17333         soc_U3_M0SS_STATUSr_fields,
  17334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17335         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
  17336         -1,
  17337         -1,
  17338     },
  17339 #endif /* chips */
  17340 
  17341 #if defined(BCM_56370_A0)
  17342     { /* SOC_REG_INT_U3_M0SS_STATUS_BCM56370_A0r */
  17343         soc_block_list[61],
  17344         soc_iprocreg,
  17345         1,
  17346         0,
  17347         0x10038010,
  17348         0,
  17349         0,
  17350         10,
  17351         soc_U0_M0SS_STATUS_BCM56870_A0r_fields,
  17352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17353         SOC_RESET_MASK_DEC(0xffff001f, 0x00000000)
  17354         -1,
  17355         -1,
  17356         3,
  17357     },
  17358 #endif /* chips */
  17359 
  17360 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  17361     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  17362     { /* SOC_REG_INT_U3_M0SS_STATUS_BCM56870_A0r */
  17363         soc_block_list[61],
  17364         soc_iprocreg,
  17365         1,
  17366         0,
  17367         0x1338010,
  17368         0,
  17369         0,
  17370         10,
  17371         soc_U0_M0SS_STATUS_BCM56870_A0r_fields,
  17372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17373         SOC_RESET_MASK_DEC(0xffff001f, 0x00000000)
  17374         -1,
  17375         -1,
  17376         3,
  17377     },
  17378 #endif /* chips */
  17379 
  17380 #if defined(BCM_88690_A0)
  17381     { /* SOC_REG_INT_U3_M0SS_STATUS_BCM88690_A0r */
  17382         soc_block_list[61],
  17383         soc_iprocreg,
  17384         1,
  17385         0,
  17386         0x1338010,
  17387         0,
  17388         0,
  17389         10,
  17390         soc_U3_M0SS_STATUS_BCM88690_A0r_fields,
  17391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17392         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
  17393         -1,
  17394         -1,
  17395     },
  17396 #endif /* chips */
  17397 
  17398 #if defined(BCM_88690_B0)
  17399     { /* SOC_REG_INT_U3_M0SS_STATUS_BCM88690_B0r */
  17400         soc_block_list[61],
  17401         soc_iprocreg,
  17402         1,
  17403         0,
  17404         0x1338010,
  17405         0,
  17406         0,
  17407         10,
  17408         soc_U3_M0SS_STATUS_BCM88690_B0r_fields,
  17409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17410         SOC_RESET_MASK_DEC(0xffff0f1f, 0x00000000)
  17411         -1,
  17412         -1,
  17413     },
  17414 #endif /* chips */
  17415 
  17416 #if defined(BCM_88790_A0)
  17417     { /* SOC_REG_INT_U3_M0SS_TCM_CTRLr */
  17418         soc_block_list[61],
  17419         soc_iprocreg,
  17420         1,
  17421         0,
  17422         0x1338014,
  17423         0,
  17424         0,
  17425         1,
  17426         soc_U3_M0SS_TCM_CTRLr_fields,
  17427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17428         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17429         -1,
  17430         -1,
  17431     },
  17432 #endif /* chips */
  17433 
  17434 #if defined(BCM_56370_A0)
  17435     { /* SOC_REG_INT_U3_M0SS_TCM_CTRL_BCM56370_A0r */
  17436         soc_block_list[61],
  17437         soc_iprocreg,
  17438         1,
  17439         0,
  17440         0x10038014,
  17441         0,
  17442         0,
  17443         1,
  17444         soc_U0_M0SS_TCM_CTRL_BCM56870_A0r_fields,
  17445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17446         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17447         -1,
  17448         -1,
  17449         3,
  17450     },
  17451 #endif /* chips */
  17452 
  17453 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  17454     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  17455     { /* SOC_REG_INT_U3_M0SS_TCM_CTRL_BCM56870_A0r */
  17456         soc_block_list[61],
  17457         soc_iprocreg,
  17458         1,
  17459         0,
  17460         0x1338014,
  17461         0,
  17462         0,
  17463         1,
  17464         soc_U0_M0SS_TCM_CTRL_BCM56870_A0r_fields,
  17465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17466         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17467         -1,
  17468         -1,
  17469         3,
  17470     },
  17471 #endif /* chips */
  17472 
  17473 #if defined(BCM_88690_A0)
  17474     { /* SOC_REG_INT_U3_M0SS_TCM_CTRL_BCM88690_A0r */
  17475         soc_block_list[61],
  17476         soc_iprocreg,
  17477         1,
  17478         0,
  17479         0x1338014,
  17480         0,
  17481         0,
  17482         1,
  17483         soc_U3_M0SS_TCM_CTRL_BCM88690_A0r_fields,
  17484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17485         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17486         -1,
  17487         -1,
  17488     },
  17489 #endif /* chips */
  17490 
  17491 #if defined(BCM_88690_B0)
  17492     { /* SOC_REG_INT_U3_M0SS_TCM_CTRL_BCM88690_B0r */
  17493         soc_block_list[61],
  17494         soc_iprocreg,
  17495         1,
  17496         0,
  17497         0x1338014,
  17498         0,
  17499         0,
  17500         1,
  17501         soc_U3_M0SS_TCM_CTRL_BCM88690_B0r_fields,
  17502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17503         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  17504         -1,
  17505         -1,
  17506     },
  17507 #endif /* chips */
  17508 
  17509 #if defined(BCM_56370_A0)
  17510     { /* SOC_REG_INT_U3_SW_PROG_INTR_CLRr */
  17511         soc_block_list[61],
  17512         soc_iprocreg,
  17513         1,
  17514         0,
  17515         0x10038090,
  17516         0,
  17517         0,
  17518         1,
  17519         soc_PAXB_0_SW_PROG_INTR_CLRr_fields,
  17520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17521         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17522         -1,
  17523         -1,
  17524         3,
  17525     },
  17526 #endif /* chips */
  17527 
  17528 #if defined(BCM_56370_A0)
  17529     { /* SOC_REG_INT_U3_SW_PROG_INTR_ENABLEr */
  17530         soc_block_list[61],
  17531         soc_iprocreg,
  17532         1,
  17533         0,
  17534         0x10038084,
  17535         0,
  17536         0,
  17537         1,
  17538         soc_MIIM_DMA_CH0_DST_HOST_ADDRESS_BCM56870_A0r_fields,
  17539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17540         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17541         -1,
  17542         -1,
  17543         3,
  17544     },
  17545 #endif /* chips */
  17546 
  17547 #if defined(BCM_56370_A0)
  17548     { /* SOC_REG_INT_U3_SW_PROG_INTR_SETr */
  17549         soc_block_list[61],
  17550         soc_iprocreg,
  17551         1,
  17552         0,
  17553         0x1003808c,
  17554         0,
  17555         0,
  17556         1,
  17557         soc_PAXB_0_SW_PROG_INTR_CLRr_fields,
  17558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17559         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17560         -1,
  17561         -1,
  17562         3,
  17563     },
  17564 #endif /* chips */
  17565 
  17566 #if defined(BCM_56370_A0)
  17567     { /* SOC_REG_INT_U3_SW_PROG_INTR_STATUSr */
  17568         soc_block_list[61],
  17569         soc_iprocreg,
  17570         1,
  17571         0,
  17572         0x10038088,
  17573         SOC_REG_FLAG_RO,
  17574         0,
  17575         1,
  17576         soc_MIIM_DMA_CH0_CURR_DST_HOST_ADDRESS_BCM56870_A0r_fields,
  17577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17578         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17579         -1,
  17580         -1,
  17581         3,
  17582     },
  17583 #endif /* chips */
  17584 
  17585 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  17586     { /* SOC_REG_INT_UCQDBMEMDEBUGr */
  17587         soc_block_list[4],
  17588         soc_genreg,
  17589         1,
  17590         0,
  17591         0x12002300,
  17592         0,
  17593         0,
  17594         1,
  17595         soc_UCQDBMEMDEBUGr_fields,
  17596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17597         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17598         -1,
  17599         -1,
  17600     },
  17601 #endif /* chips */
  17602 
  17603 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  17604     { /* SOC_REG_INT_UCQRPMEMDEBUGr */
  17605         soc_block_list[4],
  17606         soc_genreg,
  17607         1,
  17608         0,
  17609         0x4080024,
  17610         0,
  17611         0,
  17612         1,
  17613         soc_CFAPMEMDEBUGr_fields,
  17614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17615         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17616         -1,
  17617         -1,
  17618     },
  17619 #endif /* chips */
  17620 
  17621 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  17622     { /* SOC_REG_INT_UCQWPMEMDEBUGr */
  17623         soc_block_list[4],
  17624         soc_genreg,
  17625         1,
  17626         0,
  17627         0x4080023,
  17628         0,
  17629         0,
  17630         1,
  17631         soc_CFAPMEMDEBUGr_fields,
  17632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17633         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17634         -1,
  17635         -1,
  17636     },
  17637 #endif /* chips */
  17638 
  17639 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  17640     { /* SOC_REG_INT_UCQ_CONFIGr */
  17641         soc_block_list[4],
  17642         soc_genreg,
  17643         1,
  17644         0,
  17645         0x12000100,
  17646         0,
  17647         0,
  17648         1,
  17649         soc_UCQ_CONFIGr_fields,
  17650         SOC_RESET_VAL_DEC(0x000003f0, 0x00000000)
  17651         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  17652         -1,
  17653         -1,
  17654     },
  17655 #endif /* chips */
  17656 
  17657 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  17658     { /* SOC_REG_INT_UCQ_COS_EMPTY_REGr */
  17659         soc_block_list[4],
  17660         soc_portreg,
  17661         1,
  17662         0,
  17663         0x4000110,
  17664         SOC_REG_FLAG_RO,
  17665         0,
  17666         1,
  17667         soc_UCQ_COS_EMPTY_REGr_fields,
  17668         SOC_RESET_VAL_DEC(0x000003ff, 0x00000000)
  17669         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  17670         -1,
  17671         37,
  17672     },
  17673 #endif /* chips */
  17674 
  17675 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  17676     { /* SOC_REG_INT_UCQ_EXTCOS1_EMPTY_REGr */
  17677         soc_block_list[4],
  17678         soc_portreg,
  17679         1,
  17680         0,
  17681         0x4000120,
  17682         SOC_REG_FLAG_64_BITS |
  17683                           SOC_REG_FLAG_RO,
  17684         0,
  17685         1,
  17686         soc_UCQ_EXTCOS1_EMPTY_REGr_fields,
  17687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17688         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17689         -1,
  17690         36,
  17691     },
  17692 #endif /* chips */
  17693 
  17694 #if defined(BCM_56640_A0)
  17695     { /* SOC_REG_INT_UCQ_FREE_MEMDEBUGr */
  17696         soc_block_list[4],
  17697         soc_genreg,
  17698         1,
  17699         0,
  17700         0x1a008100,
  17701         0,
  17702         0,
  17703         1,
  17704         soc_UCQ_FREE_MEMDEBUGr_fields,
  17705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17706         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17707         -1,
  17708         -1,
  17709     },
  17710 #endif /* chips */
  17711 
  17712 #if defined(BCM_56640_A0)
  17713     { /* SOC_REG_INT_UCQ_FREE_MEMECC_ERRPTRr */
  17714         soc_block_list[4],
  17715         soc_genreg,
  17716         1,
  17717         0,
  17718         0x1a008900,
  17719         SOC_REG_FLAG_RO,
  17720         0,
  17721         1,
  17722         soc_UCQ_FREE_MEMECC_ERRPTRr_fields,
  17723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17724         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  17725         -1,
  17726         -1,
  17727     },
  17728 #endif /* chips */
  17729 
  17730 #if defined(BCM_56640_A0)
  17731     { /* SOC_REG_INT_UCQ_UCQE0_MEMDEBUGr */
  17732         soc_block_list[4],
  17733         soc_genreg,
  17734         1,
  17735         0,
  17736         0x1a008200,
  17737         0,
  17738         0,
  17739         1,
  17740         soc_UCQ_FREE_MEMDEBUGr_fields,
  17741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17742         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17743         -1,
  17744         -1,
  17745     },
  17746 #endif /* chips */
  17747 
  17748 #if defined(BCM_56640_A0)
  17749     { /* SOC_REG_INT_UCQ_UCQE1_MEMDEBUGr */
  17750         soc_block_list[4],
  17751         soc_genreg,
  17752         1,
  17753         0,
  17754         0x1a008300,
  17755         0,
  17756         0,
  17757         1,
  17758         soc_UCQ_FREE_MEMDEBUGr_fields,
  17759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17760         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17761         -1,
  17762         -1,
  17763     },
  17764 #endif /* chips */
  17765 
  17766 #if defined(BCM_56640_A0)
  17767     { /* SOC_REG_INT_UCQ_UCQE2_MEMDEBUGr */
  17768         soc_block_list[4],
  17769         soc_genreg,
  17770         1,
  17771         0,
  17772         0x1a008400,
  17773         0,
  17774         0,
  17775         1,
  17776         soc_UCQ_FREE_MEMDEBUGr_fields,
  17777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17778         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17779         -1,
  17780         -1,
  17781     },
  17782 #endif /* chips */
  17783 
  17784 #if defined(BCM_56640_A0)
  17785     { /* SOC_REG_INT_UCQ_UCQE3_MEMDEBUGr */
  17786         soc_block_list[4],
  17787         soc_genreg,
  17788         1,
  17789         0,
  17790         0x1a008500,
  17791         0,
  17792         0,
  17793         1,
  17794         soc_UCQ_FREE_MEMDEBUGr_fields,
  17795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17796         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17797         -1,
  17798         -1,
  17799     },
  17800 #endif /* chips */
  17801 
  17802 #if defined(BCM_56640_A0)
  17803     { /* SOC_REG_INT_UCQ_UCQE_MEMECC_ERRPTRr */
  17804         soc_block_list[4],
  17805         soc_genreg,
  17806         1,
  17807         0,
  17808         0x1a008800,
  17809         SOC_REG_FLAG_RO,
  17810         0,
  17811         1,
  17812         soc_UCQ_UCQE_MEMECC_ERRPTRr_fields,
  17813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17814         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  17815         -1,
  17816         -1,
  17817     },
  17818 #endif /* chips */
  17819 
  17820 #if defined(BCM_88650_A0)
  17821     { /* SOC_REG_INT_UC_0_CONFIGr */
  17822         soc_block_list[1],
  17823         soc_mcsreg,
  17824         1,
  17825         0,
  17826         0x7006004,
  17827         0,
  17828         0,
  17829         20,
  17830         soc_UC_0_CONFIGr_fields,
  17831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17832         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17833         -1,
  17834         -1,
  17835     },
  17836 #endif /* chips */
  17837 
  17838 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  17839     { /* SOC_REG_INT_UC_0_CONFIG_BCM56440_A0r */
  17840         soc_block_list[1],
  17841         soc_mcsreg,
  17842         1,
  17843         0,
  17844         0x7006004,
  17845         0,
  17846         0,
  17847         20,
  17848         soc_UC_0_CONFIG_BCM56440_A0r_fields,
  17849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17850         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17851         -1,
  17852         -1,
  17853     },
  17854 #endif /* chips */
  17855 
  17856 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  17857     defined(BCM_56860_A0)
  17858     { /* SOC_REG_INT_UC_0_CONFIG_BCM56640_A0r */
  17859         soc_block_list[1],
  17860         soc_mcsreg,
  17861         1,
  17862         0,
  17863         0x7006004,
  17864         0,
  17865         0,
  17866         20,
  17867         soc_UC_0_CONFIG_BCM56640_A0r_fields,
  17868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17869         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17870         -1,
  17871         -1,
  17872     },
  17873 #endif /* chips */
  17874 
  17875 #if defined(BCM_88202_A0)
  17876     { /* SOC_REG_INT_UC_0_CONFIG_BCM88202_A0r */
  17877         soc_block_list[1],
  17878         soc_mcsreg,
  17879         1,
  17880         0,
  17881         0x7006004,
  17882         0,
  17883         0,
  17884         20,
  17885         soc_UC_0_CONFIG_BCM88202_A0r_fields,
  17886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17887         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17888         -1,
  17889         -1,
  17890     },
  17891 #endif /* chips */
  17892 
  17893 #if defined(BCM_88650_B0)
  17894     { /* SOC_REG_INT_UC_0_CONFIG_BCM88650_B0r */
  17895         soc_block_list[1],
  17896         soc_mcsreg,
  17897         1,
  17898         0,
  17899         0x7006004,
  17900         0,
  17901         0,
  17902         20,
  17903         soc_UC_0_CONFIG_BCM88650_B0r_fields,
  17904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17905         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17906         -1,
  17907         -1,
  17908     },
  17909 #endif /* chips */
  17910 
  17911 #if defined(BCM_88660_A0)
  17912     { /* SOC_REG_INT_UC_0_CONFIG_BCM88660_A0r */
  17913         soc_block_list[1],
  17914         soc_mcsreg,
  17915         1,
  17916         0,
  17917         0x7006004,
  17918         0,
  17919         0,
  17920         20,
  17921         soc_UC_0_CONFIG_BCM88660_A0r_fields,
  17922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17923         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17924         -1,
  17925         -1,
  17926     },
  17927 #endif /* chips */
  17928 
  17929 #if defined(BCM_88650_A0)
  17930     { /* SOC_REG_INT_UC_0_DEBUG_CONFIGr */
  17931         soc_block_list[1],
  17932         soc_mcsreg,
  17933         1,
  17934         0,
  17935         0x7006014,
  17936         0,
  17937         0,
  17938         7,
  17939         soc_UC_0_DEBUG_CONFIGr_fields,
  17940         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  17941         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17942         -1,
  17943         -1,
  17944     },
  17945 #endif /* chips */
  17946 
  17947 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  17948     { /* SOC_REG_INT_UC_0_DEBUG_CONFIG_BCM56440_A0r */
  17949         soc_block_list[1],
  17950         soc_mcsreg,
  17951         1,
  17952         0,
  17953         0x7006014,
  17954         0,
  17955         0,
  17956         7,
  17957         soc_UC_0_DEBUG_CONFIG_BCM56440_A0r_fields,
  17958         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  17959         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17960         -1,
  17961         -1,
  17962     },
  17963 #endif /* chips */
  17964 
  17965 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  17966     defined(BCM_56860_A0)
  17967     { /* SOC_REG_INT_UC_0_DEBUG_CONFIG_BCM56640_A0r */
  17968         soc_block_list[1],
  17969         soc_mcsreg,
  17970         1,
  17971         0,
  17972         0x7006014,
  17973         0,
  17974         0,
  17975         7,
  17976         soc_UC_0_DEBUG_CONFIG_BCM56640_A0r_fields,
  17977         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  17978         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17979         -1,
  17980         -1,
  17981     },
  17982 #endif /* chips */
  17983 
  17984 #if defined(BCM_88202_A0)
  17985     { /* SOC_REG_INT_UC_0_DEBUG_CONFIG_BCM88202_A0r */
  17986         soc_block_list[1],
  17987         soc_mcsreg,
  17988         1,
  17989         0,
  17990         0x7006014,
  17991         0,
  17992         0,
  17993         7,
  17994         soc_UC_0_DEBUG_CONFIG_BCM88202_A0r_fields,
  17995         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  17996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17997         -1,
  17998         -1,
  17999     },
  18000 #endif /* chips */
  18001 
  18002 #if defined(BCM_88650_B0)
  18003     { /* SOC_REG_INT_UC_0_DEBUG_CONFIG_BCM88650_B0r */
  18004         soc_block_list[1],
  18005         soc_mcsreg,
  18006         1,
  18007         0,
  18008         0x7006014,
  18009         0,
  18010         0,
  18011         7,
  18012         soc_UC_0_DEBUG_CONFIG_BCM88650_B0r_fields,
  18013         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  18014         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18015         -1,
  18016         -1,
  18017     },
  18018 #endif /* chips */
  18019 
  18020 #if defined(BCM_88660_A0)
  18021     { /* SOC_REG_INT_UC_0_DEBUG_CONFIG_BCM88660_A0r */
  18022         soc_block_list[1],
  18023         soc_mcsreg,
  18024         1,
  18025         0,
  18026         0x7006014,
  18027         0,
  18028         0,
  18029         7,
  18030         soc_UC_0_DEBUG_CONFIG_BCM88660_A0r_fields,
  18031         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  18032         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18033         -1,
  18034         -1,
  18035     },
  18036 #endif /* chips */
  18037 
  18038 #if defined(BCM_88650_A0)
  18039     { /* SOC_REG_INT_UC_0_DEBUG_STATUSr */
  18040         soc_block_list[1],
  18041         soc_mcsreg,
  18042         1,
  18043         0,
  18044         0x7006018,
  18045         SOC_REG_FLAG_RO,
  18046         0,
  18047         8,
  18048         soc_UC_0_DEBUG_STATUSr_fields,
  18049         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18050         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18051         -1,
  18052         -1,
  18053     },
  18054 #endif /* chips */
  18055 
  18056 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  18057     { /* SOC_REG_INT_UC_0_DEBUG_STATUS_BCM56440_A0r */
  18058         soc_block_list[1],
  18059         soc_mcsreg,
  18060         1,
  18061         0,
  18062         0x7006018,
  18063         SOC_REG_FLAG_RO,
  18064         0,
  18065         8,
  18066         soc_UC_0_DEBUG_STATUS_BCM56440_A0r_fields,
  18067         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18068         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18069         -1,
  18070         -1,
  18071     },
  18072 #endif /* chips */
  18073 
  18074 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  18075     defined(BCM_56860_A0)
  18076     { /* SOC_REG_INT_UC_0_DEBUG_STATUS_BCM56640_A0r */
  18077         soc_block_list[1],
  18078         soc_mcsreg,
  18079         1,
  18080         0,
  18081         0x7006018,
  18082         SOC_REG_FLAG_RO,
  18083         0,
  18084         8,
  18085         soc_UC_0_DEBUG_STATUS_BCM56640_A0r_fields,
  18086         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18087         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18088         -1,
  18089         -1,
  18090     },
  18091 #endif /* chips */
  18092 
  18093 #if defined(BCM_88202_A0)
  18094     { /* SOC_REG_INT_UC_0_DEBUG_STATUS_BCM88202_A0r */
  18095         soc_block_list[1],
  18096         soc_mcsreg,
  18097         1,
  18098         0,
  18099         0x7006018,
  18100         SOC_REG_FLAG_RO,
  18101         0,
  18102         8,
  18103         soc_UC_0_DEBUG_STATUS_BCM88202_A0r_fields,
  18104         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18105         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18106         -1,
  18107         -1,
  18108     },
  18109 #endif /* chips */
  18110 
  18111 #if defined(BCM_88650_B0)
  18112     { /* SOC_REG_INT_UC_0_DEBUG_STATUS_BCM88650_B0r */
  18113         soc_block_list[1],
  18114         soc_mcsreg,
  18115         1,
  18116         0,
  18117         0x7006018,
  18118         SOC_REG_FLAG_RO,
  18119         0,
  18120         8,
  18121         soc_UC_0_DEBUG_STATUS_BCM88650_B0r_fields,
  18122         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18123         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18124         -1,
  18125         -1,
  18126     },
  18127 #endif /* chips */
  18128 
  18129 #if defined(BCM_88660_A0)
  18130     { /* SOC_REG_INT_UC_0_DEBUG_STATUS_BCM88660_A0r */
  18131         soc_block_list[1],
  18132         soc_mcsreg,
  18133         1,
  18134         0,
  18135         0x7006018,
  18136         SOC_REG_FLAG_RO,
  18137         0,
  18138         8,
  18139         soc_UC_0_DEBUG_STATUS_BCM88660_A0r_fields,
  18140         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18141         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18142         -1,
  18143         -1,
  18144     },
  18145 #endif /* chips */
  18146 
  18147 #if defined(BCM_88650_A0)
  18148     { /* SOC_REG_INT_UC_0_RST_CONTROLr */
  18149         soc_block_list[1],
  18150         soc_mcsreg,
  18151         1,
  18152         0,
  18153         0x7006000,
  18154         0,
  18155         0,
  18156         6,
  18157         soc_UC_0_RST_CONTROLr_fields,
  18158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18159         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18160         -1,
  18161         -1,
  18162     },
  18163 #endif /* chips */
  18164 
  18165 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  18166     { /* SOC_REG_INT_UC_0_RST_CONTROL_BCM56440_A0r */
  18167         soc_block_list[1],
  18168         soc_mcsreg,
  18169         1,
  18170         0,
  18171         0x7006000,
  18172         0,
  18173         0,
  18174         6,
  18175         soc_UC_0_RST_CONTROL_BCM56440_A0r_fields,
  18176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18177         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18178         -1,
  18179         -1,
  18180     },
  18181 #endif /* chips */
  18182 
  18183 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  18184     defined(BCM_56860_A0)
  18185     { /* SOC_REG_INT_UC_0_RST_CONTROL_BCM56640_A0r */
  18186         soc_block_list[1],
  18187         soc_mcsreg,
  18188         1,
  18189         0,
  18190         0x7006000,
  18191         0,
  18192         0,
  18193         6,
  18194         soc_UC_0_RST_CONTROL_BCM56640_A0r_fields,
  18195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18196         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18197         -1,
  18198         -1,
  18199     },
  18200 #endif /* chips */
  18201 
  18202 #if defined(BCM_88202_A0)
  18203     { /* SOC_REG_INT_UC_0_RST_CONTROL_BCM88202_A0r */
  18204         soc_block_list[1],
  18205         soc_mcsreg,
  18206         1,
  18207         0,
  18208         0x7006000,
  18209         0,
  18210         0,
  18211         6,
  18212         soc_UC_0_RST_CONTROL_BCM88202_A0r_fields,
  18213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18214         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18215         -1,
  18216         -1,
  18217     },
  18218 #endif /* chips */
  18219 
  18220 #if defined(BCM_88650_B0)
  18221     { /* SOC_REG_INT_UC_0_RST_CONTROL_BCM88650_B0r */
  18222         soc_block_list[1],
  18223         soc_mcsreg,
  18224         1,
  18225         0,
  18226         0x7006000,
  18227         0,
  18228         0,
  18229         6,
  18230         soc_UC_0_RST_CONTROL_BCM88650_B0r_fields,
  18231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18232         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18233         -1,
  18234         -1,
  18235     },
  18236 #endif /* chips */
  18237 
  18238 #if defined(BCM_88660_A0)
  18239     { /* SOC_REG_INT_UC_0_RST_CONTROL_BCM88660_A0r */
  18240         soc_block_list[1],
  18241         soc_mcsreg,
  18242         1,
  18243         0,
  18244         0x7006000,
  18245         0,
  18246         0,
  18247         6,
  18248         soc_UC_0_RST_CONTROL_BCM88660_A0r_fields,
  18249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18250         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18251         -1,
  18252         -1,
  18253     },
  18254 #endif /* chips */
  18255 
  18256 #if defined(BCM_88650_A0)
  18257     { /* SOC_REG_INT_UC_0_STATUSr */
  18258         soc_block_list[1],
  18259         soc_mcsreg,
  18260         1,
  18261         0,
  18262         0x70060a0,
  18263         SOC_REG_FLAG_RO,
  18264         0,
  18265         19,
  18266         soc_UC_0_STATUSr_fields,
  18267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18268         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18269         -1,
  18270         -1,
  18271     },
  18272 #endif /* chips */
  18273 
  18274 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  18275     { /* SOC_REG_INT_UC_0_STATUS_BCM56440_A0r */
  18276         soc_block_list[1],
  18277         soc_mcsreg,
  18278         1,
  18279         0,
  18280         0x70060a0,
  18281         SOC_REG_FLAG_RO,
  18282         0,
  18283         19,
  18284         soc_UC_0_STATUS_BCM56440_A0r_fields,
  18285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18286         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18287         -1,
  18288         -1,
  18289     },
  18290 #endif /* chips */
  18291 
  18292 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  18293     defined(BCM_56860_A0)
  18294     { /* SOC_REG_INT_UC_0_STATUS_BCM56640_A0r */
  18295         soc_block_list[1],
  18296         soc_mcsreg,
  18297         1,
  18298         0,
  18299         0x70060a0,
  18300         SOC_REG_FLAG_RO,
  18301         0,
  18302         19,
  18303         soc_UC_0_STATUS_BCM56640_A0r_fields,
  18304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18305         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18306         -1,
  18307         -1,
  18308     },
  18309 #endif /* chips */
  18310 
  18311 #if defined(BCM_88202_A0)
  18312     { /* SOC_REG_INT_UC_0_STATUS_BCM88202_A0r */
  18313         soc_block_list[1],
  18314         soc_mcsreg,
  18315         1,
  18316         0,
  18317         0x70060a0,
  18318         SOC_REG_FLAG_RO,
  18319         0,
  18320         19,
  18321         soc_UC_0_STATUS_BCM88202_A0r_fields,
  18322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18323         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18324         -1,
  18325         -1,
  18326     },
  18327 #endif /* chips */
  18328 
  18329 #if defined(BCM_88650_B0)
  18330     { /* SOC_REG_INT_UC_0_STATUS_BCM88650_B0r */
  18331         soc_block_list[1],
  18332         soc_mcsreg,
  18333         1,
  18334         0,
  18335         0x70060a0,
  18336         SOC_REG_FLAG_RO,
  18337         0,
  18338         19,
  18339         soc_UC_0_STATUS_BCM88650_B0r_fields,
  18340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18341         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18342         -1,
  18343         -1,
  18344     },
  18345 #endif /* chips */
  18346 
  18347 #if defined(BCM_88660_A0)
  18348     { /* SOC_REG_INT_UC_0_STATUS_BCM88660_A0r */
  18349         soc_block_list[1],
  18350         soc_mcsreg,
  18351         1,
  18352         0,
  18353         0x70060a0,
  18354         SOC_REG_FLAG_RO,
  18355         0,
  18356         19,
  18357         soc_UC_0_STATUS_BCM88660_A0r_fields,
  18358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18359         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18360         -1,
  18361         -1,
  18362     },
  18363 #endif /* chips */
  18364 
  18365 #if defined(BCM_88650_A0)
  18366     { /* SOC_REG_INT_UC_0_TIMER_INTR_MASKr */
  18367         soc_block_list[1],
  18368         soc_mcsreg,
  18369         1,
  18370         0,
  18371         0x70060b0,
  18372         0,
  18373         0,
  18374         21,
  18375         soc_UC_0_TIMER_INTR_MASKr_fields,
  18376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18377         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18378         -1,
  18379         -1,
  18380     },
  18381 #endif /* chips */
  18382 
  18383 #if defined(BCM_56440_A0)
  18384     { /* SOC_REG_INT_UC_0_TIMER_INTR_MASK_BCM56440_A0r */
  18385         soc_block_list[1],
  18386         soc_mcsreg,
  18387         1,
  18388         0,
  18389         0x70060b0,
  18390         0,
  18391         0,
  18392         5,
  18393         soc_UC_0_TIMER_INTR_MASK_BCM56440_A0r_fields,
  18394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18395         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18396         -1,
  18397         -1,
  18398     },
  18399 #endif /* chips */
  18400 
  18401 #if defined(BCM_56440_B0)
  18402     { /* SOC_REG_INT_UC_0_TIMER_INTR_MASK_BCM56440_B0r */
  18403         soc_block_list[1],
  18404         soc_mcsreg,
  18405         1,
  18406         0,
  18407         0x70060b0,
  18408         0,
  18409         0,
  18410         21,
  18411         soc_UC_0_TIMER_INTR_MASK_BCM56440_B0r_fields,
  18412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18413         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18414         -1,
  18415         -1,
  18416     },
  18417 #endif /* chips */
  18418 
  18419 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  18420     defined(BCM_56860_A0)
  18421     { /* SOC_REG_INT_UC_0_TIMER_INTR_MASK_BCM56640_A0r */
  18422         soc_block_list[1],
  18423         soc_mcsreg,
  18424         1,
  18425         0,
  18426         0x70060b0,
  18427         0,
  18428         0,
  18429         21,
  18430         soc_UC_0_TIMER_INTR_MASK_BCM56640_A0r_fields,
  18431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18433         -1,
  18434         -1,
  18435     },
  18436 #endif /* chips */
  18437 
  18438 #if defined(BCM_88202_A0)
  18439     { /* SOC_REG_INT_UC_0_TIMER_INTR_MASK_BCM88202_A0r */
  18440         soc_block_list[1],
  18441         soc_mcsreg,
  18442         1,
  18443         0,
  18444         0x70060b0,
  18445         0,
  18446         0,
  18447         21,
  18448         soc_UC_0_TIMER_INTR_MASK_BCM88202_A0r_fields,
  18449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18451         -1,
  18452         -1,
  18453     },
  18454 #endif /* chips */
  18455 
  18456 #if defined(BCM_88650_B0)
  18457     { /* SOC_REG_INT_UC_0_TIMER_INTR_MASK_BCM88650_B0r */
  18458         soc_block_list[1],
  18459         soc_mcsreg,
  18460         1,
  18461         0,
  18462         0x70060b0,
  18463         0,
  18464         0,
  18465         21,
  18466         soc_UC_0_TIMER_INTR_MASK_BCM88650_B0r_fields,
  18467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18469         -1,
  18470         -1,
  18471     },
  18472 #endif /* chips */
  18473 
  18474 #if defined(BCM_88660_A0)
  18475     { /* SOC_REG_INT_UC_0_TIMER_INTR_MASK_BCM88660_A0r */
  18476         soc_block_list[1],
  18477         soc_mcsreg,
  18478         1,
  18479         0,
  18480         0x70060b0,
  18481         0,
  18482         0,
  18483         21,
  18484         soc_UC_0_TIMER_INTR_MASK_BCM88660_A0r_fields,
  18485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18486         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18487         -1,
  18488         -1,
  18489     },
  18490 #endif /* chips */
  18491 
  18492 #if defined(BCM_88650_A0)
  18493     { /* SOC_REG_INT_UC_1_CONFIGr */
  18494         soc_block_list[1],
  18495         soc_mcsreg,
  18496         1,
  18497         0,
  18498         0x700600c,
  18499         0,
  18500         0,
  18501         19,
  18502         soc_UC_1_CONFIGr_fields,
  18503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18504         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18505         -1,
  18506         -1,
  18507     },
  18508 #endif /* chips */
  18509 
  18510 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  18511     { /* SOC_REG_INT_UC_1_CONFIG_BCM56440_A0r */
  18512         soc_block_list[1],
  18513         soc_mcsreg,
  18514         1,
  18515         0,
  18516         0x700600c,
  18517         0,
  18518         0,
  18519         19,
  18520         soc_UC_1_CONFIG_BCM56440_A0r_fields,
  18521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18522         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18523         -1,
  18524         -1,
  18525     },
  18526 #endif /* chips */
  18527 
  18528 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  18529     defined(BCM_56860_A0)
  18530     { /* SOC_REG_INT_UC_1_CONFIG_BCM56640_A0r */
  18531         soc_block_list[1],
  18532         soc_mcsreg,
  18533         1,
  18534         0,
  18535         0x700600c,
  18536         0,
  18537         0,
  18538         19,
  18539         soc_UC_1_CONFIG_BCM56640_A0r_fields,
  18540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18542         -1,
  18543         -1,
  18544     },
  18545 #endif /* chips */
  18546 
  18547 #if defined(BCM_88202_A0)
  18548     { /* SOC_REG_INT_UC_1_CONFIG_BCM88202_A0r */
  18549         soc_block_list[1],
  18550         soc_mcsreg,
  18551         1,
  18552         0,
  18553         0x700600c,
  18554         0,
  18555         0,
  18556         19,
  18557         soc_UC_1_CONFIG_BCM88202_A0r_fields,
  18558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18559         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18560         -1,
  18561         -1,
  18562     },
  18563 #endif /* chips */
  18564 
  18565 #if defined(BCM_88650_B0)
  18566     { /* SOC_REG_INT_UC_1_CONFIG_BCM88650_B0r */
  18567         soc_block_list[1],
  18568         soc_mcsreg,
  18569         1,
  18570         0,
  18571         0x700600c,
  18572         0,
  18573         0,
  18574         19,
  18575         soc_UC_1_CONFIG_BCM88650_B0r_fields,
  18576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18577         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18578         -1,
  18579         -1,
  18580     },
  18581 #endif /* chips */
  18582 
  18583 #if defined(BCM_88660_A0)
  18584     { /* SOC_REG_INT_UC_1_CONFIG_BCM88660_A0r */
  18585         soc_block_list[1],
  18586         soc_mcsreg,
  18587         1,
  18588         0,
  18589         0x700600c,
  18590         0,
  18591         0,
  18592         19,
  18593         soc_UC_1_CONFIG_BCM88660_A0r_fields,
  18594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18596         -1,
  18597         -1,
  18598     },
  18599 #endif /* chips */
  18600 
  18601 #if defined(BCM_88650_A0)
  18602     { /* SOC_REG_INT_UC_1_DEBUG_CONFIGr */
  18603         soc_block_list[1],
  18604         soc_mcsreg,
  18605         1,
  18606         0,
  18607         0x700601c,
  18608         0,
  18609         0,
  18610         7,
  18611         soc_UC_1_DEBUG_CONFIGr_fields,
  18612         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  18613         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18614         -1,
  18615         -1,
  18616     },
  18617 #endif /* chips */
  18618 
  18619 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  18620     { /* SOC_REG_INT_UC_1_DEBUG_CONFIG_BCM56440_A0r */
  18621         soc_block_list[1],
  18622         soc_mcsreg,
  18623         1,
  18624         0,
  18625         0x700601c,
  18626         0,
  18627         0,
  18628         7,
  18629         soc_UC_0_DEBUG_CONFIG_BCM56440_A0r_fields,
  18630         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  18631         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18632         -1,
  18633         -1,
  18634     },
  18635 #endif /* chips */
  18636 
  18637 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  18638     defined(BCM_56860_A0)
  18639     { /* SOC_REG_INT_UC_1_DEBUG_CONFIG_BCM56640_A0r */
  18640         soc_block_list[1],
  18641         soc_mcsreg,
  18642         1,
  18643         0,
  18644         0x700601c,
  18645         0,
  18646         0,
  18647         7,
  18648         soc_UC_0_DEBUG_CONFIG_BCM56640_A0r_fields,
  18649         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  18650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18651         -1,
  18652         -1,
  18653     },
  18654 #endif /* chips */
  18655 
  18656 #if defined(BCM_88202_A0)
  18657     { /* SOC_REG_INT_UC_1_DEBUG_CONFIG_BCM88202_A0r */
  18658         soc_block_list[1],
  18659         soc_mcsreg,
  18660         1,
  18661         0,
  18662         0x700601c,
  18663         0,
  18664         0,
  18665         7,
  18666         soc_UC_1_DEBUG_CONFIG_BCM88202_A0r_fields,
  18667         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  18668         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18669         -1,
  18670         -1,
  18671     },
  18672 #endif /* chips */
  18673 
  18674 #if defined(BCM_88650_B0)
  18675     { /* SOC_REG_INT_UC_1_DEBUG_CONFIG_BCM88650_B0r */
  18676         soc_block_list[1],
  18677         soc_mcsreg,
  18678         1,
  18679         0,
  18680         0x700601c,
  18681         0,
  18682         0,
  18683         7,
  18684         soc_UC_1_DEBUG_CONFIG_BCM88650_B0r_fields,
  18685         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  18686         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18687         -1,
  18688         -1,
  18689     },
  18690 #endif /* chips */
  18691 
  18692 #if defined(BCM_88660_A0)
  18693     { /* SOC_REG_INT_UC_1_DEBUG_CONFIG_BCM88660_A0r */
  18694         soc_block_list[1],
  18695         soc_mcsreg,
  18696         1,
  18697         0,
  18698         0x700601c,
  18699         0,
  18700         0,
  18701         7,
  18702         soc_UC_1_DEBUG_CONFIG_BCM88660_A0r_fields,
  18703         SOC_RESET_VAL_DEC(0x00000021, 0x00000000)
  18704         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18705         -1,
  18706         -1,
  18707     },
  18708 #endif /* chips */
  18709 
  18710 #if defined(BCM_88650_A0)
  18711     { /* SOC_REG_INT_UC_1_DEBUG_STATUSr */
  18712         soc_block_list[1],
  18713         soc_mcsreg,
  18714         1,
  18715         0,
  18716         0x7006020,
  18717         SOC_REG_FLAG_RO,
  18718         0,
  18719         8,
  18720         soc_UC_1_DEBUG_STATUSr_fields,
  18721         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18722         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18723         -1,
  18724         -1,
  18725     },
  18726 #endif /* chips */
  18727 
  18728 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  18729     { /* SOC_REG_INT_UC_1_DEBUG_STATUS_BCM56440_A0r */
  18730         soc_block_list[1],
  18731         soc_mcsreg,
  18732         1,
  18733         0,
  18734         0x7006020,
  18735         SOC_REG_FLAG_RO,
  18736         0,
  18737         8,
  18738         soc_UC_0_DEBUG_STATUS_BCM56440_A0r_fields,
  18739         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18740         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18741         -1,
  18742         -1,
  18743     },
  18744 #endif /* chips */
  18745 
  18746 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  18747     defined(BCM_56860_A0)
  18748     { /* SOC_REG_INT_UC_1_DEBUG_STATUS_BCM56640_A0r */
  18749         soc_block_list[1],
  18750         soc_mcsreg,
  18751         1,
  18752         0,
  18753         0x7006020,
  18754         SOC_REG_FLAG_RO,
  18755         0,
  18756         8,
  18757         soc_UC_0_DEBUG_STATUS_BCM56640_A0r_fields,
  18758         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18760         -1,
  18761         -1,
  18762     },
  18763 #endif /* chips */
  18764 
  18765 #if defined(BCM_88202_A0)
  18766     { /* SOC_REG_INT_UC_1_DEBUG_STATUS_BCM88202_A0r */
  18767         soc_block_list[1],
  18768         soc_mcsreg,
  18769         1,
  18770         0,
  18771         0x7006020,
  18772         SOC_REG_FLAG_RO,
  18773         0,
  18774         8,
  18775         soc_UC_1_DEBUG_STATUS_BCM88202_A0r_fields,
  18776         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18778         -1,
  18779         -1,
  18780     },
  18781 #endif /* chips */
  18782 
  18783 #if defined(BCM_88650_B0)
  18784     { /* SOC_REG_INT_UC_1_DEBUG_STATUS_BCM88650_B0r */
  18785         soc_block_list[1],
  18786         soc_mcsreg,
  18787         1,
  18788         0,
  18789         0x7006020,
  18790         SOC_REG_FLAG_RO,
  18791         0,
  18792         8,
  18793         soc_UC_1_DEBUG_STATUS_BCM88650_B0r_fields,
  18794         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18796         -1,
  18797         -1,
  18798     },
  18799 #endif /* chips */
  18800 
  18801 #if defined(BCM_88660_A0)
  18802     { /* SOC_REG_INT_UC_1_DEBUG_STATUS_BCM88660_A0r */
  18803         soc_block_list[1],
  18804         soc_mcsreg,
  18805         1,
  18806         0,
  18807         0x7006020,
  18808         SOC_REG_FLAG_RO,
  18809         0,
  18810         8,
  18811         soc_UC_1_DEBUG_STATUS_BCM88660_A0r_fields,
  18812         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  18813         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18814         -1,
  18815         -1,
  18816     },
  18817 #endif /* chips */
  18818 
  18819 #if defined(BCM_88650_A0)
  18820     { /* SOC_REG_INT_UC_1_RST_CONTROLr */
  18821         soc_block_list[1],
  18822         soc_mcsreg,
  18823         1,
  18824         0,
  18825         0x7006008,
  18826         0,
  18827         0,
  18828         5,
  18829         soc_UC_1_RST_CONTROLr_fields,
  18830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18831         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18832         -1,
  18833         -1,
  18834     },
  18835 #endif /* chips */
  18836 
  18837 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  18838     { /* SOC_REG_INT_UC_1_RST_CONTROL_BCM56440_A0r */
  18839         soc_block_list[1],
  18840         soc_mcsreg,
  18841         1,
  18842         0,
  18843         0x7006008,
  18844         0,
  18845         0,
  18846         5,
  18847         soc_UC_1_RST_CONTROL_BCM56440_A0r_fields,
  18848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18849         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18850         -1,
  18851         -1,
  18852     },
  18853 #endif /* chips */
  18854 
  18855 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  18856     defined(BCM_56860_A0)
  18857     { /* SOC_REG_INT_UC_1_RST_CONTROL_BCM56640_A0r */
  18858         soc_block_list[1],
  18859         soc_mcsreg,
  18860         1,
  18861         0,
  18862         0x7006008,
  18863         0,
  18864         0,
  18865         5,
  18866         soc_UC_1_RST_CONTROL_BCM56640_A0r_fields,
  18867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18868         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18869         -1,
  18870         -1,
  18871     },
  18872 #endif /* chips */
  18873 
  18874 #if defined(BCM_88202_A0)
  18875     { /* SOC_REG_INT_UC_1_RST_CONTROL_BCM88202_A0r */
  18876         soc_block_list[1],
  18877         soc_mcsreg,
  18878         1,
  18879         0,
  18880         0x7006008,
  18881         0,
  18882         0,
  18883         5,
  18884         soc_UC_1_RST_CONTROL_BCM88202_A0r_fields,
  18885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18886         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18887         -1,
  18888         -1,
  18889     },
  18890 #endif /* chips */
  18891 
  18892 #if defined(BCM_88650_B0)
  18893     { /* SOC_REG_INT_UC_1_RST_CONTROL_BCM88650_B0r */
  18894         soc_block_list[1],
  18895         soc_mcsreg,
  18896         1,
  18897         0,
  18898         0x7006008,
  18899         0,
  18900         0,
  18901         5,
  18902         soc_UC_1_RST_CONTROL_BCM88650_B0r_fields,
  18903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18904         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18905         -1,
  18906         -1,
  18907     },
  18908 #endif /* chips */
  18909 
  18910 #if defined(BCM_88660_A0)
  18911     { /* SOC_REG_INT_UC_1_RST_CONTROL_BCM88660_A0r */
  18912         soc_block_list[1],
  18913         soc_mcsreg,
  18914         1,
  18915         0,
  18916         0x7006008,
  18917         0,
  18918         0,
  18919         5,
  18920         soc_UC_1_RST_CONTROL_BCM88660_A0r_fields,
  18921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18922         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18923         -1,
  18924         -1,
  18925     },
  18926 #endif /* chips */
  18927 
  18928 #if defined(BCM_88650_A0)
  18929     { /* SOC_REG_INT_UC_1_STATUSr */
  18930         soc_block_list[1],
  18931         soc_mcsreg,
  18932         1,
  18933         0,
  18934         0x70060a4,
  18935         SOC_REG_FLAG_RO,
  18936         0,
  18937         18,
  18938         soc_UC_1_STATUSr_fields,
  18939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18940         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18941         -1,
  18942         -1,
  18943     },
  18944 #endif /* chips */
  18945 
  18946 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  18947     { /* SOC_REG_INT_UC_1_STATUS_BCM56440_A0r */
  18948         soc_block_list[1],
  18949         soc_mcsreg,
  18950         1,
  18951         0,
  18952         0x70060a4,
  18953         SOC_REG_FLAG_RO,
  18954         0,
  18955         18,
  18956         soc_UC_1_STATUS_BCM56440_A0r_fields,
  18957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18958         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18959         -1,
  18960         -1,
  18961     },
  18962 #endif /* chips */
  18963 
  18964 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  18965     defined(BCM_56860_A0)
  18966     { /* SOC_REG_INT_UC_1_STATUS_BCM56640_A0r */
  18967         soc_block_list[1],
  18968         soc_mcsreg,
  18969         1,
  18970         0,
  18971         0x70060a4,
  18972         SOC_REG_FLAG_RO,
  18973         0,
  18974         18,
  18975         soc_UC_1_STATUS_BCM56640_A0r_fields,
  18976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18977         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18978         -1,
  18979         -1,
  18980     },
  18981 #endif /* chips */
  18982 
  18983 #if defined(BCM_88202_A0)
  18984     { /* SOC_REG_INT_UC_1_STATUS_BCM88202_A0r */
  18985         soc_block_list[1],
  18986         soc_mcsreg,
  18987         1,
  18988         0,
  18989         0x70060a4,
  18990         SOC_REG_FLAG_RO,
  18991         0,
  18992         18,
  18993         soc_UC_1_STATUS_BCM88202_A0r_fields,
  18994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18995         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18996         -1,
  18997         -1,
  18998     },
  18999 #endif /* chips */
  19000 
  19001 #if defined(BCM_88650_B0)
  19002     { /* SOC_REG_INT_UC_1_STATUS_BCM88650_B0r */
  19003         soc_block_list[1],
  19004         soc_mcsreg,
  19005         1,
  19006         0,
  19007         0x70060a4,
  19008         SOC_REG_FLAG_RO,
  19009         0,
  19010         18,
  19011         soc_UC_1_STATUS_BCM88650_B0r_fields,
  19012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19013         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19014         -1,
  19015         -1,
  19016     },
  19017 #endif /* chips */
  19018 
  19019 #if defined(BCM_88660_A0)
  19020     { /* SOC_REG_INT_UC_1_STATUS_BCM88660_A0r */
  19021         soc_block_list[1],
  19022         soc_mcsreg,
  19023         1,
  19024         0,
  19025         0x70060a4,
  19026         SOC_REG_FLAG_RO,
  19027         0,
  19028         18,
  19029         soc_UC_1_STATUS_BCM88660_A0r_fields,
  19030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19031         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19032         -1,
  19033         -1,
  19034     },
  19035 #endif /* chips */
  19036 
  19037 #if defined(BCM_88650_A0)
  19038     { /* SOC_REG_INT_UC_1_TIMER_INTR_MASKr */
  19039         soc_block_list[1],
  19040         soc_mcsreg,
  19041         1,
  19042         0,
  19043         0x70060b4,
  19044         0,
  19045         0,
  19046         21,
  19047         soc_UC_1_TIMER_INTR_MASKr_fields,
  19048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19049         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19050         -1,
  19051         -1,
  19052     },
  19053 #endif /* chips */
  19054 
  19055 #if defined(BCM_56440_A0)
  19056     { /* SOC_REG_INT_UC_1_TIMER_INTR_MASK_BCM56440_A0r */
  19057         soc_block_list[1],
  19058         soc_mcsreg,
  19059         1,
  19060         0,
  19061         0x70060b4,
  19062         0,
  19063         0,
  19064         5,
  19065         soc_UC_1_TIMER_INTR_MASK_BCM56440_A0r_fields,
  19066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19067         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19068         -1,
  19069         -1,
  19070     },
  19071 #endif /* chips */
  19072 
  19073 #if defined(BCM_56440_B0)
  19074     { /* SOC_REG_INT_UC_1_TIMER_INTR_MASK_BCM56440_B0r */
  19075         soc_block_list[1],
  19076         soc_mcsreg,
  19077         1,
  19078         0,
  19079         0x70060b4,
  19080         0,
  19081         0,
  19082         21,
  19083         soc_UC_1_TIMER_INTR_MASK_BCM56440_B0r_fields,
  19084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19085         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19086         -1,
  19087         -1,
  19088     },
  19089 #endif /* chips */
  19090 
  19091 #if defined(BCM_56640_A0) || defined(BCM_56850_A0) || \
  19092     defined(BCM_56860_A0)
  19093     { /* SOC_REG_INT_UC_1_TIMER_INTR_MASK_BCM56640_A0r */
  19094         soc_block_list[1],
  19095         soc_mcsreg,
  19096         1,
  19097         0,
  19098         0x70060b4,
  19099         0,
  19100         0,
  19101         21,
  19102         soc_UC_1_TIMER_INTR_MASK_BCM56640_A0r_fields,
  19103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19104         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19105         -1,
  19106         -1,
  19107     },
  19108 #endif /* chips */
  19109 
  19110 #if defined(BCM_88202_A0)
  19111     { /* SOC_REG_INT_UC_1_TIMER_INTR_MASK_BCM88202_A0r */
  19112         soc_block_list[1],
  19113         soc_mcsreg,
  19114         1,
  19115         0,
  19116         0x70060b4,
  19117         0,
  19118         0,
  19119         21,
  19120         soc_UC_1_TIMER_INTR_MASK_BCM88202_A0r_fields,
  19121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19122         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19123         -1,
  19124         -1,
  19125     },
  19126 #endif /* chips */
  19127 
  19128 #if defined(BCM_88650_B0)
  19129     { /* SOC_REG_INT_UC_1_TIMER_INTR_MASK_BCM88650_B0r */
  19130         soc_block_list[1],
  19131         soc_mcsreg,
  19132         1,
  19133         0,
  19134         0x70060b4,
  19135         0,
  19136         0,
  19137         21,
  19138         soc_UC_1_TIMER_INTR_MASK_BCM88650_B0r_fields,
  19139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19140         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19141         -1,
  19142         -1,
  19143     },
  19144 #endif /* chips */
  19145 
  19146 #if defined(BCM_88660_A0)
  19147     { /* SOC_REG_INT_UC_1_TIMER_INTR_MASK_BCM88660_A0r */
  19148         soc_block_list[1],
  19149         soc_mcsreg,
  19150         1,
  19151         0,
  19152         0x70060b4,
  19153         0,
  19154         0,
  19155         21,
  19156         soc_UC_1_TIMER_INTR_MASK_BCM88660_A0r_fields,
  19157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19158         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19159         -1,
  19160         -1,
  19161     },
  19162 #endif /* chips */
  19163 
  19164 #if defined(BCM_56370_A0)
  19165     { /* SOC_REG_INT_UC_HG_QUEUE_MODEr */
  19166         soc_block_list[124],
  19167         soc_portreg,
  19168         1,
  19169         0,
  19170         0x2c811000,
  19171         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19172         0,
  19173         2,
  19174         soc_UC_HG_QUEUE_MODEr_fields,
  19175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19176         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19177         -1,
  19178         111,
  19179         3,
  19180     },
  19181 #endif /* chips */
  19182 
  19183 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  19184     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  19185     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  19186     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIGr */
  19187         soc_block_list[5],
  19188         soc_genreg,
  19189         1,
  19190         0,
  19191         0x2080116,
  19192         0,
  19193         0,
  19194         4,
  19195         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  19196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19197         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19198         -1,
  19199         -1,
  19200     },
  19201 #endif /* chips */
  19202 
  19203 #if defined(BCM_56970_A0)
  19204     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_64r */
  19205         soc_block_list[5],
  19206         soc_genreg,
  19207         1,
  19208         0,
  19209         0x53060000,
  19210         SOC_REG_FLAG_64_BITS |
  19211                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19212         0,
  19213         5,
  19214         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  19215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19216         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19217         -1,
  19218         -1,
  19219         0,
  19220     },
  19221 #endif /* chips */
  19222 
  19223 #if defined(BCM_56970_A0)
  19224     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_64_PIPE0r */
  19225         soc_block_list[5],
  19226         soc_genreg,
  19227         1,
  19228         0,
  19229         0x53060000,
  19230         SOC_REG_FLAG_64_BITS,
  19231         0,
  19232         5,
  19233         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  19234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19235         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19236         -1,
  19237         -1,
  19238         0,
  19239     },
  19240 #endif /* chips */
  19241 
  19242 #if defined(BCM_56970_A0)
  19243     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_64_PIPE1r */
  19244         soc_block_list[5],
  19245         soc_genreg,
  19246         1,
  19247         0,
  19248         0x53060000,
  19249         SOC_REG_FLAG_64_BITS |
  19250                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19251         0,
  19252         5,
  19253         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  19254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19255         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19256         -1,
  19257         -1,
  19258         0,
  19259     },
  19260 #endif /* chips */
  19261 
  19262 #if defined(BCM_56970_A0)
  19263     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_64_PIPE2r */
  19264         soc_block_list[5],
  19265         soc_genreg,
  19266         1,
  19267         0,
  19268         0x53060000,
  19269         SOC_REG_FLAG_64_BITS |
  19270                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19271         0,
  19272         5,
  19273         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  19274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19275         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19276         -1,
  19277         -1,
  19278         0,
  19279     },
  19280 #endif /* chips */
  19281 
  19282 #if defined(BCM_56970_A0)
  19283     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_64_PIPE3r */
  19284         soc_block_list[5],
  19285         soc_genreg,
  19286         1,
  19287         0,
  19288         0x53060000,
  19289         SOC_REG_FLAG_64_BITS |
  19290                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19291         0,
  19292         5,
  19293         soc_CPU_COS_CAM_BIST_CONFIG_64r_fields,
  19294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19295         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19296         -1,
  19297         -1,
  19298         0,
  19299     },
  19300 #endif /* chips */
  19301 
  19302 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  19303     defined(BCM_56270_A0)
  19304     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_BCM56260_A0r */
  19305         soc_block_list[5],
  19306         soc_genreg,
  19307         1,
  19308         0,
  19309         0xa010600,
  19310         0,
  19311         0,
  19312         4,
  19313         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  19314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19315         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19316         -1,
  19317         -1,
  19318     },
  19319 #endif /* chips */
  19320 
  19321 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  19322     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  19323     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_BCM56560_A0r */
  19324         soc_block_list[5],
  19325         soc_genreg,
  19326         1,
  19327         0,
  19328         0xb060000,
  19329         0,
  19330         0,
  19331         4,
  19332         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  19333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19334         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19335         -1,
  19336         -1,
  19337     },
  19338 #endif /* chips */
  19339 
  19340 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19341     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  19342     defined(BCM_56640_A0)
  19343     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_BCM56640_A0r */
  19344         soc_block_list[5],
  19345         soc_genreg,
  19346         1,
  19347         0,
  19348         0xa010600,
  19349         0,
  19350         0,
  19351         4,
  19352         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
  19353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19354         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19355         -1,
  19356         -1,
  19357     },
  19358 #endif /* chips */
  19359 
  19360 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  19361     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19362     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_BCM56840_A0r */
  19363         soc_block_list[5],
  19364         soc_genreg,
  19365         1,
  19366         0,
  19367         0x2080d06,
  19368         0,
  19369         0,
  19370         4,
  19371         soc_CPU_COS_CAM_BIST_CONFIGr_fields,
  19372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19373         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19374         -1,
  19375         -1,
  19376     },
  19377 #endif /* chips */
  19378 
  19379 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  19380     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_BCM56850_A0r */
  19381         soc_block_list[5],
  19382         soc_genreg,
  19383         1,
  19384         0,
  19385         0xb060000,
  19386         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19387         0,
  19388         4,
  19389         soc_CPU_COS_CAM_BIST_CONFIG_BCM56640_A0r_fields,
  19390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19391         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19392         -1,
  19393         -1,
  19394     },
  19395 #endif /* chips */
  19396 
  19397 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19398     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_BCM56960_A0r */
  19399         soc_block_list[5],
  19400         soc_genreg,
  19401         1,
  19402         0,
  19403         0x2f060000,
  19404         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19405         0,
  19406         4,
  19407         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  19408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19409         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19410         -1,
  19411         -1,
  19412         0,
  19413     },
  19414 #endif /* chips */
  19415 
  19416 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19417     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_PIPE0r */
  19418         soc_block_list[5],
  19419         soc_genreg,
  19420         1,
  19421         0,
  19422         0x2f060000,
  19423         0,
  19424         0,
  19425         4,
  19426         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  19427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19429         -1,
  19430         -1,
  19431         0,
  19432     },
  19433 #endif /* chips */
  19434 
  19435 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19436     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_PIPE1r */
  19437         soc_block_list[5],
  19438         soc_genreg,
  19439         1,
  19440         0,
  19441         0x2f060000,
  19442         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19443         0,
  19444         4,
  19445         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  19446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19447         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19448         -1,
  19449         -1,
  19450         0,
  19451     },
  19452 #endif /* chips */
  19453 
  19454 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19455     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_PIPE2r */
  19456         soc_block_list[5],
  19457         soc_genreg,
  19458         1,
  19459         0,
  19460         0x2f060000,
  19461         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19462         0,
  19463         4,
  19464         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  19465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19466         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19467         -1,
  19468         -1,
  19469         0,
  19470     },
  19471 #endif /* chips */
  19472 
  19473 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19474     { /* SOC_REG_INT_UDF_CAM_BIST_CONFIG_PIPE3r */
  19475         soc_block_list[5],
  19476         soc_genreg,
  19477         1,
  19478         0,
  19479         0x2f060000,
  19480         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19481         0,
  19482         4,
  19483         soc_CPU_COS_CAM_BIST_CONFIG_BCM53400_A0r_fields,
  19484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19485         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19486         -1,
  19487         -1,
  19488         0,
  19489     },
  19490 #endif /* chips */
  19491 
  19492 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  19493     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  19494     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  19495     { /* SOC_REG_INT_UDF_CAM_BIST_DBG_DATAr */
  19496         soc_block_list[5],
  19497         soc_genreg,
  19498         1,
  19499         0,
  19500         0x2080117,
  19501         SOC_REG_FLAG_WO,
  19502         0,
  19503         1,
  19504         soc_FP_CAM_DEBUG_DATA_0r_fields,
  19505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19506         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19507         -1,
  19508         -1,
  19509     },
  19510 #endif /* chips */
  19511 
  19512 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  19513     defined(BCM_56270_A0)
  19514     { /* SOC_REG_INT_UDF_CAM_BIST_DBG_DATA_BCM56260_A0r */
  19515         soc_block_list[5],
  19516         soc_genreg,
  19517         1,
  19518         0,
  19519         0xa010700,
  19520         SOC_REG_FLAG_WO,
  19521         0,
  19522         1,
  19523         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  19524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19525         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19526         -1,
  19527         -1,
  19528     },
  19529 #endif /* chips */
  19530 
  19531 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  19532     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  19533     { /* SOC_REG_INT_UDF_CAM_BIST_DBG_DATA_BCM56560_A0r */
  19534         soc_block_list[5],
  19535         soc_genreg,
  19536         1,
  19537         0,
  19538         0xb070000,
  19539         SOC_REG_FLAG_WO,
  19540         0,
  19541         1,
  19542         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  19543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19544         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19545         -1,
  19546         -1,
  19547     },
  19548 #endif /* chips */
  19549 
  19550 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19551     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  19552     defined(BCM_56640_A0)
  19553     { /* SOC_REG_INT_UDF_CAM_BIST_DBG_DATA_BCM56640_A0r */
  19554         soc_block_list[5],
  19555         soc_genreg,
  19556         1,
  19557         0,
  19558         0xa010700,
  19559         SOC_REG_FLAG_WO,
  19560         0,
  19561         1,
  19562         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
  19563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19564         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19565         -1,
  19566         -1,
  19567     },
  19568 #endif /* chips */
  19569 
  19570 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  19571     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19572     { /* SOC_REG_INT_UDF_CAM_BIST_DBG_DATA_BCM56840_A0r */
  19573         soc_block_list[5],
  19574         soc_genreg,
  19575         1,
  19576         0,
  19577         0x2080d07,
  19578         SOC_REG_FLAG_WO,
  19579         0,
  19580         1,
  19581         soc_FP_CAM_DEBUG_DATA_0r_fields,
  19582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19583         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19584         -1,
  19585         -1,
  19586     },
  19587 #endif /* chips */
  19588 
  19589 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  19590     { /* SOC_REG_INT_UDF_CAM_BIST_DBG_DATA_BCM56850_A0r */
  19591         soc_block_list[5],
  19592         soc_genreg,
  19593         1,
  19594         0,
  19595         0xb070000,
  19596         SOC_REG_FLAG_WO |
  19597                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19598         0,
  19599         1,
  19600         soc_CPU_COS_CAM_BIST_DBG_DATAr_fields,
  19601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19602         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19603         -1,
  19604         -1,
  19605     },
  19606 #endif /* chips */
  19607 
  19608 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19609     { /* SOC_REG_INT_UDF_CAM_BIST_DBG_DATA_BCM56960_A0r */
  19610         soc_block_list[5],
  19611         soc_genreg,
  19612         1,
  19613         0,
  19614         0x2f070000,
  19615         SOC_REG_FLAG_WO |
  19616                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19617         0,
  19618         1,
  19619         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  19620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19621         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19622         -1,
  19623         -1,
  19624         0,
  19625     },
  19626 #endif /* chips */
  19627 
  19628 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19629     { /* SOC_REG_INT_UDF_CAM_BIST_DBG_DATA_PIPE0r */
  19630         soc_block_list[5],
  19631         soc_genreg,
  19632         1,
  19633         0,
  19634         0x2f070000,
  19635         SOC_REG_FLAG_WO,
  19636         0,
  19637         1,
  19638         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  19639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19640         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19641         -1,
  19642         -1,
  19643         0,
  19644     },
  19645 #endif /* chips */
  19646 
  19647 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19648     { /* SOC_REG_INT_UDF_CAM_BIST_DBG_DATA_PIPE1r */
  19649         soc_block_list[5],
  19650         soc_genreg,
  19651         1,
  19652         0,
  19653         0x2f070000,
  19654         SOC_REG_FLAG_WO |
  19655                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19656         0,
  19657         1,
  19658         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  19659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19660         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19661         -1,
  19662         -1,
  19663         0,
  19664     },
  19665 #endif /* chips */
  19666 
  19667 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19668     { /* SOC_REG_INT_UDF_CAM_BIST_DBG_DATA_PIPE2r */
  19669         soc_block_list[5],
  19670         soc_genreg,
  19671         1,
  19672         0,
  19673         0x2f070000,
  19674         SOC_REG_FLAG_WO |
  19675                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19676         0,
  19677         1,
  19678         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  19679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19680         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19681         -1,
  19682         -1,
  19683         0,
  19684     },
  19685 #endif /* chips */
  19686 
  19687 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19688     { /* SOC_REG_INT_UDF_CAM_BIST_DBG_DATA_PIPE3r */
  19689         soc_block_list[5],
  19690         soc_genreg,
  19691         1,
  19692         0,
  19693         0x2f070000,
  19694         SOC_REG_FLAG_WO |
  19695                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19696         0,
  19697         1,
  19698         soc_CPU_COS_CAM_BIST_DBG_DATA_BCM53400_A0r_fields,
  19699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19700         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19701         -1,
  19702         -1,
  19703         0,
  19704     },
  19705 #endif /* chips */
  19706 
  19707 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  19708     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  19709     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  19710     { /* SOC_REG_INT_UDF_CAM_BIST_STATUSr */
  19711         soc_block_list[5],
  19712         soc_genreg,
  19713         1,
  19714         0,
  19715         0x2080115,
  19716         SOC_REG_FLAG_RO,
  19717         0,
  19718         1,
  19719         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  19720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19721         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19722         -1,
  19723         -1,
  19724     },
  19725 #endif /* chips */
  19726 
  19727 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  19728     defined(BCM_56270_A0)
  19729     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_BCM56260_A0r */
  19730         soc_block_list[5],
  19731         soc_genreg,
  19732         1,
  19733         0,
  19734         0xa010500,
  19735         SOC_REG_FLAG_RO,
  19736         0,
  19737         1,
  19738         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19740         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19741         -1,
  19742         -1,
  19743     },
  19744 #endif /* chips */
  19745 
  19746 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  19747     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  19748     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_BCM56560_A0r */
  19749         soc_block_list[5],
  19750         soc_genreg,
  19751         1,
  19752         0,
  19753         0xb050000,
  19754         SOC_REG_FLAG_RO,
  19755         0,
  19756         1,
  19757         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19760         -1,
  19761         -1,
  19762     },
  19763 #endif /* chips */
  19764 
  19765 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  19766     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  19767     defined(BCM_56640_A0)
  19768     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_BCM56640_A0r */
  19769         soc_block_list[5],
  19770         soc_genreg,
  19771         1,
  19772         0,
  19773         0xa010500,
  19774         SOC_REG_FLAG_RO,
  19775         0,
  19776         1,
  19777         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  19778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19779         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19780         -1,
  19781         -1,
  19782     },
  19783 #endif /* chips */
  19784 
  19785 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  19786     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  19787     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_BCM56840_A0r */
  19788         soc_block_list[5],
  19789         soc_genreg,
  19790         1,
  19791         0,
  19792         0x2080d05,
  19793         SOC_REG_FLAG_RO,
  19794         0,
  19795         1,
  19796         soc_FP_CAM_BIST_STATUS_BCM56624_A0r_fields,
  19797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19798         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19799         -1,
  19800         -1,
  19801     },
  19802 #endif /* chips */
  19803 
  19804 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  19805     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_BCM56850_A0r */
  19806         soc_block_list[5],
  19807         soc_genreg,
  19808         1,
  19809         0,
  19810         0xb050000,
  19811         SOC_REG_FLAG_RO |
  19812                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19813         0,
  19814         1,
  19815         soc_ESM_PKT_TYPE_ID_CAM_BIST_STATUSr_fields,
  19816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19817         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19818         -1,
  19819         -1,
  19820     },
  19821 #endif /* chips */
  19822 
  19823 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19824     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_BCM56960_A0r */
  19825         soc_block_list[5],
  19826         soc_genreg,
  19827         1,
  19828         0,
  19829         0x2f050000,
  19830         SOC_REG_FLAG_RO |
  19831                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19832         0,
  19833         1,
  19834         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19836         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19837         -1,
  19838         -1,
  19839         0,
  19840     },
  19841 #endif /* chips */
  19842 
  19843 #if defined(BCM_56970_A0)
  19844     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_BCM56970_A0r */
  19845         soc_block_list[5],
  19846         soc_genreg,
  19847         1,
  19848         0,
  19849         0x53050000,
  19850         SOC_REG_FLAG_RO |
  19851                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19852         0,
  19853         1,
  19854         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19856         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19857         -1,
  19858         -1,
  19859         0,
  19860     },
  19861 #endif /* chips */
  19862 
  19863 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19864     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_PIPE0r */
  19865         soc_block_list[5],
  19866         soc_genreg,
  19867         1,
  19868         0,
  19869         0x2f050000,
  19870         SOC_REG_FLAG_RO,
  19871         0,
  19872         1,
  19873         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19875         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19876         -1,
  19877         -1,
  19878         0,
  19879     },
  19880 #endif /* chips */
  19881 
  19882 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19883     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_PIPE1r */
  19884         soc_block_list[5],
  19885         soc_genreg,
  19886         1,
  19887         0,
  19888         0x2f050000,
  19889         SOC_REG_FLAG_RO |
  19890                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19891         0,
  19892         1,
  19893         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19895         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19896         -1,
  19897         -1,
  19898         0,
  19899     },
  19900 #endif /* chips */
  19901 
  19902 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19903     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_PIPE2r */
  19904         soc_block_list[5],
  19905         soc_genreg,
  19906         1,
  19907         0,
  19908         0x2f050000,
  19909         SOC_REG_FLAG_RO |
  19910                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19911         0,
  19912         1,
  19913         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19915         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19916         -1,
  19917         -1,
  19918         0,
  19919     },
  19920 #endif /* chips */
  19921 
  19922 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  19923     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_PIPE3r */
  19924         soc_block_list[5],
  19925         soc_genreg,
  19926         1,
  19927         0,
  19928         0x2f050000,
  19929         SOC_REG_FLAG_RO |
  19930                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19931         0,
  19932         1,
  19933         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19935         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19936         -1,
  19937         -1,
  19938         0,
  19939     },
  19940 #endif /* chips */
  19941 
  19942 #if defined(BCM_56970_A0)
  19943     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_PIPE0_BCM56970_A0r */
  19944         soc_block_list[5],
  19945         soc_genreg,
  19946         1,
  19947         0,
  19948         0x53050000,
  19949         SOC_REG_FLAG_RO,
  19950         0,
  19951         1,
  19952         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19954         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19955         -1,
  19956         -1,
  19957         0,
  19958     },
  19959 #endif /* chips */
  19960 
  19961 #if defined(BCM_56970_A0)
  19962     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_PIPE1_BCM56970_A0r */
  19963         soc_block_list[5],
  19964         soc_genreg,
  19965         1,
  19966         0,
  19967         0x53050000,
  19968         SOC_REG_FLAG_RO |
  19969                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19970         0,
  19971         1,
  19972         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19974         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19975         -1,
  19976         -1,
  19977         0,
  19978     },
  19979 #endif /* chips */
  19980 
  19981 #if defined(BCM_56970_A0)
  19982     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_PIPE2_BCM56970_A0r */
  19983         soc_block_list[5],
  19984         soc_genreg,
  19985         1,
  19986         0,
  19987         0x53050000,
  19988         SOC_REG_FLAG_RO |
  19989                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  19990         0,
  19991         1,
  19992         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  19993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19994         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19995         -1,
  19996         -1,
  19997         0,
  19998     },
  19999 #endif /* chips */
  20000 
  20001 #if defined(BCM_56970_A0)
  20002     { /* SOC_REG_INT_UDF_CAM_BIST_STATUS_PIPE3_BCM56970_A0r */
  20003         soc_block_list[5],
  20004         soc_genreg,
  20005         1,
  20006         0,
  20007         0x53050000,
  20008         SOC_REG_FLAG_RO |
  20009                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20010         0,
  20011         1,
  20012         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  20013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20014         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20015         -1,
  20016         -1,
  20017         0,
  20018     },
  20019 #endif /* chips */
  20020 
  20021 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  20022     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  20023     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  20024     { /* SOC_REG_INT_UDF_CAM_DBGCTRLr */
  20025         soc_block_list[5],
  20026         soc_genreg,
  20027         1,
  20028         0,
  20029         0x2080114,
  20030         0,
  20031         0,
  20032         3,
  20033         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56624_A0r_fields,
  20034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20035         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20036         -1,
  20037         -1,
  20038     },
  20039 #endif /* chips */
  20040 
  20041 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  20042     defined(BCM_56270_A0)
  20043     { /* SOC_REG_INT_UDF_CAM_DBGCTRL_BCM56260_A0r */
  20044         soc_block_list[5],
  20045         soc_genreg,
  20046         1,
  20047         0,
  20048         0xa010400,
  20049         0,
  20050         0,
  20051         2,
  20052         soc_CPU_COS_CAM_DBGCTRL_BCM53400_A0r_fields,
  20053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20054         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20055         -1,
  20056         -1,
  20057     },
  20058 #endif /* chips */
  20059 
  20060 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  20061     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  20062     { /* SOC_REG_INT_UDF_CAM_DBGCTRL_BCM56560_A0r */
  20063         soc_block_list[5],
  20064         soc_genreg,
  20065         1,
  20066         0,
  20067         0xb040000,
  20068         0,
  20069         0,
  20070         3,
  20071         soc_UDF_CAM_DBGCTRL_BCM56960_A0r_fields,
  20072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20073         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20074         -1,
  20075         -1,
  20076     },
  20077 #endif /* chips */
  20078 
  20079 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  20080     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  20081     defined(BCM_56640_A0)
  20082     { /* SOC_REG_INT_UDF_CAM_DBGCTRL_BCM56640_A0r */
  20083         soc_block_list[5],
  20084         soc_genreg,
  20085         1,
  20086         0,
  20087         0xa010400,
  20088         0,
  20089         0,
  20090         3,
  20091         soc_UDF_CAM_DBGCTRLr_fields,
  20092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20093         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20094         -1,
  20095         -1,
  20096     },
  20097 #endif /* chips */
  20098 
  20099 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  20100     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  20101     { /* SOC_REG_INT_UDF_CAM_DBGCTRL_BCM56840_A0r */
  20102         soc_block_list[5],
  20103         soc_genreg,
  20104         1,
  20105         0,
  20106         0x2080d04,
  20107         0,
  20108         0,
  20109         3,
  20110         soc_VLAN_SUBNET_CAM_DBGCTRL_BCM56624_A0r_fields,
  20111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20112         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20113         -1,
  20114         -1,
  20115     },
  20116 #endif /* chips */
  20117 
  20118 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  20119     { /* SOC_REG_INT_UDF_CAM_DBGCTRL_BCM56850_A0r */
  20120         soc_block_list[5],
  20121         soc_genreg,
  20122         1,
  20123         0,
  20124         0xb040000,
  20125         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20126         0,
  20127         3,
  20128         soc_UDF_CAM_DBGCTRLr_fields,
  20129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20130         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20131         -1,
  20132         -1,
  20133     },
  20134 #endif /* chips */
  20135 
  20136 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20137     { /* SOC_REG_INT_UDF_CAM_DBGCTRL_BCM56960_A0r */
  20138         soc_block_list[5],
  20139         soc_genreg,
  20140         1,
  20141         0,
  20142         0x2f040000,
  20143         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20144         0,
  20145         3,
  20146         soc_UDF_CAM_DBGCTRL_BCM56960_A0r_fields,
  20147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20148         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20149         -1,
  20150         -1,
  20151         0,
  20152     },
  20153 #endif /* chips */
  20154 
  20155 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20156     { /* SOC_REG_INT_UDF_CAM_DBGCTRL_PIPE0r */
  20157         soc_block_list[5],
  20158         soc_genreg,
  20159         1,
  20160         0,
  20161         0x2f040000,
  20162         0,
  20163         0,
  20164         3,
  20165         soc_UDF_CAM_DBGCTRL_BCM56960_A0r_fields,
  20166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20167         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20168         -1,
  20169         -1,
  20170         0,
  20171     },
  20172 #endif /* chips */
  20173 
  20174 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20175     { /* SOC_REG_INT_UDF_CAM_DBGCTRL_PIPE1r */
  20176         soc_block_list[5],
  20177         soc_genreg,
  20178         1,
  20179         0,
  20180         0x2f040000,
  20181         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20182         0,
  20183         3,
  20184         soc_UDF_CAM_DBGCTRL_BCM56960_A0r_fields,
  20185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20187         -1,
  20188         -1,
  20189         0,
  20190     },
  20191 #endif /* chips */
  20192 
  20193 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20194     { /* SOC_REG_INT_UDF_CAM_DBGCTRL_PIPE2r */
  20195         soc_block_list[5],
  20196         soc_genreg,
  20197         1,
  20198         0,
  20199         0x2f040000,
  20200         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20201         0,
  20202         3,
  20203         soc_UDF_CAM_DBGCTRL_BCM56960_A0r_fields,
  20204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20205         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20206         -1,
  20207         -1,
  20208         0,
  20209     },
  20210 #endif /* chips */
  20211 
  20212 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  20213     { /* SOC_REG_INT_UDF_CAM_DBGCTRL_PIPE3r */
  20214         soc_block_list[5],
  20215         soc_genreg,
  20216         1,
  20217         0,
  20218         0x2f040000,
  20219         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20220         0,
  20221         3,
  20222         soc_UDF_CAM_DBGCTRL_BCM56960_A0r_fields,
  20223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20224         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20225         -1,
  20226         -1,
  20227         0,
  20228     },
  20229 #endif /* chips */
  20230 
  20231 #if defined(BCM_56970_A0)
  20232     { /* SOC_REG_INT_UDF_CAM_SERCTRLr */
  20233         soc_block_list[5],
  20234         soc_genreg,
  20235         1,
  20236         0,
  20237         0x53040000,
  20238         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20239         0,
  20240         2,
  20241         soc_CPU_COS_CAM_SERCTRLr_fields,
  20242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20243         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20244         -1,
  20245         -1,
  20246         0,
  20247     },
  20248 #endif /* chips */
  20249 
  20250 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20251     { /* SOC_REG_INT_UDF_CAM_SERCTRL_BCM56980_A0r */
  20252         soc_block_list[5],
  20253         soc_genreg,
  20254         1,
  20255         0,
  20256         0x6010400,
  20257         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20258         0,
  20259         7,
  20260         soc_MY_STATION_TCAM_CAM_SERCTRLr_fields,
  20261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20262         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20263         -1,
  20264         -1,
  20265         3,
  20266     },
  20267 #endif /* chips */
  20268 
  20269 #if defined(BCM_56314_A0) || defined(BCM_56334_A0) || \
  20270     defined(BCM_56334_B0) || defined(BCM_56504_B0) || \
  20271     defined(BCM_56514_A0) || defined(BCM_56624_A0) || \
  20272     defined(BCM_56624_B0) || defined(BCM_56680_A0) || \
  20273     defined(BCM_56680_B0)
  20274     { /* SOC_REG_INT_UDF_ETHERTYPE_MATCHr */
  20275         soc_block_list[5],
  20276         soc_genreg,
  20277         8,
  20278         0,
  20279         0x208001a,
  20280         SOC_REG_FLAG_ARRAY,
  20281         0,
  20282         4,
  20283         soc_UDF_ETHERTYPE_MATCHr_fields,
  20284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20285         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  20286         -1,
  20287         -1,
  20288     },
  20289 #endif /* chips */
  20290 
  20291 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20292     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20293     defined(BCM_56160_A0)
  20294     { /* SOC_REG_INT_UDF_ETHERTYPE_MATCH_BCM53400_A0r */
  20295         soc_block_list[5],
  20296         soc_genreg,
  20297         8,
  20298         0,
  20299         0xa001a00,
  20300         SOC_REG_FLAG_ARRAY,
  20301         0,
  20302         4,
  20303         soc_UDF_ETHERTYPE_MATCH_BCM53400_A0r_fields,
  20304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20305         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  20306         -1,
  20307         -1,
  20308     },
  20309 #endif /* chips */
  20310 
  20311 #if defined(BCM_56142_A0)
  20312     { /* SOC_REG_INT_UDF_ETHERTYPE_MATCH_BCM56142_A0r */
  20313         soc_block_list[5],
  20314         soc_genreg,
  20315         8,
  20316         0,
  20317         0x208001a,
  20318         SOC_REG_FLAG_ARRAY,
  20319         0,
  20320         3,
  20321         soc_UDF_ETHERTYPE_MATCH_BCM56142_A0r_fields,
  20322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20323         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  20324         -1,
  20325         -1,
  20326     },
  20327 #endif /* chips */
  20328 
  20329 #if defined(BCM_56150_A0)
  20330     { /* SOC_REG_INT_UDF_ETHERTYPE_MATCH_BCM56150_A0r */
  20331         soc_block_list[5],
  20332         soc_genreg,
  20333         8,
  20334         0,
  20335         0xa001a00,
  20336         SOC_REG_FLAG_ARRAY,
  20337         0,
  20338         4,
  20339         soc_UDF_ETHERTYPE_MATCH_BCM56150_A0r_fields,
  20340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20341         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  20342         -1,
  20343         -1,
  20344     },
  20345 #endif /* chips */
  20346 
  20347 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  20348     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  20349     { /* SOC_REG_INT_UDF_ETHERTYPE_MATCH_BCM56224_A0r */
  20350         soc_block_list[5],
  20351         soc_genreg,
  20352         8,
  20353         0,
  20354         0x2080000,
  20355         SOC_REG_FLAG_ARRAY,
  20356         0,
  20357         4,
  20358         soc_UDF_ETHERTYPE_MATCHr_fields,
  20359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20360         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  20361         -1,
  20362         -1,
  20363     },
  20364 #endif /* chips */
  20365 
  20366 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  20367     defined(BCM_56820_A0)
  20368     { /* SOC_REG_INT_UDF_ETHERTYPE_MATCH_BCM56800_A0r */
  20369         soc_block_list[5],
  20370         soc_genreg,
  20371         8,
  20372         0,
  20373         0x208061a,
  20374         SOC_REG_FLAG_ARRAY,
  20375         0,
  20376         4,
  20377         soc_UDF_ETHERTYPE_MATCHr_fields,
  20378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20379         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  20380         -1,
  20381         -1,
  20382     },
  20383 #endif /* chips */
  20384 
  20385 #if defined(BCM_88732_A0)
  20386     { /* SOC_REG_INT_UDF_ETHERTYPE_MATCH_BCM88732_A0r */
  20387         soc_block_list[5],
  20388         soc_genreg,
  20389         8,
  20390         0,
  20391         0x2080031,
  20392         SOC_REG_FLAG_ARRAY,
  20393         0,
  20394         3,
  20395         soc_UDF_ETHERTYPE_MATCH_BCM88732_A0r_fields,
  20396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20397         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  20398         -1,
  20399         -1,
  20400     },
  20401 #endif /* chips */
  20402 
  20403 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \
  20404     defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
  20405     defined(BCM_56504_B0) || defined(BCM_56514_A0) || \
  20406     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  20407     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  20408     { /* SOC_REG_INT_UDF_IPPROTO_MATCHr */
  20409         soc_block_list[5],
  20410         soc_genreg,
  20411         2,
  20412         0,
  20413         0x2080022,
  20414         SOC_REG_FLAG_ARRAY,
  20415         0,
  20416         3,
  20417         soc_UDF_IPPROTO_MATCHr_fields,
  20418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20419         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  20420         -1,
  20421         -1,
  20422     },
  20423 #endif /* chips */
  20424 
  20425 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20426     defined(BCM_56160_A0)
  20427     { /* SOC_REG_INT_UDF_IPPROTO_MATCH_BCM53400_A0r */
  20428         soc_block_list[5],
  20429         soc_genreg,
  20430         2,
  20431         0,
  20432         0xa002200,
  20433         SOC_REG_FLAG_ARRAY,
  20434         0,
  20435         3,
  20436         soc_UDF_IPPROTO_MATCH_BCM53400_A0r_fields,
  20437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20438         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  20439         -1,
  20440         -1,
  20441     },
  20442 #endif /* chips */
  20443 
  20444 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  20445     { /* SOC_REG_INT_UDF_IPPROTO_MATCH_BCM53570_A0r */
  20446         soc_block_list[5],
  20447         soc_genreg,
  20448         2,
  20449         0,
  20450         0xa002300,
  20451         SOC_REG_FLAG_ARRAY,
  20452         0,
  20453         3,
  20454         soc_UDF_IPPROTO_MATCH_BCM53400_A0r_fields,
  20455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20456         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  20457         -1,
  20458         -1,
  20459     },
  20460 #endif /* chips */
  20461 
  20462 #if defined(BCM_56150_A0)
  20463     { /* SOC_REG_INT_UDF_IPPROTO_MATCH_BCM56150_A0r */
  20464         soc_block_list[5],
  20465         soc_genreg,
  20466         2,
  20467         0,
  20468         0xa002200,
  20469         SOC_REG_FLAG_ARRAY,
  20470         0,
  20471         3,
  20472         soc_UDF_IPPROTO_MATCH_BCM56150_A0r_fields,
  20473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20474         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  20475         -1,
  20476         -1,
  20477     },
  20478 #endif /* chips */
  20479 
  20480 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  20481     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  20482     { /* SOC_REG_INT_UDF_IPPROTO_MATCH_BCM56224_A0r */
  20483         soc_block_list[5],
  20484         soc_genreg,
  20485         2,
  20486         0,
  20487         0x2080008,
  20488         SOC_REG_FLAG_ARRAY,
  20489         0,
  20490         3,
  20491         soc_UDF_IPPROTO_MATCHr_fields,
  20492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20493         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  20494         -1,
  20495         -1,
  20496     },
  20497 #endif /* chips */
  20498 
  20499 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \
  20500     defined(BCM_56820_A0)
  20501     { /* SOC_REG_INT_UDF_IPPROTO_MATCH_BCM56800_A0r */
  20502         soc_block_list[5],
  20503         soc_genreg,
  20504         2,
  20505         0,
  20506         0x2080622,
  20507         SOC_REG_FLAG_ARRAY,
  20508         0,
  20509         3,
  20510         soc_UDF_IPPROTO_MATCHr_fields,
  20511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20512         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  20513         -1,
  20514         -1,
  20515     },
  20516 #endif /* chips */
  20517 
  20518 #if defined(BCM_88732_A0)
  20519     { /* SOC_REG_INT_UDF_IPPROTO_MATCH_BCM88732_A0r */
  20520         soc_block_list[5],
  20521         soc_genreg,
  20522         2,
  20523         0,
  20524         0x2080039,
  20525         SOC_REG_FLAG_ARRAY,
  20526         0,
  20527         3,
  20528         soc_UDF_IPPROTO_MATCHr_fields,
  20529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20530         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  20531         -1,
  20532         -1,
  20533     },
  20534 #endif /* chips */
  20535 
  20536 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  20537     defined(BCM_56270_A0)
  20538     { /* SOC_REG_INT_UDF_OFFSET_ECC_CONTROLr */
  20539         soc_block_list[5],
  20540         soc_genreg,
  20541         1,
  20542         0,
  20543         0xa011c00,
  20544         0,
  20545         0,
  20546         2,
  20547         soc_EGR_MASK_ECC_CONTROLr_fields,
  20548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20549         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20550         -1,
  20551         -1,
  20552     },
  20553 #endif /* chips */
  20554 
  20555 #if defined(BCM_53400_A0)
  20556     { /* SOC_REG_INT_UDF_OFFSET_PARITY_CONTROLr */
  20557         soc_block_list[5],
  20558         soc_genreg,
  20559         1,
  20560         0,
  20561         0xa010b00,
  20562         0,
  20563         0,
  20564         1,
  20565         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  20566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20567         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20568         -1,
  20569         -1,
  20570     },
  20571 #endif /* chips */
  20572 
  20573 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  20574     { /* SOC_REG_INT_UDF_OFFSET_PARITY_CONTROL_BCM53570_A0r */
  20575         soc_block_list[5],
  20576         soc_genreg,
  20577         1,
  20578         0,
  20579         0xa011000,
  20580         0,
  20581         0,
  20582         1,
  20583         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL_BCM53400_A0r_fields,
  20584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20585         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20586         -1,
  20587         -1,
  20588     },
  20589 #endif /* chips */
  20590 
  20591 #if defined(BCM_53400_A0)
  20592     { /* SOC_REG_INT_UDF_OFFSET_PARITY_STATUSr */
  20593         soc_block_list[5],
  20594         soc_genreg,
  20595         1,
  20596         0,
  20597         0xa010c00,
  20598         0,
  20599         0,
  20600         3,
  20601         soc_EFP_METER_TABLE_PARITY_STATUSr_fields,
  20602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20603         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  20604         -1,
  20605         -1,
  20606     },
  20607 #endif /* chips */
  20608 
  20609 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  20610     { /* SOC_REG_INT_UDF_OFFSET_PARITY_STATUS_BCM53570_A0r */
  20611         soc_block_list[5],
  20612         soc_genreg,
  20613         1,
  20614         0,
  20615         0xa011100,
  20616         0,
  20617         0,
  20618         3,
  20619         soc_EFP_METER_TABLE_PARITY_STATUSr_fields,
  20620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20621         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  20622         -1,
  20623         -1,
  20624     },
  20625 #endif /* chips */
  20626 
  20627 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  20628     { /* SOC_REG_INT_UDF_OFFSET_PARITY_STATUS_BCM56160_A0r */
  20629         soc_block_list[5],
  20630         soc_genreg,
  20631         1,
  20632         0,
  20633         0xa010f00,
  20634         0,
  20635         0,
  20636         3,
  20637         soc_EFP_METER_TABLE_PARITY_STATUSr_fields,
  20638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20639         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  20640         -1,
  20641         -1,
  20642     },
  20643 #endif /* chips */
  20644 
  20645 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20646     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_CONFIGr */
  20647         soc_block_list[5],
  20648         soc_genreg,
  20649         1,
  20650         0,
  20651         0x6010200,
  20652         SOC_REG_FLAG_64_BITS |
  20653                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20654         0,
  20655         5,
  20656         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  20657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20658         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20659         -1,
  20660         -1,
  20661         3,
  20662     },
  20663 #endif /* chips */
  20664 
  20665 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20666     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_CONFIG_PIPE0r */
  20667         soc_block_list[5],
  20668         soc_genreg,
  20669         1,
  20670         0,
  20671         0x6010200,
  20672         SOC_REG_FLAG_64_BITS,
  20673         0,
  20674         5,
  20675         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  20676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20677         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20678         -1,
  20679         -1,
  20680         3,
  20681     },
  20682 #endif /* chips */
  20683 
  20684 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20685     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_CONFIG_PIPE1r */
  20686         soc_block_list[5],
  20687         soc_genreg,
  20688         1,
  20689         0,
  20690         0x6010200,
  20691         SOC_REG_FLAG_64_BITS |
  20692                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20693         0,
  20694         5,
  20695         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  20696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20697         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20698         -1,
  20699         -1,
  20700         3,
  20701     },
  20702 #endif /* chips */
  20703 
  20704 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20705     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_CONFIG_PIPE2r */
  20706         soc_block_list[5],
  20707         soc_genreg,
  20708         1,
  20709         0,
  20710         0x6010200,
  20711         SOC_REG_FLAG_64_BITS |
  20712                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20713         0,
  20714         5,
  20715         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  20716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20717         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20718         -1,
  20719         -1,
  20720         3,
  20721     },
  20722 #endif /* chips */
  20723 
  20724 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20725     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_CONFIG_PIPE3r */
  20726         soc_block_list[5],
  20727         soc_genreg,
  20728         1,
  20729         0,
  20730         0x6010200,
  20731         SOC_REG_FLAG_64_BITS |
  20732                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20733         0,
  20734         5,
  20735         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  20736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20737         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20738         -1,
  20739         -1,
  20740         3,
  20741     },
  20742 #endif /* chips */
  20743 
  20744 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20745     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_CONFIG_PIPE4r */
  20746         soc_block_list[5],
  20747         soc_genreg,
  20748         1,
  20749         0,
  20750         0x6010200,
  20751         SOC_REG_FLAG_64_BITS |
  20752                           (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20753         0,
  20754         5,
  20755         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  20756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20757         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20758         -1,
  20759         -1,
  20760         3,
  20761     },
  20762 #endif /* chips */
  20763 
  20764 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20765     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_CONFIG_PIPE5r */
  20766         soc_block_list[5],
  20767         soc_genreg,
  20768         1,
  20769         0,
  20770         0x6010200,
  20771         SOC_REG_FLAG_64_BITS |
  20772                           (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20773         0,
  20774         5,
  20775         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  20776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20777         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20778         -1,
  20779         -1,
  20780         3,
  20781     },
  20782 #endif /* chips */
  20783 
  20784 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20785     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_CONFIG_PIPE6r */
  20786         soc_block_list[5],
  20787         soc_genreg,
  20788         1,
  20789         0,
  20790         0x6010200,
  20791         SOC_REG_FLAG_64_BITS |
  20792                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20793         0,
  20794         5,
  20795         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  20796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20797         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20798         -1,
  20799         -1,
  20800         3,
  20801     },
  20802 #endif /* chips */
  20803 
  20804 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20805     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_CONFIG_PIPE7r */
  20806         soc_block_list[5],
  20807         soc_genreg,
  20808         1,
  20809         0,
  20810         0x6010200,
  20811         SOC_REG_FLAG_64_BITS |
  20812                           (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20813         0,
  20814         5,
  20815         soc_CPU_COS_MAP_CAM_BIST_CONFIG_64r_fields,
  20816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20817         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20818         -1,
  20819         -1,
  20820         3,
  20821     },
  20822 #endif /* chips */
  20823 
  20824 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20825     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_STATUSr */
  20826         soc_block_list[5],
  20827         soc_genreg,
  20828         1,
  20829         0,
  20830         0x6010300,
  20831         SOC_REG_FLAG_RO |
  20832                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20833         0,
  20834         1,
  20835         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  20836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20837         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20838         -1,
  20839         -1,
  20840         3,
  20841     },
  20842 #endif /* chips */
  20843 
  20844 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20845     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_STATUS_PIPE0r */
  20846         soc_block_list[5],
  20847         soc_genreg,
  20848         1,
  20849         0,
  20850         0x6010300,
  20851         SOC_REG_FLAG_RO,
  20852         0,
  20853         1,
  20854         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  20855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20856         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20857         -1,
  20858         -1,
  20859         3,
  20860     },
  20861 #endif /* chips */
  20862 
  20863 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20864     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_STATUS_PIPE1r */
  20865         soc_block_list[5],
  20866         soc_genreg,
  20867         1,
  20868         0,
  20869         0x6010300,
  20870         SOC_REG_FLAG_RO |
  20871                           (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20872         0,
  20873         1,
  20874         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  20875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20876         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20877         -1,
  20878         -1,
  20879         3,
  20880     },
  20881 #endif /* chips */
  20882 
  20883 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20884     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_STATUS_PIPE2r */
  20885         soc_block_list[5],
  20886         soc_genreg,
  20887         1,
  20888         0,
  20889         0x6010300,
  20890         SOC_REG_FLAG_RO |
  20891                           (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20892         0,
  20893         1,
  20894         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  20895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20896         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20897         -1,
  20898         -1,
  20899         3,
  20900     },
  20901 #endif /* chips */
  20902 
  20903 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20904     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_STATUS_PIPE3r */
  20905         soc_block_list[5],
  20906         soc_genreg,
  20907         1,
  20908         0,
  20909         0x6010300,
  20910         SOC_REG_FLAG_RO |
  20911                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20912         0,
  20913         1,
  20914         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  20915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20916         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20917         -1,
  20918         -1,
  20919         3,
  20920     },
  20921 #endif /* chips */
  20922 
  20923 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20924     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_STATUS_PIPE4r */
  20925         soc_block_list[5],
  20926         soc_genreg,
  20927         1,
  20928         0,
  20929         0x6010300,
  20930         SOC_REG_FLAG_RO |
  20931                           (4 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20932         0,
  20933         1,
  20934         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  20935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20936         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20937         -1,
  20938         -1,
  20939         3,
  20940     },
  20941 #endif /* chips */
  20942 
  20943 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20944     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_STATUS_PIPE5r */
  20945         soc_block_list[5],
  20946         soc_genreg,
  20947         1,
  20948         0,
  20949         0x6010300,
  20950         SOC_REG_FLAG_RO |
  20951                           (5 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20952         0,
  20953         1,
  20954         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  20955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20956         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20957         -1,
  20958         -1,
  20959         3,
  20960     },
  20961 #endif /* chips */
  20962 
  20963 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20964     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_STATUS_PIPE6r */
  20965         soc_block_list[5],
  20966         soc_genreg,
  20967         1,
  20968         0,
  20969         0x6010300,
  20970         SOC_REG_FLAG_RO |
  20971                           (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20972         0,
  20973         1,
  20974         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  20975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20976         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20977         -1,
  20978         -1,
  20979         3,
  20980     },
  20981 #endif /* chips */
  20982 
  20983 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
  20984     { /* SOC_REG_INT_UDF_TCAM_CAM_BIST_STATUS_PIPE7r */
  20985         soc_block_list[5],
  20986         soc_genreg,
  20987         1,
  20988         0,
  20989         0x6010300,
  20990         SOC_REG_FLAG_RO |
  20991                           (7 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  20992         0,
  20993         1,
  20994         soc_FP_CAM_BIST_STATUS_BCM53400_A0r_fields,
  20995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20996         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20997         -1,
  20998         -1,
  20999         3,
  21000     },
  21001 #endif /* chips */
  21002 
  21003 #if defined(BCM_88732_A0)
  21004     { /* SOC_REG_INT_UFLOW_AGED_COUNTr */
  21005         soc_block_list[5],
  21006         soc_genreg,
  21007         2,
  21008         0,
  21009         0x608017c,
  21010         SOC_REG_FLAG_ARRAY,
  21011         0,
  21012         1,
  21013         soc_UFLOW_AGED_COUNTr_fields,
  21014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21016         -1,
  21017         -1,
  21018     },
  21019 #endif /* chips */
  21020 
  21021 #if defined(BCM_88732_A0)
  21022     { /* SOC_REG_INT_UFLOW_DEBUG_RANGEr */
  21023         soc_block_list[5],
  21024         soc_genreg,
  21025         2,
  21026         0,
  21027         0x6080176,
  21028         SOC_REG_FLAG_ARRAY,
  21029         0,
  21030         2,
  21031         soc_UFLOW_DEBUG_RANGEr_fields,
  21032         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
  21033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21034         -1,
  21035         -1,
  21036     },
  21037 #endif /* chips */
  21038 
  21039 #if defined(BCM_88732_A0)
  21040     { /* SOC_REG_INT_UFLOW_HASH_CONTROL_RTAG7r */
  21041         soc_block_list[5],
  21042         soc_genreg,
  21043         2,
  21044         0,
  21045         0x2080044,
  21046         SOC_REG_FLAG_ARRAY,
  21047         0,
  21048         16,
  21049         soc_UFLOW_HASH_CONTROL_RTAG7r_fields,
  21050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21051         SOC_RESET_MASK_DEC(0x01ff6707, 0x00000000)
  21052         -1,
  21053         -1,
  21054     },
  21055 #endif /* chips */
  21056 
  21057 #if defined(BCM_88732_A0)
  21058     { /* SOC_REG_INT_UFLOW_INACTIVE_COUNTr */
  21059         soc_block_list[5],
  21060         soc_genreg,
  21061         2,
  21062         0,
  21063         0x608017a,
  21064         SOC_REG_FLAG_ARRAY,
  21065         0,
  21066         1,
  21067         soc_UFLOW_INACTIVE_COUNTr_fields,
  21068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21069         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21070         -1,
  21071         -1,
  21072     },
  21073 #endif /* chips */
  21074 
  21075 #if defined(BCM_88732_A0)
  21076     { /* SOC_REG_INT_UFLOW_LFSR_CONTROLr */
  21077         soc_block_list[5],
  21078         soc_genreg,
  21079         1,
  21080         0,
  21081         0x608006a,
  21082         SOC_REG_FLAG_64_BITS,
  21083         0,
  21084         2,
  21085         soc_UFLOW_LFSR_CONTROLr_fields,
  21086         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21087         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  21088         -1,
  21089         -1,
  21090     },
  21091 #endif /* chips */
  21092 
  21093 #if defined(BCM_88732_A0)
  21094     { /* SOC_REG_INT_UFLOW_PORT_CONTROLr */
  21095         soc_block_list[5],
  21096         soc_portreg,
  21097         1,
  21098         0,
  21099         0x600006b,
  21100         0,
  21101         0,
  21102         2,
  21103         soc_UFLOW_PORT_CONTROLr_fields,
  21104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21105         SOC_RESET_MASK_DEC(0x0000005f, 0x00000000)
  21106         -1,
  21107         -1,
  21108     },
  21109 #endif /* chips */
  21110 
  21111 #if defined(BCM_88732_A0)
  21112     { /* SOC_REG_INT_UFLOW_REBALANCE_COUNTr */
  21113         soc_block_list[5],
  21114         soc_genreg,
  21115         2,
  21116         0,
  21117         0x6080178,
  21118         SOC_REG_FLAG_ARRAY,
  21119         0,
  21120         1,
  21121         soc_UFLOW_INACTIVE_COUNTr_fields,
  21122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21123         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21124         -1,
  21125         -1,
  21126     },
  21127 #endif /* chips */
  21128 
  21129 #if defined(BCM_88732_A0)
  21130     { /* SOC_REG_INT_UFLOW_TABLE_CONTROLr */
  21131         soc_block_list[5],
  21132         soc_genreg,
  21133         2,
  21134         0,
  21135         0x608006c,
  21136         SOC_REG_FLAG_ARRAY,
  21137         0,
  21138         3,
  21139         soc_UFLOW_TABLE_CONTROLr_fields,
  21140         SOC_RESET_VAL_DEC(0x000001fe, 0x00000000)
  21141         SOC_RESET_MASK_DEC(0x000effff, 0x00000000)
  21142         -1,
  21143         -1,
  21144     },
  21145 #endif /* chips */
  21146 
  21147 #if defined(BCM_88732_A0)
  21148     { /* SOC_REG_INT_UFLOW_TABLE_SIZEr */
  21149         soc_block_list[5],
  21150         soc_genreg,
  21151         1,
  21152         0,
  21153         0x608006e,
  21154         0,
  21155         0,
  21156         2,
  21157         soc_UFLOW_TABLE_SIZEr_fields,
  21158         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  21159         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21160         -1,
  21161         -1,
  21162     },
  21163 #endif /* chips */
  21164 
  21165 #if defined(BCM_88732_A0)
  21166     { /* SOC_REG_INT_UFLOW_TIMER_CONTROLr */
  21167         soc_block_list[5],
  21168         soc_genreg,
  21169         1,
  21170         0,
  21171         0x6080068,
  21172         SOC_REG_FLAG_64_BITS,
  21173         0,
  21174         4,
  21175         soc_UFLOW_TIMER_CONTROLr_fields,
  21176         SOC_RESET_VAL_DEC(0x007f0e0f, 0x0000007f)
  21177         SOC_RESET_MASK_DEC(0x01ffffff, 0x000007ff)
  21178         -1,
  21179         -1,
  21180     },
  21181 #endif /* chips */
  21182 
  21183 #if defined(BCM_88732_A0)
  21184     { /* SOC_REG_INT_UFLOW_TIMER_STATUSr */
  21185         soc_block_list[5],
  21186         soc_genreg,
  21187         1,
  21188         0,
  21189         0x6080069,
  21190         SOC_REG_FLAG_RO,
  21191         0,
  21192         2,
  21193         soc_UFLOW_TIMER_STATUSr_fields,
  21194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21195         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  21196         -1,
  21197         -1,
  21198     },
  21199 #endif /* chips */
  21200 
  21201 #if defined(BCM_53324_A0)
  21202     { /* SOC_REG_INT_UMAC_EEE_CTRLr */
  21203         soc_block_list[2],
  21204         soc_portreg,
  21205         1,
  21206         0,
  21207         0x119,
  21208         0,
  21209         0,
  21210         6,
  21211         soc_UMAC_EEE_CTRLr_fields,
  21212         SOC_RESET_VAL_DEC(0x00000044, 0x00000000)
  21213         SOC_RESET_MASK_DEC(0x000000fc, 0x00000000)
  21214         -1,
  21215         -1,
  21216     },
  21217 #endif /* chips */
  21218 
  21219 #if defined(BCM_53400_A0)
  21220     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM53400_A0r */
  21221         soc_block_list[9],
  21222         soc_portreg,
  21223         1,
  21224         0,
  21225         0x11900,
  21226         0,
  21227         0,
  21228         5,
  21229         soc_UMAC_EEE_CTRL_BCM53400_A0r_fields,
  21230         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21231         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21232         -1,
  21233         -1,
  21234     },
  21235 #endif /* chips */
  21236 
  21237 #if defined(BCM_53540_A0)
  21238     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM53540_A0r */
  21239         soc_block_list[2],
  21240         soc_portreg,
  21241         1,
  21242         0,
  21243         0x11900,
  21244         0,
  21245         0,
  21246         5,
  21247         soc_UMAC_EEE_CTRL_BCM53400_A0r_fields,
  21248         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21249         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21250         -1,
  21251         -1,
  21252     },
  21253 #endif /* chips */
  21254 
  21255 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  21256     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM53570_A0r */
  21257         soc_block_list[2],
  21258         soc_portreg,
  21259         1,
  21260         0,
  21261         0x11900,
  21262         0,
  21263         0,
  21264         6,
  21265         soc_UMAC_EEE_CTRL_BCM53570_A0r_fields,
  21266         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21267         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  21268         -1,
  21269         -1,
  21270     },
  21271 #endif /* chips */
  21272 
  21273 #if defined(BCM_56142_A0)
  21274     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM56142_A0r */
  21275         soc_block_list[210],
  21276         soc_portreg,
  21277         1,
  21278         0,
  21279         0x219,
  21280         0,
  21281         0,
  21282         7,
  21283         soc_UMAC_EEE_CTRL_BCM56840_A0r_fields,
  21284         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21285         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  21286         -1,
  21287         -1,
  21288     },
  21289 #endif /* chips */
  21290 
  21291 #if defined(BCM_56150_A0)
  21292     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM56150_A0r */
  21293         soc_block_list[2],
  21294         soc_portreg,
  21295         1,
  21296         0,
  21297         0x11900,
  21298         0,
  21299         0,
  21300         5,
  21301         soc_UNIMAC0_UMAC_EEE_CTRLr_fields,
  21302         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21303         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21304         -1,
  21305         -1,
  21306     },
  21307 #endif /* chips */
  21308 
  21309 #if defined(BCM_56160_A0)
  21310     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM56160_A0r */
  21311         soc_block_list[2],
  21312         soc_portreg,
  21313         1,
  21314         0,
  21315         0x11900,
  21316         0,
  21317         0,
  21318         5,
  21319         soc_UMAC_EEE_CTRL_BCM53400_A0r_fields,
  21320         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21321         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21322         -1,
  21323         -1,
  21324     },
  21325 #endif /* chips */
  21326 
  21327 #if defined(BCM_56370_A0)
  21328     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM56370_A0r */
  21329         soc_block_list[9],
  21330         soc_portreg,
  21331         1,
  21332         0,
  21333         0x11900,
  21334         0,
  21335         0,
  21336         5,
  21337         soc_UMAC_EEE_CTRL_BCM53400_A0r_fields,
  21338         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21339         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21340         -1,
  21341         -1,
  21342         3,
  21343     },
  21344 #endif /* chips */
  21345 
  21346 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  21347     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM56440_A0r */
  21348         soc_block_list[2],
  21349         soc_portreg,
  21350         1,
  21351         0,
  21352         0x519,
  21353         0,
  21354         0,
  21355         5,
  21356         soc_UMAC_EEE_CTRL_BCM56440_A0r_fields,
  21357         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21358         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21359         -1,
  21360         -1,
  21361     },
  21362 #endif /* chips */
  21363 
  21364 #if defined(BCM_56840_A0)
  21365     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM56840_A0r */
  21366         soc_block_list[16],
  21367         soc_portreg,
  21368         1,
  21369         0,
  21370         0x519,
  21371         0,
  21372         0,
  21373         7,
  21374         soc_UMAC_EEE_CTRL_BCM56840_A0r_fields,
  21375         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21376         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  21377         -1,
  21378         -1,
  21379     },
  21380 #endif /* chips */
  21381 
  21382 #if defined(BCM_56840_B0)
  21383     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM56840_B0r */
  21384         soc_block_list[16],
  21385         soc_portreg,
  21386         1,
  21387         0,
  21388         0x519,
  21389         0,
  21390         0,
  21391         7,
  21392         soc_UMAC_EEE_CTRL_BCM56840_A0r_fields,
  21393         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21394         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  21395         -1,
  21396         -1,
  21397     },
  21398 #endif /* chips */
  21399 
  21400 #if defined(BCM_88375_A0)
  21401     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM88375_A0r */
  21402         soc_block_list[2],
  21403         soc_portreg,
  21404         1,
  21405         0,
  21406         0x11900,
  21407         0,
  21408         0,
  21409         5,
  21410         soc_UMAC_EEE_CTRL_BCM88375_A0r_fields,
  21411         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21412         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21413         -1,
  21414         -1,
  21415     },
  21416 #endif /* chips */
  21417 
  21418 #if defined(BCM_88375_B0)
  21419     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM88375_B0r */
  21420         soc_block_list[2],
  21421         soc_portreg,
  21422         1,
  21423         0,
  21424         0x11900,
  21425         0,
  21426         0,
  21427         5,
  21428         soc_UMAC_EEE_CTRL_BCM88375_B0r_fields,
  21429         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21430         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21431         -1,
  21432         -1,
  21433     },
  21434 #endif /* chips */
  21435 
  21436 #if defined(BCM_88470_A0)
  21437     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM88470_A0r */
  21438         soc_block_list[2],
  21439         soc_portreg,
  21440         1,
  21441         0,
  21442         0x11900,
  21443         0,
  21444         0,
  21445         5,
  21446         soc_UMAC_EEE_CTRL_BCM88470_A0r_fields,
  21447         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21448         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21449         -1,
  21450         -1,
  21451     },
  21452 #endif /* chips */
  21453 
  21454 #if defined(BCM_88470_B0)
  21455     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM88470_B0r */
  21456         soc_block_list[2],
  21457         soc_portreg,
  21458         1,
  21459         0,
  21460         0x11900,
  21461         0,
  21462         0,
  21463         5,
  21464         soc_UMAC_EEE_CTRL_BCM88470_B0r_fields,
  21465         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21466         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21467         -1,
  21468         -1,
  21469     },
  21470 #endif /* chips */
  21471 
  21472 #if defined(BCM_88675_A0)
  21473     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM88675_A0r */
  21474         soc_block_list[2],
  21475         soc_portreg,
  21476         1,
  21477         0,
  21478         0x11900,
  21479         0,
  21480         0,
  21481         5,
  21482         soc_UMAC_EEE_CTRL_BCM88675_A0r_fields,
  21483         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21484         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21485         -1,
  21486         -1,
  21487     },
  21488 #endif /* chips */
  21489 
  21490 #if defined(BCM_88675_B0)
  21491     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM88675_B0r */
  21492         soc_block_list[2],
  21493         soc_portreg,
  21494         1,
  21495         0,
  21496         0x11900,
  21497         0,
  21498         0,
  21499         5,
  21500         soc_UMAC_EEE_CTRL_BCM88675_B0r_fields,
  21501         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21502         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21503         -1,
  21504         -1,
  21505     },
  21506 #endif /* chips */
  21507 
  21508 #if defined(BCM_88680_A0)
  21509     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM88680_A0r */
  21510         soc_block_list[2],
  21511         soc_portreg,
  21512         1,
  21513         0,
  21514         0x11900,
  21515         0,
  21516         0,
  21517         5,
  21518         soc_UMAC_EEE_CTRL_BCM88680_A0r_fields,
  21519         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21520         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  21521         -1,
  21522         -1,
  21523     },
  21524 #endif /* chips */
  21525 
  21526 #if defined(BCM_88732_A0)
  21527     { /* SOC_REG_INT_UMAC_EEE_CTRL_BCM88732_A0r */
  21528         soc_block_list[16],
  21529         soc_portreg,
  21530         1,
  21531         0,
  21532         0x519,
  21533         0,
  21534         0,
  21535         7,
  21536         soc_UMAC_EEE_CTRL_BCM56840_A0r_fields,
  21537         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  21538         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  21539         -1,
  21540         -1,
  21541     },
  21542 #endif /* chips */
  21543 
  21544 #if defined(BCM_53324_A0)
  21545     { /* SOC_REG_INT_UMAC_EEE_REF_COUNTr */
  21546         soc_block_list[2],
  21547         soc_portreg,
  21548         1,
  21549         0,
  21550         0x11c,
  21551         0,
  21552         0,
  21553         1,
  21554         soc_UMAC_EEE_REF_COUNTr_fields,
  21555         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21556         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21557         -1,
  21558         -1,
  21559     },
  21560 #endif /* chips */
  21561 
  21562 #if defined(BCM_53400_A0)
  21563     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM53400_A0r */
  21564         soc_block_list[9],
  21565         soc_portreg,
  21566         1,
  21567         0,
  21568         0x11c00,
  21569         0,
  21570         0,
  21571         1,
  21572         soc_UMAC_EEE_REF_COUNT_BCM53400_A0r_fields,
  21573         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21574         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21575         -1,
  21576         -1,
  21577     },
  21578 #endif /* chips */
  21579 
  21580 #if defined(BCM_53540_A0)
  21581     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM53540_A0r */
  21582         soc_block_list[2],
  21583         soc_portreg,
  21584         1,
  21585         0,
  21586         0x11c00,
  21587         0,
  21588         0,
  21589         1,
  21590         soc_UMAC_EEE_REF_COUNT_BCM53400_A0r_fields,
  21591         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21592         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21593         -1,
  21594         -1,
  21595     },
  21596 #endif /* chips */
  21597 
  21598 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  21599     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM53570_A0r */
  21600         soc_block_list[2],
  21601         soc_portreg,
  21602         1,
  21603         0,
  21604         0x11c00,
  21605         0,
  21606         0,
  21607         1,
  21608         soc_UMAC_EEE_REF_COUNT_BCM53400_A0r_fields,
  21609         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21610         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21611         -1,
  21612         -1,
  21613     },
  21614 #endif /* chips */
  21615 
  21616 #if defined(BCM_56142_A0)
  21617     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM56142_A0r */
  21618         soc_block_list[210],
  21619         soc_portreg,
  21620         1,
  21621         0,
  21622         0x21c,
  21623         0,
  21624         0,
  21625         1,
  21626         soc_UMAC_EEE_REF_COUNTr_fields,
  21627         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21628         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21629         -1,
  21630         -1,
  21631     },
  21632 #endif /* chips */
  21633 
  21634 #if defined(BCM_56150_A0)
  21635     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM56150_A0r */
  21636         soc_block_list[2],
  21637         soc_portreg,
  21638         1,
  21639         0,
  21640         0x11c00,
  21641         0,
  21642         0,
  21643         1,
  21644         soc_UNIMAC0_UMAC_EEE_REF_COUNTr_fields,
  21645         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21646         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21647         -1,
  21648         -1,
  21649     },
  21650 #endif /* chips */
  21651 
  21652 #if defined(BCM_56160_A0)
  21653     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM56160_A0r */
  21654         soc_block_list[2],
  21655         soc_portreg,
  21656         1,
  21657         0,
  21658         0x11c00,
  21659         0,
  21660         0,
  21661         1,
  21662         soc_UMAC_EEE_REF_COUNT_BCM53400_A0r_fields,
  21663         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21664         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21665         -1,
  21666         -1,
  21667     },
  21668 #endif /* chips */
  21669 
  21670 #if defined(BCM_56370_A0)
  21671     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM56370_A0r */
  21672         soc_block_list[9],
  21673         soc_portreg,
  21674         1,
  21675         0,
  21676         0x11c00,
  21677         0,
  21678         0,
  21679         1,
  21680         soc_UMAC_EEE_REF_COUNT_BCM53400_A0r_fields,
  21681         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21682         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21683         -1,
  21684         -1,
  21685         3,
  21686     },
  21687 #endif /* chips */
  21688 
  21689 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  21690     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM56440_A0r */
  21691         soc_block_list[2],
  21692         soc_portreg,
  21693         1,
  21694         0,
  21695         0x51c,
  21696         0,
  21697         0,
  21698         1,
  21699         soc_UMAC_EEE_REF_COUNTr_fields,
  21700         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21701         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21702         -1,
  21703         -1,
  21704     },
  21705 #endif /* chips */
  21706 
  21707 #if defined(BCM_56840_A0)
  21708     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM56840_A0r */
  21709         soc_block_list[16],
  21710         soc_portreg,
  21711         1,
  21712         0,
  21713         0x51c,
  21714         0,
  21715         0,
  21716         1,
  21717         soc_UMAC_EEE_REF_COUNTr_fields,
  21718         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21719         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21720         -1,
  21721         -1,
  21722     },
  21723 #endif /* chips */
  21724 
  21725 #if defined(BCM_56840_B0)
  21726     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM56840_B0r */
  21727         soc_block_list[16],
  21728         soc_portreg,
  21729         1,
  21730         0,
  21731         0x51c,
  21732         0,
  21733         0,
  21734         1,
  21735         soc_UMAC_EEE_REF_COUNTr_fields,
  21736         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21737         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21738         -1,
  21739         -1,
  21740     },
  21741 #endif /* chips */
  21742 
  21743 #if defined(BCM_88375_A0)
  21744     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM88375_A0r */
  21745         soc_block_list[2],
  21746         soc_portreg,
  21747         1,
  21748         0,
  21749         0x11c00,
  21750         0,
  21751         0,
  21752         1,
  21753         soc_UMAC_EEE_REF_COUNT_BCM88375_A0r_fields,
  21754         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21755         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21756         -1,
  21757         -1,
  21758     },
  21759 #endif /* chips */
  21760 
  21761 #if defined(BCM_88375_B0)
  21762     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM88375_B0r */
  21763         soc_block_list[2],
  21764         soc_portreg,
  21765         1,
  21766         0,
  21767         0x11c00,
  21768         0,
  21769         0,
  21770         1,
  21771         soc_UMAC_EEE_REF_COUNT_BCM88375_B0r_fields,
  21772         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21773         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21774         -1,
  21775         -1,
  21776     },
  21777 #endif /* chips */
  21778 
  21779 #if defined(BCM_88470_A0)
  21780     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM88470_A0r */
  21781         soc_block_list[2],
  21782         soc_portreg,
  21783         1,
  21784         0,
  21785         0x11c00,
  21786         0,
  21787         0,
  21788         1,
  21789         soc_UMAC_EEE_REF_COUNT_BCM88470_A0r_fields,
  21790         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21791         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21792         -1,
  21793         -1,
  21794     },
  21795 #endif /* chips */
  21796 
  21797 #if defined(BCM_88470_B0)
  21798     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM88470_B0r */
  21799         soc_block_list[2],
  21800         soc_portreg,
  21801         1,
  21802         0,
  21803         0x11c00,
  21804         0,
  21805         0,
  21806         1,
  21807         soc_UMAC_EEE_REF_COUNT_BCM88470_B0r_fields,
  21808         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21809         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21810         -1,
  21811         -1,
  21812     },
  21813 #endif /* chips */
  21814 
  21815 #if defined(BCM_88675_A0)
  21816     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM88675_A0r */
  21817         soc_block_list[2],
  21818         soc_portreg,
  21819         1,
  21820         0,
  21821         0x11c00,
  21822         0,
  21823         0,
  21824         1,
  21825         soc_UMAC_EEE_REF_COUNT_BCM88675_A0r_fields,
  21826         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21827         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21828         -1,
  21829         -1,
  21830     },
  21831 #endif /* chips */
  21832 
  21833 #if defined(BCM_88675_B0)
  21834     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM88675_B0r */
  21835         soc_block_list[2],
  21836         soc_portreg,
  21837         1,
  21838         0,
  21839         0x11c00,
  21840         0,
  21841         0,
  21842         1,
  21843         soc_UMAC_EEE_REF_COUNT_BCM88675_B0r_fields,
  21844         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21845         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21846         -1,
  21847         -1,
  21848     },
  21849 #endif /* chips */
  21850 
  21851 #if defined(BCM_88680_A0)
  21852     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM88680_A0r */
  21853         soc_block_list[2],
  21854         soc_portreg,
  21855         1,
  21856         0,
  21857         0x11c00,
  21858         0,
  21859         0,
  21860         1,
  21861         soc_UMAC_EEE_REF_COUNT_BCM88680_A0r_fields,
  21862         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21863         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21864         -1,
  21865         -1,
  21866     },
  21867 #endif /* chips */
  21868 
  21869 #if defined(BCM_88732_A0)
  21870     { /* SOC_REG_INT_UMAC_EEE_REF_COUNT_BCM88732_A0r */
  21871         soc_block_list[16],
  21872         soc_portreg,
  21873         1,
  21874         0,
  21875         0x51c,
  21876         0,
  21877         0,
  21878         1,
  21879         soc_UMAC_EEE_REF_COUNTr_fields,
  21880         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  21881         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21882         -1,
  21883         -1,
  21884     },
  21885 #endif /* chips */
  21886 
  21887 #if defined(BCM_88675_A0)
  21888     { /* SOC_REG_INT_UMAC_REV_IDr */
  21889         soc_block_list[2],
  21890         soc_portreg,
  21891         1,
  21892         0,
  21893         0x12200,
  21894         SOC_REG_FLAG_RO |
  21895                           SOC_REG_FLAG_SIGNAL,
  21896         0,
  21897         3,
  21898         soc_UMAC_REV_IDr_fields,
  21899         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  21900         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  21901         -1,
  21902         -1,
  21903     },
  21904 #endif /* chips */
  21905 
  21906 #if defined(BCM_53400_A0)
  21907     { /* SOC_REG_INT_UMAC_REV_ID_BCM53400_A0r */
  21908         soc_block_list[9],
  21909         soc_portreg,
  21910         1,
  21911         0,
  21912         0x12200,
  21913         SOC_REG_FLAG_RO,
  21914         0,
  21915         3,
  21916         soc_UMAC_REV_ID_BCM53400_A0r_fields,
  21917         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  21918         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  21919         -1,
  21920         -1,
  21921     },
  21922 #endif /* chips */
  21923 
  21924 #if defined(BCM_53540_A0)
  21925     { /* SOC_REG_INT_UMAC_REV_ID_BCM53540_A0r */
  21926         soc_block_list[2],
  21927         soc_portreg,
  21928         1,
  21929         0,
  21930         0x12200,
  21931         SOC_REG_FLAG_RO,
  21932         0,
  21933         3,
  21934         soc_UMAC_REV_ID_BCM53400_A0r_fields,
  21935         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  21936         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  21937         -1,
  21938         -1,
  21939     },
  21940 #endif /* chips */
  21941 
  21942 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  21943     { /* SOC_REG_INT_UMAC_REV_ID_BCM53570_A0r */
  21944         soc_block_list[2],
  21945         soc_portreg,
  21946         1,
  21947         0,
  21948         0x12200,
  21949         SOC_REG_FLAG_RO,
  21950         0,
  21951         3,
  21952         soc_UMAC_REV_ID_BCM53570_A0r_fields,
  21953         SOC_RESET_VAL_DEC(0x00040001, 0x00000000)
  21954         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  21955         -1,
  21956         -1,
  21957     },
  21958 #endif /* chips */
  21959 
  21960 #if defined(BCM_56150_A0)
  21961     { /* SOC_REG_INT_UMAC_REV_ID_BCM56150_A0r */
  21962         soc_block_list[2],
  21963         soc_portreg,
  21964         1,
  21965         0,
  21966         0x12200,
  21967         SOC_REG_FLAG_RO,
  21968         0,
  21969         3,
  21970         soc_UMAC_REV_ID_BCM56150_A0r_fields,
  21971         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  21972         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  21973         -1,
  21974         -1,
  21975     },
  21976 #endif /* chips */
  21977 
  21978 #if defined(BCM_56160_A0)
  21979     { /* SOC_REG_INT_UMAC_REV_ID_BCM56160_A0r */
  21980         soc_block_list[2],
  21981         soc_portreg,
  21982         1,
  21983         0,
  21984         0x12200,
  21985         SOC_REG_FLAG_RO,
  21986         0,
  21987         3,
  21988         soc_UMAC_REV_ID_BCM53400_A0r_fields,
  21989         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  21990         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  21991         -1,
  21992         -1,
  21993     },
  21994 #endif /* chips */
  21995 
  21996 #if defined(BCM_56370_A0)
  21997     { /* SOC_REG_INT_UMAC_REV_ID_BCM56370_A0r */
  21998         soc_block_list[9],
  21999         soc_portreg,
  22000         1,
  22001         0,
  22002         0x12200,
  22003         SOC_REG_FLAG_RO,
  22004         0,
  22005         3,
  22006         soc_UMAC_REV_ID_BCM53400_A0r_fields,
  22007         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  22008         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  22009         -1,
  22010         -1,
  22011         3,
  22012     },
  22013 #endif /* chips */
  22014 
  22015 #if defined(BCM_88375_A0)
  22016     { /* SOC_REG_INT_UMAC_REV_ID_BCM88375_A0r */
  22017         soc_block_list[2],
  22018         soc_portreg,
  22019         1,
  22020         0,
  22021         0x12200,
  22022         SOC_REG_FLAG_RO |
  22023                           SOC_REG_FLAG_SIGNAL,
  22024         0,
  22025         3,
  22026         soc_UMAC_REV_ID_BCM88375_A0r_fields,
  22027         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  22028         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  22029         -1,
  22030         -1,
  22031     },
  22032 #endif /* chips */
  22033 
  22034 #if defined(BCM_88375_B0)
  22035     { /* SOC_REG_INT_UMAC_REV_ID_BCM88375_B0r */
  22036         soc_block_list[2],
  22037         soc_portreg,
  22038         1,
  22039         0,
  22040         0x12200,
  22041         SOC_REG_FLAG_RO |
  22042                           SOC_REG_FLAG_SIGNAL,
  22043         0,
  22044         3,
  22045         soc_UMAC_REV_ID_BCM88375_B0r_fields,
  22046         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  22047         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  22048         -1,
  22049         -1,
  22050     },
  22051 #endif /* chips */
  22052 
  22053 #if defined(BCM_88470_A0)
  22054     { /* SOC_REG_INT_UMAC_REV_ID_BCM88470_A0r */
  22055         soc_block_list[2],
  22056         soc_portreg,
  22057         1,
  22058         0,
  22059         0x12200,
  22060         SOC_REG_FLAG_RO |
  22061                           SOC_REG_FLAG_SIGNAL,
  22062         0,
  22063         3,
  22064         soc_UMAC_REV_ID_BCM88470_A0r_fields,
  22065         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  22066         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  22067         -1,
  22068         -1,
  22069     },
  22070 #endif /* chips */
  22071 
  22072 #if defined(BCM_88470_B0)
  22073     { /* SOC_REG_INT_UMAC_REV_ID_BCM88470_B0r */
  22074         soc_block_list[2],
  22075         soc_portreg,
  22076         1,
  22077         0,
  22078         0x12200,
  22079         SOC_REG_FLAG_RO |
  22080                           SOC_REG_FLAG_SIGNAL,
  22081         0,
  22082         3,
  22083         soc_UMAC_REV_ID_BCM88470_B0r_fields,
  22084         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  22085         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  22086         -1,
  22087         -1,
  22088     },
  22089 #endif /* chips */
  22090 
  22091 #if defined(BCM_88675_B0)
  22092     { /* SOC_REG_INT_UMAC_REV_ID_BCM88675_B0r */
  22093         soc_block_list[2],
  22094         soc_portreg,
  22095         1,
  22096         0,
  22097         0x12200,
  22098         SOC_REG_FLAG_RO |
  22099                           SOC_REG_FLAG_SIGNAL,
  22100         0,
  22101         3,
  22102         soc_UMAC_REV_ID_BCM88675_B0r_fields,
  22103         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  22104         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  22105         -1,
  22106         -1,
  22107     },
  22108 #endif /* chips */
  22109 
  22110 #if defined(BCM_88680_A0)
  22111     { /* SOC_REG_INT_UMAC_REV_ID_BCM88680_A0r */
  22112         soc_block_list[2],
  22113         soc_portreg,
  22114         1,
  22115         0,
  22116         0x12200,
  22117         SOC_REG_FLAG_RO |
  22118                           SOC_REG_FLAG_SIGNAL,
  22119         0,
  22120         3,
  22121         soc_UMAC_REV_ID_BCM88680_A0r_fields,
  22122         SOC_RESET_VAL_DEC(0x00030601, 0x00000000)
  22123         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  22124         -1,
  22125         -1,
  22126     },
  22127 #endif /* chips */
  22128 
  22129 #if defined(BCM_88675_A0)
  22130     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUSr */
  22131         soc_block_list[2],
  22132         soc_portreg,
  22133         1,
  22134         0,
  22135         0x11e00,
  22136         0,
  22137         0,
  22138         1,
  22139         soc_UMAC_RX_PKT_DROP_STATUSr_fields,
  22140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22141         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22142         -1,
  22143         -1,
  22144     },
  22145 #endif /* chips */
  22146 
  22147 #if defined(BCM_53400_A0)
  22148     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM53400_A0r */
  22149         soc_block_list[9],
  22150         soc_portreg,
  22151         1,
  22152         0,
  22153         0x11e00,
  22154         0,
  22155         0,
  22156         1,
  22157         soc_UMAC_RX_PKT_DROP_STATUS_BCM53400_A0r_fields,
  22158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22159         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22160         -1,
  22161         -1,
  22162     },
  22163 #endif /* chips */
  22164 
  22165 #if defined(BCM_53540_A0)
  22166     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM53540_A0r */
  22167         soc_block_list[2],
  22168         soc_portreg,
  22169         1,
  22170         0,
  22171         0x11e00,
  22172         0,
  22173         0,
  22174         1,
  22175         soc_UMAC_RX_PKT_DROP_STATUS_BCM53400_A0r_fields,
  22176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22177         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22178         -1,
  22179         -1,
  22180     },
  22181 #endif /* chips */
  22182 
  22183 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  22184     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM53570_A0r */
  22185         soc_block_list[2],
  22186         soc_portreg,
  22187         1,
  22188         0,
  22189         0x11e00,
  22190         0,
  22191         0,
  22192         1,
  22193         soc_UMAC_RX_PKT_DROP_STATUS_BCM53400_A0r_fields,
  22194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22195         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22196         -1,
  22197         -1,
  22198     },
  22199 #endif /* chips */
  22200 
  22201 #if defined(BCM_56150_A0)
  22202     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM56150_A0r */
  22203         soc_block_list[2],
  22204         soc_portreg,
  22205         1,
  22206         0,
  22207         0x11e00,
  22208         0,
  22209         0,
  22210         1,
  22211         soc_UNIMAC0_UMAC_RX_PKT_DROP_STATUSr_fields,
  22212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22213         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22214         -1,
  22215         -1,
  22216     },
  22217 #endif /* chips */
  22218 
  22219 #if defined(BCM_56160_A0)
  22220     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM56160_A0r */
  22221         soc_block_list[2],
  22222         soc_portreg,
  22223         1,
  22224         0,
  22225         0x11e00,
  22226         0,
  22227         0,
  22228         1,
  22229         soc_UMAC_RX_PKT_DROP_STATUS_BCM53400_A0r_fields,
  22230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22231         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22232         -1,
  22233         -1,
  22234     },
  22235 #endif /* chips */
  22236 
  22237 #if defined(BCM_56370_A0)
  22238     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM56370_A0r */
  22239         soc_block_list[9],
  22240         soc_portreg,
  22241         1,
  22242         0,
  22243         0x11e00,
  22244         0,
  22245         0,
  22246         1,
  22247         soc_UMAC_RX_PKT_DROP_STATUS_BCM53400_A0r_fields,
  22248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22249         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22250         -1,
  22251         -1,
  22252         3,
  22253     },
  22254 #endif /* chips */
  22255 
  22256 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  22257     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM56440_A0r */
  22258         soc_block_list[2],
  22259         soc_portreg,
  22260         1,
  22261         0,
  22262         0x51e,
  22263         0,
  22264         0,
  22265         1,
  22266         soc_UMAC_RX_PKT_DROP_STATUS_BCM56440_A0r_fields,
  22267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22268         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22269         -1,
  22270         -1,
  22271     },
  22272 #endif /* chips */
  22273 
  22274 #if defined(BCM_88375_A0)
  22275     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM88375_A0r */
  22276         soc_block_list[2],
  22277         soc_portreg,
  22278         1,
  22279         0,
  22280         0x11e00,
  22281         0,
  22282         0,
  22283         1,
  22284         soc_UMAC_RX_PKT_DROP_STATUS_BCM88375_A0r_fields,
  22285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22286         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22287         -1,
  22288         -1,
  22289     },
  22290 #endif /* chips */
  22291 
  22292 #if defined(BCM_88375_B0)
  22293     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM88375_B0r */
  22294         soc_block_list[2],
  22295         soc_portreg,
  22296         1,
  22297         0,
  22298         0x11e00,
  22299         0,
  22300         0,
  22301         1,
  22302         soc_UMAC_RX_PKT_DROP_STATUS_BCM88375_B0r_fields,
  22303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22304         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22305         -1,
  22306         -1,
  22307     },
  22308 #endif /* chips */
  22309 
  22310 #if defined(BCM_88470_A0)
  22311     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM88470_A0r */
  22312         soc_block_list[2],
  22313         soc_portreg,
  22314         1,
  22315         0,
  22316         0x11e00,
  22317         0,
  22318         0,
  22319         1,
  22320         soc_UMAC_RX_PKT_DROP_STATUS_BCM88470_A0r_fields,
  22321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22322         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22323         -1,
  22324         -1,
  22325     },
  22326 #endif /* chips */
  22327 
  22328 #if defined(BCM_88470_B0)
  22329     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM88470_B0r */
  22330         soc_block_list[2],
  22331         soc_portreg,
  22332         1,
  22333         0,
  22334         0x11e00,
  22335         0,
  22336         0,
  22337         1,
  22338         soc_UMAC_RX_PKT_DROP_STATUS_BCM88470_B0r_fields,
  22339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22340         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22341         -1,
  22342         -1,
  22343     },
  22344 #endif /* chips */
  22345 
  22346 #if defined(BCM_88675_B0)
  22347     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM88675_B0r */
  22348         soc_block_list[2],
  22349         soc_portreg,
  22350         1,
  22351         0,
  22352         0x11e00,
  22353         0,
  22354         0,
  22355         1,
  22356         soc_UMAC_RX_PKT_DROP_STATUS_BCM88675_B0r_fields,
  22357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22358         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22359         -1,
  22360         -1,
  22361     },
  22362 #endif /* chips */
  22363 
  22364 #if defined(BCM_88680_A0)
  22365     { /* SOC_REG_INT_UMAC_RX_PKT_DROP_STATUS_BCM88680_A0r */
  22366         soc_block_list[2],
  22367         soc_portreg,
  22368         1,
  22369         0,
  22370         0x11e00,
  22371         0,
  22372         0,
  22373         1,
  22374         soc_UMAC_RX_PKT_DROP_STATUS_BCM88680_A0r_fields,
  22375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22376         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22377         -1,
  22378         -1,
  22379     },
  22380 #endif /* chips */
  22381 
  22382 #if defined(BCM_53324_A0)
  22383     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLDr */
  22384         soc_block_list[2],
  22385         soc_portreg,
  22386         1,
  22387         0,
  22388         0x11f,
  22389         0,
  22390         0,
  22391         1,
  22392         soc_UMAC_SYMMETRIC_IDLE_THRESHOLDr_fields,
  22393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22394         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22395         -1,
  22396         -1,
  22397     },
  22398 #endif /* chips */
  22399 
  22400 #if defined(BCM_53400_A0)
  22401     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53400_A0r */
  22402         soc_block_list[9],
  22403         soc_portreg,
  22404         1,
  22405         0,
  22406         0x11f00,
  22407         0,
  22408         0,
  22409         1,
  22410         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53400_A0r_fields,
  22411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22412         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22413         -1,
  22414         -1,
  22415     },
  22416 #endif /* chips */
  22417 
  22418 #if defined(BCM_53540_A0)
  22419     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53540_A0r */
  22420         soc_block_list[2],
  22421         soc_portreg,
  22422         1,
  22423         0,
  22424         0x11f00,
  22425         0,
  22426         0,
  22427         1,
  22428         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53400_A0r_fields,
  22429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22430         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22431         -1,
  22432         -1,
  22433     },
  22434 #endif /* chips */
  22435 
  22436 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  22437     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53570_A0r */
  22438         soc_block_list[2],
  22439         soc_portreg,
  22440         1,
  22441         0,
  22442         0x11f00,
  22443         0,
  22444         0,
  22445         1,
  22446         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53400_A0r_fields,
  22447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22448         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22449         -1,
  22450         -1,
  22451     },
  22452 #endif /* chips */
  22453 
  22454 #if defined(BCM_56150_A0)
  22455     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM56150_A0r */
  22456         soc_block_list[2],
  22457         soc_portreg,
  22458         1,
  22459         0,
  22460         0x11f00,
  22461         0,
  22462         0,
  22463         1,
  22464         soc_UNIMAC0_UMAC_SYMMETRIC_IDLE_THRESHOLDr_fields,
  22465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22466         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22467         -1,
  22468         -1,
  22469     },
  22470 #endif /* chips */
  22471 
  22472 #if defined(BCM_56160_A0)
  22473     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM56160_A0r */
  22474         soc_block_list[2],
  22475         soc_portreg,
  22476         1,
  22477         0,
  22478         0x11f00,
  22479         0,
  22480         0,
  22481         1,
  22482         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53400_A0r_fields,
  22483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22484         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22485         -1,
  22486         -1,
  22487     },
  22488 #endif /* chips */
  22489 
  22490 #if defined(BCM_56370_A0)
  22491     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM56370_A0r */
  22492         soc_block_list[9],
  22493         soc_portreg,
  22494         1,
  22495         0,
  22496         0x11f00,
  22497         0,
  22498         0,
  22499         1,
  22500         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53400_A0r_fields,
  22501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22502         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22503         -1,
  22504         -1,
  22505         3,
  22506     },
  22507 #endif /* chips */
  22508 
  22509 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  22510     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM56440_A0r */
  22511         soc_block_list[2],
  22512         soc_portreg,
  22513         1,
  22514         0,
  22515         0x51f,
  22516         0,
  22517         0,
  22518         1,
  22519         soc_UMAC_SYMMETRIC_IDLE_THRESHOLDr_fields,
  22520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22521         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22522         -1,
  22523         -1,
  22524     },
  22525 #endif /* chips */
  22526 
  22527 #if defined(BCM_88375_A0)
  22528     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88375_A0r */
  22529         soc_block_list[2],
  22530         soc_portreg,
  22531         1,
  22532         0,
  22533         0x11f00,
  22534         0,
  22535         0,
  22536         1,
  22537         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88375_A0r_fields,
  22538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22539         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22540         -1,
  22541         -1,
  22542     },
  22543 #endif /* chips */
  22544 
  22545 #if defined(BCM_88375_B0)
  22546     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88375_B0r */
  22547         soc_block_list[2],
  22548         soc_portreg,
  22549         1,
  22550         0,
  22551         0x11f00,
  22552         0,
  22553         0,
  22554         1,
  22555         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88375_B0r_fields,
  22556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22557         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22558         -1,
  22559         -1,
  22560     },
  22561 #endif /* chips */
  22562 
  22563 #if defined(BCM_88470_A0)
  22564     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88470_A0r */
  22565         soc_block_list[2],
  22566         soc_portreg,
  22567         1,
  22568         0,
  22569         0x11f00,
  22570         0,
  22571         0,
  22572         1,
  22573         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88470_A0r_fields,
  22574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22575         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22576         -1,
  22577         -1,
  22578     },
  22579 #endif /* chips */
  22580 
  22581 #if defined(BCM_88470_B0)
  22582     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88470_B0r */
  22583         soc_block_list[2],
  22584         soc_portreg,
  22585         1,
  22586         0,
  22587         0x11f00,
  22588         0,
  22589         0,
  22590         1,
  22591         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88470_B0r_fields,
  22592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22593         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22594         -1,
  22595         -1,
  22596     },
  22597 #endif /* chips */
  22598 
  22599 #if defined(BCM_88675_A0)
  22600     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88675_A0r */
  22601         soc_block_list[2],
  22602         soc_portreg,
  22603         1,
  22604         0,
  22605         0x11f00,
  22606         0,
  22607         0,
  22608         1,
  22609         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88675_A0r_fields,
  22610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22611         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22612         -1,
  22613         -1,
  22614     },
  22615 #endif /* chips */
  22616 
  22617 #if defined(BCM_88675_B0)
  22618     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88675_B0r */
  22619         soc_block_list[2],
  22620         soc_portreg,
  22621         1,
  22622         0,
  22623         0x11f00,
  22624         0,
  22625         0,
  22626         1,
  22627         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88675_B0r_fields,
  22628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22629         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22630         -1,
  22631         -1,
  22632     },
  22633 #endif /* chips */
  22634 
  22635 #if defined(BCM_88680_A0)
  22636     { /* SOC_REG_INT_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88680_A0r */
  22637         soc_block_list[2],
  22638         soc_portreg,
  22639         1,
  22640         0,
  22641         0x11f00,
  22642         0,
  22643         0,
  22644         1,
  22645         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM88680_A0r_fields,
  22646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22647         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  22648         -1,
  22649         -1,
  22650     },
  22651 #endif /* chips */
  22652 
  22653 #if defined(BCM_88675_A0)
  22654     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUSTr */
  22655         soc_block_list[2],
  22656         soc_portreg,
  22657         1,
  22658         0,
  22659         0x11d00,
  22660         0,
  22661         0,
  22662         3,
  22663         soc_UMAC_TIMESTAMP_ADJUSTr_fields,
  22664         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22665         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22666         -1,
  22667         -1,
  22668     },
  22669 #endif /* chips */
  22670 
  22671 #if defined(BCM_53400_A0)
  22672     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM53400_A0r */
  22673         soc_block_list[9],
  22674         soc_portreg,
  22675         1,
  22676         0,
  22677         0x11d00,
  22678         0,
  22679         0,
  22680         3,
  22681         soc_UMAC_TIMESTAMP_ADJUST_BCM53400_A0r_fields,
  22682         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22683         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22684         -1,
  22685         -1,
  22686     },
  22687 #endif /* chips */
  22688 
  22689 #if defined(BCM_53540_A0)
  22690     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM53540_A0r */
  22691         soc_block_list[2],
  22692         soc_portreg,
  22693         1,
  22694         0,
  22695         0x11d00,
  22696         0,
  22697         0,
  22698         3,
  22699         soc_UMAC_TIMESTAMP_ADJUST_BCM53400_A0r_fields,
  22700         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22701         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22702         -1,
  22703         -1,
  22704     },
  22705 #endif /* chips */
  22706 
  22707 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  22708     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM53570_A0r */
  22709         soc_block_list[2],
  22710         soc_portreg,
  22711         1,
  22712         0,
  22713         0x11d00,
  22714         0,
  22715         0,
  22716         3,
  22717         soc_UMAC_TIMESTAMP_ADJUST_BCM53400_A0r_fields,
  22718         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22719         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22720         -1,
  22721         -1,
  22722     },
  22723 #endif /* chips */
  22724 
  22725 #if defined(BCM_56150_A0)
  22726     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM56150_A0r */
  22727         soc_block_list[2],
  22728         soc_portreg,
  22729         1,
  22730         0,
  22731         0x11d00,
  22732         0,
  22733         0,
  22734         3,
  22735         soc_UMAC_TIMESTAMP_ADJUST_BCM56150_A0r_fields,
  22736         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22737         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22738         -1,
  22739         -1,
  22740     },
  22741 #endif /* chips */
  22742 
  22743 #if defined(BCM_56160_A0)
  22744     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM56160_A0r */
  22745         soc_block_list[2],
  22746         soc_portreg,
  22747         1,
  22748         0,
  22749         0x11d00,
  22750         0,
  22751         0,
  22752         3,
  22753         soc_UMAC_TIMESTAMP_ADJUST_BCM53400_A0r_fields,
  22754         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22755         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22756         -1,
  22757         -1,
  22758     },
  22759 #endif /* chips */
  22760 
  22761 #if defined(BCM_56370_A0)
  22762     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM56370_A0r */
  22763         soc_block_list[9],
  22764         soc_portreg,
  22765         1,
  22766         0,
  22767         0x11d00,
  22768         0,
  22769         0,
  22770         3,
  22771         soc_UMAC_TIMESTAMP_ADJUST_BCM53400_A0r_fields,
  22772         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22773         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22774         -1,
  22775         -1,
  22776         3,
  22777     },
  22778 #endif /* chips */
  22779 
  22780 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  22781     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM56440_A0r */
  22782         soc_block_list[2],
  22783         soc_portreg,
  22784         1,
  22785         0,
  22786         0x51d,
  22787         0,
  22788         0,
  22789         3,
  22790         soc_UMAC_TIMESTAMP_ADJUST_BCM56440_A0r_fields,
  22791         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22792         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22793         -1,
  22794         -1,
  22795     },
  22796 #endif /* chips */
  22797 
  22798 #if defined(BCM_88375_A0)
  22799     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM88375_A0r */
  22800         soc_block_list[2],
  22801         soc_portreg,
  22802         1,
  22803         0,
  22804         0x11d00,
  22805         0,
  22806         0,
  22807         3,
  22808         soc_UMAC_TIMESTAMP_ADJUST_BCM88375_A0r_fields,
  22809         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22810         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22811         -1,
  22812         -1,
  22813     },
  22814 #endif /* chips */
  22815 
  22816 #if defined(BCM_88375_B0)
  22817     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM88375_B0r */
  22818         soc_block_list[2],
  22819         soc_portreg,
  22820         1,
  22821         0,
  22822         0x11d00,
  22823         0,
  22824         0,
  22825         3,
  22826         soc_UMAC_TIMESTAMP_ADJUST_BCM88375_B0r_fields,
  22827         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22828         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22829         -1,
  22830         -1,
  22831     },
  22832 #endif /* chips */
  22833 
  22834 #if defined(BCM_88470_A0)
  22835     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM88470_A0r */
  22836         soc_block_list[2],
  22837         soc_portreg,
  22838         1,
  22839         0,
  22840         0x11d00,
  22841         0,
  22842         0,
  22843         3,
  22844         soc_UMAC_TIMESTAMP_ADJUST_BCM88470_A0r_fields,
  22845         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22846         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22847         -1,
  22848         -1,
  22849     },
  22850 #endif /* chips */
  22851 
  22852 #if defined(BCM_88470_B0)
  22853     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM88470_B0r */
  22854         soc_block_list[2],
  22855         soc_portreg,
  22856         1,
  22857         0,
  22858         0x11d00,
  22859         0,
  22860         0,
  22861         3,
  22862         soc_UMAC_TIMESTAMP_ADJUST_BCM88470_B0r_fields,
  22863         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22864         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22865         -1,
  22866         -1,
  22867     },
  22868 #endif /* chips */
  22869 
  22870 #if defined(BCM_88675_B0)
  22871     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM88675_B0r */
  22872         soc_block_list[2],
  22873         soc_portreg,
  22874         1,
  22875         0,
  22876         0x11d00,
  22877         0,
  22878         0,
  22879         3,
  22880         soc_UMAC_TIMESTAMP_ADJUST_BCM88675_B0r_fields,
  22881         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22882         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22883         -1,
  22884         -1,
  22885     },
  22886 #endif /* chips */
  22887 
  22888 #if defined(BCM_88680_A0)
  22889     { /* SOC_REG_INT_UMAC_TIMESTAMP_ADJUST_BCM88680_A0r */
  22890         soc_block_list[2],
  22891         soc_portreg,
  22892         1,
  22893         0,
  22894         0x11d00,
  22895         0,
  22896         0,
  22897         3,
  22898         soc_UMAC_TIMESTAMP_ADJUST_BCM88680_A0r_fields,
  22899         SOC_RESET_VAL_DEC(0x00000600, 0x00000000)
  22900         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22901         -1,
  22902         -1,
  22903     },
  22904 #endif /* chips */
  22905 
  22906 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  22907     { /* SOC_REG_INT_UMAN_EP_FLSH_WAIT_CNTRr */
  22908         soc_block_list[2],
  22909         soc_genreg,
  22910         1,
  22911         0,
  22912         0x80034,
  22913         0,
  22914         0,
  22915         1,
  22916         soc_UMAN_EP_FLSH_WAIT_CNTRr_fields,
  22917         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  22918         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  22919         -1,
  22920         -1,
  22921     },
  22922 #endif /* chips */
  22923 
  22924 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  22925     { /* SOC_REG_INT_UMAN_IP_FLSH_WAIT_CNTRr */
  22926         soc_block_list[2],
  22927         soc_genreg,
  22928         1,
  22929         0,
  22930         0x80035,
  22931         0,
  22932         0,
  22933         1,
  22934         soc_UMAN_IP_FLSH_WAIT_CNTRr_fields,
  22935         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  22936         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  22937         -1,
  22938         -1,
  22939     },
  22940 #endif /* chips */
  22941 
  22942 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  22943     { /* SOC_REG_INT_UMAN_LINKUP_DLY_CNTRr */
  22944         soc_block_list[2],
  22945         soc_genreg,
  22946         1,
  22947         0,
  22948         0x80033,
  22949         0,
  22950         0,
  22951         1,
  22952         soc_UMAN_LINKUP_DLY_CNTRr_fields,
  22953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22954         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22955         -1,
  22956         -1,
  22957     },
  22958 #endif /* chips */
  22959 
  22960 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  22961     defined(BCM_56450_A0)
  22962     { /* SOC_REG_INT_UNIMAC0_COMMAND_CONFIGr */
  22963         soc_block_list[61],
  22964         soc_iprocreg,
  22965         1,
  22966         0,
  22967         0x18022808,
  22968         0,
  22969         0,
  22970         28,
  22971         soc_UNIMAC0_COMMAND_CONFIGr_fields,
  22972         SOC_RESET_VAL_DEC(0x010000db, 0x00000000)
  22973         SOC_RESET_MASK_DEC(0x7fa7dfff, 0x00000000)
  22974         -1,
  22975         -1,
  22976     },
  22977 #endif /* chips */
  22978 
  22979 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22980     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22981     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22982     defined(BCM_56260_B0)
  22983     { /* SOC_REG_INT_UNIMAC0_COMMAND_CONFIG_BCM53400_A0r */
  22984         soc_block_list[61],
  22985         soc_iprocreg,
  22986         1,
  22987         0,
  22988         0x18042808,
  22989         0,
  22990         0,
  22991         28,
  22992         soc_UNIMAC0_COMMAND_CONFIG_BCM53400_A0r_fields,
  22993         SOC_RESET_VAL_DEC(0x010000db, 0x00000000)
  22994         SOC_RESET_MASK_DEC(0x7fa7dfff, 0x00000000)
  22995         -1,
  22996         -1,
  22997     },
  22998 #endif /* chips */
  22999 
  23000 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23001     { /* SOC_REG_INT_UNIMAC0_COMMAND_CONFIG_BCM56450_B0r */
  23002         soc_block_list[61],
  23003         soc_iprocreg,
  23004         1,
  23005         0,
  23006         0x18022808,
  23007         0,
  23008         0,
  23009         28,
  23010         soc_UNIMAC0_COMMAND_CONFIG_BCM56450_B0r_fields,
  23011         SOC_RESET_VAL_DEC(0x010000db, 0x00000000)
  23012         SOC_RESET_MASK_DEC(0x7fa7dfff, 0x00000000)
  23013         -1,
  23014         -1,
  23015     },
  23016 #endif /* chips */
  23017 
  23018 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23019     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23020     defined(BCM_56450_B1)
  23021     { /* SOC_REG_INT_UNIMAC0_FLUSH_CONTROLr */
  23022         soc_block_list[61],
  23023         soc_iprocreg,
  23024         1,
  23025         0,
  23026         0x18022b34,
  23027         0,
  23028         0,
  23029         1,
  23030         soc_UNIMAC0_FLUSH_CONTROLr_fields,
  23031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23032         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23033         -1,
  23034         -1,
  23035     },
  23036 #endif /* chips */
  23037 
  23038 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23039     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23040     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23041     defined(BCM_56260_B0)
  23042     { /* SOC_REG_INT_UNIMAC0_FLUSH_CONTROL_BCM53400_A0r */
  23043         soc_block_list[61],
  23044         soc_iprocreg,
  23045         1,
  23046         0,
  23047         0x18042b34,
  23048         0,
  23049         0,
  23050         1,
  23051         soc_FLUSH_CONTROL_BCM53400_A0r_fields,
  23052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23053         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23054         -1,
  23055         -1,
  23056     },
  23057 #endif /* chips */
  23058 
  23059 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23060     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23061     defined(BCM_56450_B1)
  23062     { /* SOC_REG_INT_UNIMAC0_FRM_LENGTHr */
  23063         soc_block_list[61],
  23064         soc_iprocreg,
  23065         1,
  23066         0,
  23067         0x18022814,
  23068         0,
  23069         0,
  23070         1,
  23071         soc_UNIMAC0_FRM_LENGTHr_fields,
  23072         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  23073         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  23074         -1,
  23075         -1,
  23076     },
  23077 #endif /* chips */
  23078 
  23079 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23080     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23081     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23082     defined(BCM_56260_B0)
  23083     { /* SOC_REG_INT_UNIMAC0_FRM_LENGTH_BCM53400_A0r */
  23084         soc_block_list[61],
  23085         soc_iprocreg,
  23086         1,
  23087         0,
  23088         0x18042814,
  23089         0,
  23090         0,
  23091         1,
  23092         soc_FRM_LENGTH_BCM53400_A0r_fields,
  23093         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  23094         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  23095         -1,
  23096         -1,
  23097     },
  23098 #endif /* chips */
  23099 
  23100 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23101     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23102     defined(BCM_56450_B1)
  23103     { /* SOC_REG_INT_UNIMAC0_GMII_EEE_DELAY_ENTRY_TIMERr */
  23104         soc_block_list[61],
  23105         soc_iprocreg,
  23106         1,
  23107         0,
  23108         0x1802286c,
  23109         0,
  23110         0,
  23111         1,
  23112         soc_UNIMAC0_GMII_EEE_DELAY_ENTRY_TIMERr_fields,
  23113         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23114         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23115         -1,
  23116         -1,
  23117     },
  23118 #endif /* chips */
  23119 
  23120 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23121     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23122     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23123     defined(BCM_56260_B0)
  23124     { /* SOC_REG_INT_UNIMAC0_GMII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r */
  23125         soc_block_list[61],
  23126         soc_iprocreg,
  23127         1,
  23128         0,
  23129         0x1804286c,
  23130         0,
  23131         0,
  23132         1,
  23133         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r_fields,
  23134         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  23135         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23136         -1,
  23137         -1,
  23138     },
  23139 #endif /* chips */
  23140 
  23141 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23142     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23143     defined(BCM_56450_B1)
  23144     { /* SOC_REG_INT_UNIMAC0_GMII_EEE_WAKE_TIMERr */
  23145         soc_block_list[61],
  23146         soc_iprocreg,
  23147         1,
  23148         0,
  23149         0x18022884,
  23150         0,
  23151         0,
  23152         1,
  23153         soc_UNIMAC0_GMII_EEE_WAKE_TIMERr_fields,
  23154         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  23155         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23156         -1,
  23157         -1,
  23158     },
  23159 #endif /* chips */
  23160 
  23161 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23162     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23163     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23164     defined(BCM_56260_B0)
  23165     { /* SOC_REG_INT_UNIMAC0_GMII_EEE_WAKE_TIMER_BCM53400_A0r */
  23166         soc_block_list[61],
  23167         soc_iprocreg,
  23168         1,
  23169         0,
  23170         0x18042884,
  23171         0,
  23172         0,
  23173         1,
  23174         soc_GMII_EEE_WAKE_TIMER_BCM53400_A0r_fields,
  23175         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  23176         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23177         -1,
  23178         -1,
  23179     },
  23180 #endif /* chips */
  23181 
  23182 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23183     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23184     defined(BCM_56450_B1)
  23185     { /* SOC_REG_INT_UNIMAC0_IPG_HD_BKP_CNTLr */
  23186         soc_block_list[61],
  23187         soc_iprocreg,
  23188         1,
  23189         0,
  23190         0x18022804,
  23191         0,
  23192         0,
  23193         3,
  23194         soc_UNIMAC0_IPG_HD_BKP_CNTLr_fields,
  23195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23196         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23197         -1,
  23198         -1,
  23199     },
  23200 #endif /* chips */
  23201 
  23202 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23203     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23204     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23205     defined(BCM_56260_B0)
  23206     { /* SOC_REG_INT_UNIMAC0_IPG_HD_BKP_CNTL_BCM53400_A0r */
  23207         soc_block_list[61],
  23208         soc_iprocreg,
  23209         1,
  23210         0,
  23211         0x18042804,
  23212         0,
  23213         0,
  23214         3,
  23215         soc_IPG_HD_BKP_CNTL_BCM53400_A0r_fields,
  23216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23217         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  23218         -1,
  23219         -1,
  23220     },
  23221 #endif /* chips */
  23222 
  23223 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  23224     { /* SOC_REG_INT_UNIMAC0_MACSEC_CNTRLr */
  23225         soc_block_list[61],
  23226         soc_iprocreg,
  23227         1,
  23228         0,
  23229         0x18042b14,
  23230         0,
  23231         0,
  23232         4,
  23233         soc_MACSEC_CNTRL_BCM53570_A0r_fields,
  23234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23235         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  23236         -1,
  23237         -1,
  23238     },
  23239 #endif /* chips */
  23240 
  23241 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23242     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23243     defined(BCM_56450_B1)
  23244     { /* SOC_REG_INT_UNIMAC0_MAC_0r */
  23245         soc_block_list[61],
  23246         soc_iprocreg,
  23247         1,
  23248         0,
  23249         0x1802280c,
  23250         0,
  23251         0,
  23252         1,
  23253         soc_UNIMAC0_MAC_0r_fields,
  23254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23255         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23256         -1,
  23257         -1,
  23258     },
  23259 #endif /* chips */
  23260 
  23261 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23262     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23263     defined(BCM_56450_B1)
  23264     { /* SOC_REG_INT_UNIMAC0_MAC_1r */
  23265         soc_block_list[61],
  23266         soc_iprocreg,
  23267         1,
  23268         0,
  23269         0x18022810,
  23270         0,
  23271         0,
  23272         1,
  23273         soc_UNIMAC0_MAC_1r_fields,
  23274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23275         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23276         -1,
  23277         -1,
  23278     },
  23279 #endif /* chips */
  23280 
  23281 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23282     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23283     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23284     defined(BCM_56260_B0)
  23285     { /* SOC_REG_INT_UNIMAC0_MAC_0_BCM53400_A0r */
  23286         soc_block_list[61],
  23287         soc_iprocreg,
  23288         1,
  23289         0,
  23290         0x1804280c,
  23291         0,
  23292         0,
  23293         1,
  23294         soc_MAC_0_BCM53400_A0r_fields,
  23295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23296         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23297         -1,
  23298         -1,
  23299     },
  23300 #endif /* chips */
  23301 
  23302 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23303     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23304     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23305     defined(BCM_56260_B0)
  23306     { /* SOC_REG_INT_UNIMAC0_MAC_1_BCM53400_A0r */
  23307         soc_block_list[61],
  23308         soc_iprocreg,
  23309         1,
  23310         0,
  23311         0x18042810,
  23312         0,
  23313         0,
  23314         1,
  23315         soc_MAC_1_BCM53400_A0r_fields,
  23316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23317         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23318         -1,
  23319         -1,
  23320     },
  23321 #endif /* chips */
  23322 
  23323 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23324     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23325     defined(BCM_56450_B1)
  23326     { /* SOC_REG_INT_UNIMAC0_MAC_MODEr */
  23327         soc_block_list[61],
  23328         soc_iprocreg,
  23329         1,
  23330         0,
  23331         0x18022844,
  23332         SOC_REG_FLAG_RO,
  23333         0,
  23334         5,
  23335         soc_UNIMAC0_MAC_MODEr_fields,
  23336         SOC_RESET_VAL_DEC(0x0000001a, 0x00000000)
  23337         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  23338         -1,
  23339         -1,
  23340     },
  23341 #endif /* chips */
  23342 
  23343 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23344     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23345     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23346     defined(BCM_56260_B0)
  23347     { /* SOC_REG_INT_UNIMAC0_MAC_MODE_BCM53400_A0r */
  23348         soc_block_list[61],
  23349         soc_iprocreg,
  23350         1,
  23351         0,
  23352         0x18042844,
  23353         SOC_REG_FLAG_RO,
  23354         0,
  23355         5,
  23356         soc_MAC_MODE_BCM53400_A0r_fields,
  23357         SOC_RESET_VAL_DEC(0x0000001a, 0x00000000)
  23358         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  23359         -1,
  23360         -1,
  23361     },
  23362 #endif /* chips */
  23363 
  23364 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23365     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23366     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_CTRLr */
  23367         soc_block_list[61],
  23368         soc_iprocreg,
  23369         1,
  23370         0,
  23371         0x18022b40,
  23372         0,
  23373         0,
  23374         5,
  23375         soc_UNIMAC0_MAC_PFC_CTRLr_fields,
  23376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23377         SOC_RESET_MASK_DEC(0x00000033, 0x00000000)
  23378         -1,
  23379         -1,
  23380     },
  23381 #endif /* chips */
  23382 
  23383 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  23384     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  23385     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_CTRL_BCM56160_A0r */
  23386         soc_block_list[61],
  23387         soc_iprocreg,
  23388         1,
  23389         0,
  23390         0x18042b40,
  23391         0,
  23392         0,
  23393         5,
  23394         soc_UNIMAC0_MAC_PFC_CTRL_BCM56160_A0r_fields,
  23395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23396         SOC_RESET_MASK_DEC(0x00000033, 0x00000000)
  23397         -1,
  23398         -1,
  23399     },
  23400 #endif /* chips */
  23401 
  23402 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23403     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23404     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_DA_0r */
  23405         soc_block_list[61],
  23406         soc_iprocreg,
  23407         1,
  23408         0,
  23409         0x18022b08,
  23410         0,
  23411         0,
  23412         1,
  23413         soc_UNIMAC0_MAC_PFC_DA_0r_fields,
  23414         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  23415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23416         -1,
  23417         -1,
  23418     },
  23419 #endif /* chips */
  23420 
  23421 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23422     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23423     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_DA_1r */
  23424         soc_block_list[61],
  23425         soc_iprocreg,
  23426         1,
  23427         0,
  23428         0x18022b0c,
  23429         0,
  23430         0,
  23431         1,
  23432         soc_UNIMAC0_MAC_PFC_DA_1r_fields,
  23433         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  23434         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23435         -1,
  23436         -1,
  23437     },
  23438 #endif /* chips */
  23439 
  23440 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  23441     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  23442     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_DA_0_BCM56160_A0r */
  23443         soc_block_list[61],
  23444         soc_iprocreg,
  23445         1,
  23446         0,
  23447         0x18042b08,
  23448         0,
  23449         0,
  23450         1,
  23451         soc_MAC_PFC_DA_0_BCM56160_A0r_fields,
  23452         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  23453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23454         -1,
  23455         -1,
  23456     },
  23457 #endif /* chips */
  23458 
  23459 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  23460     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  23461     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_DA_1_BCM56160_A0r */
  23462         soc_block_list[61],
  23463         soc_iprocreg,
  23464         1,
  23465         0,
  23466         0x18042b0c,
  23467         0,
  23468         0,
  23469         1,
  23470         soc_MAC_PFC_DA_1_BCM56160_A0r_fields,
  23471         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  23472         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23473         -1,
  23474         -1,
  23475     },
  23476 #endif /* chips */
  23477 
  23478 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23479     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23480     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_OPCODEr */
  23481         soc_block_list[61],
  23482         soc_iprocreg,
  23483         1,
  23484         0,
  23485         0x18022b04,
  23486         0,
  23487         0,
  23488         1,
  23489         soc_CMAC_PFC_OPCODEr_fields,
  23490         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  23491         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23492         -1,
  23493         -1,
  23494     },
  23495 #endif /* chips */
  23496 
  23497 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  23498     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  23499     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_OPCODE_BCM56160_A0r */
  23500         soc_block_list[61],
  23501         soc_iprocreg,
  23502         1,
  23503         0,
  23504         0x18042b04,
  23505         0,
  23506         0,
  23507         1,
  23508         soc_CLMAC_PFC_OPCODEr_fields,
  23509         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  23510         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23511         -1,
  23512         -1,
  23513     },
  23514 #endif /* chips */
  23515 
  23516 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23517     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23518     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_REFRESH_CTRLr */
  23519         soc_block_list[61],
  23520         soc_iprocreg,
  23521         1,
  23522         0,
  23523         0x18022b44,
  23524         0,
  23525         0,
  23526         2,
  23527         soc_UNIMAC0_MAC_PFC_REFRESH_CTRLr_fields,
  23528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23529         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23530         -1,
  23531         -1,
  23532     },
  23533 #endif /* chips */
  23534 
  23535 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  23536     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  23537     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_REFRESH_CTRL_BCM56160_A0r */
  23538         soc_block_list[61],
  23539         soc_iprocreg,
  23540         1,
  23541         0,
  23542         0x18042b44,
  23543         0,
  23544         0,
  23545         2,
  23546         soc_MAC_PFC_REFRESH_CTRL_BCM56160_A0r_fields,
  23547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23548         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23549         -1,
  23550         -1,
  23551     },
  23552 #endif /* chips */
  23553 
  23554 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  23555     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  23556     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_TYPEr */
  23557         soc_block_list[61],
  23558         soc_iprocreg,
  23559         1,
  23560         0,
  23561         0x18022b00,
  23562         0,
  23563         0,
  23564         1,
  23565         soc_CMAC_PFC_TYPEr_fields,
  23566         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  23567         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23568         -1,
  23569         -1,
  23570     },
  23571 #endif /* chips */
  23572 
  23573 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  23574     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  23575     { /* SOC_REG_INT_UNIMAC0_MAC_PFC_TYPE_BCM56160_A0r */
  23576         soc_block_list[61],
  23577         soc_iprocreg,
  23578         1,
  23579         0,
  23580         0x18042b00,
  23581         0,
  23582         0,
  23583         1,
  23584         soc_CLMAC_PFC_TYPEr_fields,
  23585         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  23586         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23587         -1,
  23588         -1,
  23589     },
  23590 #endif /* chips */
  23591 
  23592 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23593     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23594     defined(BCM_56450_B1)
  23595     { /* SOC_REG_INT_UNIMAC0_MII_EEE_DELAY_ENTRY_TIMERr */
  23596         soc_block_list[61],
  23597         soc_iprocreg,
  23598         1,
  23599         0,
  23600         0x18022868,
  23601         0,
  23602         0,
  23603         1,
  23604         soc_UNIMAC0_MII_EEE_DELAY_ENTRY_TIMERr_fields,
  23605         SOC_RESET_VAL_DEC(0x00000022, 0x00000000)
  23606         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23607         -1,
  23608         -1,
  23609     },
  23610 #endif /* chips */
  23611 
  23612 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23613     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23614     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23615     defined(BCM_56260_B0)
  23616     { /* SOC_REG_INT_UNIMAC0_MII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r */
  23617         soc_block_list[61],
  23618         soc_iprocreg,
  23619         1,
  23620         0,
  23621         0x18042868,
  23622         0,
  23623         0,
  23624         1,
  23625         soc_MII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r_fields,
  23626         SOC_RESET_VAL_DEC(0x00000022, 0x00000000)
  23627         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23628         -1,
  23629         -1,
  23630     },
  23631 #endif /* chips */
  23632 
  23633 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23634     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23635     defined(BCM_56450_B1)
  23636     { /* SOC_REG_INT_UNIMAC0_MII_EEE_WAKE_TIMERr */
  23637         soc_block_list[61],
  23638         soc_iprocreg,
  23639         1,
  23640         0,
  23641         0x18022880,
  23642         0,
  23643         0,
  23644         1,
  23645         soc_UNIMAC0_MII_EEE_WAKE_TIMERr_fields,
  23646         SOC_RESET_VAL_DEC(0x00000011, 0x00000000)
  23647         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23648         -1,
  23649         -1,
  23650     },
  23651 #endif /* chips */
  23652 
  23653 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23654     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23655     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23656     defined(BCM_56260_B0)
  23657     { /* SOC_REG_INT_UNIMAC0_MII_EEE_WAKE_TIMER_BCM53400_A0r */
  23658         soc_block_list[61],
  23659         soc_iprocreg,
  23660         1,
  23661         0,
  23662         0x18042880,
  23663         0,
  23664         0,
  23665         1,
  23666         soc_MII_EEE_WAKE_TIMER_BCM53400_A0r_fields,
  23667         SOC_RESET_VAL_DEC(0x00000011, 0x00000000)
  23668         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23669         -1,
  23670         -1,
  23671     },
  23672 #endif /* chips */
  23673 
  23674 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23675     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23676     defined(BCM_56450_B1)
  23677     { /* SOC_REG_INT_UNIMAC0_PAUSE_CONTROLr */
  23678         soc_block_list[61],
  23679         soc_iprocreg,
  23680         1,
  23681         0,
  23682         0x18022b30,
  23683         0,
  23684         0,
  23685         2,
  23686         soc_UNIMAC0_PAUSE_CONTROLr_fields,
  23687         SOC_RESET_VAL_DEC(0x0002ffff, 0x00000000)
  23688         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  23689         -1,
  23690         -1,
  23691     },
  23692 #endif /* chips */
  23693 
  23694 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23695     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23696     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23697     defined(BCM_56260_B0)
  23698     { /* SOC_REG_INT_UNIMAC0_PAUSE_CONTROL_BCM53400_A0r */
  23699         soc_block_list[61],
  23700         soc_iprocreg,
  23701         1,
  23702         0,
  23703         0x18042b30,
  23704         0,
  23705         0,
  23706         2,
  23707         soc_PAUSE_CONTROL_BCM53400_A0r_fields,
  23708         SOC_RESET_VAL_DEC(0x0002ffff, 0x00000000)
  23709         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  23710         -1,
  23711         -1,
  23712     },
  23713 #endif /* chips */
  23714 
  23715 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23716     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23717     defined(BCM_56450_B1)
  23718     { /* SOC_REG_INT_UNIMAC0_PAUSE_QUANTr */
  23719         soc_block_list[61],
  23720         soc_iprocreg,
  23721         1,
  23722         0,
  23723         0x18022818,
  23724         0,
  23725         0,
  23726         1,
  23727         soc_UNIMAC0_PAUSE_QUANTr_fields,
  23728         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  23729         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23730         -1,
  23731         -1,
  23732     },
  23733 #endif /* chips */
  23734 
  23735 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23736     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23737     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23738     defined(BCM_56260_B0)
  23739     { /* SOC_REG_INT_UNIMAC0_PAUSE_QUANT_BCM53400_A0r */
  23740         soc_block_list[61],
  23741         soc_iprocreg,
  23742         1,
  23743         0,
  23744         0x18042818,
  23745         0,
  23746         0,
  23747         1,
  23748         soc_PAUSE_QUANT_BCM53400_A0r_fields,
  23749         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  23750         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23751         -1,
  23752         -1,
  23753     },
  23754 #endif /* chips */
  23755 
  23756 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23757     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23758     defined(BCM_56450_B1)
  23759     { /* SOC_REG_INT_UNIMAC0_PFC_XOFF_TIMERr */
  23760         soc_block_list[61],
  23761         soc_iprocreg,
  23762         1,
  23763         0,
  23764         0x18022860,
  23765         0,
  23766         0,
  23767         1,
  23768         soc_UNIMAC0_PFC_XOFF_TIMERr_fields,
  23769         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  23770         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23771         -1,
  23772         -1,
  23773     },
  23774 #endif /* chips */
  23775 
  23776 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23777     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23778     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23779     defined(BCM_56260_B0)
  23780     { /* SOC_REG_INT_UNIMAC0_PFC_XOFF_TIMER_BCM53400_A0r */
  23781         soc_block_list[61],
  23782         soc_iprocreg,
  23783         1,
  23784         0,
  23785         0x18042860,
  23786         0,
  23787         0,
  23788         1,
  23789         soc_PFC_XOFF_TIMER_BCM53400_A0r_fields,
  23790         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  23791         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  23792         -1,
  23793         -1,
  23794     },
  23795 #endif /* chips */
  23796 
  23797 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23798     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23799     defined(BCM_56450_B1)
  23800     { /* SOC_REG_INT_UNIMAC0_RXFIFO_STATr */
  23801         soc_block_list[61],
  23802         soc_iprocreg,
  23803         1,
  23804         0,
  23805         0x18022b38,
  23806         SOC_REG_FLAG_RO,
  23807         0,
  23808         2,
  23809         soc_UNIMAC0_RXFIFO_STATr_fields,
  23810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23811         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23812         -1,
  23813         -1,
  23814     },
  23815 #endif /* chips */
  23816 
  23817 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23818     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23819     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23820     defined(BCM_56260_B0)
  23821     { /* SOC_REG_INT_UNIMAC0_RXFIFO_STAT_BCM53400_A0r */
  23822         soc_block_list[61],
  23823         soc_iprocreg,
  23824         1,
  23825         0,
  23826         0x18042b38,
  23827         SOC_REG_FLAG_RO,
  23828         0,
  23829         2,
  23830         soc_RXFIFO_STAT_BCM53400_A0r_fields,
  23831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23832         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23833         -1,
  23834         -1,
  23835     },
  23836 #endif /* chips */
  23837 
  23838 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23839     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23840     defined(BCM_56450_B1)
  23841     { /* SOC_REG_INT_UNIMAC0_RX_PAUSE_QUANTA_SCALEr */
  23842         soc_block_list[61],
  23843         soc_iprocreg,
  23844         1,
  23845         0,
  23846         0x18022850,
  23847         0,
  23848         0,
  23849         3,
  23850         soc_UNIMAC0_RX_PAUSE_QUANTA_SCALEr_fields,
  23851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23852         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  23853         -1,
  23854         -1,
  23855     },
  23856 #endif /* chips */
  23857 
  23858 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23859     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23860     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23861     defined(BCM_56260_B0)
  23862     { /* SOC_REG_INT_UNIMAC0_RX_PAUSE_QUANTA_SCALE_BCM53400_A0r */
  23863         soc_block_list[61],
  23864         soc_iprocreg,
  23865         1,
  23866         0,
  23867         0x18042850,
  23868         0,
  23869         0,
  23870         3,
  23871         soc_RX_PAUSE_QUANTA_SCALE_BCM53400_A0r_fields,
  23872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23873         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  23874         -1,
  23875         -1,
  23876     },
  23877 #endif /* chips */
  23878 
  23879 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  23880     { /* SOC_REG_INT_UNIMAC0_SFD_OFFSETr */
  23881         soc_block_list[61],
  23882         soc_iprocreg,
  23883         1,
  23884         0,
  23885         0x18042840,
  23886         0,
  23887         0,
  23888         1,
  23889         soc_SFD_OFFSET_BCM53570_A0r_fields,
  23890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23892         -1,
  23893         -1,
  23894     },
  23895 #endif /* chips */
  23896 
  23897 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23898     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23899     defined(BCM_56450_B1)
  23900     { /* SOC_REG_INT_UNIMAC0_TAG_0r */
  23901         soc_block_list[61],
  23902         soc_iprocreg,
  23903         1,
  23904         0,
  23905         0x18022848,
  23906         0,
  23907         0,
  23908         2,
  23909         soc_UNIMAC0_TAG_0r_fields,
  23910         SOC_RESET_VAL_DEC(0x00018100, 0x00000000)
  23911         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  23912         -1,
  23913         -1,
  23914     },
  23915 #endif /* chips */
  23916 
  23917 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23918     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23919     defined(BCM_56450_B1)
  23920     { /* SOC_REG_INT_UNIMAC0_TAG_1r */
  23921         soc_block_list[61],
  23922         soc_iprocreg,
  23923         1,
  23924         0,
  23925         0x1802284c,
  23926         0,
  23927         0,
  23928         2,
  23929         soc_UNIMAC0_TAG_1r_fields,
  23930         SOC_RESET_VAL_DEC(0x00018100, 0x00000000)
  23931         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  23932         -1,
  23933         -1,
  23934     },
  23935 #endif /* chips */
  23936 
  23937 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23938     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23939     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23940     defined(BCM_56260_B0)
  23941     { /* SOC_REG_INT_UNIMAC0_TAG_0_BCM53400_A0r */
  23942         soc_block_list[61],
  23943         soc_iprocreg,
  23944         1,
  23945         0,
  23946         0x18042848,
  23947         0,
  23948         0,
  23949         2,
  23950         soc_TAG_0_BCM53400_A0r_fields,
  23951         SOC_RESET_VAL_DEC(0x00018100, 0x00000000)
  23952         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  23953         -1,
  23954         -1,
  23955     },
  23956 #endif /* chips */
  23957 
  23958 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23959     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23960     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23961     defined(BCM_56260_B0)
  23962     { /* SOC_REG_INT_UNIMAC0_TAG_1_BCM53400_A0r */
  23963         soc_block_list[61],
  23964         soc_iprocreg,
  23965         1,
  23966         0,
  23967         0x1804284c,
  23968         0,
  23969         0,
  23970         2,
  23971         soc_TAG_1_BCM53400_A0r_fields,
  23972         SOC_RESET_VAL_DEC(0x00018100, 0x00000000)
  23973         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  23974         -1,
  23975         -1,
  23976     },
  23977 #endif /* chips */
  23978 
  23979 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23980     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23981     defined(BCM_56450_B1)
  23982     { /* SOC_REG_INT_UNIMAC0_TS_STATUS_CNTRLr */
  23983         soc_block_list[61],
  23984         soc_iprocreg,
  23985         1,
  23986         0,
  23987         0x18022b18,
  23988         SOC_REG_FLAG_RO,
  23989         0,
  23990         3,
  23991         soc_UNIMAC0_TS_STATUS_CNTRLr_fields,
  23992         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  23993         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  23994         -1,
  23995         -1,
  23996     },
  23997 #endif /* chips */
  23998 
  23999 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24000     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24001     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24002     defined(BCM_56260_B0)
  24003     { /* SOC_REG_INT_UNIMAC0_TS_STATUS_CNTRL_BCM53400_A0r */
  24004         soc_block_list[61],
  24005         soc_iprocreg,
  24006         1,
  24007         0,
  24008         0x18042b18,
  24009         SOC_REG_FLAG_RO,
  24010         0,
  24011         3,
  24012         soc_TS_STATUS_CNTRL_BCM53400_A0r_fields,
  24013         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  24014         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  24015         -1,
  24016         -1,
  24017     },
  24018 #endif /* chips */
  24019 
  24020 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24021     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24022     defined(BCM_56450_B1)
  24023     { /* SOC_REG_INT_UNIMAC0_TXFIFO_STATr */
  24024         soc_block_list[61],
  24025         soc_iprocreg,
  24026         1,
  24027         0,
  24028         0x18022b3c,
  24029         SOC_REG_FLAG_RO,
  24030         0,
  24031         2,
  24032         soc_UNIMAC0_TXFIFO_STATr_fields,
  24033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24034         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24035         -1,
  24036         -1,
  24037     },
  24038 #endif /* chips */
  24039 
  24040 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24041     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24042     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24043     defined(BCM_56260_B0)
  24044     { /* SOC_REG_INT_UNIMAC0_TXFIFO_STAT_BCM53400_A0r */
  24045         soc_block_list[61],
  24046         soc_iprocreg,
  24047         1,
  24048         0,
  24049         0x18042b3c,
  24050         SOC_REG_FLAG_RO,
  24051         0,
  24052         2,
  24053         soc_TXFIFO_STAT_BCM53400_A0r_fields,
  24054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24055         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24056         -1,
  24057         -1,
  24058     },
  24059 #endif /* chips */
  24060 
  24061 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24062     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24063     defined(BCM_56450_B1)
  24064     { /* SOC_REG_INT_UNIMAC0_TX_IPG_LENGTHr */
  24065         soc_block_list[61],
  24066         soc_iprocreg,
  24067         1,
  24068         0,
  24069         0x1802285c,
  24070         0,
  24071         0,
  24072         1,
  24073         soc_UNIMAC0_TX_IPG_LENGTHr_fields,
  24074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24075         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  24076         -1,
  24077         -1,
  24078     },
  24079 #endif /* chips */
  24080 
  24081 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24082     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24083     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24084     defined(BCM_56260_B0)
  24085     { /* SOC_REG_INT_UNIMAC0_TX_IPG_LENGTH_BCM53400_A0r */
  24086         soc_block_list[61],
  24087         soc_iprocreg,
  24088         1,
  24089         0,
  24090         0x1804285c,
  24091         0,
  24092         0,
  24093         1,
  24094         soc_TX_IPG_LENGTH_BCM53400_A0r_fields,
  24095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24096         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  24097         -1,
  24098         -1,
  24099     },
  24100 #endif /* chips */
  24101 
  24102 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24103     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24104     defined(BCM_56450_B1)
  24105     { /* SOC_REG_INT_UNIMAC0_TX_PREAMBLEr */
  24106         soc_block_list[61],
  24107         soc_iprocreg,
  24108         1,
  24109         0,
  24110         0x18022854,
  24111         0,
  24112         0,
  24113         1,
  24114         soc_UNIMAC0_TX_PREAMBLEr_fields,
  24115         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  24116         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  24117         -1,
  24118         -1,
  24119     },
  24120 #endif /* chips */
  24121 
  24122 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24123     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24124     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24125     defined(BCM_56260_B0)
  24126     { /* SOC_REG_INT_UNIMAC0_TX_PREAMBLE_BCM53400_A0r */
  24127         soc_block_list[61],
  24128         soc_iprocreg,
  24129         1,
  24130         0,
  24131         0x18042854,
  24132         0,
  24133         0,
  24134         1,
  24135         soc_TX_PREAMBLE_BCM53400_A0r_fields,
  24136         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  24137         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  24138         -1,
  24139         -1,
  24140     },
  24141 #endif /* chips */
  24142 
  24143 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24144     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24145     defined(BCM_56450_B1)
  24146     { /* SOC_REG_INT_UNIMAC0_TX_TS_DATAr */
  24147         soc_block_list[61],
  24148         soc_iprocreg,
  24149         1,
  24150         0,
  24151         0x18022b1c,
  24152         SOC_REG_FLAG_RO,
  24153         0,
  24154         1,
  24155         soc_UNIMAC0_TX_TS_DATAr_fields,
  24156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24157         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24158         -1,
  24159         -1,
  24160     },
  24161 #endif /* chips */
  24162 
  24163 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24164     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24165     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24166     defined(BCM_56260_B0)
  24167     { /* SOC_REG_INT_UNIMAC0_TX_TS_DATA_BCM53400_A0r */
  24168         soc_block_list[61],
  24169         soc_iprocreg,
  24170         1,
  24171         0,
  24172         0x18042b1c,
  24173         SOC_REG_FLAG_RO,
  24174         0,
  24175         1,
  24176         soc_TX_TS_DATA_BCM53400_A0r_fields,
  24177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24178         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24179         -1,
  24180         -1,
  24181     },
  24182 #endif /* chips */
  24183 
  24184 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24185     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24186     defined(BCM_56450_B1)
  24187     { /* SOC_REG_INT_UNIMAC0_TX_TS_SEQ_IDr */
  24188         soc_block_list[61],
  24189         soc_iprocreg,
  24190         1,
  24191         0,
  24192         0x1802283c,
  24193         SOC_REG_FLAG_RO,
  24194         0,
  24195         2,
  24196         soc_UNIMAC0_TX_TS_SEQ_IDr_fields,
  24197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24198         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  24199         -1,
  24200         -1,
  24201     },
  24202 #endif /* chips */
  24203 
  24204 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24205     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24206     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24207     defined(BCM_56260_B0)
  24208     { /* SOC_REG_INT_UNIMAC0_TX_TS_SEQ_ID_BCM53400_A0r */
  24209         soc_block_list[61],
  24210         soc_iprocreg,
  24211         1,
  24212         0,
  24213         0x1804283c,
  24214         SOC_REG_FLAG_RO,
  24215         0,
  24216         2,
  24217         soc_TX_TS_SEQ_ID_BCM53400_A0r_fields,
  24218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24219         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  24220         -1,
  24221         -1,
  24222     },
  24223 #endif /* chips */
  24224 
  24225 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24226     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24227     defined(BCM_56450_B1)
  24228     { /* SOC_REG_INT_UNIMAC0_UMAC_EEE_CTRLr */
  24229         soc_block_list[61],
  24230         soc_iprocreg,
  24231         1,
  24232         0,
  24233         0x18022864,
  24234         0,
  24235         0,
  24236         5,
  24237         soc_UNIMAC0_UMAC_EEE_CTRLr_fields,
  24238         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  24239         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  24240         -1,
  24241         -1,
  24242     },
  24243 #endif /* chips */
  24244 
  24245 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24246     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24247     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24248     defined(BCM_56260_B0)
  24249     { /* SOC_REG_INT_UNIMAC0_UMAC_EEE_CTRL_BCM53400_A0r */
  24250         soc_block_list[61],
  24251         soc_iprocreg,
  24252         1,
  24253         0,
  24254         0x18042864,
  24255         0,
  24256         0,
  24257         5,
  24258         soc_UMAC_EEE_CTRL_BCM53400_A0r_fields,
  24259         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  24260         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  24261         -1,
  24262         -1,
  24263     },
  24264 #endif /* chips */
  24265 
  24266 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24267     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24268     defined(BCM_56450_B1)
  24269     { /* SOC_REG_INT_UNIMAC0_UMAC_EEE_REF_COUNTr */
  24270         soc_block_list[61],
  24271         soc_iprocreg,
  24272         1,
  24273         0,
  24274         0x18022870,
  24275         0,
  24276         0,
  24277         1,
  24278         soc_UNIMAC0_UMAC_EEE_REF_COUNTr_fields,
  24279         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  24280         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24281         -1,
  24282         -1,
  24283     },
  24284 #endif /* chips */
  24285 
  24286 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24287     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24288     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24289     defined(BCM_56260_B0)
  24290     { /* SOC_REG_INT_UNIMAC0_UMAC_EEE_REF_COUNT_BCM53400_A0r */
  24291         soc_block_list[61],
  24292         soc_iprocreg,
  24293         1,
  24294         0,
  24295         0x18042870,
  24296         0,
  24297         0,
  24298         1,
  24299         soc_UMAC_EEE_REF_COUNT_BCM53400_A0r_fields,
  24300         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  24301         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24302         -1,
  24303         -1,
  24304     },
  24305 #endif /* chips */
  24306 
  24307 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24308     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24309     defined(BCM_56450_B1)
  24310     { /* SOC_REG_INT_UNIMAC0_UMAC_REV_IDr */
  24311         soc_block_list[61],
  24312         soc_iprocreg,
  24313         1,
  24314         0,
  24315         0x18022888,
  24316         SOC_REG_FLAG_RO,
  24317         0,
  24318         3,
  24319         soc_UNIMAC0_UMAC_REV_IDr_fields,
  24320         SOC_RESET_VAL_DEC(0x00030500, 0x00000000)
  24321         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  24322         -1,
  24323         -1,
  24324     },
  24325 #endif /* chips */
  24326 
  24327 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24328     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24329     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24330     defined(BCM_56260_B0)
  24331     { /* SOC_REG_INT_UNIMAC0_UMAC_REV_ID_BCM53400_A0r */
  24332         soc_block_list[61],
  24333         soc_iprocreg,
  24334         1,
  24335         0,
  24336         0x18042888,
  24337         SOC_REG_FLAG_RO,
  24338         0,
  24339         3,
  24340         soc_UNIMAC0_UMAC_REV_ID_BCM53400_A0r_fields,
  24341         SOC_RESET_VAL_DEC(0x00030500, 0x00000000)
  24342         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  24343         -1,
  24344         -1,
  24345     },
  24346 #endif /* chips */
  24347 
  24348 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24349     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24350     defined(BCM_56450_B1)
  24351     { /* SOC_REG_INT_UNIMAC0_UMAC_RX_PKT_DROP_STATUSr */
  24352         soc_block_list[61],
  24353         soc_iprocreg,
  24354         1,
  24355         0,
  24356         0x18022878,
  24357         0,
  24358         0,
  24359         1,
  24360         soc_UNIMAC0_UMAC_RX_PKT_DROP_STATUSr_fields,
  24361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24362         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24363         -1,
  24364         -1,
  24365     },
  24366 #endif /* chips */
  24367 
  24368 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24369     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24370     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24371     defined(BCM_56260_B0)
  24372     { /* SOC_REG_INT_UNIMAC0_UMAC_RX_PKT_DROP_STATUS_BCM53400_A0r */
  24373         soc_block_list[61],
  24374         soc_iprocreg,
  24375         1,
  24376         0,
  24377         0x18042878,
  24378         0,
  24379         0,
  24380         1,
  24381         soc_UMAC_RX_PKT_DROP_STATUS_BCM53400_A0r_fields,
  24382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24383         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24384         -1,
  24385         -1,
  24386     },
  24387 #endif /* chips */
  24388 
  24389 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24390     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24391     defined(BCM_56450_B1)
  24392     { /* SOC_REG_INT_UNIMAC0_UMAC_SYMMETRIC_IDLE_THRESHOLDr */
  24393         soc_block_list[61],
  24394         soc_iprocreg,
  24395         1,
  24396         0,
  24397         0x1802287c,
  24398         0,
  24399         0,
  24400         1,
  24401         soc_UNIMAC0_UMAC_SYMMETRIC_IDLE_THRESHOLDr_fields,
  24402         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24403         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24404         -1,
  24405         -1,
  24406     },
  24407 #endif /* chips */
  24408 
  24409 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24410     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24411     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24412     defined(BCM_56260_B0)
  24413     { /* SOC_REG_INT_UNIMAC0_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53400_A0r */
  24414         soc_block_list[61],
  24415         soc_iprocreg,
  24416         1,
  24417         0,
  24418         0x1804287c,
  24419         0,
  24420         0,
  24421         1,
  24422         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53400_A0r_fields,
  24423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24424         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24425         -1,
  24426         -1,
  24427     },
  24428 #endif /* chips */
  24429 
  24430 #if defined(BCM_56340_A0) || defined(BCM_56450_A0)
  24431     { /* SOC_REG_INT_UNIMAC1_COMMAND_CONFIGr */
  24432         soc_block_list[61],
  24433         soc_iprocreg,
  24434         1,
  24435         0,
  24436         0x18023808,
  24437         0,
  24438         0,
  24439         28,
  24440         soc_UNIMAC0_COMMAND_CONFIGr_fields,
  24441         SOC_RESET_VAL_DEC(0x010000db, 0x00000000)
  24442         SOC_RESET_MASK_DEC(0x7fa7dfff, 0x00000000)
  24443         -1,
  24444         -1,
  24445     },
  24446 #endif /* chips */
  24447 
  24448 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24449     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24450     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24451     defined(BCM_56260_B0)
  24452     { /* SOC_REG_INT_UNIMAC1_COMMAND_CONFIG_BCM53400_A0r */
  24453         soc_block_list[61],
  24454         soc_iprocreg,
  24455         1,
  24456         0,
  24457         0x1804a808,
  24458         0,
  24459         0,
  24460         28,
  24461         soc_UNIMAC0_COMMAND_CONFIG_BCM53400_A0r_fields,
  24462         SOC_RESET_VAL_DEC(0x010000db, 0x00000000)
  24463         SOC_RESET_MASK_DEC(0x7fa7dfff, 0x00000000)
  24464         -1,
  24465         -1,
  24466     },
  24467 #endif /* chips */
  24468 
  24469 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24470     { /* SOC_REG_INT_UNIMAC1_COMMAND_CONFIG_BCM56450_B0r */
  24471         soc_block_list[61],
  24472         soc_iprocreg,
  24473         1,
  24474         0,
  24475         0x18023808,
  24476         0,
  24477         0,
  24478         28,
  24479         soc_UNIMAC0_COMMAND_CONFIG_BCM56450_B0r_fields,
  24480         SOC_RESET_VAL_DEC(0x010000db, 0x00000000)
  24481         SOC_RESET_MASK_DEC(0x7fa7dfff, 0x00000000)
  24482         -1,
  24483         -1,
  24484     },
  24485 #endif /* chips */
  24486 
  24487 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24488     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24489     { /* SOC_REG_INT_UNIMAC1_FLUSH_CONTROLr */
  24490         soc_block_list[61],
  24491         soc_iprocreg,
  24492         1,
  24493         0,
  24494         0x18023b34,
  24495         0,
  24496         0,
  24497         1,
  24498         soc_UNIMAC0_FLUSH_CONTROLr_fields,
  24499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24500         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24501         -1,
  24502         -1,
  24503     },
  24504 #endif /* chips */
  24505 
  24506 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24507     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24508     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24509     defined(BCM_56260_B0)
  24510     { /* SOC_REG_INT_UNIMAC1_FLUSH_CONTROL_BCM53400_A0r */
  24511         soc_block_list[61],
  24512         soc_iprocreg,
  24513         1,
  24514         0,
  24515         0x1804ab34,
  24516         0,
  24517         0,
  24518         1,
  24519         soc_FLUSH_CONTROL_BCM53400_A0r_fields,
  24520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24521         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24522         -1,
  24523         -1,
  24524     },
  24525 #endif /* chips */
  24526 
  24527 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24528     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24529     { /* SOC_REG_INT_UNIMAC1_FRM_LENGTHr */
  24530         soc_block_list[61],
  24531         soc_iprocreg,
  24532         1,
  24533         0,
  24534         0x18023814,
  24535         0,
  24536         0,
  24537         1,
  24538         soc_UNIMAC0_FRM_LENGTHr_fields,
  24539         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24540         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24541         -1,
  24542         -1,
  24543     },
  24544 #endif /* chips */
  24545 
  24546 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24547     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24548     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24549     defined(BCM_56260_B0)
  24550     { /* SOC_REG_INT_UNIMAC1_FRM_LENGTH_BCM53400_A0r */
  24551         soc_block_list[61],
  24552         soc_iprocreg,
  24553         1,
  24554         0,
  24555         0x1804a814,
  24556         0,
  24557         0,
  24558         1,
  24559         soc_FRM_LENGTH_BCM53400_A0r_fields,
  24560         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
  24561         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24562         -1,
  24563         -1,
  24564     },
  24565 #endif /* chips */
  24566 
  24567 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24568     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24569     { /* SOC_REG_INT_UNIMAC1_GMII_EEE_DELAY_ENTRY_TIMERr */
  24570         soc_block_list[61],
  24571         soc_iprocreg,
  24572         1,
  24573         0,
  24574         0x1802386c,
  24575         0,
  24576         0,
  24577         1,
  24578         soc_UNIMAC0_GMII_EEE_DELAY_ENTRY_TIMERr_fields,
  24579         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  24580         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24581         -1,
  24582         -1,
  24583     },
  24584 #endif /* chips */
  24585 
  24586 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24587     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24588     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24589     defined(BCM_56260_B0)
  24590     { /* SOC_REG_INT_UNIMAC1_GMII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r */
  24591         soc_block_list[61],
  24592         soc_iprocreg,
  24593         1,
  24594         0,
  24595         0x1804a86c,
  24596         0,
  24597         0,
  24598         1,
  24599         soc_GMII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r_fields,
  24600         SOC_RESET_VAL_DEC(0x0000003c, 0x00000000)
  24601         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24602         -1,
  24603         -1,
  24604     },
  24605 #endif /* chips */
  24606 
  24607 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24608     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24609     { /* SOC_REG_INT_UNIMAC1_GMII_EEE_WAKE_TIMERr */
  24610         soc_block_list[61],
  24611         soc_iprocreg,
  24612         1,
  24613         0,
  24614         0x18023884,
  24615         0,
  24616         0,
  24617         1,
  24618         soc_UNIMAC0_GMII_EEE_WAKE_TIMERr_fields,
  24619         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24620         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24621         -1,
  24622         -1,
  24623     },
  24624 #endif /* chips */
  24625 
  24626 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24627     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24628     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24629     defined(BCM_56260_B0)
  24630     { /* SOC_REG_INT_UNIMAC1_GMII_EEE_WAKE_TIMER_BCM53400_A0r */
  24631         soc_block_list[61],
  24632         soc_iprocreg,
  24633         1,
  24634         0,
  24635         0x1804a884,
  24636         0,
  24637         0,
  24638         1,
  24639         soc_GMII_EEE_WAKE_TIMER_BCM53400_A0r_fields,
  24640         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  24641         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24642         -1,
  24643         -1,
  24644     },
  24645 #endif /* chips */
  24646 
  24647 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24648     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24649     { /* SOC_REG_INT_UNIMAC1_IPG_HD_BKP_CNTLr */
  24650         soc_block_list[61],
  24651         soc_iprocreg,
  24652         1,
  24653         0,
  24654         0x18023804,
  24655         0,
  24656         0,
  24657         3,
  24658         soc_UNIMAC0_IPG_HD_BKP_CNTLr_fields,
  24659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24660         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  24661         -1,
  24662         -1,
  24663     },
  24664 #endif /* chips */
  24665 
  24666 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24667     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24668     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24669     defined(BCM_56260_B0)
  24670     { /* SOC_REG_INT_UNIMAC1_IPG_HD_BKP_CNTL_BCM53400_A0r */
  24671         soc_block_list[61],
  24672         soc_iprocreg,
  24673         1,
  24674         0,
  24675         0x1804a804,
  24676         0,
  24677         0,
  24678         3,
  24679         soc_IPG_HD_BKP_CNTL_BCM53400_A0r_fields,
  24680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24681         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  24682         -1,
  24683         -1,
  24684     },
  24685 #endif /* chips */
  24686 
  24687 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  24688     { /* SOC_REG_INT_UNIMAC1_MACSEC_CNTRLr */
  24689         soc_block_list[61],
  24690         soc_iprocreg,
  24691         1,
  24692         0,
  24693         0x1804ab14,
  24694         0,
  24695         0,
  24696         4,
  24697         soc_MACSEC_CNTRL_BCM53570_A0r_fields,
  24698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24699         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  24700         -1,
  24701         -1,
  24702     },
  24703 #endif /* chips */
  24704 
  24705 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24706     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24707     { /* SOC_REG_INT_UNIMAC1_MAC_0r */
  24708         soc_block_list[61],
  24709         soc_iprocreg,
  24710         1,
  24711         0,
  24712         0x1802380c,
  24713         0,
  24714         0,
  24715         1,
  24716         soc_UNIMAC0_MAC_0r_fields,
  24717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24718         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24719         -1,
  24720         -1,
  24721     },
  24722 #endif /* chips */
  24723 
  24724 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24725     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24726     { /* SOC_REG_INT_UNIMAC1_MAC_1r */
  24727         soc_block_list[61],
  24728         soc_iprocreg,
  24729         1,
  24730         0,
  24731         0x18023810,
  24732         0,
  24733         0,
  24734         1,
  24735         soc_UNIMAC0_MAC_1r_fields,
  24736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24737         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24738         -1,
  24739         -1,
  24740     },
  24741 #endif /* chips */
  24742 
  24743 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24744     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24745     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24746     defined(BCM_56260_B0)
  24747     { /* SOC_REG_INT_UNIMAC1_MAC_0_BCM53400_A0r */
  24748         soc_block_list[61],
  24749         soc_iprocreg,
  24750         1,
  24751         0,
  24752         0x1804a80c,
  24753         0,
  24754         0,
  24755         1,
  24756         soc_MAC_0_BCM53400_A0r_fields,
  24757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24758         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24759         -1,
  24760         -1,
  24761     },
  24762 #endif /* chips */
  24763 
  24764 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24765     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24766     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24767     defined(BCM_56260_B0)
  24768     { /* SOC_REG_INT_UNIMAC1_MAC_1_BCM53400_A0r */
  24769         soc_block_list[61],
  24770         soc_iprocreg,
  24771         1,
  24772         0,
  24773         0x1804a810,
  24774         0,
  24775         0,
  24776         1,
  24777         soc_MAC_1_BCM53400_A0r_fields,
  24778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24779         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24780         -1,
  24781         -1,
  24782     },
  24783 #endif /* chips */
  24784 
  24785 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24786     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24787     { /* SOC_REG_INT_UNIMAC1_MAC_MODEr */
  24788         soc_block_list[61],
  24789         soc_iprocreg,
  24790         1,
  24791         0,
  24792         0x18023844,
  24793         SOC_REG_FLAG_RO,
  24794         0,
  24795         5,
  24796         soc_UNIMAC0_MAC_MODEr_fields,
  24797         SOC_RESET_VAL_DEC(0x0000001a, 0x00000000)
  24798         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24799         -1,
  24800         -1,
  24801     },
  24802 #endif /* chips */
  24803 
  24804 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24805     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24806     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24807     defined(BCM_56260_B0)
  24808     { /* SOC_REG_INT_UNIMAC1_MAC_MODE_BCM53400_A0r */
  24809         soc_block_list[61],
  24810         soc_iprocreg,
  24811         1,
  24812         0,
  24813         0x1804a844,
  24814         SOC_REG_FLAG_RO,
  24815         0,
  24816         5,
  24817         soc_MAC_MODE_BCM53400_A0r_fields,
  24818         SOC_RESET_VAL_DEC(0x0000001a, 0x00000000)
  24819         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  24820         -1,
  24821         -1,
  24822     },
  24823 #endif /* chips */
  24824 
  24825 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24826     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24827     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_CTRLr */
  24828         soc_block_list[61],
  24829         soc_iprocreg,
  24830         1,
  24831         0,
  24832         0x18023b40,
  24833         0,
  24834         0,
  24835         5,
  24836         soc_UNIMAC0_MAC_PFC_CTRLr_fields,
  24837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24838         SOC_RESET_MASK_DEC(0x00000033, 0x00000000)
  24839         -1,
  24840         -1,
  24841     },
  24842 #endif /* chips */
  24843 
  24844 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  24845     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  24846     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_CTRL_BCM56160_A0r */
  24847         soc_block_list[61],
  24848         soc_iprocreg,
  24849         1,
  24850         0,
  24851         0x1804ab40,
  24852         0,
  24853         0,
  24854         5,
  24855         soc_UNIMAC0_MAC_PFC_CTRL_BCM56160_A0r_fields,
  24856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24857         SOC_RESET_MASK_DEC(0x00000033, 0x00000000)
  24858         -1,
  24859         -1,
  24860     },
  24861 #endif /* chips */
  24862 
  24863 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24864     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24865     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_DA_0r */
  24866         soc_block_list[61],
  24867         soc_iprocreg,
  24868         1,
  24869         0,
  24870         0x18023b08,
  24871         0,
  24872         0,
  24873         1,
  24874         soc_UNIMAC0_MAC_PFC_DA_0r_fields,
  24875         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  24876         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24877         -1,
  24878         -1,
  24879     },
  24880 #endif /* chips */
  24881 
  24882 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24883     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24884     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_DA_1r */
  24885         soc_block_list[61],
  24886         soc_iprocreg,
  24887         1,
  24888         0,
  24889         0x18023b0c,
  24890         0,
  24891         0,
  24892         1,
  24893         soc_UNIMAC0_MAC_PFC_DA_1r_fields,
  24894         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  24895         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24896         -1,
  24897         -1,
  24898     },
  24899 #endif /* chips */
  24900 
  24901 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  24902     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  24903     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_DA_0_BCM56160_A0r */
  24904         soc_block_list[61],
  24905         soc_iprocreg,
  24906         1,
  24907         0,
  24908         0x1804ab08,
  24909         0,
  24910         0,
  24911         1,
  24912         soc_MAC_PFC_DA_0_BCM56160_A0r_fields,
  24913         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
  24914         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24915         -1,
  24916         -1,
  24917     },
  24918 #endif /* chips */
  24919 
  24920 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  24921     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  24922     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_DA_1_BCM56160_A0r */
  24923         soc_block_list[61],
  24924         soc_iprocreg,
  24925         1,
  24926         0,
  24927         0x1804ab0c,
  24928         0,
  24929         0,
  24930         1,
  24931         soc_MAC_PFC_DA_1_BCM56160_A0r_fields,
  24932         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  24933         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24934         -1,
  24935         -1,
  24936     },
  24937 #endif /* chips */
  24938 
  24939 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24940     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24941     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_OPCODEr */
  24942         soc_block_list[61],
  24943         soc_iprocreg,
  24944         1,
  24945         0,
  24946         0x18023b04,
  24947         0,
  24948         0,
  24949         1,
  24950         soc_CMAC_PFC_OPCODEr_fields,
  24951         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  24952         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24953         -1,
  24954         -1,
  24955     },
  24956 #endif /* chips */
  24957 
  24958 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  24959     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  24960     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_OPCODE_BCM56160_A0r */
  24961         soc_block_list[61],
  24962         soc_iprocreg,
  24963         1,
  24964         0,
  24965         0x1804ab04,
  24966         0,
  24967         0,
  24968         1,
  24969         soc_CLMAC_PFC_OPCODEr_fields,
  24970         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  24971         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  24972         -1,
  24973         -1,
  24974     },
  24975 #endif /* chips */
  24976 
  24977 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  24978     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  24979     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_REFRESH_CTRLr */
  24980         soc_block_list[61],
  24981         soc_iprocreg,
  24982         1,
  24983         0,
  24984         0x18023b44,
  24985         0,
  24986         0,
  24987         2,
  24988         soc_UNIMAC0_MAC_PFC_REFRESH_CTRLr_fields,
  24989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24990         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  24991         -1,
  24992         -1,
  24993     },
  24994 #endif /* chips */
  24995 
  24996 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  24997     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  24998     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_REFRESH_CTRL_BCM56160_A0r */
  24999         soc_block_list[61],
  25000         soc_iprocreg,
  25001         1,
  25002         0,
  25003         0x1804ab44,
  25004         0,
  25005         0,
  25006         2,
  25007         soc_MAC_PFC_REFRESH_CTRL_BCM56160_A0r_fields,
  25008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25009         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25010         -1,
  25011         -1,
  25012     },
  25013 #endif /* chips */
  25014 
  25015 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25016     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25017     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_TYPEr */
  25018         soc_block_list[61],
  25019         soc_iprocreg,
  25020         1,
  25021         0,
  25022         0x18023b00,
  25023         0,
  25024         0,
  25025         1,
  25026         soc_CMAC_PFC_TYPEr_fields,
  25027         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  25028         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25029         -1,
  25030         -1,
  25031     },
  25032 #endif /* chips */
  25033 
  25034 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \
  25035     defined(BCM_53570_B0) || defined(BCM_56160_A0)
  25036     { /* SOC_REG_INT_UNIMAC1_MAC_PFC_TYPE_BCM56160_A0r */
  25037         soc_block_list[61],
  25038         soc_iprocreg,
  25039         1,
  25040         0,
  25041         0x1804ab00,
  25042         0,
  25043         0,
  25044         1,
  25045         soc_CLMAC_PFC_TYPEr_fields,
  25046         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
  25047         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25048         -1,
  25049         -1,
  25050     },
  25051 #endif /* chips */
  25052 
  25053 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25054     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25055     { /* SOC_REG_INT_UNIMAC1_MII_EEE_DELAY_ENTRY_TIMERr */
  25056         soc_block_list[61],
  25057         soc_iprocreg,
  25058         1,
  25059         0,
  25060         0x18023868,
  25061         0,
  25062         0,
  25063         1,
  25064         soc_UNIMAC0_MII_EEE_DELAY_ENTRY_TIMERr_fields,
  25065         SOC_RESET_VAL_DEC(0x00000022, 0x00000000)
  25066         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25067         -1,
  25068         -1,
  25069     },
  25070 #endif /* chips */
  25071 
  25072 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25073     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25074     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25075     defined(BCM_56260_B0)
  25076     { /* SOC_REG_INT_UNIMAC1_MII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r */
  25077         soc_block_list[61],
  25078         soc_iprocreg,
  25079         1,
  25080         0,
  25081         0x1804a868,
  25082         0,
  25083         0,
  25084         1,
  25085         soc_MII_EEE_DELAY_ENTRY_TIMER_BCM53400_A0r_fields,
  25086         SOC_RESET_VAL_DEC(0x00000022, 0x00000000)
  25087         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25088         -1,
  25089         -1,
  25090     },
  25091 #endif /* chips */
  25092 
  25093 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25094     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25095     { /* SOC_REG_INT_UNIMAC1_MII_EEE_WAKE_TIMERr */
  25096         soc_block_list[61],
  25097         soc_iprocreg,
  25098         1,
  25099         0,
  25100         0x18023880,
  25101         0,
  25102         0,
  25103         1,
  25104         soc_UNIMAC0_MII_EEE_WAKE_TIMERr_fields,
  25105         SOC_RESET_VAL_DEC(0x00000011, 0x00000000)
  25106         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25107         -1,
  25108         -1,
  25109     },
  25110 #endif /* chips */
  25111 
  25112 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25113     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25114     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25115     defined(BCM_56260_B0)
  25116     { /* SOC_REG_INT_UNIMAC1_MII_EEE_WAKE_TIMER_BCM53400_A0r */
  25117         soc_block_list[61],
  25118         soc_iprocreg,
  25119         1,
  25120         0,
  25121         0x1804a880,
  25122         0,
  25123         0,
  25124         1,
  25125         soc_MII_EEE_WAKE_TIMER_BCM53400_A0r_fields,
  25126         SOC_RESET_VAL_DEC(0x00000011, 0x00000000)
  25127         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25128         -1,
  25129         -1,
  25130     },
  25131 #endif /* chips */
  25132 
  25133 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25134     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25135     { /* SOC_REG_INT_UNIMAC1_PAUSE_CONTROLr */
  25136         soc_block_list[61],
  25137         soc_iprocreg,
  25138         1,
  25139         0,
  25140         0x18023b30,
  25141         0,
  25142         0,
  25143         2,
  25144         soc_UNIMAC0_PAUSE_CONTROLr_fields,
  25145         SOC_RESET_VAL_DEC(0x0002ffff, 0x00000000)
  25146         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  25147         -1,
  25148         -1,
  25149     },
  25150 #endif /* chips */
  25151 
  25152 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25153     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25154     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25155     defined(BCM_56260_B0)
  25156     { /* SOC_REG_INT_UNIMAC1_PAUSE_CONTROL_BCM53400_A0r */
  25157         soc_block_list[61],
  25158         soc_iprocreg,
  25159         1,
  25160         0,
  25161         0x1804ab30,
  25162         0,
  25163         0,
  25164         2,
  25165         soc_PAUSE_CONTROL_BCM53400_A0r_fields,
  25166         SOC_RESET_VAL_DEC(0x0002ffff, 0x00000000)
  25167         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  25168         -1,
  25169         -1,
  25170     },
  25171 #endif /* chips */
  25172 
  25173 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25174     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25175     { /* SOC_REG_INT_UNIMAC1_PAUSE_QUANTr */
  25176         soc_block_list[61],
  25177         soc_iprocreg,
  25178         1,
  25179         0,
  25180         0x18023818,
  25181         0,
  25182         0,
  25183         1,
  25184         soc_UNIMAC0_PAUSE_QUANTr_fields,
  25185         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  25186         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25187         -1,
  25188         -1,
  25189     },
  25190 #endif /* chips */
  25191 
  25192 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25193     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25194     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25195     defined(BCM_56260_B0)
  25196     { /* SOC_REG_INT_UNIMAC1_PAUSE_QUANT_BCM53400_A0r */
  25197         soc_block_list[61],
  25198         soc_iprocreg,
  25199         1,
  25200         0,
  25201         0x1804a818,
  25202         0,
  25203         0,
  25204         1,
  25205         soc_PAUSE_QUANT_BCM53400_A0r_fields,
  25206         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  25207         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25208         -1,
  25209         -1,
  25210     },
  25211 #endif /* chips */
  25212 
  25213 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25214     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25215     { /* SOC_REG_INT_UNIMAC1_PFC_XOFF_TIMERr */
  25216         soc_block_list[61],
  25217         soc_iprocreg,
  25218         1,
  25219         0,
  25220         0x18023860,
  25221         0,
  25222         0,
  25223         1,
  25224         soc_UNIMAC0_PFC_XOFF_TIMERr_fields,
  25225         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  25226         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25227         -1,
  25228         -1,
  25229     },
  25230 #endif /* chips */
  25231 
  25232 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25233     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25234     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25235     defined(BCM_56260_B0)
  25236     { /* SOC_REG_INT_UNIMAC1_PFC_XOFF_TIMER_BCM53400_A0r */
  25237         soc_block_list[61],
  25238         soc_iprocreg,
  25239         1,
  25240         0,
  25241         0x1804a860,
  25242         0,
  25243         0,
  25244         1,
  25245         soc_PFC_XOFF_TIMER_BCM53400_A0r_fields,
  25246         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  25247         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25248         -1,
  25249         -1,
  25250     },
  25251 #endif /* chips */
  25252 
  25253 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25254     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25255     { /* SOC_REG_INT_UNIMAC1_RXFIFO_STATr */
  25256         soc_block_list[61],
  25257         soc_iprocreg,
  25258         1,
  25259         0,
  25260         0x18023b38,
  25261         SOC_REG_FLAG_RO,
  25262         0,
  25263         2,
  25264         soc_UNIMAC0_RXFIFO_STATr_fields,
  25265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25266         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25267         -1,
  25268         -1,
  25269     },
  25270 #endif /* chips */
  25271 
  25272 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25273     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25274     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25275     defined(BCM_56260_B0)
  25276     { /* SOC_REG_INT_UNIMAC1_RXFIFO_STAT_BCM53400_A0r */
  25277         soc_block_list[61],
  25278         soc_iprocreg,
  25279         1,
  25280         0,
  25281         0x1804ab38,
  25282         SOC_REG_FLAG_RO,
  25283         0,
  25284         2,
  25285         soc_RXFIFO_STAT_BCM53400_A0r_fields,
  25286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25287         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25288         -1,
  25289         -1,
  25290     },
  25291 #endif /* chips */
  25292 
  25293 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25294     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25295     { /* SOC_REG_INT_UNIMAC1_RX_PAUSE_QUANTA_SCALEr */
  25296         soc_block_list[61],
  25297         soc_iprocreg,
  25298         1,
  25299         0,
  25300         0x18023850,
  25301         0,
  25302         0,
  25303         3,
  25304         soc_UNIMAC0_RX_PAUSE_QUANTA_SCALEr_fields,
  25305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25306         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  25307         -1,
  25308         -1,
  25309     },
  25310 #endif /* chips */
  25311 
  25312 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25313     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25314     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25315     defined(BCM_56260_B0)
  25316     { /* SOC_REG_INT_UNIMAC1_RX_PAUSE_QUANTA_SCALE_BCM53400_A0r */
  25317         soc_block_list[61],
  25318         soc_iprocreg,
  25319         1,
  25320         0,
  25321         0x1804a850,
  25322         0,
  25323         0,
  25324         3,
  25325         soc_RX_PAUSE_QUANTA_SCALE_BCM53400_A0r_fields,
  25326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25327         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  25328         -1,
  25329         -1,
  25330     },
  25331 #endif /* chips */
  25332 
  25333 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  25334     { /* SOC_REG_INT_UNIMAC1_SFD_OFFSETr */
  25335         soc_block_list[61],
  25336         soc_iprocreg,
  25337         1,
  25338         0,
  25339         0x1804a840,
  25340         0,
  25341         0,
  25342         1,
  25343         soc_SFD_OFFSET_BCM53570_A0r_fields,
  25344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25345         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25346         -1,
  25347         -1,
  25348     },
  25349 #endif /* chips */
  25350 
  25351 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25352     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25353     { /* SOC_REG_INT_UNIMAC1_TAG_0r */
  25354         soc_block_list[61],
  25355         soc_iprocreg,
  25356         1,
  25357         0,
  25358         0x18023848,
  25359         0,
  25360         0,
  25361         2,
  25362         soc_UNIMAC0_TAG_0r_fields,
  25363         SOC_RESET_VAL_DEC(0x00018100, 0x00000000)
  25364         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  25365         -1,
  25366         -1,
  25367     },
  25368 #endif /* chips */
  25369 
  25370 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25371     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25372     { /* SOC_REG_INT_UNIMAC1_TAG_1r */
  25373         soc_block_list[61],
  25374         soc_iprocreg,
  25375         1,
  25376         0,
  25377         0x1802384c,
  25378         0,
  25379         0,
  25380         2,
  25381         soc_UNIMAC0_TAG_1r_fields,
  25382         SOC_RESET_VAL_DEC(0x00018100, 0x00000000)
  25383         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  25384         -1,
  25385         -1,
  25386     },
  25387 #endif /* chips */
  25388 
  25389 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25390     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25391     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25392     defined(BCM_56260_B0)
  25393     { /* SOC_REG_INT_UNIMAC1_TAG_0_BCM53400_A0r */
  25394         soc_block_list[61],
  25395         soc_iprocreg,
  25396         1,
  25397         0,
  25398         0x1804a848,
  25399         0,
  25400         0,
  25401         2,
  25402         soc_TAG_0_BCM53400_A0r_fields,
  25403         SOC_RESET_VAL_DEC(0x00018100, 0x00000000)
  25404         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  25405         -1,
  25406         -1,
  25407     },
  25408 #endif /* chips */
  25409 
  25410 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25411     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25412     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25413     defined(BCM_56260_B0)
  25414     { /* SOC_REG_INT_UNIMAC1_TAG_1_BCM53400_A0r */
  25415         soc_block_list[61],
  25416         soc_iprocreg,
  25417         1,
  25418         0,
  25419         0x1804a84c,
  25420         0,
  25421         0,
  25422         2,
  25423         soc_TAG_1_BCM53400_A0r_fields,
  25424         SOC_RESET_VAL_DEC(0x00018100, 0x00000000)
  25425         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  25426         -1,
  25427         -1,
  25428     },
  25429 #endif /* chips */
  25430 
  25431 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25432     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25433     { /* SOC_REG_INT_UNIMAC1_TS_STATUS_CNTRLr */
  25434         soc_block_list[61],
  25435         soc_iprocreg,
  25436         1,
  25437         0,
  25438         0x18023b18,
  25439         SOC_REG_FLAG_RO,
  25440         0,
  25441         3,
  25442         soc_UNIMAC0_TS_STATUS_CNTRLr_fields,
  25443         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  25444         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  25445         -1,
  25446         -1,
  25447     },
  25448 #endif /* chips */
  25449 
  25450 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25451     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25452     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25453     defined(BCM_56260_B0)
  25454     { /* SOC_REG_INT_UNIMAC1_TS_STATUS_CNTRL_BCM53400_A0r */
  25455         soc_block_list[61],
  25456         soc_iprocreg,
  25457         1,
  25458         0,
  25459         0x1804ab18,
  25460         SOC_REG_FLAG_RO,
  25461         0,
  25462         3,
  25463         soc_TS_STATUS_CNTRL_BCM53400_A0r_fields,
  25464         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  25465         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  25466         -1,
  25467         -1,
  25468     },
  25469 #endif /* chips */
  25470 
  25471 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25472     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25473     { /* SOC_REG_INT_UNIMAC1_TXFIFO_STATr */
  25474         soc_block_list[61],
  25475         soc_iprocreg,
  25476         1,
  25477         0,
  25478         0x18023b3c,
  25479         SOC_REG_FLAG_RO,
  25480         0,
  25481         2,
  25482         soc_UNIMAC0_TXFIFO_STATr_fields,
  25483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25484         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25485         -1,
  25486         -1,
  25487     },
  25488 #endif /* chips */
  25489 
  25490 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25491     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25492     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25493     defined(BCM_56260_B0)
  25494     { /* SOC_REG_INT_UNIMAC1_TXFIFO_STAT_BCM53400_A0r */
  25495         soc_block_list[61],
  25496         soc_iprocreg,
  25497         1,
  25498         0,
  25499         0x1804ab3c,
  25500         SOC_REG_FLAG_RO,
  25501         0,
  25502         2,
  25503         soc_TXFIFO_STAT_BCM53400_A0r_fields,
  25504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25505         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25506         -1,
  25507         -1,
  25508     },
  25509 #endif /* chips */
  25510 
  25511 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25512     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25513     { /* SOC_REG_INT_UNIMAC1_TX_IPG_LENGTHr */
  25514         soc_block_list[61],
  25515         soc_iprocreg,
  25516         1,
  25517         0,
  25518         0x1802385c,
  25519         0,
  25520         0,
  25521         1,
  25522         soc_UNIMAC0_TX_IPG_LENGTHr_fields,
  25523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25524         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25525         -1,
  25526         -1,
  25527     },
  25528 #endif /* chips */
  25529 
  25530 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25531     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25532     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25533     defined(BCM_56260_B0)
  25534     { /* SOC_REG_INT_UNIMAC1_TX_IPG_LENGTH_BCM53400_A0r */
  25535         soc_block_list[61],
  25536         soc_iprocreg,
  25537         1,
  25538         0,
  25539         0x1804a85c,
  25540         0,
  25541         0,
  25542         1,
  25543         soc_TX_IPG_LENGTH_BCM53400_A0r_fields,
  25544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25545         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25546         -1,
  25547         -1,
  25548     },
  25549 #endif /* chips */
  25550 
  25551 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25552     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25553     { /* SOC_REG_INT_UNIMAC1_TX_PREAMBLEr */
  25554         soc_block_list[61],
  25555         soc_iprocreg,
  25556         1,
  25557         0,
  25558         0x18023854,
  25559         0,
  25560         0,
  25561         1,
  25562         soc_UNIMAC0_TX_PREAMBLEr_fields,
  25563         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  25564         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  25565         -1,
  25566         -1,
  25567     },
  25568 #endif /* chips */
  25569 
  25570 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25571     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25572     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25573     defined(BCM_56260_B0)
  25574     { /* SOC_REG_INT_UNIMAC1_TX_PREAMBLE_BCM53400_A0r */
  25575         soc_block_list[61],
  25576         soc_iprocreg,
  25577         1,
  25578         0,
  25579         0x1804a854,
  25580         0,
  25581         0,
  25582         1,
  25583         soc_TX_PREAMBLE_BCM53400_A0r_fields,
  25584         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  25585         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  25586         -1,
  25587         -1,
  25588     },
  25589 #endif /* chips */
  25590 
  25591 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25592     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25593     { /* SOC_REG_INT_UNIMAC1_TX_TS_DATAr */
  25594         soc_block_list[61],
  25595         soc_iprocreg,
  25596         1,
  25597         0,
  25598         0x18023b1c,
  25599         SOC_REG_FLAG_RO,
  25600         0,
  25601         1,
  25602         soc_UNIMAC0_TX_TS_DATAr_fields,
  25603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25604         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25605         -1,
  25606         -1,
  25607     },
  25608 #endif /* chips */
  25609 
  25610 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25611     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25612     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25613     defined(BCM_56260_B0)
  25614     { /* SOC_REG_INT_UNIMAC1_TX_TS_DATA_BCM53400_A0r */
  25615         soc_block_list[61],
  25616         soc_iprocreg,
  25617         1,
  25618         0,
  25619         0x1804ab1c,
  25620         SOC_REG_FLAG_RO,
  25621         0,
  25622         1,
  25623         soc_TX_TS_DATA_BCM53400_A0r_fields,
  25624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25625         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25626         -1,
  25627         -1,
  25628     },
  25629 #endif /* chips */
  25630 
  25631 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25632     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25633     { /* SOC_REG_INT_UNIMAC1_TX_TS_SEQ_IDr */
  25634         soc_block_list[61],
  25635         soc_iprocreg,
  25636         1,
  25637         0,
  25638         0x1802383c,
  25639         SOC_REG_FLAG_RO,
  25640         0,
  25641         2,
  25642         soc_UNIMAC0_TX_TS_SEQ_IDr_fields,
  25643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25644         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  25645         -1,
  25646         -1,
  25647     },
  25648 #endif /* chips */
  25649 
  25650 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25651     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25652     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25653     defined(BCM_56260_B0)
  25654     { /* SOC_REG_INT_UNIMAC1_TX_TS_SEQ_ID_BCM53400_A0r */
  25655         soc_block_list[61],
  25656         soc_iprocreg,
  25657         1,
  25658         0,
  25659         0x1804a83c,
  25660         SOC_REG_FLAG_RO,
  25661         0,
  25662         2,
  25663         soc_TX_TS_SEQ_ID_BCM53400_A0r_fields,
  25664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25665         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  25666         -1,
  25667         -1,
  25668     },
  25669 #endif /* chips */
  25670 
  25671 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25672     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25673     { /* SOC_REG_INT_UNIMAC1_UMAC_EEE_CTRLr */
  25674         soc_block_list[61],
  25675         soc_iprocreg,
  25676         1,
  25677         0,
  25678         0x18023864,
  25679         0,
  25680         0,
  25681         5,
  25682         soc_UNIMAC0_UMAC_EEE_CTRLr_fields,
  25683         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  25684         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  25685         -1,
  25686         -1,
  25687     },
  25688 #endif /* chips */
  25689 
  25690 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25691     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25692     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25693     defined(BCM_56260_B0)
  25694     { /* SOC_REG_INT_UNIMAC1_UMAC_EEE_CTRL_BCM53400_A0r */
  25695         soc_block_list[61],
  25696         soc_iprocreg,
  25697         1,
  25698         0,
  25699         0x1804a864,
  25700         0,
  25701         0,
  25702         5,
  25703         soc_UMAC_EEE_CTRL_BCM53400_A0r_fields,
  25704         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  25705         SOC_RESET_MASK_DEC(0x000000f8, 0x00000000)
  25706         -1,
  25707         -1,
  25708     },
  25709 #endif /* chips */
  25710 
  25711 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25712     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25713     { /* SOC_REG_INT_UNIMAC1_UMAC_EEE_REF_COUNTr */
  25714         soc_block_list[61],
  25715         soc_iprocreg,
  25716         1,
  25717         0,
  25718         0x18023870,
  25719         0,
  25720         0,
  25721         1,
  25722         soc_UNIMAC0_UMAC_EEE_REF_COUNTr_fields,
  25723         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  25724         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25725         -1,
  25726         -1,
  25727     },
  25728 #endif /* chips */
  25729 
  25730 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25731     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25732     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25733     defined(BCM_56260_B0)
  25734     { /* SOC_REG_INT_UNIMAC1_UMAC_EEE_REF_COUNT_BCM53400_A0r */
  25735         soc_block_list[61],
  25736         soc_iprocreg,
  25737         1,
  25738         0,
  25739         0x1804a870,
  25740         0,
  25741         0,
  25742         1,
  25743         soc_UMAC_EEE_REF_COUNT_BCM53400_A0r_fields,
  25744         SOC_RESET_VAL_DEC(0x0000007d, 0x00000000)
  25745         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25746         -1,
  25747         -1,
  25748     },
  25749 #endif /* chips */
  25750 
  25751 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25752     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25753     { /* SOC_REG_INT_UNIMAC1_UMAC_REV_IDr */
  25754         soc_block_list[61],
  25755         soc_iprocreg,
  25756         1,
  25757         0,
  25758         0x18023888,
  25759         SOC_REG_FLAG_RO,
  25760         0,
  25761         3,
  25762         soc_UNIMAC0_UMAC_REV_IDr_fields,
  25763         SOC_RESET_VAL_DEC(0x00030500, 0x00000000)
  25764         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  25765         -1,
  25766         -1,
  25767     },
  25768 #endif /* chips */
  25769 
  25770 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25771     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25772     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25773     defined(BCM_56260_B0)
  25774     { /* SOC_REG_INT_UNIMAC1_UMAC_REV_ID_BCM53400_A0r */
  25775         soc_block_list[61],
  25776         soc_iprocreg,
  25777         1,
  25778         0,
  25779         0x1804a888,
  25780         SOC_REG_FLAG_RO,
  25781         0,
  25782         3,
  25783         soc_UNIMAC0_UMAC_REV_ID_BCM53400_A0r_fields,
  25784         SOC_RESET_VAL_DEC(0x00030500, 0x00000000)
  25785         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  25786         -1,
  25787         -1,
  25788     },
  25789 #endif /* chips */
  25790 
  25791 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25792     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25793     { /* SOC_REG_INT_UNIMAC1_UMAC_RX_PKT_DROP_STATUSr */
  25794         soc_block_list[61],
  25795         soc_iprocreg,
  25796         1,
  25797         0,
  25798         0x18023878,
  25799         0,
  25800         0,
  25801         1,
  25802         soc_UNIMAC0_UMAC_RX_PKT_DROP_STATUSr_fields,
  25803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25804         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25805         -1,
  25806         -1,
  25807     },
  25808 #endif /* chips */
  25809 
  25810 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25811     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25812     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25813     defined(BCM_56260_B0)
  25814     { /* SOC_REG_INT_UNIMAC1_UMAC_RX_PKT_DROP_STATUS_BCM53400_A0r */
  25815         soc_block_list[61],
  25816         soc_iprocreg,
  25817         1,
  25818         0,
  25819         0x1804a878,
  25820         0,
  25821         0,
  25822         1,
  25823         soc_UMAC_RX_PKT_DROP_STATUS_BCM53400_A0r_fields,
  25824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25825         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25826         -1,
  25827         -1,
  25828     },
  25829 #endif /* chips */
  25830 
  25831 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  25832     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  25833     { /* SOC_REG_INT_UNIMAC1_UMAC_SYMMETRIC_IDLE_THRESHOLDr */
  25834         soc_block_list[61],
  25835         soc_iprocreg,
  25836         1,
  25837         0,
  25838         0x1802387c,
  25839         0,
  25840         0,
  25841         1,
  25842         soc_UNIMAC0_UMAC_SYMMETRIC_IDLE_THRESHOLDr_fields,
  25843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25844         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25845         -1,
  25846         -1,
  25847     },
  25848 #endif /* chips */
  25849 
  25850 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25851     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25852     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25853     defined(BCM_56260_B0)
  25854     { /* SOC_REG_INT_UNIMAC1_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53400_A0r */
  25855         soc_block_list[61],
  25856         soc_iprocreg,
  25857         1,
  25858         0,
  25859         0x1804a87c,
  25860         0,
  25861         0,
  25862         1,
  25863         soc_UMAC_SYMMETRIC_IDLE_THRESHOLD_BCM53400_A0r_fields,
  25864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25865         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  25866         -1,
  25867         -1,
  25868     },
  25869 #endif /* chips */
  25870 
  25871 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  25872     { /* SOC_REG_INT_UNIMAC_PFC_CTRLr */
  25873         soc_block_list[206],
  25874         soc_portreg,
  25875         1,
  25876         0,
  25877         0x2d0,
  25878         0,
  25879         0,
  25880         6,
  25881         soc_UNIMAC_PFC_CTRLr_fields,
  25882         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  25883         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25884         -1,
  25885         -1,
  25886     },
  25887 #endif /* chips */
  25888 
  25889 #if defined(BCM_56840_A0)
  25890     { /* SOC_REG_INT_UNIMAC_PFC_CTRL_BCM56840_A0r */
  25891         soc_block_list[16],
  25892         soc_portreg,
  25893         1,
  25894         0,
  25895         0x5d0,
  25896         0,
  25897         0,
  25898         5,
  25899         soc_UNIMAC_PFC_CTRL_BCM56840_A0r_fields,
  25900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25901         SOC_RESET_MASK_DEC(0x00000033, 0x00000000)
  25902         -1,
  25903         -1,
  25904     },
  25905 #endif /* chips */
  25906 
  25907 #if defined(BCM_56840_B0)
  25908     { /* SOC_REG_INT_UNIMAC_PFC_CTRL_BCM56840_B0r */
  25909         soc_block_list[16],
  25910         soc_portreg,
  25911         1,
  25912         0,
  25913         0x5d0,
  25914         0,
  25915         0,
  25916         5,
  25917         soc_UNIMAC_PFC_CTRL_BCM56840_A0r_fields,
  25918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25919         SOC_RESET_MASK_DEC(0x00000033, 0x00000000)
  25920         -1,
  25921         -1,
  25922     },
  25923 #endif /* chips */
  25924 
  25925 #if defined(BCM_56800_A0)
  25926     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAPr */
  25927         soc_block_list[5],
  25928         soc_portreg,
  25929         1,
  25930         0,
  25931         0x100000b,
  25932         0,
  25933         0,
  25934         1,
  25935         soc_TDBGC0_SELECTr_fields,
  25936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25937         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  25938         -1,
  25939         -1,
  25940     },
  25941 #endif /* chips */
  25942 
  25943 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  25944     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  25945     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  25946     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_64r */
  25947         soc_block_list[5],
  25948         soc_portreg,
  25949         1,
  25950         0,
  25951         0xe000064,
  25952         SOC_REG_FLAG_64_BITS,
  25953         0,
  25954         2,
  25955         soc_ICONTROL_OPCODE_BITMAP_64r_fields,
  25956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25957         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
  25958         -1,
  25959         -1,
  25960     },
  25961 #endif /* chips */
  25962 
  25963 #if defined(BCM_53400_A0)
  25964     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_BCM53400_A0r */
  25965         soc_block_list[5],
  25966         soc_portreg,
  25967         1,
  25968         0,
  25969         0x40001d00,
  25970         0,
  25971         0,
  25972         1,
  25973         soc_HG_TRUNK_FAILOVER_ENABLE_BCM53400_A0r_fields,
  25974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25975         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  25976         -1,
  25977         81,
  25978     },
  25979 #endif /* chips */
  25980 
  25981 #if defined(BCM_56142_A0)
  25982     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_BCM56142_A0r */
  25983         soc_block_list[5],
  25984         soc_portreg,
  25985         1,
  25986         0,
  25987         0x11000081,
  25988         0,
  25989         0,
  25990         1,
  25991         soc_ICONTROL_OPCODE_BITMAPr_fields,
  25992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25993         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  25994         -1,
  25995         31,
  25996     },
  25997 #endif /* chips */
  25998 
  25999 #if defined(BCM_56150_A0)
  26000     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_BCM56150_A0r */
  26001         soc_block_list[5],
  26002         soc_portreg,
  26003         1,
  26004         0,
  26005         0x44001d00,
  26006         0,
  26007         0,
  26008         1,
  26009         soc_ICONTROL_OPCODE_BITMAP_BCM56150_A0r_fields,
  26010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26011         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  26012         -1,
  26013         31,
  26014     },
  26015 #endif /* chips */
  26016 
  26017 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  26018     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_BCM56160_A0r */
  26019         soc_block_list[5],
  26020         soc_portreg,
  26021         1,
  26022         0,
  26023         0x40001d00,
  26024         0,
  26025         0,
  26026         1,
  26027         soc_CMIC_MIIM_PROTOCOL_MAP_0_BCM88950_A0r_fields,
  26028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26029         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26030         -1,
  26031         90,
  26032     },
  26033 #endif /* chips */
  26034 
  26035 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  26036     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_BCM56334_A0r */
  26037         soc_block_list[5],
  26038         soc_portreg,
  26039         1,
  26040         0,
  26041         0x11000064,
  26042         0,
  26043         0,
  26044         1,
  26045         soc_ICONTROL_OPCODE_BITMAPr_fields,
  26046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26047         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  26048         -1,
  26049         31,
  26050     },
  26051 #endif /* chips */
  26052 
  26053 #if defined(BCM_56514_A0)
  26054     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_BCM56514_A0r */
  26055         soc_block_list[6],
  26056         soc_portreg,
  26057         1,
  26058         0,
  26059         0xe000139,
  26060         0,
  26061         0,
  26062         1,
  26063         soc_ICONTROL_OPCODE_BITMAPr_fields,
  26064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26065         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  26066         -1,
  26067         -1,
  26068     },
  26069 #endif /* chips */
  26070 
  26071 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  26072     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  26073     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_BCM56624_A0r */
  26074         soc_block_list[5],
  26075         soc_portreg,
  26076         1,
  26077         0,
  26078         0x11000064,
  26079         0,
  26080         0,
  26081         1,
  26082         soc_ICONTROL_OPCODE_BITMAP_BCM56624_A0r_fields,
  26083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26084         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  26085         -1,
  26086         3,
  26087     },
  26088 #endif /* chips */
  26089 
  26090 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  26091     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_BCM56820_A0r */
  26092         soc_block_list[5],
  26093         soc_portreg,
  26094         1,
  26095         0,
  26096         0xf000064,
  26097         0,
  26098         0,
  26099         1,
  26100         soc_UNKNOWN_HGI_BITMAPr_fields,
  26101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26102         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  26103         -1,
  26104         -1,
  26105     },
  26106 #endif /* chips */
  26107 
  26108 #if defined(BCM_53570_A0)
  26109     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_HIr */
  26110         soc_block_list[5],
  26111         soc_portreg,
  26112         1,
  26113         0,
  26114         0x40004e00,
  26115         SOC_REG_FLAG_64_BITS,
  26116         0,
  26117         2,
  26118         soc_HG_TRUNK_FAILOVER_ENABLE_HIr_fields,
  26119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26120         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  26121         -1,
  26122         100,
  26123     },
  26124 #endif /* chips */
  26125 
  26126 #if defined(BCM_53570_B0)
  26127     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_HI_BCM53570_B0r */
  26128         soc_block_list[5],
  26129         soc_portreg,
  26130         1,
  26131         0,
  26132         0x40005200,
  26133         SOC_REG_FLAG_64_BITS,
  26134         0,
  26135         2,
  26136         soc_HG_TRUNK_FAILOVER_ENABLE_HIr_fields,
  26137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26138         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  26139         -1,
  26140         100,
  26141     },
  26142 #endif /* chips */
  26143 
  26144 #if defined(BCM_53570_A0)
  26145     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_LOr */
  26146         soc_block_list[5],
  26147         soc_portreg,
  26148         1,
  26149         0,
  26150         0x40004d00,
  26151         SOC_REG_FLAG_64_BITS,
  26152         0,
  26153         1,
  26154         soc_HG_TRUNK_FAILOVER_ENABLE_LOr_fields,
  26155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26156         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  26157         -1,
  26158         100,
  26159     },
  26160 #endif /* chips */
  26161 
  26162 #if defined(BCM_53570_B0)
  26163     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_LO_BCM53570_B0r */
  26164         soc_block_list[5],
  26165         soc_portreg,
  26166         1,
  26167         0,
  26168         0x40005100,
  26169         SOC_REG_FLAG_64_BITS,
  26170         0,
  26171         1,
  26172         soc_HG_TRUNK_FAILOVER_ENABLE_LOr_fields,
  26173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26174         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  26175         -1,
  26176         100,
  26177     },
  26178 #endif /* chips */
  26179 
  26180 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  26181     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  26182     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  26183     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_CONTROLr */
  26184         soc_block_list[5],
  26185         soc_genreg,
  26186         1,
  26187         0,
  26188         0xe0802a6,
  26189         0,
  26190         0,
  26191         1,
  26192         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  26193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26194         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26195         -1,
  26196         -1,
  26197     },
  26198 #endif /* chips */
  26199 
  26200 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  26201     defined(BCM_56270_A0)
  26202     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_CONTROL_BCM56260_A0r */
  26203         soc_block_list[5],
  26204         soc_genreg,
  26205         1,
  26206         0,
  26207         0x3e018200,
  26208         0,
  26209         0,
  26210         1,
  26211         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  26212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26213         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26214         -1,
  26215         -1,
  26216     },
  26217 #endif /* chips */
  26218 
  26219 #if defined(BCM_56270_A0)
  26220     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_CONTROL_BCM56270_A0r */
  26221         soc_block_list[5],
  26222         soc_genreg,
  26223         1,
  26224         0,
  26225         0x3e017200,
  26226         0,
  26227         0,
  26228         1,
  26229         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  26230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26231         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26232         -1,
  26233         -1,
  26234     },
  26235 #endif /* chips */
  26236 
  26237 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  26238     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_CONTROL_BCM56440_A0r */
  26239         soc_block_list[5],
  26240         soc_genreg,
  26241         1,
  26242         0,
  26243         0xf080d75,
  26244         0,
  26245         0,
  26246         1,
  26247         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  26248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26249         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26250         -1,
  26251         -1,
  26252     },
  26253 #endif /* chips */
  26254 
  26255 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  26256     defined(BCM_56450_B1)
  26257     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_CONTROL_BCM56450_A0r */
  26258         soc_block_list[5],
  26259         soc_genreg,
  26260         1,
  26261         0,
  26262         0x3e017800,
  26263         0,
  26264         0,
  26265         1,
  26266         soc_FT_CNTR_SER_CONTROLr_fields,
  26267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26268         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26269         -1,
  26270         -1,
  26271     },
  26272 #endif /* chips */
  26273 
  26274 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26275     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_CONTROL_BCM56840_A0r */
  26276         soc_block_list[5],
  26277         soc_genreg,
  26278         1,
  26279         0,
  26280         0xf080d76,
  26281         0,
  26282         0,
  26283         1,
  26284         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  26285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26286         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26287         -1,
  26288         -1,
  26289     },
  26290 #endif /* chips */
  26291 
  26292 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  26293     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  26294     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  26295     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_STATUS_INTRr */
  26296         soc_block_list[5],
  26297         soc_genreg,
  26298         1,
  26299         0,
  26300         0xe0802a7,
  26301         0,
  26302         0,
  26303         3,
  26304         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  26305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26306         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26307         -1,
  26308         -1,
  26309     },
  26310 #endif /* chips */
  26311 
  26312 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  26313     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_STATUS_INTR_BCM56440_A0r */
  26314         soc_block_list[5],
  26315         soc_genreg,
  26316         1,
  26317         0,
  26318         0xf080d76,
  26319         0,
  26320         0,
  26321         3,
  26322         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  26323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26324         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26325         -1,
  26326         -1,
  26327     },
  26328 #endif /* chips */
  26329 
  26330 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  26331     defined(BCM_56450_B1)
  26332     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r */
  26333         soc_block_list[5],
  26334         soc_genreg,
  26335         1,
  26336         0,
  26337         0x3e017900,
  26338         0,
  26339         0,
  26340         3,
  26341         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  26342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26343         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26344         -1,
  26345         -1,
  26346     },
  26347 #endif /* chips */
  26348 
  26349 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26350     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_STATUS_INTR_BCM56840_A0r */
  26351         soc_block_list[5],
  26352         soc_genreg,
  26353         1,
  26354         0,
  26355         0xf080d77,
  26356         0,
  26357         0,
  26358         3,
  26359         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  26360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26361         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26362         -1,
  26363         -1,
  26364     },
  26365 #endif /* chips */
  26366 
  26367 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  26368     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  26369     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  26370     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_STATUS_NACKr */
  26371         soc_block_list[5],
  26372         soc_genreg,
  26373         1,
  26374         0,
  26375         0xe0802a8,
  26376         0,
  26377         0,
  26378         3,
  26379         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  26380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26381         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26382         -1,
  26383         -1,
  26384     },
  26385 #endif /* chips */
  26386 
  26387 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  26388     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_STATUS_NACK_BCM56440_A0r */
  26389         soc_block_list[5],
  26390         soc_genreg,
  26391         1,
  26392         0,
  26393         0xf080d77,
  26394         0,
  26395         0,
  26396         3,
  26397         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  26398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26399         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26400         -1,
  26401         -1,
  26402     },
  26403 #endif /* chips */
  26404 
  26405 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  26406     defined(BCM_56450_B1)
  26407     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_STATUS_NACK_BCM56450_A0r */
  26408         soc_block_list[5],
  26409         soc_genreg,
  26410         1,
  26411         0,
  26412         0x3e017a00,
  26413         0,
  26414         0,
  26415         3,
  26416         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  26417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26418         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26419         -1,
  26420         -1,
  26421     },
  26422 #endif /* chips */
  26423 
  26424 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26425     { /* SOC_REG_INT_UNKNOWN_HGI_BITMAP_PARITY_STATUS_NACK_BCM56840_A0r */
  26426         soc_block_list[5],
  26427         soc_genreg,
  26428         1,
  26429         0,
  26430         0xf080d78,
  26431         0,
  26432         0,
  26433         3,
  26434         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  26435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26436         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26437         -1,
  26438         -1,
  26439     },
  26440 #endif /* chips */
  26441 
  26442 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  26443     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  26444     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASKr */
  26445         soc_block_list[5],
  26446         soc_portreg,
  26447         1,
  26448         0,
  26449         0xe000101,
  26450         0,
  26451         0,
  26452         1,
  26453         soc_BCAST_BLOCK_MASKr_fields,
  26454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26455         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  26456         -1,
  26457         -1,
  26458     },
  26459 #endif /* chips */
  26460 
  26461 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  26462     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  26463     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_64r */
  26464         soc_block_list[5],
  26465         soc_portreg,
  26466         1,
  26467         0,
  26468         0x11000041,
  26469         SOC_REG_FLAG_64_BITS,
  26470         0,
  26471         3,
  26472         soc_BCAST_BLOCK_MASK_64r_fields,
  26473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26474         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  26475         -1,
  26476         -1,
  26477     },
  26478 #endif /* chips */
  26479 
  26480 #if defined(BCM_53400_A0)
  26481     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_64_BCM53400_A0r */
  26482         soc_block_list[5],
  26483         soc_portreg,
  26484         1,
  26485         0,
  26486         0x40000200,
  26487         0,
  26488         0,
  26489         2,
  26490         soc_BCAST_BLOCK_MASK_64_BCM53400_A0r_fields,
  26491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26492         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26493         -1,
  26494         -1,
  26495     },
  26496 #endif /* chips */
  26497 
  26498 #if defined(BCM_56142_A0)
  26499     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_64_BCM56142_A0r */
  26500         soc_block_list[5],
  26501         soc_portreg,
  26502         1,
  26503         0,
  26504         0x11000061,
  26505         0,
  26506         0,
  26507         2,
  26508         soc_BCAST_BLOCK_MASK_64_BCM56334_A0r_fields,
  26509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26510         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  26511         -1,
  26512         -1,
  26513     },
  26514 #endif /* chips */
  26515 
  26516 #if defined(BCM_56150_A0)
  26517     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_64_BCM56150_A0r */
  26518         soc_block_list[5],
  26519         soc_portreg,
  26520         1,
  26521         0,
  26522         0x44000200,
  26523         0,
  26524         0,
  26525         2,
  26526         soc_BCAST_BLOCK_MASK_64_BCM56150_A0r_fields,
  26527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26528         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26529         -1,
  26530         -1,
  26531     },
  26532 #endif /* chips */
  26533 
  26534 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  26535     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_64_BCM56160_A0r */
  26536         soc_block_list[5],
  26537         soc_portreg,
  26538         1,
  26539         0,
  26540         0x40000200,
  26541         0,
  26542         0,
  26543         2,
  26544         soc_BCAST_BLOCK_MASK_64_BCM56160_A0r_fields,
  26545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26546         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26547         -1,
  26548         -1,
  26549     },
  26550 #endif /* chips */
  26551 
  26552 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  26553     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_64_BCM56334_A0r */
  26554         soc_block_list[5],
  26555         soc_portreg,
  26556         1,
  26557         0,
  26558         0x11000041,
  26559         0,
  26560         0,
  26561         2,
  26562         soc_BCAST_BLOCK_MASK_64_BCM56334_A0r_fields,
  26563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26564         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  26565         -1,
  26566         -1,
  26567     },
  26568 #endif /* chips */
  26569 
  26570 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  26571     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  26572     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  26573     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_64_BCM56634_A0r */
  26574         soc_block_list[5],
  26575         soc_portreg,
  26576         1,
  26577         0,
  26578         0xe000041,
  26579         SOC_REG_FLAG_64_BITS,
  26580         0,
  26581         4,
  26582         soc_BCAST_BLOCK_MASK_64_BCM56634_A0r_fields,
  26583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26584         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
  26585         -1,
  26586         -1,
  26587     },
  26588 #endif /* chips */
  26589 
  26590 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  26591     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_BCM53314_A0r */
  26592         soc_block_list[5],
  26593         soc_portreg,
  26594         1,
  26595         0,
  26596         0xf000102,
  26597         0,
  26598         0,
  26599         1,
  26600         soc_BCAST_BLOCK_MASK_BCM53314_A0r_fields,
  26601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26602         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  26603         -1,
  26604         -1,
  26605     },
  26606 #endif /* chips */
  26607 
  26608 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  26609     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_BCM56224_A0r */
  26610         soc_block_list[5],
  26611         soc_portreg,
  26612         1,
  26613         0,
  26614         0xf000102,
  26615         0,
  26616         0,
  26617         1,
  26618         soc_BCAST_BLOCK_MASK_BCM56224_A0r_fields,
  26619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26620         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  26621         -1,
  26622         -1,
  26623     },
  26624 #endif /* chips */
  26625 
  26626 #if defined(BCM_56800_A0)
  26627     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_BCM56800_A0r */
  26628         soc_block_list[5],
  26629         soc_portreg,
  26630         1,
  26631         0,
  26632         0xe000041,
  26633         0,
  26634         0,
  26635         1,
  26636         soc_BCAST_BLOCK_MASK_BCM56800_A0r_fields,
  26637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26638         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  26639         -1,
  26640         -1,
  26641     },
  26642 #endif /* chips */
  26643 
  26644 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  26645     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_BCM56820_A0r */
  26646         soc_block_list[5],
  26647         soc_portreg,
  26648         1,
  26649         0,
  26650         0xf000041,
  26651         0,
  26652         0,
  26653         1,
  26654         soc_BCAST_BLOCK_MASKr_fields,
  26655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26656         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  26657         -1,
  26658         -1,
  26659     },
  26660 #endif /* chips */
  26661 
  26662 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  26663     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_HIr */
  26664         soc_block_list[5],
  26665         soc_portreg,
  26666         1,
  26667         0,
  26668         0xf000103,
  26669         0,
  26670         0,
  26671         1,
  26672         soc_BCAST_BLOCK_MASK_HIr_fields,
  26673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26674         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26675         -1,
  26676         -1,
  26677     },
  26678 #endif /* chips */
  26679 
  26680 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  26681     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_HI_64r */
  26682         soc_block_list[5],
  26683         soc_portreg,
  26684         1,
  26685         0,
  26686         0x40002300,
  26687         SOC_REG_FLAG_64_BITS,
  26688         0,
  26689         5,
  26690         soc_BCAST_BLOCK_MASK_HI_64r_fields,
  26691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26692         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  26693         -1,
  26694         -1,
  26695     },
  26696 #endif /* chips */
  26697 
  26698 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  26699     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_HI_BCM53314_A0r */
  26700         soc_block_list[5],
  26701         soc_portreg,
  26702         1,
  26703         0,
  26704         0xf000103,
  26705         0,
  26706         0,
  26707         1,
  26708         soc_BCAST_BLOCK_MASK_HIr_fields,
  26709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26710         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26711         -1,
  26712         -1,
  26713     },
  26714 #endif /* chips */
  26715 
  26716 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
  26717     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_LO_64r */
  26718         soc_block_list[5],
  26719         soc_portreg,
  26720         1,
  26721         0,
  26722         0x40002200,
  26723         SOC_REG_FLAG_64_BITS,
  26724         0,
  26725         4,
  26726         soc_BCAST_BLOCK_MASK_LO_64r_fields,
  26727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26728         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  26729         -1,
  26730         -1,
  26731     },
  26732 #endif /* chips */
  26733 
  26734 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  26735     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  26736     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  26737     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROLr */
  26738         soc_block_list[5],
  26739         soc_genreg,
  26740         1,
  26741         0,
  26742         0xe08028b,
  26743         0,
  26744         0,
  26745         1,
  26746         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  26747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26748         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26749         -1,
  26750         -1,
  26751     },
  26752 #endif /* chips */
  26753 
  26754 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  26755     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL_BCM56260_A0r */
  26756         soc_block_list[5],
  26757         soc_genreg,
  26758         1,
  26759         0,
  26760         0x3e015b00,
  26761         0,
  26762         0,
  26763         1,
  26764         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  26765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26766         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26767         -1,
  26768         -1,
  26769     },
  26770 #endif /* chips */
  26771 
  26772 #if defined(BCM_56270_A0)
  26773     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL_BCM56270_A0r */
  26774         soc_block_list[5],
  26775         soc_genreg,
  26776         1,
  26777         0,
  26778         0x3e014b00,
  26779         0,
  26780         0,
  26781         1,
  26782         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  26783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26784         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26785         -1,
  26786         -1,
  26787     },
  26788 #endif /* chips */
  26789 
  26790 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  26791     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL_BCM56440_A0r */
  26792         soc_block_list[5],
  26793         soc_genreg,
  26794         1,
  26795         0,
  26796         0xf080d5a,
  26797         0,
  26798         0,
  26799         1,
  26800         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  26801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26802         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26803         -1,
  26804         -1,
  26805     },
  26806 #endif /* chips */
  26807 
  26808 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  26809     defined(BCM_56450_B1)
  26810     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL_BCM56450_A0r */
  26811         soc_block_list[5],
  26812         soc_genreg,
  26813         1,
  26814         0,
  26815         0x3e015a00,
  26816         0,
  26817         0,
  26818         1,
  26819         soc_FT_CNTR_SER_CONTROLr_fields,
  26820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26821         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26822         -1,
  26823         -1,
  26824     },
  26825 #endif /* chips */
  26826 
  26827 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26828     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL_BCM56840_A0r */
  26829         soc_block_list[5],
  26830         soc_genreg,
  26831         1,
  26832         0,
  26833         0xf080d5b,
  26834         0,
  26835         0,
  26836         1,
  26837         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  26838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26839         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26840         -1,
  26841         -1,
  26842     },
  26843 #endif /* chips */
  26844 
  26845 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  26846     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  26847     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  26848     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTRr */
  26849         soc_block_list[5],
  26850         soc_genreg,
  26851         1,
  26852         0,
  26853         0xe08028c,
  26854         0,
  26855         0,
  26856         3,
  26857         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  26858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26859         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26860         -1,
  26861         -1,
  26862     },
  26863 #endif /* chips */
  26864 
  26865 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  26866     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56440_A0r */
  26867         soc_block_list[5],
  26868         soc_genreg,
  26869         1,
  26870         0,
  26871         0xf080d5b,
  26872         0,
  26873         0,
  26874         3,
  26875         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  26876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26877         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26878         -1,
  26879         -1,
  26880     },
  26881 #endif /* chips */
  26882 
  26883 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  26884     defined(BCM_56450_B1)
  26885     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56450_A0r */
  26886         soc_block_list[5],
  26887         soc_genreg,
  26888         1,
  26889         0,
  26890         0x3e015b00,
  26891         0,
  26892         0,
  26893         3,
  26894         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  26895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26896         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26897         -1,
  26898         -1,
  26899     },
  26900 #endif /* chips */
  26901 
  26902 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26903     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r */
  26904         soc_block_list[5],
  26905         soc_genreg,
  26906         1,
  26907         0,
  26908         0xf080d5c,
  26909         0,
  26910         0,
  26911         3,
  26912         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  26913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26914         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26915         -1,
  26916         -1,
  26917     },
  26918 #endif /* chips */
  26919 
  26920 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  26921     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  26922     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  26923     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACKr */
  26924         soc_block_list[5],
  26925         soc_genreg,
  26926         1,
  26927         0,
  26928         0xe08028d,
  26929         0,
  26930         0,
  26931         3,
  26932         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  26933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26934         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26935         -1,
  26936         -1,
  26937     },
  26938 #endif /* chips */
  26939 
  26940 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  26941     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56440_A0r */
  26942         soc_block_list[5],
  26943         soc_genreg,
  26944         1,
  26945         0,
  26946         0xf080d5c,
  26947         0,
  26948         0,
  26949         3,
  26950         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  26951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26952         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26953         -1,
  26954         -1,
  26955     },
  26956 #endif /* chips */
  26957 
  26958 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  26959     defined(BCM_56450_B1)
  26960     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56450_A0r */
  26961         soc_block_list[5],
  26962         soc_genreg,
  26963         1,
  26964         0,
  26965         0x3e015c00,
  26966         0,
  26967         0,
  26968         3,
  26969         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  26970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26971         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26972         -1,
  26973         -1,
  26974     },
  26975 #endif /* chips */
  26976 
  26977 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  26978     { /* SOC_REG_INT_UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56840_A0r */
  26979         soc_block_list[5],
  26980         soc_genreg,
  26981         1,
  26982         0,
  26983         0xf080d5d,
  26984         0,
  26985         0,
  26986         3,
  26987         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  26988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26989         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  26990         -1,
  26991         -1,
  26992     },
  26993 #endif /* chips */
  26994 
  26995 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  26996     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  26997     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASKr */
  26998         soc_block_list[5],
  26999         soc_portreg,
  27000         1,
  27001         0,
  27002         0xe000100,
  27003         0,
  27004         0,
  27005         1,
  27006         soc_BCAST_BLOCK_MASKr_fields,
  27007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27008         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  27009         -1,
  27010         -1,
  27011     },
  27012 #endif /* chips */
  27013 
  27014 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
  27015     defined(BCM_56680_A0) || defined(BCM_56680_B0)
  27016     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_64r */
  27017         soc_block_list[5],
  27018         soc_portreg,
  27019         1,
  27020         0,
  27021         0x11000040,
  27022         SOC_REG_FLAG_64_BITS,
  27023         0,
  27024         3,
  27025         soc_BCAST_BLOCK_MASK_64r_fields,
  27026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27027         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  27028         -1,
  27029         -1,
  27030     },
  27031 #endif /* chips */
  27032 
  27033 #if defined(BCM_53400_A0)
  27034     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_64_BCM53400_A0r */
  27035         soc_block_list[5],
  27036         soc_portreg,
  27037         1,
  27038         0,
  27039         0x40000000,
  27040         0,
  27041         0,
  27042         2,
  27043         soc_BCAST_BLOCK_MASK_64_BCM53400_A0r_fields,
  27044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27045         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27046         -1,
  27047         -1,
  27048     },
  27049 #endif /* chips */
  27050 
  27051 #if defined(BCM_56142_A0)
  27052     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_64_BCM56142_A0r */
  27053         soc_block_list[5],
  27054         soc_portreg,
  27055         1,
  27056         0,
  27057         0x11000060,
  27058         0,
  27059         0,
  27060         2,
  27061         soc_BCAST_BLOCK_MASK_64_BCM56334_A0r_fields,
  27062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27063         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  27064         -1,
  27065         -1,
  27066     },
  27067 #endif /* chips */
  27068 
  27069 #if defined(BCM_56150_A0)
  27070     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_64_BCM56150_A0r */
  27071         soc_block_list[5],
  27072         soc_portreg,
  27073         1,
  27074         0,
  27075         0x44000000,
  27076         0,
  27077         0,
  27078         2,
  27079         soc_BCAST_BLOCK_MASK_64_BCM56150_A0r_fields,
  27080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27081         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27082         -1,
  27083         -1,
  27084     },
  27085 #endif /* chips */
  27086 
  27087 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  27088     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_64_BCM56160_A0r */
  27089         soc_block_list[5],
  27090         soc_portreg,
  27091         1,
  27092         0,
  27093         0x40000000,
  27094         0,
  27095         0,
  27096         2,
  27097         soc_BCAST_BLOCK_MASK_64_BCM56160_A0r_fields,
  27098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27099         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27100         -1,
  27101         -1,
  27102     },
  27103 #endif /* chips */
  27104 
  27105 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
  27106     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_64_BCM56334_A0r */
  27107         soc_block_list[5],
  27108         soc_portreg,
  27109         1,
  27110         0,
  27111         0x11000040,
  27112         0,
  27113         0,
  27114         2,
  27115         soc_BCAST_BLOCK_MASK_64_BCM56334_A0r_fields,
  27116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27117         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  27118         -1,
  27119         -1,
  27120     },
  27121 #endif /* chips */
  27122 
  27123 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  27124     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  27125     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  27126     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_64_BCM56634_A0r */
  27127         soc_block_list[5],
  27128         soc_portreg,
  27129         1,
  27130         0,
  27131         0xe000040,
  27132         SOC_REG_FLAG_64_BITS,
  27133         0,
  27134         4,
  27135         soc_BCAST_BLOCK_MASK_64_BCM56634_A0r_fields,
  27136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27137         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
  27138         -1,
  27139         -1,
  27140     },
  27141 #endif /* chips */
  27142 
  27143 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  27144     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_BCM53314_A0r */
  27145         soc_block_list[5],
  27146         soc_portreg,
  27147         1,
  27148         0,
  27149         0xf000100,
  27150         0,
  27151         0,
  27152         1,
  27153         soc_BCAST_BLOCK_MASK_BCM53314_A0r_fields,
  27154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27155         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  27156         -1,
  27157         -1,
  27158     },
  27159 #endif /* chips */
  27160 
  27161 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  27162     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_BCM56224_A0r */
  27163         soc_block_list[5],
  27164         soc_portreg,
  27165         1,
  27166         0,
  27167         0xf000100,
  27168         0,
  27169         0,
  27170         1,
  27171         soc_BCAST_BLOCK_MASK_BCM56224_A0r_fields,
  27172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27173         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  27174         -1,
  27175         -1,
  27176     },
  27177 #endif /* chips */
  27178 
  27179 #if defined(BCM_56800_A0)
  27180     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_BCM56800_A0r */
  27181         soc_block_list[5],
  27182         soc_portreg,
  27183         1,
  27184         0,
  27185         0xe000040,
  27186         0,
  27187         0,
  27188         1,
  27189         soc_BCAST_BLOCK_MASK_BCM56800_A0r_fields,
  27190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27191         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  27192         -1,
  27193         -1,
  27194     },
  27195 #endif /* chips */
  27196 
  27197 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
  27198     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_BCM56820_A0r */
  27199         soc_block_list[5],
  27200         soc_portreg,
  27201         1,
  27202         0,
  27203         0xf000040,
  27204         0,
  27205         0,
  27206         1,
  27207         soc_BCAST_BLOCK_MASKr_fields,
  27208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27209         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  27210         -1,
  27211         -1,
  27212     },
  27213 #endif /* chips */
  27214 
  27215 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
  27216     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_HIr */
  27217         soc_block_list[5],
  27218         soc_portreg,
  27219         1,
  27220         0,
  27221         0xf000101,
  27222         0,
  27223         0,
  27224         1,
  27225         soc_BCAST_BLOCK_MASK_HIr_fields,
  27226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27227         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27228         -1,
  27229         -1,
  27230     },
  27231 #endif /* chips */
  27232 
  27233 #if defined(BCM_53570_A0)
  27234     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_HI_64r */
  27235         soc_block_list[5],
  27236         soc_portreg,
  27237         1,
  27238         0,
  27239         0x40001f00,
  27240         SOC_REG_FLAG_64_BITS,
  27241         0,
  27242         5,
  27243         soc_BCAST_BLOCK_MASK_HI_64r_fields,
  27244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27245         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  27246         -1,
  27247         -1,
  27248     },
  27249 #endif /* chips */
  27250 
  27251 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
  27252     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_HI_BCM53314_A0r */
  27253         soc_block_list[5],
  27254         soc_portreg,
  27255         1,
  27256         0,
  27257         0xf000101,
  27258         0,
  27259         0,
  27260         1,
  27261         soc_BCAST_BLOCK_MASK_HIr_fields,
  27262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27264         -1,
  27265         -1,
  27266     },
  27267 #endif /* chips */
  27268 
  27269 #if defined(BCM_53570_A0)
  27270     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_LO_64r */
  27271         soc_block_list[5],
  27272         soc_portreg,
  27273         1,
  27274         0,
  27275         0x40001e00,
  27276         SOC_REG_FLAG_64_BITS,
  27277         0,
  27278         4,
  27279         soc_BCAST_BLOCK_MASK_LO_64r_fields,
  27280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27281         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  27282         -1,
  27283         -1,
  27284     },
  27285 #endif /* chips */
  27286 
  27287 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  27288     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  27289     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  27290     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROLr */
  27291         soc_block_list[5],
  27292         soc_genreg,
  27293         1,
  27294         0,
  27295         0xe080288,
  27296         0,
  27297         0,
  27298         1,
  27299         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
  27300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27301         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  27302         -1,
  27303         -1,
  27304     },
  27305 #endif /* chips */
  27306 
  27307 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  27308     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROL_BCM56260_A0r */
  27309         soc_block_list[5],
  27310         soc_genreg,
  27311         1,
  27312         0,
  27313         0x3e015800,
  27314         0,
  27315         0,
  27316         1,
  27317         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  27318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27319         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27320         -1,
  27321         -1,
  27322     },
  27323 #endif /* chips */
  27324 
  27325 #if defined(BCM_56270_A0)
  27326     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROL_BCM56270_A0r */
  27327         soc_block_list[5],
  27328         soc_genreg,
  27329         1,
  27330         0,
  27331         0x3e014800,
  27332         0,
  27333         0,
  27334         1,
  27335         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
  27336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27337         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27338         -1,
  27339         -1,
  27340     },
  27341 #endif /* chips */
  27342 
  27343 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  27344     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROL_BCM56440_A0r */
  27345         soc_block_list[5],
  27346         soc_genreg,
  27347         1,
  27348         0,
  27349         0xf080d57,
  27350         0,
  27351         0,
  27352         1,
  27353         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  27354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27355         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27356         -1,
  27357         -1,
  27358     },
  27359 #endif /* chips */
  27360 
  27361 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27362     defined(BCM_56450_B1)
  27363     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROL_BCM56450_A0r */
  27364         soc_block_list[5],
  27365         soc_genreg,
  27366         1,
  27367         0,
  27368         0x3e015700,
  27369         0,
  27370         0,
  27371         1,
  27372         soc_FT_CNTR_SER_CONTROLr_fields,
  27373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27374         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27375         -1,
  27376         -1,
  27377     },
  27378 #endif /* chips */
  27379 
  27380 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  27381     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROL_BCM56840_A0r */
  27382         soc_block_list[5],
  27383         soc_genreg,
  27384         1,
  27385         0,
  27386         0xf080d58,
  27387         0,
  27388         0,
  27389         1,
  27390         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
  27391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27392         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27393         -1,
  27394         -1,
  27395     },
  27396 #endif /* chips */
  27397 
  27398 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  27399     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  27400     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  27401     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_INTRr */
  27402         soc_block_list[5],
  27403         soc_genreg,
  27404         1,
  27405         0,
  27406         0xe080289,
  27407         0,
  27408         0,
  27409         3,
  27410         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  27411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27412         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27413         -1,
  27414         -1,
  27415     },
  27416 #endif /* chips */
  27417 
  27418 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  27419     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56440_A0r */
  27420         soc_block_list[5],
  27421         soc_genreg,
  27422         1,
  27423         0,
  27424         0xf080d58,
  27425         0,
  27426         0,
  27427         3,
  27428         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  27429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27430         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27431         -1,
  27432         -1,
  27433     },
  27434 #endif /* chips */
  27435 
  27436 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27437     defined(BCM_56450_B1)
  27438     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56450_A0r */
  27439         soc_block_list[5],
  27440         soc_genreg,
  27441         1,
  27442         0,
  27443         0x3e015800,
  27444         0,
  27445         0,
  27446         3,
  27447         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  27448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27449         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27450         -1,
  27451         -1,
  27452     },
  27453 #endif /* chips */
  27454 
  27455 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  27456     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r */
  27457         soc_block_list[5],
  27458         soc_genreg,
  27459         1,
  27460         0,
  27461         0xf080d59,
  27462         0,
  27463         0,
  27464         3,
  27465         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  27466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27467         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27468         -1,
  27469         -1,
  27470     },
  27471 #endif /* chips */
  27472 
  27473 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  27474     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  27475     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  27476     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_NACKr */
  27477         soc_block_list[5],
  27478         soc_genreg,
  27479         1,
  27480         0,
  27481         0xe08028a,
  27482         0,
  27483         0,
  27484         3,
  27485         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
  27486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27487         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27488         -1,
  27489         -1,
  27490     },
  27491 #endif /* chips */
  27492 
  27493 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  27494     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56440_A0r */
  27495         soc_block_list[5],
  27496         soc_genreg,
  27497         1,
  27498         0,
  27499         0xf080d59,
  27500         0,
  27501         0,
  27502         3,
  27503         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
  27504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27505         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27506         -1,
  27507         -1,
  27508     },
  27509 #endif /* chips */
  27510 
  27511 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27512     defined(BCM_56450_B1)
  27513     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56450_A0r */
  27514         soc_block_list[5],
  27515         soc_genreg,
  27516         1,
  27517         0,
  27518         0x3e015900,
  27519         0,
  27520         0,
  27521         3,
  27522         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
  27523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27524         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27525         -1,
  27526         -1,
  27527     },
  27528 #endif /* chips */
  27529 
  27530 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  27531     { /* SOC_REG_INT_UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56840_A0r */
  27532         soc_block_list[5],
  27533         soc_genreg,
  27534         1,
  27535         0,
  27536         0xf080d5a,
  27537         0,
  27538         0,
  27539         3,
  27540         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
  27541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27542         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  27543         -1,
  27544         -1,
  27545     },
  27546 #endif /* chips */
  27547 
  27548 #if defined(BCM_56860_A0)
  27549     { /* SOC_REG_INT_UPMEP_TX_SOBMH_HDR_0_64r */
  27550         soc_block_list[5],
  27551         soc_genreg,
  27552         1,
  27553         0,
  27554         0x76001600,
  27555         SOC_REG_FLAG_64_BITS |
  27556                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  27557         0,
  27558         1,
  27559         soc_UPMEP_TX_SOBMH_HDR_0_64r_fields,
  27560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27561         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  27562         -1,
  27563         -1,
  27564     },
  27565 #endif /* chips */
  27566 
  27567 #if defined(BCM_56860_A0)
  27568     { /* SOC_REG_INT_UPMEP_TX_SOBMH_HDR_1_64r */
  27569         soc_block_list[5],
  27570         soc_genreg,
  27571         1,
  27572         0,
  27573         0x76001700,
  27574         SOC_REG_FLAG_64_BITS |
  27575                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  27576         0,
  27577         1,
  27578         soc_UPMEP_TX_SOBMH_HDR_1_64r_fields,
  27579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27580         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  27581         -1,
  27582         -1,
  27583     },
  27584 #endif /* chips */
  27585 
  27586 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27587     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27588     { /* SOC_REG_INT_USB2D_DEVCONFIGr */
  27589         soc_block_list[61],
  27590         soc_iprocreg,
  27591         1,
  27592         0,
  27593         0x18042400,
  27594         0,
  27595         0,
  27596         17,
  27597         soc_USB2D_DEVCONFIGr_fields,
  27598         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  27599         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  27600         -1,
  27601         -1,
  27602     },
  27603 #endif /* chips */
  27604 
  27605 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27606     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  27607     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  27608     defined(BCM_56260_B0)
  27609     { /* SOC_REG_INT_USB2D_DEVCONFIG_BCM53400_A0r */
  27610         soc_block_list[61],
  27611         soc_iprocreg,
  27612         1,
  27613         0,
  27614         0x1804c400,
  27615         0,
  27616         0,
  27617         17,
  27618         soc_USB2D_DEVCONFIG_BCM53400_A0r_fields,
  27619         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  27620         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  27621         -1,
  27622         -1,
  27623     },
  27624 #endif /* chips */
  27625 
  27626 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27627     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27628     { /* SOC_REG_INT_USB2D_DEVCTRLr */
  27629         soc_block_list[61],
  27630         soc_iprocreg,
  27631         1,
  27632         0,
  27633         0x18042404,
  27634         0,
  27635         0,
  27636         16,
  27637         soc_USB2D_DEVCTRLr_fields,
  27638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27639         SOC_RESET_MASK_DEC(0xffff7ffd, 0x00000000)
  27640         -1,
  27641         -1,
  27642     },
  27643 #endif /* chips */
  27644 
  27645 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27646     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  27647     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  27648     defined(BCM_56260_B0)
  27649     { /* SOC_REG_INT_USB2D_DEVCTRL_BCM53400_A0r */
  27650         soc_block_list[61],
  27651         soc_iprocreg,
  27652         1,
  27653         0,
  27654         0x1804c404,
  27655         0,
  27656         0,
  27657         16,
  27658         soc_USB2D_DEVCTRL_BCM53400_A0r_fields,
  27659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27660         SOC_RESET_MASK_DEC(0xffff7ffd, 0x00000000)
  27661         -1,
  27662         -1,
  27663     },
  27664 #endif /* chips */
  27665 
  27666 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27667     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27668     { /* SOC_REG_INT_USB2D_DEVINTRr */
  27669         soc_block_list[61],
  27670         soc_iprocreg,
  27671         1,
  27672         0,
  27673         0x1804240c,
  27674         0,
  27675         0,
  27676         11,
  27677         soc_USB2D_DEVINTRr_fields,
  27678         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
  27679         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  27680         -1,
  27681         -1,
  27682     },
  27683 #endif /* chips */
  27684 
  27685 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27686     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27687     { /* SOC_REG_INT_USB2D_DEVINTRMASKr */
  27688         soc_block_list[61],
  27689         soc_iprocreg,
  27690         1,
  27691         0,
  27692         0x18042410,
  27693         0,
  27694         0,
  27695         4,
  27696         soc_USB2D_DEVINTRMASKr_fields,
  27697         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  27698         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  27699         -1,
  27700         -1,
  27701     },
  27702 #endif /* chips */
  27703 
  27704 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27705     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  27706     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  27707     defined(BCM_56260_B0)
  27708     { /* SOC_REG_INT_USB2D_DEVINTRMASK_BCM53400_A0r */
  27709         soc_block_list[61],
  27710         soc_iprocreg,
  27711         1,
  27712         0,
  27713         0x1804c410,
  27714         0,
  27715         0,
  27716         4,
  27717         soc_USB2D_DEVINTRMASK_BCM53400_A0r_fields,
  27718         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  27719         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  27720         -1,
  27721         -1,
  27722     },
  27723 #endif /* chips */
  27724 
  27725 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27726     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  27727     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  27728     defined(BCM_56260_B0)
  27729     { /* SOC_REG_INT_USB2D_DEVINTR_BCM53400_A0r */
  27730         soc_block_list[61],
  27731         soc_iprocreg,
  27732         1,
  27733         0,
  27734         0x1804c40c,
  27735         0,
  27736         0,
  27737         11,
  27738         soc_USB2D_DEVINTR_BCM53400_A0r_fields,
  27739         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
  27740         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  27741         -1,
  27742         -1,
  27743     },
  27744 #endif /* chips */
  27745 
  27746 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27747     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27748     { /* SOC_REG_INT_USB2D_DEVSTATUSr */
  27749         soc_block_list[61],
  27750         soc_iprocreg,
  27751         1,
  27752         0,
  27753         0x18042408,
  27754         SOC_REG_FLAG_RO,
  27755         0,
  27756         9,
  27757         soc_USB2D_DEVSTATUSr_fields,
  27758         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  27759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27760         -1,
  27761         -1,
  27762     },
  27763 #endif /* chips */
  27764 
  27765 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27766     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  27767     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  27768     defined(BCM_56260_B0)
  27769     { /* SOC_REG_INT_USB2D_DEVSTATUS_BCM53400_A0r */
  27770         soc_block_list[61],
  27771         soc_iprocreg,
  27772         1,
  27773         0,
  27774         0x1804c408,
  27775         SOC_REG_FLAG_RO,
  27776         0,
  27777         9,
  27778         soc_USB2D_DEVSTATUS_BCM53400_A0r_fields,
  27779         SOC_RESET_VAL_DEC(0x00008000, 0x00000000)
  27780         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27781         -1,
  27782         -1,
  27783     },
  27784 #endif /* chips */
  27785 
  27786 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27787     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27788     { /* SOC_REG_INT_USB2D_ENDPNTINTRr */
  27789         soc_block_list[61],
  27790         soc_iprocreg,
  27791         1,
  27792         0,
  27793         0x18042414,
  27794         0,
  27795         0,
  27796         2,
  27797         soc_USB2D_ENDPNTINTRr_fields,
  27798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27799         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27800         -1,
  27801         -1,
  27802     },
  27803 #endif /* chips */
  27804 
  27805 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27806     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27807     { /* SOC_REG_INT_USB2D_ENDPNTINTRMASKr */
  27808         soc_block_list[61],
  27809         soc_iprocreg,
  27810         1,
  27811         0,
  27812         0x18042418,
  27813         0,
  27814         0,
  27815         2,
  27816         soc_USB2D_ENDPNTINTRMASKr_fields,
  27817         SOC_RESET_VAL_DEC(0x03ff03ff, 0x00000000)
  27818         SOC_RESET_MASK_DEC(0x03ff03ff, 0x00000000)
  27819         -1,
  27820         -1,
  27821     },
  27822 #endif /* chips */
  27823 
  27824 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27825     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  27826     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  27827     defined(BCM_56260_B0)
  27828     { /* SOC_REG_INT_USB2D_ENDPNTINTRMASK_BCM53400_A0r */
  27829         soc_block_list[61],
  27830         soc_iprocreg,
  27831         1,
  27832         0,
  27833         0x1804c418,
  27834         0,
  27835         0,
  27836         2,
  27837         soc_USB2D_ENDPNTINTRMASK_BCM53400_A0r_fields,
  27838         SOC_RESET_VAL_DEC(0x03ff03ff, 0x00000000)
  27839         SOC_RESET_MASK_DEC(0x03ff03ff, 0x00000000)
  27840         -1,
  27841         -1,
  27842     },
  27843 #endif /* chips */
  27844 
  27845 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27846     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  27847     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  27848     defined(BCM_56260_B0)
  27849     { /* SOC_REG_INT_USB2D_ENDPNTINTR_BCM53400_A0r */
  27850         soc_block_list[61],
  27851         soc_iprocreg,
  27852         1,
  27853         0,
  27854         0x1804c414,
  27855         0,
  27856         0,
  27857         2,
  27858         soc_USB2D_ENDPNTINTR_BCM53400_A0r_fields,
  27859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27860         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27861         -1,
  27862         -1,
  27863     },
  27864 #endif /* chips */
  27865 
  27866 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27867     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27868     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_0r */
  27869         soc_block_list[61],
  27870         soc_iprocreg,
  27871         1,
  27872         0,
  27873         0x18042008,
  27874         0,
  27875         0,
  27876         2,
  27877         soc_USB2D_ENDPNT_IN_BUFFER_0r_fields,
  27878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27879         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27880         -1,
  27881         -1,
  27882     },
  27883 #endif /* chips */
  27884 
  27885 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27886     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27887     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_1r */
  27888         soc_block_list[61],
  27889         soc_iprocreg,
  27890         1,
  27891         0,
  27892         0x18042028,
  27893         0,
  27894         0,
  27895         2,
  27896         soc_USB2D_ENDPNT_IN_BUFFER_0r_fields,
  27897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27898         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27899         -1,
  27900         -1,
  27901     },
  27902 #endif /* chips */
  27903 
  27904 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27905     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27906     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_2r */
  27907         soc_block_list[61],
  27908         soc_iprocreg,
  27909         1,
  27910         0,
  27911         0x18042048,
  27912         0,
  27913         0,
  27914         2,
  27915         soc_USB2D_ENDPNT_IN_BUFFER_0r_fields,
  27916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27917         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27918         -1,
  27919         -1,
  27920     },
  27921 #endif /* chips */
  27922 
  27923 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27924     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27925     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_3r */
  27926         soc_block_list[61],
  27927         soc_iprocreg,
  27928         1,
  27929         0,
  27930         0x18042068,
  27931         0,
  27932         0,
  27933         2,
  27934         soc_USB2D_ENDPNT_IN_BUFFER_0r_fields,
  27935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27936         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27937         -1,
  27938         -1,
  27939     },
  27940 #endif /* chips */
  27941 
  27942 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27943     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27944     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_4r */
  27945         soc_block_list[61],
  27946         soc_iprocreg,
  27947         1,
  27948         0,
  27949         0x18042088,
  27950         0,
  27951         0,
  27952         2,
  27953         soc_USB2D_ENDPNT_IN_BUFFER_0r_fields,
  27954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27955         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27956         -1,
  27957         -1,
  27958     },
  27959 #endif /* chips */
  27960 
  27961 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27962     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27963     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_5r */
  27964         soc_block_list[61],
  27965         soc_iprocreg,
  27966         1,
  27967         0,
  27968         0x180420a8,
  27969         0,
  27970         0,
  27971         2,
  27972         soc_USB2D_ENDPNT_IN_BUFFER_0r_fields,
  27973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27974         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27975         -1,
  27976         -1,
  27977     },
  27978 #endif /* chips */
  27979 
  27980 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  27981     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  27982     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_6r */
  27983         soc_block_list[61],
  27984         soc_iprocreg,
  27985         1,
  27986         0,
  27987         0x180420c8,
  27988         0,
  27989         0,
  27990         2,
  27991         soc_USB2D_ENDPNT_IN_BUFFER_0r_fields,
  27992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27993         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  27994         -1,
  27995         -1,
  27996     },
  27997 #endif /* chips */
  27998 
  27999 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28000     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28001     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_7r */
  28002         soc_block_list[61],
  28003         soc_iprocreg,
  28004         1,
  28005         0,
  28006         0x180420e8,
  28007         0,
  28008         0,
  28009         2,
  28010         soc_USB2D_ENDPNT_IN_BUFFER_0r_fields,
  28011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28012         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28013         -1,
  28014         -1,
  28015     },
  28016 #endif /* chips */
  28017 
  28018 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28019     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28020     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_8r */
  28021         soc_block_list[61],
  28022         soc_iprocreg,
  28023         1,
  28024         0,
  28025         0x18042108,
  28026         0,
  28027         0,
  28028         2,
  28029         soc_USB2D_ENDPNT_IN_BUFFER_0r_fields,
  28030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28031         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28032         -1,
  28033         -1,
  28034     },
  28035 #endif /* chips */
  28036 
  28037 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28038     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28039     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_9r */
  28040         soc_block_list[61],
  28041         soc_iprocreg,
  28042         1,
  28043         0,
  28044         0x18042128,
  28045         0,
  28046         0,
  28047         2,
  28048         soc_USB2D_ENDPNT_IN_BUFFER_0r_fields,
  28049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28050         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28051         -1,
  28052         -1,
  28053     },
  28054 #endif /* chips */
  28055 
  28056 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28057     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28058     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28059     defined(BCM_56260_B0)
  28060     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r */
  28061         soc_block_list[61],
  28062         soc_iprocreg,
  28063         1,
  28064         0,
  28065         0x1804c008,
  28066         0,
  28067         0,
  28068         2,
  28069         soc_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r_fields,
  28070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28071         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28072         -1,
  28073         -1,
  28074     },
  28075 #endif /* chips */
  28076 
  28077 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28078     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28079     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28080     defined(BCM_56260_B0)
  28081     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_1_BCM53400_A0r */
  28082         soc_block_list[61],
  28083         soc_iprocreg,
  28084         1,
  28085         0,
  28086         0x1804c028,
  28087         0,
  28088         0,
  28089         2,
  28090         soc_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r_fields,
  28091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28092         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28093         -1,
  28094         -1,
  28095     },
  28096 #endif /* chips */
  28097 
  28098 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28099     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28100     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28101     defined(BCM_56260_B0)
  28102     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_2_BCM53400_A0r */
  28103         soc_block_list[61],
  28104         soc_iprocreg,
  28105         1,
  28106         0,
  28107         0x1804c048,
  28108         0,
  28109         0,
  28110         2,
  28111         soc_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r_fields,
  28112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28113         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28114         -1,
  28115         -1,
  28116     },
  28117 #endif /* chips */
  28118 
  28119 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28120     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28121     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28122     defined(BCM_56260_B0)
  28123     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_3_BCM53400_A0r */
  28124         soc_block_list[61],
  28125         soc_iprocreg,
  28126         1,
  28127         0,
  28128         0x1804c068,
  28129         0,
  28130         0,
  28131         2,
  28132         soc_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r_fields,
  28133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28134         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28135         -1,
  28136         -1,
  28137     },
  28138 #endif /* chips */
  28139 
  28140 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28141     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28142     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28143     defined(BCM_56260_B0)
  28144     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_4_BCM53400_A0r */
  28145         soc_block_list[61],
  28146         soc_iprocreg,
  28147         1,
  28148         0,
  28149         0x1804c088,
  28150         0,
  28151         0,
  28152         2,
  28153         soc_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r_fields,
  28154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28155         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28156         -1,
  28157         -1,
  28158     },
  28159 #endif /* chips */
  28160 
  28161 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28162     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28163     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28164     defined(BCM_56260_B0)
  28165     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_5_BCM53400_A0r */
  28166         soc_block_list[61],
  28167         soc_iprocreg,
  28168         1,
  28169         0,
  28170         0x1804c0a8,
  28171         0,
  28172         0,
  28173         2,
  28174         soc_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r_fields,
  28175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28176         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28177         -1,
  28178         -1,
  28179     },
  28180 #endif /* chips */
  28181 
  28182 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28183     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28184     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28185     defined(BCM_56260_B0)
  28186     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_6_BCM53400_A0r */
  28187         soc_block_list[61],
  28188         soc_iprocreg,
  28189         1,
  28190         0,
  28191         0x1804c0c8,
  28192         0,
  28193         0,
  28194         2,
  28195         soc_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r_fields,
  28196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28197         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28198         -1,
  28199         -1,
  28200     },
  28201 #endif /* chips */
  28202 
  28203 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28204     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28205     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28206     defined(BCM_56260_B0)
  28207     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_7_BCM53400_A0r */
  28208         soc_block_list[61],
  28209         soc_iprocreg,
  28210         1,
  28211         0,
  28212         0x1804c0e8,
  28213         0,
  28214         0,
  28215         2,
  28216         soc_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r_fields,
  28217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28218         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28219         -1,
  28220         -1,
  28221     },
  28222 #endif /* chips */
  28223 
  28224 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28225     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28226     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28227     defined(BCM_56260_B0)
  28228     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_8_BCM53400_A0r */
  28229         soc_block_list[61],
  28230         soc_iprocreg,
  28231         1,
  28232         0,
  28233         0x1804c108,
  28234         0,
  28235         0,
  28236         2,
  28237         soc_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r_fields,
  28238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28239         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28240         -1,
  28241         -1,
  28242     },
  28243 #endif /* chips */
  28244 
  28245 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28246     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28247     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28248     defined(BCM_56260_B0)
  28249     { /* SOC_REG_INT_USB2D_ENDPNT_IN_BUFFER_9_BCM53400_A0r */
  28250         soc_block_list[61],
  28251         soc_iprocreg,
  28252         1,
  28253         0,
  28254         0x1804c128,
  28255         0,
  28256         0,
  28257         2,
  28258         soc_USB2D_ENDPNT_IN_BUFFER_0_BCM53400_A0r_fields,
  28259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28260         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  28261         -1,
  28262         -1,
  28263     },
  28264 #endif /* chips */
  28265 
  28266 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28267     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28268     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_0r */
  28269         soc_block_list[61],
  28270         soc_iprocreg,
  28271         1,
  28272         0,
  28273         0x18042000,
  28274         0,
  28275         0,
  28276         12,
  28277         soc_USB2D_ENDPNT_IN_CTRL_0r_fields,
  28278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28279         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28280         -1,
  28281         -1,
  28282     },
  28283 #endif /* chips */
  28284 
  28285 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28286     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28287     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_1r */
  28288         soc_block_list[61],
  28289         soc_iprocreg,
  28290         1,
  28291         0,
  28292         0x18042020,
  28293         0,
  28294         0,
  28295         12,
  28296         soc_USB2D_ENDPNT_IN_CTRL_0r_fields,
  28297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28298         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28299         -1,
  28300         -1,
  28301     },
  28302 #endif /* chips */
  28303 
  28304 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28305     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28306     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_2r */
  28307         soc_block_list[61],
  28308         soc_iprocreg,
  28309         1,
  28310         0,
  28311         0x18042040,
  28312         0,
  28313         0,
  28314         12,
  28315         soc_USB2D_ENDPNT_IN_CTRL_0r_fields,
  28316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28317         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28318         -1,
  28319         -1,
  28320     },
  28321 #endif /* chips */
  28322 
  28323 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28324     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28325     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_3r */
  28326         soc_block_list[61],
  28327         soc_iprocreg,
  28328         1,
  28329         0,
  28330         0x18042060,
  28331         0,
  28332         0,
  28333         12,
  28334         soc_USB2D_ENDPNT_IN_CTRL_0r_fields,
  28335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28336         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28337         -1,
  28338         -1,
  28339     },
  28340 #endif /* chips */
  28341 
  28342 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28343     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28344     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_4r */
  28345         soc_block_list[61],
  28346         soc_iprocreg,
  28347         1,
  28348         0,
  28349         0x18042080,
  28350         0,
  28351         0,
  28352         12,
  28353         soc_USB2D_ENDPNT_IN_CTRL_0r_fields,
  28354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28355         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28356         -1,
  28357         -1,
  28358     },
  28359 #endif /* chips */
  28360 
  28361 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28362     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28363     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_5r */
  28364         soc_block_list[61],
  28365         soc_iprocreg,
  28366         1,
  28367         0,
  28368         0x180420a0,
  28369         0,
  28370         0,
  28371         12,
  28372         soc_USB2D_ENDPNT_IN_CTRL_0r_fields,
  28373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28374         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28375         -1,
  28376         -1,
  28377     },
  28378 #endif /* chips */
  28379 
  28380 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28381     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28382     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_6r */
  28383         soc_block_list[61],
  28384         soc_iprocreg,
  28385         1,
  28386         0,
  28387         0x180420c0,
  28388         0,
  28389         0,
  28390         12,
  28391         soc_USB2D_ENDPNT_IN_CTRL_0r_fields,
  28392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28393         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28394         -1,
  28395         -1,
  28396     },
  28397 #endif /* chips */
  28398 
  28399 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28400     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28401     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_7r */
  28402         soc_block_list[61],
  28403         soc_iprocreg,
  28404         1,
  28405         0,
  28406         0x180420e0,
  28407         0,
  28408         0,
  28409         12,
  28410         soc_USB2D_ENDPNT_IN_CTRL_0r_fields,
  28411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28412         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28413         -1,
  28414         -1,
  28415     },
  28416 #endif /* chips */
  28417 
  28418 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28419     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28420     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_8r */
  28421         soc_block_list[61],
  28422         soc_iprocreg,
  28423         1,
  28424         0,
  28425         0x18042100,
  28426         0,
  28427         0,
  28428         12,
  28429         soc_USB2D_ENDPNT_IN_CTRL_0r_fields,
  28430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28431         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28432         -1,
  28433         -1,
  28434     },
  28435 #endif /* chips */
  28436 
  28437 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28438     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28439     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_9r */
  28440         soc_block_list[61],
  28441         soc_iprocreg,
  28442         1,
  28443         0,
  28444         0x18042120,
  28445         0,
  28446         0,
  28447         12,
  28448         soc_USB2D_ENDPNT_IN_CTRL_0r_fields,
  28449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28450         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28451         -1,
  28452         -1,
  28453     },
  28454 #endif /* chips */
  28455 
  28456 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28457     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28458     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28459     defined(BCM_56260_B0)
  28460     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r */
  28461         soc_block_list[61],
  28462         soc_iprocreg,
  28463         1,
  28464         0,
  28465         0x1804c000,
  28466         0,
  28467         0,
  28468         12,
  28469         soc_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r_fields,
  28470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28471         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28472         -1,
  28473         -1,
  28474     },
  28475 #endif /* chips */
  28476 
  28477 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28478     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28479     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28480     defined(BCM_56260_B0)
  28481     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_1_BCM53400_A0r */
  28482         soc_block_list[61],
  28483         soc_iprocreg,
  28484         1,
  28485         0,
  28486         0x1804c020,
  28487         0,
  28488         0,
  28489         12,
  28490         soc_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r_fields,
  28491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28492         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28493         -1,
  28494         -1,
  28495     },
  28496 #endif /* chips */
  28497 
  28498 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28499     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28500     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28501     defined(BCM_56260_B0)
  28502     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_2_BCM53400_A0r */
  28503         soc_block_list[61],
  28504         soc_iprocreg,
  28505         1,
  28506         0,
  28507         0x1804c040,
  28508         0,
  28509         0,
  28510         12,
  28511         soc_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r_fields,
  28512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28513         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28514         -1,
  28515         -1,
  28516     },
  28517 #endif /* chips */
  28518 
  28519 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28520     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28521     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28522     defined(BCM_56260_B0)
  28523     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_3_BCM53400_A0r */
  28524         soc_block_list[61],
  28525         soc_iprocreg,
  28526         1,
  28527         0,
  28528         0x1804c060,
  28529         0,
  28530         0,
  28531         12,
  28532         soc_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r_fields,
  28533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28534         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28535         -1,
  28536         -1,
  28537     },
  28538 #endif /* chips */
  28539 
  28540 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28541     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28542     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28543     defined(BCM_56260_B0)
  28544     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_4_BCM53400_A0r */
  28545         soc_block_list[61],
  28546         soc_iprocreg,
  28547         1,
  28548         0,
  28549         0x1804c080,
  28550         0,
  28551         0,
  28552         12,
  28553         soc_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r_fields,
  28554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28555         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28556         -1,
  28557         -1,
  28558     },
  28559 #endif /* chips */
  28560 
  28561 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28562     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28563     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28564     defined(BCM_56260_B0)
  28565     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_5_BCM53400_A0r */
  28566         soc_block_list[61],
  28567         soc_iprocreg,
  28568         1,
  28569         0,
  28570         0x1804c0a0,
  28571         0,
  28572         0,
  28573         12,
  28574         soc_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r_fields,
  28575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28576         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28577         -1,
  28578         -1,
  28579     },
  28580 #endif /* chips */
  28581 
  28582 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28583     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28584     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28585     defined(BCM_56260_B0)
  28586     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_6_BCM53400_A0r */
  28587         soc_block_list[61],
  28588         soc_iprocreg,
  28589         1,
  28590         0,
  28591         0x1804c0c0,
  28592         0,
  28593         0,
  28594         12,
  28595         soc_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r_fields,
  28596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28597         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28598         -1,
  28599         -1,
  28600     },
  28601 #endif /* chips */
  28602 
  28603 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28604     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28605     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28606     defined(BCM_56260_B0)
  28607     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_7_BCM53400_A0r */
  28608         soc_block_list[61],
  28609         soc_iprocreg,
  28610         1,
  28611         0,
  28612         0x1804c0e0,
  28613         0,
  28614         0,
  28615         12,
  28616         soc_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r_fields,
  28617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28618         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28619         -1,
  28620         -1,
  28621     },
  28622 #endif /* chips */
  28623 
  28624 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28625     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28626     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28627     defined(BCM_56260_B0)
  28628     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_8_BCM53400_A0r */
  28629         soc_block_list[61],
  28630         soc_iprocreg,
  28631         1,
  28632         0,
  28633         0x1804c100,
  28634         0,
  28635         0,
  28636         12,
  28637         soc_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r_fields,
  28638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28639         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28640         -1,
  28641         -1,
  28642     },
  28643 #endif /* chips */
  28644 
  28645 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28646     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28647     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28648     defined(BCM_56260_B0)
  28649     { /* SOC_REG_INT_USB2D_ENDPNT_IN_CTRL_9_BCM53400_A0r */
  28650         soc_block_list[61],
  28651         soc_iprocreg,
  28652         1,
  28653         0,
  28654         0x1804c120,
  28655         0,
  28656         0,
  28657         12,
  28658         soc_USB2D_ENDPNT_IN_CTRL_0_BCM53400_A0r_fields,
  28659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28660         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  28661         -1,
  28662         -1,
  28663     },
  28664 #endif /* chips */
  28665 
  28666 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28667     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28668     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_0r */
  28669         soc_block_list[61],
  28670         soc_iprocreg,
  28671         1,
  28672         0,
  28673         0x18042014,
  28674         0,
  28675         0,
  28676         1,
  28677         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  28678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28680         -1,
  28681         -1,
  28682     },
  28683 #endif /* chips */
  28684 
  28685 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28686     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28687     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_1r */
  28688         soc_block_list[61],
  28689         soc_iprocreg,
  28690         1,
  28691         0,
  28692         0x18042034,
  28693         0,
  28694         0,
  28695         1,
  28696         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  28697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28698         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28699         -1,
  28700         -1,
  28701     },
  28702 #endif /* chips */
  28703 
  28704 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28705     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28706     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_2r */
  28707         soc_block_list[61],
  28708         soc_iprocreg,
  28709         1,
  28710         0,
  28711         0x18042054,
  28712         0,
  28713         0,
  28714         1,
  28715         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  28716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28718         -1,
  28719         -1,
  28720     },
  28721 #endif /* chips */
  28722 
  28723 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28724     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28725     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_3r */
  28726         soc_block_list[61],
  28727         soc_iprocreg,
  28728         1,
  28729         0,
  28730         0x18042074,
  28731         0,
  28732         0,
  28733         1,
  28734         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  28735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28736         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28737         -1,
  28738         -1,
  28739     },
  28740 #endif /* chips */
  28741 
  28742 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28743     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28744     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_4r */
  28745         soc_block_list[61],
  28746         soc_iprocreg,
  28747         1,
  28748         0,
  28749         0x18042094,
  28750         0,
  28751         0,
  28752         1,
  28753         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  28754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28755         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28756         -1,
  28757         -1,
  28758     },
  28759 #endif /* chips */
  28760 
  28761 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28762     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28763     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_5r */
  28764         soc_block_list[61],
  28765         soc_iprocreg,
  28766         1,
  28767         0,
  28768         0x180420b4,
  28769         0,
  28770         0,
  28771         1,
  28772         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  28773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28774         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28775         -1,
  28776         -1,
  28777     },
  28778 #endif /* chips */
  28779 
  28780 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28781     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28782     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_6r */
  28783         soc_block_list[61],
  28784         soc_iprocreg,
  28785         1,
  28786         0,
  28787         0x180420d4,
  28788         0,
  28789         0,
  28790         1,
  28791         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  28792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28793         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28794         -1,
  28795         -1,
  28796     },
  28797 #endif /* chips */
  28798 
  28799 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28800     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28801     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_7r */
  28802         soc_block_list[61],
  28803         soc_iprocreg,
  28804         1,
  28805         0,
  28806         0x180420f4,
  28807         0,
  28808         0,
  28809         1,
  28810         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  28811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28812         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28813         -1,
  28814         -1,
  28815     },
  28816 #endif /* chips */
  28817 
  28818 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28819     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28820     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_8r */
  28821         soc_block_list[61],
  28822         soc_iprocreg,
  28823         1,
  28824         0,
  28825         0x18042114,
  28826         0,
  28827         0,
  28828         1,
  28829         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  28830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28831         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28832         -1,
  28833         -1,
  28834     },
  28835 #endif /* chips */
  28836 
  28837 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  28838     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  28839     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_9r */
  28840         soc_block_list[61],
  28841         soc_iprocreg,
  28842         1,
  28843         0,
  28844         0x18042134,
  28845         0,
  28846         0,
  28847         1,
  28848         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  28849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28850         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28851         -1,
  28852         -1,
  28853     },
  28854 #endif /* chips */
  28855 
  28856 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28857     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28858     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28859     defined(BCM_56260_B0)
  28860     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r */
  28861         soc_block_list[61],
  28862         soc_iprocreg,
  28863         1,
  28864         0,
  28865         0x1804c014,
  28866         0,
  28867         0,
  28868         1,
  28869         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  28870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28871         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28872         -1,
  28873         -1,
  28874     },
  28875 #endif /* chips */
  28876 
  28877 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28878     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28879     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28880     defined(BCM_56260_B0)
  28881     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_1_BCM53400_A0r */
  28882         soc_block_list[61],
  28883         soc_iprocreg,
  28884         1,
  28885         0,
  28886         0x1804c034,
  28887         0,
  28888         0,
  28889         1,
  28890         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  28891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28893         -1,
  28894         -1,
  28895     },
  28896 #endif /* chips */
  28897 
  28898 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28899     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28900     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28901     defined(BCM_56260_B0)
  28902     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_2_BCM53400_A0r */
  28903         soc_block_list[61],
  28904         soc_iprocreg,
  28905         1,
  28906         0,
  28907         0x1804c054,
  28908         0,
  28909         0,
  28910         1,
  28911         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  28912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28913         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28914         -1,
  28915         -1,
  28916     },
  28917 #endif /* chips */
  28918 
  28919 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28920     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28921     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28922     defined(BCM_56260_B0)
  28923     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_3_BCM53400_A0r */
  28924         soc_block_list[61],
  28925         soc_iprocreg,
  28926         1,
  28927         0,
  28928         0x1804c074,
  28929         0,
  28930         0,
  28931         1,
  28932         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  28933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28934         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28935         -1,
  28936         -1,
  28937     },
  28938 #endif /* chips */
  28939 
  28940 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28941     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28942     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28943     defined(BCM_56260_B0)
  28944     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_4_BCM53400_A0r */
  28945         soc_block_list[61],
  28946         soc_iprocreg,
  28947         1,
  28948         0,
  28949         0x1804c094,
  28950         0,
  28951         0,
  28952         1,
  28953         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  28954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28956         -1,
  28957         -1,
  28958     },
  28959 #endif /* chips */
  28960 
  28961 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28962     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28963     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28964     defined(BCM_56260_B0)
  28965     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_5_BCM53400_A0r */
  28966         soc_block_list[61],
  28967         soc_iprocreg,
  28968         1,
  28969         0,
  28970         0x1804c0b4,
  28971         0,
  28972         0,
  28973         1,
  28974         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  28975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28976         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28977         -1,
  28978         -1,
  28979     },
  28980 #endif /* chips */
  28981 
  28982 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28983     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28984     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28985     defined(BCM_56260_B0)
  28986     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_6_BCM53400_A0r */
  28987         soc_block_list[61],
  28988         soc_iprocreg,
  28989         1,
  28990         0,
  28991         0x1804c0d4,
  28992         0,
  28993         0,
  28994         1,
  28995         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  28996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28997         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28998         -1,
  28999         -1,
  29000     },
  29001 #endif /* chips */
  29002 
  29003 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29004     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29005     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29006     defined(BCM_56260_B0)
  29007     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_7_BCM53400_A0r */
  29008         soc_block_list[61],
  29009         soc_iprocreg,
  29010         1,
  29011         0,
  29012         0x1804c0f4,
  29013         0,
  29014         0,
  29015         1,
  29016         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  29017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29018         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29019         -1,
  29020         -1,
  29021     },
  29022 #endif /* chips */
  29023 
  29024 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29025     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29026     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29027     defined(BCM_56260_B0)
  29028     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_8_BCM53400_A0r */
  29029         soc_block_list[61],
  29030         soc_iprocreg,
  29031         1,
  29032         0,
  29033         0x1804c114,
  29034         0,
  29035         0,
  29036         1,
  29037         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  29038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29039         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29040         -1,
  29041         -1,
  29042     },
  29043 #endif /* chips */
  29044 
  29045 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29046     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29047     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29048     defined(BCM_56260_B0)
  29049     { /* SOC_REG_INT_USB2D_ENDPNT_IN_DATADESCR_9_BCM53400_A0r */
  29050         soc_block_list[61],
  29051         soc_iprocreg,
  29052         1,
  29053         0,
  29054         0x1804c134,
  29055         0,
  29056         0,
  29057         1,
  29058         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  29059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29060         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29061         -1,
  29062         -1,
  29063     },
  29064 #endif /* chips */
  29065 
  29066 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29067     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29068     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_0r */
  29069         soc_block_list[61],
  29070         soc_iprocreg,
  29071         1,
  29072         0,
  29073         0x1804200c,
  29074         0,
  29075         0,
  29076         1,
  29077         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0r_fields,
  29078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29079         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29080         -1,
  29081         -1,
  29082     },
  29083 #endif /* chips */
  29084 
  29085 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29086     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29087     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_1r */
  29088         soc_block_list[61],
  29089         soc_iprocreg,
  29090         1,
  29091         0,
  29092         0x1804202c,
  29093         0,
  29094         0,
  29095         1,
  29096         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0r_fields,
  29097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29098         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29099         -1,
  29100         -1,
  29101     },
  29102 #endif /* chips */
  29103 
  29104 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29105     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29106     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_2r */
  29107         soc_block_list[61],
  29108         soc_iprocreg,
  29109         1,
  29110         0,
  29111         0x1804204c,
  29112         0,
  29113         0,
  29114         1,
  29115         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0r_fields,
  29116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29117         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29118         -1,
  29119         -1,
  29120     },
  29121 #endif /* chips */
  29122 
  29123 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29124     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29125     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_3r */
  29126         soc_block_list[61],
  29127         soc_iprocreg,
  29128         1,
  29129         0,
  29130         0x1804206c,
  29131         0,
  29132         0,
  29133         1,
  29134         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0r_fields,
  29135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29136         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29137         -1,
  29138         -1,
  29139     },
  29140 #endif /* chips */
  29141 
  29142 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29143     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29144     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_4r */
  29145         soc_block_list[61],
  29146         soc_iprocreg,
  29147         1,
  29148         0,
  29149         0x1804208c,
  29150         0,
  29151         0,
  29152         1,
  29153         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0r_fields,
  29154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29155         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29156         -1,
  29157         -1,
  29158     },
  29159 #endif /* chips */
  29160 
  29161 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29162     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29163     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_5r */
  29164         soc_block_list[61],
  29165         soc_iprocreg,
  29166         1,
  29167         0,
  29168         0x180420ac,
  29169         0,
  29170         0,
  29171         1,
  29172         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0r_fields,
  29173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29174         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29175         -1,
  29176         -1,
  29177     },
  29178 #endif /* chips */
  29179 
  29180 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29181     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29182     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_6r */
  29183         soc_block_list[61],
  29184         soc_iprocreg,
  29185         1,
  29186         0,
  29187         0x180420cc,
  29188         0,
  29189         0,
  29190         1,
  29191         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0r_fields,
  29192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29193         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29194         -1,
  29195         -1,
  29196     },
  29197 #endif /* chips */
  29198 
  29199 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29200     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29201     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_7r */
  29202         soc_block_list[61],
  29203         soc_iprocreg,
  29204         1,
  29205         0,
  29206         0x180420ec,
  29207         0,
  29208         0,
  29209         1,
  29210         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0r_fields,
  29211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29212         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29213         -1,
  29214         -1,
  29215     },
  29216 #endif /* chips */
  29217 
  29218 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29219     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29220     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_8r */
  29221         soc_block_list[61],
  29222         soc_iprocreg,
  29223         1,
  29224         0,
  29225         0x1804210c,
  29226         0,
  29227         0,
  29228         1,
  29229         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0r_fields,
  29230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29231         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29232         -1,
  29233         -1,
  29234     },
  29235 #endif /* chips */
  29236 
  29237 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29238     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29239     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_9r */
  29240         soc_block_list[61],
  29241         soc_iprocreg,
  29242         1,
  29243         0,
  29244         0x1804212c,
  29245         0,
  29246         0,
  29247         1,
  29248         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0r_fields,
  29249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29250         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29251         -1,
  29252         -1,
  29253     },
  29254 #endif /* chips */
  29255 
  29256 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29257     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29258     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29259     defined(BCM_56260_B0)
  29260     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r */
  29261         soc_block_list[61],
  29262         soc_iprocreg,
  29263         1,
  29264         0,
  29265         0x1804c00c,
  29266         0,
  29267         0,
  29268         1,
  29269         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r_fields,
  29270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29271         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29272         -1,
  29273         -1,
  29274     },
  29275 #endif /* chips */
  29276 
  29277 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29278     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29279     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29280     defined(BCM_56260_B0)
  29281     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_1_BCM53400_A0r */
  29282         soc_block_list[61],
  29283         soc_iprocreg,
  29284         1,
  29285         0,
  29286         0x1804c02c,
  29287         0,
  29288         0,
  29289         1,
  29290         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r_fields,
  29291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29292         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29293         -1,
  29294         -1,
  29295     },
  29296 #endif /* chips */
  29297 
  29298 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29299     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29300     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29301     defined(BCM_56260_B0)
  29302     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_2_BCM53400_A0r */
  29303         soc_block_list[61],
  29304         soc_iprocreg,
  29305         1,
  29306         0,
  29307         0x1804c04c,
  29308         0,
  29309         0,
  29310         1,
  29311         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r_fields,
  29312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29313         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29314         -1,
  29315         -1,
  29316     },
  29317 #endif /* chips */
  29318 
  29319 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29320     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29321     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29322     defined(BCM_56260_B0)
  29323     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_3_BCM53400_A0r */
  29324         soc_block_list[61],
  29325         soc_iprocreg,
  29326         1,
  29327         0,
  29328         0x1804c06c,
  29329         0,
  29330         0,
  29331         1,
  29332         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r_fields,
  29333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29334         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29335         -1,
  29336         -1,
  29337     },
  29338 #endif /* chips */
  29339 
  29340 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29341     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29342     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29343     defined(BCM_56260_B0)
  29344     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_4_BCM53400_A0r */
  29345         soc_block_list[61],
  29346         soc_iprocreg,
  29347         1,
  29348         0,
  29349         0x1804c08c,
  29350         0,
  29351         0,
  29352         1,
  29353         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r_fields,
  29354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29355         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29356         -1,
  29357         -1,
  29358     },
  29359 #endif /* chips */
  29360 
  29361 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29362     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29363     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29364     defined(BCM_56260_B0)
  29365     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_5_BCM53400_A0r */
  29366         soc_block_list[61],
  29367         soc_iprocreg,
  29368         1,
  29369         0,
  29370         0x1804c0ac,
  29371         0,
  29372         0,
  29373         1,
  29374         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r_fields,
  29375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29376         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29377         -1,
  29378         -1,
  29379     },
  29380 #endif /* chips */
  29381 
  29382 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29383     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29384     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29385     defined(BCM_56260_B0)
  29386     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_6_BCM53400_A0r */
  29387         soc_block_list[61],
  29388         soc_iprocreg,
  29389         1,
  29390         0,
  29391         0x1804c0cc,
  29392         0,
  29393         0,
  29394         1,
  29395         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r_fields,
  29396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29397         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29398         -1,
  29399         -1,
  29400     },
  29401 #endif /* chips */
  29402 
  29403 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29404     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29405     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29406     defined(BCM_56260_B0)
  29407     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_7_BCM53400_A0r */
  29408         soc_block_list[61],
  29409         soc_iprocreg,
  29410         1,
  29411         0,
  29412         0x1804c0ec,
  29413         0,
  29414         0,
  29415         1,
  29416         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r_fields,
  29417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29418         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29419         -1,
  29420         -1,
  29421     },
  29422 #endif /* chips */
  29423 
  29424 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29425     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29426     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29427     defined(BCM_56260_B0)
  29428     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_8_BCM53400_A0r */
  29429         soc_block_list[61],
  29430         soc_iprocreg,
  29431         1,
  29432         0,
  29433         0x1804c10c,
  29434         0,
  29435         0,
  29436         1,
  29437         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r_fields,
  29438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29439         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29440         -1,
  29441         -1,
  29442     },
  29443 #endif /* chips */
  29444 
  29445 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29446     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29447     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29448     defined(BCM_56260_B0)
  29449     { /* SOC_REG_INT_USB2D_ENDPNT_IN_MAXPACKSIZE_9_BCM53400_A0r */
  29450         soc_block_list[61],
  29451         soc_iprocreg,
  29452         1,
  29453         0,
  29454         0x1804c12c,
  29455         0,
  29456         0,
  29457         1,
  29458         soc_USB2D_ENDPNT_IN_MAXPACKSIZE_0_BCM53400_A0r_fields,
  29459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29460         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  29461         -1,
  29462         -1,
  29463     },
  29464 #endif /* chips */
  29465 
  29466 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29467     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29468     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_0r */
  29469         soc_block_list[61],
  29470         soc_iprocreg,
  29471         1,
  29472         0,
  29473         0x18042004,
  29474         0,
  29475         0,
  29476         13,
  29477         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  29478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29479         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29480         -1,
  29481         -1,
  29482     },
  29483 #endif /* chips */
  29484 
  29485 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29486     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29487     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_1r */
  29488         soc_block_list[61],
  29489         soc_iprocreg,
  29490         1,
  29491         0,
  29492         0x18042024,
  29493         0,
  29494         0,
  29495         13,
  29496         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  29497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29498         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29499         -1,
  29500         -1,
  29501     },
  29502 #endif /* chips */
  29503 
  29504 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29505     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29506     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_2r */
  29507         soc_block_list[61],
  29508         soc_iprocreg,
  29509         1,
  29510         0,
  29511         0x18042044,
  29512         0,
  29513         0,
  29514         13,
  29515         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  29516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29517         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29518         -1,
  29519         -1,
  29520     },
  29521 #endif /* chips */
  29522 
  29523 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29524     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29525     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_3r */
  29526         soc_block_list[61],
  29527         soc_iprocreg,
  29528         1,
  29529         0,
  29530         0x18042064,
  29531         0,
  29532         0,
  29533         13,
  29534         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  29535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29536         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29537         -1,
  29538         -1,
  29539     },
  29540 #endif /* chips */
  29541 
  29542 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29543     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29544     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_4r */
  29545         soc_block_list[61],
  29546         soc_iprocreg,
  29547         1,
  29548         0,
  29549         0x18042084,
  29550         0,
  29551         0,
  29552         13,
  29553         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  29554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29555         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29556         -1,
  29557         -1,
  29558     },
  29559 #endif /* chips */
  29560 
  29561 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29562     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29563     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_5r */
  29564         soc_block_list[61],
  29565         soc_iprocreg,
  29566         1,
  29567         0,
  29568         0x180420a4,
  29569         0,
  29570         0,
  29571         13,
  29572         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  29573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29574         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29575         -1,
  29576         -1,
  29577     },
  29578 #endif /* chips */
  29579 
  29580 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29581     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29582     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_6r */
  29583         soc_block_list[61],
  29584         soc_iprocreg,
  29585         1,
  29586         0,
  29587         0x180420c4,
  29588         0,
  29589         0,
  29590         13,
  29591         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  29592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29593         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29594         -1,
  29595         -1,
  29596     },
  29597 #endif /* chips */
  29598 
  29599 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29600     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29601     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_7r */
  29602         soc_block_list[61],
  29603         soc_iprocreg,
  29604         1,
  29605         0,
  29606         0x180420e4,
  29607         0,
  29608         0,
  29609         13,
  29610         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  29611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29612         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29613         -1,
  29614         -1,
  29615     },
  29616 #endif /* chips */
  29617 
  29618 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29619     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29620     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_8r */
  29621         soc_block_list[61],
  29622         soc_iprocreg,
  29623         1,
  29624         0,
  29625         0x18042104,
  29626         0,
  29627         0,
  29628         13,
  29629         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  29630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29631         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29632         -1,
  29633         -1,
  29634     },
  29635 #endif /* chips */
  29636 
  29637 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29638     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29639     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_9r */
  29640         soc_block_list[61],
  29641         soc_iprocreg,
  29642         1,
  29643         0,
  29644         0x18042124,
  29645         0,
  29646         0,
  29647         13,
  29648         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  29649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29650         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29651         -1,
  29652         -1,
  29653     },
  29654 #endif /* chips */
  29655 
  29656 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29657     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29658     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29659     defined(BCM_56260_B0)
  29660     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r */
  29661         soc_block_list[61],
  29662         soc_iprocreg,
  29663         1,
  29664         0,
  29665         0x1804c004,
  29666         0,
  29667         0,
  29668         13,
  29669         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  29670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29671         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29672         -1,
  29673         -1,
  29674     },
  29675 #endif /* chips */
  29676 
  29677 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29678     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29679     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29680     defined(BCM_56260_B0)
  29681     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_1_BCM53400_A0r */
  29682         soc_block_list[61],
  29683         soc_iprocreg,
  29684         1,
  29685         0,
  29686         0x1804c024,
  29687         0,
  29688         0,
  29689         13,
  29690         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  29691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29692         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29693         -1,
  29694         -1,
  29695     },
  29696 #endif /* chips */
  29697 
  29698 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29699     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29700     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29701     defined(BCM_56260_B0)
  29702     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_2_BCM53400_A0r */
  29703         soc_block_list[61],
  29704         soc_iprocreg,
  29705         1,
  29706         0,
  29707         0x1804c044,
  29708         0,
  29709         0,
  29710         13,
  29711         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  29712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29713         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29714         -1,
  29715         -1,
  29716     },
  29717 #endif /* chips */
  29718 
  29719 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29720     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29721     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29722     defined(BCM_56260_B0)
  29723     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_3_BCM53400_A0r */
  29724         soc_block_list[61],
  29725         soc_iprocreg,
  29726         1,
  29727         0,
  29728         0x1804c064,
  29729         0,
  29730         0,
  29731         13,
  29732         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  29733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29734         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29735         -1,
  29736         -1,
  29737     },
  29738 #endif /* chips */
  29739 
  29740 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29741     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29742     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29743     defined(BCM_56260_B0)
  29744     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_4_BCM53400_A0r */
  29745         soc_block_list[61],
  29746         soc_iprocreg,
  29747         1,
  29748         0,
  29749         0x1804c084,
  29750         0,
  29751         0,
  29752         13,
  29753         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  29754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29755         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29756         -1,
  29757         -1,
  29758     },
  29759 #endif /* chips */
  29760 
  29761 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29762     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29763     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29764     defined(BCM_56260_B0)
  29765     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_5_BCM53400_A0r */
  29766         soc_block_list[61],
  29767         soc_iprocreg,
  29768         1,
  29769         0,
  29770         0x1804c0a4,
  29771         0,
  29772         0,
  29773         13,
  29774         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  29775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29776         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29777         -1,
  29778         -1,
  29779     },
  29780 #endif /* chips */
  29781 
  29782 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29783     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29784     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29785     defined(BCM_56260_B0)
  29786     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_6_BCM53400_A0r */
  29787         soc_block_list[61],
  29788         soc_iprocreg,
  29789         1,
  29790         0,
  29791         0x1804c0c4,
  29792         0,
  29793         0,
  29794         13,
  29795         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  29796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29797         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29798         -1,
  29799         -1,
  29800     },
  29801 #endif /* chips */
  29802 
  29803 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29804     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29805     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29806     defined(BCM_56260_B0)
  29807     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_7_BCM53400_A0r */
  29808         soc_block_list[61],
  29809         soc_iprocreg,
  29810         1,
  29811         0,
  29812         0x1804c0e4,
  29813         0,
  29814         0,
  29815         13,
  29816         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  29817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29818         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29819         -1,
  29820         -1,
  29821     },
  29822 #endif /* chips */
  29823 
  29824 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29825     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29826     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29827     defined(BCM_56260_B0)
  29828     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_8_BCM53400_A0r */
  29829         soc_block_list[61],
  29830         soc_iprocreg,
  29831         1,
  29832         0,
  29833         0x1804c104,
  29834         0,
  29835         0,
  29836         13,
  29837         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  29838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29839         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29840         -1,
  29841         -1,
  29842     },
  29843 #endif /* chips */
  29844 
  29845 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29846     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29847     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29848     defined(BCM_56260_B0)
  29849     { /* SOC_REG_INT_USB2D_ENDPNT_IN_STATUS_9_BCM53400_A0r */
  29850         soc_block_list[61],
  29851         soc_iprocreg,
  29852         1,
  29853         0,
  29854         0x1804c124,
  29855         0,
  29856         0,
  29857         13,
  29858         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  29859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29860         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  29861         -1,
  29862         -1,
  29863     },
  29864 #endif /* chips */
  29865 
  29866 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29867     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29868     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_0r */
  29869         soc_block_list[61],
  29870         soc_iprocreg,
  29871         1,
  29872         0,
  29873         0x1804220c,
  29874         0,
  29875         0,
  29876         2,
  29877         soc_USB2D_ENDPNT_OUT_BUFSIZE_0r_fields,
  29878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29879         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29880         -1,
  29881         -1,
  29882     },
  29883 #endif /* chips */
  29884 
  29885 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29886     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29887     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_1r */
  29888         soc_block_list[61],
  29889         soc_iprocreg,
  29890         1,
  29891         0,
  29892         0x1804222c,
  29893         0,
  29894         0,
  29895         2,
  29896         soc_USB2D_ENDPNT_OUT_BUFSIZE_0r_fields,
  29897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29898         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29899         -1,
  29900         -1,
  29901     },
  29902 #endif /* chips */
  29903 
  29904 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29905     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29906     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_2r */
  29907         soc_block_list[61],
  29908         soc_iprocreg,
  29909         1,
  29910         0,
  29911         0x1804224c,
  29912         0,
  29913         0,
  29914         2,
  29915         soc_USB2D_ENDPNT_OUT_BUFSIZE_0r_fields,
  29916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29917         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29918         -1,
  29919         -1,
  29920     },
  29921 #endif /* chips */
  29922 
  29923 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29924     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29925     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_3r */
  29926         soc_block_list[61],
  29927         soc_iprocreg,
  29928         1,
  29929         0,
  29930         0x1804226c,
  29931         0,
  29932         0,
  29933         2,
  29934         soc_USB2D_ENDPNT_OUT_BUFSIZE_0r_fields,
  29935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29936         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29937         -1,
  29938         -1,
  29939     },
  29940 #endif /* chips */
  29941 
  29942 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29943     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29944     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_4r */
  29945         soc_block_list[61],
  29946         soc_iprocreg,
  29947         1,
  29948         0,
  29949         0x1804228c,
  29950         0,
  29951         0,
  29952         2,
  29953         soc_USB2D_ENDPNT_OUT_BUFSIZE_0r_fields,
  29954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29956         -1,
  29957         -1,
  29958     },
  29959 #endif /* chips */
  29960 
  29961 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29962     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29963     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_5r */
  29964         soc_block_list[61],
  29965         soc_iprocreg,
  29966         1,
  29967         0,
  29968         0x180422ac,
  29969         0,
  29970         0,
  29971         2,
  29972         soc_USB2D_ENDPNT_OUT_BUFSIZE_0r_fields,
  29973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29974         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29975         -1,
  29976         -1,
  29977     },
  29978 #endif /* chips */
  29979 
  29980 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  29981     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  29982     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_6r */
  29983         soc_block_list[61],
  29984         soc_iprocreg,
  29985         1,
  29986         0,
  29987         0x180422cc,
  29988         0,
  29989         0,
  29990         2,
  29991         soc_USB2D_ENDPNT_OUT_BUFSIZE_0r_fields,
  29992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29993         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29994         -1,
  29995         -1,
  29996     },
  29997 #endif /* chips */
  29998 
  29999 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30000     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30001     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_7r */
  30002         soc_block_list[61],
  30003         soc_iprocreg,
  30004         1,
  30005         0,
  30006         0x180422ec,
  30007         0,
  30008         0,
  30009         2,
  30010         soc_USB2D_ENDPNT_OUT_BUFSIZE_0r_fields,
  30011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30012         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30013         -1,
  30014         -1,
  30015     },
  30016 #endif /* chips */
  30017 
  30018 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30019     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30020     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_8r */
  30021         soc_block_list[61],
  30022         soc_iprocreg,
  30023         1,
  30024         0,
  30025         0x1804230c,
  30026         0,
  30027         0,
  30028         2,
  30029         soc_USB2D_ENDPNT_OUT_BUFSIZE_0r_fields,
  30030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30031         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30032         -1,
  30033         -1,
  30034     },
  30035 #endif /* chips */
  30036 
  30037 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30038     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30039     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_9r */
  30040         soc_block_list[61],
  30041         soc_iprocreg,
  30042         1,
  30043         0,
  30044         0x1804232c,
  30045         0,
  30046         0,
  30047         2,
  30048         soc_USB2D_ENDPNT_OUT_BUFSIZE_0r_fields,
  30049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30050         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30051         -1,
  30052         -1,
  30053     },
  30054 #endif /* chips */
  30055 
  30056 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30057     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30058     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30059     defined(BCM_56260_B0)
  30060     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r */
  30061         soc_block_list[61],
  30062         soc_iprocreg,
  30063         1,
  30064         0,
  30065         0x1804c20c,
  30066         0,
  30067         0,
  30068         2,
  30069         soc_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r_fields,
  30070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30071         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30072         -1,
  30073         -1,
  30074     },
  30075 #endif /* chips */
  30076 
  30077 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30078     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30079     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30080     defined(BCM_56260_B0)
  30081     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_1_BCM53400_A0r */
  30082         soc_block_list[61],
  30083         soc_iprocreg,
  30084         1,
  30085         0,
  30086         0x1804c22c,
  30087         0,
  30088         0,
  30089         2,
  30090         soc_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r_fields,
  30091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30092         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30093         -1,
  30094         -1,
  30095     },
  30096 #endif /* chips */
  30097 
  30098 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30099     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30100     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30101     defined(BCM_56260_B0)
  30102     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_2_BCM53400_A0r */
  30103         soc_block_list[61],
  30104         soc_iprocreg,
  30105         1,
  30106         0,
  30107         0x1804c24c,
  30108         0,
  30109         0,
  30110         2,
  30111         soc_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r_fields,
  30112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30113         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30114         -1,
  30115         -1,
  30116     },
  30117 #endif /* chips */
  30118 
  30119 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30120     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30121     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30122     defined(BCM_56260_B0)
  30123     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_3_BCM53400_A0r */
  30124         soc_block_list[61],
  30125         soc_iprocreg,
  30126         1,
  30127         0,
  30128         0x1804c26c,
  30129         0,
  30130         0,
  30131         2,
  30132         soc_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r_fields,
  30133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30134         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30135         -1,
  30136         -1,
  30137     },
  30138 #endif /* chips */
  30139 
  30140 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30141     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30142     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30143     defined(BCM_56260_B0)
  30144     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_4_BCM53400_A0r */
  30145         soc_block_list[61],
  30146         soc_iprocreg,
  30147         1,
  30148         0,
  30149         0x1804c28c,
  30150         0,
  30151         0,
  30152         2,
  30153         soc_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r_fields,
  30154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30156         -1,
  30157         -1,
  30158     },
  30159 #endif /* chips */
  30160 
  30161 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30162     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30163     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30164     defined(BCM_56260_B0)
  30165     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_5_BCM53400_A0r */
  30166         soc_block_list[61],
  30167         soc_iprocreg,
  30168         1,
  30169         0,
  30170         0x1804c2ac,
  30171         0,
  30172         0,
  30173         2,
  30174         soc_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r_fields,
  30175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30176         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30177         -1,
  30178         -1,
  30179     },
  30180 #endif /* chips */
  30181 
  30182 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30183     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30184     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30185     defined(BCM_56260_B0)
  30186     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_6_BCM53400_A0r */
  30187         soc_block_list[61],
  30188         soc_iprocreg,
  30189         1,
  30190         0,
  30191         0x1804c2cc,
  30192         0,
  30193         0,
  30194         2,
  30195         soc_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r_fields,
  30196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30197         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30198         -1,
  30199         -1,
  30200     },
  30201 #endif /* chips */
  30202 
  30203 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30204     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30205     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30206     defined(BCM_56260_B0)
  30207     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_7_BCM53400_A0r */
  30208         soc_block_list[61],
  30209         soc_iprocreg,
  30210         1,
  30211         0,
  30212         0x1804c2ec,
  30213         0,
  30214         0,
  30215         2,
  30216         soc_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r_fields,
  30217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30218         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30219         -1,
  30220         -1,
  30221     },
  30222 #endif /* chips */
  30223 
  30224 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30225     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30226     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30227     defined(BCM_56260_B0)
  30228     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_8_BCM53400_A0r */
  30229         soc_block_list[61],
  30230         soc_iprocreg,
  30231         1,
  30232         0,
  30233         0x1804c30c,
  30234         0,
  30235         0,
  30236         2,
  30237         soc_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r_fields,
  30238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30239         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30240         -1,
  30241         -1,
  30242     },
  30243 #endif /* chips */
  30244 
  30245 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30246     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30247     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30248     defined(BCM_56260_B0)
  30249     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_BUFSIZE_9_BCM53400_A0r */
  30250         soc_block_list[61],
  30251         soc_iprocreg,
  30252         1,
  30253         0,
  30254         0x1804c32c,
  30255         0,
  30256         0,
  30257         2,
  30258         soc_USB2D_ENDPNT_OUT_BUFSIZE_0_BCM53400_A0r_fields,
  30259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30260         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30261         -1,
  30262         -1,
  30263     },
  30264 #endif /* chips */
  30265 
  30266 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30267     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30268     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_0r */
  30269         soc_block_list[61],
  30270         soc_iprocreg,
  30271         1,
  30272         0,
  30273         0x18042200,
  30274         0,
  30275         0,
  30276         12,
  30277         soc_USB2D_ENDPNT_OUT_CTRL_0r_fields,
  30278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30279         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30280         -1,
  30281         -1,
  30282     },
  30283 #endif /* chips */
  30284 
  30285 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30286     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30287     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_1r */
  30288         soc_block_list[61],
  30289         soc_iprocreg,
  30290         1,
  30291         0,
  30292         0x18042220,
  30293         0,
  30294         0,
  30295         12,
  30296         soc_USB2D_ENDPNT_OUT_CTRL_0r_fields,
  30297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30298         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30299         -1,
  30300         -1,
  30301     },
  30302 #endif /* chips */
  30303 
  30304 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30305     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30306     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_2r */
  30307         soc_block_list[61],
  30308         soc_iprocreg,
  30309         1,
  30310         0,
  30311         0x18042240,
  30312         0,
  30313         0,
  30314         12,
  30315         soc_USB2D_ENDPNT_OUT_CTRL_0r_fields,
  30316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30317         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30318         -1,
  30319         -1,
  30320     },
  30321 #endif /* chips */
  30322 
  30323 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30324     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30325     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_3r */
  30326         soc_block_list[61],
  30327         soc_iprocreg,
  30328         1,
  30329         0,
  30330         0x18042260,
  30331         0,
  30332         0,
  30333         12,
  30334         soc_USB2D_ENDPNT_OUT_CTRL_0r_fields,
  30335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30336         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30337         -1,
  30338         -1,
  30339     },
  30340 #endif /* chips */
  30341 
  30342 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30343     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30344     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_4r */
  30345         soc_block_list[61],
  30346         soc_iprocreg,
  30347         1,
  30348         0,
  30349         0x18042280,
  30350         0,
  30351         0,
  30352         12,
  30353         soc_USB2D_ENDPNT_OUT_CTRL_0r_fields,
  30354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30355         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30356         -1,
  30357         -1,
  30358     },
  30359 #endif /* chips */
  30360 
  30361 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30362     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30363     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_5r */
  30364         soc_block_list[61],
  30365         soc_iprocreg,
  30366         1,
  30367         0,
  30368         0x180422a0,
  30369         0,
  30370         0,
  30371         12,
  30372         soc_USB2D_ENDPNT_OUT_CTRL_0r_fields,
  30373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30374         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30375         -1,
  30376         -1,
  30377     },
  30378 #endif /* chips */
  30379 
  30380 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30381     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30382     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_6r */
  30383         soc_block_list[61],
  30384         soc_iprocreg,
  30385         1,
  30386         0,
  30387         0x180422c0,
  30388         0,
  30389         0,
  30390         12,
  30391         soc_USB2D_ENDPNT_OUT_CTRL_0r_fields,
  30392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30393         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30394         -1,
  30395         -1,
  30396     },
  30397 #endif /* chips */
  30398 
  30399 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30400     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30401     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_7r */
  30402         soc_block_list[61],
  30403         soc_iprocreg,
  30404         1,
  30405         0,
  30406         0x180422e0,
  30407         0,
  30408         0,
  30409         12,
  30410         soc_USB2D_ENDPNT_OUT_CTRL_0r_fields,
  30411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30412         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30413         -1,
  30414         -1,
  30415     },
  30416 #endif /* chips */
  30417 
  30418 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30419     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30420     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_8r */
  30421         soc_block_list[61],
  30422         soc_iprocreg,
  30423         1,
  30424         0,
  30425         0x18042300,
  30426         0,
  30427         0,
  30428         12,
  30429         soc_USB2D_ENDPNT_OUT_CTRL_0r_fields,
  30430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30431         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30432         -1,
  30433         -1,
  30434     },
  30435 #endif /* chips */
  30436 
  30437 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30438     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30439     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_9r */
  30440         soc_block_list[61],
  30441         soc_iprocreg,
  30442         1,
  30443         0,
  30444         0x18042320,
  30445         0,
  30446         0,
  30447         12,
  30448         soc_USB2D_ENDPNT_OUT_CTRL_0r_fields,
  30449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30450         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30451         -1,
  30452         -1,
  30453     },
  30454 #endif /* chips */
  30455 
  30456 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30457     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30458     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30459     defined(BCM_56260_B0)
  30460     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r */
  30461         soc_block_list[61],
  30462         soc_iprocreg,
  30463         1,
  30464         0,
  30465         0x1804c200,
  30466         0,
  30467         0,
  30468         12,
  30469         soc_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r_fields,
  30470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30471         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30472         -1,
  30473         -1,
  30474     },
  30475 #endif /* chips */
  30476 
  30477 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30478     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30479     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30480     defined(BCM_56260_B0)
  30481     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_1_BCM53400_A0r */
  30482         soc_block_list[61],
  30483         soc_iprocreg,
  30484         1,
  30485         0,
  30486         0x1804c220,
  30487         0,
  30488         0,
  30489         12,
  30490         soc_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r_fields,
  30491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30492         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30493         -1,
  30494         -1,
  30495     },
  30496 #endif /* chips */
  30497 
  30498 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30499     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30500     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30501     defined(BCM_56260_B0)
  30502     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_2_BCM53400_A0r */
  30503         soc_block_list[61],
  30504         soc_iprocreg,
  30505         1,
  30506         0,
  30507         0x1804c240,
  30508         0,
  30509         0,
  30510         12,
  30511         soc_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r_fields,
  30512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30513         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30514         -1,
  30515         -1,
  30516     },
  30517 #endif /* chips */
  30518 
  30519 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30520     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30521     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30522     defined(BCM_56260_B0)
  30523     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_3_BCM53400_A0r */
  30524         soc_block_list[61],
  30525         soc_iprocreg,
  30526         1,
  30527         0,
  30528         0x1804c260,
  30529         0,
  30530         0,
  30531         12,
  30532         soc_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r_fields,
  30533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30534         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30535         -1,
  30536         -1,
  30537     },
  30538 #endif /* chips */
  30539 
  30540 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30541     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30542     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30543     defined(BCM_56260_B0)
  30544     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_4_BCM53400_A0r */
  30545         soc_block_list[61],
  30546         soc_iprocreg,
  30547         1,
  30548         0,
  30549         0x1804c280,
  30550         0,
  30551         0,
  30552         12,
  30553         soc_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r_fields,
  30554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30555         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30556         -1,
  30557         -1,
  30558     },
  30559 #endif /* chips */
  30560 
  30561 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30562     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30563     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30564     defined(BCM_56260_B0)
  30565     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_5_BCM53400_A0r */
  30566         soc_block_list[61],
  30567         soc_iprocreg,
  30568         1,
  30569         0,
  30570         0x1804c2a0,
  30571         0,
  30572         0,
  30573         12,
  30574         soc_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r_fields,
  30575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30576         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30577         -1,
  30578         -1,
  30579     },
  30580 #endif /* chips */
  30581 
  30582 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30583     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30584     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30585     defined(BCM_56260_B0)
  30586     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_6_BCM53400_A0r */
  30587         soc_block_list[61],
  30588         soc_iprocreg,
  30589         1,
  30590         0,
  30591         0x1804c2c0,
  30592         0,
  30593         0,
  30594         12,
  30595         soc_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r_fields,
  30596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30597         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30598         -1,
  30599         -1,
  30600     },
  30601 #endif /* chips */
  30602 
  30603 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30604     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30605     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30606     defined(BCM_56260_B0)
  30607     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_7_BCM53400_A0r */
  30608         soc_block_list[61],
  30609         soc_iprocreg,
  30610         1,
  30611         0,
  30612         0x1804c2e0,
  30613         0,
  30614         0,
  30615         12,
  30616         soc_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r_fields,
  30617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30618         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30619         -1,
  30620         -1,
  30621     },
  30622 #endif /* chips */
  30623 
  30624 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30625     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30626     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30627     defined(BCM_56260_B0)
  30628     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_8_BCM53400_A0r */
  30629         soc_block_list[61],
  30630         soc_iprocreg,
  30631         1,
  30632         0,
  30633         0x1804c300,
  30634         0,
  30635         0,
  30636         12,
  30637         soc_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r_fields,
  30638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30639         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30640         -1,
  30641         -1,
  30642     },
  30643 #endif /* chips */
  30644 
  30645 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30646     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30647     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30648     defined(BCM_56260_B0)
  30649     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_CTRL_9_BCM53400_A0r */
  30650         soc_block_list[61],
  30651         soc_iprocreg,
  30652         1,
  30653         0,
  30654         0x1804c320,
  30655         0,
  30656         0,
  30657         12,
  30658         soc_USB2D_ENDPNT_OUT_CTRL_0_BCM53400_A0r_fields,
  30659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30660         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30661         -1,
  30662         -1,
  30663     },
  30664 #endif /* chips */
  30665 
  30666 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30667     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30668     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_0r */
  30669         soc_block_list[61],
  30670         soc_iprocreg,
  30671         1,
  30672         0,
  30673         0x18042214,
  30674         0,
  30675         0,
  30676         1,
  30677         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  30678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30680         -1,
  30681         -1,
  30682     },
  30683 #endif /* chips */
  30684 
  30685 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30686     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30687     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_1r */
  30688         soc_block_list[61],
  30689         soc_iprocreg,
  30690         1,
  30691         0,
  30692         0x18042234,
  30693         0,
  30694         0,
  30695         1,
  30696         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  30697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30698         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30699         -1,
  30700         -1,
  30701     },
  30702 #endif /* chips */
  30703 
  30704 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30705     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30706     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_2r */
  30707         soc_block_list[61],
  30708         soc_iprocreg,
  30709         1,
  30710         0,
  30711         0x18042254,
  30712         0,
  30713         0,
  30714         1,
  30715         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  30716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30718         -1,
  30719         -1,
  30720     },
  30721 #endif /* chips */
  30722 
  30723 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30724     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30725     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_3r */
  30726         soc_block_list[61],
  30727         soc_iprocreg,
  30728         1,
  30729         0,
  30730         0x18042274,
  30731         0,
  30732         0,
  30733         1,
  30734         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  30735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30736         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30737         -1,
  30738         -1,
  30739     },
  30740 #endif /* chips */
  30741 
  30742 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30743     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30744     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_4r */
  30745         soc_block_list[61],
  30746         soc_iprocreg,
  30747         1,
  30748         0,
  30749         0x18042294,
  30750         0,
  30751         0,
  30752         1,
  30753         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  30754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30755         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30756         -1,
  30757         -1,
  30758     },
  30759 #endif /* chips */
  30760 
  30761 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30762     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30763     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_5r */
  30764         soc_block_list[61],
  30765         soc_iprocreg,
  30766         1,
  30767         0,
  30768         0x180422b4,
  30769         0,
  30770         0,
  30771         1,
  30772         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  30773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30774         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30775         -1,
  30776         -1,
  30777     },
  30778 #endif /* chips */
  30779 
  30780 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30781     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30782     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_6r */
  30783         soc_block_list[61],
  30784         soc_iprocreg,
  30785         1,
  30786         0,
  30787         0x180422d4,
  30788         0,
  30789         0,
  30790         1,
  30791         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  30792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30793         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30794         -1,
  30795         -1,
  30796     },
  30797 #endif /* chips */
  30798 
  30799 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30800     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30801     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_7r */
  30802         soc_block_list[61],
  30803         soc_iprocreg,
  30804         1,
  30805         0,
  30806         0x180422f4,
  30807         0,
  30808         0,
  30809         1,
  30810         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  30811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30812         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30813         -1,
  30814         -1,
  30815     },
  30816 #endif /* chips */
  30817 
  30818 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30819     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30820     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_8r */
  30821         soc_block_list[61],
  30822         soc_iprocreg,
  30823         1,
  30824         0,
  30825         0x18042314,
  30826         0,
  30827         0,
  30828         1,
  30829         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  30830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30831         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30832         -1,
  30833         -1,
  30834     },
  30835 #endif /* chips */
  30836 
  30837 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  30838     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  30839     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_9r */
  30840         soc_block_list[61],
  30841         soc_iprocreg,
  30842         1,
  30843         0,
  30844         0x18042334,
  30845         0,
  30846         0,
  30847         1,
  30848         soc_USB2D_ENDPNT_IN_DATADESCR_0r_fields,
  30849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30850         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30851         -1,
  30852         -1,
  30853     },
  30854 #endif /* chips */
  30855 
  30856 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30857     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30858     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30859     defined(BCM_56260_B0)
  30860     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_0_BCM53400_A0r */
  30861         soc_block_list[61],
  30862         soc_iprocreg,
  30863         1,
  30864         0,
  30865         0x1804c214,
  30866         0,
  30867         0,
  30868         1,
  30869         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  30870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30871         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30872         -1,
  30873         -1,
  30874     },
  30875 #endif /* chips */
  30876 
  30877 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30878     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30879     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30880     defined(BCM_56260_B0)
  30881     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_1_BCM53400_A0r */
  30882         soc_block_list[61],
  30883         soc_iprocreg,
  30884         1,
  30885         0,
  30886         0x1804c234,
  30887         0,
  30888         0,
  30889         1,
  30890         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  30891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30893         -1,
  30894         -1,
  30895     },
  30896 #endif /* chips */
  30897 
  30898 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30899     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30900     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30901     defined(BCM_56260_B0)
  30902     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_2_BCM53400_A0r */
  30903         soc_block_list[61],
  30904         soc_iprocreg,
  30905         1,
  30906         0,
  30907         0x1804c254,
  30908         0,
  30909         0,
  30910         1,
  30911         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  30912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30913         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30914         -1,
  30915         -1,
  30916     },
  30917 #endif /* chips */
  30918 
  30919 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30920     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30921     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30922     defined(BCM_56260_B0)
  30923     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_3_BCM53400_A0r */
  30924         soc_block_list[61],
  30925         soc_iprocreg,
  30926         1,
  30927         0,
  30928         0x1804c274,
  30929         0,
  30930         0,
  30931         1,
  30932         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  30933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30934         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30935         -1,
  30936         -1,
  30937     },
  30938 #endif /* chips */
  30939 
  30940 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30941     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30942     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30943     defined(BCM_56260_B0)
  30944     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_4_BCM53400_A0r */
  30945         soc_block_list[61],
  30946         soc_iprocreg,
  30947         1,
  30948         0,
  30949         0x1804c294,
  30950         0,
  30951         0,
  30952         1,
  30953         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  30954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30956         -1,
  30957         -1,
  30958     },
  30959 #endif /* chips */
  30960 
  30961 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30962     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30963     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30964     defined(BCM_56260_B0)
  30965     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_5_BCM53400_A0r */
  30966         soc_block_list[61],
  30967         soc_iprocreg,
  30968         1,
  30969         0,
  30970         0x1804c2b4,
  30971         0,
  30972         0,
  30973         1,
  30974         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  30975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30976         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30977         -1,
  30978         -1,
  30979     },
  30980 #endif /* chips */
  30981 
  30982 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30983     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30984     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30985     defined(BCM_56260_B0)
  30986     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_6_BCM53400_A0r */
  30987         soc_block_list[61],
  30988         soc_iprocreg,
  30989         1,
  30990         0,
  30991         0x1804c2d4,
  30992         0,
  30993         0,
  30994         1,
  30995         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  30996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30997         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30998         -1,
  30999         -1,
  31000     },
  31001 #endif /* chips */
  31002 
  31003 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31004     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31005     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31006     defined(BCM_56260_B0)
  31007     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_7_BCM53400_A0r */
  31008         soc_block_list[61],
  31009         soc_iprocreg,
  31010         1,
  31011         0,
  31012         0x1804c2f4,
  31013         0,
  31014         0,
  31015         1,
  31016         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  31017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31018         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31019         -1,
  31020         -1,
  31021     },
  31022 #endif /* chips */
  31023 
  31024 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31025     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31026     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31027     defined(BCM_56260_B0)
  31028     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_8_BCM53400_A0r */
  31029         soc_block_list[61],
  31030         soc_iprocreg,
  31031         1,
  31032         0,
  31033         0x1804c314,
  31034         0,
  31035         0,
  31036         1,
  31037         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  31038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31039         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31040         -1,
  31041         -1,
  31042     },
  31043 #endif /* chips */
  31044 
  31045 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31046     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31047     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31048     defined(BCM_56260_B0)
  31049     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_DATADESCR_9_BCM53400_A0r */
  31050         soc_block_list[61],
  31051         soc_iprocreg,
  31052         1,
  31053         0,
  31054         0x1804c334,
  31055         0,
  31056         0,
  31057         1,
  31058         soc_USB2D_ENDPNT_IN_DATADESCR_0_BCM53400_A0r_fields,
  31059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31060         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31061         -1,
  31062         -1,
  31063     },
  31064 #endif /* chips */
  31065 
  31066 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31067     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31068     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_0r */
  31069         soc_block_list[61],
  31070         soc_iprocreg,
  31071         1,
  31072         0,
  31073         0x18042210,
  31074         0,
  31075         0,
  31076         1,
  31077         soc_USB2D_ENDPNT_OUT_SETUPBUF_0r_fields,
  31078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31079         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31080         -1,
  31081         -1,
  31082     },
  31083 #endif /* chips */
  31084 
  31085 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31086     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31087     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_1r */
  31088         soc_block_list[61],
  31089         soc_iprocreg,
  31090         1,
  31091         0,
  31092         0x18042230,
  31093         0,
  31094         0,
  31095         1,
  31096         soc_USB2D_ENDPNT_OUT_SETUPBUF_0r_fields,
  31097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31098         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31099         -1,
  31100         -1,
  31101     },
  31102 #endif /* chips */
  31103 
  31104 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31105     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31106     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_2r */
  31107         soc_block_list[61],
  31108         soc_iprocreg,
  31109         1,
  31110         0,
  31111         0x18042250,
  31112         0,
  31113         0,
  31114         1,
  31115         soc_USB2D_ENDPNT_OUT_SETUPBUF_0r_fields,
  31116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31117         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31118         -1,
  31119         -1,
  31120     },
  31121 #endif /* chips */
  31122 
  31123 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31124     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31125     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_3r */
  31126         soc_block_list[61],
  31127         soc_iprocreg,
  31128         1,
  31129         0,
  31130         0x18042270,
  31131         0,
  31132         0,
  31133         1,
  31134         soc_USB2D_ENDPNT_OUT_SETUPBUF_0r_fields,
  31135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31136         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31137         -1,
  31138         -1,
  31139     },
  31140 #endif /* chips */
  31141 
  31142 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31143     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31144     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_4r */
  31145         soc_block_list[61],
  31146         soc_iprocreg,
  31147         1,
  31148         0,
  31149         0x18042290,
  31150         0,
  31151         0,
  31152         1,
  31153         soc_USB2D_ENDPNT_OUT_SETUPBUF_0r_fields,
  31154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31156         -1,
  31157         -1,
  31158     },
  31159 #endif /* chips */
  31160 
  31161 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31162     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31163     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_5r */
  31164         soc_block_list[61],
  31165         soc_iprocreg,
  31166         1,
  31167         0,
  31168         0x180422b0,
  31169         0,
  31170         0,
  31171         1,
  31172         soc_USB2D_ENDPNT_OUT_SETUPBUF_0r_fields,
  31173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31174         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31175         -1,
  31176         -1,
  31177     },
  31178 #endif /* chips */
  31179 
  31180 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31181     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31182     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_6r */
  31183         soc_block_list[61],
  31184         soc_iprocreg,
  31185         1,
  31186         0,
  31187         0x180422d0,
  31188         0,
  31189         0,
  31190         1,
  31191         soc_USB2D_ENDPNT_OUT_SETUPBUF_0r_fields,
  31192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31193         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31194         -1,
  31195         -1,
  31196     },
  31197 #endif /* chips */
  31198 
  31199 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31200     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31201     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_7r */
  31202         soc_block_list[61],
  31203         soc_iprocreg,
  31204         1,
  31205         0,
  31206         0x180422f0,
  31207         0,
  31208         0,
  31209         1,
  31210         soc_USB2D_ENDPNT_OUT_SETUPBUF_0r_fields,
  31211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31212         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31213         -1,
  31214         -1,
  31215     },
  31216 #endif /* chips */
  31217 
  31218 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31219     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31220     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_8r */
  31221         soc_block_list[61],
  31222         soc_iprocreg,
  31223         1,
  31224         0,
  31225         0x18042310,
  31226         0,
  31227         0,
  31228         1,
  31229         soc_USB2D_ENDPNT_OUT_SETUPBUF_0r_fields,
  31230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31231         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31232         -1,
  31233         -1,
  31234     },
  31235 #endif /* chips */
  31236 
  31237 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31238     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31239     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_9r */
  31240         soc_block_list[61],
  31241         soc_iprocreg,
  31242         1,
  31243         0,
  31244         0x18042330,
  31245         0,
  31246         0,
  31247         1,
  31248         soc_USB2D_ENDPNT_OUT_SETUPBUF_0r_fields,
  31249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31250         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31251         -1,
  31252         -1,
  31253     },
  31254 #endif /* chips */
  31255 
  31256 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31257     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31258     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31259     defined(BCM_56260_B0)
  31260     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r */
  31261         soc_block_list[61],
  31262         soc_iprocreg,
  31263         1,
  31264         0,
  31265         0x1804c210,
  31266         0,
  31267         0,
  31268         1,
  31269         soc_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r_fields,
  31270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31271         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31272         -1,
  31273         -1,
  31274     },
  31275 #endif /* chips */
  31276 
  31277 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31278     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31279     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31280     defined(BCM_56260_B0)
  31281     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_1_BCM53400_A0r */
  31282         soc_block_list[61],
  31283         soc_iprocreg,
  31284         1,
  31285         0,
  31286         0x1804c230,
  31287         0,
  31288         0,
  31289         1,
  31290         soc_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r_fields,
  31291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31292         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31293         -1,
  31294         -1,
  31295     },
  31296 #endif /* chips */
  31297 
  31298 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31299     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31300     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31301     defined(BCM_56260_B0)
  31302     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_2_BCM53400_A0r */
  31303         soc_block_list[61],
  31304         soc_iprocreg,
  31305         1,
  31306         0,
  31307         0x1804c250,
  31308         0,
  31309         0,
  31310         1,
  31311         soc_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r_fields,
  31312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31313         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31314         -1,
  31315         -1,
  31316     },
  31317 #endif /* chips */
  31318 
  31319 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31320     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31321     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31322     defined(BCM_56260_B0)
  31323     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_3_BCM53400_A0r */
  31324         soc_block_list[61],
  31325         soc_iprocreg,
  31326         1,
  31327         0,
  31328         0x1804c270,
  31329         0,
  31330         0,
  31331         1,
  31332         soc_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r_fields,
  31333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31334         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31335         -1,
  31336         -1,
  31337     },
  31338 #endif /* chips */
  31339 
  31340 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31341     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31342     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31343     defined(BCM_56260_B0)
  31344     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_4_BCM53400_A0r */
  31345         soc_block_list[61],
  31346         soc_iprocreg,
  31347         1,
  31348         0,
  31349         0x1804c290,
  31350         0,
  31351         0,
  31352         1,
  31353         soc_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r_fields,
  31354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31355         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31356         -1,
  31357         -1,
  31358     },
  31359 #endif /* chips */
  31360 
  31361 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31362     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31363     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31364     defined(BCM_56260_B0)
  31365     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_5_BCM53400_A0r */
  31366         soc_block_list[61],
  31367         soc_iprocreg,
  31368         1,
  31369         0,
  31370         0x1804c2b0,
  31371         0,
  31372         0,
  31373         1,
  31374         soc_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r_fields,
  31375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31376         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31377         -1,
  31378         -1,
  31379     },
  31380 #endif /* chips */
  31381 
  31382 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31383     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31384     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31385     defined(BCM_56260_B0)
  31386     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_6_BCM53400_A0r */
  31387         soc_block_list[61],
  31388         soc_iprocreg,
  31389         1,
  31390         0,
  31391         0x1804c2d0,
  31392         0,
  31393         0,
  31394         1,
  31395         soc_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r_fields,
  31396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31397         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31398         -1,
  31399         -1,
  31400     },
  31401 #endif /* chips */
  31402 
  31403 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31404     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31405     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31406     defined(BCM_56260_B0)
  31407     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_7_BCM53400_A0r */
  31408         soc_block_list[61],
  31409         soc_iprocreg,
  31410         1,
  31411         0,
  31412         0x1804c2f0,
  31413         0,
  31414         0,
  31415         1,
  31416         soc_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r_fields,
  31417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31418         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31419         -1,
  31420         -1,
  31421     },
  31422 #endif /* chips */
  31423 
  31424 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31425     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31426     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31427     defined(BCM_56260_B0)
  31428     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_8_BCM53400_A0r */
  31429         soc_block_list[61],
  31430         soc_iprocreg,
  31431         1,
  31432         0,
  31433         0x1804c310,
  31434         0,
  31435         0,
  31436         1,
  31437         soc_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r_fields,
  31438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31439         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31440         -1,
  31441         -1,
  31442     },
  31443 #endif /* chips */
  31444 
  31445 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31446     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31447     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31448     defined(BCM_56260_B0)
  31449     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_SETUPBUF_9_BCM53400_A0r */
  31450         soc_block_list[61],
  31451         soc_iprocreg,
  31452         1,
  31453         0,
  31454         0x1804c330,
  31455         0,
  31456         0,
  31457         1,
  31458         soc_USB2D_ENDPNT_OUT_SETUPBUF_0_BCM53400_A0r_fields,
  31459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31460         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31461         -1,
  31462         -1,
  31463     },
  31464 #endif /* chips */
  31465 
  31466 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31467     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31468     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_0r */
  31469         soc_block_list[61],
  31470         soc_iprocreg,
  31471         1,
  31472         0,
  31473         0x18042204,
  31474         0,
  31475         0,
  31476         13,
  31477         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  31478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31479         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31480         -1,
  31481         -1,
  31482     },
  31483 #endif /* chips */
  31484 
  31485 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31486     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31487     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_1r */
  31488         soc_block_list[61],
  31489         soc_iprocreg,
  31490         1,
  31491         0,
  31492         0x18042224,
  31493         0,
  31494         0,
  31495         13,
  31496         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  31497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31498         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31499         -1,
  31500         -1,
  31501     },
  31502 #endif /* chips */
  31503 
  31504 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31505     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31506     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_2r */
  31507         soc_block_list[61],
  31508         soc_iprocreg,
  31509         1,
  31510         0,
  31511         0x18042244,
  31512         0,
  31513         0,
  31514         13,
  31515         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  31516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31517         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31518         -1,
  31519         -1,
  31520     },
  31521 #endif /* chips */
  31522 
  31523 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31524     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31525     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_3r */
  31526         soc_block_list[61],
  31527         soc_iprocreg,
  31528         1,
  31529         0,
  31530         0x18042264,
  31531         0,
  31532         0,
  31533         13,
  31534         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  31535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31536         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31537         -1,
  31538         -1,
  31539     },
  31540 #endif /* chips */
  31541 
  31542 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31543     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31544     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_4r */
  31545         soc_block_list[61],
  31546         soc_iprocreg,
  31547         1,
  31548         0,
  31549         0x18042284,
  31550         0,
  31551         0,
  31552         13,
  31553         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  31554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31555         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31556         -1,
  31557         -1,
  31558     },
  31559 #endif /* chips */
  31560 
  31561 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31562     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31563     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_5r */
  31564         soc_block_list[61],
  31565         soc_iprocreg,
  31566         1,
  31567         0,
  31568         0x180422a4,
  31569         0,
  31570         0,
  31571         13,
  31572         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  31573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31574         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31575         -1,
  31576         -1,
  31577     },
  31578 #endif /* chips */
  31579 
  31580 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31581     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31582     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_6r */
  31583         soc_block_list[61],
  31584         soc_iprocreg,
  31585         1,
  31586         0,
  31587         0x180422c4,
  31588         0,
  31589         0,
  31590         13,
  31591         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  31592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31593         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31594         -1,
  31595         -1,
  31596     },
  31597 #endif /* chips */
  31598 
  31599 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31600     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31601     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_7r */
  31602         soc_block_list[61],
  31603         soc_iprocreg,
  31604         1,
  31605         0,
  31606         0x180422e4,
  31607         0,
  31608         0,
  31609         13,
  31610         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  31611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31612         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31613         -1,
  31614         -1,
  31615     },
  31616 #endif /* chips */
  31617 
  31618 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31619     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31620     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_8r */
  31621         soc_block_list[61],
  31622         soc_iprocreg,
  31623         1,
  31624         0,
  31625         0x18042304,
  31626         0,
  31627         0,
  31628         13,
  31629         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  31630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31631         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31632         -1,
  31633         -1,
  31634     },
  31635 #endif /* chips */
  31636 
  31637 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31638     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31639     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_9r */
  31640         soc_block_list[61],
  31641         soc_iprocreg,
  31642         1,
  31643         0,
  31644         0x18042324,
  31645         0,
  31646         0,
  31647         13,
  31648         soc_USB2D_ENDPNT_IN_STATUS_0r_fields,
  31649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31650         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31651         -1,
  31652         -1,
  31653     },
  31654 #endif /* chips */
  31655 
  31656 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31657     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31658     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31659     defined(BCM_56260_B0)
  31660     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_0_BCM53400_A0r */
  31661         soc_block_list[61],
  31662         soc_iprocreg,
  31663         1,
  31664         0,
  31665         0x1804c204,
  31666         0,
  31667         0,
  31668         13,
  31669         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  31670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31671         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31672         -1,
  31673         -1,
  31674     },
  31675 #endif /* chips */
  31676 
  31677 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31678     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31679     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31680     defined(BCM_56260_B0)
  31681     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_1_BCM53400_A0r */
  31682         soc_block_list[61],
  31683         soc_iprocreg,
  31684         1,
  31685         0,
  31686         0x1804c224,
  31687         0,
  31688         0,
  31689         13,
  31690         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  31691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31692         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31693         -1,
  31694         -1,
  31695     },
  31696 #endif /* chips */
  31697 
  31698 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31699     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31700     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31701     defined(BCM_56260_B0)
  31702     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_2_BCM53400_A0r */
  31703         soc_block_list[61],
  31704         soc_iprocreg,
  31705         1,
  31706         0,
  31707         0x1804c244,
  31708         0,
  31709         0,
  31710         13,
  31711         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  31712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31713         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31714         -1,
  31715         -1,
  31716     },
  31717 #endif /* chips */
  31718 
  31719 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31720     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31721     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31722     defined(BCM_56260_B0)
  31723     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_3_BCM53400_A0r */
  31724         soc_block_list[61],
  31725         soc_iprocreg,
  31726         1,
  31727         0,
  31728         0x1804c264,
  31729         0,
  31730         0,
  31731         13,
  31732         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  31733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31734         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31735         -1,
  31736         -1,
  31737     },
  31738 #endif /* chips */
  31739 
  31740 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31741     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31742     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31743     defined(BCM_56260_B0)
  31744     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_4_BCM53400_A0r */
  31745         soc_block_list[61],
  31746         soc_iprocreg,
  31747         1,
  31748         0,
  31749         0x1804c284,
  31750         0,
  31751         0,
  31752         13,
  31753         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  31754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31755         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31756         -1,
  31757         -1,
  31758     },
  31759 #endif /* chips */
  31760 
  31761 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31762     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31763     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31764     defined(BCM_56260_B0)
  31765     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_5_BCM53400_A0r */
  31766         soc_block_list[61],
  31767         soc_iprocreg,
  31768         1,
  31769         0,
  31770         0x1804c2a4,
  31771         0,
  31772         0,
  31773         13,
  31774         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  31775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31776         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31777         -1,
  31778         -1,
  31779     },
  31780 #endif /* chips */
  31781 
  31782 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31783     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31784     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31785     defined(BCM_56260_B0)
  31786     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_6_BCM53400_A0r */
  31787         soc_block_list[61],
  31788         soc_iprocreg,
  31789         1,
  31790         0,
  31791         0x1804c2c4,
  31792         0,
  31793         0,
  31794         13,
  31795         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  31796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31797         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31798         -1,
  31799         -1,
  31800     },
  31801 #endif /* chips */
  31802 
  31803 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31804     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31805     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31806     defined(BCM_56260_B0)
  31807     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_7_BCM53400_A0r */
  31808         soc_block_list[61],
  31809         soc_iprocreg,
  31810         1,
  31811         0,
  31812         0x1804c2e4,
  31813         0,
  31814         0,
  31815         13,
  31816         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  31817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31818         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31819         -1,
  31820         -1,
  31821     },
  31822 #endif /* chips */
  31823 
  31824 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31825     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31826     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31827     defined(BCM_56260_B0)
  31828     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_8_BCM53400_A0r */
  31829         soc_block_list[61],
  31830         soc_iprocreg,
  31831         1,
  31832         0,
  31833         0x1804c304,
  31834         0,
  31835         0,
  31836         13,
  31837         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  31838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31839         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31840         -1,
  31841         -1,
  31842     },
  31843 #endif /* chips */
  31844 
  31845 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31846     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31847     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31848     defined(BCM_56260_B0)
  31849     { /* SOC_REG_INT_USB2D_ENDPNT_OUT_STATUS_9_BCM53400_A0r */
  31850         soc_block_list[61],
  31851         soc_iprocreg,
  31852         1,
  31853         0,
  31854         0x1804c324,
  31855         0,
  31856         0,
  31857         13,
  31858         soc_USB2D_ENDPNT_IN_STATUS_0_BCM53400_A0r_fields,
  31859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31860         SOC_RESET_MASK_DEC(0x1ffffff0, 0x00000000)
  31861         -1,
  31862         -1,
  31863     },
  31864 #endif /* chips */
  31865 
  31866 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31867     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31868     { /* SOC_REG_INT_USB2D_IDM_IDM_INTERRUPT_STATUSr */
  31869         soc_block_list[61],
  31870         soc_iprocreg,
  31871         1,
  31872         0,
  31873         0x18116a00,
  31874         SOC_REG_FLAG_RO,
  31875         0,
  31876         3,
  31877         soc_A9JTAG_M0_IDM_IDM_INTERRUPT_STATUS_BCM56450_A0r_fields,
  31878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31879         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31880         -1,
  31881         -1,
  31882     },
  31883 #endif /* chips */
  31884 
  31885 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31886     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31887     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31888     defined(BCM_56260_B0) || defined(BCM_56270_A0) || \
  31889     defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  31890     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  31891     { /* SOC_REG_INT_USB2D_IDM_IDM_INTERRUPT_STATUS_BCM53400_A0r */
  31892         soc_block_list[61],
  31893         soc_iprocreg,
  31894         1,
  31895         0,
  31896         0x18111a00,
  31897         SOC_REG_FLAG_RO,
  31898         0,
  31899         3,
  31900         soc_A9JTAG_M0_IDM_IDM_INTERRUPT_STATUS_BCM53400_A0r_fields,
  31901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31902         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31903         -1,
  31904         -1,
  31905     },
  31906 #endif /* chips */
  31907 
  31908 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31909     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31910     { /* SOC_REG_INT_USB2D_IDM_IDM_IO_CONTROL_DIRECTr */
  31911         soc_block_list[61],
  31912         soc_iprocreg,
  31913         1,
  31914         0,
  31915         0x18116408,
  31916         0,
  31917         0,
  31918         18,
  31919         soc_USB2D_IDM_IDM_IO_CONTROL_DIRECTr_fields,
  31920         SOC_RESET_VAL_DEC(0x000003fc, 0x00000000)
  31921         SOC_RESET_MASK_DEC(0xf7ff03fd, 0x00000000)
  31922         -1,
  31923         -1,
  31924     },
  31925 #endif /* chips */
  31926 
  31927 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31928     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31929     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31930     defined(BCM_56260_B0)
  31931     { /* SOC_REG_INT_USB2D_IDM_IDM_IO_CONTROL_DIRECT_BCM53400_A0r */
  31932         soc_block_list[61],
  31933         soc_iprocreg,
  31934         1,
  31935         0,
  31936         0x18111408,
  31937         0,
  31938         0,
  31939         20,
  31940         soc_USB2D_IDM_IDM_IO_CONTROL_DIRECT_BCM53400_A0r_fields,
  31941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31942         SOC_RESET_MASK_DEC(0xf7ffc3fd, 0x00000000)
  31943         -1,
  31944         -1,
  31945     },
  31946 #endif /* chips */
  31947 
  31948 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31949     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31950     { /* SOC_REG_INT_USB2D_IDM_IDM_IO_STATUSr */
  31951         soc_block_list[61],
  31952         soc_iprocreg,
  31953         1,
  31954         0,
  31955         0x18116500,
  31956         SOC_REG_FLAG_RO,
  31957         0,
  31958         1,
  31959         soc_DDR_S2_IDM_IO_STATUSr_fields,
  31960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31961         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31962         -1,
  31963         -1,
  31964     },
  31965 #endif /* chips */
  31966 
  31967 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31968     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31969     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31970     defined(BCM_56260_B0)
  31971     { /* SOC_REG_INT_USB2D_IDM_IDM_IO_STATUS_BCM53400_A0r */
  31972         soc_block_list[61],
  31973         soc_iprocreg,
  31974         1,
  31975         0,
  31976         0x18111500,
  31977         SOC_REG_FLAG_RO,
  31978         0,
  31979         1,
  31980         soc_CMICD_S0_IDM_IDM_IO_STATUS_BCM53400_A0r_fields,
  31981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31982         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31983         -1,
  31984         -1,
  31985     },
  31986 #endif /* chips */
  31987 
  31988 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  31989     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  31990     { /* SOC_REG_INT_USB2D_IDM_IDM_RESET_CONTROLr */
  31991         soc_block_list[61],
  31992         soc_iprocreg,
  31993         1,
  31994         0,
  31995         0x18116800,
  31996         0,
  31997         0,
  31998         2,
  31999         soc_AMAC_IDM0_IDM_RESET_CONTROLr_fields,
  32000         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  32001         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32002         -1,
  32003         -1,
  32004     },
  32005 #endif /* chips */
  32006 
  32007 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32008     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32009     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32010     defined(BCM_56260_B0)
  32011     { /* SOC_REG_INT_USB2D_IDM_IDM_RESET_CONTROL_BCM53400_A0r */
  32012         soc_block_list[61],
  32013         soc_iprocreg,
  32014         1,
  32015         0,
  32016         0x18111800,
  32017         0,
  32018         0,
  32019         2,
  32020         soc_AMAC_IDM0_IDM_RESET_CONTROL_BCM53400_A0r_fields,
  32021         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  32022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32023         -1,
  32024         -1,
  32025     },
  32026 #endif /* chips */
  32027 
  32028 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32029     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32030     { /* SOC_REG_INT_USB2D_IDM_IDM_RESET_STATUSr */
  32031         soc_block_list[61],
  32032         soc_iprocreg,
  32033         1,
  32034         0,
  32035         0x18116804,
  32036         SOC_REG_FLAG_RO,
  32037         0,
  32038         5,
  32039         soc_A9JTAG_M0_IDM_IDM_RESET_STATUS_BCM56450_A0r_fields,
  32040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32041         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32042         -1,
  32043         -1,
  32044     },
  32045 #endif /* chips */
  32046 
  32047 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32048     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32049     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32050     defined(BCM_56260_B0) || defined(BCM_56270_A0) || \
  32051     defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  32052     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  32053     { /* SOC_REG_INT_USB2D_IDM_IDM_RESET_STATUS_BCM53400_A0r */
  32054         soc_block_list[61],
  32055         soc_iprocreg,
  32056         1,
  32057         0,
  32058         0x18111804,
  32059         SOC_REG_FLAG_RO,
  32060         0,
  32061         5,
  32062         soc_A9JTAG_M0_IDM_IDM_RESET_STATUS_BCM53400_A0r_fields,
  32063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32064         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32065         -1,
  32066         -1,
  32067     },
  32068 #endif /* chips */
  32069 
  32070 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32071     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32072     { /* SOC_REG_INT_USB2D_LPMCTRLSTATUSr */
  32073         soc_block_list[61],
  32074         soc_iprocreg,
  32075         1,
  32076         0,
  32077         0x18042424,
  32078         0,
  32079         0,
  32080         10,
  32081         soc_USB2D_LPMCTRLSTATUSr_fields,
  32082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32083         SOC_RESET_MASK_DEC(0xff01ffff, 0x00000000)
  32084         -1,
  32085         -1,
  32086     },
  32087 #endif /* chips */
  32088 
  32089 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32090     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32091     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32092     defined(BCM_56260_B0)
  32093     { /* SOC_REG_INT_USB2D_LPMCTRLSTATUS_BCM53400_A0r */
  32094         soc_block_list[61],
  32095         soc_iprocreg,
  32096         1,
  32097         0,
  32098         0x1804c424,
  32099         0,
  32100         0,
  32101         10,
  32102         soc_USB2D_LPMCTRLSTATUS_BCM53400_A0r_fields,
  32103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32104         SOC_RESET_MASK_DEC(0xff01ffff, 0x00000000)
  32105         -1,
  32106         -1,
  32107     },
  32108 #endif /* chips */
  32109 
  32110 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32111     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32112     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_0r */
  32113         soc_block_list[61],
  32114         soc_iprocreg,
  32115         1,
  32116         0,
  32117         0x18042208,
  32118         SOC_REG_FLAG_RO,
  32119         0,
  32120         2,
  32121         soc_USB2D_RECPACKFRAMNO_0r_fields,
  32122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32123         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32124         -1,
  32125         -1,
  32126     },
  32127 #endif /* chips */
  32128 
  32129 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32130     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32131     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_1r */
  32132         soc_block_list[61],
  32133         soc_iprocreg,
  32134         1,
  32135         0,
  32136         0x18042228,
  32137         SOC_REG_FLAG_RO,
  32138         0,
  32139         2,
  32140         soc_USB2D_RECPACKFRAMNO_0r_fields,
  32141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32142         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32143         -1,
  32144         -1,
  32145     },
  32146 #endif /* chips */
  32147 
  32148 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32149     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32150     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_2r */
  32151         soc_block_list[61],
  32152         soc_iprocreg,
  32153         1,
  32154         0,
  32155         0x18042248,
  32156         SOC_REG_FLAG_RO,
  32157         0,
  32158         2,
  32159         soc_USB2D_RECPACKFRAMNO_0r_fields,
  32160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32161         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32162         -1,
  32163         -1,
  32164     },
  32165 #endif /* chips */
  32166 
  32167 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32168     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32169     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_3r */
  32170         soc_block_list[61],
  32171         soc_iprocreg,
  32172         1,
  32173         0,
  32174         0x18042268,
  32175         SOC_REG_FLAG_RO,
  32176         0,
  32177         2,
  32178         soc_USB2D_RECPACKFRAMNO_0r_fields,
  32179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32180         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32181         -1,
  32182         -1,
  32183     },
  32184 #endif /* chips */
  32185 
  32186 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32187     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32188     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_4r */
  32189         soc_block_list[61],
  32190         soc_iprocreg,
  32191         1,
  32192         0,
  32193         0x18042288,
  32194         SOC_REG_FLAG_RO,
  32195         0,
  32196         2,
  32197         soc_USB2D_RECPACKFRAMNO_0r_fields,
  32198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32199         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32200         -1,
  32201         -1,
  32202     },
  32203 #endif /* chips */
  32204 
  32205 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32206     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32207     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_5r */
  32208         soc_block_list[61],
  32209         soc_iprocreg,
  32210         1,
  32211         0,
  32212         0x180422a8,
  32213         SOC_REG_FLAG_RO,
  32214         0,
  32215         2,
  32216         soc_USB2D_RECPACKFRAMNO_0r_fields,
  32217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32218         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32219         -1,
  32220         -1,
  32221     },
  32222 #endif /* chips */
  32223 
  32224 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32225     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32226     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_6r */
  32227         soc_block_list[61],
  32228         soc_iprocreg,
  32229         1,
  32230         0,
  32231         0x180422c8,
  32232         SOC_REG_FLAG_RO,
  32233         0,
  32234         2,
  32235         soc_USB2D_RECPACKFRAMNO_0r_fields,
  32236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32237         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32238         -1,
  32239         -1,
  32240     },
  32241 #endif /* chips */
  32242 
  32243 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32244     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32245     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_7r */
  32246         soc_block_list[61],
  32247         soc_iprocreg,
  32248         1,
  32249         0,
  32250         0x180422e8,
  32251         SOC_REG_FLAG_RO,
  32252         0,
  32253         2,
  32254         soc_USB2D_RECPACKFRAMNO_0r_fields,
  32255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32256         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32257         -1,
  32258         -1,
  32259     },
  32260 #endif /* chips */
  32261 
  32262 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32263     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32264     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_8r */
  32265         soc_block_list[61],
  32266         soc_iprocreg,
  32267         1,
  32268         0,
  32269         0x18042308,
  32270         SOC_REG_FLAG_RO,
  32271         0,
  32272         2,
  32273         soc_USB2D_RECPACKFRAMNO_0r_fields,
  32274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32275         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32276         -1,
  32277         -1,
  32278     },
  32279 #endif /* chips */
  32280 
  32281 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32282     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32283     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_9r */
  32284         soc_block_list[61],
  32285         soc_iprocreg,
  32286         1,
  32287         0,
  32288         0x18042328,
  32289         SOC_REG_FLAG_RO,
  32290         0,
  32291         2,
  32292         soc_USB2D_RECPACKFRAMNO_0r_fields,
  32293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32294         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32295         -1,
  32296         -1,
  32297     },
  32298 #endif /* chips */
  32299 
  32300 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32301     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32302     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32303     defined(BCM_56260_B0)
  32304     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_0_BCM53400_A0r */
  32305         soc_block_list[61],
  32306         soc_iprocreg,
  32307         1,
  32308         0,
  32309         0x1804c208,
  32310         SOC_REG_FLAG_RO,
  32311         0,
  32312         2,
  32313         soc_USB2D_RECPACKFRAMNO_0_BCM53400_A0r_fields,
  32314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32315         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32316         -1,
  32317         -1,
  32318     },
  32319 #endif /* chips */
  32320 
  32321 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32322     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32323     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32324     defined(BCM_56260_B0)
  32325     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_1_BCM53400_A0r */
  32326         soc_block_list[61],
  32327         soc_iprocreg,
  32328         1,
  32329         0,
  32330         0x1804c228,
  32331         SOC_REG_FLAG_RO,
  32332         0,
  32333         2,
  32334         soc_USB2D_RECPACKFRAMNO_0_BCM53400_A0r_fields,
  32335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32336         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32337         -1,
  32338         -1,
  32339     },
  32340 #endif /* chips */
  32341 
  32342 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32343     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32344     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32345     defined(BCM_56260_B0)
  32346     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_2_BCM53400_A0r */
  32347         soc_block_list[61],
  32348         soc_iprocreg,
  32349         1,
  32350         0,
  32351         0x1804c248,
  32352         SOC_REG_FLAG_RO,
  32353         0,
  32354         2,
  32355         soc_USB2D_RECPACKFRAMNO_0_BCM53400_A0r_fields,
  32356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32357         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32358         -1,
  32359         -1,
  32360     },
  32361 #endif /* chips */
  32362 
  32363 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32364     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32365     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32366     defined(BCM_56260_B0)
  32367     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_3_BCM53400_A0r */
  32368         soc_block_list[61],
  32369         soc_iprocreg,
  32370         1,
  32371         0,
  32372         0x1804c268,
  32373         SOC_REG_FLAG_RO,
  32374         0,
  32375         2,
  32376         soc_USB2D_RECPACKFRAMNO_0_BCM53400_A0r_fields,
  32377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32378         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32379         -1,
  32380         -1,
  32381     },
  32382 #endif /* chips */
  32383 
  32384 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32385     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32386     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32387     defined(BCM_56260_B0)
  32388     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_4_BCM53400_A0r */
  32389         soc_block_list[61],
  32390         soc_iprocreg,
  32391         1,
  32392         0,
  32393         0x1804c288,
  32394         SOC_REG_FLAG_RO,
  32395         0,
  32396         2,
  32397         soc_USB2D_RECPACKFRAMNO_0_BCM53400_A0r_fields,
  32398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32399         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32400         -1,
  32401         -1,
  32402     },
  32403 #endif /* chips */
  32404 
  32405 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32406     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32407     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32408     defined(BCM_56260_B0)
  32409     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_5_BCM53400_A0r */
  32410         soc_block_list[61],
  32411         soc_iprocreg,
  32412         1,
  32413         0,
  32414         0x1804c2a8,
  32415         SOC_REG_FLAG_RO,
  32416         0,
  32417         2,
  32418         soc_USB2D_RECPACKFRAMNO_0_BCM53400_A0r_fields,
  32419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32420         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32421         -1,
  32422         -1,
  32423     },
  32424 #endif /* chips */
  32425 
  32426 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32427     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32428     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32429     defined(BCM_56260_B0)
  32430     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_6_BCM53400_A0r */
  32431         soc_block_list[61],
  32432         soc_iprocreg,
  32433         1,
  32434         0,
  32435         0x1804c2c8,
  32436         SOC_REG_FLAG_RO,
  32437         0,
  32438         2,
  32439         soc_USB2D_RECPACKFRAMNO_0_BCM53400_A0r_fields,
  32440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32441         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32442         -1,
  32443         -1,
  32444     },
  32445 #endif /* chips */
  32446 
  32447 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32448     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32449     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32450     defined(BCM_56260_B0)
  32451     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_7_BCM53400_A0r */
  32452         soc_block_list[61],
  32453         soc_iprocreg,
  32454         1,
  32455         0,
  32456         0x1804c2e8,
  32457         SOC_REG_FLAG_RO,
  32458         0,
  32459         2,
  32460         soc_USB2D_RECPACKFRAMNO_0_BCM53400_A0r_fields,
  32461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32462         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32463         -1,
  32464         -1,
  32465     },
  32466 #endif /* chips */
  32467 
  32468 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32469     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32470     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32471     defined(BCM_56260_B0)
  32472     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_8_BCM53400_A0r */
  32473         soc_block_list[61],
  32474         soc_iprocreg,
  32475         1,
  32476         0,
  32477         0x1804c308,
  32478         SOC_REG_FLAG_RO,
  32479         0,
  32480         2,
  32481         soc_USB2D_RECPACKFRAMNO_0_BCM53400_A0r_fields,
  32482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32483         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32484         -1,
  32485         -1,
  32486     },
  32487 #endif /* chips */
  32488 
  32489 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32490     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32491     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32492     defined(BCM_56260_B0)
  32493     { /* SOC_REG_INT_USB2D_RECPACKFRAMNO_9_BCM53400_A0r */
  32494         soc_block_list[61],
  32495         soc_iprocreg,
  32496         1,
  32497         0,
  32498         0x1804c328,
  32499         SOC_REG_FLAG_RO,
  32500         0,
  32501         2,
  32502         soc_USB2D_RECPACKFRAMNO_0_BCM53400_A0r_fields,
  32503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32504         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  32505         -1,
  32506         -1,
  32507     },
  32508 #endif /* chips */
  32509 
  32510 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32511     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32512     { /* SOC_REG_INT_USB2D_RELEASE_NUMBERr */
  32513         soc_block_list[61],
  32514         soc_iprocreg,
  32515         1,
  32516         0,
  32517         0x18042420,
  32518         SOC_REG_FLAG_RO,
  32519         0,
  32520         1,
  32521         soc_USB2D_RELEASE_NUMBERr_fields,
  32522         SOC_RESET_VAL_DEC(0x3234352a, 0x00000000)
  32523         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32524         -1,
  32525         -1,
  32526     },
  32527 #endif /* chips */
  32528 
  32529 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32530     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32531     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32532     defined(BCM_56260_B0)
  32533     { /* SOC_REG_INT_USB2D_RELEASE_NUMBER_BCM53400_A0r */
  32534         soc_block_list[61],
  32535         soc_iprocreg,
  32536         1,
  32537         0,
  32538         0x1804c420,
  32539         SOC_REG_FLAG_RO,
  32540         0,
  32541         1,
  32542         soc_USB2D_RELEASE_NUMBER_BCM53400_A0r_fields,
  32543         SOC_RESET_VAL_DEC(0x3234352a, 0x00000000)
  32544         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32545         -1,
  32546         -1,
  32547     },
  32548 #endif /* chips */
  32549 
  32550 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32551     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32552     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT0r */
  32553         soc_block_list[61],
  32554         soc_iprocreg,
  32555         1,
  32556         0,
  32557         0x18042504,
  32558         0,
  32559         0,
  32560         7,
  32561         soc_USB2D_UDC20_ENDPOINT0r_fields,
  32562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32563         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32564         -1,
  32565         -1,
  32566     },
  32567 #endif /* chips */
  32568 
  32569 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32570     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32571     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT1r */
  32572         soc_block_list[61],
  32573         soc_iprocreg,
  32574         1,
  32575         0,
  32576         0x18042508,
  32577         0,
  32578         0,
  32579         7,
  32580         soc_USB2D_UDC20_ENDPOINT0r_fields,
  32581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32582         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32583         -1,
  32584         -1,
  32585     },
  32586 #endif /* chips */
  32587 
  32588 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32589     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32590     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT2r */
  32591         soc_block_list[61],
  32592         soc_iprocreg,
  32593         1,
  32594         0,
  32595         0x1804250c,
  32596         0,
  32597         0,
  32598         7,
  32599         soc_USB2D_UDC20_ENDPOINT0r_fields,
  32600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32601         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32602         -1,
  32603         -1,
  32604     },
  32605 #endif /* chips */
  32606 
  32607 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32608     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32609     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT3r */
  32610         soc_block_list[61],
  32611         soc_iprocreg,
  32612         1,
  32613         0,
  32614         0x18042510,
  32615         0,
  32616         0,
  32617         7,
  32618         soc_USB2D_UDC20_ENDPOINT0r_fields,
  32619         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32620         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32621         -1,
  32622         -1,
  32623     },
  32624 #endif /* chips */
  32625 
  32626 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32627     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32628     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT4r */
  32629         soc_block_list[61],
  32630         soc_iprocreg,
  32631         1,
  32632         0,
  32633         0x18042514,
  32634         0,
  32635         0,
  32636         7,
  32637         soc_USB2D_UDC20_ENDPOINT0r_fields,
  32638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32639         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32640         -1,
  32641         -1,
  32642     },
  32643 #endif /* chips */
  32644 
  32645 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32646     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32647     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT5r */
  32648         soc_block_list[61],
  32649         soc_iprocreg,
  32650         1,
  32651         0,
  32652         0x18042518,
  32653         0,
  32654         0,
  32655         7,
  32656         soc_USB2D_UDC20_ENDPOINT0r_fields,
  32657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32658         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32659         -1,
  32660         -1,
  32661     },
  32662 #endif /* chips */
  32663 
  32664 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32665     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32666     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT6r */
  32667         soc_block_list[61],
  32668         soc_iprocreg,
  32669         1,
  32670         0,
  32671         0x1804251c,
  32672         0,
  32673         0,
  32674         7,
  32675         soc_USB2D_UDC20_ENDPOINT0r_fields,
  32676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32677         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32678         -1,
  32679         -1,
  32680     },
  32681 #endif /* chips */
  32682 
  32683 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32684     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32685     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT7r */
  32686         soc_block_list[61],
  32687         soc_iprocreg,
  32688         1,
  32689         0,
  32690         0x18042520,
  32691         0,
  32692         0,
  32693         7,
  32694         soc_USB2D_UDC20_ENDPOINT0r_fields,
  32695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32696         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32697         -1,
  32698         -1,
  32699     },
  32700 #endif /* chips */
  32701 
  32702 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32703     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32704     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT8r */
  32705         soc_block_list[61],
  32706         soc_iprocreg,
  32707         1,
  32708         0,
  32709         0x18042524,
  32710         0,
  32711         0,
  32712         7,
  32713         soc_USB2D_UDC20_ENDPOINT0r_fields,
  32714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32715         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32716         -1,
  32717         -1,
  32718     },
  32719 #endif /* chips */
  32720 
  32721 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32722     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32723     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT9r */
  32724         soc_block_list[61],
  32725         soc_iprocreg,
  32726         1,
  32727         0,
  32728         0x18042528,
  32729         0,
  32730         0,
  32731         7,
  32732         soc_USB2D_UDC20_ENDPOINT0r_fields,
  32733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32734         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32735         -1,
  32736         -1,
  32737     },
  32738 #endif /* chips */
  32739 
  32740 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32741     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32742     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32743     defined(BCM_56260_B0)
  32744     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT0_BCM53400_A0r */
  32745         soc_block_list[61],
  32746         soc_iprocreg,
  32747         1,
  32748         0,
  32749         0x1804c504,
  32750         0,
  32751         0,
  32752         7,
  32753         soc_USB2D_UDC20_ENDPOINT0_BCM53400_A0r_fields,
  32754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32755         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32756         -1,
  32757         -1,
  32758     },
  32759 #endif /* chips */
  32760 
  32761 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32762     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32763     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32764     defined(BCM_56260_B0)
  32765     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT1_BCM53400_A0r */
  32766         soc_block_list[61],
  32767         soc_iprocreg,
  32768         1,
  32769         0,
  32770         0x1804c508,
  32771         0,
  32772         0,
  32773         7,
  32774         soc_USB2D_UDC20_ENDPOINT0_BCM53400_A0r_fields,
  32775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32776         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32777         -1,
  32778         -1,
  32779     },
  32780 #endif /* chips */
  32781 
  32782 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32783     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32784     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32785     defined(BCM_56260_B0)
  32786     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT2_BCM53400_A0r */
  32787         soc_block_list[61],
  32788         soc_iprocreg,
  32789         1,
  32790         0,
  32791         0x1804c50c,
  32792         0,
  32793         0,
  32794         7,
  32795         soc_USB2D_UDC20_ENDPOINT0_BCM53400_A0r_fields,
  32796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32797         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32798         -1,
  32799         -1,
  32800     },
  32801 #endif /* chips */
  32802 
  32803 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32804     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32805     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32806     defined(BCM_56260_B0)
  32807     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT3_BCM53400_A0r */
  32808         soc_block_list[61],
  32809         soc_iprocreg,
  32810         1,
  32811         0,
  32812         0x1804c510,
  32813         0,
  32814         0,
  32815         7,
  32816         soc_USB2D_UDC20_ENDPOINT0_BCM53400_A0r_fields,
  32817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32818         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32819         -1,
  32820         -1,
  32821     },
  32822 #endif /* chips */
  32823 
  32824 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32825     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32826     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32827     defined(BCM_56260_B0)
  32828     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT4_BCM53400_A0r */
  32829         soc_block_list[61],
  32830         soc_iprocreg,
  32831         1,
  32832         0,
  32833         0x1804c514,
  32834         0,
  32835         0,
  32836         7,
  32837         soc_USB2D_UDC20_ENDPOINT0_BCM53400_A0r_fields,
  32838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32839         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32840         -1,
  32841         -1,
  32842     },
  32843 #endif /* chips */
  32844 
  32845 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32846     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32847     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32848     defined(BCM_56260_B0)
  32849     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT5_BCM53400_A0r */
  32850         soc_block_list[61],
  32851         soc_iprocreg,
  32852         1,
  32853         0,
  32854         0x1804c518,
  32855         0,
  32856         0,
  32857         7,
  32858         soc_USB2D_UDC20_ENDPOINT0_BCM53400_A0r_fields,
  32859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32860         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32861         -1,
  32862         -1,
  32863     },
  32864 #endif /* chips */
  32865 
  32866 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32867     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32868     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32869     defined(BCM_56260_B0)
  32870     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT6_BCM53400_A0r */
  32871         soc_block_list[61],
  32872         soc_iprocreg,
  32873         1,
  32874         0,
  32875         0x1804c51c,
  32876         0,
  32877         0,
  32878         7,
  32879         soc_USB2D_UDC20_ENDPOINT0_BCM53400_A0r_fields,
  32880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32881         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32882         -1,
  32883         -1,
  32884     },
  32885 #endif /* chips */
  32886 
  32887 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32888     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32889     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32890     defined(BCM_56260_B0)
  32891     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT7_BCM53400_A0r */
  32892         soc_block_list[61],
  32893         soc_iprocreg,
  32894         1,
  32895         0,
  32896         0x1804c520,
  32897         0,
  32898         0,
  32899         7,
  32900         soc_USB2D_UDC20_ENDPOINT0_BCM53400_A0r_fields,
  32901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32902         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32903         -1,
  32904         -1,
  32905     },
  32906 #endif /* chips */
  32907 
  32908 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32909     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32910     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32911     defined(BCM_56260_B0)
  32912     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT8_BCM53400_A0r */
  32913         soc_block_list[61],
  32914         soc_iprocreg,
  32915         1,
  32916         0,
  32917         0x1804c524,
  32918         0,
  32919         0,
  32920         7,
  32921         soc_USB2D_UDC20_ENDPOINT0_BCM53400_A0r_fields,
  32922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32923         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32924         -1,
  32925         -1,
  32926     },
  32927 #endif /* chips */
  32928 
  32929 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32930     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32931     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32932     defined(BCM_56260_B0)
  32933     { /* SOC_REG_INT_USB2D_UDC20_ENDPOINT9_BCM53400_A0r */
  32934         soc_block_list[61],
  32935         soc_iprocreg,
  32936         1,
  32937         0,
  32938         0x1804c528,
  32939         0,
  32940         0,
  32941         7,
  32942         soc_USB2D_UDC20_ENDPOINT0_BCM53400_A0r_fields,
  32943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32944         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  32945         -1,
  32946         -1,
  32947     },
  32948 #endif /* chips */
  32949 
  32950 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32951     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32952     { /* SOC_REG_INT_USB2_IDM_IDM_INTERRUPT_STATUSr */
  32953         soc_block_list[61],
  32954         soc_iprocreg,
  32955         1,
  32956         0,
  32957         0x18115a00,
  32958         SOC_REG_FLAG_RO,
  32959         0,
  32960         3,
  32961         soc_A9JTAG_M0_IDM_IDM_INTERRUPT_STATUS_BCM56450_A0r_fields,
  32962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32964         -1,
  32965         -1,
  32966     },
  32967 #endif /* chips */
  32968 
  32969 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32970     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32971     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32972     defined(BCM_56260_B0) || defined(BCM_56270_A0) || \
  32973     defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  32974     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  32975     { /* SOC_REG_INT_USB2_IDM_IDM_INTERRUPT_STATUS_BCM53400_A0r */
  32976         soc_block_list[61],
  32977         soc_iprocreg,
  32978         1,
  32979         0,
  32980         0x18115a00,
  32981         SOC_REG_FLAG_RO,
  32982         0,
  32983         3,
  32984         soc_A9JTAG_M0_IDM_IDM_INTERRUPT_STATUS_BCM53400_A0r_fields,
  32985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32986         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32987         -1,
  32988         -1,
  32989     },
  32990 #endif /* chips */
  32991 
  32992 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  32993     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  32994     { /* SOC_REG_INT_USB2_IDM_IDM_IO_CONTROL_DIRECTr */
  32995         soc_block_list[61],
  32996         soc_iprocreg,
  32997         1,
  32998         0,
  32999         0x18115408,
  33000         0,
  33001         0,
  33002         6,
  33003         soc_USB2_IDM_IDM_IO_CONTROL_DIRECTr_fields,
  33004         SOC_RESET_VAL_DEC(0x000003fc, 0x00000000)
  33005         SOC_RESET_MASK_DEC(0x000073fd, 0x00000000)
  33006         -1,
  33007         -1,
  33008     },
  33009 #endif /* chips */
  33010 
  33011 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  33012     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  33013     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  33014     defined(BCM_56260_B0)
  33015     { /* SOC_REG_INT_USB2_IDM_IDM_IO_CONTROL_DIRECT_BCM53400_A0r */
  33016         soc_block_list[61],
  33017         soc_iprocreg,
  33018         1,
  33019         0,
  33020         0x18115408,
  33021         0,
  33022         0,
  33023         11,
  33024         soc_USB2_IDM_IDM_IO_CONTROL_DIRECT_BCM53400_A0r_fields,
  33025         SOC_RESET_VAL_DEC(0x03de0000, 0x00000000)
  33026         SOC_RESET_MASK_DEC(0x37fef3fd, 0x00000000)
  33027         -1,
  33028         -1,
  33029     },
  33030 #endif /* chips */
  33031 
  33032 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  33033     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  33034     { /* SOC_REG_INT_USB2_IDM_IDM_IO_STATUSr */
  33035         soc_block_list[61],
  33036         soc_iprocreg,
  33037         1,
  33038         0,
  33039         0x18115500,
  33040         SOC_REG_FLAG_RO,
  33041         0,
  33042         1,
  33043         soc_USB2_IDM_IDM_IO_STATUSr_fields,
  33044         SOC_RESET_VAL_DEC(0x00000044, 0x00000000)
  33045         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33046         -1,
  33047         -1,
  33048     },
  33049 #endif /* chips */
  33050 
  33051 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  33052     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  33053     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  33054     defined(BCM_56260_B0)
  33055     { /* SOC_REG_INT_USB2_IDM_IDM_IO_STATUS_BCM53400_A0r */
  33056         soc_block_list[61],
  33057         soc_iprocreg,
  33058         1,
  33059         0,
  33060         0x18115500,
  33061         SOC_REG_FLAG_RO,
  33062         0,
  33063         1,
  33064         soc_USB2_IDM_IDM_IO_STATUS_BCM53400_A0r_fields,
  33065         SOC_RESET_VAL_DEC(0x00000044, 0x00000000)
  33066         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33067         -1,
  33068         -1,
  33069     },
  33070 #endif /* chips */
  33071 
  33072 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  33073     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  33074     { /* SOC_REG_INT_USB2_IDM_IDM_RESET_CONTROLr */
  33075         soc_block_list[61],
  33076         soc_iprocreg,
  33077         1,
  33078         0,
  33079         0x18115800,
  33080         0,
  33081         0,
  33082         2,
  33083         soc_AMAC_IDM0_IDM_RESET_CONTROLr_fields,
  33084         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33085         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33086         -1,
  33087         -1,
  33088     },
  33089 #endif /* chips */
  33090 
  33091 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  33092     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  33093     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  33094     defined(BCM_56260_B0)
  33095     { /* SOC_REG_INT_USB2_IDM_IDM_RESET_CONTROL_BCM53400_A0r */
  33096         soc_block_list[61],
  33097         soc_iprocreg,
  33098         1,
  33099         0,
  33100         0x18115800,
  33101         0,
  33102         0,
  33103         2,
  33104         soc_AMAC_IDM0_IDM_RESET_CONTROL_BCM53400_A0r_fields,
  33105         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33106         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33107         -1,
  33108         -1,
  33109     },
  33110 #endif /* chips */
  33111 
  33112 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  33113     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  33114     { /* SOC_REG_INT_USB2_IDM_IDM_RESET_STATUSr */
  33115         soc_block_list[61],
  33116         soc_iprocreg,
  33117         1,
  33118         0,
  33119         0x18115804,
  33120         SOC_REG_FLAG_RO,
  33121         0,
  33122         5,
  33123         soc_A9JTAG_M0_IDM_IDM_RESET_STATUS_BCM56450_A0r_fields,
  33124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33125         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33126         -1,
  33127         -1,
  33128     },
  33129 #endif /* chips */
  33130 
  33131 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  33132     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  33133     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  33134     defined(BCM_56260_B0) || defined(BCM_56270_A0) || \
  33135     defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  33136     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  33137     { /* SOC_REG_INT_USB2_IDM_IDM_RESET_STATUS_BCM53400_A0r */
  33138         soc_block_list[61],
  33139         soc_iprocreg,
  33140         1,
  33141         0,
  33142         0x18115804,
  33143         SOC_REG_FLAG_RO,
  33144         0,
  33145         5,
  33146         soc_A9JTAG_M0_IDM_IDM_RESET_STATUS_BCM53400_A0r_fields,
  33147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33148         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33149         -1,
  33150         -1,
  33151     },
  33152 #endif /* chips */
  33153 
  33154 #if defined(BCM_56370_A0)
  33155     { /* SOC_REG_INT_USBD_BDC_AIUDMAr */
  33156         soc_block_list[61],
  33157         soc_iprocreg,
  33158         1,
  33159         0,
  33160         0x10242c34,
  33161         0,
  33162         0,
  33163         5,
  33164         soc_USBD_BDC_AIUDMAr_fields,
  33165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33166         SOC_RESET_MASK_DEC(0x0f0fffff, 0x00000000)
  33167         -1,
  33168         -1,
  33169         3,
  33170     },
  33171 #endif /* chips */
  33172 
  33173 #if defined(BCM_56370_A0)
  33174     { /* SOC_REG_INT_USBD_BDC_AIUIEPS0r */
  33175         soc_block_list[61],
  33176         soc_iprocreg,
  33177         1,
  33178         0,
  33179         0x10242c80,
  33180         0,
  33181         0,
  33182         9,
  33183         soc_USBD_BDC_AIUIEPS0r_fields,
  33184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33185         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33186         -1,
  33187         -1,
  33188         3,
  33189     },
  33190 #endif /* chips */
  33191 
  33192 #if defined(BCM_56370_A0)
  33193     { /* SOC_REG_INT_USBD_BDC_AIUIEPS1r */
  33194         soc_block_list[61],
  33195         soc_iprocreg,
  33196         1,
  33197         0,
  33198         0x10242c84,
  33199         0,
  33200         0,
  33201         9,
  33202         soc_USBD_BDC_AIUIEPS0r_fields,
  33203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33204         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33205         -1,
  33206         -1,
  33207         3,
  33208     },
  33209 #endif /* chips */
  33210 
  33211 #if defined(BCM_56370_A0)
  33212     { /* SOC_REG_INT_USBD_BDC_AIUIEPS2r */
  33213         soc_block_list[61],
  33214         soc_iprocreg,
  33215         1,
  33216         0,
  33217         0x10242c88,
  33218         0,
  33219         0,
  33220         9,
  33221         soc_USBD_BDC_AIUIEPS0r_fields,
  33222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33223         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33224         -1,
  33225         -1,
  33226         3,
  33227     },
  33228 #endif /* chips */
  33229 
  33230 #if defined(BCM_56370_A0)
  33231     { /* SOC_REG_INT_USBD_BDC_AIUIEPS3r */
  33232         soc_block_list[61],
  33233         soc_iprocreg,
  33234         1,
  33235         0,
  33236         0x10242c8c,
  33237         0,
  33238         0,
  33239         9,
  33240         soc_USBD_BDC_AIUIEPS0r_fields,
  33241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33242         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33243         -1,
  33244         -1,
  33245         3,
  33246     },
  33247 #endif /* chips */
  33248 
  33249 #if defined(BCM_56370_A0)
  33250     { /* SOC_REG_INT_USBD_BDC_AIUIEPS4r */
  33251         soc_block_list[61],
  33252         soc_iprocreg,
  33253         1,
  33254         0,
  33255         0x10242c90,
  33256         0,
  33257         0,
  33258         9,
  33259         soc_USBD_BDC_AIUIEPS0r_fields,
  33260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33261         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33262         -1,
  33263         -1,
  33264         3,
  33265     },
  33266 #endif /* chips */
  33267 
  33268 #if defined(BCM_56370_A0)
  33269     { /* SOC_REG_INT_USBD_BDC_AIUIEPS5r */
  33270         soc_block_list[61],
  33271         soc_iprocreg,
  33272         1,
  33273         0,
  33274         0x10242c94,
  33275         0,
  33276         0,
  33277         9,
  33278         soc_USBD_BDC_AIUIEPS0r_fields,
  33279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33280         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33281         -1,
  33282         -1,
  33283         3,
  33284     },
  33285 #endif /* chips */
  33286 
  33287 #if defined(BCM_56370_A0)
  33288     { /* SOC_REG_INT_USBD_BDC_AIUOEPS0r */
  33289         soc_block_list[61],
  33290         soc_iprocreg,
  33291         1,
  33292         0,
  33293         0x10242c40,
  33294         0,
  33295         0,
  33296         9,
  33297         soc_USBD_BDC_AIUIEPS0r_fields,
  33298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33299         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33300         -1,
  33301         -1,
  33302         3,
  33303     },
  33304 #endif /* chips */
  33305 
  33306 #if defined(BCM_56370_A0)
  33307     { /* SOC_REG_INT_USBD_BDC_AIUOEPS1r */
  33308         soc_block_list[61],
  33309         soc_iprocreg,
  33310         1,
  33311         0,
  33312         0x10242c44,
  33313         0,
  33314         0,
  33315         9,
  33316         soc_USBD_BDC_AIUIEPS0r_fields,
  33317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33318         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33319         -1,
  33320         -1,
  33321         3,
  33322     },
  33323 #endif /* chips */
  33324 
  33325 #if defined(BCM_56370_A0)
  33326     { /* SOC_REG_INT_USBD_BDC_AIUOEPS3r */
  33327         soc_block_list[61],
  33328         soc_iprocreg,
  33329         1,
  33330         0,
  33331         0x10242c4c,
  33332         0,
  33333         0,
  33334         9,
  33335         soc_USBD_BDC_AIUIEPS0r_fields,
  33336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33337         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33338         -1,
  33339         -1,
  33340         3,
  33341     },
  33342 #endif /* chips */
  33343 
  33344 #if defined(BCM_56370_A0)
  33345     { /* SOC_REG_INT_USBD_BDC_AIUOEPS4r */
  33346         soc_block_list[61],
  33347         soc_iprocreg,
  33348         1,
  33349         0,
  33350         0x10242c50,
  33351         0,
  33352         0,
  33353         9,
  33354         soc_USBD_BDC_AIUIEPS0r_fields,
  33355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33356         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33357         -1,
  33358         -1,
  33359         3,
  33360     },
  33361 #endif /* chips */
  33362 
  33363 #if defined(BCM_56370_A0)
  33364     { /* SOC_REG_INT_USBD_BDC_AIUOEPS5r */
  33365         soc_block_list[61],
  33366         soc_iprocreg,
  33367         1,
  33368         0,
  33369         0x10242c54,
  33370         0,
  33371         0,
  33372         9,
  33373         soc_USBD_BDC_AIUIEPS0r_fields,
  33374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33375         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33376         -1,
  33377         -1,
  33378         3,
  33379     },
  33380 #endif /* chips */
  33381 
  33382 #if defined(BCM_56370_A0)
  33383     { /* SOC_REG_INT_USBD_BDC_AIUOPS2r */
  33384         soc_block_list[61],
  33385         soc_iprocreg,
  33386         1,
  33387         0,
  33388         0x10242c48,
  33389         0,
  33390         0,
  33391         9,
  33392         soc_USBD_BDC_AIUIEPS0r_fields,
  33393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33394         SOC_RESET_MASK_DEC(0xf800ffff, 0x00000000)
  33395         -1,
  33396         -1,
  33397         3,
  33398     },
  33399 #endif /* chips */
  33400 
  33401 #if defined(BCM_56370_A0)
  33402     { /* SOC_REG_INT_USBD_BDC_AXILPMr */
  33403         soc_block_list[61],
  33404         soc_iprocreg,
  33405         1,
  33406         0,
  33407         0x10242c10,
  33408         0,
  33409         0,
  33410         3,
  33411         soc_USBD_BDC_AXILPMr_fields,
  33412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33413         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33414         -1,
  33415         -1,
  33416         3,
  33417     },
  33418 #endif /* chips */
  33419 
  33420 #if defined(BCM_56370_A0)
  33421     { /* SOC_REG_INT_USBD_BDC_AXIQOSr */
  33422         soc_block_list[61],
  33423         soc_iprocreg,
  33424         1,
  33425         0,
  33426         0x10242c14,
  33427         0,
  33428         0,
  33429         8,
  33430         soc_USBD_BDC_AXIQOSr_fields,
  33431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33433         -1,
  33434         -1,
  33435         3,
  33436     },
  33437 #endif /* chips */
  33438 
  33439 #if defined(BCM_56370_A0)
  33440     { /* SOC_REG_INT_USBD_BDC_AXIRDAr */
  33441         soc_block_list[61],
  33442         soc_iprocreg,
  33443         1,
  33444         0,
  33445         0x10242c0c,
  33446         0,
  33447         0,
  33448         5,
  33449         soc_USBD_BDC_AXIRDAr_fields,
  33450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33451         SOC_RESET_MASK_DEC(0xf9ffffff, 0x00000000)
  33452         -1,
  33453         -1,
  33454         3,
  33455     },
  33456 #endif /* chips */
  33457 
  33458 #if defined(BCM_56370_A0)
  33459     { /* SOC_REG_INT_USBD_BDC_AXIWRAr */
  33460         soc_block_list[61],
  33461         soc_iprocreg,
  33462         1,
  33463         0,
  33464         0x10242c08,
  33465         0,
  33466         0,
  33467         5,
  33468         soc_USBD_BDC_AXIWRAr_fields,
  33469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33470         SOC_RESET_MASK_DEC(0xf9ffffff, 0x00000000)
  33471         -1,
  33472         -1,
  33473         3,
  33474     },
  33475 #endif /* chips */
  33476 
  33477 #if defined(BCM_56370_A0)
  33478     { /* SOC_REG_INT_USBD_BDC_BDCCAP0r */
  33479         soc_block_list[61],
  33480         soc_iprocreg,
  33481         1,
  33482         0,
  33483         0x10242008,
  33484         SOC_REG_FLAG_RO,
  33485         0,
  33486         3,
  33487         soc_USBD_BDC_BDCCAP0r_fields,
  33488         SOC_RESET_VAL_DEC(0x03e80300, 0x00000000)
  33489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33490         -1,
  33491         -1,
  33492         3,
  33493     },
  33494 #endif /* chips */
  33495 
  33496 #if defined(BCM_56370_A0)
  33497     { /* SOC_REG_INT_USBD_BDC_BDCCAP1r */
  33498         soc_block_list[61],
  33499         soc_iprocreg,
  33500         1,
  33501         0,
  33502         0x1024200c,
  33503         SOC_REG_FLAG_RO,
  33504         0,
  33505         9,
  33506         soc_USBD_BDC_BDCCAP1r_fields,
  33507         SOC_RESET_VAL_DEC(0xc80000bc, 0x00000000)
  33508         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33509         -1,
  33510         -1,
  33511         3,
  33512     },
  33513 #endif /* chips */
  33514 
  33515 #if defined(BCM_56370_A0)
  33516     { /* SOC_REG_INT_USBD_BDC_BDCCFG0r */
  33517         soc_block_list[61],
  33518         soc_iprocreg,
  33519         1,
  33520         0,
  33521         0x10242000,
  33522         SOC_REG_FLAG_RO,
  33523         0,
  33524         6,
  33525         soc_USBD_BDC_BDCCFG0r_fields,
  33526         SOC_RESET_VAL_DEC(0x00091a06, 0x00000000)
  33527         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33528         -1,
  33529         -1,
  33530         3,
  33531     },
  33532 #endif /* chips */
  33533 
  33534 #if defined(BCM_56370_A0)
  33535     { /* SOC_REG_INT_USBD_BDC_BDCCFG1r */
  33536         soc_block_list[61],
  33537         soc_iprocreg,
  33538         1,
  33539         0,
  33540         0x10242004,
  33541         SOC_REG_FLAG_RO,
  33542         0,
  33543         3,
  33544         soc_USBD_BDC_BDCCFG1r_fields,
  33545         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  33546         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33547         -1,
  33548         -1,
  33549         3,
  33550     },
  33551 #endif /* chips */
  33552 
  33553 #if defined(BCM_56370_A0)
  33554     { /* SOC_REG_INT_USBD_BDC_BDCSCr */
  33555         soc_block_list[61],
  33556         soc_iprocreg,
  33557         1,
  33558         0,
  33559         0x10242040,
  33560         0,
  33561         0,
  33562         19,
  33563         soc_USBD_BDC_BDCSCr_fields,
  33564         SOC_RESET_VAL_DEC(0x00900000, 0x00000000)
  33565         SOC_RESET_MASK_DEC(0xf0f77fff, 0x00000000)
  33566         -1,
  33567         -1,
  33568         3,
  33569     },
  33570 #endif /* chips */
  33571 
  33572 #if defined(BCM_56370_A0)
  33573     { /* SOC_REG_INT_USBD_BDC_BIUSPCr */
  33574         soc_block_list[61],
  33575         soc_iprocreg,
  33576         1,
  33577         0,
  33578         0x10242c04,
  33579         SOC_REG_FLAG_RO,
  33580         0,
  33581         6,
  33582         soc_USBD_BDC_BIUSPCr_fields,
  33583         SOC_RESET_VAL_DEC(0x01000010, 0x00000000)
  33584         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33585         -1,
  33586         -1,
  33587         3,
  33588     },
  33589 #endif /* chips */
  33590 
  33591 #if defined(BCM_56370_A0)
  33592     { /* SOC_REG_INT_USBD_BDC_CMDPAR0r */
  33593         soc_block_list[61],
  33594         soc_iprocreg,
  33595         1,
  33596         0,
  33597         0x10242010,
  33598         0,
  33599         0,
  33600         1,
  33601         soc_USBD_BDC_CMDPAR0r_fields,
  33602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33603         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33604         -1,
  33605         -1,
  33606         3,
  33607     },
  33608 #endif /* chips */
  33609 
  33610 #if defined(BCM_56370_A0)
  33611     { /* SOC_REG_INT_USBD_BDC_CMDPAR1r */
  33612         soc_block_list[61],
  33613         soc_iprocreg,
  33614         1,
  33615         0,
  33616         0x10242014,
  33617         0,
  33618         0,
  33619         1,
  33620         soc_USBD_BDC_CMDPAR0r_fields,
  33621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33622         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33623         -1,
  33624         -1,
  33625         3,
  33626     },
  33627 #endif /* chips */
  33628 
  33629 #if defined(BCM_56370_A0)
  33630     { /* SOC_REG_INT_USBD_BDC_CMDPAR2r */
  33631         soc_block_list[61],
  33632         soc_iprocreg,
  33633         1,
  33634         0,
  33635         0x10242018,
  33636         0,
  33637         0,
  33638         1,
  33639         soc_USBD_BDC_CMDPAR0r_fields,
  33640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33641         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33642         -1,
  33643         -1,
  33644         3,
  33645     },
  33646 #endif /* chips */
  33647 
  33648 #if defined(BCM_56370_A0)
  33649     { /* SOC_REG_INT_USBD_BDC_CMDSCr */
  33650         soc_block_list[61],
  33651         soc_iprocreg,
  33652         1,
  33653         0,
  33654         0x1024201c,
  33655         0,
  33656         0,
  33657         10,
  33658         soc_USBD_BDC_CMDSCr_fields,
  33659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33660         SOC_RESET_MASK_DEC(0xf9ffffff, 0x00000000)
  33661         -1,
  33662         -1,
  33663         3,
  33664     },
  33665 #endif /* chips */
  33666 
  33667 #if defined(BCM_56370_A0)
  33668     { /* SOC_REG_INT_USBD_BDC_CSRSPCr */
  33669         soc_block_list[61],
  33670         soc_iprocreg,
  33671         1,
  33672         0,
  33673         0x10242c24,
  33674         SOC_REG_FLAG_RO,
  33675         0,
  33676         5,
  33677         soc_USBD_BDC_CSRSPCr_fields,
  33678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33680         -1,
  33681         -1,
  33682         3,
  33683     },
  33684 #endif /* chips */
  33685 
  33686 #if defined(BCM_56370_A0)
  33687     { /* SOC_REG_INT_USBD_BDC_DVCNPHr */
  33688         soc_block_list[61],
  33689         soc_iprocreg,
  33690         1,
  33691         0,
  33692         0x10242fac,
  33693         SOC_REG_FLAG_RO,
  33694         0,
  33695         1,
  33696         soc_USBD_BDC_DVCNPHr_fields,
  33697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33698         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33699         -1,
  33700         -1,
  33701         3,
  33702     },
  33703 #endif /* chips */
  33704 
  33705 #if defined(BCM_56370_A0)
  33706     { /* SOC_REG_INT_USBD_BDC_DVCNPLr */
  33707         soc_block_list[61],
  33708         soc_iprocreg,
  33709         1,
  33710         0,
  33711         0x10242fa8,
  33712         SOC_REG_FLAG_RO,
  33713         0,
  33714         1,
  33715         soc_USBD_BDC_DVCNPLr_fields,
  33716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33718         -1,
  33719         -1,
  33720         3,
  33721     },
  33722 #endif /* chips */
  33723 
  33724 #if defined(BCM_56370_A0)
  33725     { /* SOC_REG_INT_USBD_BDC_DVCSAr */
  33726         soc_block_list[61],
  33727         soc_iprocreg,
  33728         1,
  33729         0,
  33730         0x10242050,
  33731         0,
  33732         0,
  33733         3,
  33734         soc_USBD_BDC_DVCSAr_fields,
  33735         SOC_RESET_VAL_DEC(0xf8000000, 0x00000000)
  33736         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33737         -1,
  33738         -1,
  33739         3,
  33740     },
  33741 #endif /* chips */
  33742 
  33743 #if defined(BCM_56370_A0)
  33744     { /* SOC_REG_INT_USBD_BDC_DVCSBr */
  33745         soc_block_list[61],
  33746         soc_iprocreg,
  33747         1,
  33748         0,
  33749         0x10242054,
  33750         0,
  33751         0,
  33752         3,
  33753         soc_USBD_BDC_DVCSBr_fields,
  33754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33755         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  33756         -1,
  33757         -1,
  33758         3,
  33759     },
  33760 #endif /* chips */
  33761 
  33762 #if defined(BCM_56370_A0)
  33763     { /* SOC_REG_INT_USBD_BDC_DVCSCr */
  33764         soc_block_list[61],
  33765         soc_iprocreg,
  33766         1,
  33767         0,
  33768         0x10242058,
  33769         0,
  33770         0,
  33771         1,
  33772         soc_USBD_BDC_DVCSCr_fields,
  33773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33774         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33775         -1,
  33776         -1,
  33777         3,
  33778     },
  33779 #endif /* chips */
  33780 
  33781 #if defined(BCM_56370_A0)
  33782     { /* SOC_REG_INT_USBD_BDC_DVCSDr */
  33783         soc_block_list[61],
  33784         soc_iprocreg,
  33785         1,
  33786         0,
  33787         0x1024205c,
  33788         0,
  33789         0,
  33790         1,
  33791         soc_USBD_BDC_DVCSCr_fields,
  33792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33793         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33794         -1,
  33795         -1,
  33796         3,
  33797     },
  33798 #endif /* chips */
  33799 
  33800 #if defined(BCM_56370_A0)
  33801     { /* SOC_REG_INT_USBD_BDC_DVCSTPr */
  33802         soc_block_list[61],
  33803         soc_iprocreg,
  33804         1,
  33805         0,
  33806         0x10242fa4,
  33807         0,
  33808         0,
  33809         5,
  33810         soc_USBD_BDC_DVCSTPr_fields,
  33811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33812         SOC_RESET_MASK_DEC(0xefffffff, 0x00000000)
  33813         -1,
  33814         -1,
  33815         3,
  33816     },
  33817 #endif /* chips */
  33818 
  33819 #if defined(BCM_56370_A0)
  33820     { /* SOC_REG_INT_USBD_BDC_ECHAIUr */
  33821         soc_block_list[61],
  33822         soc_iprocreg,
  33823         1,
  33824         0,
  33825         0x10242c30,
  33826         0,
  33827         0,
  33828         6,
  33829         soc_USBD_BDC_ECHAIUr_fields,
  33830         SOC_RESET_VAL_DEC(0x400624c2, 0x00000000)
  33831         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33832         -1,
  33833         -1,
  33834         3,
  33835     },
  33836 #endif /* chips */
  33837 
  33838 #if defined(BCM_56370_A0)
  33839     { /* SOC_REG_INT_USBD_BDC_ECHBIUr */
  33840         soc_block_list[61],
  33841         soc_iprocreg,
  33842         1,
  33843         0,
  33844         0x10242c00,
  33845         SOC_REG_FLAG_RO,
  33846         0,
  33847         6,
  33848         soc_USBD_BDC_ECHBIUr_fields,
  33849         SOC_RESET_VAL_DEC(0x000008c0, 0x00000000)
  33850         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33851         -1,
  33852         -1,
  33853         3,
  33854     },
  33855 #endif /* chips */
  33856 
  33857 #if defined(BCM_56370_A0)
  33858     { /* SOC_REG_INT_USBD_BDC_ECHCSRr */
  33859         soc_block_list[61],
  33860         soc_iprocreg,
  33861         1,
  33862         0,
  33863         0x10242c20,
  33864         SOC_REG_FLAG_RO,
  33865         0,
  33866         4,
  33867         soc_USBD_BDC_ECHCSRr_fields,
  33868         SOC_RESET_VAL_DEC(0x000004c1, 0x00000000)
  33869         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33870         -1,
  33871         -1,
  33872         3,
  33873     },
  33874 #endif /* chips */
  33875 
  33876 #if defined(BCM_56370_A0)
  33877     { /* SOC_REG_INT_USBD_BDC_ECHDVCr */
  33878         soc_block_list[61],
  33879         soc_iprocreg,
  33880         1,
  33881         0,
  33882         0x10242fa0,
  33883         0,
  33884         0,
  33885         11,
  33886         soc_USBD_BDC_ECHDVCr_fields,
  33887         SOC_RESET_VAL_DEC(0x101804fd, 0x00000000)
  33888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33889         -1,
  33890         -1,
  33891         3,
  33892     },
  33893 #endif /* chips */
  33894 
  33895 #if defined(BCM_56370_A0)
  33896     { /* SOC_REG_INT_USBD_BDC_ECHFSCr */
  33897         soc_block_list[61],
  33898         soc_iprocreg,
  33899         1,
  33900         0,
  33901         0x10242cc0,
  33902         SOC_REG_FLAG_RO,
  33903         0,
  33904         7,
  33905         soc_USBD_BDC_ECHFSCr_fields,
  33906         SOC_RESET_VAL_DEC(0x000050c3, 0x00000000)
  33907         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33908         -1,
  33909         -1,
  33910         3,
  33911     },
  33912 #endif /* chips */
  33913 
  33914 #if defined(BCM_56370_A0)
  33915     { /* SOC_REG_INT_USBD_BDC_ECHIRAr */
  33916         soc_block_list[61],
  33917         soc_iprocreg,
  33918         1,
  33919         0,
  33920         0x10242f90,
  33921         SOC_REG_FLAG_RO,
  33922         0,
  33923         3,
  33924         soc_USBD_BDC_ECHIRAr_fields,
  33925         SOC_RESET_VAL_DEC(0x000004fe, 0x00000000)
  33926         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33927         -1,
  33928         -1,
  33929         3,
  33930     },
  33931 #endif /* chips */
  33932 
  33933 #if defined(BCM_56370_A0)
  33934     { /* SOC_REG_INT_USBD_BDC_ECHLNKr */
  33935         soc_block_list[61],
  33936         soc_iprocreg,
  33937         1,
  33938         0,
  33939         0x10242e10,
  33940         SOC_REG_FLAG_RO,
  33941         0,
  33942         4,
  33943         soc_USBD_BDC_ECHLNKr_fields,
  33944         SOC_RESET_VAL_DEC(0x000104bb, 0x00000000)
  33945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33946         -1,
  33947         -1,
  33948         3,
  33949     },
  33950 #endif /* chips */
  33951 
  33952 #if defined(BCM_56370_A0)
  33953     { /* SOC_REG_INT_USBD_BDC_ECHPHYr */
  33954         soc_block_list[61],
  33955         soc_iprocreg,
  33956         1,
  33957         0,
  33958         0x10242e20,
  33959         SOC_REG_FLAG_RO,
  33960         0,
  33961         3,
  33962         soc_USBD_BDC_ECHPHYr_fields,
  33963         SOC_RESET_VAL_DEC(0x000004c6, 0x00000000)
  33964         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33965         -1,
  33966         -1,
  33967         3,
  33968     },
  33969 #endif /* chips */
  33970 
  33971 #if defined(BCM_56370_A0)
  33972     { /* SOC_REG_INT_USBD_BDC_ECHPRTr */
  33973         soc_block_list[61],
  33974         soc_iprocreg,
  33975         1,
  33976         0,
  33977         0x10242e00,
  33978         SOC_REG_FLAG_RO,
  33979         0,
  33980         4,
  33981         soc_USBD_BDC_ECHPRTr_fields,
  33982         SOC_RESET_VAL_DEC(0x000104c4, 0x00000000)
  33983         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33984         -1,
  33985         -1,
  33986         3,
  33987     },
  33988 #endif /* chips */
  33989 
  33990 #if defined(BCM_56370_A0)
  33991     { /* SOC_REG_INT_USBD_BDC_ECHRBVr */
  33992         soc_block_list[61],
  33993         soc_iprocreg,
  33994         1,
  33995         0,
  33996         0x10242fb0,
  33997         SOC_REG_FLAG_RO,
  33998         0,
  33999         5,
  34000         soc_USBD_BDC_ECHRBVr_fields,
  34001         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  34002         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34003         -1,
  34004         -1,
  34005         3,
  34006     },
  34007 #endif /* chips */
  34008 
  34009 #if defined(BCM_56370_A0)
  34010     { /* SOC_REG_INT_USBD_BDC_ECHRSVr */
  34011         soc_block_list[61],
  34012         soc_iprocreg,
  34013         1,
  34014         0,
  34015         0x10242280,
  34016         SOC_REG_FLAG_RO,
  34017         0,
  34018         3,
  34019         soc_USBD_BDC_ECHRSVr_fields,
  34020         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  34021         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34022         -1,
  34023         -1,
  34024         3,
  34025     },
  34026 #endif /* chips */
  34027 
  34028 #if defined(BCM_56370_A0)
  34029     { /* SOC_REG_INT_USBD_BDC_ECHRSV2r */
  34030         soc_block_list[61],
  34031         soc_iprocreg,
  34032         1,
  34033         0,
  34034         0x10242e30,
  34035         SOC_REG_FLAG_RO,
  34036         0,
  34037         3,
  34038         soc_USBD_BDC_ECHRSVr_fields,
  34039         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  34040         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34041         -1,
  34042         -1,
  34043         3,
  34044     },
  34045 #endif /* chips */
  34046 
  34047 #if defined(BCM_56370_A0)
  34048     { /* SOC_REG_INT_USBD_BDC_EPS0r */
  34049         soc_block_list[61],
  34050         soc_iprocreg,
  34051         1,
  34052         0,
  34053         0x10242060,
  34054         0,
  34055         0,
  34056         2,
  34057         soc_USBD_BDC_EPS0r_fields,
  34058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34059         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34060         -1,
  34061         -1,
  34062         3,
  34063     },
  34064 #endif /* chips */
  34065 
  34066 #if defined(BCM_56370_A0)
  34067     { /* SOC_REG_INT_USBD_BDC_EPS1r */
  34068         soc_block_list[61],
  34069         soc_iprocreg,
  34070         1,
  34071         0,
  34072         0x10242064,
  34073         0,
  34074         0,
  34075         1,
  34076         soc_USBD_BDC_EPS1r_fields,
  34077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34078         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34079         -1,
  34080         -1,
  34081         3,
  34082     },
  34083 #endif /* chips */
  34084 
  34085 #if defined(BCM_56370_A0)
  34086     { /* SOC_REG_INT_USBD_BDC_EPS2r */
  34087         soc_block_list[61],
  34088         soc_iprocreg,
  34089         1,
  34090         0,
  34091         0x10242068,
  34092         0,
  34093         0,
  34094         8,
  34095         soc_USBD_BDC_EPS2r_fields,
  34096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34098         -1,
  34099         -1,
  34100         3,
  34101     },
  34102 #endif /* chips */
  34103 
  34104 #if defined(BCM_56370_A0)
  34105     { /* SOC_REG_INT_USBD_BDC_EPS3r */
  34106         soc_block_list[61],
  34107         soc_iprocreg,
  34108         1,
  34109         0,
  34110         0x1024206c,
  34111         0,
  34112         0,
  34113         4,
  34114         soc_USBD_BDC_EPS3r_fields,
  34115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34116         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34117         -1,
  34118         -1,
  34119         3,
  34120     },
  34121 #endif /* chips */
  34122 
  34123 #if defined(BCM_56370_A0)
  34124     { /* SOC_REG_INT_USBD_BDC_EPS4r */
  34125         soc_block_list[61],
  34126         soc_iprocreg,
  34127         1,
  34128         0,
  34129         0x10242070,
  34130         0,
  34131         0,
  34132         1,
  34133         soc_USBD_BDC_DVCSCr_fields,
  34134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34135         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34136         -1,
  34137         -1,
  34138         3,
  34139     },
  34140 #endif /* chips */
  34141 
  34142 #if defined(BCM_56370_A0)
  34143     { /* SOC_REG_INT_USBD_BDC_EPS5r */
  34144         soc_block_list[61],
  34145         soc_iprocreg,
  34146         1,
  34147         0,
  34148         0x10242074,
  34149         0,
  34150         0,
  34151         1,
  34152         soc_USBD_BDC_DVCSCr_fields,
  34153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34154         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34155         -1,
  34156         -1,
  34157         3,
  34158     },
  34159 #endif /* chips */
  34160 
  34161 #if defined(BCM_56370_A0)
  34162     { /* SOC_REG_INT_USBD_BDC_EPS6r */
  34163         soc_block_list[61],
  34164         soc_iprocreg,
  34165         1,
  34166         0,
  34167         0x10242078,
  34168         0,
  34169         0,
  34170         1,
  34171         soc_USBD_BDC_DVCSCr_fields,
  34172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34173         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34174         -1,
  34175         -1,
  34176         3,
  34177     },
  34178 #endif /* chips */
  34179 
  34180 #if defined(BCM_56370_A0)
  34181     { /* SOC_REG_INT_USBD_BDC_EPS7r */
  34182         soc_block_list[61],
  34183         soc_iprocreg,
  34184         1,
  34185         0,
  34186         0x1024207c,
  34187         0,
  34188         0,
  34189         1,
  34190         soc_USBD_BDC_DVCSCr_fields,
  34191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34192         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34193         -1,
  34194         -1,
  34195         3,
  34196     },
  34197 #endif /* chips */
  34198 
  34199 #if defined(BCM_56370_A0)
  34200     { /* SOC_REG_INT_USBD_BDC_EXCPBAr */
  34201         soc_block_list[61],
  34202         soc_iprocreg,
  34203         1,
  34204         0,
  34205         0x10242030,
  34206         SOC_REG_FLAG_RO,
  34207         0,
  34208         2,
  34209         soc_USBD_BDC_EXCPBAr_fields,
  34210         SOC_RESET_VAL_DEC(0x00000c00, 0x00000000)
  34211         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  34212         -1,
  34213         -1,
  34214         3,
  34215     },
  34216 #endif /* chips */
  34217 
  34218 #if defined(BCM_56370_A0)
  34219     { /* SOC_REG_INT_USBD_BDC_FSCHICr */
  34220         soc_block_list[61],
  34221         soc_iprocreg,
  34222         1,
  34223         0,
  34224         0x10242cec,
  34225         SOC_REG_FLAG_RO,
  34226         0,
  34227         6,
  34228         soc_USBD_BDC_FSCHICr_fields,
  34229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34230         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34231         -1,
  34232         -1,
  34233         3,
  34234     },
  34235 #endif /* chips */
  34236 
  34237 #if defined(BCM_56370_A0)
  34238     { /* SOC_REG_INT_USBD_BDC_FSCHOCr */
  34239         soc_block_list[61],
  34240         soc_iprocreg,
  34241         1,
  34242         0,
  34243         0x10242cdc,
  34244         SOC_REG_FLAG_RO,
  34245         0,
  34246         3,
  34247         soc_USBD_BDC_FSCHOCr_fields,
  34248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34249         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34250         -1,
  34251         -1,
  34252         3,
  34253     },
  34254 #endif /* chips */
  34255 
  34256 #if defined(BCM_56370_A0)
  34257     { /* SOC_REG_INT_USBD_BDC_FSCIBDC0r */
  34258         soc_block_list[61],
  34259         soc_iprocreg,
  34260         1,
  34261         0,
  34262         0x10242d80,
  34263         0,
  34264         0,
  34265         3,
  34266         soc_USBD_BDC_FSCIBDC0r_fields,
  34267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34268         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34269         -1,
  34270         -1,
  34271         3,
  34272     },
  34273 #endif /* chips */
  34274 
  34275 #if defined(BCM_56370_A0)
  34276     { /* SOC_REG_INT_USBD_BDC_FSCIBDC1r */
  34277         soc_block_list[61],
  34278         soc_iprocreg,
  34279         1,
  34280         0,
  34281         0x10242d84,
  34282         0,
  34283         0,
  34284         3,
  34285         soc_USBD_BDC_FSCIBDC0r_fields,
  34286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34287         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34288         -1,
  34289         -1,
  34290         3,
  34291     },
  34292 #endif /* chips */
  34293 
  34294 #if defined(BCM_56370_A0)
  34295     { /* SOC_REG_INT_USBD_BDC_FSCIBDC2r */
  34296         soc_block_list[61],
  34297         soc_iprocreg,
  34298         1,
  34299         0,
  34300         0x10242d88,
  34301         0,
  34302         0,
  34303         3,
  34304         soc_USBD_BDC_FSCIBDC0r_fields,
  34305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34306         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34307         -1,
  34308         -1,
  34309         3,
  34310     },
  34311 #endif /* chips */
  34312 
  34313 #if defined(BCM_56370_A0)
  34314     { /* SOC_REG_INT_USBD_BDC_FSCIBDC3r */
  34315         soc_block_list[61],
  34316         soc_iprocreg,
  34317         1,
  34318         0,
  34319         0x10242d8c,
  34320         0,
  34321         0,
  34322         3,
  34323         soc_USBD_BDC_FSCIBDC0r_fields,
  34324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34325         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34326         -1,
  34327         -1,
  34328         3,
  34329     },
  34330 #endif /* chips */
  34331 
  34332 #if defined(BCM_56370_A0)
  34333     { /* SOC_REG_INT_USBD_BDC_FSCIBDC4r */
  34334         soc_block_list[61],
  34335         soc_iprocreg,
  34336         1,
  34337         0,
  34338         0x10242d90,
  34339         0,
  34340         0,
  34341         3,
  34342         soc_USBD_BDC_FSCIBDC0r_fields,
  34343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34344         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34345         -1,
  34346         -1,
  34347         3,
  34348     },
  34349 #endif /* chips */
  34350 
  34351 #if defined(BCM_56370_A0)
  34352     { /* SOC_REG_INT_USBD_BDC_FSCIBDC5r */
  34353         soc_block_list[61],
  34354         soc_iprocreg,
  34355         1,
  34356         0,
  34357         0x10242d94,
  34358         0,
  34359         0,
  34360         3,
  34361         soc_USBD_BDC_FSCIBDC0r_fields,
  34362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34363         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34364         -1,
  34365         -1,
  34366         3,
  34367     },
  34368 #endif /* chips */
  34369 
  34370 #if defined(BCM_56370_A0)
  34371     { /* SOC_REG_INT_USBD_BDC_FSCIBDC6r */
  34372         soc_block_list[61],
  34373         soc_iprocreg,
  34374         1,
  34375         0,
  34376         0x10242d98,
  34377         0,
  34378         0,
  34379         3,
  34380         soc_USBD_BDC_FSCIBDC0r_fields,
  34381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34382         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34383         -1,
  34384         -1,
  34385         3,
  34386     },
  34387 #endif /* chips */
  34388 
  34389 #if defined(BCM_56370_A0)
  34390     { /* SOC_REG_INT_USBD_BDC_FSCICH0r */
  34391         soc_block_list[61],
  34392         soc_iprocreg,
  34393         1,
  34394         0,
  34395         0x10242d00,
  34396         0,
  34397         0,
  34398         4,
  34399         soc_USBD_BDC_FSCICH0r_fields,
  34400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34401         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34402         -1,
  34403         -1,
  34404         3,
  34405     },
  34406 #endif /* chips */
  34407 
  34408 #if defined(BCM_56370_A0)
  34409     { /* SOC_REG_INT_USBD_BDC_FSCICH1r */
  34410         soc_block_list[61],
  34411         soc_iprocreg,
  34412         1,
  34413         0,
  34414         0x10242d04,
  34415         0,
  34416         0,
  34417         4,
  34418         soc_USBD_BDC_FSCICH0r_fields,
  34419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34420         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34421         -1,
  34422         -1,
  34423         3,
  34424     },
  34425 #endif /* chips */
  34426 
  34427 #if defined(BCM_56370_A0)
  34428     { /* SOC_REG_INT_USBD_BDC_FSCICH2r */
  34429         soc_block_list[61],
  34430         soc_iprocreg,
  34431         1,
  34432         0,
  34433         0x10242d08,
  34434         0,
  34435         0,
  34436         4,
  34437         soc_USBD_BDC_FSCICH0r_fields,
  34438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34439         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34440         -1,
  34441         -1,
  34442         3,
  34443     },
  34444 #endif /* chips */
  34445 
  34446 #if defined(BCM_56370_A0)
  34447     { /* SOC_REG_INT_USBD_BDC_FSCICH3r */
  34448         soc_block_list[61],
  34449         soc_iprocreg,
  34450         1,
  34451         0,
  34452         0x10242d0c,
  34453         0,
  34454         0,
  34455         4,
  34456         soc_USBD_BDC_FSCICH0r_fields,
  34457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34458         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34459         -1,
  34460         -1,
  34461         3,
  34462     },
  34463 #endif /* chips */
  34464 
  34465 #if defined(BCM_56370_A0)
  34466     { /* SOC_REG_INT_USBD_BDC_FSCICH4r */
  34467         soc_block_list[61],
  34468         soc_iprocreg,
  34469         1,
  34470         0,
  34471         0x10242d10,
  34472         0,
  34473         0,
  34474         4,
  34475         soc_USBD_BDC_FSCICH0r_fields,
  34476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34477         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34478         -1,
  34479         -1,
  34480         3,
  34481     },
  34482 #endif /* chips */
  34483 
  34484 #if defined(BCM_56370_A0)
  34485     { /* SOC_REG_INT_USBD_BDC_FSCICH5r */
  34486         soc_block_list[61],
  34487         soc_iprocreg,
  34488         1,
  34489         0,
  34490         0x10242d14,
  34491         0,
  34492         0,
  34493         4,
  34494         soc_USBD_BDC_FSCICH0r_fields,
  34495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34496         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34497         -1,
  34498         -1,
  34499         3,
  34500     },
  34501 #endif /* chips */
  34502 
  34503 #if defined(BCM_56370_A0)
  34504     { /* SOC_REG_INT_USBD_BDC_FSCICH6r */
  34505         soc_block_list[61],
  34506         soc_iprocreg,
  34507         1,
  34508         0,
  34509         0x10242d18,
  34510         0,
  34511         0,
  34512         4,
  34513         soc_USBD_BDC_FSCICH0r_fields,
  34514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34516         -1,
  34517         -1,
  34518         3,
  34519     },
  34520 #endif /* chips */
  34521 
  34522 #if defined(BCM_56370_A0)
  34523     { /* SOC_REG_INT_USBD_BDC_FSCICHX0r */
  34524         soc_block_list[61],
  34525         soc_iprocreg,
  34526         1,
  34527         0,
  34528         0x10242dc0,
  34529         0,
  34530         0,
  34531         3,
  34532         soc_USBD_BDC_FSCICHX0r_fields,
  34533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34534         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34535         -1,
  34536         -1,
  34537         3,
  34538     },
  34539 #endif /* chips */
  34540 
  34541 #if defined(BCM_56370_A0)
  34542     { /* SOC_REG_INT_USBD_BDC_FSCICHX1r */
  34543         soc_block_list[61],
  34544         soc_iprocreg,
  34545         1,
  34546         0,
  34547         0x10242dc4,
  34548         0,
  34549         0,
  34550         3,
  34551         soc_USBD_BDC_FSCICHX0r_fields,
  34552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34553         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34554         -1,
  34555         -1,
  34556         3,
  34557     },
  34558 #endif /* chips */
  34559 
  34560 #if defined(BCM_56370_A0)
  34561     { /* SOC_REG_INT_USBD_BDC_FSCICHX2r */
  34562         soc_block_list[61],
  34563         soc_iprocreg,
  34564         1,
  34565         0,
  34566         0x10242dc8,
  34567         0,
  34568         0,
  34569         3,
  34570         soc_USBD_BDC_FSCICHX0r_fields,
  34571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34572         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34573         -1,
  34574         -1,
  34575         3,
  34576     },
  34577 #endif /* chips */
  34578 
  34579 #if defined(BCM_56370_A0)
  34580     { /* SOC_REG_INT_USBD_BDC_FSCICHX3r */
  34581         soc_block_list[61],
  34582         soc_iprocreg,
  34583         1,
  34584         0,
  34585         0x10242dcc,
  34586         0,
  34587         0,
  34588         3,
  34589         soc_USBD_BDC_FSCICHX0r_fields,
  34590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34591         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34592         -1,
  34593         -1,
  34594         3,
  34595     },
  34596 #endif /* chips */
  34597 
  34598 #if defined(BCM_56370_A0)
  34599     { /* SOC_REG_INT_USBD_BDC_FSCICHX4r */
  34600         soc_block_list[61],
  34601         soc_iprocreg,
  34602         1,
  34603         0,
  34604         0x10242dd0,
  34605         0,
  34606         0,
  34607         3,
  34608         soc_USBD_BDC_FSCICHX0r_fields,
  34609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34610         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34611         -1,
  34612         -1,
  34613         3,
  34614     },
  34615 #endif /* chips */
  34616 
  34617 #if defined(BCM_56370_A0)
  34618     { /* SOC_REG_INT_USBD_BDC_FSCICHX5r */
  34619         soc_block_list[61],
  34620         soc_iprocreg,
  34621         1,
  34622         0,
  34623         0x10242dd4,
  34624         0,
  34625         0,
  34626         3,
  34627         soc_USBD_BDC_FSCICHX0r_fields,
  34628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34629         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34630         -1,
  34631         -1,
  34632         3,
  34633     },
  34634 #endif /* chips */
  34635 
  34636 #if defined(BCM_56370_A0)
  34637     { /* SOC_REG_INT_USBD_BDC_FSCICHX6r */
  34638         soc_block_list[61],
  34639         soc_iprocreg,
  34640         1,
  34641         0,
  34642         0x10242dd8,
  34643         0,
  34644         0,
  34645         3,
  34646         soc_USBD_BDC_FSCICHX0r_fields,
  34647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34648         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34649         -1,
  34650         -1,
  34651         3,
  34652     },
  34653 #endif /* chips */
  34654 
  34655 #if defined(BCM_56370_A0)
  34656     { /* SOC_REG_INT_USBD_BDC_FSCLICr */
  34657         soc_block_list[61],
  34658         soc_iprocreg,
  34659         1,
  34660         0,
  34661         0x10242ce8,
  34662         SOC_REG_FLAG_RO,
  34663         0,
  34664         6,
  34665         soc_USBD_BDC_FSCHICr_fields,
  34666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34667         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34668         -1,
  34669         -1,
  34670         3,
  34671     },
  34672 #endif /* chips */
  34673 
  34674 #if defined(BCM_56370_A0)
  34675     { /* SOC_REG_INT_USBD_BDC_FSCLOCr */
  34676         soc_block_list[61],
  34677         soc_iprocreg,
  34678         1,
  34679         0,
  34680         0x10242cd8,
  34681         SOC_REG_FLAG_RO,
  34682         0,
  34683         3,
  34684         soc_USBD_BDC_FSCHOCr_fields,
  34685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34686         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34687         -1,
  34688         -1,
  34689         3,
  34690     },
  34691 #endif /* chips */
  34692 
  34693 #if defined(BCM_56370_A0)
  34694     { /* SOC_REG_INT_USBD_BDC_FSCNICr */
  34695         soc_block_list[61],
  34696         soc_iprocreg,
  34697         1,
  34698         0,
  34699         0x10242ce4,
  34700         SOC_REG_FLAG_RO,
  34701         0,
  34702         6,
  34703         soc_USBD_BDC_FSCHICr_fields,
  34704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34705         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34706         -1,
  34707         -1,
  34708         3,
  34709     },
  34710 #endif /* chips */
  34711 
  34712 #if defined(BCM_56370_A0)
  34713     { /* SOC_REG_INT_USBD_BDC_FSCNOCr */
  34714         soc_block_list[61],
  34715         soc_iprocreg,
  34716         1,
  34717         0,
  34718         0x10242cd4,
  34719         SOC_REG_FLAG_RO,
  34720         0,
  34721         3,
  34722         soc_USBD_BDC_FSCHOCr_fields,
  34723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34724         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34725         -1,
  34726         -1,
  34727         3,
  34728     },
  34729 #endif /* chips */
  34730 
  34731 #if defined(BCM_56370_A0)
  34732     { /* SOC_REG_INT_USBD_BDC_FSCOBDC1r */
  34733         soc_block_list[61],
  34734         soc_iprocreg,
  34735         1,
  34736         0,
  34737         0x10242d44,
  34738         0,
  34739         0,
  34740         3,
  34741         soc_USBD_BDC_FSCIBDC0r_fields,
  34742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34744         -1,
  34745         -1,
  34746         3,
  34747     },
  34748 #endif /* chips */
  34749 
  34750 #if defined(BCM_56370_A0)
  34751     { /* SOC_REG_INT_USBD_BDC_FSCOBDC2r */
  34752         soc_block_list[61],
  34753         soc_iprocreg,
  34754         1,
  34755         0,
  34756         0x10242d48,
  34757         0,
  34758         0,
  34759         3,
  34760         soc_USBD_BDC_FSCIBDC0r_fields,
  34761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34762         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34763         -1,
  34764         -1,
  34765         3,
  34766     },
  34767 #endif /* chips */
  34768 
  34769 #if defined(BCM_56370_A0)
  34770     { /* SOC_REG_INT_USBD_BDC_FSCOBDC3r */
  34771         soc_block_list[61],
  34772         soc_iprocreg,
  34773         1,
  34774         0,
  34775         0x10242d4c,
  34776         0,
  34777         0,
  34778         3,
  34779         soc_USBD_BDC_FSCIBDC0r_fields,
  34780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34781         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34782         -1,
  34783         -1,
  34784         3,
  34785     },
  34786 #endif /* chips */
  34787 
  34788 #if defined(BCM_56370_A0)
  34789     { /* SOC_REG_INT_USBD_BDC_FSCOBDC4r */
  34790         soc_block_list[61],
  34791         soc_iprocreg,
  34792         1,
  34793         0,
  34794         0x10242d50,
  34795         0,
  34796         0,
  34797         3,
  34798         soc_USBD_BDC_FSCIBDC0r_fields,
  34799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34800         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34801         -1,
  34802         -1,
  34803         3,
  34804     },
  34805 #endif /* chips */
  34806 
  34807 #if defined(BCM_56370_A0)
  34808     { /* SOC_REG_INT_USBD_BDC_FSCOBDC5r */
  34809         soc_block_list[61],
  34810         soc_iprocreg,
  34811         1,
  34812         0,
  34813         0x10242d54,
  34814         0,
  34815         0,
  34816         3,
  34817         soc_USBD_BDC_FSCIBDC0r_fields,
  34818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34819         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34820         -1,
  34821         -1,
  34822         3,
  34823     },
  34824 #endif /* chips */
  34825 
  34826 #if defined(BCM_56370_A0)
  34827     { /* SOC_REG_INT_USBD_BDC_FSCOBDC6r */
  34828         soc_block_list[61],
  34829         soc_iprocreg,
  34830         1,
  34831         0,
  34832         0x10242d58,
  34833         0,
  34834         0,
  34835         3,
  34836         soc_USBD_BDC_FSCIBDC0r_fields,
  34837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34838         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34839         -1,
  34840         -1,
  34841         3,
  34842     },
  34843 #endif /* chips */
  34844 
  34845 #if defined(BCM_56370_A0)
  34846     { /* SOC_REG_INT_USBD_BDC_FSCODBC0r */
  34847         soc_block_list[61],
  34848         soc_iprocreg,
  34849         1,
  34850         0,
  34851         0x10242d40,
  34852         0,
  34853         0,
  34854         3,
  34855         soc_USBD_BDC_FSCIBDC0r_fields,
  34856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34857         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34858         -1,
  34859         -1,
  34860         3,
  34861     },
  34862 #endif /* chips */
  34863 
  34864 #if defined(BCM_56370_A0)
  34865     { /* SOC_REG_INT_USBD_BDC_FSCOUTr */
  34866         soc_block_list[61],
  34867         soc_iprocreg,
  34868         1,
  34869         0,
  34870         0x10242cd0,
  34871         SOC_REG_FLAG_RO,
  34872         0,
  34873         3,
  34874         soc_USBD_BDC_FSCOUTr_fields,
  34875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34876         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  34877         -1,
  34878         -1,
  34879         3,
  34880     },
  34881 #endif /* chips */
  34882 
  34883 #if defined(BCM_56370_A0)
  34884     { /* SOC_REG_INT_USBD_BDC_INTCLS0r */
  34885         soc_block_list[61],
  34886         soc_iprocreg,
  34887         1,
  34888         0,
  34889         0x1024220c,
  34890         0,
  34891         0,
  34892         2,
  34893         soc_USBD_BDC_INTCLS0r_fields,
  34894         SOC_RESET_VAL_DEC(0x00000fa0, 0x00000000)
  34895         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34896         -1,
  34897         -1,
  34898         3,
  34899     },
  34900 #endif /* chips */
  34901 
  34902 #if defined(BCM_56370_A0)
  34903     { /* SOC_REG_INT_USBD_BDC_INTCLS1r */
  34904         soc_block_list[61],
  34905         soc_iprocreg,
  34906         1,
  34907         0,
  34908         0x1024221c,
  34909         0,
  34910         0,
  34911         2,
  34912         soc_USBD_BDC_INTCLS0r_fields,
  34913         SOC_RESET_VAL_DEC(0x00000fa0, 0x00000000)
  34914         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34915         -1,
  34916         -1,
  34917         3,
  34918     },
  34919 #endif /* chips */
  34920 
  34921 #if defined(BCM_56370_A0)
  34922     { /* SOC_REG_INT_USBD_BDC_INTCLS2r */
  34923         soc_block_list[61],
  34924         soc_iprocreg,
  34925         1,
  34926         0,
  34927         0x1024222c,
  34928         0,
  34929         0,
  34930         2,
  34931         soc_USBD_BDC_INTCLS0r_fields,
  34932         SOC_RESET_VAL_DEC(0x00000fa0, 0x00000000)
  34933         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34934         -1,
  34935         -1,
  34936         3,
  34937     },
  34938 #endif /* chips */
  34939 
  34940 #if defined(BCM_56370_A0)
  34941     { /* SOC_REG_INT_USBD_BDC_INTCLS3r */
  34942         soc_block_list[61],
  34943         soc_iprocreg,
  34944         1,
  34945         0,
  34946         0x1024223c,
  34947         0,
  34948         0,
  34949         2,
  34950         soc_USBD_BDC_INTCLS0r_fields,
  34951         SOC_RESET_VAL_DEC(0x00000fa0, 0x00000000)
  34952         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34953         -1,
  34954         -1,
  34955         3,
  34956     },
  34957 #endif /* chips */
  34958 
  34959 #if defined(BCM_56370_A0)
  34960     { /* SOC_REG_INT_USBD_BDC_IRAADRr */
  34961         soc_block_list[61],
  34962         soc_iprocreg,
  34963         1,
  34964         0,
  34965         0x10242f98,
  34966         0,
  34967         0,
  34968         3,
  34969         soc_USBD_BDC_IRAADRr_fields,
  34970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34971         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  34972         -1,
  34973         -1,
  34974         3,
  34975     },
  34976 #endif /* chips */
  34977 
  34978 #if defined(BCM_56370_A0)
  34979     { /* SOC_REG_INT_USBD_BDC_IRADATr */
  34980         soc_block_list[61],
  34981         soc_iprocreg,
  34982         1,
  34983         0,
  34984         0x10242f9c,
  34985         0,
  34986         0,
  34987         1,
  34988         soc_USBD_BDC_IRADATr_fields,
  34989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34990         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34991         -1,
  34992         -1,
  34993         3,
  34994     },
  34995 #endif /* chips */
  34996 
  34997 #if defined(BCM_56370_A0)
  34998     { /* SOC_REG_INT_USBD_BDC_LNKHSCr */
  34999         soc_block_list[61],
  35000         soc_iprocreg,
  35001         1,
  35002         0,
  35003         0x10242e18,
  35004         0,
  35005         0,
  35006         6,
  35007         soc_USBD_BDC_LNKHSCr_fields,
  35008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35009         SOC_RESET_MASK_DEC(0xffff00ff, 0x00000000)
  35010         -1,
  35011         -1,
  35012         3,
  35013     },
  35014 #endif /* chips */
  35015 
  35016 #if defined(BCM_56370_A0)
  35017     { /* SOC_REG_INT_USBD_BDC_LNKHSRr */
  35018         soc_block_list[61],
  35019         soc_iprocreg,
  35020         1,
  35021         0,
  35022         0x10242e1c,
  35023         SOC_REG_FLAG_RO,
  35024         0,
  35025         4,
  35026         soc_USBD_BDC_LNKHSRr_fields,
  35027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35028         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35029         -1,
  35030         -1,
  35031         3,
  35032     },
  35033 #endif /* chips */
  35034 
  35035 #if defined(BCM_56370_A0)
  35036     { /* SOC_REG_INT_USBD_BDC_MFNUMr */
  35037         soc_block_list[61],
  35038         soc_iprocreg,
  35039         1,
  35040         0,
  35041         0x10242048,
  35042         0,
  35043         0,
  35044         3,
  35045         soc_USBD_BDC_MFNUMr_fields,
  35046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35047         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35048         -1,
  35049         -1,
  35050         3,
  35051     },
  35052 #endif /* chips */
  35053 
  35054 #if defined(BCM_56370_A0)
  35055     { /* SOC_REG_INT_USBD_BDC_OSC0r */
  35056         soc_block_list[61],
  35057         soc_iprocreg,
  35058         1,
  35059         0,
  35060         0x10242080,
  35061         SOC_REG_FLAG_RO,
  35062         0,
  35063         3,
  35064         soc_USBD_BDC_OSC0r_fields,
  35065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35066         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35067         -1,
  35068         -1,
  35069         3,
  35070     },
  35071 #endif /* chips */
  35072 
  35073 #if defined(BCM_56370_A0)
  35074     { /* SOC_REG_INT_USBD_BDC_OSC1r */
  35075         soc_block_list[61],
  35076         soc_iprocreg,
  35077         1,
  35078         0,
  35079         0x10242084,
  35080         SOC_REG_FLAG_RO,
  35081         0,
  35082         1,
  35083         soc_CMICD_S0_IDM_IDM_IO_STATUS_BCM53400_A0r_fields,
  35084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35085         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35086         -1,
  35087         -1,
  35088         3,
  35089     },
  35090 #endif /* chips */
  35091 
  35092 #if defined(BCM_56370_A0)
  35093     { /* SOC_REG_INT_USBD_BDC_OSC2r */
  35094         soc_block_list[61],
  35095         soc_iprocreg,
  35096         1,
  35097         0,
  35098         0x10242088,
  35099         SOC_REG_FLAG_RO,
  35100         0,
  35101         1,
  35102         soc_CMICD_S0_IDM_IDM_IO_STATUS_BCM53400_A0r_fields,
  35103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35104         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35105         -1,
  35106         -1,
  35107         3,
  35108     },
  35109 #endif /* chips */
  35110 
  35111 #if defined(BCM_56370_A0)
  35112     { /* SOC_REG_INT_USBD_BDC_OSC3r */
  35113         soc_block_list[61],
  35114         soc_iprocreg,
  35115         1,
  35116         0,
  35117         0x1024208c,
  35118         SOC_REG_FLAG_RO,
  35119         0,
  35120         1,
  35121         soc_CMICD_S0_IDM_IDM_IO_STATUS_BCM53400_A0r_fields,
  35122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35123         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35124         -1,
  35125         -1,
  35126         3,
  35127     },
  35128 #endif /* chips */
  35129 
  35130 #if defined(BCM_56370_A0)
  35131     { /* SOC_REG_INT_USBD_BDC_PHYSSPr */
  35132         soc_block_list[61],
  35133         soc_iprocreg,
  35134         1,
  35135         0,
  35136         0x10242e28,
  35137         SOC_REG_FLAG_RO,
  35138         0,
  35139         9,
  35140         soc_USBD_BDC_PHYSSPr_fields,
  35141         SOC_RESET_VAL_DEC(0x30011000, 0x00000000)
  35142         SOC_RESET_MASK_DEC(0xfff73e0f, 0x00000000)
  35143         -1,
  35144         -1,
  35145         3,
  35146     },
  35147 #endif /* chips */
  35148 
  35149 #if defined(BCM_56370_A0)
  35150     { /* SOC_REG_INT_USBD_BDC_PHYU2Pr */
  35151         soc_block_list[61],
  35152         soc_iprocreg,
  35153         1,
  35154         0,
  35155         0x10242e2c,
  35156         SOC_REG_FLAG_RO,
  35157         0,
  35158         7,
  35159         soc_USBD_BDC_PHYU2Pr_fields,
  35160         SOC_RESET_VAL_DEC(0x10010010, 0x00000000)
  35161         SOC_RESET_MASK_DEC(0xfff7001f, 0x00000000)
  35162         -1,
  35163         -1,
  35164         3,
  35165     },
  35166 #endif /* chips */
  35167 
  35168 #if defined(BCM_56370_A0)
  35169     { /* SOC_REG_INT_USBD_BDC_PRTHSCr */
  35170         soc_block_list[61],
  35171         soc_iprocreg,
  35172         1,
  35173         0,
  35174         0x10242e08,
  35175         0,
  35176         0,
  35177         6,
  35178         soc_USBD_BDC_LNKHSCr_fields,
  35179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35180         SOC_RESET_MASK_DEC(0xffff00ff, 0x00000000)
  35181         -1,
  35182         -1,
  35183         3,
  35184     },
  35185 #endif /* chips */
  35186 
  35187 #if defined(BCM_56370_A0)
  35188     { /* SOC_REG_INT_USBD_BDC_PRTHSRr */
  35189         soc_block_list[61],
  35190         soc_iprocreg,
  35191         1,
  35192         0,
  35193         0x10242e0c,
  35194         SOC_REG_FLAG_RO,
  35195         0,
  35196         4,
  35197         soc_USBD_BDC_LNKHSRr_fields,
  35198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35199         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35200         -1,
  35201         -1,
  35202         3,
  35203     },
  35204 #endif /* chips */
  35205 
  35206 #if defined(BCM_56370_A0)
  35207     { /* SOC_REG_INT_USBD_BDC_RBVMGNr */
  35208         soc_block_list[61],
  35209         soc_iprocreg,
  35210         1,
  35211         0,
  35212         0x10242fbc,
  35213         SOC_REG_FLAG_RO,
  35214         0,
  35215         1,
  35216         soc_USBD_BDC_RBVMGNr_fields,
  35217         SOC_RESET_VAL_DEC(0x4e504148, 0x00000000)
  35218         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35219         -1,
  35220         -1,
  35221         3,
  35222     },
  35223 #endif /* chips */
  35224 
  35225 #if defined(BCM_56370_A0)
  35226     { /* SOC_REG_INT_USBD_BDC_RBVPDTr */
  35227         soc_block_list[61],
  35228         soc_iprocreg,
  35229         1,
  35230         0,
  35231         0x10242fb4,
  35232         SOC_REG_FLAG_RO,
  35233         0,
  35234         2,
  35235         soc_USBD_BDC_RBVPDTr_fields,
  35236         SOC_RESET_VAL_DEC(0x0a5c0000, 0x00000000)
  35237         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35238         -1,
  35239         -1,
  35240         3,
  35241     },
  35242 #endif /* chips */
  35243 
  35244 #if defined(BCM_56370_A0)
  35245     { /* SOC_REG_INT_USBD_BDC_SPBBAHr */
  35246         soc_block_list[61],
  35247         soc_iprocreg,
  35248         1,
  35249         0,
  35250         0x1024203c,
  35251         0,
  35252         0,
  35253         1,
  35254         soc_USBD_BDC_SPBBAHr_fields,
  35255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35256         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35257         -1,
  35258         -1,
  35259         3,
  35260     },
  35261 #endif /* chips */
  35262 
  35263 #if defined(BCM_56370_A0)
  35264     { /* SOC_REG_INT_USBD_BDC_SPBBALr */
  35265         soc_block_list[61],
  35266         soc_iprocreg,
  35267         1,
  35268         0,
  35269         0x10242038,
  35270         0,
  35271         0,
  35272         2,
  35273         soc_USBD_BDC_SPBBALr_fields,
  35274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35276         -1,
  35277         -1,
  35278         3,
  35279     },
  35280 #endif /* chips */
  35281 
  35282 #if defined(BCM_56370_A0)
  35283     { /* SOC_REG_INT_USBD_BDC_SRRBAH0r */
  35284         soc_block_list[61],
  35285         soc_iprocreg,
  35286         1,
  35287         0,
  35288         0x10242204,
  35289         0,
  35290         0,
  35291         1,
  35292         soc_USBD_BDC_SPBBAHr_fields,
  35293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35294         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35295         -1,
  35296         -1,
  35297         3,
  35298     },
  35299 #endif /* chips */
  35300 
  35301 #if defined(BCM_56370_A0)
  35302     { /* SOC_REG_INT_USBD_BDC_SRRBAH1r */
  35303         soc_block_list[61],
  35304         soc_iprocreg,
  35305         1,
  35306         0,
  35307         0x10242214,
  35308         0,
  35309         0,
  35310         1,
  35311         soc_USBD_BDC_SPBBAHr_fields,
  35312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35313         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35314         -1,
  35315         -1,
  35316         3,
  35317     },
  35318 #endif /* chips */
  35319 
  35320 #if defined(BCM_56370_A0)
  35321     { /* SOC_REG_INT_USBD_BDC_SRRBAH2r */
  35322         soc_block_list[61],
  35323         soc_iprocreg,
  35324         1,
  35325         0,
  35326         0x10242224,
  35327         0,
  35328         0,
  35329         1,
  35330         soc_USBD_BDC_SPBBAHr_fields,
  35331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35333         -1,
  35334         -1,
  35335         3,
  35336     },
  35337 #endif /* chips */
  35338 
  35339 #if defined(BCM_56370_A0)
  35340     { /* SOC_REG_INT_USBD_BDC_SRRBAH3r */
  35341         soc_block_list[61],
  35342         soc_iprocreg,
  35343         1,
  35344         0,
  35345         0x10242234,
  35346         0,
  35347         0,
  35348         1,
  35349         soc_USBD_BDC_SPBBAHr_fields,
  35350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35351         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35352         -1,
  35353         -1,
  35354         3,
  35355     },
  35356 #endif /* chips */
  35357 
  35358 #if defined(BCM_56370_A0)
  35359     { /* SOC_REG_INT_USBD_BDC_SRRBAL0r */
  35360         soc_block_list[61],
  35361         soc_iprocreg,
  35362         1,
  35363         0,
  35364         0x10242200,
  35365         0,
  35366         0,
  35367         3,
  35368         soc_USBD_BDC_SRRBAL0r_fields,
  35369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35370         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35371         -1,
  35372         -1,
  35373         3,
  35374     },
  35375 #endif /* chips */
  35376 
  35377 #if defined(BCM_56370_A0)
  35378     { /* SOC_REG_INT_USBD_BDC_SRRBAL1r */
  35379         soc_block_list[61],
  35380         soc_iprocreg,
  35381         1,
  35382         0,
  35383         0x10242210,
  35384         0,
  35385         0,
  35386         3,
  35387         soc_USBD_BDC_SRRBAL0r_fields,
  35388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35389         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35390         -1,
  35391         -1,
  35392         3,
  35393     },
  35394 #endif /* chips */
  35395 
  35396 #if defined(BCM_56370_A0)
  35397     { /* SOC_REG_INT_USBD_BDC_SRRBAL2r */
  35398         soc_block_list[61],
  35399         soc_iprocreg,
  35400         1,
  35401         0,
  35402         0x10242220,
  35403         0,
  35404         0,
  35405         3,
  35406         soc_USBD_BDC_SRRBAL0r_fields,
  35407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35408         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35409         -1,
  35410         -1,
  35411         3,
  35412     },
  35413 #endif /* chips */
  35414 
  35415 #if defined(BCM_56370_A0)
  35416     { /* SOC_REG_INT_USBD_BDC_SRRBAL3r */
  35417         soc_block_list[61],
  35418         soc_iprocreg,
  35419         1,
  35420         0,
  35421         0x10242230,
  35422         0,
  35423         0,
  35424         3,
  35425         soc_USBD_BDC_SRRBAL0r_fields,
  35426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35428         -1,
  35429         -1,
  35430         3,
  35431     },
  35432 #endif /* chips */
  35433 
  35434 #if defined(BCM_56370_A0)
  35435     { /* SOC_REG_INT_USBD_BDC_SRRINT0r */
  35436         soc_block_list[61],
  35437         soc_iprocreg,
  35438         1,
  35439         0,
  35440         0x10242208,
  35441         0,
  35442         0,
  35443         8,
  35444         soc_USBD_BDC_SRRINT0r_fields,
  35445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35446         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35447         -1,
  35448         -1,
  35449         3,
  35450     },
  35451 #endif /* chips */
  35452 
  35453 #if defined(BCM_56370_A0)
  35454     { /* SOC_REG_INT_USBD_BDC_SRRINT1r */
  35455         soc_block_list[61],
  35456         soc_iprocreg,
  35457         1,
  35458         0,
  35459         0x10242218,
  35460         0,
  35461         0,
  35462         8,
  35463         soc_USBD_BDC_SRRINT0r_fields,
  35464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35465         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35466         -1,
  35467         -1,
  35468         3,
  35469     },
  35470 #endif /* chips */
  35471 
  35472 #if defined(BCM_56370_A0)
  35473     { /* SOC_REG_INT_USBD_BDC_SRRINT2r */
  35474         soc_block_list[61],
  35475         soc_iprocreg,
  35476         1,
  35477         0,
  35478         0x10242228,
  35479         0,
  35480         0,
  35481         8,
  35482         soc_USBD_BDC_SRRINT0r_fields,
  35483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35484         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35485         -1,
  35486         -1,
  35487         3,
  35488     },
  35489 #endif /* chips */
  35490 
  35491 #if defined(BCM_56370_A0)
  35492     { /* SOC_REG_INT_USBD_BDC_SRRINT3r */
  35493         soc_block_list[61],
  35494         soc_iprocreg,
  35495         1,
  35496         0,
  35497         0x10242238,
  35498         0,
  35499         0,
  35500         8,
  35501         soc_USBD_BDC_SRRINT0r_fields,
  35502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35503         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35504         -1,
  35505         -1,
  35506         3,
  35507     },
  35508 #endif /* chips */
  35509 
  35510 #if defined(BCM_56370_A0)
  35511     { /* SOC_REG_INT_USBD_BDC_USPPM2r */
  35512         soc_block_list[61],
  35513         soc_iprocreg,
  35514         1,
  35515         0,
  35516         0x1024202c,
  35517         0,
  35518         0,
  35519         8,
  35520         soc_USBD_BDC_USPPM2r_fields,
  35521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35522         SOC_RESET_MASK_DEC(0xfff1ffff, 0x00000000)
  35523         -1,
  35524         -1,
  35525         3,
  35526     },
  35527 #endif /* chips */
  35528 
  35529 #if defined(BCM_56370_A0)
  35530     { /* SOC_REG_INT_USBD_BDC_USPPMSr */
  35531         soc_block_list[61],
  35532         soc_iprocreg,
  35533         1,
  35534         0,
  35535         0x10242028,
  35536         0,
  35537         0,
  35538         9,
  35539         soc_USBD_BDC_USPPMSr_fields,
  35540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35542         -1,
  35543         -1,
  35544         3,
  35545     },
  35546 #endif /* chips */
  35547 
  35548 #if defined(BCM_56370_A0)
  35549     { /* SOC_REG_INT_USBD_BDC_USPSCr */
  35550         soc_block_list[61],
  35551         soc_iprocreg,
  35552         1,
  35553         0,
  35554         0x10242020,
  35555         0,
  35556         0,
  35557         15,
  35558         soc_USBD_BDC_USPSCr_fields,
  35559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35560         SOC_RESET_MASK_DEC(0xfff001ff, 0x00000000)
  35561         -1,
  35562         -1,
  35563         3,
  35564     },
  35565 #endif /* chips */
  35566 
  35567 #if defined(BCM_56370_A0)
  35568     { /* SOC_REG_INT_USBD_BDC_USPTDSr */
  35569         soc_block_list[61],
  35570         soc_iprocreg,
  35571         1,
  35572         0,
  35573         0x10242024,
  35574         0,
  35575         0,
  35576         12,
  35577         soc_USBD_BDC_USPTDSr_fields,
  35578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35579         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35580         -1,
  35581         -1,
  35582         3,
  35583     },
  35584 #endif /* chips */
  35585 
  35586 #if defined(BCM_56370_A0)
  35587     { /* SOC_REG_INT_USBD_BDC_XSFNTFr */
  35588         soc_block_list[61],
  35589         soc_iprocreg,
  35590         1,
  35591         0,
  35592         0x1024204c,
  35593         0,
  35594         0,
  35595         3,
  35596         soc_USBD_BDC_XSFNTFr_fields,
  35597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35598         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35599         -1,
  35600         -1,
  35601         3,
  35602     },
  35603 #endif /* chips */
  35604 
  35605 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  35606     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  35607     { /* SOC_REG_INT_USBH_ASYNCLISTADDRr */
  35608         soc_block_list[61],
  35609         soc_iprocreg,
  35610         1,
  35611         0,
  35612         0x1802a028,
  35613         0,
  35614         0,
  35615         1,
  35616         soc_USBH_ASYNCLISTADDRr_fields,
  35617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35618         SOC_RESET_MASK_DEC(0xffffffe0, 0x00000000)
  35619         -1,
  35620         -1,
  35621     },
  35622 #endif /* chips */
  35623 
  35624 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35625     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35626     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35627     defined(BCM_56260_B0)
  35628     { /* SOC_REG_INT_USBH_ASYNCLISTADDR_BCM53400_A0r */
  35629         soc_block_list[61],
  35630         soc_iprocreg,
  35631         1,
  35632         0,
  35633         0x18048028,
  35634         0,
  35635         0,
  35636         1,
  35637         soc_USBH_ASYNCLISTADDR_BCM53400_A0r_fields,
  35638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35639         SOC_RESET_MASK_DEC(0xffffffe0, 0x00000000)
  35640         -1,
  35641         -1,
  35642     },
  35643 #endif /* chips */
  35644 
  35645 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  35646     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  35647     { /* SOC_REG_INT_USBH_CONFIGFLAGr */
  35648         soc_block_list[61],
  35649         soc_iprocreg,
  35650         1,
  35651         0,
  35652         0x1802a050,
  35653         0,
  35654         0,
  35655         1,
  35656         soc_USBH_CONFIGFLAGr_fields,
  35657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35658         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35659         -1,
  35660         -1,
  35661     },
  35662 #endif /* chips */
  35663 
  35664 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35665     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35666     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35667     defined(BCM_56260_B0)
  35668     { /* SOC_REG_INT_USBH_CONFIGFLAG_BCM53400_A0r */
  35669         soc_block_list[61],
  35670         soc_iprocreg,
  35671         1,
  35672         0,
  35673         0x18048050,
  35674         0,
  35675         0,
  35676         1,
  35677         soc_USBH_CONFIGFLAG_BCM53400_A0r_fields,
  35678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35679         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35680         -1,
  35681         -1,
  35682     },
  35683 #endif /* chips */
  35684 
  35685 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  35686     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  35687     { /* SOC_REG_INT_USBH_CTRLDSSEGMENTr */
  35688         soc_block_list[61],
  35689         soc_iprocreg,
  35690         1,
  35691         0,
  35692         0x1802a020,
  35693         0,
  35694         0,
  35695         1,
  35696         soc_USBH_CTRLDSSEGMENTr_fields,
  35697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35698         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35699         -1,
  35700         -1,
  35701     },
  35702 #endif /* chips */
  35703 
  35704 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35705     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35706     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35707     defined(BCM_56260_B0)
  35708     { /* SOC_REG_INT_USBH_CTRLDSSEGMENT_BCM53400_A0r */
  35709         soc_block_list[61],
  35710         soc_iprocreg,
  35711         1,
  35712         0,
  35713         0x18048020,
  35714         0,
  35715         0,
  35716         1,
  35717         soc_USBH_CTRLDSSEGMENT_BCM53400_A0r_fields,
  35718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35719         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35720         -1,
  35721         -1,
  35722     },
  35723 #endif /* chips */
  35724 
  35725 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35726     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35727     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35728     defined(BCM_56260_B0)
  35729     { /* SOC_REG_INT_USBH_EHCI_INCRX_STRAPr */
  35730         soc_block_list[61],
  35731         soc_iprocreg,
  35732         1,
  35733         0,
  35734         0x18049800,
  35735         0,
  35736         0,
  35737         4,
  35738         soc_USBH_EHCI_INCRX_STRAPr_fields,
  35739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35740         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  35741         -1,
  35742         -1,
  35743     },
  35744 #endif /* chips */
  35745 
  35746 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35747     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35748     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35749     defined(BCM_56260_B0)
  35750     { /* SOC_REG_INT_USBH_EHCI_LPSMC_STATEr */
  35751         soc_block_list[61],
  35752         soc_iprocreg,
  35753         1,
  35754         0,
  35755         0x1804960c,
  35756         SOC_REG_FLAG_RO,
  35757         0,
  35758         1,
  35759         soc_USBH_EHCI_LPSMC_STATEr_fields,
  35760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35761         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  35762         -1,
  35763         -1,
  35764     },
  35765 #endif /* chips */
  35766 
  35767 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  35768     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  35769     { /* SOC_REG_INT_USBH_EHCI_STATUSr */
  35770         soc_block_list[61],
  35771         soc_iprocreg,
  35772         1,
  35773         0,
  35774         0x1802a314,
  35775         SOC_REG_FLAG_RO,
  35776         0,
  35777         1,
  35778         soc_USBH_EHCI_STATUSr_fields,
  35779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35780         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  35781         -1,
  35782         -1,
  35783     },
  35784 #endif /* chips */
  35785 
  35786 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35787     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35788     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35789     defined(BCM_56260_B0)
  35790     { /* SOC_REG_INT_USBH_EHCI_STATUS_BCM53400_A0r */
  35791         soc_block_list[61],
  35792         soc_iprocreg,
  35793         1,
  35794         0,
  35795         0x18049314,
  35796         SOC_REG_FLAG_RO,
  35797         0,
  35798         1,
  35799         soc_USBH_EHCI_STATUS_BCM53400_A0r_fields,
  35800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35801         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  35802         -1,
  35803         -1,
  35804     },
  35805 #endif /* chips */
  35806 
  35807 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35808     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35809     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35810     defined(BCM_56260_B0)
  35811     { /* SOC_REG_INT_USBH_EHCI_XFERr */
  35812         soc_block_list[61],
  35813         soc_iprocreg,
  35814         1,
  35815         0,
  35816         0x18049608,
  35817         SOC_REG_FLAG_RO,
  35818         0,
  35819         1,
  35820         soc_USBH_EHCI_XFERr_fields,
  35821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35822         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  35823         -1,
  35824         -1,
  35825     },
  35826 #endif /* chips */
  35827 
  35828 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  35829     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  35830     { /* SOC_REG_INT_USBH_FRAME_LENADJr */
  35831         soc_block_list[61],
  35832         soc_iprocreg,
  35833         1,
  35834         0,
  35835         0x1802a300,
  35836         0,
  35837         0,
  35838         1,
  35839         soc_USBH_FRAME_LENADJr_fields,
  35840         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  35841         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  35842         -1,
  35843         -1,
  35844     },
  35845 #endif /* chips */
  35846 
  35847 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35848     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35849     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35850     defined(BCM_56260_B0)
  35851     { /* SOC_REG_INT_USBH_FRAME_LENADJ_BCM53400_A0r */
  35852         soc_block_list[61],
  35853         soc_iprocreg,
  35854         1,
  35855         0,
  35856         0x18049300,
  35857         0,
  35858         0,
  35859         1,
  35860         soc_USBH_FRAME_LENADJ_BCM53400_A0r_fields,
  35861         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
  35862         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  35863         -1,
  35864         -1,
  35865     },
  35866 #endif /* chips */
  35867 
  35868 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  35869     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  35870     { /* SOC_REG_INT_USBH_FRINDEXr */
  35871         soc_block_list[61],
  35872         soc_iprocreg,
  35873         1,
  35874         0,
  35875         0x1802a01c,
  35876         0,
  35877         0,
  35878         1,
  35879         soc_USBH_FRINDEXr_fields,
  35880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35881         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  35882         -1,
  35883         -1,
  35884     },
  35885 #endif /* chips */
  35886 
  35887 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35888     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35889     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35890     defined(BCM_56260_B0)
  35891     { /* SOC_REG_INT_USBH_FRINDEX_BCM53400_A0r */
  35892         soc_block_list[61],
  35893         soc_iprocreg,
  35894         1,
  35895         0,
  35896         0x1804801c,
  35897         0,
  35898         0,
  35899         1,
  35900         soc_USBH_FRINDEX_BCM53400_A0r_fields,
  35901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35902         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  35903         -1,
  35904         -1,
  35905     },
  35906 #endif /* chips */
  35907 
  35908 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  35909     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  35910     { /* SOC_REG_INT_USBH_GPIO_OEr */
  35911         soc_block_list[61],
  35912         soc_iprocreg,
  35913         1,
  35914         0,
  35915         0x1802a520,
  35916         SOC_REG_FLAG_RO,
  35917         0,
  35918         1,
  35919         soc_USBH_GPIO_OEr_fields,
  35920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35921         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35922         -1,
  35923         -1,
  35924     },
  35925 #endif /* chips */
  35926 
  35927 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35928     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35929     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35930     defined(BCM_56260_B0)
  35931     { /* SOC_REG_INT_USBH_GPIO_OE_BCM53400_A0r */
  35932         soc_block_list[61],
  35933         soc_iprocreg,
  35934         1,
  35935         0,
  35936         0x18049520,
  35937         SOC_REG_FLAG_RO,
  35938         0,
  35939         1,
  35940         soc_USBH_GPIO_OE_BCM53400_A0r_fields,
  35941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35942         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35943         -1,
  35944         -1,
  35945     },
  35946 #endif /* chips */
  35947 
  35948 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  35949     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  35950     { /* SOC_REG_INT_USBH_GPIO_SELr */
  35951         soc_block_list[61],
  35952         soc_iprocreg,
  35953         1,
  35954         0,
  35955         0x1802a51c,
  35956         0,
  35957         0,
  35958         1,
  35959         soc_USBH_GPIO_SELr_fields,
  35960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35961         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35962         -1,
  35963         -1,
  35964     },
  35965 #endif /* chips */
  35966 
  35967 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35968     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35969     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35970     defined(BCM_56260_B0)
  35971     { /* SOC_REG_INT_USBH_GPIO_SEL_BCM53400_A0r */
  35972         soc_block_list[61],
  35973         soc_iprocreg,
  35974         1,
  35975         0,
  35976         0x1804951c,
  35977         0,
  35978         0,
  35979         1,
  35980         soc_USBH_GPIO_SEL_BCM53400_A0r_fields,
  35981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35982         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35983         -1,
  35984         -1,
  35985     },
  35986 #endif /* chips */
  35987 
  35988 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  35989     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  35990     { /* SOC_REG_INT_USBH_HCBULKCURRENTEDr */
  35991         soc_block_list[61],
  35992         soc_iprocreg,
  35993         1,
  35994         0,
  35995         0x1802b02c,
  35996         0,
  35997         0,
  35998         1,
  35999         soc_USBH_HCBULKCURRENTEDr_fields,
  36000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36001         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36002         -1,
  36003         -1,
  36004     },
  36005 #endif /* chips */
  36006 
  36007 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36008     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36009     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36010     defined(BCM_56260_B0)
  36011     { /* SOC_REG_INT_USBH_HCBULKCURRENTED_BCM53400_A0r */
  36012         soc_block_list[61],
  36013         soc_iprocreg,
  36014         1,
  36015         0,
  36016         0x1804882c,
  36017         0,
  36018         0,
  36019         1,
  36020         soc_USBH_HCBULKCURRENTED_BCM53400_A0r_fields,
  36021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36022         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36023         -1,
  36024         -1,
  36025     },
  36026 #endif /* chips */
  36027 
  36028 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36029     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36030     { /* SOC_REG_INT_USBH_HCBULKHEADEDr */
  36031         soc_block_list[61],
  36032         soc_iprocreg,
  36033         1,
  36034         0,
  36035         0x1802b028,
  36036         0,
  36037         0,
  36038         1,
  36039         soc_USBH_HCBULKHEADEDr_fields,
  36040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36041         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36042         -1,
  36043         -1,
  36044     },
  36045 #endif /* chips */
  36046 
  36047 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36048     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36049     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36050     defined(BCM_56260_B0)
  36051     { /* SOC_REG_INT_USBH_HCBULKHEADED_BCM53400_A0r */
  36052         soc_block_list[61],
  36053         soc_iprocreg,
  36054         1,
  36055         0,
  36056         0x18048828,
  36057         0,
  36058         0,
  36059         1,
  36060         soc_USBH_HCBULKHEADED_BCM53400_A0r_fields,
  36061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36062         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36063         -1,
  36064         -1,
  36065     },
  36066 #endif /* chips */
  36067 
  36068 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36069     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36070     { /* SOC_REG_INT_USBH_HCCAPBASEr */
  36071         soc_block_list[61],
  36072         soc_iprocreg,
  36073         1,
  36074         0,
  36075         0x1802a000,
  36076         SOC_REG_FLAG_RO,
  36077         0,
  36078         2,
  36079         soc_USBH_HCCAPBASEr_fields,
  36080         SOC_RESET_VAL_DEC(0x01000010, 0x00000000)
  36081         SOC_RESET_MASK_DEC(0xffff00ff, 0x00000000)
  36082         -1,
  36083         -1,
  36084     },
  36085 #endif /* chips */
  36086 
  36087 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36088     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36089     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36090     defined(BCM_56260_B0)
  36091     { /* SOC_REG_INT_USBH_HCCAPBASE_BCM53400_A0r */
  36092         soc_block_list[61],
  36093         soc_iprocreg,
  36094         1,
  36095         0,
  36096         0x18048000,
  36097         SOC_REG_FLAG_RO,
  36098         0,
  36099         2,
  36100         soc_USBH_HCCAPBASE_BCM53400_A0r_fields,
  36101         SOC_RESET_VAL_DEC(0x01000010, 0x00000000)
  36102         SOC_RESET_MASK_DEC(0xffff00ff, 0x00000000)
  36103         -1,
  36104         -1,
  36105     },
  36106 #endif /* chips */
  36107 
  36108 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36109     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36110     { /* SOC_REG_INT_USBH_HCCOMMANDSTATUSr */
  36111         soc_block_list[61],
  36112         soc_iprocreg,
  36113         1,
  36114         0,
  36115         0x1802b008,
  36116         0,
  36117         0,
  36118         5,
  36119         soc_USBH_HCCOMMANDSTATUSr_fields,
  36120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36121         SOC_RESET_MASK_DEC(0x0003000f, 0x00000000)
  36122         -1,
  36123         -1,
  36124     },
  36125 #endif /* chips */
  36126 
  36127 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36128     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36129     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36130     defined(BCM_56260_B0)
  36131     { /* SOC_REG_INT_USBH_HCCOMMANDSTATUS_BCM53400_A0r */
  36132         soc_block_list[61],
  36133         soc_iprocreg,
  36134         1,
  36135         0,
  36136         0x18048808,
  36137         0,
  36138         0,
  36139         5,
  36140         soc_USBH_HCCOMMANDSTATUS_BCM53400_A0r_fields,
  36141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36142         SOC_RESET_MASK_DEC(0x0003000f, 0x00000000)
  36143         -1,
  36144         -1,
  36145     },
  36146 #endif /* chips */
  36147 
  36148 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36149     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36150     { /* SOC_REG_INT_USBH_HCCONTOLCURRENTEDr */
  36151         soc_block_list[61],
  36152         soc_iprocreg,
  36153         1,
  36154         0,
  36155         0x1802b024,
  36156         0,
  36157         0,
  36158         1,
  36159         soc_USBH_HCCONTOLCURRENTEDr_fields,
  36160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36161         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36162         -1,
  36163         -1,
  36164     },
  36165 #endif /* chips */
  36166 
  36167 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36168     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36169     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36170     defined(BCM_56260_B0)
  36171     { /* SOC_REG_INT_USBH_HCCONTOLCURRENTED_BCM53400_A0r */
  36172         soc_block_list[61],
  36173         soc_iprocreg,
  36174         1,
  36175         0,
  36176         0x18048824,
  36177         0,
  36178         0,
  36179         1,
  36180         soc_USBH_HCCONTOLCURRENTED_BCM53400_A0r_fields,
  36181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36182         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36183         -1,
  36184         -1,
  36185     },
  36186 #endif /* chips */
  36187 
  36188 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36189     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36190     { /* SOC_REG_INT_USBH_HCCONTROLr */
  36191         soc_block_list[61],
  36192         soc_iprocreg,
  36193         1,
  36194         0,
  36195         0x1802b004,
  36196         0,
  36197         0,
  36198         9,
  36199         soc_USBH_HCCONTROLr_fields,
  36200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36201         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  36202         -1,
  36203         -1,
  36204     },
  36205 #endif /* chips */
  36206 
  36207 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36208     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36209     { /* SOC_REG_INT_USBH_HCCONTROLHEADEDr */
  36210         soc_block_list[61],
  36211         soc_iprocreg,
  36212         1,
  36213         0,
  36214         0x1802b020,
  36215         0,
  36216         0,
  36217         1,
  36218         soc_USBH_HCCONTROLHEADEDr_fields,
  36219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36220         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36221         -1,
  36222         -1,
  36223     },
  36224 #endif /* chips */
  36225 
  36226 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36227     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36228     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36229     defined(BCM_56260_B0)
  36230     { /* SOC_REG_INT_USBH_HCCONTROLHEADED_BCM53400_A0r */
  36231         soc_block_list[61],
  36232         soc_iprocreg,
  36233         1,
  36234         0,
  36235         0x18048820,
  36236         0,
  36237         0,
  36238         1,
  36239         soc_USBH_HCCONTROLHEADED_BCM53400_A0r_fields,
  36240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36241         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36242         -1,
  36243         -1,
  36244     },
  36245 #endif /* chips */
  36246 
  36247 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36248     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36249     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36250     defined(BCM_56260_B0)
  36251     { /* SOC_REG_INT_USBH_HCCONTROL_BCM53400_A0r */
  36252         soc_block_list[61],
  36253         soc_iprocreg,
  36254         1,
  36255         0,
  36256         0x18048804,
  36257         0,
  36258         0,
  36259         9,
  36260         soc_USBH_HCCONTROL_BCM53400_A0r_fields,
  36261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36262         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  36263         -1,
  36264         -1,
  36265     },
  36266 #endif /* chips */
  36267 
  36268 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36269     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36270     { /* SOC_REG_INT_USBH_HCCPARAMSr */
  36271         soc_block_list[61],
  36272         soc_iprocreg,
  36273         1,
  36274         0,
  36275         0x1802a008,
  36276         SOC_REG_FLAG_RO,
  36277         0,
  36278         5,
  36279         soc_USBH_HCCPARAMSr_fields,
  36280         SOC_RESET_VAL_DEC(0x0000a010, 0x00000000)
  36281         SOC_RESET_MASK_DEC(0x0000fff7, 0x00000000)
  36282         -1,
  36283         -1,
  36284     },
  36285 #endif /* chips */
  36286 
  36287 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36288     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36289     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36290     defined(BCM_56260_B0)
  36291     { /* SOC_REG_INT_USBH_HCCPARAMS_BCM53400_A0r */
  36292         soc_block_list[61],
  36293         soc_iprocreg,
  36294         1,
  36295         0,
  36296         0x18048008,
  36297         SOC_REG_FLAG_RO,
  36298         0,
  36299         5,
  36300         soc_USBH_HCCPARAMS_BCM53400_A0r_fields,
  36301         SOC_RESET_VAL_DEC(0x0000a010, 0x00000000)
  36302         SOC_RESET_MASK_DEC(0x0000fff7, 0x00000000)
  36303         -1,
  36304         -1,
  36305     },
  36306 #endif /* chips */
  36307 
  36308 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36309     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36310     { /* SOC_REG_INT_USBH_HCDONEHEADr */
  36311         soc_block_list[61],
  36312         soc_iprocreg,
  36313         1,
  36314         0,
  36315         0x1802b030,
  36316         SOC_REG_FLAG_RO,
  36317         0,
  36318         1,
  36319         soc_USBH_HCDONEHEADr_fields,
  36320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36321         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36322         -1,
  36323         -1,
  36324     },
  36325 #endif /* chips */
  36326 
  36327 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36328     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36329     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36330     defined(BCM_56260_B0)
  36331     { /* SOC_REG_INT_USBH_HCDONEHEAD_BCM53400_A0r */
  36332         soc_block_list[61],
  36333         soc_iprocreg,
  36334         1,
  36335         0,
  36336         0x18048830,
  36337         SOC_REG_FLAG_RO,
  36338         0,
  36339         1,
  36340         soc_USBH_HCDONEHEAD_BCM53400_A0r_fields,
  36341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36342         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36343         -1,
  36344         -1,
  36345     },
  36346 #endif /* chips */
  36347 
  36348 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36349     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36350     { /* SOC_REG_INT_USBH_HCFMINTERVALr */
  36351         soc_block_list[61],
  36352         soc_iprocreg,
  36353         1,
  36354         0,
  36355         0x1802b034,
  36356         0,
  36357         0,
  36358         3,
  36359         soc_USBH_HCFMINTERVALr_fields,
  36360         SOC_RESET_VAL_DEC(0x00002edf, 0x00000000)
  36361         SOC_RESET_MASK_DEC(0xffff3fff, 0x00000000)
  36362         -1,
  36363         -1,
  36364     },
  36365 #endif /* chips */
  36366 
  36367 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36368     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36369     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36370     defined(BCM_56260_B0)
  36371     { /* SOC_REG_INT_USBH_HCFMINTERVAL_BCM53400_A0r */
  36372         soc_block_list[61],
  36373         soc_iprocreg,
  36374         1,
  36375         0,
  36376         0x18048834,
  36377         0,
  36378         0,
  36379         3,
  36380         soc_USBH_HCFMINTERVAL_BCM53400_A0r_fields,
  36381         SOC_RESET_VAL_DEC(0x00002edf, 0x00000000)
  36382         SOC_RESET_MASK_DEC(0xffff3fff, 0x00000000)
  36383         -1,
  36384         -1,
  36385     },
  36386 #endif /* chips */
  36387 
  36388 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36389     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36390     { /* SOC_REG_INT_USBH_HCFMNUMBERr */
  36391         soc_block_list[61],
  36392         soc_iprocreg,
  36393         1,
  36394         0,
  36395         0x1802b03c,
  36396         0,
  36397         0,
  36398         1,
  36399         soc_USBH_HCFMNUMBERr_fields,
  36400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36401         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  36402         -1,
  36403         -1,
  36404     },
  36405 #endif /* chips */
  36406 
  36407 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36408     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36409     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36410     defined(BCM_56260_B0)
  36411     { /* SOC_REG_INT_USBH_HCFMNUMBER_BCM53400_A0r */
  36412         soc_block_list[61],
  36413         soc_iprocreg,
  36414         1,
  36415         0,
  36416         0x1804883c,
  36417         0,
  36418         0,
  36419         1,
  36420         soc_USBH_HCFMNUMBER_BCM53400_A0r_fields,
  36421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36422         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  36423         -1,
  36424         -1,
  36425     },
  36426 #endif /* chips */
  36427 
  36428 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36429     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36430     { /* SOC_REG_INT_USBH_HCFMREMAININGr */
  36431         soc_block_list[61],
  36432         soc_iprocreg,
  36433         1,
  36434         0,
  36435         0x1802b038,
  36436         0,
  36437         0,
  36438         2,
  36439         soc_USBH_HCFMREMAININGr_fields,
  36440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36441         SOC_RESET_MASK_DEC(0x80003fff, 0x00000000)
  36442         -1,
  36443         -1,
  36444     },
  36445 #endif /* chips */
  36446 
  36447 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36448     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36449     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36450     defined(BCM_56260_B0)
  36451     { /* SOC_REG_INT_USBH_HCFMREMAINING_BCM53400_A0r */
  36452         soc_block_list[61],
  36453         soc_iprocreg,
  36454         1,
  36455         0,
  36456         0x18048838,
  36457         0,
  36458         0,
  36459         2,
  36460         soc_USBH_HCFMREMAINING_BCM53400_A0r_fields,
  36461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36462         SOC_RESET_MASK_DEC(0x80003fff, 0x00000000)
  36463         -1,
  36464         -1,
  36465     },
  36466 #endif /* chips */
  36467 
  36468 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36469     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36470     { /* SOC_REG_INT_USBH_HCHCCAr */
  36471         soc_block_list[61],
  36472         soc_iprocreg,
  36473         1,
  36474         0,
  36475         0x1802b018,
  36476         0,
  36477         0,
  36478         1,
  36479         soc_USBH_HCHCCAr_fields,
  36480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36481         SOC_RESET_MASK_DEC(0xffffff00, 0x00000000)
  36482         -1,
  36483         -1,
  36484     },
  36485 #endif /* chips */
  36486 
  36487 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36488     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36489     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36490     defined(BCM_56260_B0)
  36491     { /* SOC_REG_INT_USBH_HCHCCA_BCM53400_A0r */
  36492         soc_block_list[61],
  36493         soc_iprocreg,
  36494         1,
  36495         0,
  36496         0x18048818,
  36497         0,
  36498         0,
  36499         1,
  36500         soc_USBH_HCHCCA_BCM53400_A0r_fields,
  36501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36502         SOC_RESET_MASK_DEC(0xffffff00, 0x00000000)
  36503         -1,
  36504         -1,
  36505     },
  36506 #endif /* chips */
  36507 
  36508 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36509     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36510     { /* SOC_REG_INT_USBH_HCINTERRUPTDISABLEr */
  36511         soc_block_list[61],
  36512         soc_iprocreg,
  36513         1,
  36514         0,
  36515         0x1802b014,
  36516         0,
  36517         0,
  36518         9,
  36519         soc_USBH_HCINTERRUPTDISABLEr_fields,
  36520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36521         SOC_RESET_MASK_DEC(0xc000007f, 0x00000000)
  36522         -1,
  36523         -1,
  36524     },
  36525 #endif /* chips */
  36526 
  36527 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36528     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36529     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36530     defined(BCM_56260_B0)
  36531     { /* SOC_REG_INT_USBH_HCINTERRUPTDISABLE_BCM53400_A0r */
  36532         soc_block_list[61],
  36533         soc_iprocreg,
  36534         1,
  36535         0,
  36536         0x18048814,
  36537         0,
  36538         0,
  36539         9,
  36540         soc_USBH_HCINTERRUPTDISABLE_BCM53400_A0r_fields,
  36541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36542         SOC_RESET_MASK_DEC(0xc000007f, 0x00000000)
  36543         -1,
  36544         -1,
  36545     },
  36546 #endif /* chips */
  36547 
  36548 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36549     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36550     { /* SOC_REG_INT_USBH_HCINTERRUPTENABLEr */
  36551         soc_block_list[61],
  36552         soc_iprocreg,
  36553         1,
  36554         0,
  36555         0x1802b010,
  36556         0,
  36557         0,
  36558         9,
  36559         soc_USBH_HCINTERRUPTDISABLEr_fields,
  36560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36561         SOC_RESET_MASK_DEC(0xc000007f, 0x00000000)
  36562         -1,
  36563         -1,
  36564     },
  36565 #endif /* chips */
  36566 
  36567 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36568     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36569     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36570     defined(BCM_56260_B0)
  36571     { /* SOC_REG_INT_USBH_HCINTERRUPTENABLE_BCM53400_A0r */
  36572         soc_block_list[61],
  36573         soc_iprocreg,
  36574         1,
  36575         0,
  36576         0x18048810,
  36577         0,
  36578         0,
  36579         9,
  36580         soc_USBH_HCINTERRUPTDISABLE_BCM53400_A0r_fields,
  36581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36582         SOC_RESET_MASK_DEC(0xc000007f, 0x00000000)
  36583         -1,
  36584         -1,
  36585     },
  36586 #endif /* chips */
  36587 
  36588 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36589     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36590     { /* SOC_REG_INT_USBH_HCINTERRUPTSTATUSr */
  36591         soc_block_list[61],
  36592         soc_iprocreg,
  36593         1,
  36594         0,
  36595         0x1802b00c,
  36596         0,
  36597         0,
  36598         8,
  36599         soc_USBH_HCINTERRUPTSTATUSr_fields,
  36600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36601         SOC_RESET_MASK_DEC(0x4000007f, 0x00000000)
  36602         -1,
  36603         -1,
  36604     },
  36605 #endif /* chips */
  36606 
  36607 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36608     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36609     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36610     defined(BCM_56260_B0)
  36611     { /* SOC_REG_INT_USBH_HCINTERRUPTSTATUS_BCM53400_A0r */
  36612         soc_block_list[61],
  36613         soc_iprocreg,
  36614         1,
  36615         0,
  36616         0x1804880c,
  36617         0,
  36618         0,
  36619         8,
  36620         soc_USBH_HCINTERRUPTSTATUS_BCM53400_A0r_fields,
  36621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36622         SOC_RESET_MASK_DEC(0x4000007f, 0x00000000)
  36623         -1,
  36624         -1,
  36625     },
  36626 #endif /* chips */
  36627 
  36628 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36629     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36630     { /* SOC_REG_INT_USBH_HCLSTHRESHOLDr */
  36631         soc_block_list[61],
  36632         soc_iprocreg,
  36633         1,
  36634         0,
  36635         0x1802b044,
  36636         0,
  36637         0,
  36638         1,
  36639         soc_USBH_HCLSTHRESHOLDr_fields,
  36640         SOC_RESET_VAL_DEC(0x00000628, 0x00000000)
  36641         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  36642         -1,
  36643         -1,
  36644     },
  36645 #endif /* chips */
  36646 
  36647 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36648     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36649     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36650     defined(BCM_56260_B0)
  36651     { /* SOC_REG_INT_USBH_HCLSTHRESHOLD_BCM53400_A0r */
  36652         soc_block_list[61],
  36653         soc_iprocreg,
  36654         1,
  36655         0,
  36656         0x18048844,
  36657         0,
  36658         0,
  36659         1,
  36660         soc_USBH_HCLSTHRESHOLD_BCM53400_A0r_fields,
  36661         SOC_RESET_VAL_DEC(0x00000628, 0x00000000)
  36662         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  36663         -1,
  36664         -1,
  36665     },
  36666 #endif /* chips */
  36667 
  36668 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36669     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36670     { /* SOC_REG_INT_USBH_HCPERIODCURRENTEDr */
  36671         soc_block_list[61],
  36672         soc_iprocreg,
  36673         1,
  36674         0,
  36675         0x1802b01c,
  36676         SOC_REG_FLAG_RO,
  36677         0,
  36678         1,
  36679         soc_USBH_HCPERIODCURRENTEDr_fields,
  36680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36681         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36682         -1,
  36683         -1,
  36684     },
  36685 #endif /* chips */
  36686 
  36687 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36688     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36689     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36690     defined(BCM_56260_B0)
  36691     { /* SOC_REG_INT_USBH_HCPERIODCURRENTED_BCM53400_A0r */
  36692         soc_block_list[61],
  36693         soc_iprocreg,
  36694         1,
  36695         0,
  36696         0x1804881c,
  36697         SOC_REG_FLAG_RO,
  36698         0,
  36699         1,
  36700         soc_USBH_HCPERIODCURRENTED_BCM53400_A0r_fields,
  36701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36702         SOC_RESET_MASK_DEC(0xfffffff0, 0x00000000)
  36703         -1,
  36704         -1,
  36705     },
  36706 #endif /* chips */
  36707 
  36708 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36709     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36710     { /* SOC_REG_INT_USBH_HCPERIODICSTARTr */
  36711         soc_block_list[61],
  36712         soc_iprocreg,
  36713         1,
  36714         0,
  36715         0x1802b040,
  36716         0,
  36717         0,
  36718         1,
  36719         soc_USBH_HCPERIODICSTARTr_fields,
  36720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36721         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  36722         -1,
  36723         -1,
  36724     },
  36725 #endif /* chips */
  36726 
  36727 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36728     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36729     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36730     defined(BCM_56260_B0)
  36731     { /* SOC_REG_INT_USBH_HCPERIODICSTART_BCM53400_A0r */
  36732         soc_block_list[61],
  36733         soc_iprocreg,
  36734         1,
  36735         0,
  36736         0x18048840,
  36737         0,
  36738         0,
  36739         1,
  36740         soc_USBH_HCPERIODICSTART_BCM53400_A0r_fields,
  36741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36742         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  36743         -1,
  36744         -1,
  36745     },
  36746 #endif /* chips */
  36747 
  36748 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36749     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36750     { /* SOC_REG_INT_USBH_HCREVISIONr */
  36751         soc_block_list[61],
  36752         soc_iprocreg,
  36753         1,
  36754         0,
  36755         0x1802b000,
  36756         SOC_REG_FLAG_RO,
  36757         0,
  36758         1,
  36759         soc_USBH_HCREVISIONr_fields,
  36760         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  36761         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  36762         -1,
  36763         -1,
  36764     },
  36765 #endif /* chips */
  36766 
  36767 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36768     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36769     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36770     defined(BCM_56260_B0)
  36771     { /* SOC_REG_INT_USBH_HCREVISION_BCM53400_A0r */
  36772         soc_block_list[61],
  36773         soc_iprocreg,
  36774         1,
  36775         0,
  36776         0x18048800,
  36777         SOC_REG_FLAG_RO,
  36778         0,
  36779         1,
  36780         soc_USBH_HCREVISION_BCM53400_A0r_fields,
  36781         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  36782         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  36783         -1,
  36784         -1,
  36785     },
  36786 #endif /* chips */
  36787 
  36788 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36789     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36790     { /* SOC_REG_INT_USBH_HCRHDESCRIPTORAr */
  36791         soc_block_list[61],
  36792         soc_iprocreg,
  36793         1,
  36794         0,
  36795         0x1802b048,
  36796         0,
  36797         0,
  36798         7,
  36799         soc_USBH_HCRHDESCRIPTORAr_fields,
  36800         SOC_RESET_VAL_DEC(0x02000002, 0x00000000)
  36801         SOC_RESET_MASK_DEC(0xff001fff, 0x00000000)
  36802         -1,
  36803         -1,
  36804     },
  36805 #endif /* chips */
  36806 
  36807 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36808     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36809     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36810     defined(BCM_56260_B0)
  36811     { /* SOC_REG_INT_USBH_HCRHDESCRIPTORA_BCM53400_A0r */
  36812         soc_block_list[61],
  36813         soc_iprocreg,
  36814         1,
  36815         0,
  36816         0x18048848,
  36817         0,
  36818         0,
  36819         7,
  36820         soc_USBH_HCRHDESCRIPTORA_BCM53400_A0r_fields,
  36821         SOC_RESET_VAL_DEC(0x02000003, 0x00000000)
  36822         SOC_RESET_MASK_DEC(0xff001fff, 0x00000000)
  36823         -1,
  36824         -1,
  36825     },
  36826 #endif /* chips */
  36827 
  36828 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36829     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36830     { /* SOC_REG_INT_USBH_HCRHDESCRIPTORBr */
  36831         soc_block_list[61],
  36832         soc_iprocreg,
  36833         1,
  36834         0,
  36835         0x1802b04c,
  36836         0,
  36837         0,
  36838         2,
  36839         soc_USBH_HCRHDESCRIPTORBr_fields,
  36840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36841         SOC_RESET_MASK_DEC(0x00060006, 0x00000000)
  36842         -1,
  36843         -1,
  36844     },
  36845 #endif /* chips */
  36846 
  36847 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36848     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36849     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36850     defined(BCM_56260_B0)
  36851     { /* SOC_REG_INT_USBH_HCRHDESCRIPTORB_BCM53400_A0r */
  36852         soc_block_list[61],
  36853         soc_iprocreg,
  36854         1,
  36855         0,
  36856         0x1804884c,
  36857         0,
  36858         0,
  36859         2,
  36860         soc_USBH_HCRHDESCRIPTORB_BCM53400_A0r_fields,
  36861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36862         SOC_RESET_MASK_DEC(0x00060006, 0x00000000)
  36863         -1,
  36864         -1,
  36865     },
  36866 #endif /* chips */
  36867 
  36868 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36869     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36870     { /* SOC_REG_INT_USBH_HCRHPORT00r */
  36871         soc_block_list[61],
  36872         soc_iprocreg,
  36873         1,
  36874         0,
  36875         0x1802b054,
  36876         0,
  36877         0,
  36878         12,
  36879         soc_USBH_HCRHPORT00r_fields,
  36880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36881         SOC_RESET_MASK_DEC(0x001f031f, 0x00000000)
  36882         -1,
  36883         -1,
  36884     },
  36885 #endif /* chips */
  36886 
  36887 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36888     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36889     { /* SOC_REG_INT_USBH_HCRHPORT01r */
  36890         soc_block_list[61],
  36891         soc_iprocreg,
  36892         1,
  36893         0,
  36894         0x1802b058,
  36895         0,
  36896         0,
  36897         12,
  36898         soc_USBH_HCRHPORT00r_fields,
  36899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36900         SOC_RESET_MASK_DEC(0x001f031f, 0x00000000)
  36901         -1,
  36902         -1,
  36903     },
  36904 #endif /* chips */
  36905 
  36906 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36907     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36908     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36909     defined(BCM_56260_B0)
  36910     { /* SOC_REG_INT_USBH_HCRHPORT02r */
  36911         soc_block_list[61],
  36912         soc_iprocreg,
  36913         1,
  36914         0,
  36915         0x1804885c,
  36916         0,
  36917         0,
  36918         12,
  36919         soc_USBH_HCRHPORT00_BCM53400_A0r_fields,
  36920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36921         SOC_RESET_MASK_DEC(0x001f031f, 0x00000000)
  36922         -1,
  36923         -1,
  36924     },
  36925 #endif /* chips */
  36926 
  36927 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36928     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36929     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36930     defined(BCM_56260_B0)
  36931     { /* SOC_REG_INT_USBH_HCRHPORT00_BCM53400_A0r */
  36932         soc_block_list[61],
  36933         soc_iprocreg,
  36934         1,
  36935         0,
  36936         0x18048854,
  36937         0,
  36938         0,
  36939         12,
  36940         soc_USBH_HCRHPORT00_BCM53400_A0r_fields,
  36941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36942         SOC_RESET_MASK_DEC(0x001f031f, 0x00000000)
  36943         -1,
  36944         -1,
  36945     },
  36946 #endif /* chips */
  36947 
  36948 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36949     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36950     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36951     defined(BCM_56260_B0)
  36952     { /* SOC_REG_INT_USBH_HCRHPORT01_BCM53400_A0r */
  36953         soc_block_list[61],
  36954         soc_iprocreg,
  36955         1,
  36956         0,
  36957         0x18048858,
  36958         0,
  36959         0,
  36960         12,
  36961         soc_USBH_HCRHPORT00_BCM53400_A0r_fields,
  36962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36963         SOC_RESET_MASK_DEC(0x001f031f, 0x00000000)
  36964         -1,
  36965         -1,
  36966     },
  36967 #endif /* chips */
  36968 
  36969 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  36970     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  36971     { /* SOC_REG_INT_USBH_HCRHSTATUSr */
  36972         soc_block_list[61],
  36973         soc_iprocreg,
  36974         1,
  36975         0,
  36976         0x1802b050,
  36977         0,
  36978         0,
  36979         6,
  36980         soc_USBH_HCRHSTATUSr_fields,
  36981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36982         SOC_RESET_MASK_DEC(0x80038003, 0x00000000)
  36983         -1,
  36984         -1,
  36985     },
  36986 #endif /* chips */
  36987 
  36988 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36989     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36990     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36991     defined(BCM_56260_B0)
  36992     { /* SOC_REG_INT_USBH_HCRHSTATUS_BCM53400_A0r */
  36993         soc_block_list[61],
  36994         soc_iprocreg,
  36995         1,
  36996         0,
  36997         0x18048850,
  36998         0,
  36999         0,
  37000         6,
  37001         soc_USBH_HCRHSTATUS_BCM53400_A0r_fields,
  37002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37003         SOC_RESET_MASK_DEC(0x80038003, 0x00000000)
  37004         -1,
  37005         -1,
  37006     },
  37007 #endif /* chips */
  37008 
  37009 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37010     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37011     { /* SOC_REG_INT_USBH_HCSPARAMSr */
  37012         soc_block_list[61],
  37013         soc_iprocreg,
  37014         1,
  37015         0,
  37016         0x1802a004,
  37017         SOC_REG_FLAG_RO,
  37018         0,
  37019         7,
  37020         soc_USBH_HCSPARAMSr_fields,
  37021         SOC_RESET_VAL_DEC(0x00001212, 0x00000000)
  37022         SOC_RESET_MASK_DEC(0x00f1ff9f, 0x00000000)
  37023         -1,
  37024         -1,
  37025     },
  37026 #endif /* chips */
  37027 
  37028 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37029     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37030     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37031     defined(BCM_56260_B0)
  37032     { /* SOC_REG_INT_USBH_HCSPARAMS_BCM53400_A0r */
  37033         soc_block_list[61],
  37034         soc_iprocreg,
  37035         1,
  37036         0,
  37037         0x18048004,
  37038         SOC_REG_FLAG_RO,
  37039         0,
  37040         7,
  37041         soc_USBH_HCSPARAMS_BCM53400_A0r_fields,
  37042         SOC_RESET_VAL_DEC(0x00001212, 0x00000000)
  37043         SOC_RESET_MASK_DEC(0x00f1ff9f, 0x00000000)
  37044         -1,
  37045         -1,
  37046     },
  37047 #endif /* chips */
  37048 
  37049 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37050     { /* SOC_REG_INT_USBH_INSNREG00r */
  37051         soc_block_list[61],
  37052         soc_iprocreg,
  37053         1,
  37054         0,
  37055         0x1802a090,
  37056         0,
  37057         0,
  37058         1,
  37059         soc_USBH_INSNREG00r_fields,
  37060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37061         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  37062         -1,
  37063         -1,
  37064     },
  37065 #endif /* chips */
  37066 
  37067 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37068     { /* SOC_REG_INT_USBH_INSNREG01r */
  37069         soc_block_list[61],
  37070         soc_iprocreg,
  37071         1,
  37072         0,
  37073         0x1802a094,
  37074         0,
  37075         0,
  37076         2,
  37077         soc_USBH_INSNREG01r_fields,
  37078         SOC_RESET_VAL_DEC(0x00400040, 0x00000000)
  37079         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37080         -1,
  37081         -1,
  37082     },
  37083 #endif /* chips */
  37084 
  37085 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37086     { /* SOC_REG_INT_USBH_INSNREG02r */
  37087         soc_block_list[61],
  37088         soc_iprocreg,
  37089         1,
  37090         0,
  37091         0x1802a098,
  37092         0,
  37093         0,
  37094         1,
  37095         soc_USBH_INSNREG02r_fields,
  37096         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  37097         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  37098         -1,
  37099         -1,
  37100     },
  37101 #endif /* chips */
  37102 
  37103 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37104     { /* SOC_REG_INT_USBH_INSNREG03r */
  37105         soc_block_list[61],
  37106         soc_iprocreg,
  37107         1,
  37108         0,
  37109         0x1802a09c,
  37110         0,
  37111         0,
  37112         4,
  37113         soc_USBH_INSNREG03r_fields,
  37114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37115         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  37116         -1,
  37117         -1,
  37118     },
  37119 #endif /* chips */
  37120 
  37121 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37122     { /* SOC_REG_INT_USBH_INSNREG04r */
  37123         soc_block_list[61],
  37124         soc_iprocreg,
  37125         1,
  37126         0,
  37127         0x1802a0a0,
  37128         0,
  37129         0,
  37130         6,
  37131         soc_USBH_INSNREG04r_fields,
  37132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37133         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  37134         -1,
  37135         -1,
  37136     },
  37137 #endif /* chips */
  37138 
  37139 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37140     { /* SOC_REG_INT_USBH_INSNREG05r */
  37141         soc_block_list[61],
  37142         soc_iprocreg,
  37143         1,
  37144         0,
  37145         0x1802a0a4,
  37146         0,
  37147         0,
  37148         6,
  37149         soc_USBH_INSNREG05r_fields,
  37150         SOC_RESET_VAL_DEC(0x00001000, 0x00000000)
  37151         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37152         -1,
  37153         -1,
  37154     },
  37155 #endif /* chips */
  37156 
  37157 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37158     { /* SOC_REG_INT_USBH_INSNREG06r */
  37159         soc_block_list[61],
  37160         soc_iprocreg,
  37161         1,
  37162         0,
  37163         0x1802a0a8,
  37164         0,
  37165         0,
  37166         5,
  37167         soc_USBH_INSNREG06r_fields,
  37168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37169         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37170         -1,
  37171         -1,
  37172     },
  37173 #endif /* chips */
  37174 
  37175 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37176     { /* SOC_REG_INT_USBH_INSNREG07r */
  37177         soc_block_list[61],
  37178         soc_iprocreg,
  37179         1,
  37180         0,
  37181         0x1802a0ac,
  37182         SOC_REG_FLAG_RO,
  37183         0,
  37184         1,
  37185         soc_USBH_INSNREG07r_fields,
  37186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37187         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37188         -1,
  37189         -1,
  37190     },
  37191 #endif /* chips */
  37192 
  37193 #if defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37194     { /* SOC_REG_INT_USBH_INSNREG08r */
  37195         soc_block_list[61],
  37196         soc_iprocreg,
  37197         1,
  37198         0,
  37199         0x1802a0b0,
  37200         0,
  37201         0,
  37202         1,
  37203         soc_USBH_INSNREG08r_fields,
  37204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37205         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37206         -1,
  37207         -1,
  37208     },
  37209 #endif /* chips */
  37210 
  37211 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37212     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37213     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37214     defined(BCM_56260_B0)
  37215     { /* SOC_REG_INT_USBH_INSNREG00_BCM53400_A0r */
  37216         soc_block_list[61],
  37217         soc_iprocreg,
  37218         1,
  37219         0,
  37220         0x18048090,
  37221         0,
  37222         0,
  37223         1,
  37224         soc_USBH_INSNREG00_BCM53400_A0r_fields,
  37225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37226         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  37227         -1,
  37228         -1,
  37229     },
  37230 #endif /* chips */
  37231 
  37232 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37233     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37234     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37235     defined(BCM_56260_B0)
  37236     { /* SOC_REG_INT_USBH_INSNREG01_BCM53400_A0r */
  37237         soc_block_list[61],
  37238         soc_iprocreg,
  37239         1,
  37240         0,
  37241         0x18048094,
  37242         0,
  37243         0,
  37244         2,
  37245         soc_USBH_INSNREG01_BCM53400_A0r_fields,
  37246         SOC_RESET_VAL_DEC(0x00400040, 0x00000000)
  37247         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37248         -1,
  37249         -1,
  37250     },
  37251 #endif /* chips */
  37252 
  37253 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37254     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37255     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37256     defined(BCM_56260_B0)
  37257     { /* SOC_REG_INT_USBH_INSNREG02_BCM53400_A0r */
  37258         soc_block_list[61],
  37259         soc_iprocreg,
  37260         1,
  37261         0,
  37262         0x18048098,
  37263         0,
  37264         0,
  37265         1,
  37266         soc_USBH_INSNREG02_BCM53400_A0r_fields,
  37267         SOC_RESET_VAL_DEC(0x00000100, 0x00000000)
  37268         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  37269         -1,
  37270         -1,
  37271     },
  37272 #endif /* chips */
  37273 
  37274 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37275     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37276     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37277     defined(BCM_56260_B0)
  37278     { /* SOC_REG_INT_USBH_INSNREG03_BCM53400_A0r */
  37279         soc_block_list[61],
  37280         soc_iprocreg,
  37281         1,
  37282         0,
  37283         0x1804809c,
  37284         0,
  37285         0,
  37286         7,
  37287         soc_USBH_INSNREG03_BCM53400_A0r_fields,
  37288         SOC_RESET_VAL_DEC(0x00002001, 0x00000000)
  37289         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  37290         -1,
  37291         -1,
  37292     },
  37293 #endif /* chips */
  37294 
  37295 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37296     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37297     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37298     defined(BCM_56260_B0)
  37299     { /* SOC_REG_INT_USBH_INSNREG04_BCM53400_A0r */
  37300         soc_block_list[61],
  37301         soc_iprocreg,
  37302         1,
  37303         0,
  37304         0x180480a0,
  37305         0,
  37306         0,
  37307         7,
  37308         soc_USBH_INSNREG04_BCM53400_A0r_fields,
  37309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37310         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  37311         -1,
  37312         -1,
  37313     },
  37314 #endif /* chips */
  37315 
  37316 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37317     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37318     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37319     defined(BCM_56260_B0)
  37320     { /* SOC_REG_INT_USBH_INSNREG05_BCM53400_A0r */
  37321         soc_block_list[61],
  37322         soc_iprocreg,
  37323         1,
  37324         0,
  37325         0x180480a4,
  37326         0,
  37327         0,
  37328         6,
  37329         soc_USBH_INSNREG05_BCM53400_A0r_fields,
  37330         SOC_RESET_VAL_DEC(0x00001000, 0x00000000)
  37331         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37332         -1,
  37333         -1,
  37334     },
  37335 #endif /* chips */
  37336 
  37337 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37338     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37339     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37340     defined(BCM_56260_B0)
  37341     { /* SOC_REG_INT_USBH_INSNREG06_BCM53400_A0r */
  37342         soc_block_list[61],
  37343         soc_iprocreg,
  37344         1,
  37345         0,
  37346         0x180480a8,
  37347         0,
  37348         0,
  37349         5,
  37350         soc_USBH_INSNREG06_BCM53400_A0r_fields,
  37351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37352         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37353         -1,
  37354         -1,
  37355     },
  37356 #endif /* chips */
  37357 
  37358 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37359     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37360     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37361     defined(BCM_56260_B0)
  37362     { /* SOC_REG_INT_USBH_INSNREG07_BCM53400_A0r */
  37363         soc_block_list[61],
  37364         soc_iprocreg,
  37365         1,
  37366         0,
  37367         0x180480ac,
  37368         SOC_REG_FLAG_RO,
  37369         0,
  37370         1,
  37371         soc_USBH_INSNREG07_BCM53400_A0r_fields,
  37372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37373         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37374         -1,
  37375         -1,
  37376     },
  37377 #endif /* chips */
  37378 
  37379 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37380     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37381     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37382     defined(BCM_56260_B0)
  37383     { /* SOC_REG_INT_USBH_INSNREG08_BCM53400_A0r */
  37384         soc_block_list[61],
  37385         soc_iprocreg,
  37386         1,
  37387         0,
  37388         0x180480b0,
  37389         0,
  37390         0,
  37391         1,
  37392         soc_USBH_INSNREG08_BCM53400_A0r_fields,
  37393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37394         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37395         -1,
  37396         -1,
  37397     },
  37398 #endif /* chips */
  37399 
  37400 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37401     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37402     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37403     defined(BCM_56260_B0)
  37404     { /* SOC_REG_INT_USBH_INTR_CONTROLr */
  37405         soc_block_list[61],
  37406         soc_iprocreg,
  37407         1,
  37408         0,
  37409         0x1804970c,
  37410         0,
  37411         0,
  37412         2,
  37413         soc_USBH_INTR_CONTROLr_fields,
  37414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37415         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  37416         -1,
  37417         -1,
  37418     },
  37419 #endif /* chips */
  37420 
  37421 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37422     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37423     { /* SOC_REG_INT_USBH_MDIO_CTRLr */
  37424         soc_block_list[61],
  37425         soc_iprocreg,
  37426         1,
  37427         0,
  37428         0x1802a524,
  37429         0,
  37430         0,
  37431         6,
  37432         soc_USBH_MDIO_CTRLr_fields,
  37433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37434         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  37435         -1,
  37436         -1,
  37437     },
  37438 #endif /* chips */
  37439 
  37440 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37441     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37442     { /* SOC_REG_INT_USBH_MDIO_RDDATr */
  37443         soc_block_list[61],
  37444         soc_iprocreg,
  37445         1,
  37446         0,
  37447         0x1802a528,
  37448         SOC_REG_FLAG_RO,
  37449         0,
  37450         2,
  37451         soc_USBH_MDIO_RDDATr_fields,
  37452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37453         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  37454         -1,
  37455         -1,
  37456     },
  37457 #endif /* chips */
  37458 
  37459 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37460     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37461     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37462     defined(BCM_56260_B0)
  37463     { /* SOC_REG_INT_USBH_OHCI_CCS_STSr */
  37464         soc_block_list[61],
  37465         soc_iprocreg,
  37466         1,
  37467         0,
  37468         0x18049704,
  37469         SOC_REG_FLAG_RO,
  37470         0,
  37471         1,
  37472         soc_USBH_OHCI_CCS_STSr_fields,
  37473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37474         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  37475         -1,
  37476         -1,
  37477     },
  37478 #endif /* chips */
  37479 
  37480 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37481     defined(BCM_53570_A0) || defined(BCM_56160_A0) || \
  37482     defined(BCM_56260_A0) || defined(BCM_56260_B0)
  37483     { /* SOC_REG_INT_USBH_OHCI_EHCI_STRAPr */
  37484         soc_block_list[61],
  37485         soc_iprocreg,
  37486         1,
  37487         0,
  37488         0x18049700,
  37489         0,
  37490         0,
  37491         10,
  37492         soc_USBH_OHCI_EHCI_STRAPr_fields,
  37493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37494         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  37495         -1,
  37496         -1,
  37497     },
  37498 #endif /* chips */
  37499 
  37500 #if defined(BCM_53570_B0)
  37501     { /* SOC_REG_INT_USBH_OHCI_EHCI_STRAP_BCM53570_B0r */
  37502         soc_block_list[61],
  37503         soc_iprocreg,
  37504         1,
  37505         0,
  37506         0x18049700,
  37507         0,
  37508         0,
  37509         11,
  37510         soc_USBH_OHCI_EHCI_STRAP_BCM53570_B0r_fields,
  37511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37512         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  37513         -1,
  37514         -1,
  37515     },
  37516 #endif /* chips */
  37517 
  37518 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37519     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37520     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37521     defined(BCM_56260_B0)
  37522     { /* SOC_REG_INT_USBH_OHCI_PWR_STSr */
  37523         soc_block_list[61],
  37524         soc_iprocreg,
  37525         1,
  37526         0,
  37527         0x18049604,
  37528         SOC_REG_FLAG_RO,
  37529         0,
  37530         1,
  37531         soc_USBH_OHCI_PWR_STSr_fields,
  37532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37533         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  37534         -1,
  37535         -1,
  37536     },
  37537 #endif /* chips */
  37538 
  37539 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37540     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37541     { /* SOC_REG_INT_USBH_PERIODICLISTBASEr */
  37542         soc_block_list[61],
  37543         soc_iprocreg,
  37544         1,
  37545         0,
  37546         0x1802a024,
  37547         0,
  37548         0,
  37549         1,
  37550         soc_USBH_PERIODICLISTBASEr_fields,
  37551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37552         SOC_RESET_MASK_DEC(0xfffff000, 0x00000000)
  37553         -1,
  37554         -1,
  37555     },
  37556 #endif /* chips */
  37557 
  37558 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37559     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37560     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37561     defined(BCM_56260_B0)
  37562     { /* SOC_REG_INT_USBH_PERIODICLISTBASE_BCM53400_A0r */
  37563         soc_block_list[61],
  37564         soc_iprocreg,
  37565         1,
  37566         0,
  37567         0x18048024,
  37568         0,
  37569         0,
  37570         1,
  37571         soc_USBH_PERIODICLISTBASE_BCM53400_A0r_fields,
  37572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37573         SOC_RESET_MASK_DEC(0xfffff000, 0x00000000)
  37574         -1,
  37575         -1,
  37576     },
  37577 #endif /* chips */
  37578 
  37579 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37580     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37581     { /* SOC_REG_INT_USBH_PHY_CTRL_P0r */
  37582         soc_block_list[61],
  37583         soc_iprocreg,
  37584         1,
  37585         0,
  37586         0x1802a200,
  37587         0,
  37588         0,
  37589         6,
  37590         soc_USBH_PHY_CTRL_P0r_fields,
  37591         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  37592         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  37593         -1,
  37594         -1,
  37595     },
  37596 #endif /* chips */
  37597 
  37598 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37599     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37600     { /* SOC_REG_INT_USBH_PHY_CTRL_P1r */
  37601         soc_block_list[61],
  37602         soc_iprocreg,
  37603         1,
  37604         0,
  37605         0x1802a204,
  37606         0,
  37607         0,
  37608         6,
  37609         soc_USBH_PHY_CTRL_P0r_fields,
  37610         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  37611         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  37612         -1,
  37613         -1,
  37614     },
  37615 #endif /* chips */
  37616 
  37617 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37618     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37619     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37620     defined(BCM_56260_B0)
  37621     { /* SOC_REG_INT_USBH_PHY_CTRL_P2r */
  37622         soc_block_list[61],
  37623         soc_iprocreg,
  37624         1,
  37625         0,
  37626         0x18049208,
  37627         0,
  37628         0,
  37629         6,
  37630         soc_USBH_PHY_CTRL_P0_BCM53400_A0r_fields,
  37631         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  37632         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  37633         -1,
  37634         -1,
  37635     },
  37636 #endif /* chips */
  37637 
  37638 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37639     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37640     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37641     defined(BCM_56260_B0)
  37642     { /* SOC_REG_INT_USBH_PHY_CTRL_P0_BCM53400_A0r */
  37643         soc_block_list[61],
  37644         soc_iprocreg,
  37645         1,
  37646         0,
  37647         0x18049200,
  37648         0,
  37649         0,
  37650         6,
  37651         soc_USBH_PHY_CTRL_P0_BCM53400_A0r_fields,
  37652         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  37653         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  37654         -1,
  37655         -1,
  37656     },
  37657 #endif /* chips */
  37658 
  37659 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37660     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37661     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37662     defined(BCM_56260_B0)
  37663     { /* SOC_REG_INT_USBH_PHY_CTRL_P1_BCM53400_A0r */
  37664         soc_block_list[61],
  37665         soc_iprocreg,
  37666         1,
  37667         0,
  37668         0x18049204,
  37669         0,
  37670         0,
  37671         6,
  37672         soc_USBH_PHY_CTRL_P0_BCM53400_A0r_fields,
  37673         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  37674         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  37675         -1,
  37676         -1,
  37677     },
  37678 #endif /* chips */
  37679 
  37680 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37681     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37682     { /* SOC_REG_INT_USBH_PORTSC_0r */
  37683         soc_block_list[61],
  37684         soc_iprocreg,
  37685         1,
  37686         0,
  37687         0x1802a054,
  37688         0,
  37689         0,
  37690         17,
  37691         soc_USBH_PORTSC_0r_fields,
  37692         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
  37693         SOC_RESET_MASK_DEC(0x007ffdff, 0x00000000)
  37694         -1,
  37695         -1,
  37696     },
  37697 #endif /* chips */
  37698 
  37699 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37700     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37701     { /* SOC_REG_INT_USBH_PORTSC_1r */
  37702         soc_block_list[61],
  37703         soc_iprocreg,
  37704         1,
  37705         0,
  37706         0x1802a058,
  37707         0,
  37708         0,
  37709         17,
  37710         soc_USBH_PORTSC_0r_fields,
  37711         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
  37712         SOC_RESET_MASK_DEC(0x007ffdff, 0x00000000)
  37713         -1,
  37714         -1,
  37715     },
  37716 #endif /* chips */
  37717 
  37718 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37719     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37720     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37721     defined(BCM_56260_B0)
  37722     { /* SOC_REG_INT_USBH_PORTSC_2r */
  37723         soc_block_list[61],
  37724         soc_iprocreg,
  37725         1,
  37726         0,
  37727         0x1804805c,
  37728         0,
  37729         0,
  37730         17,
  37731         soc_USBH_PORTSC_0_BCM53400_A0r_fields,
  37732         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
  37733         SOC_RESET_MASK_DEC(0x007ffdff, 0x00000000)
  37734         -1,
  37735         -1,
  37736     },
  37737 #endif /* chips */
  37738 
  37739 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37740     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37741     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37742     defined(BCM_56260_B0)
  37743     { /* SOC_REG_INT_USBH_PORTSC_0_BCM53400_A0r */
  37744         soc_block_list[61],
  37745         soc_iprocreg,
  37746         1,
  37747         0,
  37748         0x18048054,
  37749         0,
  37750         0,
  37751         17,
  37752         soc_USBH_PORTSC_0_BCM53400_A0r_fields,
  37753         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
  37754         SOC_RESET_MASK_DEC(0x007ffdff, 0x00000000)
  37755         -1,
  37756         -1,
  37757     },
  37758 #endif /* chips */
  37759 
  37760 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37761     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37762     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37763     defined(BCM_56260_B0)
  37764     { /* SOC_REG_INT_USBH_PORTSC_1_BCM53400_A0r */
  37765         soc_block_list[61],
  37766         soc_iprocreg,
  37767         1,
  37768         0,
  37769         0x18048058,
  37770         0,
  37771         0,
  37772         17,
  37773         soc_USBH_PORTSC_0_BCM53400_A0r_fields,
  37774         SOC_RESET_VAL_DEC(0x00002000, 0x00000000)
  37775         SOC_RESET_MASK_DEC(0x007ffdff, 0x00000000)
  37776         -1,
  37777         -1,
  37778     },
  37779 #endif /* chips */
  37780 
  37781 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37782     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37783     { /* SOC_REG_INT_USBH_SB_ADDRHIr */
  37784         soc_block_list[61],
  37785         soc_iprocreg,
  37786         1,
  37787         0,
  37788         0x1802a320,
  37789         0,
  37790         0,
  37791         1,
  37792         soc_USBH_SB_ADDRHIr_fields,
  37793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37794         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37795         -1,
  37796         -1,
  37797     },
  37798 #endif /* chips */
  37799 
  37800 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37801     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37802     { /* SOC_REG_INT_USBH_SHIM_CTRLr */
  37803         soc_block_list[61],
  37804         soc_iprocreg,
  37805         1,
  37806         0,
  37807         0x1802a304,
  37808         0,
  37809         0,
  37810         6,
  37811         soc_USBH_SHIM_CTRLr_fields,
  37812         SOC_RESET_VAL_DEC(0x000009ff, 0x00000000)
  37813         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  37814         -1,
  37815         -1,
  37816     },
  37817 #endif /* chips */
  37818 
  37819 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37820     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37821     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37822     defined(BCM_56260_B0)
  37823     { /* SOC_REG_INT_USBH_SHIM_CTRL_BCM53400_A0r */
  37824         soc_block_list[61],
  37825         soc_iprocreg,
  37826         1,
  37827         0,
  37828         0x18049304,
  37829         0,
  37830         0,
  37831         6,
  37832         soc_USBH_SHIM_CTRL_BCM53400_A0r_fields,
  37833         SOC_RESET_VAL_DEC(0x000009ff, 0x00000000)
  37834         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  37835         -1,
  37836         -1,
  37837     },
  37838 #endif /* chips */
  37839 
  37840 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37841     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37842     { /* SOC_REG_INT_USBH_SHIM_MASTER_STATUSr */
  37843         soc_block_list[61],
  37844         soc_iprocreg,
  37845         1,
  37846         0,
  37847         0x1802a30c,
  37848         0,
  37849         0,
  37850         3,
  37851         soc_USBH_SHIM_MASTER_STATUSr_fields,
  37852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37853         SOC_RESET_MASK_DEC(0x0000007d, 0x00000000)
  37854         -1,
  37855         -1,
  37856     },
  37857 #endif /* chips */
  37858 
  37859 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37860     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37861     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37862     defined(BCM_56260_B0)
  37863     { /* SOC_REG_INT_USBH_SHIM_MASTER_STATUS_BCM53400_A0r */
  37864         soc_block_list[61],
  37865         soc_iprocreg,
  37866         1,
  37867         0,
  37868         0x1804930c,
  37869         0,
  37870         0,
  37871         3,
  37872         soc_USBH_SHIM_MASTER_STATUS_BCM53400_A0r_fields,
  37873         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37874         SOC_RESET_MASK_DEC(0x0000007d, 0x00000000)
  37875         -1,
  37876         -1,
  37877     },
  37878 #endif /* chips */
  37879 
  37880 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37881     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37882     { /* SOC_REG_INT_USBH_SHIM_SLAVE_STATUSr */
  37883         soc_block_list[61],
  37884         soc_iprocreg,
  37885         1,
  37886         0,
  37887         0x1802a308,
  37888         0,
  37889         0,
  37890         4,
  37891         soc_USBH_SHIM_SLAVE_STATUSr_fields,
  37892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37893         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  37894         -1,
  37895         -1,
  37896     },
  37897 #endif /* chips */
  37898 
  37899 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37900     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37901     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37902     defined(BCM_56260_B0)
  37903     { /* SOC_REG_INT_USBH_SHIM_SLAVE_STATUS_BCM53400_A0r */
  37904         soc_block_list[61],
  37905         soc_iprocreg,
  37906         1,
  37907         0,
  37908         0x18049308,
  37909         0,
  37910         0,
  37911         4,
  37912         soc_USBH_SHIM_SLAVE_STATUS_BCM53400_A0r_fields,
  37913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37914         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  37915         -1,
  37916         -1,
  37917     },
  37918 #endif /* chips */
  37919 
  37920 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37921     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37922     { /* SOC_REG_INT_USBH_TP_CTLr */
  37923         soc_block_list[61],
  37924         soc_iprocreg,
  37925         1,
  37926         0,
  37927         0x1802a514,
  37928         0,
  37929         0,
  37930         4,
  37931         soc_USBH_TP_CTLr_fields,
  37932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37933         SOC_RESET_MASK_DEC(0xff0f0f1f, 0x00000000)
  37934         -1,
  37935         -1,
  37936     },
  37937 #endif /* chips */
  37938 
  37939 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37940     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37941     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37942     defined(BCM_56260_B0)
  37943     { /* SOC_REG_INT_USBH_TP_CTL_BCM53400_A0r */
  37944         soc_block_list[61],
  37945         soc_iprocreg,
  37946         1,
  37947         0,
  37948         0x18049514,
  37949         0,
  37950         0,
  37951         4,
  37952         soc_USBH_TP_CTL_BCM53400_A0r_fields,
  37953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37954         SOC_RESET_MASK_DEC(0xff0f0f1f, 0x00000000)
  37955         -1,
  37956         -1,
  37957     },
  37958 #endif /* chips */
  37959 
  37960 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37961     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37962     { /* SOC_REG_INT_USBH_TP_OUTP0r */
  37963         soc_block_list[61],
  37964         soc_iprocreg,
  37965         1,
  37966         0,
  37967         0x1802a538,
  37968         SOC_REG_FLAG_RO,
  37969         0,
  37970         1,
  37971         soc_USBH_TP_OUTP0r_fields,
  37972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37973         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37974         -1,
  37975         -1,
  37976     },
  37977 #endif /* chips */
  37978 
  37979 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  37980     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  37981     { /* SOC_REG_INT_USBH_TP_OUTP1r */
  37982         soc_block_list[61],
  37983         soc_iprocreg,
  37984         1,
  37985         0,
  37986         0x1802a53c,
  37987         SOC_REG_FLAG_RO,
  37988         0,
  37989         1,
  37990         soc_USBH_TP_OUTP0r_fields,
  37991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37992         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37993         -1,
  37994         -1,
  37995     },
  37996 #endif /* chips */
  37997 
  37998 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37999     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38000     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38001     defined(BCM_56260_B0)
  38002     { /* SOC_REG_INT_USBH_TP_OUTP2r */
  38003         soc_block_list[61],
  38004         soc_iprocreg,
  38005         1,
  38006         0,
  38007         0x18049540,
  38008         SOC_REG_FLAG_RO,
  38009         0,
  38010         1,
  38011         soc_USBH_TP_OUTP0_BCM53400_A0r_fields,
  38012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38013         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38014         -1,
  38015         -1,
  38016     },
  38017 #endif /* chips */
  38018 
  38019 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38020     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38021     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38022     defined(BCM_56260_B0)
  38023     { /* SOC_REG_INT_USBH_TP_OUTP0_BCM53400_A0r */
  38024         soc_block_list[61],
  38025         soc_iprocreg,
  38026         1,
  38027         0,
  38028         0x18049538,
  38029         SOC_REG_FLAG_RO,
  38030         0,
  38031         1,
  38032         soc_USBH_TP_OUTP0_BCM53400_A0r_fields,
  38033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38034         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38035         -1,
  38036         -1,
  38037     },
  38038 #endif /* chips */
  38039 
  38040 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38041     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38042     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38043     defined(BCM_56260_B0)
  38044     { /* SOC_REG_INT_USBH_TP_OUTP1_BCM53400_A0r */
  38045         soc_block_list[61],
  38046         soc_iprocreg,
  38047         1,
  38048         0,
  38049         0x1804953c,
  38050         SOC_REG_FLAG_RO,
  38051         0,
  38052         1,
  38053         soc_USBH_TP_OUTP0_BCM53400_A0r_fields,
  38054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38055         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38056         -1,
  38057         -1,
  38058     },
  38059 #endif /* chips */
  38060 
  38061 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38062     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38063     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38064     defined(BCM_56260_B0)
  38065     { /* SOC_REG_INT_USBH_USB2H_STDCELL_SRAM_PARAMr */
  38066         soc_block_list[61],
  38067         soc_iprocreg,
  38068         1,
  38069         0,
  38070         0x18049600,
  38071         0,
  38072         0,
  38073         1,
  38074         soc_USBH_USB2H_STDCELL_SRAM_PARAMr_fields,
  38075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38076         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  38077         -1,
  38078         -1,
  38079     },
  38080 #endif /* chips */
  38081 
  38082 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  38083     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  38084     { /* SOC_REG_INT_USBH_USBCMDr */
  38085         soc_block_list[61],
  38086         soc_iprocreg,
  38087         1,
  38088         0,
  38089         0x1802a010,
  38090         0,
  38091         0,
  38092         10,
  38093         soc_USBH_USBCMDr_fields,
  38094         SOC_RESET_VAL_DEC(0x00080000, 0x00000000)
  38095         SOC_RESET_MASK_DEC(0x00ff0bff, 0x00000000)
  38096         -1,
  38097         -1,
  38098     },
  38099 #endif /* chips */
  38100 
  38101 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38102     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38103     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38104     defined(BCM_56260_B0)
  38105     { /* SOC_REG_INT_USBH_USBCMD_BCM53400_A0r */
  38106         soc_block_list[61],
  38107         soc_iprocreg,
  38108         1,
  38109         0,
  38110         0x18048010,
  38111         0,
  38112         0,
  38113         10,
  38114         soc_USBH_USBCMD_BCM53400_A0r_fields,
  38115         SOC_RESET_VAL_DEC(0x00080000, 0x00000000)
  38116         SOC_RESET_MASK_DEC(0x00ff0bff, 0x00000000)
  38117         -1,
  38118         -1,
  38119     },
  38120 #endif /* chips */
  38121 
  38122 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  38123     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  38124     { /* SOC_REG_INT_USBH_USBINTRr */
  38125         soc_block_list[61],
  38126         soc_iprocreg,
  38127         1,
  38128         0,
  38129         0x1802a018,
  38130         0,
  38131         0,
  38132         6,
  38133         soc_USBH_USBINTRr_fields,
  38134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38135         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  38136         -1,
  38137         -1,
  38138     },
  38139 #endif /* chips */
  38140 
  38141 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38142     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38143     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38144     defined(BCM_56260_B0)
  38145     { /* SOC_REG_INT_USBH_USBINTR_BCM53400_A0r */
  38146         soc_block_list[61],
  38147         soc_iprocreg,
  38148         1,
  38149         0,
  38150         0x18048018,
  38151         0,
  38152         0,
  38153         6,
  38154         soc_USBH_USBINTR_BCM53400_A0r_fields,
  38155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38156         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  38157         -1,
  38158         -1,
  38159     },
  38160 #endif /* chips */
  38161 
  38162 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  38163     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  38164     { /* SOC_REG_INT_USBH_USBSTSr */
  38165         soc_block_list[61],
  38166         soc_iprocreg,
  38167         1,
  38168         0,
  38169         0x1802a014,
  38170         0,
  38171         0,
  38172         10,
  38173         soc_USBH_USBSTSr_fields,
  38174         SOC_RESET_VAL_DEC(0x00001000, 0x00000000)
  38175         SOC_RESET_MASK_DEC(0x0000f03f, 0x00000000)
  38176         -1,
  38177         -1,
  38178     },
  38179 #endif /* chips */
  38180 
  38181 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38182     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38183     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38184     defined(BCM_56260_B0)
  38185     { /* SOC_REG_INT_USBH_USBSTS_BCM53400_A0r */
  38186         soc_block_list[61],
  38187         soc_iprocreg,
  38188         1,
  38189         0,
  38190         0x18048014,
  38191         0,
  38192         0,
  38193         10,
  38194         soc_USBH_USBSTS_BCM53400_A0r_fields,
  38195         SOC_RESET_VAL_DEC(0x00001000, 0x00000000)
  38196         SOC_RESET_MASK_DEC(0x0000f03f, 0x00000000)
  38197         -1,
  38198         -1,
  38199     },
  38200 #endif /* chips */
  38201 
  38202 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  38203     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  38204     { /* SOC_REG_INT_USBH_UTMI_P0CTLr */
  38205         soc_block_list[61],
  38206         soc_iprocreg,
  38207         1,
  38208         0,
  38209         0x1802a510,
  38210         0,
  38211         0,
  38212         12,
  38213         soc_USBH_UTMI_P0CTLr_fields,
  38214         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  38215         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  38216         -1,
  38217         -1,
  38218     },
  38219 #endif /* chips */
  38220 
  38221 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38222     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38223     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38224     defined(BCM_56260_B0)
  38225     { /* SOC_REG_INT_USBH_UTMI_P0CTL_BCM53400_A0r */
  38226         soc_block_list[61],
  38227         soc_iprocreg,
  38228         1,
  38229         0,
  38230         0x18049510,
  38231         0,
  38232         0,
  38233         12,
  38234         soc_USBH_UTMI_P0CTL_BCM53400_A0r_fields,
  38235         SOC_RESET_VAL_DEC(0x00000803, 0x00000000)
  38236         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  38237         -1,
  38238         -1,
  38239     },
  38240 #endif /* chips */
  38241 
  38242 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  38243     defined(BCM_56450_B0) || defined(BCM_56450_B1)
  38244     { /* SOC_REG_INT_USBH_UTMI_P1CTLr */
  38245         soc_block_list[61],
  38246         soc_iprocreg,
  38247         1,
  38248         0,
  38249         0x1802a518,
  38250         0,
  38251         0,
  38252         12,
  38253         soc_USBH_UTMI_P0CTLr_fields,
  38254         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  38255         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  38256         -1,
  38257         -1,
  38258     },
  38259 #endif /* chips */
  38260 
  38261 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38262     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38263     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38264     defined(BCM_56260_B0)
  38265     { /* SOC_REG_INT_USBH_UTMI_P1CTL_BCM53400_A0r */
  38266         soc_block_list[61],
  38267         soc_iprocreg,
  38268         1,
  38269         0,
  38270         0x18049518,
  38271         0,
  38272         0,
  38273         12,
  38274         soc_USBH_UTMI_P0CTL_BCM53400_A0r_fields,
  38275         SOC_RESET_VAL_DEC(0x00000803, 0x00000000)
  38276         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  38277         -1,
  38278         -1,
  38279     },
  38280 #endif /* chips */
  38281 
  38282 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38283     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38284     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38285     defined(BCM_56260_B0)
  38286     { /* SOC_REG_INT_USBH_UTMI_P2CTLr */
  38287         soc_block_list[61],
  38288         soc_iprocreg,
  38289         1,
  38290         0,
  38291         0x18049708,
  38292         0,
  38293         0,
  38294         12,
  38295         soc_USBH_UTMI_P0CTL_BCM53400_A0r_fields,
  38296         SOC_RESET_VAL_DEC(0x00000803, 0x00000000)
  38297         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  38298         -1,
  38299         -1,
  38300     },
  38301 #endif /* chips */
  38302 
  38303 #if defined(BCM_56370_A0)
  38304     { /* SOC_REG_INT_USBH_XHC_AIUCFGr */
  38305         soc_block_list[61],
  38306         soc_iprocreg,
  38307         1,
  38308         0,
  38309         0x10243c3c,
  38310         0,
  38311         0,
  38312         9,
  38313         soc_USBH_XHC_AIUCFGr_fields,
  38314         SOC_RESET_VAL_DEC(0x25330108, 0x00000000)
  38315         SOC_RESET_MASK_DEC(0x7777ffff, 0x00000000)
  38316         -1,
  38317         -1,
  38318         3,
  38319     },
  38320 #endif /* chips */
  38321 
  38322 #if defined(BCM_56370_A0)
  38323     { /* SOC_REG_INT_USBH_XHC_AIUDMAr */
  38324         soc_block_list[61],
  38325         soc_iprocreg,
  38326         1,
  38327         0,
  38328         0x10243c34,
  38329         0,
  38330         0,
  38331         9,
  38332         soc_USBH_XHC_AIUDMAr_fields,
  38333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38334         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38335         -1,
  38336         -1,
  38337         3,
  38338     },
  38339 #endif /* chips */
  38340 
  38341 #if defined(BCM_56370_A0)
  38342     { /* SOC_REG_INT_USBH_XHC_AIUFLAr */
  38343         soc_block_list[61],
  38344         soc_iprocreg,
  38345         1,
  38346         0,
  38347         0x10243c38,
  38348         0,
  38349         0,
  38350         4,
  38351         soc_USBH_XHC_AIUFLAr_fields,
  38352         SOC_RESET_VAL_DEC(0x361a5e20, 0x00000000)
  38353         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38354         -1,
  38355         -1,
  38356         3,
  38357     },
  38358 #endif /* chips */
  38359 
  38360 #if defined(BCM_56370_A0)
  38361     { /* SOC_REG_INT_USBH_XHC_AXILPMr */
  38362         soc_block_list[61],
  38363         soc_iprocreg,
  38364         1,
  38365         0,
  38366         0x10243c10,
  38367         0,
  38368         0,
  38369         3,
  38370         soc_USBH_XHC_AXILPMr_fields,
  38371         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  38372         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38373         -1,
  38374         -1,
  38375         3,
  38376     },
  38377 #endif /* chips */
  38378 
  38379 #if defined(BCM_56370_A0)
  38380     { /* SOC_REG_INT_USBH_XHC_AXIQOSr */
  38381         soc_block_list[61],
  38382         soc_iprocreg,
  38383         1,
  38384         0,
  38385         0x10243c14,
  38386         0,
  38387         0,
  38388         8,
  38389         soc_USBD_BDC_AXIQOSr_fields,
  38390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38391         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38392         -1,
  38393         -1,
  38394         3,
  38395     },
  38396 #endif /* chips */
  38397 
  38398 #if defined(BCM_56370_A0)
  38399     { /* SOC_REG_INT_USBH_XHC_AXIRDAr */
  38400         soc_block_list[61],
  38401         soc_iprocreg,
  38402         1,
  38403         0,
  38404         0x10243c0c,
  38405         0,
  38406         0,
  38407         5,
  38408         soc_USBH_XHC_AXIRDAr_fields,
  38409         SOC_RESET_VAL_DEC(0x60000000, 0x00000000)
  38410         SOC_RESET_MASK_DEC(0xf9ffffff, 0x00000000)
  38411         -1,
  38412         -1,
  38413         3,
  38414     },
  38415 #endif /* chips */
  38416 
  38417 #if defined(BCM_56370_A0)
  38418     { /* SOC_REG_INT_USBH_XHC_AXIWRAr */
  38419         soc_block_list[61],
  38420         soc_iprocreg,
  38421         1,
  38422         0,
  38423         0x10243c08,
  38424         0,
  38425         0,
  38426         5,
  38427         soc_USBH_XHC_AXIWRAr_fields,
  38428         SOC_RESET_VAL_DEC(0x60000000, 0x00000000)
  38429         SOC_RESET_MASK_DEC(0xf1ffffff, 0x00000000)
  38430         -1,
  38431         -1,
  38432         3,
  38433     },
  38434 #endif /* chips */
  38435 
  38436 #if defined(BCM_56370_A0)
  38437     { /* SOC_REG_INT_USBH_XHC_BIUSPCr */
  38438         soc_block_list[61],
  38439         soc_iprocreg,
  38440         1,
  38441         0,
  38442         0x10243c04,
  38443         SOC_REG_FLAG_RO,
  38444         0,
  38445         6,
  38446         soc_USBH_XHC_BIUSPCr_fields,
  38447         SOC_RESET_VAL_DEC(0x3110000c, 0x00000000)
  38448         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38449         -1,
  38450         -1,
  38451         3,
  38452     },
  38453 #endif /* chips */
  38454 
  38455 #if defined(BCM_56370_A0)
  38456     { /* SOC_REG_INT_USBH_XHC_CONFIGr */
  38457         soc_block_list[61],
  38458         soc_iprocreg,
  38459         1,
  38460         0,
  38461         0x10243058,
  38462         0,
  38463         0,
  38464         4,
  38465         soc_USBH_XHC_CONFIGr_fields,
  38466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38467         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38468         -1,
  38469         -1,
  38470         3,
  38471     },
  38472 #endif /* chips */
  38473 
  38474 #if defined(BCM_56370_A0)
  38475     { /* SOC_REG_INT_USBH_XHC_CPARAMS1r */
  38476         soc_block_list[61],
  38477         soc_iprocreg,
  38478         1,
  38479         0,
  38480         0x10243010,
  38481         SOC_REG_FLAG_RO,
  38482         0,
  38483         14,
  38484         soc_USBH_XHC_CPARAMS1r_fields,
  38485         SOC_RESET_VAL_DEC(0x0250f16d, 0x00000000)
  38486         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38487         -1,
  38488         -1,
  38489         3,
  38490     },
  38491 #endif /* chips */
  38492 
  38493 #if defined(BCM_56370_A0)
  38494     { /* SOC_REG_INT_USBH_XHC_CPARAMS2r */
  38495         soc_block_list[61],
  38496         soc_iprocreg,
  38497         1,
  38498         0,
  38499         0x1024301c,
  38500         SOC_REG_FLAG_RO,
  38501         0,
  38502         7,
  38503         soc_USBH_XHC_CPARAMS2r_fields,
  38504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38505         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38506         -1,
  38507         -1,
  38508         3,
  38509     },
  38510 #endif /* chips */
  38511 
  38512 #if defined(BCM_56370_A0)
  38513     { /* SOC_REG_INT_USBH_XHC_CPLIVERr */
  38514         soc_block_list[61],
  38515         soc_iprocreg,
  38516         1,
  38517         0,
  38518         0x10243000,
  38519         SOC_REG_FLAG_RO,
  38520         0,
  38521         4,
  38522         soc_USBH_XHC_CPLIVERr_fields,
  38523         SOC_RESET_VAL_DEC(0x01000020, 0x00000000)
  38524         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38525         -1,
  38526         -1,
  38527         3,
  38528     },
  38529 #endif /* chips */
  38530 
  38531 #if defined(BCM_56370_A0)
  38532     { /* SOC_REG_INT_USBH_XHC_CRCRHr */
  38533         soc_block_list[61],
  38534         soc_iprocreg,
  38535         1,
  38536         0,
  38537         0x1024303c,
  38538         0,
  38539         0,
  38540         1,
  38541         soc_USBH_XHC_CRCRHr_fields,
  38542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38544         -1,
  38545         -1,
  38546         3,
  38547     },
  38548 #endif /* chips */
  38549 
  38550 #if defined(BCM_56370_A0)
  38551     { /* SOC_REG_INT_USBH_XHC_CRCRLr */
  38552         soc_block_list[61],
  38553         soc_iprocreg,
  38554         1,
  38555         0,
  38556         0x10243038,
  38557         0,
  38558         0,
  38559         6,
  38560         soc_USBH_XHC_CRCRLr_fields,
  38561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38562         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38563         -1,
  38564         -1,
  38565         3,
  38566     },
  38567 #endif /* chips */
  38568 
  38569 #if defined(BCM_56370_A0)
  38570     { /* SOC_REG_INT_USBH_XHC_CSRSPCr */
  38571         soc_block_list[61],
  38572         soc_iprocreg,
  38573         1,
  38574         0,
  38575         0x10243c24,
  38576         SOC_REG_FLAG_RO,
  38577         0,
  38578         6,
  38579         soc_USBH_XHC_CSRSPCr_fields,
  38580         SOC_RESET_VAL_DEC(0x31100000, 0x00000000)
  38581         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38582         -1,
  38583         -1,
  38584         3,
  38585     },
  38586 #endif /* chips */
  38587 
  38588 #if defined(BCM_56370_A0)
  38589     { /* SOC_REG_INT_USBH_XHC_CTTMTS0r */
  38590         soc_block_list[61],
  38591         soc_iprocreg,
  38592         1,
  38593         0,
  38594         0x10243bf8,
  38595         SOC_REG_FLAG_RO,
  38596         0,
  38597         3,
  38598         soc_USBH_XHC_CTTMTS0r_fields,
  38599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38600         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38601         -1,
  38602         -1,
  38603         3,
  38604     },
  38605 #endif /* chips */
  38606 
  38607 #if defined(BCM_56370_A0)
  38608     { /* SOC_REG_INT_USBH_XHC_CTTMTS1r */
  38609         soc_block_list[61],
  38610         soc_iprocreg,
  38611         1,
  38612         0,
  38613         0x10243bfc,
  38614         SOC_REG_FLAG_RO,
  38615         0,
  38616         3,
  38617         soc_USBH_XHC_CTTMTS1r_fields,
  38618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38619         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  38620         -1,
  38621         -1,
  38622         3,
  38623     },
  38624 #endif /* chips */
  38625 
  38626 #if defined(BCM_56370_A0)
  38627     { /* SOC_REG_INT_USBH_XHC_DBLCMDr */
  38628         soc_block_list[61],
  38629         soc_iprocreg,
  38630         1,
  38631         0,
  38632         0x102438c0,
  38633         0,
  38634         0,
  38635         3,
  38636         soc_USBH_XHC_DBLCMDr_fields,
  38637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38638         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38639         -1,
  38640         -1,
  38641         3,
  38642     },
  38643 #endif /* chips */
  38644 
  38645 #if defined(BCM_56370_A0)
  38646     { /* SOC_REG_INT_USBH_XHC_DBLDVX1r */
  38647         soc_block_list[61],
  38648         soc_iprocreg,
  38649         1,
  38650         0,
  38651         0x102438c4,
  38652         0,
  38653         0,
  38654         3,
  38655         soc_USBH_XHC_DBLCMDr_fields,
  38656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38657         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38658         -1,
  38659         -1,
  38660         3,
  38661     },
  38662 #endif /* chips */
  38663 
  38664 #if defined(BCM_56370_A0)
  38665     { /* SOC_REG_INT_USBH_XHC_DBLDVX2r */
  38666         soc_block_list[61],
  38667         soc_iprocreg,
  38668         1,
  38669         0,
  38670         0x102438c8,
  38671         0,
  38672         0,
  38673         3,
  38674         soc_USBH_XHC_DBLCMDr_fields,
  38675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38676         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38677         -1,
  38678         -1,
  38679         3,
  38680     },
  38681 #endif /* chips */
  38682 
  38683 #if defined(BCM_56370_A0)
  38684     { /* SOC_REG_INT_USBH_XHC_DBLDVX3r */
  38685         soc_block_list[61],
  38686         soc_iprocreg,
  38687         1,
  38688         0,
  38689         0x102438cc,
  38690         0,
  38691         0,
  38692         3,
  38693         soc_USBH_XHC_DBLCMDr_fields,
  38694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38695         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38696         -1,
  38697         -1,
  38698         3,
  38699     },
  38700 #endif /* chips */
  38701 
  38702 #if defined(BCM_56370_A0)
  38703     { /* SOC_REG_INT_USBH_XHC_DBLDVX4r */
  38704         soc_block_list[61],
  38705         soc_iprocreg,
  38706         1,
  38707         0,
  38708         0x102438d0,
  38709         0,
  38710         0,
  38711         3,
  38712         soc_USBH_XHC_DBLCMDr_fields,
  38713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38714         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38715         -1,
  38716         -1,
  38717         3,
  38718     },
  38719 #endif /* chips */
  38720 
  38721 #if defined(BCM_56370_A0)
  38722     { /* SOC_REG_INT_USBH_XHC_DBLDVX5r */
  38723         soc_block_list[61],
  38724         soc_iprocreg,
  38725         1,
  38726         0,
  38727         0x102438d4,
  38728         0,
  38729         0,
  38730         3,
  38731         soc_USBH_XHC_DBLCMDr_fields,
  38732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38733         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38734         -1,
  38735         -1,
  38736         3,
  38737     },
  38738 #endif /* chips */
  38739 
  38740 #if defined(BCM_56370_A0)
  38741     { /* SOC_REG_INT_USBH_XHC_DBLDVX6r */
  38742         soc_block_list[61],
  38743         soc_iprocreg,
  38744         1,
  38745         0,
  38746         0x102438d8,
  38747         0,
  38748         0,
  38749         3,
  38750         soc_USBH_XHC_DBLCMDr_fields,
  38751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38752         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38753         -1,
  38754         -1,
  38755         3,
  38756     },
  38757 #endif /* chips */
  38758 
  38759 #if defined(BCM_56370_A0)
  38760     { /* SOC_REG_INT_USBH_XHC_DBLDVX7r */
  38761         soc_block_list[61],
  38762         soc_iprocreg,
  38763         1,
  38764         0,
  38765         0x102438dc,
  38766         0,
  38767         0,
  38768         3,
  38769         soc_USBH_XHC_DBLCMDr_fields,
  38770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38771         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38772         -1,
  38773         -1,
  38774         3,
  38775     },
  38776 #endif /* chips */
  38777 
  38778 #if defined(BCM_56370_A0)
  38779     { /* SOC_REG_INT_USBH_XHC_DBLDVX8r */
  38780         soc_block_list[61],
  38781         soc_iprocreg,
  38782         1,
  38783         0,
  38784         0x102438e0,
  38785         0,
  38786         0,
  38787         3,
  38788         soc_USBH_XHC_DBLCMDr_fields,
  38789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38790         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38791         -1,
  38792         -1,
  38793         3,
  38794     },
  38795 #endif /* chips */
  38796 
  38797 #if defined(BCM_56370_A0)
  38798     { /* SOC_REG_INT_USBH_XHC_DBLDVX9r */
  38799         soc_block_list[61],
  38800         soc_iprocreg,
  38801         1,
  38802         0,
  38803         0x102438e4,
  38804         0,
  38805         0,
  38806         3,
  38807         soc_USBH_XHC_DBLCMDr_fields,
  38808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38809         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38810         -1,
  38811         -1,
  38812         3,
  38813     },
  38814 #endif /* chips */
  38815 
  38816 #if defined(BCM_56370_A0)
  38817     { /* SOC_REG_INT_USBH_XHC_DBLDVX10r */
  38818         soc_block_list[61],
  38819         soc_iprocreg,
  38820         1,
  38821         0,
  38822         0x102438e8,
  38823         0,
  38824         0,
  38825         3,
  38826         soc_USBH_XHC_DBLCMDr_fields,
  38827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38828         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38829         -1,
  38830         -1,
  38831         3,
  38832     },
  38833 #endif /* chips */
  38834 
  38835 #if defined(BCM_56370_A0)
  38836     { /* SOC_REG_INT_USBH_XHC_DBLDVX11r */
  38837         soc_block_list[61],
  38838         soc_iprocreg,
  38839         1,
  38840         0,
  38841         0x102438ec,
  38842         0,
  38843         0,
  38844         3,
  38845         soc_USBH_XHC_DBLCMDr_fields,
  38846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38847         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38848         -1,
  38849         -1,
  38850         3,
  38851     },
  38852 #endif /* chips */
  38853 
  38854 #if defined(BCM_56370_A0)
  38855     { /* SOC_REG_INT_USBH_XHC_DBLDVX12r */
  38856         soc_block_list[61],
  38857         soc_iprocreg,
  38858         1,
  38859         0,
  38860         0x102438f0,
  38861         0,
  38862         0,
  38863         3,
  38864         soc_USBH_XHC_DBLCMDr_fields,
  38865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38866         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38867         -1,
  38868         -1,
  38869         3,
  38870     },
  38871 #endif /* chips */
  38872 
  38873 #if defined(BCM_56370_A0)
  38874     { /* SOC_REG_INT_USBH_XHC_DBLDVX13r */
  38875         soc_block_list[61],
  38876         soc_iprocreg,
  38877         1,
  38878         0,
  38879         0x102438f4,
  38880         0,
  38881         0,
  38882         3,
  38883         soc_USBH_XHC_DBLCMDr_fields,
  38884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38885         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38886         -1,
  38887         -1,
  38888         3,
  38889     },
  38890 #endif /* chips */
  38891 
  38892 #if defined(BCM_56370_A0)
  38893     { /* SOC_REG_INT_USBH_XHC_DBLDVX14r */
  38894         soc_block_list[61],
  38895         soc_iprocreg,
  38896         1,
  38897         0,
  38898         0x102438f8,
  38899         0,
  38900         0,
  38901         3,
  38902         soc_USBH_XHC_DBLCMDr_fields,
  38903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38904         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38905         -1,
  38906         -1,
  38907         3,
  38908     },
  38909 #endif /* chips */
  38910 
  38911 #if defined(BCM_56370_A0)
  38912     { /* SOC_REG_INT_USBH_XHC_DBLDVX15r */
  38913         soc_block_list[61],
  38914         soc_iprocreg,
  38915         1,
  38916         0,
  38917         0x102438fc,
  38918         0,
  38919         0,
  38920         3,
  38921         soc_USBH_XHC_DBLCMDr_fields,
  38922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38923         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38924         -1,
  38925         -1,
  38926         3,
  38927     },
  38928 #endif /* chips */
  38929 
  38930 #if defined(BCM_56370_A0)
  38931     { /* SOC_REG_INT_USBH_XHC_DBLDVX16r */
  38932         soc_block_list[61],
  38933         soc_iprocreg,
  38934         1,
  38935         0,
  38936         0x10243900,
  38937         0,
  38938         0,
  38939         3,
  38940         soc_USBH_XHC_DBLCMDr_fields,
  38941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38942         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38943         -1,
  38944         -1,
  38945         3,
  38946     },
  38947 #endif /* chips */
  38948 
  38949 #if defined(BCM_56370_A0)
  38950     { /* SOC_REG_INT_USBH_XHC_DBOFFr */
  38951         soc_block_list[61],
  38952         soc_iprocreg,
  38953         1,
  38954         0,
  38955         0x10243014,
  38956         SOC_REG_FLAG_RO,
  38957         0,
  38958         2,
  38959         soc_USBH_XHC_DBOFFr_fields,
  38960         SOC_RESET_VAL_DEC(0x000008c0, 0x00000000)
  38961         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  38962         -1,
  38963         -1,
  38964         3,
  38965     },
  38966 #endif /* chips */
  38967 
  38968 #if defined(BCM_56370_A0)
  38969     { /* SOC_REG_INT_USBH_XHC_DCBAAPHr */
  38970         soc_block_list[61],
  38971         soc_iprocreg,
  38972         1,
  38973         0,
  38974         0x10243054,
  38975         0,
  38976         0,
  38977         1,
  38978         soc_USBH_XHC_DCBAAPHr_fields,
  38979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38980         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38981         -1,
  38982         -1,
  38983         3,
  38984     },
  38985 #endif /* chips */
  38986 
  38987 #if defined(BCM_56370_A0)
  38988     { /* SOC_REG_INT_USBH_XHC_DCBAAPLr */
  38989         soc_block_list[61],
  38990         soc_iprocreg,
  38991         1,
  38992         0,
  38993         0x10243050,
  38994         0,
  38995         0,
  38996         2,
  38997         soc_USBH_XHC_DCBAAPLr_fields,
  38998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38999         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39000         -1,
  39001         -1,
  39002         3,
  39003     },
  39004 #endif /* chips */
  39005 
  39006 #if defined(BCM_56370_A0)
  39007     { /* SOC_REG_INT_USBH_XHC_DNCTRLr */
  39008         soc_block_list[61],
  39009         soc_iprocreg,
  39010         1,
  39011         0,
  39012         0x10243034,
  39013         0,
  39014         0,
  39015         2,
  39016         soc_USBH_XHC_DNCTRLr_fields,
  39017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39018         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39019         -1,
  39020         -1,
  39021         3,
  39022     },
  39023 #endif /* chips */
  39024 
  39025 #if defined(BCM_56370_A0)
  39026     { /* SOC_REG_INT_USBH_XHC_ECHAIUr */
  39027         soc_block_list[61],
  39028         soc_iprocreg,
  39029         1,
  39030         0,
  39031         0x10243c30,
  39032         0,
  39033         0,
  39034         10,
  39035         soc_USBH_XHC_ECHAIUr_fields,
  39036         SOC_RESET_VAL_DEC(0x400604c2, 0x00000000)
  39037         SOC_RESET_MASK_DEC(0xdfffffff, 0x00000000)
  39038         -1,
  39039         -1,
  39040         3,
  39041     },
  39042 #endif /* chips */
  39043 
  39044 #if defined(BCM_56370_A0)
  39045     { /* SOC_REG_INT_USBH_XHC_ECHBIUr */
  39046         soc_block_list[61],
  39047         soc_iprocreg,
  39048         1,
  39049         0,
  39050         0x10243c00,
  39051         SOC_REG_FLAG_RO,
  39052         0,
  39053         5,
  39054         soc_USBH_XHC_ECHBIUr_fields,
  39055         SOC_RESET_VAL_DEC(0x100108c0, 0x00000000)
  39056         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39057         -1,
  39058         -1,
  39059         3,
  39060     },
  39061 #endif /* chips */
  39062 
  39063 #if defined(BCM_56370_A0)
  39064     { /* SOC_REG_INT_USBH_XHC_ECHCSRr */
  39065         soc_block_list[61],
  39066         soc_iprocreg,
  39067         1,
  39068         0,
  39069         0x10243c20,
  39070         SOC_REG_FLAG_RO,
  39071         0,
  39072         5,
  39073         soc_USBH_XHC_ECHCSRr_fields,
  39074         SOC_RESET_VAL_DEC(0x0d8004c1, 0x00000000)
  39075         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39076         -1,
  39077         -1,
  39078         3,
  39079     },
  39080 #endif /* chips */
  39081 
  39082 #if defined(BCM_56370_A0)
  39083     { /* SOC_REG_INT_USBH_XHC_ECHCTTr */
  39084         soc_block_list[61],
  39085         soc_iprocreg,
  39086         1,
  39087         0,
  39088         0x10243bf0,
  39089         SOC_REG_FLAG_RO,
  39090         0,
  39091         3,
  39092         soc_USBH_XHC_ECHCTTr_fields,
  39093         SOC_RESET_VAL_DEC(0x000004e0, 0x00000000)
  39094         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39095         -1,
  39096         -1,
  39097         3,
  39098     },
  39099 #endif /* chips */
  39100 
  39101 #if defined(BCM_56370_A0)
  39102     { /* SOC_REG_INT_USBH_XHC_ECHDBGr */
  39103         soc_block_list[61],
  39104         soc_iprocreg,
  39105         1,
  39106         0,
  39107         0x10243af8,
  39108         SOC_REG_FLAG_RO,
  39109         0,
  39110         3,
  39111         soc_USBH_XHC_ECHDBGr_fields,
  39112         SOC_RESET_VAL_DEC(0x000010cb, 0x00000000)
  39113         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39114         -1,
  39115         -1,
  39116         3,
  39117     },
  39118 #endif /* chips */
  39119 
  39120 #if defined(BCM_56370_A0)
  39121     { /* SOC_REG_INT_USBH_XHC_ECHFSCr */
  39122         soc_block_list[61],
  39123         soc_iprocreg,
  39124         1,
  39125         0,
  39126         0x10243c40,
  39127         SOC_REG_FLAG_RO,
  39128         0,
  39129         5,
  39130         soc_USBH_XHC_ECHFSCr_fields,
  39131         SOC_RESET_VAL_DEC(0x00330cff, 0x00000000)
  39132         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39133         -1,
  39134         -1,
  39135         3,
  39136     },
  39137 #endif /* chips */
  39138 
  39139 #if defined(BCM_56370_A0)
  39140     { /* SOC_REG_INT_USBH_XHC_ECHHSTr */
  39141         soc_block_list[61],
  39142         soc_iprocreg,
  39143         1,
  39144         0,
  39145         0x10243fa0,
  39146         0,
  39147         0,
  39148         10,
  39149         soc_USBH_XHC_ECHHSTr_fields,
  39150         SOC_RESET_VAL_DEC(0xb61304fc, 0x00000000)
  39151         SOC_RESET_MASK_DEC(0xff1fffff, 0x00000000)
  39152         -1,
  39153         -1,
  39154         3,
  39155     },
  39156 #endif /* chips */
  39157 
  39158 #if defined(BCM_56370_A0)
  39159     { /* SOC_REG_INT_USBH_XHC_ECHIOVr */
  39160         soc_block_list[61],
  39161         soc_iprocreg,
  39162         1,
  39163         0,
  39164         0x10243968,
  39165         SOC_REG_FLAG_RO,
  39166         0,
  39167         3,
  39168         soc_USBH_XHC_ECHIOVr_fields,
  39169         SOC_RESET_VAL_DEC(0x00006004, 0x00000000)
  39170         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39171         -1,
  39172         -1,
  39173         3,
  39174     },
  39175 #endif /* chips */
  39176 
  39177 #if defined(BCM_56370_A0)
  39178     { /* SOC_REG_INT_USBH_XHC_ECHIRAr */
  39179         soc_block_list[61],
  39180         soc_iprocreg,
  39181         1,
  39182         0,
  39183         0x10243f90,
  39184         SOC_REG_FLAG_RO,
  39185         0,
  39186         3,
  39187         soc_USBD_BDC_ECHIRAr_fields,
  39188         SOC_RESET_VAL_DEC(0x000004fe, 0x00000000)
  39189         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39190         -1,
  39191         -1,
  39192         3,
  39193     },
  39194 #endif /* chips */
  39195 
  39196 #if defined(BCM_56370_A0)
  39197     { /* SOC_REG_INT_USBH_XHC_ECHMSIr */
  39198         soc_block_list[61],
  39199         soc_iprocreg,
  39200         1,
  39201         0,
  39202         0x10243ae8,
  39203         SOC_REG_FLAG_RO,
  39204         0,
  39205         8,
  39206         soc_USBH_XHC_ECHMSIr_fields,
  39207         SOC_RESET_VAL_DEC(0x00850405, 0x00000000)
  39208         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39209         -1,
  39210         -1,
  39211         3,
  39212     },
  39213 #endif /* chips */
  39214 
  39215 #if defined(BCM_56370_A0)
  39216     { /* SOC_REG_INT_USBH_XHC_ECHPMGr */
  39217         soc_block_list[61],
  39218         soc_iprocreg,
  39219         1,
  39220         0,
  39221         0x10243960,
  39222         SOC_REG_FLAG_RO,
  39223         0,
  39224         3,
  39225         soc_USBH_XHC_ECHPMGr_fields,
  39226         SOC_RESET_VAL_DEC(0x00000203, 0x00000000)
  39227         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39228         -1,
  39229         -1,
  39230         3,
  39231     },
  39232 #endif /* chips */
  39233 
  39234 #if defined(BCM_56370_A0)
  39235     { /* SOC_REG_INT_USBH_XHC_ECHPMGCSDr */
  39236         soc_block_list[61],
  39237         soc_iprocreg,
  39238         1,
  39239         0,
  39240         0x10243964,
  39241         SOC_REG_FLAG_RO,
  39242         0,
  39243         1,
  39244         soc_CMICD_S0_IDM_IDM_IO_STATUS_BCM53400_A0r_fields,
  39245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39246         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39247         -1,
  39248         -1,
  39249         3,
  39250     },
  39251 #endif /* chips */
  39252 
  39253 #if defined(BCM_56370_A0)
  39254     { /* SOC_REG_INT_USBH_XHC_ECHPRTr */
  39255         soc_block_list[61],
  39256         soc_iprocreg,
  39257         1,
  39258         0,
  39259         0x10243c70,
  39260         0,
  39261         0,
  39262         7,
  39263         soc_USBH_XHC_ECHPRTr_fields,
  39264         SOC_RESET_VAL_DEC(0x00fb04ff, 0x00000000)
  39265         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39266         -1,
  39267         -1,
  39268         3,
  39269     },
  39270 #endif /* chips */
  39271 
  39272 #if defined(BCM_56370_A0)
  39273     { /* SOC_REG_INT_USBH_XHC_ECHRBVr */
  39274         soc_block_list[61],
  39275         soc_iprocreg,
  39276         1,
  39277         0,
  39278         0x10243fb0,
  39279         SOC_REG_FLAG_RO,
  39280         0,
  39281         5,
  39282         soc_USBH_XHC_ECHRBVr_fields,
  39283         SOC_RESET_VAL_DEC(0x300800fe, 0x00000000)
  39284         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39285         -1,
  39286         -1,
  39287         3,
  39288     },
  39289 #endif /* chips */
  39290 
  39291 #if defined(BCM_56370_A0)
  39292     { /* SOC_REG_INT_USBH_XHC_ECHRH2r */
  39293         soc_block_list[61],
  39294         soc_iprocreg,
  39295         1,
  39296         0,
  39297         0x10243f50,
  39298         SOC_REG_FLAG_RO,
  39299         0,
  39300         3,
  39301         soc_USBH_XHC_ECHRH2r_fields,
  39302         SOC_RESET_VAL_DEC(0x00000cff, 0x00000000)
  39303         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39304         -1,
  39305         -1,
  39306         3,
  39307     },
  39308 #endif /* chips */
  39309 
  39310 #if defined(BCM_56370_A0)
  39311     { /* SOC_REG_INT_USBH_XHC_ECHRHSr */
  39312         soc_block_list[61],
  39313         soc_iprocreg,
  39314         1,
  39315         0,
  39316         0x10243c80,
  39317         SOC_REG_FLAG_RO,
  39318         0,
  39319         6,
  39320         soc_USBH_XHC_ECHRHSr_fields,
  39321         SOC_RESET_VAL_DEC(0x01200cff, 0x00000000)
  39322         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  39323         -1,
  39324         -1,
  39325         3,
  39326     },
  39327 #endif /* chips */
  39328 
  39329 #if defined(BCM_56370_A0)
  39330     { /* SOC_REG_INT_USBH_XHC_ECHRSV2r */
  39331         soc_block_list[61],
  39332         soc_iprocreg,
  39333         1,
  39334         0,
  39335         0x10243cc0,
  39336         SOC_REG_FLAG_RO,
  39337         0,
  39338         3,
  39339         soc_USBH_XHC_ECHRSV2r_fields,
  39340         SOC_RESET_VAL_DEC(0x0000a4ff, 0x00000000)
  39341         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39342         -1,
  39343         -1,
  39344         3,
  39345     },
  39346 #endif /* chips */
  39347 
  39348 #if defined(BCM_56370_A0)
  39349     { /* SOC_REG_INT_USBH_XHC_ECHRSVOr */
  39350         soc_block_list[61],
  39351         soc_iprocreg,
  39352         1,
  39353         0,
  39354         0x10243b38,
  39355         SOC_REG_FLAG_RO,
  39356         0,
  39357         3,
  39358         soc_USBH_XHC_ECHRSVOr_fields,
  39359         SOC_RESET_VAL_DEC(0x00002eff, 0x00000000)
  39360         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39361         -1,
  39362         -1,
  39363         3,
  39364     },
  39365 #endif /* chips */
  39366 
  39367 #if defined(BCM_56370_A0)
  39368     { /* SOC_REG_INT_USBH_XHC_ECHSPT2r */
  39369         soc_block_list[61],
  39370         soc_iprocreg,
  39371         1,
  39372         0,
  39373         0x10243950,
  39374         SOC_REG_FLAG_RO,
  39375         0,
  39376         4,
  39377         soc_USBH_XHC_ECHSPT2r_fields,
  39378         SOC_RESET_VAL_DEC(0x02000402, 0x00000000)
  39379         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39380         -1,
  39381         -1,
  39382         3,
  39383     },
  39384 #endif /* chips */
  39385 
  39386 #if defined(BCM_56370_A0)
  39387     { /* SOC_REG_INT_USBH_XHC_ECHSPT3r */
  39388         soc_block_list[61],
  39389         soc_iprocreg,
  39390         1,
  39391         0,
  39392         0x10243940,
  39393         SOC_REG_FLAG_RO,
  39394         0,
  39395         4,
  39396         soc_USBH_XHC_ECHSPT3r_fields,
  39397         SOC_RESET_VAL_DEC(0x030004ff, 0x00000000)
  39398         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39399         -1,
  39400         -1,
  39401         3,
  39402     },
  39403 #endif /* chips */
  39404 
  39405 #if defined(BCM_56370_A0)
  39406     { /* SOC_REG_INT_USBH_XHC_ECHSSPr */
  39407         soc_block_list[61],
  39408         soc_iprocreg,
  39409         1,
  39410         0,
  39411         0x10243cb0,
  39412         SOC_REG_FLAG_RO,
  39413         0,
  39414         3,
  39415         soc_USBH_XHC_ECHSSPr_fields,
  39416         SOC_RESET_VAL_DEC(0x000004ff, 0x00000000)
  39417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39418         -1,
  39419         -1,
  39420         3,
  39421     },
  39422 #endif /* chips */
  39423 
  39424 #if defined(BCM_56370_A0)
  39425     { /* SOC_REG_INT_USBH_XHC_ECHU2Pr */
  39426         soc_block_list[61],
  39427         soc_iprocreg,
  39428         1,
  39429         0,
  39430         0x10243f80,
  39431         SOC_REG_FLAG_RO,
  39432         0,
  39433         3,
  39434         soc_USBH_XHC_ECHSSPr_fields,
  39435         SOC_RESET_VAL_DEC(0x000004ff, 0x00000000)
  39436         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39437         -1,
  39438         -1,
  39439         3,
  39440     },
  39441 #endif /* chips */
  39442 
  39443 #if defined(BCM_56370_A0)
  39444     { /* SOC_REG_INT_USBH_XHC_ERDPH0r */
  39445         soc_block_list[61],
  39446         soc_iprocreg,
  39447         1,
  39448         0,
  39449         0x102434dc,
  39450         0,
  39451         0,
  39452         1,
  39453         soc_USBH_XHC_ERDPH0r_fields,
  39454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39455         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39456         -1,
  39457         -1,
  39458         3,
  39459     },
  39460 #endif /* chips */
  39461 
  39462 #if defined(BCM_56370_A0)
  39463     { /* SOC_REG_INT_USBH_XHC_ERDPH1r */
  39464         soc_block_list[61],
  39465         soc_iprocreg,
  39466         1,
  39467         0,
  39468         0x102434fc,
  39469         0,
  39470         0,
  39471         1,
  39472         soc_USBH_XHC_ERDPH0r_fields,
  39473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39474         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39475         -1,
  39476         -1,
  39477         3,
  39478     },
  39479 #endif /* chips */
  39480 
  39481 #if defined(BCM_56370_A0)
  39482     { /* SOC_REG_INT_USBH_XHC_ERDPL0r */
  39483         soc_block_list[61],
  39484         soc_iprocreg,
  39485         1,
  39486         0,
  39487         0x102434d8,
  39488         0,
  39489         0,
  39490         3,
  39491         soc_USBH_XHC_ERDPL0r_fields,
  39492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39493         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39494         -1,
  39495         -1,
  39496         3,
  39497     },
  39498 #endif /* chips */
  39499 
  39500 #if defined(BCM_56370_A0)
  39501     { /* SOC_REG_INT_USBH_XHC_ERDPL1r */
  39502         soc_block_list[61],
  39503         soc_iprocreg,
  39504         1,
  39505         0,
  39506         0x102434f8,
  39507         0,
  39508         0,
  39509         3,
  39510         soc_USBH_XHC_ERDPL0r_fields,
  39511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39512         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39513         -1,
  39514         -1,
  39515         3,
  39516     },
  39517 #endif /* chips */
  39518 
  39519 #if defined(BCM_56370_A0)
  39520     { /* SOC_REG_INT_USBH_XHC_ERSTBAH0r */
  39521         soc_block_list[61],
  39522         soc_iprocreg,
  39523         1,
  39524         0,
  39525         0x102434d4,
  39526         0,
  39527         0,
  39528         1,
  39529         soc_USBD_BDC_SPBBAHr_fields,
  39530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39531         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39532         -1,
  39533         -1,
  39534         3,
  39535     },
  39536 #endif /* chips */
  39537 
  39538 #if defined(BCM_56370_A0)
  39539     { /* SOC_REG_INT_USBH_XHC_ERSTBAH1r */
  39540         soc_block_list[61],
  39541         soc_iprocreg,
  39542         1,
  39543         0,
  39544         0x102434f4,
  39545         0,
  39546         0,
  39547         1,
  39548         soc_USBD_BDC_SPBBAHr_fields,
  39549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39550         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39551         -1,
  39552         -1,
  39553         3,
  39554     },
  39555 #endif /* chips */
  39556 
  39557 #if defined(BCM_56370_A0)
  39558     { /* SOC_REG_INT_USBH_XHC_ERSTBAL0r */
  39559         soc_block_list[61],
  39560         soc_iprocreg,
  39561         1,
  39562         0,
  39563         0x102434d0,
  39564         0,
  39565         0,
  39566         2,
  39567         soc_USBH_XHC_ERSTBAL0r_fields,
  39568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39569         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39570         -1,
  39571         -1,
  39572         3,
  39573     },
  39574 #endif /* chips */
  39575 
  39576 #if defined(BCM_56370_A0)
  39577     { /* SOC_REG_INT_USBH_XHC_ERSTBAL1r */
  39578         soc_block_list[61],
  39579         soc_iprocreg,
  39580         1,
  39581         0,
  39582         0x102434f0,
  39583         0,
  39584         0,
  39585         2,
  39586         soc_USBH_XHC_ERSTBAL0r_fields,
  39587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39588         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39589         -1,
  39590         -1,
  39591         3,
  39592     },
  39593 #endif /* chips */
  39594 
  39595 #if defined(BCM_56370_A0)
  39596     { /* SOC_REG_INT_USBH_XHC_ERSTSZ0r */
  39597         soc_block_list[61],
  39598         soc_iprocreg,
  39599         1,
  39600         0,
  39601         0x102434c8,
  39602         0,
  39603         0,
  39604         2,
  39605         soc_USBH_XHC_ERSTSZ0r_fields,
  39606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39607         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39608         -1,
  39609         -1,
  39610         3,
  39611     },
  39612 #endif /* chips */
  39613 
  39614 #if defined(BCM_56370_A0)
  39615     { /* SOC_REG_INT_USBH_XHC_ERSTSZ1r */
  39616         soc_block_list[61],
  39617         soc_iprocreg,
  39618         1,
  39619         0,
  39620         0x102434e8,
  39621         0,
  39622         0,
  39623         2,
  39624         soc_USBH_XHC_ERSTSZ0r_fields,
  39625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39626         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39627         -1,
  39628         -1,
  39629         3,
  39630     },
  39631 #endif /* chips */
  39632 
  39633 #if defined(BCM_56370_A0)
  39634     { /* SOC_REG_INT_USBH_XHC_HSTDBGr */
  39635         soc_block_list[61],
  39636         soc_iprocreg,
  39637         1,
  39638         0,
  39639         0x10243fa4,
  39640         0,
  39641         0,
  39642         4,
  39643         soc_USBH_XHC_HSTDBGr_fields,
  39644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39646         -1,
  39647         -1,
  39648         3,
  39649     },
  39650 #endif /* chips */
  39651 
  39652 #if defined(BCM_56370_A0)
  39653     { /* SOC_REG_INT_USBH_XHC_HSTNPHr */
  39654         soc_block_list[61],
  39655         soc_iprocreg,
  39656         1,
  39657         0,
  39658         0x10243fac,
  39659         SOC_REG_FLAG_RO,
  39660         0,
  39661         1,
  39662         soc_USBD_BDC_DVCNPHr_fields,
  39663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39664         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39665         -1,
  39666         -1,
  39667         3,
  39668     },
  39669 #endif /* chips */
  39670 
  39671 #if defined(BCM_56370_A0)
  39672     { /* SOC_REG_INT_USBH_XHC_HSTNPLr */
  39673         soc_block_list[61],
  39674         soc_iprocreg,
  39675         1,
  39676         0,
  39677         0x10243fa8,
  39678         SOC_REG_FLAG_RO,
  39679         0,
  39680         2,
  39681         soc_USBH_XHC_HSTNPLr_fields,
  39682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39683         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39684         -1,
  39685         -1,
  39686         3,
  39687     },
  39688 #endif /* chips */
  39689 
  39690 #if defined(BCM_56370_A0)
  39691     { /* SOC_REG_INT_USBH_XHC_IMAN0r */
  39692         soc_block_list[61],
  39693         soc_iprocreg,
  39694         1,
  39695         0,
  39696         0x102434c0,
  39697         0,
  39698         0,
  39699         3,
  39700         soc_USBH_XHC_IMAN0r_fields,
  39701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39703         -1,
  39704         -1,
  39705         3,
  39706     },
  39707 #endif /* chips */
  39708 
  39709 #if defined(BCM_56370_A0)
  39710     { /* SOC_REG_INT_USBH_XHC_IMAN1r */
  39711         soc_block_list[61],
  39712         soc_iprocreg,
  39713         1,
  39714         0,
  39715         0x102434e0,
  39716         0,
  39717         0,
  39718         3,
  39719         soc_USBH_XHC_IMAN0r_fields,
  39720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39721         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39722         -1,
  39723         -1,
  39724         3,
  39725     },
  39726 #endif /* chips */
  39727 
  39728 #if defined(BCM_56370_A0)
  39729     { /* SOC_REG_INT_USBH_XHC_IMOD0r */
  39730         soc_block_list[61],
  39731         soc_iprocreg,
  39732         1,
  39733         0,
  39734         0x102434c4,
  39735         0,
  39736         0,
  39737         2,
  39738         soc_USBH_XHC_IMOD0r_fields,
  39739         SOC_RESET_VAL_DEC(0x00000fa0, 0x00000000)
  39740         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39741         -1,
  39742         -1,
  39743         3,
  39744     },
  39745 #endif /* chips */
  39746 
  39747 #if defined(BCM_56370_A0)
  39748     { /* SOC_REG_INT_USBH_XHC_IMOD1r */
  39749         soc_block_list[61],
  39750         soc_iprocreg,
  39751         1,
  39752         0,
  39753         0x102434e4,
  39754         0,
  39755         0,
  39756         2,
  39757         soc_USBH_XHC_IMOD0r_fields,
  39758         SOC_RESET_VAL_DEC(0x00000fa0, 0x00000000)
  39759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39760         -1,
  39761         -1,
  39762         3,
  39763     },
  39764 #endif /* chips */
  39765 
  39766 #if defined(BCM_56370_A0)
  39767     { /* SOC_REG_INT_USBH_XHC_IRAADRr */
  39768         soc_block_list[61],
  39769         soc_iprocreg,
  39770         1,
  39771         0,
  39772         0x10243f98,
  39773         0,
  39774         0,
  39775         3,
  39776         soc_USBH_XHC_IRAADRr_fields,
  39777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39778         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  39779         -1,
  39780         -1,
  39781         3,
  39782     },
  39783 #endif /* chips */
  39784 
  39785 #if defined(BCM_56370_A0)
  39786     { /* SOC_REG_INT_USBH_XHC_IRADATr */
  39787         soc_block_list[61],
  39788         soc_iprocreg,
  39789         1,
  39790         0,
  39791         0x10243f9c,
  39792         0,
  39793         0,
  39794         1,
  39795         soc_USBD_BDC_IRADATr_fields,
  39796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39797         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39798         -1,
  39799         -1,
  39800         3,
  39801     },
  39802 #endif /* chips */
  39803 
  39804 #if defined(BCM_56370_A0)
  39805     { /* SOC_REG_INT_USBH_XHC_MFINDEXr */
  39806         soc_block_list[61],
  39807         soc_iprocreg,
  39808         1,
  39809         0,
  39810         0x102434a0,
  39811         0,
  39812         0,
  39813         2,
  39814         soc_USBH_XHC_MFINDEXr_fields,
  39815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39816         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39817         -1,
  39818         -1,
  39819         3,
  39820     },
  39821 #endif /* chips */
  39822 
  39823 #if defined(BCM_56370_A0)
  39824     { /* SOC_REG_INT_USBH_XHC_PAGESIZEr */
  39825         soc_block_list[61],
  39826         soc_iprocreg,
  39827         1,
  39828         0,
  39829         0x10243028,
  39830         SOC_REG_FLAG_RO,
  39831         0,
  39832         2,
  39833         soc_USBH_XHC_PAGESIZEr_fields,
  39834         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  39835         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39836         -1,
  39837         -1,
  39838         3,
  39839     },
  39840 #endif /* chips */
  39841 
  39842 #if defined(BCM_56370_A0)
  39843     { /* SOC_REG_INT_USBH_XHC_PNSTR2r */
  39844         soc_block_list[61],
  39845         soc_iprocreg,
  39846         1,
  39847         0,
  39848         0x10243954,
  39849         SOC_REG_FLAG_RO,
  39850         0,
  39851         1,
  39852         soc_USBH_XHC_PNSTR2r_fields,
  39853         SOC_RESET_VAL_DEC(0x20425355, 0x00000000)
  39854         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39855         -1,
  39856         -1,
  39857         3,
  39858     },
  39859 #endif /* chips */
  39860 
  39861 #if defined(BCM_56370_A0)
  39862     { /* SOC_REG_INT_USBH_XHC_PORTLI1r */
  39863         soc_block_list[61],
  39864         soc_iprocreg,
  39865         1,
  39866         0,
  39867         0x10243428,
  39868         SOC_REG_FLAG_RO,
  39869         0,
  39870         1,
  39871         soc_CMICD_S0_IDM_IDM_IO_STATUS_BCM53400_A0r_fields,
  39872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39873         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39874         -1,
  39875         -1,
  39876         3,
  39877     },
  39878 #endif /* chips */
  39879 
  39880 #if defined(BCM_56370_A0)
  39881     { /* SOC_REG_INT_USBH_XHC_PORTPM1r */
  39882         soc_block_list[61],
  39883         soc_iprocreg,
  39884         1,
  39885         0,
  39886         0x10243424,
  39887         0,
  39888         0,
  39889         4,
  39890         soc_USBH_XHC_PORTPM1r_fields,
  39891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39893         -1,
  39894         -1,
  39895         3,
  39896     },
  39897 #endif /* chips */
  39898 
  39899 #if defined(BCM_56370_A0)
  39900     { /* SOC_REG_INT_USBH_XHC_PORTSC1r */
  39901         soc_block_list[61],
  39902         soc_iprocreg,
  39903         1,
  39904         0,
  39905         0x10243420,
  39906         0,
  39907         0,
  39908         23,
  39909         soc_USBH_XHC_PORTSC1r_fields,
  39910         SOC_RESET_VAL_DEC(0x000002a0, 0x00000000)
  39911         SOC_RESET_MASK_DEC(0xcfffffff, 0x00000000)
  39912         -1,
  39913         -1,
  39914         3,
  39915     },
  39916 #endif /* chips */
  39917 
  39918 #if defined(BCM_56370_A0)
  39919     { /* SOC_REG_INT_USBH_XHC_PSUM2r */
  39920         soc_block_list[61],
  39921         soc_iprocreg,
  39922         1,
  39923         0,
  39924         0x10243958,
  39925         SOC_REG_FLAG_RO,
  39926         0,
  39927         9,
  39928         soc_USBH_XHC_PSUM2r_fields,
  39929         SOC_RESET_VAL_DEC(0x00000203, 0x00000000)
  39930         SOC_RESET_MASK_DEC(0xfe1fffff, 0x00000000)
  39931         -1,
  39932         -1,
  39933         3,
  39934     },
  39935 #endif /* chips */
  39936 
  39937 #if defined(BCM_56370_A0)
  39938     { /* SOC_REG_INT_USBH_XHC_PTSLTYP2r */
  39939         soc_block_list[61],
  39940         soc_iprocreg,
  39941         1,
  39942         0,
  39943         0x1024395c,
  39944         SOC_REG_FLAG_RO,
  39945         0,
  39946         2,
  39947         soc_USBH_XHC_PTSLTYP2r_fields,
  39948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39949         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39950         -1,
  39951         -1,
  39952         3,
  39953     },
  39954 #endif /* chips */
  39955 
  39956 #if defined(BCM_56370_A0)
  39957     { /* SOC_REG_INT_USBH_XHC_RTOFFr */
  39958         soc_block_list[61],
  39959         soc_iprocreg,
  39960         1,
  39961         0,
  39962         0x10243018,
  39963         SOC_REG_FLAG_RO,
  39964         0,
  39965         2,
  39966         soc_USBH_XHC_RTOFFr_fields,
  39967         SOC_RESET_VAL_DEC(0x000004a0, 0x00000000)
  39968         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  39969         -1,
  39970         -1,
  39971         3,
  39972     },
  39973 #endif /* chips */
  39974 
  39975 #if defined(BCM_56370_A0)
  39976     { /* SOC_REG_INT_USBH_XHC_SPARAMS1r */
  39977         soc_block_list[61],
  39978         soc_iprocreg,
  39979         1,
  39980         0,
  39981         0x10243004,
  39982         SOC_REG_FLAG_RO,
  39983         0,
  39984         4,
  39985         soc_USBH_XHC_SPARAMS1r_fields,
  39986         SOC_RESET_VAL_DEC(0x0400021f, 0x00000000)
  39987         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39988         -1,
  39989         -1,
  39990         3,
  39991     },
  39992 #endif /* chips */
  39993 
  39994 #if defined(BCM_56370_A0)
  39995     { /* SOC_REG_INT_USBH_XHC_SPARAMS2r */
  39996         soc_block_list[61],
  39997         soc_iprocreg,
  39998         1,
  39999         0,
  40000         0x10243008,
  40001         SOC_REG_FLAG_RO,
  40002         0,
  40003         6,
  40004         soc_USBH_XHC_SPARAMS2r_fields,
  40005         SOC_RESET_VAL_DEC(0x14000052, 0x00000000)
  40006         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40007         -1,
  40008         -1,
  40009         3,
  40010     },
  40011 #endif /* chips */
  40012 
  40013 #if defined(BCM_56370_A0)
  40014     { /* SOC_REG_INT_USBH_XHC_SPARAMS3r */
  40015         soc_block_list[61],
  40016         soc_iprocreg,
  40017         1,
  40018         0,
  40019         0x1024300c,
  40020         SOC_REG_FLAG_RO,
  40021         0,
  40022         3,
  40023         soc_USBH_XHC_SPARAMS3r_fields,
  40024         SOC_RESET_VAL_DEC(0x07ff0002, 0x00000000)
  40025         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40026         -1,
  40027         -1,
  40028         3,
  40029     },
  40030 #endif /* chips */
  40031 
  40032 #if defined(BCM_56370_A0)
  40033     { /* SOC_REG_INT_USBH_XHC_USBCMDr */
  40034         soc_block_list[61],
  40035         soc_iprocreg,
  40036         1,
  40037         0,
  40038         0x10243020,
  40039         0,
  40040         0,
  40041         12,
  40042         soc_USBH_XHC_USBCMDr_fields,
  40043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40044         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  40045         -1,
  40046         -1,
  40047         3,
  40048     },
  40049 #endif /* chips */
  40050 
  40051 #if defined(BCM_56370_A0)
  40052     { /* SOC_REG_INT_USBH_XHC_USBSTSr */
  40053         soc_block_list[61],
  40054         soc_iprocreg,
  40055         1,
  40056         0,
  40057         0x10243024,
  40058         0,
  40059         0,
  40060         10,
  40061         soc_USBH_XHC_USBSTSr_fields,
  40062         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  40063         SOC_RESET_MASK_DEC(0x00001f1f, 0x00000000)
  40064         -1,
  40065         -1,
  40066         3,
  40067     },
  40068 #endif /* chips */
  40069 
  40070 #if defined(BCM_56370_A0)
  40071     { /* SOC_REG_INT_USB_NIC_M0_IDM_IDM_INTERRUPT_STATUSr */
  40072         soc_block_list[61],
  40073         soc_iprocreg,
  40074         1,
  40075         0,
  40076         0x10256a00,
  40077         SOC_REG_FLAG_RO,
  40078         0,
  40079         3,
  40080         soc_A9JTAG_M0_IDM_IDM_INTERRUPT_STATUS_BCM53400_A0r_fields,
  40081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40082         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40083         -1,
  40084         -1,
  40085         3,
  40086     },
  40087 #endif /* chips */
  40088 
  40089 #if defined(BCM_56370_A0)
  40090     { /* SOC_REG_INT_USB_NIC_M0_IDM_IDM_RESET_CONTROLr */
  40091         soc_block_list[61],
  40092         soc_iprocreg,
  40093         1,
  40094         0,
  40095         0x10256800,
  40096         0,
  40097         0,
  40098         2,
  40099         soc_A9JTAG_M0_IDM_RESET_CONTROL_BCM53400_A0r_fields,
  40100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40101         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40102         -1,
  40103         -1,
  40104         3,
  40105     },
  40106 #endif /* chips */
  40107 
  40108 #if defined(BCM_56370_A0)
  40109     { /* SOC_REG_INT_USB_NIC_M0_IDM_IDM_RESET_STATUSr */
  40110         soc_block_list[61],
  40111         soc_iprocreg,
  40112         1,
  40113         0,
  40114         0x10256804,
  40115         SOC_REG_FLAG_RO,
  40116         0,
  40117         5,
  40118         soc_A9JTAG_M0_IDM_IDM_RESET_STATUS_BCM53400_A0r_fields,
  40119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40120         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40121         -1,
  40122         -1,
  40123         3,
  40124     },
  40125 #endif /* chips */
  40126 
  40127 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40128     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40129     { /* SOC_REG_INT_USER_OTP_BONDOPTION_127_96_REGr */
  40130         soc_block_list[1],
  40131         soc_iprocreg,
  40132         1,
  40133         0,
  40134         0x3240c0c,
  40135         SOC_REG_FLAG_RO,
  40136         0,
  40137         1,
  40138         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40140         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40141         -1,
  40142         -1,
  40143     },
  40144 #endif /* chips */
  40145 
  40146 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40147     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40148     { /* SOC_REG_INT_USER_OTP_BONDOPTION_159_128_REGr */
  40149         soc_block_list[1],
  40150         soc_iprocreg,
  40151         1,
  40152         0,
  40153         0x3240c10,
  40154         SOC_REG_FLAG_RO,
  40155         0,
  40156         1,
  40157         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40159         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40160         -1,
  40161         -1,
  40162     },
  40163 #endif /* chips */
  40164 
  40165 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40166     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40167     { /* SOC_REG_INT_USER_OTP_BONDOPTION_191_160_REGr */
  40168         soc_block_list[1],
  40169         soc_iprocreg,
  40170         1,
  40171         0,
  40172         0x3240c14,
  40173         SOC_REG_FLAG_RO,
  40174         0,
  40175         1,
  40176         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40178         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40179         -1,
  40180         -1,
  40181     },
  40182 #endif /* chips */
  40183 
  40184 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40185     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40186     { /* SOC_REG_INT_USER_OTP_BONDOPTION_223_192_REGr */
  40187         soc_block_list[1],
  40188         soc_iprocreg,
  40189         1,
  40190         0,
  40191         0x3240c18,
  40192         SOC_REG_FLAG_RO,
  40193         0,
  40194         1,
  40195         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40197         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40198         -1,
  40199         -1,
  40200     },
  40201 #endif /* chips */
  40202 
  40203 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40204     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40205     { /* SOC_REG_INT_USER_OTP_BONDOPTION_255_224_REGr */
  40206         soc_block_list[1],
  40207         soc_iprocreg,
  40208         1,
  40209         0,
  40210         0x3240c1c,
  40211         SOC_REG_FLAG_RO,
  40212         0,
  40213         1,
  40214         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40216         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40217         -1,
  40218         -1,
  40219     },
  40220 #endif /* chips */
  40221 
  40222 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40223     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40224     { /* SOC_REG_INT_USER_OTP_BONDOPTION_287_256_REGr */
  40225         soc_block_list[1],
  40226         soc_iprocreg,
  40227         1,
  40228         0,
  40229         0x3240c20,
  40230         SOC_REG_FLAG_RO,
  40231         0,
  40232         1,
  40233         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40235         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40236         -1,
  40237         -1,
  40238     },
  40239 #endif /* chips */
  40240 
  40241 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40242     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40243     { /* SOC_REG_INT_USER_OTP_BONDOPTION_319_288_REGr */
  40244         soc_block_list[1],
  40245         soc_iprocreg,
  40246         1,
  40247         0,
  40248         0x3240c24,
  40249         SOC_REG_FLAG_RO,
  40250         0,
  40251         1,
  40252         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40254         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40255         -1,
  40256         -1,
  40257     },
  40258 #endif /* chips */
  40259 
  40260 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40261     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40262     { /* SOC_REG_INT_USER_OTP_BONDOPTION_31_0_REGr */
  40263         soc_block_list[1],
  40264         soc_iprocreg,
  40265         1,
  40266         0,
  40267         0x3240c00,
  40268         SOC_REG_FLAG_RO,
  40269         0,
  40270         1,
  40271         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40273         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40274         -1,
  40275         -1,
  40276     },
  40277 #endif /* chips */
  40278 
  40279 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40280     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40281     { /* SOC_REG_INT_USER_OTP_BONDOPTION_351_320_REGr */
  40282         soc_block_list[1],
  40283         soc_iprocreg,
  40284         1,
  40285         0,
  40286         0x3240c28,
  40287         SOC_REG_FLAG_RO,
  40288         0,
  40289         1,
  40290         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40292         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40293         -1,
  40294         -1,
  40295     },
  40296 #endif /* chips */
  40297 
  40298 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40299     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40300     { /* SOC_REG_INT_USER_OTP_BONDOPTION_383_352_REGr */
  40301         soc_block_list[1],
  40302         soc_iprocreg,
  40303         1,
  40304         0,
  40305         0x3240c2c,
  40306         SOC_REG_FLAG_RO,
  40307         0,
  40308         1,
  40309         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40311         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40312         -1,
  40313         -1,
  40314     },
  40315 #endif /* chips */
  40316 
  40317 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40318     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40319     { /* SOC_REG_INT_USER_OTP_BONDOPTION_415_384_REGr */
  40320         soc_block_list[1],
  40321         soc_iprocreg,
  40322         1,
  40323         0,
  40324         0x3240c30,
  40325         SOC_REG_FLAG_RO,
  40326         0,
  40327         1,
  40328         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40330         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40331         -1,
  40332         -1,
  40333     },
  40334 #endif /* chips */
  40335 
  40336 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40337     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40338     { /* SOC_REG_INT_USER_OTP_BONDOPTION_447_416_REGr */
  40339         soc_block_list[1],
  40340         soc_iprocreg,
  40341         1,
  40342         0,
  40343         0x3240c34,
  40344         SOC_REG_FLAG_RO,
  40345         0,
  40346         1,
  40347         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40349         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40350         -1,
  40351         -1,
  40352     },
  40353 #endif /* chips */
  40354 
  40355 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40356     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40357     { /* SOC_REG_INT_USER_OTP_BONDOPTION_479_448_REGr */
  40358         soc_block_list[1],
  40359         soc_iprocreg,
  40360         1,
  40361         0,
  40362         0x3240c38,
  40363         SOC_REG_FLAG_RO,
  40364         0,
  40365         1,
  40366         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40368         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40369         -1,
  40370         -1,
  40371     },
  40372 #endif /* chips */
  40373 
  40374 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40375     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40376     { /* SOC_REG_INT_USER_OTP_BONDOPTION_511_480_REGr */
  40377         soc_block_list[1],
  40378         soc_iprocreg,
  40379         1,
  40380         0,
  40381         0x3240c3c,
  40382         SOC_REG_FLAG_RO,
  40383         0,
  40384         1,
  40385         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40387         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40388         -1,
  40389         -1,
  40390     },
  40391 #endif /* chips */
  40392 
  40393 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40394     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40395     { /* SOC_REG_INT_USER_OTP_BONDOPTION_63_32_REGr */
  40396         soc_block_list[1],
  40397         soc_iprocreg,
  40398         1,
  40399         0,
  40400         0x3240c04,
  40401         SOC_REG_FLAG_RO,
  40402         0,
  40403         1,
  40404         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40406         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40407         -1,
  40408         -1,
  40409     },
  40410 #endif /* chips */
  40411 
  40412 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  40413     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  40414     { /* SOC_REG_INT_USER_OTP_BONDOPTION_95_64_REGr */
  40415         soc_block_list[1],
  40416         soc_iprocreg,
  40417         1,
  40418         0,
  40419         0x3240c08,
  40420         SOC_REG_FLAG_RO,
  40421         0,
  40422         1,
  40423         soc_USER_OTP_BONDOPTION_127_96_REGr_fields,
  40424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40425         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40426         -1,
  40427         -1,
  40428     },
  40429 #endif /* chips */
  40430 
  40431 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \
  40432     defined(BCM_56514_A0)
  40433     { /* SOC_REG_INT_USER_TRUNK_HASH_SELECTr */
  40434         soc_block_list[5],
  40435         soc_portreg,
  40436         1,
  40437         0,
  40438         0xe000134,
  40439         0,
  40440         0,
  40441         1,
  40442         soc_IUSER_TRUNK_HASH_SELECTr_fields,
  40443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40444         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40445         -1,
  40446         -1,
  40447     },
  40448 #endif /* chips */
  40449 
  40450 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  40451     defined(BCM_56160_A0)
  40452     { /* SOC_REG_INT_USER_TRUNK_HASH_SELECT_BCM53400_A0r */
  40453         soc_block_list[5],
  40454         soc_portreg,
  40455         1,
  40456         0,
  40457         0x40006500,
  40458         0,
  40459         0,
  40460         1,
  40461         soc_IUSER_TRUNK_HASH_SELECT_BCM53400_A0r_fields,
  40462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40463         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40464         -1,
  40465         -1,
  40466     },
  40467 #endif /* chips */
  40468 
  40469 #if defined(BCM_56142_A0)
  40470     { /* SOC_REG_INT_USER_TRUNK_HASH_SELECT_BCM56142_A0r */
  40471         soc_block_list[5],
  40472         soc_portreg,
  40473         1,
  40474         0,
  40475         0x110000a4,
  40476         0,
  40477         0,
  40478         1,
  40479         soc_IUSER_TRUNK_HASH_SELECTr_fields,
  40480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40481         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40482         -1,
  40483         -1,
  40484     },
  40485 #endif /* chips */
  40486 
  40487 #if defined(BCM_56150_A0)
  40488     { /* SOC_REG_INT_USER_TRUNK_HASH_SELECT_BCM56150_A0r */
  40489         soc_block_list[5],
  40490         soc_portreg,
  40491         1,
  40492         0,
  40493         0x44006500,
  40494         0,
  40495         0,
  40496         1,
  40497         soc_IUSER_TRUNK_HASH_SELECT_BCM56150_A0r_fields,
  40498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40499         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40500         -1,
  40501         -1,
  40502     },
  40503 #endif /* chips */
  40504 
  40505 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
  40506     defined(BCM_56224_A0) || defined(BCM_56224_B0)
  40507     { /* SOC_REG_INT_USER_TRUNK_HASH_SELECT_BCM56224_A0r */
  40508         soc_block_list[5],
  40509         soc_portreg,
  40510         1,
  40511         0,
  40512         0xf000134,
  40513         0,
  40514         0,
  40515         1,
  40516         soc_IUSER_TRUNK_HASH_SELECTr_fields,
  40517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40518         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  40519         -1,
  40520         -1,
  40521     },
  40522 #endif /* chips */
  40523 
  40524 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \
  40525     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  40526     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  40527     defined(BCM_56685_A0) || defined(BCM_56685_B0) || \
  40528     defined(BCM_56840_A0) || defined(BCM_56840_B0)
  40529     { /* SOC_REG_INT_USE_SP_SHAREDr */
  40530         soc_block_list[4],
  40531         soc_genreg,
  40532         1,
  40533         0,
  40534         0x2080132,
  40535         0,
  40536         0,
  40537         1,
  40538         soc_COLOR_AWAREr_fields,
  40539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40540         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  40541         -1,
  40542         -1,
  40543     },
  40544 #endif /* chips */
  40545 
  40546 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  40547     defined(BCM_56270_A0)
  40548     { /* SOC_REG_INT_USE_SP_SHARED_BCM56260_A0r */
  40549         soc_block_list[4],
  40550         soc_genreg,
  40551         1,
  40552         0,
  40553         0xa013200,
  40554         0,
  40555         0,
  40556         1,
  40557         soc_SER_RING_ERR_CTRLr_fields,
  40558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40559         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  40560         -1,
  40561         -1,
  40562     },
  40563 #endif /* chips */
  40564 
  40565 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \
  40566     defined(BCM_56450_B0) || defined(BCM_56450_B1) || \
  40567     defined(BCM_56640_A0)
  40568     { /* SOC_REG_INT_USE_SP_SHARED_BCM56640_A0r */
  40569         soc_block_list[4],
  40570         soc_genreg,
  40571         1,
  40572         0,
  40573         0xa013200,
  40574         0,
  40575         0,
  40576         1,
  40577         soc_AXP_CH_MMU_REQ_ENr_fields,
  40578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40579         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  40580         -1,
  40581         -1,
  40582     },
  40583 #endif /* chips */
  40584