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allregs_q.i (1237686B)

      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_q.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
     16     { /* SOC_REG_INT_QBLOCK_NEXT_MEMDEBUGr */
     17         soc_block_list[4],
     18         soc_genreg,
     19         1,
     20         0,
     21         0x2a080021,
     22         0,
     23         0,
     24         9,
     25         soc_QBLOCK_NEXT_MEMDEBUGr_fields,
     26         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     27         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
     28         -1,
     29         -1,
     30     },
     31 #endif /* chips */
     32 
     33 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
     34     { /* SOC_REG_INT_QBLOCK_NEXT_MEMDEBUG_BCM56260_A0r */
     35         soc_block_list[4],
     36         soc_genreg,
     37         1,
     38         0,
     39         0xaa001300,
     40         0,
     41         0,
     42         1,
     43         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
     44         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     45         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
     46         -1,
     47         -1,
     48     },
     49 #endif /* chips */
     50 
     51 #if defined(BCM_56270_A0)
     52     { /* SOC_REG_INT_QBLOCK_NEXT_MEMDEBUG_BCM56270_A0r */
     53         soc_block_list[4],
     54         soc_genreg,
     55         1,
     56         0,
     57         0xaa001200,
     58         0,
     59         0,
     60         1,
     61         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
     62         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     63         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
     64         -1,
     65         -1,
     66     },
     67 #endif /* chips */
     68 
     69 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
     70     defined(BCM_56450_B1)
     71     { /* SOC_REG_INT_QBLOCK_NEXT_MEMDEBUG_BCM56450_A0r */
     72         soc_block_list[4],
     73         soc_genreg,
     74         1,
     75         0,
     76         0xaa001f00,
     77         0,
     78         0,
     79         1,
     80         soc_FT_CNTR_RAM_CONTROLr_fields,
     81         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     82         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
     83         -1,
     84         -1,
     85     },
     86 #endif /* chips */
     87 
     88 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
     89     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_0r */
     90         soc_block_list[4],
     91         soc_genreg,
     92         1,
     93         0,
     94         0x2a080032,
     95         0,
     96         0,
     97         1,
     98         soc_EGR_MASK_ECC_STATUSr_fields,
     99         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    100         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    101         -1,
    102         -1,
    103     },
    104 #endif /* chips */
    105 
    106 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    107     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_1r */
    108         soc_block_list[4],
    109         soc_genreg,
    110         1,
    111         0,
    112         0x2a080033,
    113         0,
    114         0,
    115         1,
    116         soc_EGR_MASK_ECC_STATUSr_fields,
    117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    118         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    119         -1,
    120         -1,
    121     },
    122 #endif /* chips */
    123 
    124 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    125     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_2r */
    126         soc_block_list[4],
    127         soc_genreg,
    128         1,
    129         0,
    130         0x2a080034,
    131         0,
    132         0,
    133         1,
    134         soc_EGR_MASK_ECC_STATUSr_fields,
    135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    136         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    137         -1,
    138         -1,
    139     },
    140 #endif /* chips */
    141 
    142 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    143     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_3r */
    144         soc_block_list[4],
    145         soc_genreg,
    146         1,
    147         0,
    148         0x2a080035,
    149         0,
    150         0,
    151         1,
    152         soc_EGR_MASK_ECC_STATUSr_fields,
    153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    154         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    155         -1,
    156         -1,
    157     },
    158 #endif /* chips */
    159 
    160 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    161     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_4r */
    162         soc_block_list[4],
    163         soc_genreg,
    164         1,
    165         0,
    166         0x2a080036,
    167         0,
    168         0,
    169         1,
    170         soc_EGR_MASK_ECC_STATUSr_fields,
    171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    172         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    173         -1,
    174         -1,
    175     },
    176 #endif /* chips */
    177 
    178 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    179     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_5r */
    180         soc_block_list[4],
    181         soc_genreg,
    182         1,
    183         0,
    184         0x2a080037,
    185         0,
    186         0,
    187         1,
    188         soc_EGR_MASK_ECC_STATUSr_fields,
    189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    190         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    191         -1,
    192         -1,
    193     },
    194 #endif /* chips */
    195 
    196 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    197     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_6r */
    198         soc_block_list[4],
    199         soc_genreg,
    200         1,
    201         0,
    202         0x2a080038,
    203         0,
    204         0,
    205         1,
    206         soc_EGR_MASK_ECC_STATUSr_fields,
    207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    208         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    209         -1,
    210         -1,
    211     },
    212 #endif /* chips */
    213 
    214 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    215     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_7r */
    216         soc_block_list[4],
    217         soc_genreg,
    218         1,
    219         0,
    220         0x2a080039,
    221         0,
    222         0,
    223         1,
    224         soc_EGR_MASK_ECC_STATUSr_fields,
    225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    226         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    227         -1,
    228         -1,
    229     },
    230 #endif /* chips */
    231 
    232 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
    233     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_0_BCM56260_A0r */
    234         soc_block_list[4],
    235         soc_genreg,
    236         1,
    237         0,
    238         0xaa001500,
    239         0,
    240         0,
    241         1,
    242         soc_MMU_REPL_HEAD_TBL_ECC_STATUS_BCM56260_A0r_fields,
    243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    244         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
    245         -1,
    246         -1,
    247     },
    248 #endif /* chips */
    249 
    250 #if defined(BCM_56270_A0)
    251     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_0_BCM56270_A0r */
    252         soc_block_list[4],
    253         soc_genreg,
    254         1,
    255         0,
    256         0xaa001400,
    257         0,
    258         0,
    259         1,
    260         soc_CTR_FLEX_CNT_ECC_STATUS_BCM56260_A0r_fields,
    261         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    262         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    263         -1,
    264         -1,
    265     },
    266 #endif /* chips */
    267 
    268 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    269     defined(BCM_56450_B1)
    270     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_0_BCM56450_A0r */
    271         soc_block_list[4],
    272         soc_genreg,
    273         1,
    274         0,
    275         0xaa003000,
    276         0,
    277         0,
    278         1,
    279         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
    280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    281         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    282         -1,
    283         -1,
    284     },
    285 #endif /* chips */
    286 
    287 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    288     defined(BCM_56450_B1)
    289     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_1_BCM56450_A0r */
    290         soc_block_list[4],
    291         soc_genreg,
    292         1,
    293         0,
    294         0xaa003100,
    295         0,
    296         0,
    297         1,
    298         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
    299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    300         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    301         -1,
    302         -1,
    303     },
    304 #endif /* chips */
    305 
    306 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    307     defined(BCM_56450_B1)
    308     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_2_BCM56450_A0r */
    309         soc_block_list[4],
    310         soc_genreg,
    311         1,
    312         0,
    313         0xaa003200,
    314         0,
    315         0,
    316         1,
    317         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
    318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    319         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    320         -1,
    321         -1,
    322     },
    323 #endif /* chips */
    324 
    325 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    326     defined(BCM_56450_B1)
    327     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_3_BCM56450_A0r */
    328         soc_block_list[4],
    329         soc_genreg,
    330         1,
    331         0,
    332         0xaa003300,
    333         0,
    334         0,
    335         1,
    336         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
    337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    338         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    339         -1,
    340         -1,
    341     },
    342 #endif /* chips */
    343 
    344 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    345     defined(BCM_56450_B1)
    346     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_4_BCM56450_A0r */
    347         soc_block_list[4],
    348         soc_genreg,
    349         1,
    350         0,
    351         0xaa003400,
    352         0,
    353         0,
    354         1,
    355         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
    356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    357         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    358         -1,
    359         -1,
    360     },
    361 #endif /* chips */
    362 
    363 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    364     defined(BCM_56450_B1)
    365     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_5_BCM56450_A0r */
    366         soc_block_list[4],
    367         soc_genreg,
    368         1,
    369         0,
    370         0xaa003500,
    371         0,
    372         0,
    373         1,
    374         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
    375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    376         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    377         -1,
    378         -1,
    379     },
    380 #endif /* chips */
    381 
    382 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    383     defined(BCM_56450_B1)
    384     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_6_BCM56450_A0r */
    385         soc_block_list[4],
    386         soc_genreg,
    387         1,
    388         0,
    389         0xaa003600,
    390         0,
    391         0,
    392         1,
    393         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
    394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    395         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    396         -1,
    397         -1,
    398     },
    399 #endif /* chips */
    400 
    401 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    402     defined(BCM_56450_B1)
    403     { /* SOC_REG_INT_QBLOCK_NEXT_MEM_ECC_STATUS_7_BCM56450_A0r */
    404         soc_block_list[4],
    405         soc_genreg,
    406         1,
    407         0,
    408         0xaa003700,
    409         0,
    410         0,
    411         1,
    412         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
    413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    414         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
    415         -1,
    416         -1,
    417     },
    418 #endif /* chips */
    419 
    420 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    421     { /* SOC_REG_INT_QCN_CNM_PRP_CNTr */
    422         soc_block_list[4],
    423         soc_genreg,
    424         1,
    425         0,
    426         0x9a004000,
    427         0,
    428         0,
    429         1,
    430         soc_ECC_SINGLE_BIT_ERRORS_BCM56640_A0r_fields,
    431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    433         -1,
    434         -1,
    435     },
    436 #endif /* chips */
    437 
    438 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
    439     { /* SOC_REG_INT_QCN_CNM_PRP_CNT_BCM56560_A0r */
    440         soc_block_list[4],
    441         soc_genreg,
    442         1,
    443         0,
    444         0x5e004000,
    445         0,
    446         0,
    447         1,
    448         soc_CT_PURGE_CNTr_fields,
    449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    451         -1,
    452         -1,
    453     },
    454 #endif /* chips */
    455 
    456 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
    457     { /* SOC_REG_INT_QCN_CNM_PRP_CNT_BCM56850_A0r */
    458         soc_block_list[4],
    459         soc_genreg,
    460         1,
    461         0,
    462         0x5e004000,
    463         0,
    464         0,
    465         1,
    466         soc_ECC_SINGLE_BIT_ERRORS_BCM56640_A0r_fields,
    467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
    469         -1,
    470         -1,
    471     },
    472 #endif /* chips */
    473 
    474 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    475     { /* SOC_REG_INT_QCN_CNM_PRP_CTRLr */
    476         soc_block_list[5],
    477         soc_portreg,
    478         1,
    479         0,
    480         0x38001000,
    481         0,
    482         0,
    483         2,
    484         soc_QCN_CNM_PRP_CTRLr_fields,
    485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    486         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
    487         -1,
    488         -1,
    489     },
    490 #endif /* chips */
    491 
    492 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
    493     { /* SOC_REG_INT_QCN_CNM_PRP_CTRL_BCM56560_A0r */
    494         soc_block_list[5],
    495         soc_portreg,
    496         1,
    497         0,
    498         0x54007c00,
    499         0,
    500         0,
    501         2,
    502         soc_QCN_CNM_PRP_CTRL_BCM56560_A0r_fields,
    503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    504         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
    505         -1,
    506         -1,
    507     },
    508 #endif /* chips */
    509 
    510 #if defined(BCM_56850_A0)
    511     { /* SOC_REG_INT_QCN_CNM_PRP_CTRL_BCM56850_A0r */
    512         soc_block_list[5],
    513         soc_portreg,
    514         1,
    515         0,
    516         0x44007c00,
    517         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    518         0,
    519         2,
    520         soc_QCN_CNM_PRP_CTRLr_fields,
    521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    522         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
    523         -1,
    524         -1,
    525     },
    526 #endif /* chips */
    527 
    528 #if defined(BCM_56860_A0)
    529     { /* SOC_REG_INT_QCN_CNM_PRP_CTRL_BCM56860_A0r */
    530         soc_block_list[5],
    531         soc_portreg,
    532         1,
    533         0,
    534         0x54007c00,
    535         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    536         0,
    537         2,
    538         soc_QCN_CNM_PRP_CTRLr_fields,
    539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    540         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
    541         -1,
    542         -1,
    543     },
    544 #endif /* chips */
    545 
    546 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    547     { /* SOC_REG_INT_QCN_CNM_PRP_DLF_COUNTr */
    548         soc_block_list[5],
    549         soc_genreg,
    550         1,
    551         0,
    552         0x3a000a00,
    553         0,
    554         0,
    555         1,
    556         soc_QCN_CNM_PRP_DLF_COUNTr_fields,
    557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    558         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    559         -1,
    560         -1,
    561     },
    562 #endif /* chips */
    563 
    564 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
    565     defined(BCM_56670_A0) || defined(BCM_56670_B0)
    566     { /* SOC_REG_INT_QCN_CNM_PRP_DLF_COUNT_BCM56560_A0r */
    567         soc_block_list[5],
    568         soc_genreg,
    569         1,
    570         0,
    571         0x56007b00,
    572         0,
    573         0,
    574         1,
    575         soc_QCN_CNM_PRP_DLF_COUNT_BCM56560_A0r_fields,
    576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    577         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    578         -1,
    579         -1,
    580     },
    581 #endif /* chips */
    582 
    583 #if defined(BCM_56850_A0)
    584     { /* SOC_REG_INT_QCN_CNM_PRP_DLF_COUNT_BCM56850_A0r */
    585         soc_block_list[5],
    586         soc_genreg,
    587         1,
    588         0,
    589         0x46007b00,
    590         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    591         0,
    592         1,
    593         soc_QCN_CNM_PRP_DLF_COUNTr_fields,
    594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    595         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    596         -1,
    597         -1,
    598     },
    599 #endif /* chips */
    600 
    601 #if defined(BCM_56860_A0)
    602     { /* SOC_REG_INT_QCN_CNM_PRP_DLF_COUNT_BCM56860_A0r */
    603         soc_block_list[5],
    604         soc_genreg,
    605         1,
    606         0,
    607         0x56007b00,
    608         (6 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    609         0,
    610         1,
    611         soc_QCN_CNM_PRP_DLF_COUNTr_fields,
    612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    613         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    614         -1,
    615         -1,
    616     },
    617 #endif /* chips */
    618 
    619 #if defined(BCM_56850_A0)
    620     { /* SOC_REG_INT_QCN_CNM_PRP_DLF_COUNT_Xr */
    621         soc_block_list[5],
    622         soc_genreg,
    623         1,
    624         0,
    625         0x46007b00,
    626         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    627         0,
    628         1,
    629         soc_QCN_CNM_PRP_DLF_COUNTr_fields,
    630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    631         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    632         -1,
    633         -1,
    634     },
    635 #endif /* chips */
    636 
    637 #if defined(BCM_56860_A0)
    638     { /* SOC_REG_INT_QCN_CNM_PRP_DLF_COUNT_X_BCM56860_A0r */
    639         soc_block_list[5],
    640         soc_genreg,
    641         1,
    642         0,
    643         0x56007b00,
    644         (1 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    645         0,
    646         1,
    647         soc_QCN_CNM_PRP_DLF_COUNTr_fields,
    648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    649         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    650         -1,
    651         -1,
    652     },
    653 #endif /* chips */
    654 
    655 #if defined(BCM_56850_A0)
    656     { /* SOC_REG_INT_QCN_CNM_PRP_DLF_COUNT_Yr */
    657         soc_block_list[5],
    658         soc_genreg,
    659         1,
    660         0,
    661         0x46007b00,
    662         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    663         0,
    664         1,
    665         soc_QCN_CNM_PRP_DLF_COUNTr_fields,
    666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    667         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    668         -1,
    669         -1,
    670     },
    671 #endif /* chips */
    672 
    673 #if defined(BCM_56860_A0)
    674     { /* SOC_REG_INT_QCN_CNM_PRP_DLF_COUNT_Y_BCM56860_A0r */
    675         soc_block_list[5],
    676         soc_genreg,
    677         1,
    678         0,
    679         0x56007b00,
    680         (2 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    681         0,
    682         1,
    683         soc_QCN_CNM_PRP_DLF_COUNTr_fields,
    684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    685         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
    686         -1,
    687         -1,
    688     },
    689 #endif /* chips */
    690 
    691 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    692     { /* SOC_REG_INT_QCN_CNM_RVD_TBL_ECC_ERR1r */
    693         soc_block_list[4],
    694         soc_genreg,
    695         1,
    696         0,
    697         0x9a004800,
    698         0,
    699         0,
    700         3,
    701         soc_QCN_CNM_RVD_TBL_ECC_ERR1r_fields,
    702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    703         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
    704         -1,
    705         -1,
    706     },
    707 #endif /* chips */
    708 
    709 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    710     { /* SOC_REG_INT_QCN_CNM_RVD_TBL_ECC_ERR2r */
    711         soc_block_list[4],
    712         soc_genreg,
    713         1,
    714         0,
    715         0x9a004900,
    716         0,
    717         0,
    718         3,
    719         soc_QCN_CNM_RVD_TBL_ECC_ERR1r_fields,
    720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    721         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
    722         -1,
    723         -1,
    724     },
    725 #endif /* chips */
    726 
    727 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    728     { /* SOC_REG_INT_QCN_CNM_TIMER_TBL_ECC_ERR1r */
    729         soc_block_list[4],
    730         soc_genreg,
    731         1,
    732         0,
    733         0x9a004600,
    734         0,
    735         0,
    736         3,
    737         soc_QCN_CNM_RVD_TBL_ECC_ERR1r_fields,
    738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    739         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
    740         -1,
    741         -1,
    742     },
    743 #endif /* chips */
    744 
    745 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    746     { /* SOC_REG_INT_QCN_CNM_TIMER_TBL_ECC_ERR2r */
    747         soc_block_list[4],
    748         soc_genreg,
    749         1,
    750         0,
    751         0x9a004700,
    752         0,
    753         0,
    754         3,
    755         soc_QCN_CNM_RVD_TBL_ECC_ERR1r_fields,
    756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    757         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
    758         -1,
    759         -1,
    760     },
    761 #endif /* chips */
    762 
    763 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    764     { /* SOC_REG_INT_QCN_PFC_STATEr */
    765         soc_block_list[4],
    766         soc_portreg,
    767         1,
    768         0,
    769         0x98003000,
    770         0,
    771         0,
    772         1,
    773         soc_CHFC2PFC_STATE_BCM56640_A0r_fields,
    774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    775         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    776         -1,
    777         -1,
    778     },
    779 #endif /* chips */
    780 
    781 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
    782     { /* SOC_REG_INT_QCN_PFC_STATE_BCM56560_A0r */
    783         soc_block_list[4],
    784         soc_portreg,
    785         1,
    786         0,
    787         0x5c003000,
    788         0,
    789         0,
    790         1,
    791         soc_CHFC2PFC_STATE_BCM56960_A0r_fields,
    792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    793         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    794         -1,
    795         86,
    796     },
    797 #endif /* chips */
    798 
    799 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
    800     { /* SOC_REG_INT_QCN_PFC_STATE_BCM56850_A0r */
    801         soc_block_list[4],
    802         soc_portreg,
    803         1,
    804         0,
    805         0x5c003000,
    806         0,
    807         0,
    808         1,
    809         soc_CHFC2PFC_STATE_BCM56640_A0r_fields,
    810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    811         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    812         -1,
    813         72,
    814     },
    815 #endif /* chips */
    816 
    817 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    818     { /* SOC_REG_INT_QCN_TBID_TBL_ECC_ERR1r */
    819         soc_block_list[4],
    820         soc_genreg,
    821         1,
    822         0,
    823         0x9a004200,
    824         0,
    825         0,
    826         3,
    827         soc_CHFC_TC2PRI_TBL_ECC_ERR1r_fields,
    828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    829         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    830         -1,
    831         -1,
    832     },
    833 #endif /* chips */
    834 
    835 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    836     { /* SOC_REG_INT_QCN_TBID_TBL_ECC_ERR2r */
    837         soc_block_list[4],
    838         soc_genreg,
    839         1,
    840         0,
    841         0x9a004300,
    842         0,
    843         0,
    844         3,
    845         soc_CHFC_TC2PRI_TBL_ECC_ERR1r_fields,
    846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    847         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    848         -1,
    849         -1,
    850     },
    851 #endif /* chips */
    852 
    853 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    854     { /* SOC_REG_INT_QCN_TOV_TBL_ECC_ERR1r */
    855         soc_block_list[4],
    856         soc_genreg,
    857         1,
    858         0,
    859         0x9a004400,
    860         0,
    861         0,
    862         3,
    863         soc_QCN_TOV_TBL_ECC_ERR1r_fields,
    864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    865         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    866         -1,
    867         -1,
    868     },
    869 #endif /* chips */
    870 
    871 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
    872     { /* SOC_REG_INT_QCN_TOV_TBL_ECC_ERR2r */
    873         soc_block_list[4],
    874         soc_genreg,
    875         1,
    876         0,
    877         0x9a004500,
    878         0,
    879         0,
    880         3,
    881         soc_QCN_TOV_TBL_ECC_ERR1r_fields,
    882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    883         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
    884         -1,
    885         -1,
    886     },
    887 #endif /* chips */
    888 
    889 #if defined(BCM_56850_A0)
    890     { /* SOC_REG_INT_QDB_MEM_DEBUG_TMr */
    891         soc_block_list[4],
    892         soc_genreg,
    893         1,
    894         0,
    895         0x12002700,
    896         0,
    897         0,
    898         6,
    899         soc_QDB_MEM_DEBUG_TMr_fields,
    900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    901         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    902         -1,
    903         -1,
    904     },
    905 #endif /* chips */
    906 
    907 #if defined(BCM_56370_A0) || defined(BCM_56770_A0)
    908     { /* SOC_REG_INT_QDB_MEM_DEBUG_TM_BCM56370_A0r */
    909         soc_block_list[125],
    910         soc_xpereg,
    911         1,
    912         0,
    913         0x6802700,
    914         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    915         0,
    916         3,
    917         soc_QDB_MEM_DEBUG_TM_BCM56370_A0r_fields,
    918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    919         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    920         -1,
    921         -1,
    922         3,
    923     },
    924 #endif /* chips */
    925 
    926 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
    927     defined(BCM_56670_A0) || defined(BCM_56670_B0)
    928     { /* SOC_REG_INT_QDB_MEM_DEBUG_TM_BCM56560_A0r */
    929         soc_block_list[4],
    930         soc_genreg,
    931         1,
    932         0,
    933         0x12002600,
    934         0,
    935         0,
    936         4,
    937         soc_QDB_MEM_DEBUG_TM_BCM56560_A0r_fields,
    938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    939         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    940         -1,
    941         -1,
    942     },
    943 #endif /* chips */
    944 
    945 #if defined(BCM_56860_A0)
    946     { /* SOC_REG_INT_QDB_MEM_DEBUG_TM_BCM56860_A0r */
    947         soc_block_list[4],
    948         soc_genreg,
    949         1,
    950         0,
    951         0x12002700,
    952         0,
    953         0,
    954         6,
    955         soc_QDB_MEM_DEBUG_TM_BCM56860_A0r_fields,
    956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    957         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    958         -1,
    959         -1,
    960     },
    961 #endif /* chips */
    962 
    963 #if defined(BCM_56870_A0)
    964     { /* SOC_REG_INT_QDB_MEM_DEBUG_TM_BCM56870_A0r */
    965         soc_block_list[125],
    966         soc_xpereg,
    967         1,
    968         0,
    969         0x6802700,
    970         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    971         0,
    972         6,
    973         soc_QDB_MEM_DEBUG_TM_BCM56870_A0r_fields,
    974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    975         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    976         -1,
    977         -1,
    978         3,
    979     },
    980 #endif /* chips */
    981 
    982 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
    983     { /* SOC_REG_INT_QDB_MEM_DEBUG_TM_BCM56960_A0r */
    984         soc_block_list[125],
    985         soc_xpereg,
    986         1,
    987         0,
    988         0xa802700,
    989         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
    990         0,
    991         8,
    992         soc_QDB_MEM_DEBUG_TM_BCM56960_A0r_fields,
    993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    994         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    995         -1,
    996         -1,
    997         3,
    998     },
    999 #endif /* chips */
   1000 
   1001 #if defined(BCM_56970_A0)
   1002     { /* SOC_REG_INT_QDB_MEM_DEBUG_TM_BCM56970_A0r */
   1003         soc_block_list[125],
   1004         soc_xpereg,
   1005         1,
   1006         0,
   1007         0x6802700,
   1008         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   1009         0,
   1010         8,
   1011         soc_QDB_MEM_DEBUG_TM_BCM56970_A0r_fields,
   1012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1013         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1014         -1,
   1015         -1,
   1016         3,
   1017     },
   1018 #endif /* chips */
   1019 
   1020 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1021     { /* SOC_REG_INT_QENTRY_LOWER_MEMDEBUG_0r */
   1022         soc_block_list[4],
   1023         soc_genreg,
   1024         1,
   1025         0,
   1026         0x2a08001f,
   1027         0,
   1028         0,
   1029         4,
   1030         soc_QENTRY_LOWER_MEMDEBUG_0r_fields,
   1031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1032         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1033         -1,
   1034         -1,
   1035     },
   1036 #endif /* chips */
   1037 
   1038 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1039     { /* SOC_REG_INT_QENTRY_LOWER_MEMDEBUG_1r */
   1040         soc_block_list[4],
   1041         soc_genreg,
   1042         1,
   1043         0,
   1044         0x2a080020,
   1045         0,
   1046         0,
   1047         14,
   1048         soc_QENTRY_LOWER_MEMDEBUG_1r_fields,
   1049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1050         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1051         -1,
   1052         -1,
   1053     },
   1054 #endif /* chips */
   1055 
   1056 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1057     defined(BCM_56450_B1)
   1058     { /* SOC_REG_INT_QENTRY_LOWER_MEMDEBUG_0_BCM56450_A0r */
   1059         soc_block_list[4],
   1060         soc_genreg,
   1061         1,
   1062         0,
   1063         0xaa001e00,
   1064         0,
   1065         0,
   1066         2,
   1067         soc_QENTRY_LOWER_MEMDEBUG_0_BCM56450_A0r_fields,
   1068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1069         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1070         -1,
   1071         -1,
   1072     },
   1073 #endif /* chips */
   1074 
   1075 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1076     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_0r */
   1077         soc_block_list[4],
   1078         soc_genreg,
   1079         1,
   1080         0,
   1081         0x2a08002a,
   1082         0,
   1083         0,
   1084         1,
   1085         soc_EGR_MASK_ECC_STATUSr_fields,
   1086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1087         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1088         -1,
   1089         -1,
   1090     },
   1091 #endif /* chips */
   1092 
   1093 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1094     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_1r */
   1095         soc_block_list[4],
   1096         soc_genreg,
   1097         1,
   1098         0,
   1099         0x2a08002b,
   1100         0,
   1101         0,
   1102         1,
   1103         soc_EGR_MASK_ECC_STATUSr_fields,
   1104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1105         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1106         -1,
   1107         -1,
   1108     },
   1109 #endif /* chips */
   1110 
   1111 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1112     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_2r */
   1113         soc_block_list[4],
   1114         soc_genreg,
   1115         1,
   1116         0,
   1117         0x2a08002c,
   1118         0,
   1119         0,
   1120         1,
   1121         soc_EGR_MASK_ECC_STATUSr_fields,
   1122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1123         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1124         -1,
   1125         -1,
   1126     },
   1127 #endif /* chips */
   1128 
   1129 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1130     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_3r */
   1131         soc_block_list[4],
   1132         soc_genreg,
   1133         1,
   1134         0,
   1135         0x2a08002d,
   1136         0,
   1137         0,
   1138         1,
   1139         soc_EGR_MASK_ECC_STATUSr_fields,
   1140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1141         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1142         -1,
   1143         -1,
   1144     },
   1145 #endif /* chips */
   1146 
   1147 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1148     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_4r */
   1149         soc_block_list[4],
   1150         soc_genreg,
   1151         1,
   1152         0,
   1153         0x2a08002e,
   1154         0,
   1155         0,
   1156         1,
   1157         soc_EGR_MASK_ECC_STATUSr_fields,
   1158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1159         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1160         -1,
   1161         -1,
   1162     },
   1163 #endif /* chips */
   1164 
   1165 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1166     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_5r */
   1167         soc_block_list[4],
   1168         soc_genreg,
   1169         1,
   1170         0,
   1171         0x2a08002f,
   1172         0,
   1173         0,
   1174         1,
   1175         soc_EGR_MASK_ECC_STATUSr_fields,
   1176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1177         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1178         -1,
   1179         -1,
   1180     },
   1181 #endif /* chips */
   1182 
   1183 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1184     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_6r */
   1185         soc_block_list[4],
   1186         soc_genreg,
   1187         1,
   1188         0,
   1189         0x2a080030,
   1190         0,
   1191         0,
   1192         1,
   1193         soc_EGR_MASK_ECC_STATUSr_fields,
   1194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1195         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1196         -1,
   1197         -1,
   1198     },
   1199 #endif /* chips */
   1200 
   1201 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1202     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_7r */
   1203         soc_block_list[4],
   1204         soc_genreg,
   1205         1,
   1206         0,
   1207         0x2a080031,
   1208         0,
   1209         0,
   1210         1,
   1211         soc_EGR_MASK_ECC_STATUSr_fields,
   1212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1213         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1214         -1,
   1215         -1,
   1216     },
   1217 #endif /* chips */
   1218 
   1219 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1220     defined(BCM_56450_B1)
   1221     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_0_BCM56450_A0r */
   1222         soc_block_list[4],
   1223         soc_genreg,
   1224         1,
   1225         0,
   1226         0xaa002800,
   1227         0,
   1228         0,
   1229         1,
   1230         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
   1231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1232         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1233         -1,
   1234         -1,
   1235     },
   1236 #endif /* chips */
   1237 
   1238 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1239     defined(BCM_56450_B1)
   1240     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_1_BCM56450_A0r */
   1241         soc_block_list[4],
   1242         soc_genreg,
   1243         1,
   1244         0,
   1245         0xaa002900,
   1246         0,
   1247         0,
   1248         1,
   1249         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
   1250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1251         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1252         -1,
   1253         -1,
   1254     },
   1255 #endif /* chips */
   1256 
   1257 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1258     defined(BCM_56450_B1)
   1259     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_2_BCM56450_A0r */
   1260         soc_block_list[4],
   1261         soc_genreg,
   1262         1,
   1263         0,
   1264         0xaa002a00,
   1265         0,
   1266         0,
   1267         1,
   1268         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
   1269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1270         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1271         -1,
   1272         -1,
   1273     },
   1274 #endif /* chips */
   1275 
   1276 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1277     defined(BCM_56450_B1)
   1278     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_3_BCM56450_A0r */
   1279         soc_block_list[4],
   1280         soc_genreg,
   1281         1,
   1282         0,
   1283         0xaa002b00,
   1284         0,
   1285         0,
   1286         1,
   1287         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
   1288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1289         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1290         -1,
   1291         -1,
   1292     },
   1293 #endif /* chips */
   1294 
   1295 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1296     defined(BCM_56450_B1)
   1297     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_4_BCM56450_A0r */
   1298         soc_block_list[4],
   1299         soc_genreg,
   1300         1,
   1301         0,
   1302         0xaa002c00,
   1303         0,
   1304         0,
   1305         1,
   1306         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
   1307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1308         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1309         -1,
   1310         -1,
   1311     },
   1312 #endif /* chips */
   1313 
   1314 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1315     defined(BCM_56450_B1)
   1316     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_5_BCM56450_A0r */
   1317         soc_block_list[4],
   1318         soc_genreg,
   1319         1,
   1320         0,
   1321         0xaa002d00,
   1322         0,
   1323         0,
   1324         1,
   1325         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
   1326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1327         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1328         -1,
   1329         -1,
   1330     },
   1331 #endif /* chips */
   1332 
   1333 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1334     defined(BCM_56450_B1)
   1335     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_6_BCM56450_A0r */
   1336         soc_block_list[4],
   1337         soc_genreg,
   1338         1,
   1339         0,
   1340         0xaa002e00,
   1341         0,
   1342         0,
   1343         1,
   1344         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
   1345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1346         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1347         -1,
   1348         -1,
   1349     },
   1350 #endif /* chips */
   1351 
   1352 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1353     defined(BCM_56450_B1)
   1354     { /* SOC_REG_INT_QENTRY_LOWER_MEM_ECC_STATUS_7_BCM56450_A0r */
   1355         soc_block_list[4],
   1356         soc_genreg,
   1357         1,
   1358         0,
   1359         0xaa002f00,
   1360         0,
   1361         0,
   1362         1,
   1363         soc_CTR_FLEX_CNT_ECC_STATUSr_fields,
   1364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1365         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1366         -1,
   1367         -1,
   1368     },
   1369 #endif /* chips */
   1370 
   1371 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   1372     { /* SOC_REG_INT_QENTRY_L_MEMDEBUGr */
   1373         soc_block_list[4],
   1374         soc_genreg,
   1375         1,
   1376         0,
   1377         0xaa001200,
   1378         0,
   1379         0,
   1380         1,
   1381         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   1382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1384         -1,
   1385         -1,
   1386     },
   1387 #endif /* chips */
   1388 
   1389 #if defined(BCM_56270_A0)
   1390     { /* SOC_REG_INT_QENTRY_L_MEMDEBUG_BCM56270_A0r */
   1391         soc_block_list[4],
   1392         soc_genreg,
   1393         1,
   1394         0,
   1395         0xaa001100,
   1396         0,
   1397         0,
   1398         1,
   1399         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
   1400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1401         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1402         -1,
   1403         -1,
   1404     },
   1405 #endif /* chips */
   1406 
   1407 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   1408     { /* SOC_REG_INT_QENTRY_MEM_ECC_STATUS_0r */
   1409         soc_block_list[4],
   1410         soc_genreg,
   1411         1,
   1412         0,
   1413         0xaa001400,
   1414         0,
   1415         0,
   1416         1,
   1417         soc_QENTRY_MEM_ECC_STATUS_0r_fields,
   1418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1419         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   1420         -1,
   1421         -1,
   1422     },
   1423 #endif /* chips */
   1424 
   1425 #if defined(BCM_56270_A0)
   1426     { /* SOC_REG_INT_QENTRY_MEM_ECC_STATUS_0_BCM56270_A0r */
   1427         soc_block_list[4],
   1428         soc_genreg,
   1429         1,
   1430         0,
   1431         0xaa001300,
   1432         0,
   1433         0,
   1434         1,
   1435         soc_MMU_CCPE_MEM_ECC_STATUS_BCM56260_A0r_fields,
   1436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1437         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1438         -1,
   1439         -1,
   1440     },
   1441 #endif /* chips */
   1442 
   1443 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1444     { /* SOC_REG_INT_QENTRY_UPPER_MEMDEBUG_0r */
   1445         soc_block_list[4],
   1446         soc_genreg,
   1447         1,
   1448         0,
   1449         0x2a08001d,
   1450         0,
   1451         0,
   1452         4,
   1453         soc_QENTRY_LOWER_MEMDEBUG_0r_fields,
   1454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1455         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1456         -1,
   1457         -1,
   1458     },
   1459 #endif /* chips */
   1460 
   1461 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1462     { /* SOC_REG_INT_QENTRY_UPPER_MEMDEBUG_1r */
   1463         soc_block_list[4],
   1464         soc_genreg,
   1465         1,
   1466         0,
   1467         0x2a08001e,
   1468         0,
   1469         0,
   1470         14,
   1471         soc_QENTRY_LOWER_MEMDEBUG_1r_fields,
   1472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1473         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1474         -1,
   1475         -1,
   1476     },
   1477 #endif /* chips */
   1478 
   1479 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1480     defined(BCM_56450_B1)
   1481     { /* SOC_REG_INT_QENTRY_UPPER_MEMDEBUG_0_BCM56450_A0r */
   1482         soc_block_list[4],
   1483         soc_genreg,
   1484         1,
   1485         0,
   1486         0xaa001d00,
   1487         0,
   1488         0,
   1489         2,
   1490         soc_QENTRY_LOWER_MEMDEBUG_0_BCM56450_A0r_fields,
   1491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1492         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1493         -1,
   1494         -1,
   1495     },
   1496 #endif /* chips */
   1497 
   1498 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1499     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_0r */
   1500         soc_block_list[4],
   1501         soc_genreg,
   1502         1,
   1503         0,
   1504         0x2a080022,
   1505         0,
   1506         0,
   1507         1,
   1508         soc_QENTRY_UPPER_MEM_ECC_STATUS_0r_fields,
   1509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1510         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1511         -1,
   1512         -1,
   1513     },
   1514 #endif /* chips */
   1515 
   1516 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1517     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_1r */
   1518         soc_block_list[4],
   1519         soc_genreg,
   1520         1,
   1521         0,
   1522         0x2a080023,
   1523         0,
   1524         0,
   1525         1,
   1526         soc_QENTRY_UPPER_MEM_ECC_STATUS_0r_fields,
   1527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1528         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1529         -1,
   1530         -1,
   1531     },
   1532 #endif /* chips */
   1533 
   1534 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1535     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_2r */
   1536         soc_block_list[4],
   1537         soc_genreg,
   1538         1,
   1539         0,
   1540         0x2a080024,
   1541         0,
   1542         0,
   1543         1,
   1544         soc_QENTRY_UPPER_MEM_ECC_STATUS_0r_fields,
   1545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1546         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1547         -1,
   1548         -1,
   1549     },
   1550 #endif /* chips */
   1551 
   1552 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1553     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_3r */
   1554         soc_block_list[4],
   1555         soc_genreg,
   1556         1,
   1557         0,
   1558         0x2a080025,
   1559         0,
   1560         0,
   1561         1,
   1562         soc_QENTRY_UPPER_MEM_ECC_STATUS_0r_fields,
   1563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1564         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1565         -1,
   1566         -1,
   1567     },
   1568 #endif /* chips */
   1569 
   1570 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1571     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_4r */
   1572         soc_block_list[4],
   1573         soc_genreg,
   1574         1,
   1575         0,
   1576         0x2a080026,
   1577         0,
   1578         0,
   1579         1,
   1580         soc_QENTRY_UPPER_MEM_ECC_STATUS_0r_fields,
   1581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1582         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1583         -1,
   1584         -1,
   1585     },
   1586 #endif /* chips */
   1587 
   1588 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1589     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_5r */
   1590         soc_block_list[4],
   1591         soc_genreg,
   1592         1,
   1593         0,
   1594         0x2a080027,
   1595         0,
   1596         0,
   1597         1,
   1598         soc_QENTRY_UPPER_MEM_ECC_STATUS_0r_fields,
   1599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1600         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1601         -1,
   1602         -1,
   1603     },
   1604 #endif /* chips */
   1605 
   1606 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1607     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_6r */
   1608         soc_block_list[4],
   1609         soc_genreg,
   1610         1,
   1611         0,
   1612         0x2a080028,
   1613         0,
   1614         0,
   1615         1,
   1616         soc_QENTRY_UPPER_MEM_ECC_STATUS_0r_fields,
   1617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1618         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1619         -1,
   1620         -1,
   1621     },
   1622 #endif /* chips */
   1623 
   1624 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   1625     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_7r */
   1626         soc_block_list[4],
   1627         soc_genreg,
   1628         1,
   1629         0,
   1630         0x2a080029,
   1631         0,
   1632         0,
   1633         1,
   1634         soc_QENTRY_UPPER_MEM_ECC_STATUS_0r_fields,
   1635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1636         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1637         -1,
   1638         -1,
   1639     },
   1640 #endif /* chips */
   1641 
   1642 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1643     defined(BCM_56450_B1)
   1644     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_0_BCM56450_A0r */
   1645         soc_block_list[4],
   1646         soc_genreg,
   1647         1,
   1648         0,
   1649         0xaa002000,
   1650         0,
   1651         0,
   1652         1,
   1653         soc_MMU_REPL_HEAD_TBL_ECC_STATUSr_fields,
   1654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1655         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1656         -1,
   1657         -1,
   1658     },
   1659 #endif /* chips */
   1660 
   1661 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1662     defined(BCM_56450_B1)
   1663     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_1_BCM56450_A0r */
   1664         soc_block_list[4],
   1665         soc_genreg,
   1666         1,
   1667         0,
   1668         0xaa002100,
   1669         0,
   1670         0,
   1671         1,
   1672         soc_MMU_REPL_HEAD_TBL_ECC_STATUSr_fields,
   1673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1674         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1675         -1,
   1676         -1,
   1677     },
   1678 #endif /* chips */
   1679 
   1680 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1681     defined(BCM_56450_B1)
   1682     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_2_BCM56450_A0r */
   1683         soc_block_list[4],
   1684         soc_genreg,
   1685         1,
   1686         0,
   1687         0xaa002200,
   1688         0,
   1689         0,
   1690         1,
   1691         soc_MMU_REPL_HEAD_TBL_ECC_STATUSr_fields,
   1692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1693         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1694         -1,
   1695         -1,
   1696     },
   1697 #endif /* chips */
   1698 
   1699 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1700     defined(BCM_56450_B1)
   1701     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_3_BCM56450_A0r */
   1702         soc_block_list[4],
   1703         soc_genreg,
   1704         1,
   1705         0,
   1706         0xaa002300,
   1707         0,
   1708         0,
   1709         1,
   1710         soc_MMU_REPL_HEAD_TBL_ECC_STATUSr_fields,
   1711         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1712         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1713         -1,
   1714         -1,
   1715     },
   1716 #endif /* chips */
   1717 
   1718 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1719     defined(BCM_56450_B1)
   1720     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_4_BCM56450_A0r */
   1721         soc_block_list[4],
   1722         soc_genreg,
   1723         1,
   1724         0,
   1725         0xaa002400,
   1726         0,
   1727         0,
   1728         1,
   1729         soc_MMU_REPL_HEAD_TBL_ECC_STATUSr_fields,
   1730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1731         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1732         -1,
   1733         -1,
   1734     },
   1735 #endif /* chips */
   1736 
   1737 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1738     defined(BCM_56450_B1)
   1739     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_5_BCM56450_A0r */
   1740         soc_block_list[4],
   1741         soc_genreg,
   1742         1,
   1743         0,
   1744         0xaa002500,
   1745         0,
   1746         0,
   1747         1,
   1748         soc_MMU_REPL_HEAD_TBL_ECC_STATUSr_fields,
   1749         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1750         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1751         -1,
   1752         -1,
   1753     },
   1754 #endif /* chips */
   1755 
   1756 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1757     defined(BCM_56450_B1)
   1758     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_6_BCM56450_A0r */
   1759         soc_block_list[4],
   1760         soc_genreg,
   1761         1,
   1762         0,
   1763         0xaa002600,
   1764         0,
   1765         0,
   1766         1,
   1767         soc_MMU_REPL_HEAD_TBL_ECC_STATUSr_fields,
   1768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1769         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1770         -1,
   1771         -1,
   1772     },
   1773 #endif /* chips */
   1774 
   1775 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   1776     defined(BCM_56450_B1)
   1777     { /* SOC_REG_INT_QENTRY_UPPER_MEM_ECC_STATUS_7_BCM56450_A0r */
   1778         soc_block_list[4],
   1779         soc_genreg,
   1780         1,
   1781         0,
   1782         0xaa002700,
   1783         0,
   1784         0,
   1785         1,
   1786         soc_MMU_REPL_HEAD_TBL_ECC_STATUSr_fields,
   1787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1788         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   1789         -1,
   1790         -1,
   1791     },
   1792 #endif /* chips */
   1793 
   1794 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   1795     { /* SOC_REG_INT_QENTRY_U_MEMDEBUGr */
   1796         soc_block_list[4],
   1797         soc_genreg,
   1798         1,
   1799         0,
   1800         0xaa001100,
   1801         0,
   1802         0,
   1803         1,
   1804         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
   1805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1806         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1807         -1,
   1808         -1,
   1809     },
   1810 #endif /* chips */
   1811 
   1812 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   1813     defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   1814     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   1815     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   1816     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   1817     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   1818     { /* SOC_REG_INT_QE_INTEROP_CONFIGr */
   1819         soc_block_list[4],
   1820         soc_genreg,
   1821         1,
   1822         0,
   1823         0x308001a,
   1824         0,
   1825         0,
   1826         1,
   1827         soc_QE_INTEROP_CONFIGr_fields,
   1828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1829         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1830         -1,
   1831         -1,
   1832     },
   1833 #endif /* chips */
   1834 
   1835 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   1836     { /* SOC_REG_INT_QGPORT_CONFIGr */
   1837         soc_block_list[13],
   1838         soc_genreg,
   1839         1,
   1840         0,
   1841         0x80d00,
   1842         0,
   1843         0,
   1844         2,
   1845         soc_GPORT_CONFIGr_fields,
   1846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1847         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1848         -1,
   1849         -1,
   1850     },
   1851 #endif /* chips */
   1852 
   1853 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   1854     { /* SOC_REG_INT_QGPORT_MAC_XGXS_CTRLr */
   1855         soc_block_list[13],
   1856         soc_genreg,
   1857         1,
   1858         0,
   1859         0x80d01,
   1860         0,
   1861         0,
   1862         11,
   1863         soc_MAC_XGXS_CTRL_BCM56800_A0r_fields,
   1864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1865         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1866         -1,
   1867         -1,
   1868     },
   1869 #endif /* chips */
   1870 
   1871 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   1872     { /* SOC_REG_INT_QGPORT_MAC_XGXS_STAT_GS0r */
   1873         soc_block_list[13],
   1874         soc_genreg,
   1875         1,
   1876         0,
   1877         0x80d02,
   1878         SOC_REG_FLAG_RO,
   1879         0,
   1880         22,
   1881         soc_MAC_XGXS_STAT_BCM56800_A0r_fields,
   1882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1883         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1884         -1,
   1885         -1,
   1886     },
   1887 #endif /* chips */
   1888 
   1889 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   1890     { /* SOC_REG_INT_QGPORT_MAC_XGXS_STAT_GS1r */
   1891         soc_block_list[13],
   1892         soc_genreg,
   1893         1,
   1894         0,
   1895         0x80d03,
   1896         SOC_REG_FLAG_RO,
   1897         0,
   1898         22,
   1899         soc_MAC_XGXS_STAT_BCM56800_A0r_fields,
   1900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1901         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1902         -1,
   1903         -1,
   1904     },
   1905 #endif /* chips */
   1906 
   1907 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   1908     { /* SOC_REG_INT_QGPORT_MAC_XGXS_STAT_GS2r */
   1909         soc_block_list[13],
   1910         soc_genreg,
   1911         1,
   1912         0,
   1913         0x80d04,
   1914         SOC_REG_FLAG_RO,
   1915         0,
   1916         22,
   1917         soc_MAC_XGXS_STAT_BCM56800_A0r_fields,
   1918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1919         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1920         -1,
   1921         -1,
   1922     },
   1923 #endif /* chips */
   1924 
   1925 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   1926     { /* SOC_REG_INT_QGPORT_MAC_XGXS_STAT_GS3r */
   1927         soc_block_list[13],
   1928         soc_genreg,
   1929         1,
   1930         0,
   1931         0x80d05,
   1932         SOC_REG_FLAG_RO,
   1933         0,
   1934         22,
   1935         soc_MAC_XGXS_STAT_BCM56800_A0r_fields,
   1936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1937         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1938         -1,
   1939         -1,
   1940     },
   1941 #endif /* chips */
   1942 
   1943 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   1944     defined(BCM_56334_B0)
   1945     { /* SOC_REG_INT_QPORT_CNTMAXSIZEr */
   1946         soc_block_list[14],
   1947         soc_genreg,
   1948         1,
   1949         0,
   1950         0x80903,
   1951         0,
   1952         0,
   1953         1,
   1954         soc_GPORT_CNTMAXSIZEr_fields,
   1955         SOC_RESET_VAL_DEC(0x000005ee, 0x00000000)
   1956         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   1957         -1,
   1958         -1,
   1959     },
   1960 #endif /* chips */
   1961 
   1962 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   1963     defined(BCM_56334_B0)
   1964     { /* SOC_REG_INT_QPORT_CONFIGr */
   1965         soc_block_list[14],
   1966         soc_genreg,
   1967         1,
   1968         0,
   1969         0x80900,
   1970         0,
   1971         0,
   1972         1,
   1973         soc_GPORT_CONFIG_BCM56624_A0r_fields,
   1974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1975         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1976         -1,
   1977         -1,
   1978     },
   1979 #endif /* chips */
   1980 
   1981 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   1982     defined(BCM_56334_B0)
   1983     { /* SOC_REG_INT_QPORT_RSV_MASKr */
   1984         soc_block_list[14],
   1985         soc_genreg,
   1986         1,
   1987         0,
   1988         0x80901,
   1989         0,
   1990         0,
   1991         1,
   1992         soc_GPORT_RSV_MASK_BCM56334_A0r_fields,
   1993         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
   1994         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   1995         -1,
   1996         -1,
   1997     },
   1998 #endif /* chips */
   1999 
   2000 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   2001     defined(BCM_56334_B0)
   2002     { /* SOC_REG_INT_QPORT_SGNDET_EARLYCRSr */
   2003         soc_block_list[14],
   2004         soc_portreg,
   2005         1,
   2006         0,
   2007         0x908,
   2008         0,
   2009         0,
   2010         2,
   2011         soc_GPORT_SGNDET_EARLYCRSr_fields,
   2012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2013         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   2014         -1,
   2015         -1,
   2016     },
   2017 #endif /* chips */
   2018 
   2019 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   2020     defined(BCM_56334_B0)
   2021     { /* SOC_REG_INT_QPORT_STAT_UPDATE_MASKr */
   2022         soc_block_list[14],
   2023         soc_genreg,
   2024         1,
   2025         0,
   2026         0x80902,
   2027         0,
   2028         0,
   2029         1,
   2030         soc_GPORT_RSV_MASK_BCM56334_A0r_fields,
   2031         SOC_RESET_VAL_DEC(0x00000070, 0x00000000)
   2032         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   2033         -1,
   2034         -1,
   2035     },
   2036 #endif /* chips */
   2037 
   2038 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \
   2039     defined(BCM_56334_B0)
   2040     { /* SOC_REG_INT_QPORT_TPIDr */
   2041         soc_block_list[14],
   2042         soc_genreg,
   2043         1,
   2044         0,
   2045         0x80907,
   2046         0,
   2047         0,
   2048         1,
   2049         soc_GPORT_TPIDr_fields,
   2050         SOC_RESET_VAL_DEC(0x00008100, 0x00000000)
   2051         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2052         -1,
   2053         -1,
   2054     },
   2055 #endif /* chips */
   2056 
   2057 #if defined(BCM_88790_A0)
   2058     { /* SOC_REG_INT_QRH_ALLOWED_LINKS_PIPE_0_REGISTERr */
   2059         soc_block_list[107],
   2060         soc_genreg,
   2061         1,
   2062         0,
   2063         0x109,
   2064         SOC_REG_FLAG_ABOVE_64_BITS,
   2065         0,
   2066         1,
   2067         soc_QRH_ALLOWED_LINKS_PIPE_0_REGISTERr_fields,
   2068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2069         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2070         -1,
   2071         -1,
   2072     },
   2073 #endif /* chips */
   2074 
   2075 #if defined(BCM_88790_A0)
   2076     { /* SOC_REG_INT_QRH_ALLOWED_LINKS_PIPE_1_REGISTERr */
   2077         soc_block_list[107],
   2078         soc_genreg,
   2079         1,
   2080         0,
   2081         0x10f,
   2082         SOC_REG_FLAG_ABOVE_64_BITS,
   2083         0,
   2084         1,
   2085         soc_QRH_ALLOWED_LINKS_PIPE_1_REGISTERr_fields,
   2086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2088         -1,
   2089         -1,
   2090     },
   2091 #endif /* chips */
   2092 
   2093 #if defined(BCM_88790_A0)
   2094     { /* SOC_REG_INT_QRH_ALLOWED_LINKS_PIPE_2_REGISTERr */
   2095         soc_block_list[107],
   2096         soc_genreg,
   2097         1,
   2098         0,
   2099         0x115,
   2100         SOC_REG_FLAG_ABOVE_64_BITS,
   2101         0,
   2102         1,
   2103         soc_QRH_ALLOWED_LINKS_PIPE_2_REGISTERr_fields,
   2104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2105         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2106         -1,
   2107         -1,
   2108     },
   2109 #endif /* chips */
   2110 
   2111 #if defined(BCM_88790_A0)
   2112     { /* SOC_REG_INT_QRH_ALL_MUL_DROP_THr */
   2113         soc_block_list[107],
   2114         soc_genreg,
   2115         1,
   2116         0,
   2117         0x125,
   2118         SOC_REG_FLAG_64_BITS,
   2119         0,
   2120         3,
   2121         soc_QRH_ALL_MUL_DROP_THr_fields,
   2122         SOC_RESET_VAL_DEC(0x08000200, 0x00000000)
   2123         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
   2124         -1,
   2125         -1,
   2126     },
   2127 #endif /* chips */
   2128 
   2129 #if defined(BCM_88790_A0)
   2130     { /* SOC_REG_INT_QRH_AUTO_DOC_NAME_0r */
   2131         soc_block_list[107],
   2132         soc_genreg,
   2133         1,
   2134         0,
   2135         0x107,
   2136         0,
   2137         0,
   2138         1,
   2139         soc_QRH_AUTO_DOC_NAME_0r_fields,
   2140         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   2141         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2142         -1,
   2143         -1,
   2144     },
   2145 #endif /* chips */
   2146 
   2147 #if defined(BCM_88790_A0)
   2148     { /* SOC_REG_INT_QRH_AUTO_DOC_NAME_1r */
   2149         soc_block_list[107],
   2150         soc_genreg,
   2151         1,
   2152         0,
   2153         0x13e,
   2154         SOC_REG_FLAG_ABOVE_64_BITS,
   2155         0,
   2156         1,
   2157         soc_QRH_AUTO_DOC_NAME_1r_fields,
   2158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2159         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2160         -1,
   2161         -1,
   2162     },
   2163 #endif /* chips */
   2164 
   2165 #if defined(BCM_88790_A0)
   2166     { /* SOC_REG_INT_QRH_CRH_INTERRUPT_MASK_REGISTERr */
   2167         soc_block_list[107],
   2168         soc_genreg,
   2169         1,
   2170         0,
   2171         0x104,
   2172         0,
   2173         0,
   2174         3,
   2175         soc_QRH_CRH_INTERRUPT_MASK_REGISTERr_fields,
   2176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2177         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2178         -1,
   2179         -1,
   2180     },
   2181 #endif /* chips */
   2182 
   2183 #if defined(BCM_88790_A0)
   2184     { /* SOC_REG_INT_QRH_CRH_INTERRUPT_REGISTERr */
   2185         soc_block_list[107],
   2186         soc_genreg,
   2187         1,
   2188         0,
   2189         0x103,
   2190         SOC_REG_FLAG_INTERRUPT |
   2191                           SOC_REG_FLAG_SIGNAL,
   2192         0,
   2193         3,
   2194         soc_QRH_CRH_INTERRUPT_REGISTERr_fields,
   2195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2196         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2197         -1,
   2198         -1,
   2199     },
   2200 #endif /* chips */
   2201 
   2202 #if defined(BCM_88790_A0)
   2203     { /* SOC_REG_INT_QRH_CRH_INTERRUPT_REGISTER_TESTr */
   2204         soc_block_list[107],
   2205         soc_genreg,
   2206         1,
   2207         0,
   2208         0x105,
   2209         0,
   2210         0,
   2211         1,
   2212         soc_QRH_CRH_INTERRUPT_REGISTER_TESTr_fields,
   2213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2214         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2215         -1,
   2216         -1,
   2217     },
   2218 #endif /* chips */
   2219 
   2220 #if defined(BCM_88790_A0)
   2221     { /* SOC_REG_INT_QRH_DRH_DROPPED_LOW_MULr */
   2222         soc_block_list[107],
   2223         soc_genreg,
   2224         1,
   2225         0,
   2226         0x127,
   2227         SOC_REG_FLAG_RO,
   2228         SOC_REG_FLAG_COUNTER_FEILDS,
   2229         2,
   2230         soc_QRH_DRH_DROPPED_LOW_MULr_fields,
   2231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2232         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2233         -1,
   2234         -1,
   2235     },
   2236 #endif /* chips */
   2237 
   2238 #if defined(BCM_88790_A0)
   2239     { /* SOC_REG_INT_QRH_DRH_FLOW_CONTROL_CNT_Pr */
   2240         soc_block_list[107],
   2241         soc_genreg,
   2242         3,
   2243         0,
   2244         0x12c,
   2245         SOC_REG_FLAG_ARRAY |
   2246                           SOC_REG_FLAG_RO |
   2247                           SOC_REG_FLAG_REG_ARRAY,
   2248         SOC_REG_FLAG_COUNTER_FEILDS,
   2249         1,
   2250         soc_QRH_DRH_FLOW_CONTROL_CNT_Pr_fields,
   2251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2252         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2253         -1,
   2254         -1,
   2255     },
   2256 #endif /* chips */
   2257 
   2258 #if defined(BCM_88790_A0)
   2259     { /* SOC_REG_INT_QRH_DRH_INPUT_QUERY_CNT_Pr */
   2260         soc_block_list[107],
   2261         soc_genreg,
   2262         3,
   2263         0,
   2264         0x129,
   2265         SOC_REG_FLAG_ARRAY |
   2266                           SOC_REG_FLAG_RO |
   2267                           SOC_REG_FLAG_REG_ARRAY,
   2268         SOC_REG_FLAG_COUNTER_FEILDS,
   2269         1,
   2270         soc_QRH_DRH_INPUT_QUERY_CNT_Pr_fields,
   2271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2272         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2273         -1,
   2274         -1,
   2275     },
   2276 #endif /* chips */
   2277 
   2278 #if defined(BCM_88790_A0)
   2279     { /* SOC_REG_INT_QRH_DRH_INTERRUPT_MASK_REGISTERr */
   2280         soc_block_list[107],
   2281         soc_genreg,
   2282         1,
   2283         0,
   2284         0x101,
   2285         0,
   2286         0,
   2287         6,
   2288         soc_QRH_DRH_INTERRUPT_MASK_REGISTERr_fields,
   2289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2290         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2291         -1,
   2292         -1,
   2293     },
   2294 #endif /* chips */
   2295 
   2296 #if defined(BCM_88790_A0)
   2297     { /* SOC_REG_INT_QRH_DRH_INTERRUPT_REGISTERr */
   2298         soc_block_list[107],
   2299         soc_genreg,
   2300         1,
   2301         0,
   2302         0x100,
   2303         SOC_REG_FLAG_INTERRUPT |
   2304                           SOC_REG_FLAG_SIGNAL,
   2305         0,
   2306         6,
   2307         soc_QRH_DRH_INTERRUPT_REGISTERr_fields,
   2308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2309         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2310         -1,
   2311         -1,
   2312     },
   2313 #endif /* chips */
   2314 
   2315 #if defined(BCM_88790_A0)
   2316     { /* SOC_REG_INT_QRH_DRH_INTERRUPT_REGISTER_TESTr */
   2317         soc_block_list[107],
   2318         soc_genreg,
   2319         1,
   2320         0,
   2321         0x102,
   2322         0,
   2323         0,
   2324         1,
   2325         soc_QRH_DRH_INTERRUPT_REGISTER_TESTr_fields,
   2326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2327         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2328         -1,
   2329         -1,
   2330     },
   2331 #endif /* chips */
   2332 
   2333 #if defined(BCM_88790_A0)
   2334     { /* SOC_REG_INT_QRH_DRH_LOAD_BALANCING_GENERAL_CONFIGr */
   2335         soc_block_list[107],
   2336         soc_genreg,
   2337         1,
   2338         0,
   2339         0x135,
   2340         SOC_REG_FLAG_64_BITS,
   2341         0,
   2342         6,
   2343         soc_QRH_DRH_LOAD_BALANCING_GENERAL_CONFIGr_fields,
   2344         SOC_RESET_VAL_DEC(0x00000030, 0x0000ffff)
   2345         SOC_RESET_MASK_DEC(0x0000007f, 0xffffffff)
   2346         -1,
   2347         -1,
   2348     },
   2349 #endif /* chips */
   2350 
   2351 #if defined(BCM_88790_A0)
   2352     { /* SOC_REG_INT_QRH_DRH_LOAD_BALANCING_LEVEL_CONFIGr */
   2353         soc_block_list[107],
   2354         soc_genreg,
   2355         1,
   2356         0,
   2357         0x132,
   2358         SOC_REG_FLAG_64_BITS,
   2359         0,
   2360         4,
   2361         soc_QRH_DRH_LOAD_BALANCING_LEVEL_CONFIGr_fields,
   2362         SOC_RESET_VAL_DEC(0x11008ff0, 0x00000000)
   2363         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   2364         -1,
   2365         -1,
   2366     },
   2367 #endif /* chips */
   2368 
   2369 #if defined(BCM_88790_A0)
   2370     { /* SOC_REG_INT_QRH_DRH_LOAD_BALANCING_LEVEL_OPTIMIZATIONr */
   2371         soc_block_list[107],
   2372         soc_genreg,
   2373         1,
   2374         0,
   2375         0x134,
   2376         0,
   2377         0,
   2378         3,
   2379         soc_QRH_DRH_LOAD_BALANCING_LEVEL_OPTIMIZATIONr_fields,
   2380         SOC_RESET_VAL_DEC(0xffff0080, 0x00000000)
   2381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2382         -1,
   2383         -1,
   2384     },
   2385 #endif /* chips */
   2386 
   2387 #if defined(BCM_88790_A0)
   2388     { /* SOC_REG_INT_QRH_DRH_MCSFF_HIT_COUNTERr */
   2389         soc_block_list[107],
   2390         soc_genreg,
   2391         1,
   2392         0,
   2393         0x128,
   2394         SOC_REG_FLAG_RO,
   2395         SOC_REG_FLAG_COUNTER_FEILDS,
   2396         2,
   2397         soc_QRH_DRH_MCSFF_HIT_COUNTERr_fields,
   2398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2399         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2400         -1,
   2401         -1,
   2402     },
   2403 #endif /* chips */
   2404 
   2405 #if defined(BCM_88790_A0)
   2406     { /* SOC_REG_INT_QRH_DRH_OUTPUT_REPLY_CNT_Pr */
   2407         soc_block_list[107],
   2408         soc_genreg,
   2409         3,
   2410         0,
   2411         0x12f,
   2412         SOC_REG_FLAG_ARRAY |
   2413                           SOC_REG_FLAG_RO |
   2414                           SOC_REG_FLAG_REG_ARRAY,
   2415         SOC_REG_FLAG_COUNTER_FEILDS,
   2416         1,
   2417         soc_QRH_DRH_OUTPUT_REPLY_CNT_Pr_fields,
   2418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2420         -1,
   2421         -1,
   2422     },
   2423 #endif /* chips */
   2424 
   2425 #if defined(BCM_88790_A0)
   2426     { /* SOC_REG_INT_QRH_DRH_REP_FIFO_STAT_Pr */
   2427         soc_block_list[107],
   2428         soc_genreg,
   2429         3,
   2430         0,
   2431         0x151,
   2432         SOC_REG_FLAG_ARRAY |
   2433                           SOC_REG_FLAG_RO |
   2434                           SOC_REG_FLAG_REG_ARRAY,
   2435         0,
   2436         1,
   2437         soc_QRH_DRH_REP_FIFO_STAT_Pr_fields,
   2438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2439         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   2440         -1,
   2441         -1,
   2442     },
   2443 #endif /* chips */
   2444 
   2445 #if defined(BCM_88790_A0)
   2446     { /* SOC_REG_INT_QRH_DRH_UNREACHABLEMULTICASTINFOr */
   2447         soc_block_list[107],
   2448         soc_genreg,
   2449         1,
   2450         0,
   2451         0x121,
   2452         SOC_REG_FLAG_RO,
   2453         0,
   2454         2,
   2455         soc_QRH_DRH_UNREACHABLEMULTICASTINFOr_fields,
   2456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2457         SOC_RESET_MASK_DEC(0x7ffff7ff, 0x00000000)
   2458         -1,
   2459         -1,
   2460     },
   2461 #endif /* chips */
   2462 
   2463 #if defined(BCM_88790_A0)
   2464     { /* SOC_REG_INT_QRH_DRH_WFQ_CONFIGURATIONSr */
   2465         soc_block_list[107],
   2466         soc_genreg,
   2467         1,
   2468         0,
   2469         0x141,
   2470         SOC_REG_FLAG_ABOVE_64_BITS,
   2471         0,
   2472         10,
   2473         soc_QRH_DRH_WFQ_CONFIGURATIONSr_fields,
   2474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2475         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2476         -1,
   2477         -1,
   2478     },
   2479 #endif /* chips */
   2480 
   2481 #if defined(BCM_88790_A0)
   2482     { /* SOC_REG_INT_QRH_DYN_PIPES_WEIGHTS_REGISTERr */
   2483         soc_block_list[107],
   2484         soc_genreg,
   2485         1,
   2486         0,
   2487         0x146,
   2488         0,
   2489         0,
   2490         5,
   2491         soc_QRH_DYN_PIPES_WEIGHTS_REGISTERr_fields,
   2492         SOC_RESET_VAL_DEC(0x81010101, 0x00000000)
   2493         SOC_RESET_MASK_DEC(0xff7f7f7f, 0x00000000)
   2494         -1,
   2495         -1,
   2496     },
   2497 #endif /* chips */
   2498 
   2499 #if defined(BCM_88790_A0)
   2500     { /* SOC_REG_INT_QRH_ECC_1B_ERR_CNTr */
   2501         soc_block_list[107],
   2502         soc_genreg,
   2503         1,
   2504         0,
   2505         0x94,
   2506         SOC_REG_FLAG_64_BITS |
   2507                           SOC_REG_FLAG_RO,
   2508         SOC_REG_FLAG_COUNTER_FEILDS,
   2509         4,
   2510         soc_QRH_ECC_1B_ERR_CNTr_fields,
   2511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2512         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2513         -1,
   2514         -1,
   2515     },
   2516 #endif /* chips */
   2517 
   2518 #if defined(BCM_88790_A0)
   2519     { /* SOC_REG_INT_QRH_ECC_2B_ERR_CNTr */
   2520         soc_block_list[107],
   2521         soc_genreg,
   2522         1,
   2523         0,
   2524         0x96,
   2525         SOC_REG_FLAG_64_BITS |
   2526                           SOC_REG_FLAG_RO,
   2527         SOC_REG_FLAG_COUNTER_FEILDS,
   2528         4,
   2529         soc_QRH_ECC_2B_ERR_CNTr_fields,
   2530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2531         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   2532         -1,
   2533         -1,
   2534     },
   2535 #endif /* chips */
   2536 
   2537 #if defined(BCM_88790_A0)
   2538     { /* SOC_REG_INT_QRH_ECC_ERR_1B_INITIATEr */
   2539         soc_block_list[107],
   2540         soc_genreg,
   2541         1,
   2542         0,
   2543         0xa4,
   2544         0,
   2545         0,
   2546         30,
   2547         soc_QRH_ECC_ERR_1B_INITIATEr_fields,
   2548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2549         SOC_RESET_MASK_DEC(0xfffff3ff, 0x00000000)
   2550         -1,
   2551         -1,
   2552     },
   2553 #endif /* chips */
   2554 
   2555 #if defined(BCM_88790_A0)
   2556     { /* SOC_REG_INT_QRH_ECC_ERR_1B_MONITOR_MEM_MASKr */
   2557         soc_block_list[107],
   2558         soc_genreg,
   2559         1,
   2560         0,
   2561         0x9a,
   2562         0,
   2563         0,
   2564         30,
   2565         soc_QRH_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
   2566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2567         SOC_RESET_MASK_DEC(0xfffff3ff, 0x00000000)
   2568         -1,
   2569         -1,
   2570     },
   2571 #endif /* chips */
   2572 
   2573 #if defined(BCM_88790_A0)
   2574     { /* SOC_REG_INT_QRH_ECC_ERR_2B_INITIATEr */
   2575         soc_block_list[107],
   2576         soc_genreg,
   2577         1,
   2578         0,
   2579         0xa6,
   2580         0,
   2581         0,
   2582         30,
   2583         soc_QRH_ECC_ERR_2B_INITIATEr_fields,
   2584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2585         SOC_RESET_MASK_DEC(0xfffff3ff, 0x00000000)
   2586         -1,
   2587         -1,
   2588     },
   2589 #endif /* chips */
   2590 
   2591 #if defined(BCM_88790_A0)
   2592     { /* SOC_REG_INT_QRH_ECC_ERR_2B_MONITOR_MEM_MASKr */
   2593         soc_block_list[107],
   2594         soc_genreg,
   2595         1,
   2596         0,
   2597         0x9c,
   2598         0,
   2599         0,
   2600         30,
   2601         soc_QRH_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
   2602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2603         SOC_RESET_MASK_DEC(0xfffff3ff, 0x00000000)
   2604         -1,
   2605         -1,
   2606     },
   2607 #endif /* chips */
   2608 
   2609 #if defined(BCM_88790_A0)
   2610     { /* SOC_REG_INT_QRH_ECC_INTERRUPT_REGISTERr */
   2611         soc_block_list[107],
   2612         soc_genreg,
   2613         1,
   2614         0,
   2615         0x7,
   2616         SOC_REG_FLAG_INTERRUPT |
   2617                           SOC_REG_FLAG_SIGNAL,
   2618         0,
   2619         3,
   2620         soc_QRH_ECC_INTERRUPT_REGISTERr_fields,
   2621         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2622         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2623         -1,
   2624         -1,
   2625     },
   2626 #endif /* chips */
   2627 
   2628 #if defined(BCM_88790_A0)
   2629     { /* SOC_REG_INT_QRH_ECC_INTERRUPT_REGISTER_MASKr */
   2630         soc_block_list[107],
   2631         soc_genreg,
   2632         1,
   2633         0,
   2634         0x17,
   2635         0,
   2636         0,
   2637         3,
   2638         soc_QRH_ECC_INTERRUPT_REGISTER_MASKr_fields,
   2639         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2640         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2641         -1,
   2642         -1,
   2643     },
   2644 #endif /* chips */
   2645 
   2646 #if defined(BCM_88790_A0)
   2647     { /* SOC_REG_INT_QRH_ECC_INTERRUPT_REGISTER_TESTr */
   2648         soc_block_list[107],
   2649         soc_genreg,
   2650         1,
   2651         0,
   2652         0x1f,
   2653         0,
   2654         0,
   2655         1,
   2656         soc_QRH_ECC_INTERRUPT_REGISTER_TESTr_fields,
   2657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2658         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2659         -1,
   2660         -1,
   2661     },
   2662 #endif /* chips */
   2663 
   2664 #if defined(BCM_88790_A0)
   2665     { /* SOC_REG_INT_QRH_ENABLE_DYNAMIC_MEMORY_ACCESSr */
   2666         soc_block_list[107],
   2667         soc_genreg,
   2668         1,
   2669         0,
   2670         0x84,
   2671         0,
   2672         0,
   2673         1,
   2674         soc_QRH_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
   2675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2676         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2677         -1,
   2678         -1,
   2679     },
   2680 #endif /* chips */
   2681 
   2682 #if defined(BCM_88790_A0)
   2683     { /* SOC_REG_INT_QRH_ERROR_INITIATION_DATAr */
   2684         soc_block_list[107],
   2685         soc_genreg,
   2686         1,
   2687         0,
   2688         0xa3,
   2689         0,
   2690         0,
   2691         1,
   2692         soc_QRH_ERROR_INITIATION_DATAr_fields,
   2693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2694         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2695         -1,
   2696         -1,
   2697     },
   2698 #endif /* chips */
   2699 
   2700 #if defined(BCM_88790_A0)
   2701     { /* SOC_REG_INT_QRH_FE_GLOBAL_FE_DEST_IDS_1r */
   2702         soc_block_list[107],
   2703         soc_genreg,
   2704         1,
   2705         0,
   2706         0xf6,
   2707         0,
   2708         0,
   2709         4,
   2710         soc_QRH_FE_GLOBAL_FE_DEST_IDS_1r_fields,
   2711         SOC_RESET_VAL_DEC(0x007f97f8, 0x00000000)
   2712         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   2713         -1,
   2714         -1,
   2715     },
   2716 #endif /* chips */
   2717 
   2718 #if defined(BCM_88790_A0)
   2719     { /* SOC_REG_INT_QRH_FE_GLOBAL_FE_DEST_IDS_2r */
   2720         soc_block_list[107],
   2721         soc_genreg,
   2722         1,
   2723         0,
   2724         0xf7,
   2725         0,
   2726         0,
   2727         4,
   2728         soc_QRH_FE_GLOBAL_FE_DEST_IDS_2r_fields,
   2729         SOC_RESET_VAL_DEC(0x007fb7fa, 0x00000000)
   2730         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   2731         -1,
   2732         -1,
   2733     },
   2734 #endif /* chips */
   2735 
   2736 #if defined(BCM_88790_A0)
   2737     { /* SOC_REG_INT_QRH_FE_GLOBAL_FE_DEST_IDS_3r */
   2738         soc_block_list[107],
   2739         soc_genreg,
   2740         1,
   2741         0,
   2742         0xf8,
   2743         0,
   2744         0,
   2745         4,
   2746         soc_QRH_FE_GLOBAL_FE_DEST_IDS_3r_fields,
   2747         SOC_RESET_VAL_DEC(0x007fd7fc, 0x00000000)
   2748         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   2749         -1,
   2750         -1,
   2751     },
   2752 #endif /* chips */
   2753 
   2754 #if defined(BCM_88790_A0)
   2755     { /* SOC_REG_INT_QRH_FE_GLOBAL_FE_DEST_IDS_4r */
   2756         soc_block_list[107],
   2757         soc_genreg,
   2758         1,
   2759         0,
   2760         0xf9,
   2761         0,
   2762         0,
   2763         4,
   2764         soc_QRH_FE_GLOBAL_FE_DEST_IDS_4r_fields,
   2765         SOC_RESET_VAL_DEC(0x007ff7fe, 0x00000000)
   2766         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   2767         -1,
   2768         -1,
   2769     },
   2770 #endif /* chips */
   2771 
   2772 #if defined(BCM_88790_A0)
   2773     { /* SOC_REG_INT_QRH_FE_GLOBAL_GENERAL_CFG_1r */
   2774         soc_block_list[107],
   2775         soc_genreg,
   2776         1,
   2777         0,
   2778         0xf4,
   2779         0,
   2780         0,
   2781         4,
   2782         soc_QRH_FE_GLOBAL_GENERAL_CFG_1r_fields,
   2783         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
   2784         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   2785         -1,
   2786         -1,
   2787     },
   2788 #endif /* chips */
   2789 
   2790 #if defined(BCM_88790_A0)
   2791     { /* SOC_REG_INT_QRH_FE_GROUP_DEST_IDr */
   2792         soc_block_list[107],
   2793         soc_genreg,
   2794         8,
   2795         0,
   2796         0x147,
   2797         SOC_REG_FLAG_ARRAY |
   2798                           SOC_REG_FLAG_REG_ARRAY,
   2799         0,
   2800         2,
   2801         soc_QRH_FE_GROUP_DEST_IDr_fields,
   2802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2803         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   2804         -1,
   2805         -1,
   2806     },
   2807 #endif /* chips */
   2808 
   2809 #if defined(BCM_88790_A0)
   2810     { /* SOC_REG_INT_QRH_GLOBAL_MEM_OPTIONSr */
   2811         soc_block_list[107],
   2812         soc_genreg,
   2813         1,
   2814         0,
   2815         0xc2,
   2816         0,
   2817         0,
   2818         6,
   2819         soc_QRH_GLOBAL_MEM_OPTIONSr_fields,
   2820         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   2821         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2822         -1,
   2823         -1,
   2824     },
   2825 #endif /* chips */
   2826 
   2827 #if defined(BCM_88790_A0)
   2828     { /* SOC_REG_INT_QRH_GTIMER_CONFIGURATIONr */
   2829         soc_block_list[107],
   2830         soc_genreg,
   2831         1,
   2832         0,
   2833         0x89,
   2834         0,
   2835         0,
   2836         3,
   2837         soc_QRH_GTIMER_CONFIGURATIONr_fields,
   2838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2839         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   2840         -1,
   2841         -1,
   2842     },
   2843 #endif /* chips */
   2844 
   2845 #if defined(BCM_88790_A0)
   2846     { /* SOC_REG_INT_QRH_GTIMER_CYCLEr */
   2847         soc_block_list[107],
   2848         soc_genreg,
   2849         1,
   2850         0,
   2851         0x88,
   2852         0,
   2853         0,
   2854         1,
   2855         soc_QRH_GTIMER_CYCLEr_fields,
   2856         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   2857         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2858         -1,
   2859         -1,
   2860     },
   2861 #endif /* chips */
   2862 
   2863 #if defined(BCM_88790_A0)
   2864     { /* SOC_REG_INT_QRH_INDIRECT_COMMANDr */
   2865         soc_block_list[107],
   2866         soc_genreg,
   2867         1,
   2868         0,
   2869         0x80,
   2870         0,
   2871         0,
   2872         5,
   2873         soc_QRH_INDIRECT_COMMANDr_fields,
   2874         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
   2875         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2876         -1,
   2877         -1,
   2878     },
   2879 #endif /* chips */
   2880 
   2881 #if defined(BCM_88790_A0)
   2882     { /* SOC_REG_INT_QRH_INDIRECT_COMMAND_ADDRESSr */
   2883         soc_block_list[107],
   2884         soc_genreg,
   2885         1,
   2886         0,
   2887         0x81,
   2888         0,
   2889         0,
   2890         2,
   2891         soc_QRH_INDIRECT_COMMAND_ADDRESSr_fields,
   2892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2893         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2894         -1,
   2895         -1,
   2896     },
   2897 #endif /* chips */
   2898 
   2899 #if defined(BCM_88790_A0)
   2900     { /* SOC_REG_INT_QRH_INDIRECT_COMMAND_DATA_INCREMENTr */
   2901         soc_block_list[107],
   2902         soc_genreg,
   2903         1,
   2904         0,
   2905         0x82,
   2906         SOC_REG_FLAG_64_BITS,
   2907         0,
   2908         1,
   2909         soc_QRH_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
   2910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2911         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   2912         -1,
   2913         -1,
   2914     },
   2915 #endif /* chips */
   2916 
   2917 #if defined(BCM_88790_A0)
   2918     { /* SOC_REG_INT_QRH_INDIRECT_COMMAND_RD_DATAr */
   2919         soc_block_list[107],
   2920         soc_genreg,
   2921         1,
   2922         0,
   2923         0x60,
   2924         SOC_REG_FLAG_ABOVE_64_BITS |
   2925                           SOC_REG_FLAG_RO |
   2926                           SOC_REG_FLAG_SIGNAL,
   2927         0,
   2928         1,
   2929         soc_QRH_INDIRECT_COMMAND_RD_DATAr_fields,
   2930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2931         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2932         -1,
   2933         -1,
   2934     },
   2935 #endif /* chips */
   2936 
   2937 #if defined(BCM_88790_A0)
   2938     { /* SOC_REG_INT_QRH_INDIRECT_COMMAND_WIDE_MEMr */
   2939         soc_block_list[107],
   2940         soc_genreg,
   2941         1,
   2942         0,
   2943         0x41,
   2944         0,
   2945         0,
   2946         1,
   2947         soc_QRH_INDIRECT_COMMAND_WIDE_MEMr_fields,
   2948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2949         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2950         -1,
   2951         -1,
   2952     },
   2953 #endif /* chips */
   2954 
   2955 #if defined(BCM_88790_A0)
   2956     { /* SOC_REG_INT_QRH_INDIRECT_COMMAND_WR_DATAr */
   2957         soc_block_list[107],
   2958         soc_genreg,
   2959         1,
   2960         0,
   2961         0x20,
   2962         SOC_REG_FLAG_ABOVE_64_BITS,
   2963         0,
   2964         1,
   2965         soc_QRH_INDIRECT_COMMAND_WR_DATAr_fields,
   2966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2967         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   2968         -1,
   2969         -1,
   2970     },
   2971 #endif /* chips */
   2972 
   2973 #if defined(BCM_88790_A0)
   2974     { /* SOC_REG_INT_QRH_INDIRECT_FORCE_BUBBLEr */
   2975         soc_block_list[107],
   2976         soc_genreg,
   2977         1,
   2978         0,
   2979         0x83,
   2980         0,
   2981         0,
   2982         4,
   2983         soc_QRH_INDIRECT_FORCE_BUBBLEr_fields,
   2984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2985         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   2986         -1,
   2987         -1,
   2988     },
   2989 #endif /* chips */
   2990 
   2991 #if defined(BCM_88790_A0)
   2992     { /* SOC_REG_INT_QRH_INTERRUPT_MASK_REGISTERr */
   2993         soc_block_list[107],
   2994         soc_genreg,
   2995         1,
   2996         0,
   2997         0x10,
   2998         0,
   2999         0,
   3000         3,
   3001         soc_QRH_INTERRUPT_MASK_REGISTERr_fields,
   3002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3003         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3004         -1,
   3005         -1,
   3006     },
   3007 #endif /* chips */
   3008 
   3009 #if defined(BCM_88790_A0)
   3010     { /* SOC_REG_INT_QRH_INTERRUPT_REGISTERr */
   3011         soc_block_list[107],
   3012         soc_genreg,
   3013         1,
   3014         0,
   3015         0,
   3016         SOC_REG_FLAG_RO |
   3017                           SOC_REG_FLAG_INTERRUPT |
   3018                           SOC_REG_FLAG_SIGNAL,
   3019         0,
   3020         3,
   3021         soc_QRH_INTERRUPT_REGISTERr_fields,
   3022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3023         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3024         -1,
   3025         -1,
   3026     },
   3027 #endif /* chips */
   3028 
   3029 #if defined(BCM_88790_A0)
   3030     { /* SOC_REG_INT_QRH_INTERRUPT_REGISTER_TESTr */
   3031         soc_block_list[107],
   3032         soc_genreg,
   3033         1,
   3034         0,
   3035         0x18,
   3036         0,
   3037         0,
   3038         1,
   3039         soc_QRH_INTERRUPT_REGISTER_TESTr_fields,
   3040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3041         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3042         -1,
   3043         -1,
   3044     },
   3045 #endif /* chips */
   3046 
   3047 #if defined(BCM_88790_A0)
   3048     { /* SOC_REG_INT_QRH_LCM_FC_CONFIGr */
   3049         soc_block_list[107],
   3050         soc_genreg,
   3051         1,
   3052         0,
   3053         0x14f,
   3054         0,
   3055         0,
   3056         1,
   3057         soc_QRH_LCM_FC_CONFIGr_fields,
   3058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3059         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   3060         -1,
   3061         -1,
   3062     },
   3063 #endif /* chips */
   3064 
   3065 #if defined(BCM_88790_A0)
   3066     { /* SOC_REG_INT_QRH_LOAD_BALANCE_MAX_DEBUG_LINK_Pr */
   3067         soc_block_list[107],
   3068         soc_genreg,
   3069         3,
   3070         0,
   3071         0x157,
   3072         SOC_REG_FLAG_ARRAY |
   3073                           SOC_REG_FLAG_REG_ARRAY,
   3074         0,
   3075         2,
   3076         soc_QRH_LOAD_BALANCE_MAX_DEBUG_LINK_Pr_fields,
   3077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3078         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   3079         -1,
   3080         -1,
   3081     },
   3082 #endif /* chips */
   3083 
   3084 #if defined(BCM_88790_A0)
   3085     { /* SOC_REG_INT_QRH_LOAD_BALANCE_MAX_LEVEL_Pr */
   3086         soc_block_list[107],
   3087         soc_genreg,
   3088         3,
   3089         0,
   3090         0x154,
   3091         SOC_REG_FLAG_ARRAY |
   3092                           SOC_REG_FLAG_RO |
   3093                           SOC_REG_FLAG_REG_ARRAY,
   3094         0,
   3095         2,
   3096         soc_QRH_LOAD_BALANCE_MAX_LEVEL_Pr_fields,
   3097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3098         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   3099         -1,
   3100         -1,
   3101     },
   3102 #endif /* chips */
   3103 
   3104 #if defined(BCM_88790_A0)
   3105     { /* SOC_REG_INT_QRH_LOCAL_ROUTE_CONFIGURATIONSr */
   3106         soc_block_list[107],
   3107         soc_genreg,
   3108         1,
   3109         0,
   3110         0x13d,
   3111         0,
   3112         0,
   3113         5,
   3114         soc_QRH_LOCAL_ROUTE_CONFIGURATIONSr_fields,
   3115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3116         SOC_RESET_MASK_DEC(0x000003f6, 0x00000000)
   3117         -1,
   3118         -1,
   3119     },
   3120 #endif /* chips */
   3121 
   3122 #if defined(BCM_88790_A0)
   3123     { /* SOC_REG_INT_QRH_LOW_PR_MULTHr */
   3124         soc_block_list[107],
   3125         soc_genreg,
   3126         1,
   3127         0,
   3128         0x123,
   3129         SOC_REG_FLAG_64_BITS,
   3130         0,
   3131         3,
   3132         soc_QRH_LOW_PR_MULTHr_fields,
   3133         SOC_RESET_VAL_DEC(0x08000200, 0x00000000)
   3134         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
   3135         -1,
   3136         -1,
   3137     },
   3138 #endif /* chips */
   3139 
   3140 #if defined(BCM_88790_A0)
   3141     { /* SOC_REG_INT_QRH_LOW_PR_MUL_CTRLr */
   3142         soc_block_list[107],
   3143         soc_genreg,
   3144         1,
   3145         0,
   3146         0x122,
   3147         0,
   3148         0,
   3149         7,
   3150         soc_QRH_LOW_PR_MUL_CTRLr_fields,
   3151         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
   3152         SOC_RESET_MASK_DEC(0x0ffffff7, 0x00000000)
   3153         -1,
   3154         -1,
   3155     },
   3156 #endif /* chips */
   3157 
   3158 #if defined(BCM_88790_A0)
   3159     { /* SOC_REG_INT_QRH_MASK_FC_AGING_PERIODr */
   3160         soc_block_list[107],
   3161         soc_genreg,
   3162         1,
   3163         0,
   3164         0x150,
   3165         0,
   3166         0,
   3167         1,
   3168         soc_QRH_MASK_FC_AGING_PERIODr_fields,
   3169         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3170         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3171         -1,
   3172         -1,
   3173     },
   3174 #endif /* chips */
   3175 
   3176 #if defined(BCM_88790_A0)
   3177     { /* SOC_REG_INT_QRH_MULICAST_ALLOWED_LINKS_REGISTERr */
   3178         soc_block_list[107],
   3179         soc_genreg,
   3180         1,
   3181         0,
   3182         0x11b,
   3183         SOC_REG_FLAG_ABOVE_64_BITS,
   3184         0,
   3185         1,
   3186         soc_QRH_MULICAST_ALLOWED_LINKS_REGISTERr_fields,
   3187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3188         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3189         -1,
   3190         -1,
   3191     },
   3192 #endif /* chips */
   3193 
   3194 #if defined(BCM_88790_A0)
   3195     { /* SOC_REG_INT_QRH_MULTICAST_MODE_SELECTIONr */
   3196         soc_block_list[107],
   3197         soc_genreg,
   3198         1,
   3199         0,
   3200         0x108,
   3201         0,
   3202         0,
   3203         4,
   3204         soc_QRH_MULTICAST_MODE_SELECTIONr_fields,
   3205         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
   3206         SOC_RESET_MASK_DEC(0x001fff01, 0x00000000)
   3207         -1,
   3208         -1,
   3209     },
   3210 #endif /* chips */
   3211 
   3212 #if defined(BCM_88790_A0)
   3213     { /* SOC_REG_INT_QRH_PIPES_WEIGHTS_COUNTER_0r */
   3214         soc_block_list[107],
   3215         soc_genreg,
   3216         1,
   3217         0,
   3218         0x143,
   3219         SOC_REG_FLAG_RO,
   3220         0,
   3221         1,
   3222         soc_QRH_PIPES_WEIGHTS_COUNTER_0r_fields,
   3223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3224         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   3225         -1,
   3226         -1,
   3227     },
   3228 #endif /* chips */
   3229 
   3230 #if defined(BCM_88790_A0)
   3231     { /* SOC_REG_INT_QRH_PIPES_WEIGHTS_COUNTER_1r */
   3232         soc_block_list[107],
   3233         soc_genreg,
   3234         1,
   3235         0,
   3236         0x144,
   3237         SOC_REG_FLAG_RO,
   3238         0,
   3239         1,
   3240         soc_QRH_PIPES_WEIGHTS_COUNTER_1r_fields,
   3241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3242         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   3243         -1,
   3244         -1,
   3245     },
   3246 #endif /* chips */
   3247 
   3248 #if defined(BCM_88790_A0)
   3249     { /* SOC_REG_INT_QRH_PIPES_WEIGHTS_COUNTER_2r */
   3250         soc_block_list[107],
   3251         soc_genreg,
   3252         1,
   3253         0,
   3254         0x145,
   3255         SOC_REG_FLAG_RO,
   3256         0,
   3257         1,
   3258         soc_QRH_PIPES_WEIGHTS_COUNTER_2r_fields,
   3259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3260         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   3261         -1,
   3262         -1,
   3263     },
   3264 #endif /* chips */
   3265 
   3266 #if defined(BCM_88790_A0)
   3267     { /* SOC_REG_INT_QRH_REACHABILITY_MESSAGE_GENERATOR_CONFIGURATIONr */
   3268         soc_block_list[107],
   3269         soc_genreg,
   3270         1,
   3271         0,
   3272         0x106,
   3273         0,
   3274         0,
   3275         2,
   3276         soc_QRH_REACHABILITY_MESSAGE_GENERATOR_CONFIGURATIONr_fields,
   3277         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
   3278         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   3279         -1,
   3280         -1,
   3281     },
   3282 #endif /* chips */
   3283 
   3284 #if defined(BCM_88790_A0)
   3285     { /* SOC_REG_INT_QRH_RESERVED_MIRROR_ADDRr */
   3286         soc_block_list[107],
   3287         soc_genreg,
   3288         1,
   3289         0,
   3290         0x85,
   3291         0,
   3292         0,
   3293         2,
   3294         soc_QRH_RESERVED_MIRROR_ADDRr_fields,
   3295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3296         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   3297         -1,
   3298         -1,
   3299     },
   3300 #endif /* chips */
   3301 
   3302 #if defined(BCM_88790_A0)
   3303     { /* SOC_REG_INT_QRH_RESERVED_MTCDr */
   3304         soc_block_list[107],
   3305         soc_genreg,
   3306         1,
   3307         0,
   3308         0xae,
   3309         0,
   3310         0,
   3311         6,
   3312         soc_QRH_RESERVED_MTCDr_fields,
   3313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3314         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   3315         -1,
   3316         -1,
   3317     },
   3318 #endif /* chips */
   3319 
   3320 #if defined(BCM_88790_A0)
   3321     { /* SOC_REG_INT_QRH_RESERVED_MTCPr */
   3322         soc_block_list[107],
   3323         soc_genreg,
   3324         1,
   3325         0,
   3326         0xad,
   3327         SOC_REG_FLAG_64_BITS,
   3328         0,
   3329         17,
   3330         soc_QRH_RESERVED_MTCPr_fields,
   3331         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   3332         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   3333         -1,
   3334         -1,
   3335     },
   3336 #endif /* chips */
   3337 
   3338 #if defined(BCM_88790_A0)
   3339     { /* SOC_REG_INT_QRH_RESERVED_SPARE_0r */
   3340         soc_block_list[107],
   3341         soc_genreg,
   3342         1,
   3343         0,
   3344         0x90,
   3345         0,
   3346         0,
   3347         1,
   3348         soc_QRH_RESERVED_SPARE_0r_fields,
   3349         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3350         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3351         -1,
   3352         -1,
   3353     },
   3354 #endif /* chips */
   3355 
   3356 #if defined(BCM_88790_A0)
   3357     { /* SOC_REG_INT_QRH_RESERVED_SPARE_1r */
   3358         soc_block_list[107],
   3359         soc_genreg,
   3360         1,
   3361         0,
   3362         0x91,
   3363         0,
   3364         0,
   3365         1,
   3366         soc_QRH_RESERVED_SPARE_1r_fields,
   3367         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3368         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3369         -1,
   3370         -1,
   3371     },
   3372 #endif /* chips */
   3373 
   3374 #if defined(BCM_88790_A0)
   3375     { /* SOC_REG_INT_QRH_RESERVED_SPARE_2r */
   3376         soc_block_list[107],
   3377         soc_genreg,
   3378         1,
   3379         0,
   3380         0x92,
   3381         0,
   3382         0,
   3383         1,
   3384         soc_QRH_RESERVED_SPARE_2r_fields,
   3385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3386         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3387         -1,
   3388         -1,
   3389     },
   3390 #endif /* chips */
   3391 
   3392 #if defined(BCM_88790_A0)
   3393     { /* SOC_REG_INT_QRH_RESERVED_SPARE_3r */
   3394         soc_block_list[107],
   3395         soc_genreg,
   3396         1,
   3397         0,
   3398         0x93,
   3399         0,
   3400         0,
   3401         1,
   3402         soc_QRH_RESERVED_SPARE_3r_fields,
   3403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3404         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3405         -1,
   3406         -1,
   3407     },
   3408 #endif /* chips */
   3409 
   3410 #if defined(BCM_88790_A0)
   3411     { /* SOC_REG_INT_QRH_SBUS_BROADCAST_IDr */
   3412         soc_block_list[107],
   3413         soc_genreg,
   3414         1,
   3415         0,
   3416         0x86,
   3417         0,
   3418         0,
   3419         1,
   3420         soc_QRH_SBUS_BROADCAST_IDr_fields,
   3421         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
   3422         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   3423         -1,
   3424         -1,
   3425     },
   3426 #endif /* chips */
   3427 
   3428 #if defined(BCM_88790_A0)
   3429     { /* SOC_REG_INT_QRH_SBUS_LAST_IN_CHAINr */
   3430         soc_block_list[107],
   3431         soc_genreg,
   3432         1,
   3433         0,
   3434         0x87,
   3435         0,
   3436         0,
   3437         1,
   3438         soc_QRH_SBUS_LAST_IN_CHAINr_fields,
   3439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3440         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3441         -1,
   3442         -1,
   3443     },
   3444 #endif /* chips */
   3445 
   3446 #if defined(BCM_88790_A0)
   3447     { /* SOC_REG_INT_QRH_SIMPLE_RR_LINKS_CONFIGr */
   3448         soc_block_list[107],
   3449         soc_genreg,
   3450         1,
   3451         0,
   3452         0x137,
   3453         SOC_REG_FLAG_ABOVE_64_BITS,
   3454         0,
   3455         1,
   3456         soc_QRH_SIMPLE_RR_LINKS_CONFIGr_fields,
   3457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3458         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3459         -1,
   3460         -1,
   3461     },
   3462 #endif /* chips */
   3463 
   3464 #if defined(BCM_88675_A0)
   3465     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRLr */
   3466         soc_block_list[61],
   3467         soc_iprocreg,
   3468         1,
   3469         0,
   3470         0x18021018,
   3471         0,
   3472         0,
   3473         2,
   3474         soc_QSPI_BSPI_REGISTERS_B0_CTRLr_fields,
   3475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3476         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3477         -1,
   3478         -1,
   3479     },
   3480 #endif /* chips */
   3481 
   3482 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3483     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   3484     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   3485     defined(BCM_56260_B0)
   3486     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM53400_A0r */
   3487         soc_block_list[61],
   3488         soc_iprocreg,
   3489         1,
   3490         0,
   3491         0x18047018,
   3492         0,
   3493         0,
   3494         2,
   3495         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM53400_A0r_fields,
   3496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3498         -1,
   3499         -1,
   3500     },
   3501 #endif /* chips */
   3502 
   3503 #if defined(BCM_56370_A0)
   3504     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM56370_A0r */
   3505         soc_block_list[61],
   3506         soc_iprocreg,
   3507         1,
   3508         0,
   3509         0x15000018,
   3510         0,
   3511         0,
   3512         2,
   3513         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM53400_A0r_fields,
   3514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3516         -1,
   3517         -1,
   3518         3,
   3519     },
   3520 #endif /* chips */
   3521 
   3522 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   3523     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3524     defined(BCM_56450_B1)
   3525     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM56450_A0r */
   3526         soc_block_list[61],
   3527         soc_iprocreg,
   3528         1,
   3529         0,
   3530         0x18027018,
   3531         0,
   3532         0,
   3533         2,
   3534         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM56450_A0r_fields,
   3535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3536         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3537         -1,
   3538         -1,
   3539     },
   3540 #endif /* chips */
   3541 
   3542 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   3543     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   3544     defined(BCM_56670_B0)
   3545     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM56560_A0r */
   3546         soc_block_list[61],
   3547         soc_iprocreg,
   3548         1,
   3549         0,
   3550         0x18021018,
   3551         0,
   3552         0,
   3553         2,
   3554         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM53400_A0r_fields,
   3555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3556         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3557         -1,
   3558         -1,
   3559     },
   3560 #endif /* chips */
   3561 
   3562 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3563     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   3564     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   3565     defined(BCM_56980_B0)
   3566     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM56960_A0r */
   3567         soc_block_list[61],
   3568         soc_iprocreg,
   3569         1,
   3570         0,
   3571         0x18021018,
   3572         0,
   3573         0,
   3574         2,
   3575         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM53400_A0r_fields,
   3576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3577         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3578         -1,
   3579         -1,
   3580         3,
   3581     },
   3582 #endif /* chips */
   3583 
   3584 #if defined(BCM_88270_A0)
   3585     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88270_A0r */
   3586         soc_block_list[61],
   3587         soc_iprocreg,
   3588         1,
   3589         0,
   3590         0x18021018,
   3591         0,
   3592         0,
   3593         2,
   3594         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88270_A0r_fields,
   3595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3596         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3597         -1,
   3598         -1,
   3599     },
   3600 #endif /* chips */
   3601 
   3602 #if defined(BCM_88375_A0)
   3603     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88375_A0r */
   3604         soc_block_list[61],
   3605         soc_iprocreg,
   3606         1,
   3607         0,
   3608         0x18021018,
   3609         0,
   3610         0,
   3611         2,
   3612         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88375_A0r_fields,
   3613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3614         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3615         -1,
   3616         -1,
   3617     },
   3618 #endif /* chips */
   3619 
   3620 #if defined(BCM_88375_B0)
   3621     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88375_B0r */
   3622         soc_block_list[61],
   3623         soc_iprocreg,
   3624         1,
   3625         0,
   3626         0x18021018,
   3627         0,
   3628         0,
   3629         2,
   3630         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88375_B0r_fields,
   3631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3632         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3633         -1,
   3634         -1,
   3635     },
   3636 #endif /* chips */
   3637 
   3638 #if defined(BCM_88470_A0)
   3639     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88470_A0r */
   3640         soc_block_list[61],
   3641         soc_iprocreg,
   3642         1,
   3643         0,
   3644         0x18021018,
   3645         0,
   3646         0,
   3647         2,
   3648         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88470_A0r_fields,
   3649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3651         -1,
   3652         -1,
   3653     },
   3654 #endif /* chips */
   3655 
   3656 #if defined(BCM_88470_B0)
   3657     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88470_B0r */
   3658         soc_block_list[61],
   3659         soc_iprocreg,
   3660         1,
   3661         0,
   3662         0x18021018,
   3663         0,
   3664         0,
   3665         2,
   3666         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88470_B0r_fields,
   3667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3668         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3669         -1,
   3670         -1,
   3671     },
   3672 #endif /* chips */
   3673 
   3674 #if defined(BCM_88675_B0)
   3675     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88675_B0r */
   3676         soc_block_list[61],
   3677         soc_iprocreg,
   3678         1,
   3679         0,
   3680         0x18021018,
   3681         0,
   3682         0,
   3683         2,
   3684         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88675_B0r_fields,
   3685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3686         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3687         -1,
   3688         -1,
   3689     },
   3690 #endif /* chips */
   3691 
   3692 #if defined(BCM_88680_A0)
   3693     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88680_A0r */
   3694         soc_block_list[61],
   3695         soc_iprocreg,
   3696         1,
   3697         0,
   3698         0x18021018,
   3699         0,
   3700         0,
   3701         2,
   3702         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88680_A0r_fields,
   3703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3704         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3705         -1,
   3706         -1,
   3707     },
   3708 #endif /* chips */
   3709 
   3710 #if defined(BCM_88690_A0)
   3711     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88690_A0r */
   3712         soc_block_list[61],
   3713         soc_iprocreg,
   3714         1,
   3715         0,
   3716         0x18021018,
   3717         0,
   3718         0,
   3719         2,
   3720         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88690_A0r_fields,
   3721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3722         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3723         -1,
   3724         -1,
   3725     },
   3726 #endif /* chips */
   3727 
   3728 #if defined(BCM_88690_B0)
   3729     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88690_B0r */
   3730         soc_block_list[61],
   3731         soc_iprocreg,
   3732         1,
   3733         0,
   3734         0x18021018,
   3735         0,
   3736         0,
   3737         2,
   3738         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88690_B0r_fields,
   3739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3740         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3741         -1,
   3742         -1,
   3743     },
   3744 #endif /* chips */
   3745 
   3746 #if defined(BCM_88790_A0)
   3747     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88790_A0r */
   3748         soc_block_list[61],
   3749         soc_iprocreg,
   3750         1,
   3751         0,
   3752         0x18021018,
   3753         0,
   3754         0,
   3755         2,
   3756         soc_QSPI_BSPI_REGISTERS_B0_CTRL_BCM88790_A0r_fields,
   3757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3758         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3759         -1,
   3760         -1,
   3761     },
   3762 #endif /* chips */
   3763 
   3764 #if defined(BCM_88675_A0)
   3765     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUSr */
   3766         soc_block_list[61],
   3767         soc_iprocreg,
   3768         1,
   3769         0,
   3770         0x18021014,
   3771         SOC_REG_FLAG_RO,
   3772         0,
   3773         7,
   3774         soc_QSPI_BSPI_REGISTERS_B0_STATUSr_fields,
   3775         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3776         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3777         -1,
   3778         -1,
   3779     },
   3780 #endif /* chips */
   3781 
   3782 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3783     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   3784     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   3785     defined(BCM_56260_B0)
   3786     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM53400_A0r */
   3787         soc_block_list[61],
   3788         soc_iprocreg,
   3789         1,
   3790         0,
   3791         0x18047014,
   3792         SOC_REG_FLAG_RO,
   3793         0,
   3794         7,
   3795         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM53400_A0r_fields,
   3796         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3797         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3798         -1,
   3799         -1,
   3800     },
   3801 #endif /* chips */
   3802 
   3803 #if defined(BCM_56370_A0)
   3804     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM56370_A0r */
   3805         soc_block_list[61],
   3806         soc_iprocreg,
   3807         1,
   3808         0,
   3809         0x15000014,
   3810         SOC_REG_FLAG_RO,
   3811         0,
   3812         7,
   3813         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM53400_A0r_fields,
   3814         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3815         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3816         -1,
   3817         -1,
   3818         3,
   3819     },
   3820 #endif /* chips */
   3821 
   3822 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   3823     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3824     defined(BCM_56450_B1)
   3825     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM56450_A0r */
   3826         soc_block_list[61],
   3827         soc_iprocreg,
   3828         1,
   3829         0,
   3830         0x18027014,
   3831         SOC_REG_FLAG_RO,
   3832         0,
   3833         7,
   3834         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM56450_A0r_fields,
   3835         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3837         -1,
   3838         -1,
   3839     },
   3840 #endif /* chips */
   3841 
   3842 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   3843     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   3844     defined(BCM_56670_B0)
   3845     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM56560_A0r */
   3846         soc_block_list[61],
   3847         soc_iprocreg,
   3848         1,
   3849         0,
   3850         0x18021014,
   3851         SOC_REG_FLAG_RO,
   3852         0,
   3853         7,
   3854         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM53400_A0r_fields,
   3855         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3856         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3857         -1,
   3858         -1,
   3859     },
   3860 #endif /* chips */
   3861 
   3862 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   3863     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   3864     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   3865     defined(BCM_56980_B0)
   3866     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM56960_A0r */
   3867         soc_block_list[61],
   3868         soc_iprocreg,
   3869         1,
   3870         0,
   3871         0x18021014,
   3872         SOC_REG_FLAG_RO,
   3873         0,
   3874         7,
   3875         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM53400_A0r_fields,
   3876         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3878         -1,
   3879         -1,
   3880         3,
   3881     },
   3882 #endif /* chips */
   3883 
   3884 #if defined(BCM_88270_A0)
   3885     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88270_A0r */
   3886         soc_block_list[61],
   3887         soc_iprocreg,
   3888         1,
   3889         0,
   3890         0x18021014,
   3891         SOC_REG_FLAG_RO,
   3892         0,
   3893         7,
   3894         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88270_A0r_fields,
   3895         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3896         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3897         -1,
   3898         -1,
   3899     },
   3900 #endif /* chips */
   3901 
   3902 #if defined(BCM_88375_A0)
   3903     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88375_A0r */
   3904         soc_block_list[61],
   3905         soc_iprocreg,
   3906         1,
   3907         0,
   3908         0x18021014,
   3909         SOC_REG_FLAG_RO,
   3910         0,
   3911         7,
   3912         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88375_A0r_fields,
   3913         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3914         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3915         -1,
   3916         -1,
   3917     },
   3918 #endif /* chips */
   3919 
   3920 #if defined(BCM_88375_B0)
   3921     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88375_B0r */
   3922         soc_block_list[61],
   3923         soc_iprocreg,
   3924         1,
   3925         0,
   3926         0x18021014,
   3927         SOC_REG_FLAG_RO,
   3928         0,
   3929         7,
   3930         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88375_B0r_fields,
   3931         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3932         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3933         -1,
   3934         -1,
   3935     },
   3936 #endif /* chips */
   3937 
   3938 #if defined(BCM_88470_A0)
   3939     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88470_A0r */
   3940         soc_block_list[61],
   3941         soc_iprocreg,
   3942         1,
   3943         0,
   3944         0x18021014,
   3945         SOC_REG_FLAG_RO,
   3946         0,
   3947         7,
   3948         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88470_A0r_fields,
   3949         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3950         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3951         -1,
   3952         -1,
   3953     },
   3954 #endif /* chips */
   3955 
   3956 #if defined(BCM_88470_B0)
   3957     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88470_B0r */
   3958         soc_block_list[61],
   3959         soc_iprocreg,
   3960         1,
   3961         0,
   3962         0x18021014,
   3963         SOC_REG_FLAG_RO,
   3964         0,
   3965         7,
   3966         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88470_B0r_fields,
   3967         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3968         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3969         -1,
   3970         -1,
   3971     },
   3972 #endif /* chips */
   3973 
   3974 #if defined(BCM_88675_B0)
   3975     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88675_B0r */
   3976         soc_block_list[61],
   3977         soc_iprocreg,
   3978         1,
   3979         0,
   3980         0x18021014,
   3981         SOC_REG_FLAG_RO,
   3982         0,
   3983         7,
   3984         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88675_B0r_fields,
   3985         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   3986         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3987         -1,
   3988         -1,
   3989     },
   3990 #endif /* chips */
   3991 
   3992 #if defined(BCM_88680_A0)
   3993     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88680_A0r */
   3994         soc_block_list[61],
   3995         soc_iprocreg,
   3996         1,
   3997         0,
   3998         0x18021014,
   3999         SOC_REG_FLAG_RO,
   4000         0,
   4001         7,
   4002         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88680_A0r_fields,
   4003         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4004         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4005         -1,
   4006         -1,
   4007     },
   4008 #endif /* chips */
   4009 
   4010 #if defined(BCM_88690_A0)
   4011     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88690_A0r */
   4012         soc_block_list[61],
   4013         soc_iprocreg,
   4014         1,
   4015         0,
   4016         0x18021014,
   4017         SOC_REG_FLAG_RO,
   4018         0,
   4019         7,
   4020         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88690_A0r_fields,
   4021         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4023         -1,
   4024         -1,
   4025     },
   4026 #endif /* chips */
   4027 
   4028 #if defined(BCM_88690_B0)
   4029     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88690_B0r */
   4030         soc_block_list[61],
   4031         soc_iprocreg,
   4032         1,
   4033         0,
   4034         0x18021014,
   4035         SOC_REG_FLAG_RO,
   4036         0,
   4037         7,
   4038         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88690_B0r_fields,
   4039         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4040         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4041         -1,
   4042         -1,
   4043     },
   4044 #endif /* chips */
   4045 
   4046 #if defined(BCM_88790_A0)
   4047     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88790_A0r */
   4048         soc_block_list[61],
   4049         soc_iprocreg,
   4050         1,
   4051         0,
   4052         0x18021014,
   4053         SOC_REG_FLAG_RO,
   4054         0,
   4055         7,
   4056         soc_QSPI_BSPI_REGISTERS_B0_STATUS_BCM88790_A0r_fields,
   4057         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4058         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4059         -1,
   4060         -1,
   4061     },
   4062 #endif /* chips */
   4063 
   4064 #if defined(BCM_88675_A0)
   4065     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRLr */
   4066         soc_block_list[61],
   4067         soc_iprocreg,
   4068         1,
   4069         0,
   4070         0x18021020,
   4071         0,
   4072         0,
   4073         2,
   4074         soc_QSPI_BSPI_REGISTERS_B1_CTRLr_fields,
   4075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4076         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4077         -1,
   4078         -1,
   4079     },
   4080 #endif /* chips */
   4081 
   4082 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   4083     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   4084     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   4085     defined(BCM_56260_B0)
   4086     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM53400_A0r */
   4087         soc_block_list[61],
   4088         soc_iprocreg,
   4089         1,
   4090         0,
   4091         0x18047020,
   4092         0,
   4093         0,
   4094         2,
   4095         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM53400_A0r_fields,
   4096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4098         -1,
   4099         -1,
   4100     },
   4101 #endif /* chips */
   4102 
   4103 #if defined(BCM_56370_A0)
   4104     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM56370_A0r */
   4105         soc_block_list[61],
   4106         soc_iprocreg,
   4107         1,
   4108         0,
   4109         0x15000020,
   4110         0,
   4111         0,
   4112         2,
   4113         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM53400_A0r_fields,
   4114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4116         -1,
   4117         -1,
   4118         3,
   4119     },
   4120 #endif /* chips */
   4121 
   4122 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   4123     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4124     defined(BCM_56450_B1)
   4125     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM56450_A0r */
   4126         soc_block_list[61],
   4127         soc_iprocreg,
   4128         1,
   4129         0,
   4130         0x18027020,
   4131         0,
   4132         0,
   4133         2,
   4134         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM56450_A0r_fields,
   4135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4136         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4137         -1,
   4138         -1,
   4139     },
   4140 #endif /* chips */
   4141 
   4142 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   4143     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   4144     defined(BCM_56670_B0)
   4145     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM56560_A0r */
   4146         soc_block_list[61],
   4147         soc_iprocreg,
   4148         1,
   4149         0,
   4150         0x18021020,
   4151         0,
   4152         0,
   4153         2,
   4154         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM53400_A0r_fields,
   4155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4157         -1,
   4158         -1,
   4159     },
   4160 #endif /* chips */
   4161 
   4162 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   4163     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   4164     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   4165     defined(BCM_56980_B0)
   4166     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM56960_A0r */
   4167         soc_block_list[61],
   4168         soc_iprocreg,
   4169         1,
   4170         0,
   4171         0x18021020,
   4172         0,
   4173         0,
   4174         2,
   4175         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM53400_A0r_fields,
   4176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4177         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4178         -1,
   4179         -1,
   4180         3,
   4181     },
   4182 #endif /* chips */
   4183 
   4184 #if defined(BCM_88270_A0)
   4185     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88270_A0r */
   4186         soc_block_list[61],
   4187         soc_iprocreg,
   4188         1,
   4189         0,
   4190         0x18021020,
   4191         0,
   4192         0,
   4193         2,
   4194         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88270_A0r_fields,
   4195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4196         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4197         -1,
   4198         -1,
   4199     },
   4200 #endif /* chips */
   4201 
   4202 #if defined(BCM_88375_A0)
   4203     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88375_A0r */
   4204         soc_block_list[61],
   4205         soc_iprocreg,
   4206         1,
   4207         0,
   4208         0x18021020,
   4209         0,
   4210         0,
   4211         2,
   4212         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88375_A0r_fields,
   4213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4214         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4215         -1,
   4216         -1,
   4217     },
   4218 #endif /* chips */
   4219 
   4220 #if defined(BCM_88375_B0)
   4221     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88375_B0r */
   4222         soc_block_list[61],
   4223         soc_iprocreg,
   4224         1,
   4225         0,
   4226         0x18021020,
   4227         0,
   4228         0,
   4229         2,
   4230         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88375_B0r_fields,
   4231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4232         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4233         -1,
   4234         -1,
   4235     },
   4236 #endif /* chips */
   4237 
   4238 #if defined(BCM_88470_A0)
   4239     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88470_A0r */
   4240         soc_block_list[61],
   4241         soc_iprocreg,
   4242         1,
   4243         0,
   4244         0x18021020,
   4245         0,
   4246         0,
   4247         2,
   4248         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88470_A0r_fields,
   4249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4250         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4251         -1,
   4252         -1,
   4253     },
   4254 #endif /* chips */
   4255 
   4256 #if defined(BCM_88470_B0)
   4257     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88470_B0r */
   4258         soc_block_list[61],
   4259         soc_iprocreg,
   4260         1,
   4261         0,
   4262         0x18021020,
   4263         0,
   4264         0,
   4265         2,
   4266         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88470_B0r_fields,
   4267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4268         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4269         -1,
   4270         -1,
   4271     },
   4272 #endif /* chips */
   4273 
   4274 #if defined(BCM_88675_B0)
   4275     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88675_B0r */
   4276         soc_block_list[61],
   4277         soc_iprocreg,
   4278         1,
   4279         0,
   4280         0x18021020,
   4281         0,
   4282         0,
   4283         2,
   4284         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88675_B0r_fields,
   4285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4286         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4287         -1,
   4288         -1,
   4289     },
   4290 #endif /* chips */
   4291 
   4292 #if defined(BCM_88680_A0)
   4293     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88680_A0r */
   4294         soc_block_list[61],
   4295         soc_iprocreg,
   4296         1,
   4297         0,
   4298         0x18021020,
   4299         0,
   4300         0,
   4301         2,
   4302         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88680_A0r_fields,
   4303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4304         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4305         -1,
   4306         -1,
   4307     },
   4308 #endif /* chips */
   4309 
   4310 #if defined(BCM_88690_A0)
   4311     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88690_A0r */
   4312         soc_block_list[61],
   4313         soc_iprocreg,
   4314         1,
   4315         0,
   4316         0x18021020,
   4317         0,
   4318         0,
   4319         2,
   4320         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88690_A0r_fields,
   4321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4322         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4323         -1,
   4324         -1,
   4325     },
   4326 #endif /* chips */
   4327 
   4328 #if defined(BCM_88690_B0)
   4329     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88690_B0r */
   4330         soc_block_list[61],
   4331         soc_iprocreg,
   4332         1,
   4333         0,
   4334         0x18021020,
   4335         0,
   4336         0,
   4337         2,
   4338         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88690_B0r_fields,
   4339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4340         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4341         -1,
   4342         -1,
   4343     },
   4344 #endif /* chips */
   4345 
   4346 #if defined(BCM_88790_A0)
   4347     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88790_A0r */
   4348         soc_block_list[61],
   4349         soc_iprocreg,
   4350         1,
   4351         0,
   4352         0x18021020,
   4353         0,
   4354         0,
   4355         2,
   4356         soc_QSPI_BSPI_REGISTERS_B1_CTRL_BCM88790_A0r_fields,
   4357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4358         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4359         -1,
   4360         -1,
   4361     },
   4362 #endif /* chips */
   4363 
   4364 #if defined(BCM_88675_A0)
   4365     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUSr */
   4366         soc_block_list[61],
   4367         soc_iprocreg,
   4368         1,
   4369         0,
   4370         0x1802101c,
   4371         SOC_REG_FLAG_RO,
   4372         0,
   4373         7,
   4374         soc_QSPI_BSPI_REGISTERS_B1_STATUSr_fields,
   4375         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4376         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4377         -1,
   4378         -1,
   4379     },
   4380 #endif /* chips */
   4381 
   4382 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   4383     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   4384     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   4385     defined(BCM_56260_B0)
   4386     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM53400_A0r */
   4387         soc_block_list[61],
   4388         soc_iprocreg,
   4389         1,
   4390         0,
   4391         0x1804701c,
   4392         SOC_REG_FLAG_RO,
   4393         0,
   4394         7,
   4395         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM53400_A0r_fields,
   4396         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4397         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4398         -1,
   4399         -1,
   4400     },
   4401 #endif /* chips */
   4402 
   4403 #if defined(BCM_56370_A0)
   4404     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM56370_A0r */
   4405         soc_block_list[61],
   4406         soc_iprocreg,
   4407         1,
   4408         0,
   4409         0x1500001c,
   4410         SOC_REG_FLAG_RO,
   4411         0,
   4412         7,
   4413         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM53400_A0r_fields,
   4414         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4416         -1,
   4417         -1,
   4418         3,
   4419     },
   4420 #endif /* chips */
   4421 
   4422 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   4423     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4424     defined(BCM_56450_B1)
   4425     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM56450_A0r */
   4426         soc_block_list[61],
   4427         soc_iprocreg,
   4428         1,
   4429         0,
   4430         0x1802701c,
   4431         SOC_REG_FLAG_RO,
   4432         0,
   4433         7,
   4434         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM56450_A0r_fields,
   4435         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4436         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4437         -1,
   4438         -1,
   4439     },
   4440 #endif /* chips */
   4441 
   4442 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   4443     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   4444     defined(BCM_56670_B0)
   4445     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM56560_A0r */
   4446         soc_block_list[61],
   4447         soc_iprocreg,
   4448         1,
   4449         0,
   4450         0x1802101c,
   4451         SOC_REG_FLAG_RO,
   4452         0,
   4453         7,
   4454         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM53400_A0r_fields,
   4455         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4456         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4457         -1,
   4458         -1,
   4459     },
   4460 #endif /* chips */
   4461 
   4462 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   4463     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   4464     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   4465     defined(BCM_56980_B0)
   4466     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM56960_A0r */
   4467         soc_block_list[61],
   4468         soc_iprocreg,
   4469         1,
   4470         0,
   4471         0x1802101c,
   4472         SOC_REG_FLAG_RO,
   4473         0,
   4474         7,
   4475         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM53400_A0r_fields,
   4476         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4477         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4478         -1,
   4479         -1,
   4480         3,
   4481     },
   4482 #endif /* chips */
   4483 
   4484 #if defined(BCM_88270_A0)
   4485     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88270_A0r */
   4486         soc_block_list[61],
   4487         soc_iprocreg,
   4488         1,
   4489         0,
   4490         0x1802101c,
   4491         SOC_REG_FLAG_RO,
   4492         0,
   4493         7,
   4494         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88270_A0r_fields,
   4495         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4496         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4497         -1,
   4498         -1,
   4499     },
   4500 #endif /* chips */
   4501 
   4502 #if defined(BCM_88375_A0)
   4503     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88375_A0r */
   4504         soc_block_list[61],
   4505         soc_iprocreg,
   4506         1,
   4507         0,
   4508         0x1802101c,
   4509         SOC_REG_FLAG_RO,
   4510         0,
   4511         7,
   4512         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88375_A0r_fields,
   4513         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4514         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4515         -1,
   4516         -1,
   4517     },
   4518 #endif /* chips */
   4519 
   4520 #if defined(BCM_88375_B0)
   4521     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88375_B0r */
   4522         soc_block_list[61],
   4523         soc_iprocreg,
   4524         1,
   4525         0,
   4526         0x1802101c,
   4527         SOC_REG_FLAG_RO,
   4528         0,
   4529         7,
   4530         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88375_B0r_fields,
   4531         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4532         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4533         -1,
   4534         -1,
   4535     },
   4536 #endif /* chips */
   4537 
   4538 #if defined(BCM_88470_A0)
   4539     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88470_A0r */
   4540         soc_block_list[61],
   4541         soc_iprocreg,
   4542         1,
   4543         0,
   4544         0x1802101c,
   4545         SOC_REG_FLAG_RO,
   4546         0,
   4547         7,
   4548         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88470_A0r_fields,
   4549         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4550         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4551         -1,
   4552         -1,
   4553     },
   4554 #endif /* chips */
   4555 
   4556 #if defined(BCM_88470_B0)
   4557     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88470_B0r */
   4558         soc_block_list[61],
   4559         soc_iprocreg,
   4560         1,
   4561         0,
   4562         0x1802101c,
   4563         SOC_REG_FLAG_RO,
   4564         0,
   4565         7,
   4566         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88470_B0r_fields,
   4567         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4568         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4569         -1,
   4570         -1,
   4571     },
   4572 #endif /* chips */
   4573 
   4574 #if defined(BCM_88675_B0)
   4575     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88675_B0r */
   4576         soc_block_list[61],
   4577         soc_iprocreg,
   4578         1,
   4579         0,
   4580         0x1802101c,
   4581         SOC_REG_FLAG_RO,
   4582         0,
   4583         7,
   4584         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88675_B0r_fields,
   4585         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4586         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4587         -1,
   4588         -1,
   4589     },
   4590 #endif /* chips */
   4591 
   4592 #if defined(BCM_88680_A0)
   4593     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88680_A0r */
   4594         soc_block_list[61],
   4595         soc_iprocreg,
   4596         1,
   4597         0,
   4598         0x1802101c,
   4599         SOC_REG_FLAG_RO,
   4600         0,
   4601         7,
   4602         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88680_A0r_fields,
   4603         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4604         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4605         -1,
   4606         -1,
   4607     },
   4608 #endif /* chips */
   4609 
   4610 #if defined(BCM_88690_A0)
   4611     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88690_A0r */
   4612         soc_block_list[61],
   4613         soc_iprocreg,
   4614         1,
   4615         0,
   4616         0x1802101c,
   4617         SOC_REG_FLAG_RO,
   4618         0,
   4619         7,
   4620         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88690_A0r_fields,
   4621         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4622         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4623         -1,
   4624         -1,
   4625     },
   4626 #endif /* chips */
   4627 
   4628 #if defined(BCM_88690_B0)
   4629     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88690_B0r */
   4630         soc_block_list[61],
   4631         soc_iprocreg,
   4632         1,
   4633         0,
   4634         0x1802101c,
   4635         SOC_REG_FLAG_RO,
   4636         0,
   4637         7,
   4638         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88690_B0r_fields,
   4639         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4640         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4641         -1,
   4642         -1,
   4643     },
   4644 #endif /* chips */
   4645 
   4646 #if defined(BCM_88790_A0)
   4647     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88790_A0r */
   4648         soc_block_list[61],
   4649         soc_iprocreg,
   4650         1,
   4651         0,
   4652         0x1802101c,
   4653         SOC_REG_FLAG_RO,
   4654         0,
   4655         7,
   4656         soc_QSPI_BSPI_REGISTERS_B1_STATUS_BCM88790_A0r_fields,
   4657         SOC_RESET_VAL_DEC(0x10000000, 0x00000000)
   4658         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4659         -1,
   4660         -1,
   4661     },
   4662 #endif /* chips */
   4663 
   4664 #if defined(BCM_88675_A0)
   4665     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLEr */
   4666         soc_block_list[61],
   4667         soc_iprocreg,
   4668         1,
   4669         0,
   4670         0x1802102c,
   4671         0,
   4672         0,
   4673         5,
   4674         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLEr_fields,
   4675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4676         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4677         -1,
   4678         -1,
   4679     },
   4680 #endif /* chips */
   4681 
   4682 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   4683     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   4684     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   4685     defined(BCM_56260_B0)
   4686     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM53400_A0r */
   4687         soc_block_list[61],
   4688         soc_iprocreg,
   4689         1,
   4690         0,
   4691         0x1804702c,
   4692         0,
   4693         0,
   4694         5,
   4695         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM53400_A0r_fields,
   4696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4697         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4698         -1,
   4699         -1,
   4700     },
   4701 #endif /* chips */
   4702 
   4703 #if defined(BCM_56370_A0)
   4704     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM56370_A0r */
   4705         soc_block_list[61],
   4706         soc_iprocreg,
   4707         1,
   4708         0,
   4709         0x1500002c,
   4710         0,
   4711         0,
   4712         5,
   4713         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM53400_A0r_fields,
   4714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4715         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4716         -1,
   4717         -1,
   4718         3,
   4719     },
   4720 #endif /* chips */
   4721 
   4722 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   4723     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4724     defined(BCM_56450_B1)
   4725     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM56450_A0r */
   4726         soc_block_list[61],
   4727         soc_iprocreg,
   4728         1,
   4729         0,
   4730         0x1802702c,
   4731         0,
   4732         0,
   4733         5,
   4734         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM56450_A0r_fields,
   4735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4736         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4737         -1,
   4738         -1,
   4739     },
   4740 #endif /* chips */
   4741 
   4742 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   4743     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   4744     defined(BCM_56670_B0)
   4745     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM56560_A0r */
   4746         soc_block_list[61],
   4747         soc_iprocreg,
   4748         1,
   4749         0,
   4750         0x1802102c,
   4751         0,
   4752         0,
   4753         5,
   4754         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM53400_A0r_fields,
   4755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4756         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4757         -1,
   4758         -1,
   4759     },
   4760 #endif /* chips */
   4761 
   4762 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   4763     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   4764     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   4765     defined(BCM_56980_B0)
   4766     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM56960_A0r */
   4767         soc_block_list[61],
   4768         soc_iprocreg,
   4769         1,
   4770         0,
   4771         0x1802102c,
   4772         0,
   4773         0,
   4774         5,
   4775         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM53400_A0r_fields,
   4776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4777         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4778         -1,
   4779         -1,
   4780         3,
   4781     },
   4782 #endif /* chips */
   4783 
   4784 #if defined(BCM_88270_A0)
   4785     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88270_A0r */
   4786         soc_block_list[61],
   4787         soc_iprocreg,
   4788         1,
   4789         0,
   4790         0x1802102c,
   4791         0,
   4792         0,
   4793         5,
   4794         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88270_A0r_fields,
   4795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4796         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4797         -1,
   4798         -1,
   4799     },
   4800 #endif /* chips */
   4801 
   4802 #if defined(BCM_88375_A0)
   4803     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88375_A0r */
   4804         soc_block_list[61],
   4805         soc_iprocreg,
   4806         1,
   4807         0,
   4808         0x1802102c,
   4809         0,
   4810         0,
   4811         5,
   4812         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88375_A0r_fields,
   4813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4814         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4815         -1,
   4816         -1,
   4817     },
   4818 #endif /* chips */
   4819 
   4820 #if defined(BCM_88375_B0)
   4821     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88375_B0r */
   4822         soc_block_list[61],
   4823         soc_iprocreg,
   4824         1,
   4825         0,
   4826         0x1802102c,
   4827         0,
   4828         0,
   4829         5,
   4830         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88375_B0r_fields,
   4831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4832         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4833         -1,
   4834         -1,
   4835     },
   4836 #endif /* chips */
   4837 
   4838 #if defined(BCM_88470_A0)
   4839     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88470_A0r */
   4840         soc_block_list[61],
   4841         soc_iprocreg,
   4842         1,
   4843         0,
   4844         0x1802102c,
   4845         0,
   4846         0,
   4847         5,
   4848         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88470_A0r_fields,
   4849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4850         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4851         -1,
   4852         -1,
   4853     },
   4854 #endif /* chips */
   4855 
   4856 #if defined(BCM_88470_B0)
   4857     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88470_B0r */
   4858         soc_block_list[61],
   4859         soc_iprocreg,
   4860         1,
   4861         0,
   4862         0x1802102c,
   4863         0,
   4864         0,
   4865         5,
   4866         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88470_B0r_fields,
   4867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4868         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4869         -1,
   4870         -1,
   4871     },
   4872 #endif /* chips */
   4873 
   4874 #if defined(BCM_88675_B0)
   4875     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88675_B0r */
   4876         soc_block_list[61],
   4877         soc_iprocreg,
   4878         1,
   4879         0,
   4880         0x1802102c,
   4881         0,
   4882         0,
   4883         5,
   4884         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88675_B0r_fields,
   4885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4886         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4887         -1,
   4888         -1,
   4889     },
   4890 #endif /* chips */
   4891 
   4892 #if defined(BCM_88680_A0)
   4893     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88680_A0r */
   4894         soc_block_list[61],
   4895         soc_iprocreg,
   4896         1,
   4897         0,
   4898         0x1802102c,
   4899         0,
   4900         0,
   4901         5,
   4902         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88680_A0r_fields,
   4903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4904         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4905         -1,
   4906         -1,
   4907     },
   4908 #endif /* chips */
   4909 
   4910 #if defined(BCM_88690_A0)
   4911     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88690_A0r */
   4912         soc_block_list[61],
   4913         soc_iprocreg,
   4914         1,
   4915         0,
   4916         0x1802102c,
   4917         0,
   4918         0,
   4919         5,
   4920         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88690_A0r_fields,
   4921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4922         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4923         -1,
   4924         -1,
   4925     },
   4926 #endif /* chips */
   4927 
   4928 #if defined(BCM_88690_B0)
   4929     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88690_B0r */
   4930         soc_block_list[61],
   4931         soc_iprocreg,
   4932         1,
   4933         0,
   4934         0x1802102c,
   4935         0,
   4936         0,
   4937         5,
   4938         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88690_B0r_fields,
   4939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4940         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4941         -1,
   4942         -1,
   4943     },
   4944 #endif /* chips */
   4945 
   4946 #if defined(BCM_88790_A0)
   4947     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88790_A0r */
   4948         soc_block_list[61],
   4949         soc_iprocreg,
   4950         1,
   4951         0,
   4952         0x1802102c,
   4953         0,
   4954         0,
   4955         5,
   4956         soc_QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BCM88790_A0r_fields,
   4957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4958         SOC_RESET_MASK_DEC(0x030303ff, 0x00000000)
   4959         -1,
   4960         -1,
   4961     },
   4962 #endif /* chips */
   4963 
   4964 #if defined(BCM_88675_A0)
   4965     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASEr */
   4966         soc_block_list[61],
   4967         soc_iprocreg,
   4968         1,
   4969         0,
   4970         0x18021030,
   4971         0,
   4972         0,
   4973         5,
   4974         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASEr_fields,
   4975         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   4976         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   4977         -1,
   4978         -1,
   4979     },
   4980 #endif /* chips */
   4981 
   4982 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   4983     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   4984     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   4985     defined(BCM_56260_B0)
   4986     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM53400_A0r */
   4987         soc_block_list[61],
   4988         soc_iprocreg,
   4989         1,
   4990         0,
   4991         0x18047030,
   4992         0,
   4993         0,
   4994         5,
   4995         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM53400_A0r_fields,
   4996         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   4997         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   4998         -1,
   4999         -1,
   5000     },
   5001 #endif /* chips */
   5002 
   5003 #if defined(BCM_56370_A0)
   5004     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM56370_A0r */
   5005         soc_block_list[61],
   5006         soc_iprocreg,
   5007         1,
   5008         0,
   5009         0x15000030,
   5010         0,
   5011         0,
   5012         5,
   5013         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM53400_A0r_fields,
   5014         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5015         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5016         -1,
   5017         -1,
   5018         3,
   5019     },
   5020 #endif /* chips */
   5021 
   5022 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   5023     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5024     defined(BCM_56450_B1)
   5025     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM56450_A0r */
   5026         soc_block_list[61],
   5027         soc_iprocreg,
   5028         1,
   5029         0,
   5030         0x18027030,
   5031         0,
   5032         0,
   5033         5,
   5034         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM56450_A0r_fields,
   5035         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5036         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5037         -1,
   5038         -1,
   5039     },
   5040 #endif /* chips */
   5041 
   5042 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   5043     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   5044     defined(BCM_56670_B0)
   5045     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM56560_A0r */
   5046         soc_block_list[61],
   5047         soc_iprocreg,
   5048         1,
   5049         0,
   5050         0x18021030,
   5051         0,
   5052         0,
   5053         5,
   5054         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM53400_A0r_fields,
   5055         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5056         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5057         -1,
   5058         -1,
   5059     },
   5060 #endif /* chips */
   5061 
   5062 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5063     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   5064     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   5065     defined(BCM_56980_B0)
   5066     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM56960_A0r */
   5067         soc_block_list[61],
   5068         soc_iprocreg,
   5069         1,
   5070         0,
   5071         0x18021030,
   5072         0,
   5073         0,
   5074         5,
   5075         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM53400_A0r_fields,
   5076         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5077         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5078         -1,
   5079         -1,
   5080         3,
   5081     },
   5082 #endif /* chips */
   5083 
   5084 #if defined(BCM_88270_A0)
   5085     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88270_A0r */
   5086         soc_block_list[61],
   5087         soc_iprocreg,
   5088         1,
   5089         0,
   5090         0x18021030,
   5091         0,
   5092         0,
   5093         5,
   5094         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88270_A0r_fields,
   5095         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5096         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5097         -1,
   5098         -1,
   5099     },
   5100 #endif /* chips */
   5101 
   5102 #if defined(BCM_88375_A0)
   5103     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88375_A0r */
   5104         soc_block_list[61],
   5105         soc_iprocreg,
   5106         1,
   5107         0,
   5108         0x18021030,
   5109         0,
   5110         0,
   5111         5,
   5112         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88375_A0r_fields,
   5113         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5114         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5115         -1,
   5116         -1,
   5117     },
   5118 #endif /* chips */
   5119 
   5120 #if defined(BCM_88375_B0)
   5121     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88375_B0r */
   5122         soc_block_list[61],
   5123         soc_iprocreg,
   5124         1,
   5125         0,
   5126         0x18021030,
   5127         0,
   5128         0,
   5129         5,
   5130         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88375_B0r_fields,
   5131         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5132         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5133         -1,
   5134         -1,
   5135     },
   5136 #endif /* chips */
   5137 
   5138 #if defined(BCM_88470_A0)
   5139     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88470_A0r */
   5140         soc_block_list[61],
   5141         soc_iprocreg,
   5142         1,
   5143         0,
   5144         0x18021030,
   5145         0,
   5146         0,
   5147         5,
   5148         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88470_A0r_fields,
   5149         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5150         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5151         -1,
   5152         -1,
   5153     },
   5154 #endif /* chips */
   5155 
   5156 #if defined(BCM_88470_B0)
   5157     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88470_B0r */
   5158         soc_block_list[61],
   5159         soc_iprocreg,
   5160         1,
   5161         0,
   5162         0x18021030,
   5163         0,
   5164         0,
   5165         5,
   5166         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88470_B0r_fields,
   5167         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5168         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5169         -1,
   5170         -1,
   5171     },
   5172 #endif /* chips */
   5173 
   5174 #if defined(BCM_88675_B0)
   5175     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88675_B0r */
   5176         soc_block_list[61],
   5177         soc_iprocreg,
   5178         1,
   5179         0,
   5180         0x18021030,
   5181         0,
   5182         0,
   5183         5,
   5184         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88675_B0r_fields,
   5185         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5186         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5187         -1,
   5188         -1,
   5189     },
   5190 #endif /* chips */
   5191 
   5192 #if defined(BCM_88680_A0)
   5193     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88680_A0r */
   5194         soc_block_list[61],
   5195         soc_iprocreg,
   5196         1,
   5197         0,
   5198         0x18021030,
   5199         0,
   5200         0,
   5201         5,
   5202         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88680_A0r_fields,
   5203         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5204         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5205         -1,
   5206         -1,
   5207     },
   5208 #endif /* chips */
   5209 
   5210 #if defined(BCM_88690_A0)
   5211     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88690_A0r */
   5212         soc_block_list[61],
   5213         soc_iprocreg,
   5214         1,
   5215         0,
   5216         0x18021030,
   5217         0,
   5218         0,
   5219         5,
   5220         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88690_A0r_fields,
   5221         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5222         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5223         -1,
   5224         -1,
   5225     },
   5226 #endif /* chips */
   5227 
   5228 #if defined(BCM_88690_B0)
   5229     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88690_B0r */
   5230         soc_block_list[61],
   5231         soc_iprocreg,
   5232         1,
   5233         0,
   5234         0x18021030,
   5235         0,
   5236         0,
   5237         5,
   5238         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88690_B0r_fields,
   5239         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5240         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5241         -1,
   5242         -1,
   5243     },
   5244 #endif /* chips */
   5245 
   5246 #if defined(BCM_88790_A0)
   5247     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88790_A0r */
   5248         soc_block_list[61],
   5249         soc_iprocreg,
   5250         1,
   5251         0,
   5252         0x18021030,
   5253         0,
   5254         0,
   5255         5,
   5256         soc_QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BCM88790_A0r_fields,
   5257         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
   5258         SOC_RESET_MASK_DEC(0x0101ffff, 0x00000000)
   5259         -1,
   5260         -1,
   5261     },
   5262 #endif /* chips */
   5263 
   5264 #if defined(BCM_88675_A0)
   5265     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTEr */
   5266         soc_block_list[61],
   5267         soc_iprocreg,
   5268         1,
   5269         0,
   5270         0x18021038,
   5271         0,
   5272         0,
   5273         2,
   5274         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTEr_fields,
   5275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5276         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5277         -1,
   5278         -1,
   5279     },
   5280 #endif /* chips */
   5281 
   5282 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5283     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   5284     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   5285     defined(BCM_56260_B0)
   5286     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM53400_A0r */
   5287         soc_block_list[61],
   5288         soc_iprocreg,
   5289         1,
   5290         0,
   5291         0x18047038,
   5292         0,
   5293         0,
   5294         2,
   5295         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM53400_A0r_fields,
   5296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5298         -1,
   5299         -1,
   5300     },
   5301 #endif /* chips */
   5302 
   5303 #if defined(BCM_56370_A0)
   5304     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM56370_A0r */
   5305         soc_block_list[61],
   5306         soc_iprocreg,
   5307         1,
   5308         0,
   5309         0x15000038,
   5310         0,
   5311         0,
   5312         2,
   5313         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM53400_A0r_fields,
   5314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5315         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5316         -1,
   5317         -1,
   5318         3,
   5319     },
   5320 #endif /* chips */
   5321 
   5322 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   5323     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5324     defined(BCM_56450_B1)
   5325     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM56450_A0r */
   5326         soc_block_list[61],
   5327         soc_iprocreg,
   5328         1,
   5329         0,
   5330         0x18027038,
   5331         0,
   5332         0,
   5333         2,
   5334         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM56450_A0r_fields,
   5335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5336         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5337         -1,
   5338         -1,
   5339     },
   5340 #endif /* chips */
   5341 
   5342 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   5343     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   5344     defined(BCM_56670_B0)
   5345     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM56560_A0r */
   5346         soc_block_list[61],
   5347         soc_iprocreg,
   5348         1,
   5349         0,
   5350         0x18021038,
   5351         0,
   5352         0,
   5353         2,
   5354         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM53400_A0r_fields,
   5355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5356         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5357         -1,
   5358         -1,
   5359     },
   5360 #endif /* chips */
   5361 
   5362 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5363     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   5364     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   5365     defined(BCM_56980_B0)
   5366     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM56960_A0r */
   5367         soc_block_list[61],
   5368         soc_iprocreg,
   5369         1,
   5370         0,
   5371         0x18021038,
   5372         0,
   5373         0,
   5374         2,
   5375         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM53400_A0r_fields,
   5376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5377         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5378         -1,
   5379         -1,
   5380         3,
   5381     },
   5382 #endif /* chips */
   5383 
   5384 #if defined(BCM_88270_A0)
   5385     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88270_A0r */
   5386         soc_block_list[61],
   5387         soc_iprocreg,
   5388         1,
   5389         0,
   5390         0x18021038,
   5391         0,
   5392         0,
   5393         2,
   5394         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88270_A0r_fields,
   5395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5396         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5397         -1,
   5398         -1,
   5399     },
   5400 #endif /* chips */
   5401 
   5402 #if defined(BCM_88375_A0)
   5403     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88375_A0r */
   5404         soc_block_list[61],
   5405         soc_iprocreg,
   5406         1,
   5407         0,
   5408         0x18021038,
   5409         0,
   5410         0,
   5411         2,
   5412         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88375_A0r_fields,
   5413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5414         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5415         -1,
   5416         -1,
   5417     },
   5418 #endif /* chips */
   5419 
   5420 #if defined(BCM_88375_B0)
   5421     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88375_B0r */
   5422         soc_block_list[61],
   5423         soc_iprocreg,
   5424         1,
   5425         0,
   5426         0x18021038,
   5427         0,
   5428         0,
   5429         2,
   5430         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88375_B0r_fields,
   5431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5433         -1,
   5434         -1,
   5435     },
   5436 #endif /* chips */
   5437 
   5438 #if defined(BCM_88470_A0)
   5439     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88470_A0r */
   5440         soc_block_list[61],
   5441         soc_iprocreg,
   5442         1,
   5443         0,
   5444         0x18021038,
   5445         0,
   5446         0,
   5447         2,
   5448         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88470_A0r_fields,
   5449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5451         -1,
   5452         -1,
   5453     },
   5454 #endif /* chips */
   5455 
   5456 #if defined(BCM_88470_B0)
   5457     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88470_B0r */
   5458         soc_block_list[61],
   5459         soc_iprocreg,
   5460         1,
   5461         0,
   5462         0x18021038,
   5463         0,
   5464         0,
   5465         2,
   5466         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88470_B0r_fields,
   5467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5469         -1,
   5470         -1,
   5471     },
   5472 #endif /* chips */
   5473 
   5474 #if defined(BCM_88675_B0)
   5475     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88675_B0r */
   5476         soc_block_list[61],
   5477         soc_iprocreg,
   5478         1,
   5479         0,
   5480         0x18021038,
   5481         0,
   5482         0,
   5483         2,
   5484         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88675_B0r_fields,
   5485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5486         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5487         -1,
   5488         -1,
   5489     },
   5490 #endif /* chips */
   5491 
   5492 #if defined(BCM_88680_A0)
   5493     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88680_A0r */
   5494         soc_block_list[61],
   5495         soc_iprocreg,
   5496         1,
   5497         0,
   5498         0x18021038,
   5499         0,
   5500         0,
   5501         2,
   5502         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88680_A0r_fields,
   5503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5504         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5505         -1,
   5506         -1,
   5507     },
   5508 #endif /* chips */
   5509 
   5510 #if defined(BCM_88690_A0)
   5511     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88690_A0r */
   5512         soc_block_list[61],
   5513         soc_iprocreg,
   5514         1,
   5515         0,
   5516         0x18021038,
   5517         0,
   5518         0,
   5519         2,
   5520         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88690_A0r_fields,
   5521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5522         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5523         -1,
   5524         -1,
   5525     },
   5526 #endif /* chips */
   5527 
   5528 #if defined(BCM_88690_B0)
   5529     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88690_B0r */
   5530         soc_block_list[61],
   5531         soc_iprocreg,
   5532         1,
   5533         0,
   5534         0x18021038,
   5535         0,
   5536         0,
   5537         2,
   5538         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88690_B0r_fields,
   5539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5540         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5541         -1,
   5542         -1,
   5543     },
   5544 #endif /* chips */
   5545 
   5546 #if defined(BCM_88790_A0)
   5547     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88790_A0r */
   5548         soc_block_list[61],
   5549         soc_iprocreg,
   5550         1,
   5551         0,
   5552         0x18021038,
   5553         0,
   5554         0,
   5555         2,
   5556         soc_QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BCM88790_A0r_fields,
   5557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5558         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5559         -1,
   5560         -1,
   5561     },
   5562 #endif /* chips */
   5563 
   5564 #if defined(BCM_88675_A0)
   5565     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATAr */
   5566         soc_block_list[61],
   5567         soc_iprocreg,
   5568         1,
   5569         0,
   5570         0x1802104c,
   5571         0,
   5572         0,
   5573         2,
   5574         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATAr_fields,
   5575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5576         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5577         -1,
   5578         -1,
   5579     },
   5580 #endif /* chips */
   5581 
   5582 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5583     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   5584     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   5585     defined(BCM_56260_B0)
   5586     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM53400_A0r */
   5587         soc_block_list[61],
   5588         soc_iprocreg,
   5589         1,
   5590         0,
   5591         0x1804704c,
   5592         0,
   5593         0,
   5594         2,
   5595         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM53400_A0r_fields,
   5596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5597         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5598         -1,
   5599         -1,
   5600     },
   5601 #endif /* chips */
   5602 
   5603 #if defined(BCM_56370_A0)
   5604     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM56370_A0r */
   5605         soc_block_list[61],
   5606         soc_iprocreg,
   5607         1,
   5608         0,
   5609         0x1500004c,
   5610         0,
   5611         0,
   5612         2,
   5613         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM53400_A0r_fields,
   5614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5615         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5616         -1,
   5617         -1,
   5618         3,
   5619     },
   5620 #endif /* chips */
   5621 
   5622 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   5623     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5624     defined(BCM_56450_B1)
   5625     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM56450_A0r */
   5626         soc_block_list[61],
   5627         soc_iprocreg,
   5628         1,
   5629         0,
   5630         0x1802704c,
   5631         0,
   5632         0,
   5633         2,
   5634         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM56450_A0r_fields,
   5635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5636         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5637         -1,
   5638         -1,
   5639     },
   5640 #endif /* chips */
   5641 
   5642 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   5643     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   5644     defined(BCM_56670_B0)
   5645     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM56560_A0r */
   5646         soc_block_list[61],
   5647         soc_iprocreg,
   5648         1,
   5649         0,
   5650         0x1802104c,
   5651         0,
   5652         0,
   5653         2,
   5654         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM53400_A0r_fields,
   5655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5656         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5657         -1,
   5658         -1,
   5659     },
   5660 #endif /* chips */
   5661 
   5662 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5663     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   5664     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   5665     defined(BCM_56980_B0)
   5666     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM56960_A0r */
   5667         soc_block_list[61],
   5668         soc_iprocreg,
   5669         1,
   5670         0,
   5671         0x1802104c,
   5672         0,
   5673         0,
   5674         2,
   5675         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM53400_A0r_fields,
   5676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5677         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5678         -1,
   5679         -1,
   5680         3,
   5681     },
   5682 #endif /* chips */
   5683 
   5684 #if defined(BCM_88270_A0)
   5685     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88270_A0r */
   5686         soc_block_list[61],
   5687         soc_iprocreg,
   5688         1,
   5689         0,
   5690         0x1802104c,
   5691         0,
   5692         0,
   5693         2,
   5694         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88270_A0r_fields,
   5695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5696         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5697         -1,
   5698         -1,
   5699     },
   5700 #endif /* chips */
   5701 
   5702 #if defined(BCM_88375_A0)
   5703     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88375_A0r */
   5704         soc_block_list[61],
   5705         soc_iprocreg,
   5706         1,
   5707         0,
   5708         0x1802104c,
   5709         0,
   5710         0,
   5711         2,
   5712         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88375_A0r_fields,
   5713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5714         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5715         -1,
   5716         -1,
   5717     },
   5718 #endif /* chips */
   5719 
   5720 #if defined(BCM_88375_B0)
   5721     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88375_B0r */
   5722         soc_block_list[61],
   5723         soc_iprocreg,
   5724         1,
   5725         0,
   5726         0x1802104c,
   5727         0,
   5728         0,
   5729         2,
   5730         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88375_B0r_fields,
   5731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5732         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5733         -1,
   5734         -1,
   5735     },
   5736 #endif /* chips */
   5737 
   5738 #if defined(BCM_88470_A0)
   5739     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88470_A0r */
   5740         soc_block_list[61],
   5741         soc_iprocreg,
   5742         1,
   5743         0,
   5744         0x1802104c,
   5745         0,
   5746         0,
   5747         2,
   5748         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88470_A0r_fields,
   5749         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5750         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5751         -1,
   5752         -1,
   5753     },
   5754 #endif /* chips */
   5755 
   5756 #if defined(BCM_88470_B0)
   5757     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88470_B0r */
   5758         soc_block_list[61],
   5759         soc_iprocreg,
   5760         1,
   5761         0,
   5762         0x1802104c,
   5763         0,
   5764         0,
   5765         2,
   5766         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88470_B0r_fields,
   5767         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5768         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5769         -1,
   5770         -1,
   5771     },
   5772 #endif /* chips */
   5773 
   5774 #if defined(BCM_88675_B0)
   5775     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88675_B0r */
   5776         soc_block_list[61],
   5777         soc_iprocreg,
   5778         1,
   5779         0,
   5780         0x1802104c,
   5781         0,
   5782         0,
   5783         2,
   5784         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88675_B0r_fields,
   5785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5786         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5787         -1,
   5788         -1,
   5789     },
   5790 #endif /* chips */
   5791 
   5792 #if defined(BCM_88680_A0)
   5793     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88680_A0r */
   5794         soc_block_list[61],
   5795         soc_iprocreg,
   5796         1,
   5797         0,
   5798         0x1802104c,
   5799         0,
   5800         0,
   5801         2,
   5802         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88680_A0r_fields,
   5803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5804         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5805         -1,
   5806         -1,
   5807     },
   5808 #endif /* chips */
   5809 
   5810 #if defined(BCM_88690_A0)
   5811     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88690_A0r */
   5812         soc_block_list[61],
   5813         soc_iprocreg,
   5814         1,
   5815         0,
   5816         0x1802104c,
   5817         0,
   5818         0,
   5819         2,
   5820         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88690_A0r_fields,
   5821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5822         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5823         -1,
   5824         -1,
   5825     },
   5826 #endif /* chips */
   5827 
   5828 #if defined(BCM_88690_B0)
   5829     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88690_B0r */
   5830         soc_block_list[61],
   5831         soc_iprocreg,
   5832         1,
   5833         0,
   5834         0x1802104c,
   5835         0,
   5836         0,
   5837         2,
   5838         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88690_B0r_fields,
   5839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5840         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5841         -1,
   5842         -1,
   5843     },
   5844 #endif /* chips */
   5845 
   5846 #if defined(BCM_88790_A0)
   5847     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88790_A0r */
   5848         soc_block_list[61],
   5849         soc_iprocreg,
   5850         1,
   5851         0,
   5852         0x1802104c,
   5853         0,
   5854         0,
   5855         2,
   5856         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BCM88790_A0r_fields,
   5857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5858         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5859         -1,
   5860         -1,
   5861     },
   5862 #endif /* chips */
   5863 
   5864 #if defined(BCM_88675_A0)
   5865     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIRr */
   5866         soc_block_list[61],
   5867         soc_iprocreg,
   5868         1,
   5869         0,
   5870         0x18021048,
   5871         0,
   5872         0,
   5873         2,
   5874         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIRr_fields,
   5875         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   5876         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5877         -1,
   5878         -1,
   5879     },
   5880 #endif /* chips */
   5881 
   5882 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   5883     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   5884     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   5885     defined(BCM_56260_B0)
   5886     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM53400_A0r */
   5887         soc_block_list[61],
   5888         soc_iprocreg,
   5889         1,
   5890         0,
   5891         0x18047048,
   5892         0,
   5893         0,
   5894         2,
   5895         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM53400_A0r_fields,
   5896         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   5897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5898         -1,
   5899         -1,
   5900     },
   5901 #endif /* chips */
   5902 
   5903 #if defined(BCM_56370_A0)
   5904     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM56370_A0r */
   5905         soc_block_list[61],
   5906         soc_iprocreg,
   5907         1,
   5908         0,
   5909         0x15000048,
   5910         0,
   5911         0,
   5912         2,
   5913         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM53400_A0r_fields,
   5914         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   5915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5916         -1,
   5917         -1,
   5918         3,
   5919     },
   5920 #endif /* chips */
   5921 
   5922 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   5923     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5924     defined(BCM_56450_B1)
   5925     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM56450_A0r */
   5926         soc_block_list[61],
   5927         soc_iprocreg,
   5928         1,
   5929         0,
   5930         0x18027048,
   5931         0,
   5932         0,
   5933         2,
   5934         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM56450_A0r_fields,
   5935         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   5936         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5937         -1,
   5938         -1,
   5939     },
   5940 #endif /* chips */
   5941 
   5942 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   5943     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   5944     defined(BCM_56670_B0)
   5945     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM56560_A0r */
   5946         soc_block_list[61],
   5947         soc_iprocreg,
   5948         1,
   5949         0,
   5950         0x18021048,
   5951         0,
   5952         0,
   5953         2,
   5954         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM53400_A0r_fields,
   5955         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   5956         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5957         -1,
   5958         -1,
   5959     },
   5960 #endif /* chips */
   5961 
   5962 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   5963     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   5964     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   5965     defined(BCM_56980_B0)
   5966     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM56960_A0r */
   5967         soc_block_list[61],
   5968         soc_iprocreg,
   5969         1,
   5970         0,
   5971         0x18021048,
   5972         0,
   5973         0,
   5974         2,
   5975         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM53400_A0r_fields,
   5976         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   5977         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5978         -1,
   5979         -1,
   5980         3,
   5981     },
   5982 #endif /* chips */
   5983 
   5984 #if defined(BCM_88270_A0)
   5985     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88270_A0r */
   5986         soc_block_list[61],
   5987         soc_iprocreg,
   5988         1,
   5989         0,
   5990         0x18021048,
   5991         0,
   5992         0,
   5993         2,
   5994         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88270_A0r_fields,
   5995         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   5996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5997         -1,
   5998         -1,
   5999     },
   6000 #endif /* chips */
   6001 
   6002 #if defined(BCM_88375_A0)
   6003     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88375_A0r */
   6004         soc_block_list[61],
   6005         soc_iprocreg,
   6006         1,
   6007         0,
   6008         0x18021048,
   6009         0,
   6010         0,
   6011         2,
   6012         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88375_A0r_fields,
   6013         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6014         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6015         -1,
   6016         -1,
   6017     },
   6018 #endif /* chips */
   6019 
   6020 #if defined(BCM_88375_B0)
   6021     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88375_B0r */
   6022         soc_block_list[61],
   6023         soc_iprocreg,
   6024         1,
   6025         0,
   6026         0x18021048,
   6027         0,
   6028         0,
   6029         2,
   6030         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88375_B0r_fields,
   6031         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6032         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6033         -1,
   6034         -1,
   6035     },
   6036 #endif /* chips */
   6037 
   6038 #if defined(BCM_88470_A0)
   6039     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88470_A0r */
   6040         soc_block_list[61],
   6041         soc_iprocreg,
   6042         1,
   6043         0,
   6044         0x18021048,
   6045         0,
   6046         0,
   6047         2,
   6048         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88470_A0r_fields,
   6049         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6050         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6051         -1,
   6052         -1,
   6053     },
   6054 #endif /* chips */
   6055 
   6056 #if defined(BCM_88470_B0)
   6057     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88470_B0r */
   6058         soc_block_list[61],
   6059         soc_iprocreg,
   6060         1,
   6061         0,
   6062         0x18021048,
   6063         0,
   6064         0,
   6065         2,
   6066         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88470_B0r_fields,
   6067         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6068         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6069         -1,
   6070         -1,
   6071     },
   6072 #endif /* chips */
   6073 
   6074 #if defined(BCM_88675_B0)
   6075     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88675_B0r */
   6076         soc_block_list[61],
   6077         soc_iprocreg,
   6078         1,
   6079         0,
   6080         0x18021048,
   6081         0,
   6082         0,
   6083         2,
   6084         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88675_B0r_fields,
   6085         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6086         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6087         -1,
   6088         -1,
   6089     },
   6090 #endif /* chips */
   6091 
   6092 #if defined(BCM_88680_A0)
   6093     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88680_A0r */
   6094         soc_block_list[61],
   6095         soc_iprocreg,
   6096         1,
   6097         0,
   6098         0x18021048,
   6099         0,
   6100         0,
   6101         2,
   6102         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88680_A0r_fields,
   6103         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6104         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6105         -1,
   6106         -1,
   6107     },
   6108 #endif /* chips */
   6109 
   6110 #if defined(BCM_88690_A0)
   6111     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88690_A0r */
   6112         soc_block_list[61],
   6113         soc_iprocreg,
   6114         1,
   6115         0,
   6116         0x18021048,
   6117         0,
   6118         0,
   6119         2,
   6120         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88690_A0r_fields,
   6121         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6122         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6123         -1,
   6124         -1,
   6125     },
   6126 #endif /* chips */
   6127 
   6128 #if defined(BCM_88690_B0)
   6129     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88690_B0r */
   6130         soc_block_list[61],
   6131         soc_iprocreg,
   6132         1,
   6133         0,
   6134         0x18021048,
   6135         0,
   6136         0,
   6137         2,
   6138         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88690_B0r_fields,
   6139         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6140         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6141         -1,
   6142         -1,
   6143     },
   6144 #endif /* chips */
   6145 
   6146 #if defined(BCM_88790_A0)
   6147     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88790_A0r */
   6148         soc_block_list[61],
   6149         soc_iprocreg,
   6150         1,
   6151         0,
   6152         0x18021048,
   6153         0,
   6154         0,
   6155         2,
   6156         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BCM88790_A0r_fields,
   6157         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
   6158         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6159         -1,
   6160         -1,
   6161     },
   6162 #endif /* chips */
   6163 
   6164 #if defined(BCM_88675_A0)
   6165     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLEr */
   6166         soc_block_list[61],
   6167         soc_iprocreg,
   6168         1,
   6169         0,
   6170         0x18021044,
   6171         0,
   6172         0,
   6173         2,
   6174         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLEr_fields,
   6175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6176         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6177         -1,
   6178         -1,
   6179     },
   6180 #endif /* chips */
   6181 
   6182 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6183     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6184     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6185     defined(BCM_56260_B0)
   6186     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM53400_A0r */
   6187         soc_block_list[61],
   6188         soc_iprocreg,
   6189         1,
   6190         0,
   6191         0x18047044,
   6192         0,
   6193         0,
   6194         2,
   6195         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM53400_A0r_fields,
   6196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6197         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6198         -1,
   6199         -1,
   6200     },
   6201 #endif /* chips */
   6202 
   6203 #if defined(BCM_56370_A0)
   6204     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM56370_A0r */
   6205         soc_block_list[61],
   6206         soc_iprocreg,
   6207         1,
   6208         0,
   6209         0x15000044,
   6210         0,
   6211         0,
   6212         2,
   6213         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM53400_A0r_fields,
   6214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6215         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6216         -1,
   6217         -1,
   6218         3,
   6219     },
   6220 #endif /* chips */
   6221 
   6222 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6223     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6224     defined(BCM_56450_B1)
   6225     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM56450_A0r */
   6226         soc_block_list[61],
   6227         soc_iprocreg,
   6228         1,
   6229         0,
   6230         0x18027044,
   6231         0,
   6232         0,
   6233         2,
   6234         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM56450_A0r_fields,
   6235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6236         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6237         -1,
   6238         -1,
   6239     },
   6240 #endif /* chips */
   6241 
   6242 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   6243     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   6244     defined(BCM_56670_B0)
   6245     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM56560_A0r */
   6246         soc_block_list[61],
   6247         soc_iprocreg,
   6248         1,
   6249         0,
   6250         0x18021044,
   6251         0,
   6252         0,
   6253         2,
   6254         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM53400_A0r_fields,
   6255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6256         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6257         -1,
   6258         -1,
   6259     },
   6260 #endif /* chips */
   6261 
   6262 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6263     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   6264     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   6265     defined(BCM_56980_B0)
   6266     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM56960_A0r */
   6267         soc_block_list[61],
   6268         soc_iprocreg,
   6269         1,
   6270         0,
   6271         0x18021044,
   6272         0,
   6273         0,
   6274         2,
   6275         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM53400_A0r_fields,
   6276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6277         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6278         -1,
   6279         -1,
   6280         3,
   6281     },
   6282 #endif /* chips */
   6283 
   6284 #if defined(BCM_88270_A0)
   6285     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88270_A0r */
   6286         soc_block_list[61],
   6287         soc_iprocreg,
   6288         1,
   6289         0,
   6290         0x18021044,
   6291         0,
   6292         0,
   6293         2,
   6294         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88270_A0r_fields,
   6295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6296         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6297         -1,
   6298         -1,
   6299     },
   6300 #endif /* chips */
   6301 
   6302 #if defined(BCM_88375_A0)
   6303     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88375_A0r */
   6304         soc_block_list[61],
   6305         soc_iprocreg,
   6306         1,
   6307         0,
   6308         0x18021044,
   6309         0,
   6310         0,
   6311         2,
   6312         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88375_A0r_fields,
   6313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6314         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6315         -1,
   6316         -1,
   6317     },
   6318 #endif /* chips */
   6319 
   6320 #if defined(BCM_88375_B0)
   6321     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88375_B0r */
   6322         soc_block_list[61],
   6323         soc_iprocreg,
   6324         1,
   6325         0,
   6326         0x18021044,
   6327         0,
   6328         0,
   6329         2,
   6330         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88375_B0r_fields,
   6331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6333         -1,
   6334         -1,
   6335     },
   6336 #endif /* chips */
   6337 
   6338 #if defined(BCM_88470_A0)
   6339     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88470_A0r */
   6340         soc_block_list[61],
   6341         soc_iprocreg,
   6342         1,
   6343         0,
   6344         0x18021044,
   6345         0,
   6346         0,
   6347         2,
   6348         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88470_A0r_fields,
   6349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6350         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6351         -1,
   6352         -1,
   6353     },
   6354 #endif /* chips */
   6355 
   6356 #if defined(BCM_88470_B0)
   6357     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88470_B0r */
   6358         soc_block_list[61],
   6359         soc_iprocreg,
   6360         1,
   6361         0,
   6362         0x18021044,
   6363         0,
   6364         0,
   6365         2,
   6366         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88470_B0r_fields,
   6367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6368         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6369         -1,
   6370         -1,
   6371     },
   6372 #endif /* chips */
   6373 
   6374 #if defined(BCM_88675_B0)
   6375     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88675_B0r */
   6376         soc_block_list[61],
   6377         soc_iprocreg,
   6378         1,
   6379         0,
   6380         0x18021044,
   6381         0,
   6382         0,
   6383         2,
   6384         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88675_B0r_fields,
   6385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6386         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6387         -1,
   6388         -1,
   6389     },
   6390 #endif /* chips */
   6391 
   6392 #if defined(BCM_88680_A0)
   6393     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88680_A0r */
   6394         soc_block_list[61],
   6395         soc_iprocreg,
   6396         1,
   6397         0,
   6398         0x18021044,
   6399         0,
   6400         0,
   6401         2,
   6402         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88680_A0r_fields,
   6403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6404         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6405         -1,
   6406         -1,
   6407     },
   6408 #endif /* chips */
   6409 
   6410 #if defined(BCM_88690_A0)
   6411     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88690_A0r */
   6412         soc_block_list[61],
   6413         soc_iprocreg,
   6414         1,
   6415         0,
   6416         0x18021044,
   6417         0,
   6418         0,
   6419         2,
   6420         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88690_A0r_fields,
   6421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6422         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6423         -1,
   6424         -1,
   6425     },
   6426 #endif /* chips */
   6427 
   6428 #if defined(BCM_88690_B0)
   6429     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88690_B0r */
   6430         soc_block_list[61],
   6431         soc_iprocreg,
   6432         1,
   6433         0,
   6434         0x18021044,
   6435         0,
   6436         0,
   6437         2,
   6438         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88690_B0r_fields,
   6439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6440         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6441         -1,
   6442         -1,
   6443     },
   6444 #endif /* chips */
   6445 
   6446 #if defined(BCM_88790_A0)
   6447     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88790_A0r */
   6448         soc_block_list[61],
   6449         soc_iprocreg,
   6450         1,
   6451         0,
   6452         0x18021044,
   6453         0,
   6454         0,
   6455         2,
   6456         soc_QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BCM88790_A0r_fields,
   6457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6458         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6459         -1,
   6460         -1,
   6461     },
   6462 #endif /* chips */
   6463 
   6464 #if defined(BCM_88675_A0)
   6465     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLEr */
   6466         soc_block_list[61],
   6467         soc_iprocreg,
   6468         1,
   6469         0,
   6470         0x18021040,
   6471         0,
   6472         0,
   6473         2,
   6474         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLEr_fields,
   6475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6476         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6477         -1,
   6478         -1,
   6479     },
   6480 #endif /* chips */
   6481 
   6482 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6483     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6484     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6485     defined(BCM_56260_B0)
   6486     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM53400_A0r */
   6487         soc_block_list[61],
   6488         soc_iprocreg,
   6489         1,
   6490         0,
   6491         0x18047040,
   6492         0,
   6493         0,
   6494         2,
   6495         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM53400_A0r_fields,
   6496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6498         -1,
   6499         -1,
   6500     },
   6501 #endif /* chips */
   6502 
   6503 #if defined(BCM_56370_A0)
   6504     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM56370_A0r */
   6505         soc_block_list[61],
   6506         soc_iprocreg,
   6507         1,
   6508         0,
   6509         0x15000040,
   6510         0,
   6511         0,
   6512         2,
   6513         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM53400_A0r_fields,
   6514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6516         -1,
   6517         -1,
   6518         3,
   6519     },
   6520 #endif /* chips */
   6521 
   6522 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6523     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6524     defined(BCM_56450_B1)
   6525     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM56450_A0r */
   6526         soc_block_list[61],
   6527         soc_iprocreg,
   6528         1,
   6529         0,
   6530         0x18027040,
   6531         0,
   6532         0,
   6533         2,
   6534         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM56450_A0r_fields,
   6535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6536         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6537         -1,
   6538         -1,
   6539     },
   6540 #endif /* chips */
   6541 
   6542 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   6543     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   6544     defined(BCM_56670_B0)
   6545     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM56560_A0r */
   6546         soc_block_list[61],
   6547         soc_iprocreg,
   6548         1,
   6549         0,
   6550         0x18021040,
   6551         0,
   6552         0,
   6553         2,
   6554         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM53400_A0r_fields,
   6555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6556         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6557         -1,
   6558         -1,
   6559     },
   6560 #endif /* chips */
   6561 
   6562 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6563     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   6564     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   6565     defined(BCM_56980_B0)
   6566     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM56960_A0r */
   6567         soc_block_list[61],
   6568         soc_iprocreg,
   6569         1,
   6570         0,
   6571         0x18021040,
   6572         0,
   6573         0,
   6574         2,
   6575         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM53400_A0r_fields,
   6576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6577         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6578         -1,
   6579         -1,
   6580         3,
   6581     },
   6582 #endif /* chips */
   6583 
   6584 #if defined(BCM_88270_A0)
   6585     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88270_A0r */
   6586         soc_block_list[61],
   6587         soc_iprocreg,
   6588         1,
   6589         0,
   6590         0x18021040,
   6591         0,
   6592         0,
   6593         2,
   6594         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88270_A0r_fields,
   6595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6596         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6597         -1,
   6598         -1,
   6599     },
   6600 #endif /* chips */
   6601 
   6602 #if defined(BCM_88375_A0)
   6603     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88375_A0r */
   6604         soc_block_list[61],
   6605         soc_iprocreg,
   6606         1,
   6607         0,
   6608         0x18021040,
   6609         0,
   6610         0,
   6611         2,
   6612         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88375_A0r_fields,
   6613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6614         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6615         -1,
   6616         -1,
   6617     },
   6618 #endif /* chips */
   6619 
   6620 #if defined(BCM_88375_B0)
   6621     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88375_B0r */
   6622         soc_block_list[61],
   6623         soc_iprocreg,
   6624         1,
   6625         0,
   6626         0x18021040,
   6627         0,
   6628         0,
   6629         2,
   6630         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88375_B0r_fields,
   6631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6632         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6633         -1,
   6634         -1,
   6635     },
   6636 #endif /* chips */
   6637 
   6638 #if defined(BCM_88470_A0)
   6639     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88470_A0r */
   6640         soc_block_list[61],
   6641         soc_iprocreg,
   6642         1,
   6643         0,
   6644         0x18021040,
   6645         0,
   6646         0,
   6647         2,
   6648         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88470_A0r_fields,
   6649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6651         -1,
   6652         -1,
   6653     },
   6654 #endif /* chips */
   6655 
   6656 #if defined(BCM_88470_B0)
   6657     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88470_B0r */
   6658         soc_block_list[61],
   6659         soc_iprocreg,
   6660         1,
   6661         0,
   6662         0x18021040,
   6663         0,
   6664         0,
   6665         2,
   6666         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88470_B0r_fields,
   6667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6668         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6669         -1,
   6670         -1,
   6671     },
   6672 #endif /* chips */
   6673 
   6674 #if defined(BCM_88675_B0)
   6675     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88675_B0r */
   6676         soc_block_list[61],
   6677         soc_iprocreg,
   6678         1,
   6679         0,
   6680         0x18021040,
   6681         0,
   6682         0,
   6683         2,
   6684         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88675_B0r_fields,
   6685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6686         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6687         -1,
   6688         -1,
   6689     },
   6690 #endif /* chips */
   6691 
   6692 #if defined(BCM_88680_A0)
   6693     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88680_A0r */
   6694         soc_block_list[61],
   6695         soc_iprocreg,
   6696         1,
   6697         0,
   6698         0x18021040,
   6699         0,
   6700         0,
   6701         2,
   6702         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88680_A0r_fields,
   6703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6704         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6705         -1,
   6706         -1,
   6707     },
   6708 #endif /* chips */
   6709 
   6710 #if defined(BCM_88690_A0)
   6711     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88690_A0r */
   6712         soc_block_list[61],
   6713         soc_iprocreg,
   6714         1,
   6715         0,
   6716         0x18021040,
   6717         0,
   6718         0,
   6719         2,
   6720         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88690_A0r_fields,
   6721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6722         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6723         -1,
   6724         -1,
   6725     },
   6726 #endif /* chips */
   6727 
   6728 #if defined(BCM_88690_B0)
   6729     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88690_B0r */
   6730         soc_block_list[61],
   6731         soc_iprocreg,
   6732         1,
   6733         0,
   6734         0x18021040,
   6735         0,
   6736         0,
   6737         2,
   6738         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88690_B0r_fields,
   6739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6740         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6741         -1,
   6742         -1,
   6743     },
   6744 #endif /* chips */
   6745 
   6746 #if defined(BCM_88790_A0)
   6747     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88790_A0r */
   6748         soc_block_list[61],
   6749         soc_iprocreg,
   6750         1,
   6751         0,
   6752         0x18021040,
   6753         0,
   6754         0,
   6755         2,
   6756         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BCM88790_A0r_fields,
   6757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6758         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6759         -1,
   6760         -1,
   6761     },
   6762 #endif /* chips */
   6763 
   6764 #if defined(BCM_88675_A0)
   6765     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUEr */
   6766         soc_block_list[61],
   6767         soc_iprocreg,
   6768         1,
   6769         0,
   6770         0x1802103c,
   6771         0,
   6772         0,
   6773         2,
   6774         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUEr_fields,
   6775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6776         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6777         -1,
   6778         -1,
   6779     },
   6780 #endif /* chips */
   6781 
   6782 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6783     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   6784     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   6785     defined(BCM_56260_B0)
   6786     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM53400_A0r */
   6787         soc_block_list[61],
   6788         soc_iprocreg,
   6789         1,
   6790         0,
   6791         0x1804703c,
   6792         0,
   6793         0,
   6794         2,
   6795         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM53400_A0r_fields,
   6796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6797         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6798         -1,
   6799         -1,
   6800     },
   6801 #endif /* chips */
   6802 
   6803 #if defined(BCM_56370_A0)
   6804     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM56370_A0r */
   6805         soc_block_list[61],
   6806         soc_iprocreg,
   6807         1,
   6808         0,
   6809         0x1500003c,
   6810         0,
   6811         0,
   6812         2,
   6813         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM53400_A0r_fields,
   6814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6815         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6816         -1,
   6817         -1,
   6818         3,
   6819     },
   6820 #endif /* chips */
   6821 
   6822 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   6823     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6824     defined(BCM_56450_B1)
   6825     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM56450_A0r */
   6826         soc_block_list[61],
   6827         soc_iprocreg,
   6828         1,
   6829         0,
   6830         0x1802703c,
   6831         0,
   6832         0,
   6833         2,
   6834         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM56450_A0r_fields,
   6835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6837         -1,
   6838         -1,
   6839     },
   6840 #endif /* chips */
   6841 
   6842 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   6843     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   6844     defined(BCM_56670_B0)
   6845     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM56560_A0r */
   6846         soc_block_list[61],
   6847         soc_iprocreg,
   6848         1,
   6849         0,
   6850         0x1802103c,
   6851         0,
   6852         0,
   6853         2,
   6854         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM53400_A0r_fields,
   6855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6856         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6857         -1,
   6858         -1,
   6859     },
   6860 #endif /* chips */
   6861 
   6862 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   6863     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   6864     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   6865     defined(BCM_56980_B0)
   6866     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM56960_A0r */
   6867         soc_block_list[61],
   6868         soc_iprocreg,
   6869         1,
   6870         0,
   6871         0x1802103c,
   6872         0,
   6873         0,
   6874         2,
   6875         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM53400_A0r_fields,
   6876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6878         -1,
   6879         -1,
   6880         3,
   6881     },
   6882 #endif /* chips */
   6883 
   6884 #if defined(BCM_88270_A0)
   6885     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88270_A0r */
   6886         soc_block_list[61],
   6887         soc_iprocreg,
   6888         1,
   6889         0,
   6890         0x1802103c,
   6891         0,
   6892         0,
   6893         2,
   6894         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88270_A0r_fields,
   6895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6896         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6897         -1,
   6898         -1,
   6899     },
   6900 #endif /* chips */
   6901 
   6902 #if defined(BCM_88375_A0)
   6903     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88375_A0r */
   6904         soc_block_list[61],
   6905         soc_iprocreg,
   6906         1,
   6907         0,
   6908         0x1802103c,
   6909         0,
   6910         0,
   6911         2,
   6912         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88375_A0r_fields,
   6913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6914         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6915         -1,
   6916         -1,
   6917     },
   6918 #endif /* chips */
   6919 
   6920 #if defined(BCM_88375_B0)
   6921     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88375_B0r */
   6922         soc_block_list[61],
   6923         soc_iprocreg,
   6924         1,
   6925         0,
   6926         0x1802103c,
   6927         0,
   6928         0,
   6929         2,
   6930         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88375_B0r_fields,
   6931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6932         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6933         -1,
   6934         -1,
   6935     },
   6936 #endif /* chips */
   6937 
   6938 #if defined(BCM_88470_A0)
   6939     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88470_A0r */
   6940         soc_block_list[61],
   6941         soc_iprocreg,
   6942         1,
   6943         0,
   6944         0x1802103c,
   6945         0,
   6946         0,
   6947         2,
   6948         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88470_A0r_fields,
   6949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6950         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6951         -1,
   6952         -1,
   6953     },
   6954 #endif /* chips */
   6955 
   6956 #if defined(BCM_88470_B0)
   6957     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88470_B0r */
   6958         soc_block_list[61],
   6959         soc_iprocreg,
   6960         1,
   6961         0,
   6962         0x1802103c,
   6963         0,
   6964         0,
   6965         2,
   6966         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88470_B0r_fields,
   6967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6968         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6969         -1,
   6970         -1,
   6971     },
   6972 #endif /* chips */
   6973 
   6974 #if defined(BCM_88675_B0)
   6975     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88675_B0r */
   6976         soc_block_list[61],
   6977         soc_iprocreg,
   6978         1,
   6979         0,
   6980         0x1802103c,
   6981         0,
   6982         0,
   6983         2,
   6984         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88675_B0r_fields,
   6985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6986         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6987         -1,
   6988         -1,
   6989     },
   6990 #endif /* chips */
   6991 
   6992 #if defined(BCM_88680_A0)
   6993     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88680_A0r */
   6994         soc_block_list[61],
   6995         soc_iprocreg,
   6996         1,
   6997         0,
   6998         0x1802103c,
   6999         0,
   7000         0,
   7001         2,
   7002         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88680_A0r_fields,
   7003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7004         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7005         -1,
   7006         -1,
   7007     },
   7008 #endif /* chips */
   7009 
   7010 #if defined(BCM_88690_A0)
   7011     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88690_A0r */
   7012         soc_block_list[61],
   7013         soc_iprocreg,
   7014         1,
   7015         0,
   7016         0x1802103c,
   7017         0,
   7018         0,
   7019         2,
   7020         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88690_A0r_fields,
   7021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7023         -1,
   7024         -1,
   7025     },
   7026 #endif /* chips */
   7027 
   7028 #if defined(BCM_88690_B0)
   7029     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88690_B0r */
   7030         soc_block_list[61],
   7031         soc_iprocreg,
   7032         1,
   7033         0,
   7034         0x1802103c,
   7035         0,
   7036         0,
   7037         2,
   7038         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88690_B0r_fields,
   7039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7040         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7041         -1,
   7042         -1,
   7043     },
   7044 #endif /* chips */
   7045 
   7046 #if defined(BCM_88790_A0)
   7047     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88790_A0r */
   7048         soc_block_list[61],
   7049         soc_iprocreg,
   7050         1,
   7051         0,
   7052         0x1802103c,
   7053         0,
   7054         0,
   7055         2,
   7056         soc_QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BCM88790_A0r_fields,
   7057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7058         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7059         -1,
   7060         -1,
   7061     },
   7062 #endif /* chips */
   7063 
   7064 #if defined(BCM_88675_A0)
   7065     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUSr */
   7066         soc_block_list[61],
   7067         soc_iprocreg,
   7068         1,
   7069         0,
   7070         0x1802100c,
   7071         SOC_REG_FLAG_RO,
   7072         0,
   7073         2,
   7074         soc_QSPI_BSPI_REGISTERS_BUSY_STATUSr_fields,
   7075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7076         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7077         -1,
   7078         -1,
   7079     },
   7080 #endif /* chips */
   7081 
   7082 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7083     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7084     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7085     defined(BCM_56260_B0)
   7086     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM53400_A0r */
   7087         soc_block_list[61],
   7088         soc_iprocreg,
   7089         1,
   7090         0,
   7091         0x1804700c,
   7092         SOC_REG_FLAG_RO,
   7093         0,
   7094         2,
   7095         soc_AVS_REG_HW_MNTR_SW_MEASUREMENT_UNIT_BUSYr_fields,
   7096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7098         -1,
   7099         -1,
   7100     },
   7101 #endif /* chips */
   7102 
   7103 #if defined(BCM_56370_A0)
   7104     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM56370_A0r */
   7105         soc_block_list[61],
   7106         soc_iprocreg,
   7107         1,
   7108         0,
   7109         0x1500000c,
   7110         SOC_REG_FLAG_RO,
   7111         0,
   7112         2,
   7113         soc_AVS_REG_HW_MNTR_SW_MEASUREMENT_UNIT_BUSYr_fields,
   7114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7116         -1,
   7117         -1,
   7118         3,
   7119     },
   7120 #endif /* chips */
   7121 
   7122 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   7123     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7124     defined(BCM_56450_B1)
   7125     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM56450_A0r */
   7126         soc_block_list[61],
   7127         soc_iprocreg,
   7128         1,
   7129         0,
   7130         0x1802700c,
   7131         SOC_REG_FLAG_RO,
   7132         0,
   7133         2,
   7134         soc_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM56450_A0r_fields,
   7135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7136         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7137         -1,
   7138         -1,
   7139     },
   7140 #endif /* chips */
   7141 
   7142 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   7143     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   7144     defined(BCM_56670_B0)
   7145     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM56560_A0r */
   7146         soc_block_list[61],
   7147         soc_iprocreg,
   7148         1,
   7149         0,
   7150         0x1802100c,
   7151         SOC_REG_FLAG_RO,
   7152         0,
   7153         2,
   7154         soc_AVS_REG_HW_MNTR_SW_MEASUREMENT_UNIT_BUSYr_fields,
   7155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7157         -1,
   7158         -1,
   7159     },
   7160 #endif /* chips */
   7161 
   7162 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7163     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   7164     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   7165     defined(BCM_56980_B0)
   7166     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM56960_A0r */
   7167         soc_block_list[61],
   7168         soc_iprocreg,
   7169         1,
   7170         0,
   7171         0x1802100c,
   7172         SOC_REG_FLAG_RO,
   7173         0,
   7174         2,
   7175         soc_AVS_REG_HW_MNTR_SW_MEASUREMENT_UNIT_BUSYr_fields,
   7176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7177         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7178         -1,
   7179         -1,
   7180         3,
   7181     },
   7182 #endif /* chips */
   7183 
   7184 #if defined(BCM_88270_A0)
   7185     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88270_A0r */
   7186         soc_block_list[61],
   7187         soc_iprocreg,
   7188         1,
   7189         0,
   7190         0x1802100c,
   7191         SOC_REG_FLAG_RO,
   7192         0,
   7193         2,
   7194         soc_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88270_A0r_fields,
   7195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7196         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7197         -1,
   7198         -1,
   7199     },
   7200 #endif /* chips */
   7201 
   7202 #if defined(BCM_88375_A0)
   7203     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88375_A0r */
   7204         soc_block_list[61],
   7205         soc_iprocreg,
   7206         1,
   7207         0,
   7208         0x1802100c,
   7209         SOC_REG_FLAG_RO,
   7210         0,
   7211         2,
   7212         soc_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88375_A0r_fields,
   7213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7214         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7215         -1,
   7216         -1,
   7217     },
   7218 #endif /* chips */
   7219 
   7220 #if defined(BCM_88375_B0)
   7221     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88375_B0r */
   7222         soc_block_list[61],
   7223         soc_iprocreg,
   7224         1,
   7225         0,
   7226         0x1802100c,
   7227         SOC_REG_FLAG_RO,
   7228         0,
   7229         2,
   7230         soc_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88375_B0r_fields,
   7231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7232         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7233         -1,
   7234         -1,
   7235     },
   7236 #endif /* chips */
   7237 
   7238 #if defined(BCM_88470_A0)
   7239     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88470_A0r */
   7240         soc_block_list[61],
   7241         soc_iprocreg,
   7242         1,
   7243         0,
   7244         0x1802100c,
   7245         SOC_REG_FLAG_RO,
   7246         0,
   7247         2,
   7248         soc_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88470_A0r_fields,
   7249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7250         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7251         -1,
   7252         -1,
   7253     },
   7254 #endif /* chips */
   7255 
   7256 #if defined(BCM_88470_B0)
   7257     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88470_B0r */
   7258         soc_block_list[61],
   7259         soc_iprocreg,
   7260         1,
   7261         0,
   7262         0x1802100c,
   7263         SOC_REG_FLAG_RO,
   7264         0,
   7265         2,
   7266         soc_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88470_B0r_fields,
   7267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7268         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7269         -1,
   7270         -1,
   7271     },
   7272 #endif /* chips */
   7273 
   7274 #if defined(BCM_88675_B0)
   7275     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88675_B0r */
   7276         soc_block_list[61],
   7277         soc_iprocreg,
   7278         1,
   7279         0,
   7280         0x1802100c,
   7281         SOC_REG_FLAG_RO,
   7282         0,
   7283         2,
   7284         soc_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88675_B0r_fields,
   7285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7286         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7287         -1,
   7288         -1,
   7289     },
   7290 #endif /* chips */
   7291 
   7292 #if defined(BCM_88680_A0)
   7293     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88680_A0r */
   7294         soc_block_list[61],
   7295         soc_iprocreg,
   7296         1,
   7297         0,
   7298         0x1802100c,
   7299         SOC_REG_FLAG_RO,
   7300         0,
   7301         2,
   7302         soc_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88680_A0r_fields,
   7303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7304         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7305         -1,
   7306         -1,
   7307     },
   7308 #endif /* chips */
   7309 
   7310 #if defined(BCM_88690_A0)
   7311     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88690_A0r */
   7312         soc_block_list[61],
   7313         soc_iprocreg,
   7314         1,
   7315         0,
   7316         0x1802100c,
   7317         SOC_REG_FLAG_RO,
   7318         0,
   7319         2,
   7320         soc_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88690_A0r_fields,
   7321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7322         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7323         -1,
   7324         -1,
   7325     },
   7326 #endif /* chips */
   7327 
   7328 #if defined(BCM_88690_B0)
   7329     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88690_B0r */
   7330         soc_block_list[61],
   7331         soc_iprocreg,
   7332         1,
   7333         0,
   7334         0x1802100c,
   7335         SOC_REG_FLAG_RO,
   7336         0,
   7337         2,
   7338         soc_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88690_B0r_fields,
   7339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7340         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7341         -1,
   7342         -1,
   7343     },
   7344 #endif /* chips */
   7345 
   7346 #if defined(BCM_88790_A0)
   7347     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88790_A0r */
   7348         soc_block_list[61],
   7349         soc_iprocreg,
   7350         1,
   7351         0,
   7352         0x1802100c,
   7353         SOC_REG_FLAG_RO,
   7354         0,
   7355         2,
   7356         soc_QSPI_BSPI_REGISTERS_BUSY_STATUS_BCM88790_A0r_fields,
   7357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7358         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7359         -1,
   7360         -1,
   7361     },
   7362 #endif /* chips */
   7363 
   7364 #if defined(BCM_88675_A0)
   7365     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTEr */
   7366         soc_block_list[61],
   7367         soc_iprocreg,
   7368         1,
   7369         0,
   7370         0x18021034,
   7371         0,
   7372         0,
   7373         3,
   7374         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTEr_fields,
   7375         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7376         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7377         -1,
   7378         -1,
   7379     },
   7380 #endif /* chips */
   7381 
   7382 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7383     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7384     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7385     defined(BCM_56260_B0)
   7386     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM53400_A0r */
   7387         soc_block_list[61],
   7388         soc_iprocreg,
   7389         1,
   7390         0,
   7391         0x18047034,
   7392         0,
   7393         0,
   7394         3,
   7395         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM53400_A0r_fields,
   7396         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7397         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7398         -1,
   7399         -1,
   7400     },
   7401 #endif /* chips */
   7402 
   7403 #if defined(BCM_56370_A0)
   7404     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM56370_A0r */
   7405         soc_block_list[61],
   7406         soc_iprocreg,
   7407         1,
   7408         0,
   7409         0x15000034,
   7410         0,
   7411         0,
   7412         3,
   7413         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM53400_A0r_fields,
   7414         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7415         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7416         -1,
   7417         -1,
   7418         3,
   7419     },
   7420 #endif /* chips */
   7421 
   7422 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   7423     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7424     defined(BCM_56450_B1)
   7425     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM56450_A0r */
   7426         soc_block_list[61],
   7427         soc_iprocreg,
   7428         1,
   7429         0,
   7430         0x18027034,
   7431         0,
   7432         0,
   7433         3,
   7434         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM56450_A0r_fields,
   7435         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7436         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7437         -1,
   7438         -1,
   7439     },
   7440 #endif /* chips */
   7441 
   7442 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   7443     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   7444     defined(BCM_56670_B0)
   7445     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM56560_A0r */
   7446         soc_block_list[61],
   7447         soc_iprocreg,
   7448         1,
   7449         0,
   7450         0x18021034,
   7451         0,
   7452         0,
   7453         3,
   7454         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM53400_A0r_fields,
   7455         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7456         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7457         -1,
   7458         -1,
   7459     },
   7460 #endif /* chips */
   7461 
   7462 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7463     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   7464     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   7465     defined(BCM_56980_B0)
   7466     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM56960_A0r */
   7467         soc_block_list[61],
   7468         soc_iprocreg,
   7469         1,
   7470         0,
   7471         0x18021034,
   7472         0,
   7473         0,
   7474         3,
   7475         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM53400_A0r_fields,
   7476         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7477         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7478         -1,
   7479         -1,
   7480         3,
   7481     },
   7482 #endif /* chips */
   7483 
   7484 #if defined(BCM_88270_A0)
   7485     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88270_A0r */
   7486         soc_block_list[61],
   7487         soc_iprocreg,
   7488         1,
   7489         0,
   7490         0x18021034,
   7491         0,
   7492         0,
   7493         3,
   7494         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88270_A0r_fields,
   7495         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7496         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7497         -1,
   7498         -1,
   7499     },
   7500 #endif /* chips */
   7501 
   7502 #if defined(BCM_88375_A0)
   7503     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88375_A0r */
   7504         soc_block_list[61],
   7505         soc_iprocreg,
   7506         1,
   7507         0,
   7508         0x18021034,
   7509         0,
   7510         0,
   7511         3,
   7512         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88375_A0r_fields,
   7513         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7514         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7515         -1,
   7516         -1,
   7517     },
   7518 #endif /* chips */
   7519 
   7520 #if defined(BCM_88375_B0)
   7521     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88375_B0r */
   7522         soc_block_list[61],
   7523         soc_iprocreg,
   7524         1,
   7525         0,
   7526         0x18021034,
   7527         0,
   7528         0,
   7529         3,
   7530         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88375_B0r_fields,
   7531         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7532         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7533         -1,
   7534         -1,
   7535     },
   7536 #endif /* chips */
   7537 
   7538 #if defined(BCM_88470_A0)
   7539     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88470_A0r */
   7540         soc_block_list[61],
   7541         soc_iprocreg,
   7542         1,
   7543         0,
   7544         0x18021034,
   7545         0,
   7546         0,
   7547         3,
   7548         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88470_A0r_fields,
   7549         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7550         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7551         -1,
   7552         -1,
   7553     },
   7554 #endif /* chips */
   7555 
   7556 #if defined(BCM_88470_B0)
   7557     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88470_B0r */
   7558         soc_block_list[61],
   7559         soc_iprocreg,
   7560         1,
   7561         0,
   7562         0x18021034,
   7563         0,
   7564         0,
   7565         3,
   7566         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88470_B0r_fields,
   7567         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7568         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7569         -1,
   7570         -1,
   7571     },
   7572 #endif /* chips */
   7573 
   7574 #if defined(BCM_88675_B0)
   7575     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88675_B0r */
   7576         soc_block_list[61],
   7577         soc_iprocreg,
   7578         1,
   7579         0,
   7580         0x18021034,
   7581         0,
   7582         0,
   7583         3,
   7584         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88675_B0r_fields,
   7585         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7586         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7587         -1,
   7588         -1,
   7589     },
   7590 #endif /* chips */
   7591 
   7592 #if defined(BCM_88680_A0)
   7593     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88680_A0r */
   7594         soc_block_list[61],
   7595         soc_iprocreg,
   7596         1,
   7597         0,
   7598         0x18021034,
   7599         0,
   7600         0,
   7601         3,
   7602         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88680_A0r_fields,
   7603         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7604         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7605         -1,
   7606         -1,
   7607     },
   7608 #endif /* chips */
   7609 
   7610 #if defined(BCM_88690_A0)
   7611     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88690_A0r */
   7612         soc_block_list[61],
   7613         soc_iprocreg,
   7614         1,
   7615         0,
   7616         0x18021034,
   7617         0,
   7618         0,
   7619         3,
   7620         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88690_A0r_fields,
   7621         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7622         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7623         -1,
   7624         -1,
   7625     },
   7626 #endif /* chips */
   7627 
   7628 #if defined(BCM_88690_B0)
   7629     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88690_B0r */
   7630         soc_block_list[61],
   7631         soc_iprocreg,
   7632         1,
   7633         0,
   7634         0x18021034,
   7635         0,
   7636         0,
   7637         3,
   7638         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88690_B0r_fields,
   7639         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7640         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7641         -1,
   7642         -1,
   7643     },
   7644 #endif /* chips */
   7645 
   7646 #if defined(BCM_88790_A0)
   7647     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88790_A0r */
   7648         soc_block_list[61],
   7649         soc_iprocreg,
   7650         1,
   7651         0,
   7652         0x18021034,
   7653         0,
   7654         0,
   7655         3,
   7656         soc_QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BCM88790_A0r_fields,
   7657         SOC_RESET_VAL_DEC(0x0000000b, 0x00000000)
   7658         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7659         -1,
   7660         -1,
   7661     },
   7662 #endif /* chips */
   7663 
   7664 #if defined(BCM_88675_A0)
   7665     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLEr */
   7666         soc_block_list[61],
   7667         soc_iprocreg,
   7668         1,
   7669         0,
   7670         0x18021028,
   7671         0,
   7672         0,
   7673         2,
   7674         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLEr_fields,
   7675         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7676         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7677         -1,
   7678         -1,
   7679     },
   7680 #endif /* chips */
   7681 
   7682 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7683     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7684     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7685     defined(BCM_56260_B0)
   7686     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM53400_A0r */
   7687         soc_block_list[61],
   7688         soc_iprocreg,
   7689         1,
   7690         0,
   7691         0x18047028,
   7692         0,
   7693         0,
   7694         2,
   7695         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM53400_A0r_fields,
   7696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7698         -1,
   7699         -1,
   7700     },
   7701 #endif /* chips */
   7702 
   7703 #if defined(BCM_56370_A0)
   7704     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM56370_A0r */
   7705         soc_block_list[61],
   7706         soc_iprocreg,
   7707         1,
   7708         0,
   7709         0x15000028,
   7710         0,
   7711         0,
   7712         2,
   7713         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM53400_A0r_fields,
   7714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7715         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7716         -1,
   7717         -1,
   7718         3,
   7719     },
   7720 #endif /* chips */
   7721 
   7722 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   7723     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   7724     defined(BCM_56450_B1)
   7725     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM56450_A0r */
   7726         soc_block_list[61],
   7727         soc_iprocreg,
   7728         1,
   7729         0,
   7730         0x18027028,
   7731         0,
   7732         0,
   7733         2,
   7734         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM56450_A0r_fields,
   7735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7736         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7737         -1,
   7738         -1,
   7739     },
   7740 #endif /* chips */
   7741 
   7742 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   7743     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   7744     defined(BCM_56670_B0)
   7745     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM56560_A0r */
   7746         soc_block_list[61],
   7747         soc_iprocreg,
   7748         1,
   7749         0,
   7750         0x18021028,
   7751         0,
   7752         0,
   7753         2,
   7754         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM53400_A0r_fields,
   7755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7757         -1,
   7758         -1,
   7759     },
   7760 #endif /* chips */
   7761 
   7762 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   7763     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   7764     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   7765     defined(BCM_56980_B0)
   7766     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM56960_A0r */
   7767         soc_block_list[61],
   7768         soc_iprocreg,
   7769         1,
   7770         0,
   7771         0x18021028,
   7772         0,
   7773         0,
   7774         2,
   7775         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM53400_A0r_fields,
   7776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7778         -1,
   7779         -1,
   7780         3,
   7781     },
   7782 #endif /* chips */
   7783 
   7784 #if defined(BCM_88270_A0)
   7785     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88270_A0r */
   7786         soc_block_list[61],
   7787         soc_iprocreg,
   7788         1,
   7789         0,
   7790         0x18021028,
   7791         0,
   7792         0,
   7793         2,
   7794         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88270_A0r_fields,
   7795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7796         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7797         -1,
   7798         -1,
   7799     },
   7800 #endif /* chips */
   7801 
   7802 #if defined(BCM_88375_A0)
   7803     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88375_A0r */
   7804         soc_block_list[61],
   7805         soc_iprocreg,
   7806         1,
   7807         0,
   7808         0x18021028,
   7809         0,
   7810         0,
   7811         2,
   7812         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88375_A0r_fields,
   7813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7814         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7815         -1,
   7816         -1,
   7817     },
   7818 #endif /* chips */
   7819 
   7820 #if defined(BCM_88375_B0)
   7821     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88375_B0r */
   7822         soc_block_list[61],
   7823         soc_iprocreg,
   7824         1,
   7825         0,
   7826         0x18021028,
   7827         0,
   7828         0,
   7829         2,
   7830         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88375_B0r_fields,
   7831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7832         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7833         -1,
   7834         -1,
   7835     },
   7836 #endif /* chips */
   7837 
   7838 #if defined(BCM_88470_A0)
   7839     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88470_A0r */
   7840         soc_block_list[61],
   7841         soc_iprocreg,
   7842         1,
   7843         0,
   7844         0x18021028,
   7845         0,
   7846         0,
   7847         2,
   7848         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88470_A0r_fields,
   7849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7850         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7851         -1,
   7852         -1,
   7853     },
   7854 #endif /* chips */
   7855 
   7856 #if defined(BCM_88470_B0)
   7857     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88470_B0r */
   7858         soc_block_list[61],
   7859         soc_iprocreg,
   7860         1,
   7861         0,
   7862         0x18021028,
   7863         0,
   7864         0,
   7865         2,
   7866         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88470_B0r_fields,
   7867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7868         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7869         -1,
   7870         -1,
   7871     },
   7872 #endif /* chips */
   7873 
   7874 #if defined(BCM_88675_B0)
   7875     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88675_B0r */
   7876         soc_block_list[61],
   7877         soc_iprocreg,
   7878         1,
   7879         0,
   7880         0x18021028,
   7881         0,
   7882         0,
   7883         2,
   7884         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88675_B0r_fields,
   7885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7886         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7887         -1,
   7888         -1,
   7889     },
   7890 #endif /* chips */
   7891 
   7892 #if defined(BCM_88680_A0)
   7893     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88680_A0r */
   7894         soc_block_list[61],
   7895         soc_iprocreg,
   7896         1,
   7897         0,
   7898         0x18021028,
   7899         0,
   7900         0,
   7901         2,
   7902         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88680_A0r_fields,
   7903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7904         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7905         -1,
   7906         -1,
   7907     },
   7908 #endif /* chips */
   7909 
   7910 #if defined(BCM_88690_A0)
   7911     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88690_A0r */
   7912         soc_block_list[61],
   7913         soc_iprocreg,
   7914         1,
   7915         0,
   7916         0x18021028,
   7917         0,
   7918         0,
   7919         2,
   7920         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88690_A0r_fields,
   7921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7922         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7923         -1,
   7924         -1,
   7925     },
   7926 #endif /* chips */
   7927 
   7928 #if defined(BCM_88690_B0)
   7929     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88690_B0r */
   7930         soc_block_list[61],
   7931         soc_iprocreg,
   7932         1,
   7933         0,
   7934         0x18021028,
   7935         0,
   7936         0,
   7937         2,
   7938         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88690_B0r_fields,
   7939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7940         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7941         -1,
   7942         -1,
   7943     },
   7944 #endif /* chips */
   7945 
   7946 #if defined(BCM_88790_A0)
   7947     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88790_A0r */
   7948         soc_block_list[61],
   7949         soc_iprocreg,
   7950         1,
   7951         0,
   7952         0x18021028,
   7953         0,
   7954         0,
   7955         2,
   7956         soc_QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BCM88790_A0r_fields,
   7957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7958         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7959         -1,
   7960         -1,
   7961     },
   7962 #endif /* chips */
   7963 
   7964 #if defined(BCM_88675_A0)
   7965     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUSr */
   7966         soc_block_list[61],
   7967         soc_iprocreg,
   7968         1,
   7969         0,
   7970         0x18021010,
   7971         SOC_REG_FLAG_RO,
   7972         0,
   7973         3,
   7974         soc_QSPI_BSPI_REGISTERS_INTR_STATUSr_fields,
   7975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7976         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7977         -1,
   7978         -1,
   7979     },
   7980 #endif /* chips */
   7981 
   7982 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   7983     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   7984     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   7985     defined(BCM_56260_B0)
   7986     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM53400_A0r */
   7987         soc_block_list[61],
   7988         soc_iprocreg,
   7989         1,
   7990         0,
   7991         0x18047010,
   7992         SOC_REG_FLAG_RO,
   7993         0,
   7994         3,
   7995         soc_CMICM_BSPI_INTR_STATUS_BCM53400_A0r_fields,
   7996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7997         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7998         -1,
   7999         -1,
   8000     },
   8001 #endif /* chips */
   8002 
   8003 #if defined(BCM_56370_A0)
   8004     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM56370_A0r */
   8005         soc_block_list[61],
   8006         soc_iprocreg,
   8007         1,
   8008         0,
   8009         0x15000010,
   8010         SOC_REG_FLAG_RO,
   8011         0,
   8012         3,
   8013         soc_CMICM_BSPI_INTR_STATUS_BCM53400_A0r_fields,
   8014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8016         -1,
   8017         -1,
   8018         3,
   8019     },
   8020 #endif /* chips */
   8021 
   8022 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   8023     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   8024     defined(BCM_56450_B1)
   8025     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM56450_A0r */
   8026         soc_block_list[61],
   8027         soc_iprocreg,
   8028         1,
   8029         0,
   8030         0x18027010,
   8031         SOC_REG_FLAG_RO,
   8032         0,
   8033         3,
   8034         soc_CMICM_BSPI_INTR_STATUS_BCM56640_A0r_fields,
   8035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8036         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8037         -1,
   8038         -1,
   8039     },
   8040 #endif /* chips */
   8041 
   8042 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   8043     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   8044     defined(BCM_56670_B0)
   8045     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM56560_A0r */
   8046         soc_block_list[61],
   8047         soc_iprocreg,
   8048         1,
   8049         0,
   8050         0x18021010,
   8051         SOC_REG_FLAG_RO,
   8052         0,
   8053         3,
   8054         soc_CMICM_BSPI_INTR_STATUS_BCM53400_A0r_fields,
   8055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8056         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8057         -1,
   8058         -1,
   8059     },
   8060 #endif /* chips */
   8061 
   8062 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8063     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   8064     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   8065     defined(BCM_56980_B0)
   8066     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM56960_A0r */
   8067         soc_block_list[61],
   8068         soc_iprocreg,
   8069         1,
   8070         0,
   8071         0x18021010,
   8072         SOC_REG_FLAG_RO,
   8073         0,
   8074         3,
   8075         soc_CMICM_BSPI_INTR_STATUS_BCM53400_A0r_fields,
   8076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8078         -1,
   8079         -1,
   8080         3,
   8081     },
   8082 #endif /* chips */
   8083 
   8084 #if defined(BCM_88270_A0)
   8085     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88270_A0r */
   8086         soc_block_list[61],
   8087         soc_iprocreg,
   8088         1,
   8089         0,
   8090         0x18021010,
   8091         SOC_REG_FLAG_RO,
   8092         0,
   8093         3,
   8094         soc_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88270_A0r_fields,
   8095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8096         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8097         -1,
   8098         -1,
   8099     },
   8100 #endif /* chips */
   8101 
   8102 #if defined(BCM_88375_A0)
   8103     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88375_A0r */
   8104         soc_block_list[61],
   8105         soc_iprocreg,
   8106         1,
   8107         0,
   8108         0x18021010,
   8109         SOC_REG_FLAG_RO,
   8110         0,
   8111         3,
   8112         soc_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88375_A0r_fields,
   8113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8114         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8115         -1,
   8116         -1,
   8117     },
   8118 #endif /* chips */
   8119 
   8120 #if defined(BCM_88375_B0)
   8121     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88375_B0r */
   8122         soc_block_list[61],
   8123         soc_iprocreg,
   8124         1,
   8125         0,
   8126         0x18021010,
   8127         SOC_REG_FLAG_RO,
   8128         0,
   8129         3,
   8130         soc_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88375_B0r_fields,
   8131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8132         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8133         -1,
   8134         -1,
   8135     },
   8136 #endif /* chips */
   8137 
   8138 #if defined(BCM_88470_A0)
   8139     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88470_A0r */
   8140         soc_block_list[61],
   8141         soc_iprocreg,
   8142         1,
   8143         0,
   8144         0x18021010,
   8145         SOC_REG_FLAG_RO,
   8146         0,
   8147         3,
   8148         soc_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88470_A0r_fields,
   8149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8150         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8151         -1,
   8152         -1,
   8153     },
   8154 #endif /* chips */
   8155 
   8156 #if defined(BCM_88470_B0)
   8157     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88470_B0r */
   8158         soc_block_list[61],
   8159         soc_iprocreg,
   8160         1,
   8161         0,
   8162         0x18021010,
   8163         SOC_REG_FLAG_RO,
   8164         0,
   8165         3,
   8166         soc_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88470_B0r_fields,
   8167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8168         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8169         -1,
   8170         -1,
   8171     },
   8172 #endif /* chips */
   8173 
   8174 #if defined(BCM_88675_B0)
   8175     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88675_B0r */
   8176         soc_block_list[61],
   8177         soc_iprocreg,
   8178         1,
   8179         0,
   8180         0x18021010,
   8181         SOC_REG_FLAG_RO,
   8182         0,
   8183         3,
   8184         soc_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88675_B0r_fields,
   8185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8186         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8187         -1,
   8188         -1,
   8189     },
   8190 #endif /* chips */
   8191 
   8192 #if defined(BCM_88680_A0)
   8193     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88680_A0r */
   8194         soc_block_list[61],
   8195         soc_iprocreg,
   8196         1,
   8197         0,
   8198         0x18021010,
   8199         SOC_REG_FLAG_RO,
   8200         0,
   8201         3,
   8202         soc_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88680_A0r_fields,
   8203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8204         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8205         -1,
   8206         -1,
   8207     },
   8208 #endif /* chips */
   8209 
   8210 #if defined(BCM_88690_A0)
   8211     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88690_A0r */
   8212         soc_block_list[61],
   8213         soc_iprocreg,
   8214         1,
   8215         0,
   8216         0x18021010,
   8217         SOC_REG_FLAG_RO,
   8218         0,
   8219         3,
   8220         soc_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88690_A0r_fields,
   8221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8222         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8223         -1,
   8224         -1,
   8225     },
   8226 #endif /* chips */
   8227 
   8228 #if defined(BCM_88690_B0)
   8229     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88690_B0r */
   8230         soc_block_list[61],
   8231         soc_iprocreg,
   8232         1,
   8233         0,
   8234         0x18021010,
   8235         SOC_REG_FLAG_RO,
   8236         0,
   8237         3,
   8238         soc_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88690_B0r_fields,
   8239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8240         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8241         -1,
   8242         -1,
   8243     },
   8244 #endif /* chips */
   8245 
   8246 #if defined(BCM_88790_A0)
   8247     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88790_A0r */
   8248         soc_block_list[61],
   8249         soc_iprocreg,
   8250         1,
   8251         0,
   8252         0x18021010,
   8253         SOC_REG_FLAG_RO,
   8254         0,
   8255         3,
   8256         soc_QSPI_BSPI_REGISTERS_INTR_STATUS_BCM88790_A0r_fields,
   8257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8258         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8259         -1,
   8260         -1,
   8261     },
   8262 #endif /* chips */
   8263 
   8264 #if defined(BCM_88675_A0)
   8265     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRLr */
   8266         soc_block_list[61],
   8267         soc_iprocreg,
   8268         1,
   8269         0,
   8270         0x18021008,
   8271         0,
   8272         0,
   8273         2,
   8274         soc_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRLr_fields,
   8275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8276         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8277         -1,
   8278         -1,
   8279     },
   8280 #endif /* chips */
   8281 
   8282 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8283     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8284     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8285     defined(BCM_56260_B0)
   8286     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM53400_A0r */
   8287         soc_block_list[61],
   8288         soc_iprocreg,
   8289         1,
   8290         0,
   8291         0x18047008,
   8292         0,
   8293         0,
   8294         2,
   8295         soc_CMICM_BSPI_MAST_N_BOOT_BCM53400_A0r_fields,
   8296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8298         -1,
   8299         -1,
   8300     },
   8301 #endif /* chips */
   8302 
   8303 #if defined(BCM_56370_A0)
   8304     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM56370_A0r */
   8305         soc_block_list[61],
   8306         soc_iprocreg,
   8307         1,
   8308         0,
   8309         0x15000008,
   8310         0,
   8311         0,
   8312         2,
   8313         soc_CMICM_BSPI_MAST_N_BOOT_BCM53400_A0r_fields,
   8314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8315         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8316         -1,
   8317         -1,
   8318         3,
   8319     },
   8320 #endif /* chips */
   8321 
   8322 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   8323     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   8324     defined(BCM_56450_B1)
   8325     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM56450_A0r */
   8326         soc_block_list[61],
   8327         soc_iprocreg,
   8328         1,
   8329         0,
   8330         0x18027008,
   8331         0,
   8332         0,
   8333         2,
   8334         soc_CMICM_BSPI_MAST_N_BOOT_BCM56640_A0r_fields,
   8335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8336         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8337         -1,
   8338         -1,
   8339     },
   8340 #endif /* chips */
   8341 
   8342 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   8343     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   8344     defined(BCM_56670_B0)
   8345     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM56560_A0r */
   8346         soc_block_list[61],
   8347         soc_iprocreg,
   8348         1,
   8349         0,
   8350         0x18021008,
   8351         0,
   8352         0,
   8353         2,
   8354         soc_CMICM_BSPI_MAST_N_BOOT_BCM53400_A0r_fields,
   8355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8356         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8357         -1,
   8358         -1,
   8359     },
   8360 #endif /* chips */
   8361 
   8362 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8363     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   8364     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   8365     defined(BCM_56980_B0)
   8366     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM56960_A0r */
   8367         soc_block_list[61],
   8368         soc_iprocreg,
   8369         1,
   8370         0,
   8371         0x18021008,
   8372         0,
   8373         0,
   8374         2,
   8375         soc_CMICM_BSPI_MAST_N_BOOT_BCM53400_A0r_fields,
   8376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8377         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8378         -1,
   8379         -1,
   8380         3,
   8381     },
   8382 #endif /* chips */
   8383 
   8384 #if defined(BCM_88270_A0)
   8385     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88270_A0r */
   8386         soc_block_list[61],
   8387         soc_iprocreg,
   8388         1,
   8389         0,
   8390         0x18021008,
   8391         0,
   8392         0,
   8393         2,
   8394         soc_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88270_A0r_fields,
   8395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8396         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8397         -1,
   8398         -1,
   8399     },
   8400 #endif /* chips */
   8401 
   8402 #if defined(BCM_88375_A0)
   8403     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88375_A0r */
   8404         soc_block_list[61],
   8405         soc_iprocreg,
   8406         1,
   8407         0,
   8408         0x18021008,
   8409         0,
   8410         0,
   8411         2,
   8412         soc_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88375_A0r_fields,
   8413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8414         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8415         -1,
   8416         -1,
   8417     },
   8418 #endif /* chips */
   8419 
   8420 #if defined(BCM_88375_B0)
   8421     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88375_B0r */
   8422         soc_block_list[61],
   8423         soc_iprocreg,
   8424         1,
   8425         0,
   8426         0x18021008,
   8427         0,
   8428         0,
   8429         2,
   8430         soc_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88375_B0r_fields,
   8431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8433         -1,
   8434         -1,
   8435     },
   8436 #endif /* chips */
   8437 
   8438 #if defined(BCM_88470_A0)
   8439     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88470_A0r */
   8440         soc_block_list[61],
   8441         soc_iprocreg,
   8442         1,
   8443         0,
   8444         0x18021008,
   8445         0,
   8446         0,
   8447         2,
   8448         soc_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88470_A0r_fields,
   8449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8451         -1,
   8452         -1,
   8453     },
   8454 #endif /* chips */
   8455 
   8456 #if defined(BCM_88470_B0)
   8457     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88470_B0r */
   8458         soc_block_list[61],
   8459         soc_iprocreg,
   8460         1,
   8461         0,
   8462         0x18021008,
   8463         0,
   8464         0,
   8465         2,
   8466         soc_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88470_B0r_fields,
   8467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8469         -1,
   8470         -1,
   8471     },
   8472 #endif /* chips */
   8473 
   8474 #if defined(BCM_88675_B0)
   8475     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88675_B0r */
   8476         soc_block_list[61],
   8477         soc_iprocreg,
   8478         1,
   8479         0,
   8480         0x18021008,
   8481         0,
   8482         0,
   8483         2,
   8484         soc_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88675_B0r_fields,
   8485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8486         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8487         -1,
   8488         -1,
   8489     },
   8490 #endif /* chips */
   8491 
   8492 #if defined(BCM_88680_A0)
   8493     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88680_A0r */
   8494         soc_block_list[61],
   8495         soc_iprocreg,
   8496         1,
   8497         0,
   8498         0x18021008,
   8499         0,
   8500         0,
   8501         2,
   8502         soc_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88680_A0r_fields,
   8503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8504         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8505         -1,
   8506         -1,
   8507     },
   8508 #endif /* chips */
   8509 
   8510 #if defined(BCM_88690_A0)
   8511     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88690_A0r */
   8512         soc_block_list[61],
   8513         soc_iprocreg,
   8514         1,
   8515         0,
   8516         0x18021008,
   8517         0,
   8518         0,
   8519         2,
   8520         soc_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88690_A0r_fields,
   8521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8522         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8523         -1,
   8524         -1,
   8525     },
   8526 #endif /* chips */
   8527 
   8528 #if defined(BCM_88690_B0)
   8529     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88690_B0r */
   8530         soc_block_list[61],
   8531         soc_iprocreg,
   8532         1,
   8533         0,
   8534         0x18021008,
   8535         0,
   8536         0,
   8537         2,
   8538         soc_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88690_B0r_fields,
   8539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8540         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8541         -1,
   8542         -1,
   8543     },
   8544 #endif /* chips */
   8545 
   8546 #if defined(BCM_88790_A0)
   8547     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88790_A0r */
   8548         soc_block_list[61],
   8549         soc_iprocreg,
   8550         1,
   8551         0,
   8552         0x18021008,
   8553         0,
   8554         0,
   8555         2,
   8556         soc_QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BCM88790_A0r_fields,
   8557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8558         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8559         -1,
   8560         -1,
   8561     },
   8562 #endif /* chips */
   8563 
   8564 #if defined(BCM_88675_A0)
   8565     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_IDr */
   8566         soc_block_list[61],
   8567         soc_iprocreg,
   8568         1,
   8569         0,
   8570         0x18021000,
   8571         SOC_REG_FLAG_RO,
   8572         0,
   8573         3,
   8574         soc_QSPI_BSPI_REGISTERS_REVISION_IDr_fields,
   8575         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8576         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8577         -1,
   8578         -1,
   8579     },
   8580 #endif /* chips */
   8581 
   8582 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8583     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8584     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8585     defined(BCM_56260_B0)
   8586     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM53400_A0r */
   8587         soc_block_list[61],
   8588         soc_iprocreg,
   8589         1,
   8590         0,
   8591         0x18047000,
   8592         SOC_REG_FLAG_RO,
   8593         0,
   8594         3,
   8595         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM53400_A0r_fields,
   8596         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8597         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8598         -1,
   8599         -1,
   8600     },
   8601 #endif /* chips */
   8602 
   8603 #if defined(BCM_56370_A0)
   8604     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM56370_A0r */
   8605         soc_block_list[61],
   8606         soc_iprocreg,
   8607         1,
   8608         0,
   8609         0x15000000,
   8610         SOC_REG_FLAG_RO,
   8611         0,
   8612         3,
   8613         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM53400_A0r_fields,
   8614         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8615         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8616         -1,
   8617         -1,
   8618         3,
   8619     },
   8620 #endif /* chips */
   8621 
   8622 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   8623     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   8624     defined(BCM_56450_B1)
   8625     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM56450_A0r */
   8626         soc_block_list[61],
   8627         soc_iprocreg,
   8628         1,
   8629         0,
   8630         0x18027000,
   8631         SOC_REG_FLAG_RO,
   8632         0,
   8633         3,
   8634         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM56450_A0r_fields,
   8635         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8636         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8637         -1,
   8638         -1,
   8639     },
   8640 #endif /* chips */
   8641 
   8642 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   8643     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   8644     defined(BCM_56670_B0)
   8645     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM56560_A0r */
   8646         soc_block_list[61],
   8647         soc_iprocreg,
   8648         1,
   8649         0,
   8650         0x18021000,
   8651         SOC_REG_FLAG_RO,
   8652         0,
   8653         3,
   8654         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM53400_A0r_fields,
   8655         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8656         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8657         -1,
   8658         -1,
   8659     },
   8660 #endif /* chips */
   8661 
   8662 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8663     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   8664     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   8665     defined(BCM_56980_B0)
   8666     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM56960_A0r */
   8667         soc_block_list[61],
   8668         soc_iprocreg,
   8669         1,
   8670         0,
   8671         0x18021000,
   8672         SOC_REG_FLAG_RO,
   8673         0,
   8674         3,
   8675         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM53400_A0r_fields,
   8676         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8677         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8678         -1,
   8679         -1,
   8680         3,
   8681     },
   8682 #endif /* chips */
   8683 
   8684 #if defined(BCM_88270_A0)
   8685     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88270_A0r */
   8686         soc_block_list[61],
   8687         soc_iprocreg,
   8688         1,
   8689         0,
   8690         0x18021000,
   8691         SOC_REG_FLAG_RO,
   8692         0,
   8693         3,
   8694         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88270_A0r_fields,
   8695         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8696         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8697         -1,
   8698         -1,
   8699     },
   8700 #endif /* chips */
   8701 
   8702 #if defined(BCM_88375_A0)
   8703     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88375_A0r */
   8704         soc_block_list[61],
   8705         soc_iprocreg,
   8706         1,
   8707         0,
   8708         0x18021000,
   8709         SOC_REG_FLAG_RO,
   8710         0,
   8711         3,
   8712         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88375_A0r_fields,
   8713         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8714         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8715         -1,
   8716         -1,
   8717     },
   8718 #endif /* chips */
   8719 
   8720 #if defined(BCM_88375_B0)
   8721     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88375_B0r */
   8722         soc_block_list[61],
   8723         soc_iprocreg,
   8724         1,
   8725         0,
   8726         0x18021000,
   8727         SOC_REG_FLAG_RO,
   8728         0,
   8729         3,
   8730         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88375_B0r_fields,
   8731         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8732         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8733         -1,
   8734         -1,
   8735     },
   8736 #endif /* chips */
   8737 
   8738 #if defined(BCM_88470_A0)
   8739     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88470_A0r */
   8740         soc_block_list[61],
   8741         soc_iprocreg,
   8742         1,
   8743         0,
   8744         0x18021000,
   8745         SOC_REG_FLAG_RO,
   8746         0,
   8747         3,
   8748         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88470_A0r_fields,
   8749         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8750         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8751         -1,
   8752         -1,
   8753     },
   8754 #endif /* chips */
   8755 
   8756 #if defined(BCM_88470_B0)
   8757     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88470_B0r */
   8758         soc_block_list[61],
   8759         soc_iprocreg,
   8760         1,
   8761         0,
   8762         0x18021000,
   8763         SOC_REG_FLAG_RO,
   8764         0,
   8765         3,
   8766         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88470_B0r_fields,
   8767         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8768         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8769         -1,
   8770         -1,
   8771     },
   8772 #endif /* chips */
   8773 
   8774 #if defined(BCM_88675_B0)
   8775     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88675_B0r */
   8776         soc_block_list[61],
   8777         soc_iprocreg,
   8778         1,
   8779         0,
   8780         0x18021000,
   8781         SOC_REG_FLAG_RO,
   8782         0,
   8783         3,
   8784         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88675_B0r_fields,
   8785         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8786         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8787         -1,
   8788         -1,
   8789     },
   8790 #endif /* chips */
   8791 
   8792 #if defined(BCM_88680_A0)
   8793     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88680_A0r */
   8794         soc_block_list[61],
   8795         soc_iprocreg,
   8796         1,
   8797         0,
   8798         0x18021000,
   8799         SOC_REG_FLAG_RO,
   8800         0,
   8801         3,
   8802         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88680_A0r_fields,
   8803         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8804         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8805         -1,
   8806         -1,
   8807     },
   8808 #endif /* chips */
   8809 
   8810 #if defined(BCM_88690_A0)
   8811     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88690_A0r */
   8812         soc_block_list[61],
   8813         soc_iprocreg,
   8814         1,
   8815         0,
   8816         0x18021000,
   8817         SOC_REG_FLAG_RO,
   8818         0,
   8819         3,
   8820         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88690_A0r_fields,
   8821         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8822         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8823         -1,
   8824         -1,
   8825     },
   8826 #endif /* chips */
   8827 
   8828 #if defined(BCM_88690_B0)
   8829     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88690_B0r */
   8830         soc_block_list[61],
   8831         soc_iprocreg,
   8832         1,
   8833         0,
   8834         0x18021000,
   8835         SOC_REG_FLAG_RO,
   8836         0,
   8837         3,
   8838         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88690_B0r_fields,
   8839         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8840         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8841         -1,
   8842         -1,
   8843     },
   8844 #endif /* chips */
   8845 
   8846 #if defined(BCM_88790_A0)
   8847     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88790_A0r */
   8848         soc_block_list[61],
   8849         soc_iprocreg,
   8850         1,
   8851         0,
   8852         0x18021000,
   8853         SOC_REG_FLAG_RO,
   8854         0,
   8855         3,
   8856         soc_QSPI_BSPI_REGISTERS_REVISION_ID_BCM88790_A0r_fields,
   8857         SOC_RESET_VAL_DEC(0x00000401, 0x00000000)
   8858         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8859         -1,
   8860         -1,
   8861     },
   8862 #endif /* chips */
   8863 
   8864 #if defined(BCM_88675_A0)
   8865     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCHr */
   8866         soc_block_list[61],
   8867         soc_iprocreg,
   8868         1,
   8869         0,
   8870         0x18021004,
   8871         0,
   8872         0,
   8873         1,
   8874         soc_QSPI_BSPI_REGISTERS_SCRATCHr_fields,
   8875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8876         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8877         -1,
   8878         -1,
   8879     },
   8880 #endif /* chips */
   8881 
   8882 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   8883     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   8884     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   8885     defined(BCM_56260_B0)
   8886     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM53400_A0r */
   8887         soc_block_list[61],
   8888         soc_iprocreg,
   8889         1,
   8890         0,
   8891         0x18047004,
   8892         0,
   8893         0,
   8894         1,
   8895         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM53400_A0r_fields,
   8896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8898         -1,
   8899         -1,
   8900     },
   8901 #endif /* chips */
   8902 
   8903 #if defined(BCM_56370_A0)
   8904     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM56370_A0r */
   8905         soc_block_list[61],
   8906         soc_iprocreg,
   8907         1,
   8908         0,
   8909         0x15000004,
   8910         0,
   8911         0,
   8912         1,
   8913         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM53400_A0r_fields,
   8914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8916         -1,
   8917         -1,
   8918         3,
   8919     },
   8920 #endif /* chips */
   8921 
   8922 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   8923     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   8924     defined(BCM_56450_B1)
   8925     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM56450_A0r */
   8926         soc_block_list[61],
   8927         soc_iprocreg,
   8928         1,
   8929         0,
   8930         0x18027004,
   8931         0,
   8932         0,
   8933         1,
   8934         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM56450_A0r_fields,
   8935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8936         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8937         -1,
   8938         -1,
   8939     },
   8940 #endif /* chips */
   8941 
   8942 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   8943     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   8944     defined(BCM_56670_B0)
   8945     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM56560_A0r */
   8946         soc_block_list[61],
   8947         soc_iprocreg,
   8948         1,
   8949         0,
   8950         0x18021004,
   8951         0,
   8952         0,
   8953         1,
   8954         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM53400_A0r_fields,
   8955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8956         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8957         -1,
   8958         -1,
   8959     },
   8960 #endif /* chips */
   8961 
   8962 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   8963     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   8964     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   8965     defined(BCM_56980_B0)
   8966     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM56960_A0r */
   8967         soc_block_list[61],
   8968         soc_iprocreg,
   8969         1,
   8970         0,
   8971         0x18021004,
   8972         0,
   8973         0,
   8974         1,
   8975         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM53400_A0r_fields,
   8976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8977         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8978         -1,
   8979         -1,
   8980         3,
   8981     },
   8982 #endif /* chips */
   8983 
   8984 #if defined(BCM_88270_A0)
   8985     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM88270_A0r */
   8986         soc_block_list[61],
   8987         soc_iprocreg,
   8988         1,
   8989         0,
   8990         0x18021004,
   8991         0,
   8992         0,
   8993         1,
   8994         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM88270_A0r_fields,
   8995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8997         -1,
   8998         -1,
   8999     },
   9000 #endif /* chips */
   9001 
   9002 #if defined(BCM_88375_A0)
   9003     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM88375_A0r */
   9004         soc_block_list[61],
   9005         soc_iprocreg,
   9006         1,
   9007         0,
   9008         0x18021004,
   9009         0,
   9010         0,
   9011         1,
   9012         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM88375_A0r_fields,
   9013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9014         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9015         -1,
   9016         -1,
   9017     },
   9018 #endif /* chips */
   9019 
   9020 #if defined(BCM_88375_B0)
   9021     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM88375_B0r */
   9022         soc_block_list[61],
   9023         soc_iprocreg,
   9024         1,
   9025         0,
   9026         0x18021004,
   9027         0,
   9028         0,
   9029         1,
   9030         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM88375_B0r_fields,
   9031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9032         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9033         -1,
   9034         -1,
   9035     },
   9036 #endif /* chips */
   9037 
   9038 #if defined(BCM_88470_A0)
   9039     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM88470_A0r */
   9040         soc_block_list[61],
   9041         soc_iprocreg,
   9042         1,
   9043         0,
   9044         0x18021004,
   9045         0,
   9046         0,
   9047         1,
   9048         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM88470_A0r_fields,
   9049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9050         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9051         -1,
   9052         -1,
   9053     },
   9054 #endif /* chips */
   9055 
   9056 #if defined(BCM_88470_B0)
   9057     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM88470_B0r */
   9058         soc_block_list[61],
   9059         soc_iprocreg,
   9060         1,
   9061         0,
   9062         0x18021004,
   9063         0,
   9064         0,
   9065         1,
   9066         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM88470_B0r_fields,
   9067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9068         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9069         -1,
   9070         -1,
   9071     },
   9072 #endif /* chips */
   9073 
   9074 #if defined(BCM_88675_B0)
   9075     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM88675_B0r */
   9076         soc_block_list[61],
   9077         soc_iprocreg,
   9078         1,
   9079         0,
   9080         0x18021004,
   9081         0,
   9082         0,
   9083         1,
   9084         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM88675_B0r_fields,
   9085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9086         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9087         -1,
   9088         -1,
   9089     },
   9090 #endif /* chips */
   9091 
   9092 #if defined(BCM_88680_A0)
   9093     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM88680_A0r */
   9094         soc_block_list[61],
   9095         soc_iprocreg,
   9096         1,
   9097         0,
   9098         0x18021004,
   9099         0,
   9100         0,
   9101         1,
   9102         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM88680_A0r_fields,
   9103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9104         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9105         -1,
   9106         -1,
   9107     },
   9108 #endif /* chips */
   9109 
   9110 #if defined(BCM_88690_A0)
   9111     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM88690_A0r */
   9112         soc_block_list[61],
   9113         soc_iprocreg,
   9114         1,
   9115         0,
   9116         0x18021004,
   9117         0,
   9118         0,
   9119         1,
   9120         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM88690_A0r_fields,
   9121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9122         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9123         -1,
   9124         -1,
   9125     },
   9126 #endif /* chips */
   9127 
   9128 #if defined(BCM_88690_B0)
   9129     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM88690_B0r */
   9130         soc_block_list[61],
   9131         soc_iprocreg,
   9132         1,
   9133         0,
   9134         0x18021004,
   9135         0,
   9136         0,
   9137         1,
   9138         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM88690_B0r_fields,
   9139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9140         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9141         -1,
   9142         -1,
   9143     },
   9144 #endif /* chips */
   9145 
   9146 #if defined(BCM_88790_A0)
   9147     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_SCRATCH_BCM88790_A0r */
   9148         soc_block_list[61],
   9149         soc_iprocreg,
   9150         1,
   9151         0,
   9152         0x18021004,
   9153         0,
   9154         0,
   9155         1,
   9156         soc_QSPI_BSPI_REGISTERS_SCRATCH_BCM88790_A0r_fields,
   9157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9158         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9159         -1,
   9160         -1,
   9161     },
   9162 #endif /* chips */
   9163 
   9164 #if defined(BCM_88675_A0)
   9165     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRLr */
   9166         soc_block_list[61],
   9167         soc_iprocreg,
   9168         1,
   9169         0,
   9170         0x18021024,
   9171         0,
   9172         0,
   9173         6,
   9174         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRLr_fields,
   9175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9176         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9177         -1,
   9178         -1,
   9179     },
   9180 #endif /* chips */
   9181 
   9182 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   9183     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   9184     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
   9185     defined(BCM_56260_B0)
   9186     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM53400_A0r */
   9187         soc_block_list[61],
   9188         soc_iprocreg,
   9189         1,
   9190         0,
   9191         0x18047024,
   9192         0,
   9193         0,
   9194         6,
   9195         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM53400_A0r_fields,
   9196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9197         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9198         -1,
   9199         -1,
   9200     },
   9201 #endif /* chips */
   9202 
   9203 #if defined(BCM_56370_A0)
   9204     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM56370_A0r */
   9205         soc_block_list[61],
   9206         soc_iprocreg,
   9207         1,
   9208         0,
   9209         0x15000024,
   9210         0,
   9211         0,
   9212         7,
   9213         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM56870_A0r_fields,
   9214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9215         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9216         -1,
   9217         -1,
   9218         3,
   9219     },
   9220 #endif /* chips */
   9221 
   9222 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   9223     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   9224     defined(BCM_56450_B1)
   9225     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM56450_A0r */
   9226         soc_block_list[61],
   9227         soc_iprocreg,
   9228         1,
   9229         0,
   9230         0x18027024,
   9231         0,
   9232         0,
   9233         6,
   9234         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM56450_A0r_fields,
   9235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9236         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9237         -1,
   9238         -1,
   9239     },
   9240 #endif /* chips */
   9241 
   9242 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   9243     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   9244     defined(BCM_56670_B0)
   9245     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM56560_A0r */
   9246         soc_block_list[61],
   9247         soc_iprocreg,
   9248         1,
   9249         0,
   9250         0x18021024,
   9251         0,
   9252         0,
   9253         6,
   9254         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM53400_A0r_fields,
   9255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9256         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9257         -1,
   9258         -1,
   9259     },
   9260 #endif /* chips */
   9261 
   9262 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9263     defined(BCM_56980_A0) || defined(BCM_56980_B0)
   9264     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM56870_A0r */
   9265         soc_block_list[61],
   9266         soc_iprocreg,
   9267         1,
   9268         0,
   9269         0x18021024,
   9270         0,
   9271         0,
   9272         7,
   9273         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM56870_A0r_fields,
   9274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9276         -1,
   9277         -1,
   9278         3,
   9279     },
   9280 #endif /* chips */
   9281 
   9282 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   9283     defined(BCM_56970_A0)
   9284     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM56960_A0r */
   9285         soc_block_list[61],
   9286         soc_iprocreg,
   9287         1,
   9288         0,
   9289         0x18021024,
   9290         0,
   9291         0,
   9292         6,
   9293         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM53400_A0r_fields,
   9294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9295         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9296         -1,
   9297         -1,
   9298         3,
   9299     },
   9300 #endif /* chips */
   9301 
   9302 #if defined(BCM_88270_A0)
   9303     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88270_A0r */
   9304         soc_block_list[61],
   9305         soc_iprocreg,
   9306         1,
   9307         0,
   9308         0x18021024,
   9309         0,
   9310         0,
   9311         6,
   9312         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88270_A0r_fields,
   9313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9314         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9315         -1,
   9316         -1,
   9317     },
   9318 #endif /* chips */
   9319 
   9320 #if defined(BCM_88375_A0)
   9321     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88375_A0r */
   9322         soc_block_list[61],
   9323         soc_iprocreg,
   9324         1,
   9325         0,
   9326         0x18021024,
   9327         0,
   9328         0,
   9329         6,
   9330         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88375_A0r_fields,
   9331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9333         -1,
   9334         -1,
   9335     },
   9336 #endif /* chips */
   9337 
   9338 #if defined(BCM_88375_B0)
   9339     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88375_B0r */
   9340         soc_block_list[61],
   9341         soc_iprocreg,
   9342         1,
   9343         0,
   9344         0x18021024,
   9345         0,
   9346         0,
   9347         6,
   9348         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88375_B0r_fields,
   9349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9350         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9351         -1,
   9352         -1,
   9353     },
   9354 #endif /* chips */
   9355 
   9356 #if defined(BCM_88470_A0)
   9357     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88470_A0r */
   9358         soc_block_list[61],
   9359         soc_iprocreg,
   9360         1,
   9361         0,
   9362         0x18021024,
   9363         0,
   9364         0,
   9365         6,
   9366         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88470_A0r_fields,
   9367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9368         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9369         -1,
   9370         -1,
   9371     },
   9372 #endif /* chips */
   9373 
   9374 #if defined(BCM_88470_B0)
   9375     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88470_B0r */
   9376         soc_block_list[61],
   9377         soc_iprocreg,
   9378         1,
   9379         0,
   9380         0x18021024,
   9381         0,
   9382         0,
   9383         6,
   9384         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88470_B0r_fields,
   9385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9386         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9387         -1,
   9388         -1,
   9389     },
   9390 #endif /* chips */
   9391 
   9392 #if defined(BCM_88675_B0)
   9393     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88675_B0r */
   9394         soc_block_list[61],
   9395         soc_iprocreg,
   9396         1,
   9397         0,
   9398         0x18021024,
   9399         0,
   9400         0,
   9401         6,
   9402         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88675_B0r_fields,
   9403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9404         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9405         -1,
   9406         -1,
   9407     },
   9408 #endif /* chips */
   9409 
   9410 #if defined(BCM_88680_A0)
   9411     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88680_A0r */
   9412         soc_block_list[61],
   9413         soc_iprocreg,
   9414         1,
   9415         0,
   9416         0x18021024,
   9417         0,
   9418         0,
   9419         6,
   9420         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88680_A0r_fields,
   9421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9422         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9423         -1,
   9424         -1,
   9425     },
   9426 #endif /* chips */
   9427 
   9428 #if defined(BCM_88690_A0)
   9429     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88690_A0r */
   9430         soc_block_list[61],
   9431         soc_iprocreg,
   9432         1,
   9433         0,
   9434         0x18021024,
   9435         0,
   9436         0,
   9437         7,
   9438         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88690_A0r_fields,
   9439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9440         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9441         -1,
   9442         -1,
   9443     },
   9444 #endif /* chips */
   9445 
   9446 #if defined(BCM_88690_B0)
   9447     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88690_B0r */
   9448         soc_block_list[61],
   9449         soc_iprocreg,
   9450         1,
   9451         0,
   9452         0x18021024,
   9453         0,
   9454         0,
   9455         7,
   9456         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88690_B0r_fields,
   9457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9458         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9459         -1,
   9460         -1,
   9461     },
   9462 #endif /* chips */
   9463 
   9464 #if defined(BCM_88790_A0)
   9465     { /* SOC_REG_INT_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88790_A0r */
   9466         soc_block_list[61],
   9467         soc_iprocreg,
   9468         1,
   9469         0,
   9470         0x18021024,
   9471         0,
   9472         0,
   9473         7,
   9474         soc_QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BCM88790_A0r_fields,
   9475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9476         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9477         -1,
   9478         -1,
   9479     },
   9480 #endif /* chips */
   9481 
   9482 #if defined(BCM_88675_A0)
   9483     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSBr */
   9484         soc_block_list[61],
   9485         soc_iprocreg,
   9486         1,
   9487         0,
   9488         0x1811590c,
   9489         SOC_REG_FLAG_RO,
   9490         0,
   9491         1,
   9492         soc_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSBr_fields,
   9493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9494         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9495         -1,
   9496         -1,
   9497     },
   9498 #endif /* chips */
   9499 
   9500 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
   9501     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
   9502     defined(BCM_56260_B0)
   9503     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM53400_A0r */
   9504         soc_block_list[61],
   9505         soc_iprocreg,
   9506         1,
   9507         0,
   9508         0xf810690c,
   9509         SOC_REG_FLAG_RO,
   9510         0,
   9511         1,
   9512         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM53400_A0r_fields,
   9513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9514         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9515         -1,
   9516         -1,
   9517     },
   9518 #endif /* chips */
   9519 
   9520 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
   9521     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM56160_A0r */
   9522         soc_block_list[61],
   9523         soc_iprocreg,
   9524         1,
   9525         0,
   9526         0x1811f90c,
   9527         SOC_REG_FLAG_RO,
   9528         0,
   9529         1,
   9530         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM53400_A0r_fields,
   9531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9532         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9533         -1,
   9534         -1,
   9535     },
   9536 #endif /* chips */
   9537 
   9538 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   9539     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   9540     defined(BCM_56450_B1)
   9541     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM56450_A0r */
   9542         soc_block_list[61],
   9543         soc_iprocreg,
   9544         1,
   9545         0,
   9546         0x1811c90c,
   9547         SOC_REG_FLAG_RO,
   9548         0,
   9549         1,
   9550         soc_CMIC_CMC0_CCM_DMA_CUR_HOST0_ADDR_BCM56640_A0r_fields,
   9551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9552         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9553         -1,
   9554         -1,
   9555     },
   9556 #endif /* chips */
   9557 
   9558 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   9559     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   9560     defined(BCM_56670_B0)
   9561     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM56560_A0r */
   9562         soc_block_list[61],
   9563         soc_iprocreg,
   9564         1,
   9565         0,
   9566         0x1811590c,
   9567         SOC_REG_FLAG_RO,
   9568         0,
   9569         1,
   9570         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM53400_A0r_fields,
   9571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9572         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9573         -1,
   9574         -1,
   9575     },
   9576 #endif /* chips */
   9577 
   9578 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9579     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   9580     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   9581     defined(BCM_56980_B0)
   9582     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM56960_A0r */
   9583         soc_block_list[61],
   9584         soc_iprocreg,
   9585         1,
   9586         0,
   9587         0x1811590c,
   9588         SOC_REG_FLAG_RO,
   9589         0,
   9590         1,
   9591         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM53400_A0r_fields,
   9592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9593         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9594         -1,
   9595         -1,
   9596         3,
   9597     },
   9598 #endif /* chips */
   9599 
   9600 #if defined(BCM_88270_A0)
   9601     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88270_A0r */
   9602         soc_block_list[61],
   9603         soc_iprocreg,
   9604         1,
   9605         0,
   9606         0x1811590c,
   9607         SOC_REG_FLAG_RO,
   9608         0,
   9609         1,
   9610         soc_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88270_A0r_fields,
   9611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9612         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9613         -1,
   9614         -1,
   9615     },
   9616 #endif /* chips */
   9617 
   9618 #if defined(BCM_88375_A0)
   9619     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88375_A0r */
   9620         soc_block_list[61],
   9621         soc_iprocreg,
   9622         1,
   9623         0,
   9624         0x1811590c,
   9625         SOC_REG_FLAG_RO,
   9626         0,
   9627         1,
   9628         soc_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88375_A0r_fields,
   9629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9630         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9631         -1,
   9632         -1,
   9633     },
   9634 #endif /* chips */
   9635 
   9636 #if defined(BCM_88375_B0)
   9637     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88375_B0r */
   9638         soc_block_list[61],
   9639         soc_iprocreg,
   9640         1,
   9641         0,
   9642         0x1811590c,
   9643         SOC_REG_FLAG_RO,
   9644         0,
   9645         1,
   9646         soc_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88375_B0r_fields,
   9647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9648         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9649         -1,
   9650         -1,
   9651     },
   9652 #endif /* chips */
   9653 
   9654 #if defined(BCM_88470_A0)
   9655     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88470_A0r */
   9656         soc_block_list[61],
   9657         soc_iprocreg,
   9658         1,
   9659         0,
   9660         0x1811590c,
   9661         SOC_REG_FLAG_RO,
   9662         0,
   9663         1,
   9664         soc_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88470_A0r_fields,
   9665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9666         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9667         -1,
   9668         -1,
   9669     },
   9670 #endif /* chips */
   9671 
   9672 #if defined(BCM_88470_B0)
   9673     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88470_B0r */
   9674         soc_block_list[61],
   9675         soc_iprocreg,
   9676         1,
   9677         0,
   9678         0x1811590c,
   9679         SOC_REG_FLAG_RO,
   9680         0,
   9681         1,
   9682         soc_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88470_B0r_fields,
   9683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9685         -1,
   9686         -1,
   9687     },
   9688 #endif /* chips */
   9689 
   9690 #if defined(BCM_88675_B0)
   9691     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88675_B0r */
   9692         soc_block_list[61],
   9693         soc_iprocreg,
   9694         1,
   9695         0,
   9696         0x1811590c,
   9697         SOC_REG_FLAG_RO,
   9698         0,
   9699         1,
   9700         soc_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88675_B0r_fields,
   9701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9703         -1,
   9704         -1,
   9705     },
   9706 #endif /* chips */
   9707 
   9708 #if defined(BCM_88680_A0)
   9709     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88680_A0r */
   9710         soc_block_list[61],
   9711         soc_iprocreg,
   9712         1,
   9713         0,
   9714         0x1811590c,
   9715         SOC_REG_FLAG_RO,
   9716         0,
   9717         1,
   9718         soc_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88680_A0r_fields,
   9719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9720         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9721         -1,
   9722         -1,
   9723     },
   9724 #endif /* chips */
   9725 
   9726 #if defined(BCM_88690_A0)
   9727     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88690_A0r */
   9728         soc_block_list[61],
   9729         soc_iprocreg,
   9730         1,
   9731         0,
   9732         0x1811590c,
   9733         SOC_REG_FLAG_RO,
   9734         0,
   9735         1,
   9736         soc_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88690_A0r_fields,
   9737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9738         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9739         -1,
   9740         -1,
   9741     },
   9742 #endif /* chips */
   9743 
   9744 #if defined(BCM_88690_B0)
   9745     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88690_B0r */
   9746         soc_block_list[61],
   9747         soc_iprocreg,
   9748         1,
   9749         0,
   9750         0x1811590c,
   9751         SOC_REG_FLAG_RO,
   9752         0,
   9753         1,
   9754         soc_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88690_B0r_fields,
   9755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9757         -1,
   9758         -1,
   9759     },
   9760 #endif /* chips */
   9761 
   9762 #if defined(BCM_88790_A0)
   9763     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88790_A0r */
   9764         soc_block_list[61],
   9765         soc_iprocreg,
   9766         1,
   9767         0,
   9768         0x1811590c,
   9769         SOC_REG_FLAG_RO,
   9770         0,
   9771         1,
   9772         soc_QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM88790_A0r_fields,
   9773         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9774         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9775         -1,
   9776         -1,
   9777     },
   9778 #endif /* chips */
   9779 
   9780 #if defined(BCM_88675_A0)
   9781     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETEr */
   9782         soc_block_list[61],
   9783         soc_iprocreg,
   9784         1,
   9785         0,
   9786         0x18115904,
   9787         SOC_REG_FLAG_RO,
   9788         0,
   9789         3,
   9790         soc_QSPI_IDM_IDM_ERROR_LOG_COMPLETEr_fields,
   9791         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9792         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9793         -1,
   9794         -1,
   9795     },
   9796 #endif /* chips */
   9797 
   9798 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
   9799     defined(BCM_53570_B0) || defined(BCM_56260_A0)
   9800     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM53400_A0r */
   9801         soc_block_list[61],
   9802         soc_iprocreg,
   9803         1,
   9804         0,
   9805         0xf8106904,
   9806         SOC_REG_FLAG_RO,
   9807         0,
   9808         3,
   9809         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE_BCM53400_A0r_fields,
   9810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9811         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9812         -1,
   9813         -1,
   9814     },
   9815 #endif /* chips */
   9816 
   9817 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
   9818     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM56160_A0r */
   9819         soc_block_list[61],
   9820         soc_iprocreg,
   9821         1,
   9822         0,
   9823         0x1811f904,
   9824         SOC_REG_FLAG_RO,
   9825         0,
   9826         3,
   9827         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE_BCM53400_A0r_fields,
   9828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9829         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9830         -1,
   9831         -1,
   9832     },
   9833 #endif /* chips */
   9834 
   9835 #if defined(BCM_56260_B0)
   9836     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM56260_B0r */
   9837         soc_block_list[61],
   9838         soc_iprocreg,
   9839         1,
   9840         0,
   9841         0xf8106904,
   9842         0,
   9843         0,
   9844         3,
   9845         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE_BCM56260_B0r_fields,
   9846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9847         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9848         -1,
   9849         -1,
   9850     },
   9851 #endif /* chips */
   9852 
   9853 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
   9854     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   9855     defined(BCM_56450_B1)
   9856     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM56450_A0r */
   9857         soc_block_list[61],
   9858         soc_iprocreg,
   9859         1,
   9860         0,
   9861         0x1811c904,
   9862         SOC_REG_FLAG_RO,
   9863         0,
   9864         3,
   9865         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE_BCM56450_A0r_fields,
   9866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9867         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9868         -1,
   9869         -1,
   9870     },
   9871 #endif /* chips */
   9872 
   9873 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
   9874     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
   9875     defined(BCM_56670_B0)
   9876     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM56560_A0r */
   9877         soc_block_list[61],
   9878         soc_iprocreg,
   9879         1,
   9880         0,
   9881         0x18115904,
   9882         SOC_REG_FLAG_RO,
   9883         0,
   9884         3,
   9885         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE_BCM53400_A0r_fields,
   9886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9887         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9888         -1,
   9889         -1,
   9890     },
   9891 #endif /* chips */
   9892 
   9893 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
   9894     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
   9895     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
   9896     defined(BCM_56980_B0)
   9897     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM56960_A0r */
   9898         soc_block_list[61],
   9899         soc_iprocreg,
   9900         1,
   9901         0,
   9902         0x18115904,
   9903         SOC_REG_FLAG_RO,
   9904         0,
   9905         3,
   9906         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE_BCM53400_A0r_fields,
   9907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9908         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9909         -1,
   9910         -1,
   9911         3,
   9912     },
   9913 #endif /* chips */
   9914 
   9915 #if defined(BCM_88270_A0)
   9916     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88270_A0r */
   9917         soc_block_list[61],
   9918         soc_iprocreg,
   9919         1,
   9920         0,
   9921         0x18115904,
   9922         SOC_REG_FLAG_RO,
   9923         0,
   9924         3,
   9925         soc_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88270_A0r_fields,
   9926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9927         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9928         -1,
   9929         -1,
   9930     },
   9931 #endif /* chips */
   9932 
   9933 #if defined(BCM_88375_A0)
   9934     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88375_A0r */
   9935         soc_block_list[61],
   9936         soc_iprocreg,
   9937         1,
   9938         0,
   9939         0x18115904,
   9940         SOC_REG_FLAG_RO,
   9941         0,
   9942         3,
   9943         soc_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88375_A0r_fields,
   9944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9946         -1,
   9947         -1,
   9948     },
   9949 #endif /* chips */
   9950 
   9951 #if defined(BCM_88375_B0)
   9952     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88375_B0r */
   9953         soc_block_list[61],
   9954         soc_iprocreg,
   9955         1,
   9956         0,
   9957         0x18115904,
   9958         SOC_REG_FLAG_RO,
   9959         0,
   9960         3,
   9961         soc_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88375_B0r_fields,
   9962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9964         -1,
   9965         -1,
   9966     },
   9967 #endif /* chips */
   9968 
   9969 #if defined(BCM_88470_A0)
   9970     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88470_A0r */
   9971         soc_block_list[61],
   9972         soc_iprocreg,
   9973         1,
   9974         0,
   9975         0x18115904,
   9976         SOC_REG_FLAG_RO,
   9977         0,
   9978         3,
   9979         soc_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88470_A0r_fields,
   9980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9981         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9982         -1,
   9983         -1,
   9984     },
   9985 #endif /* chips */
   9986 
   9987 #if defined(BCM_88470_B0)
   9988     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88470_B0r */
   9989         soc_block_list[61],
   9990         soc_iprocreg,
   9991         1,
   9992         0,
   9993         0x18115904,
   9994         SOC_REG_FLAG_RO,
   9995         0,
   9996         3,
   9997         soc_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88470_B0r_fields,
   9998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9999         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10000         -1,
  10001         -1,
  10002     },
  10003 #endif /* chips */
  10004 
  10005 #if defined(BCM_88675_B0)
  10006     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88675_B0r */
  10007         soc_block_list[61],
  10008         soc_iprocreg,
  10009         1,
  10010         0,
  10011         0x18115904,
  10012         SOC_REG_FLAG_RO,
  10013         0,
  10014         3,
  10015         soc_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88675_B0r_fields,
  10016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10018         -1,
  10019         -1,
  10020     },
  10021 #endif /* chips */
  10022 
  10023 #if defined(BCM_88680_A0)
  10024     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88680_A0r */
  10025         soc_block_list[61],
  10026         soc_iprocreg,
  10027         1,
  10028         0,
  10029         0x18115904,
  10030         SOC_REG_FLAG_RO,
  10031         0,
  10032         3,
  10033         soc_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88680_A0r_fields,
  10034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10035         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10036         -1,
  10037         -1,
  10038     },
  10039 #endif /* chips */
  10040 
  10041 #if defined(BCM_88690_A0)
  10042     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88690_A0r */
  10043         soc_block_list[61],
  10044         soc_iprocreg,
  10045         1,
  10046         0,
  10047         0x18115904,
  10048         SOC_REG_FLAG_RO,
  10049         0,
  10050         3,
  10051         soc_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88690_A0r_fields,
  10052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10053         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10054         -1,
  10055         -1,
  10056     },
  10057 #endif /* chips */
  10058 
  10059 #if defined(BCM_88690_B0)
  10060     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88690_B0r */
  10061         soc_block_list[61],
  10062         soc_iprocreg,
  10063         1,
  10064         0,
  10065         0x18115904,
  10066         SOC_REG_FLAG_RO,
  10067         0,
  10068         3,
  10069         soc_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88690_B0r_fields,
  10070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10071         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10072         -1,
  10073         -1,
  10074     },
  10075 #endif /* chips */
  10076 
  10077 #if defined(BCM_88790_A0)
  10078     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88790_A0r */
  10079         soc_block_list[61],
  10080         soc_iprocreg,
  10081         1,
  10082         0,
  10083         0x18115904,
  10084         SOC_REG_FLAG_RO,
  10085         0,
  10086         3,
  10087         soc_QSPI_IDM_IDM_ERROR_LOG_COMPLETE_BCM88790_A0r_fields,
  10088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10089         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10090         -1,
  10091         -1,
  10092     },
  10093 #endif /* chips */
  10094 
  10095 #if defined(BCM_88675_A0)
  10096     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROLr */
  10097         soc_block_list[61],
  10098         soc_iprocreg,
  10099         1,
  10100         0,
  10101         0x18115900,
  10102         0,
  10103         0,
  10104         7,
  10105         soc_QSPI_IDM_IDM_ERROR_LOG_CONTROLr_fields,
  10106         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10107         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10108         -1,
  10109         -1,
  10110     },
  10111 #endif /* chips */
  10112 
  10113 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  10114     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
  10115     defined(BCM_56260_B0)
  10116     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM53400_A0r */
  10117         soc_block_list[61],
  10118         soc_iprocreg,
  10119         1,
  10120         0,
  10121         0xf8106900,
  10122         0,
  10123         0,
  10124         7,
  10125         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL_BCM53400_A0r_fields,
  10126         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10127         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10128         -1,
  10129         -1,
  10130     },
  10131 #endif /* chips */
  10132 
  10133 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  10134     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM56160_A0r */
  10135         soc_block_list[61],
  10136         soc_iprocreg,
  10137         1,
  10138         0,
  10139         0x1811f900,
  10140         0,
  10141         0,
  10142         7,
  10143         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL_BCM53400_A0r_fields,
  10144         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10145         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10146         -1,
  10147         -1,
  10148     },
  10149 #endif /* chips */
  10150 
  10151 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  10152     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10153     defined(BCM_56450_B1)
  10154     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM56450_A0r */
  10155         soc_block_list[61],
  10156         soc_iprocreg,
  10157         1,
  10158         0,
  10159         0x1811c900,
  10160         0,
  10161         0,
  10162         7,
  10163         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL_BCM56450_A0r_fields,
  10164         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10165         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10166         -1,
  10167         -1,
  10168     },
  10169 #endif /* chips */
  10170 
  10171 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  10172     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  10173     defined(BCM_56670_B0)
  10174     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM56560_A0r */
  10175         soc_block_list[61],
  10176         soc_iprocreg,
  10177         1,
  10178         0,
  10179         0x18115900,
  10180         0,
  10181         0,
  10182         7,
  10183         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL_BCM53400_A0r_fields,
  10184         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10186         -1,
  10187         -1,
  10188     },
  10189 #endif /* chips */
  10190 
  10191 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10192     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  10193     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  10194     defined(BCM_56980_B0)
  10195     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM56960_A0r */
  10196         soc_block_list[61],
  10197         soc_iprocreg,
  10198         1,
  10199         0,
  10200         0x18115900,
  10201         0,
  10202         0,
  10203         7,
  10204         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL_BCM53400_A0r_fields,
  10205         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10206         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10207         -1,
  10208         -1,
  10209         3,
  10210     },
  10211 #endif /* chips */
  10212 
  10213 #if defined(BCM_88270_A0)
  10214     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88270_A0r */
  10215         soc_block_list[61],
  10216         soc_iprocreg,
  10217         1,
  10218         0,
  10219         0x18115900,
  10220         0,
  10221         0,
  10222         7,
  10223         soc_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88270_A0r_fields,
  10224         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10225         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10226         -1,
  10227         -1,
  10228     },
  10229 #endif /* chips */
  10230 
  10231 #if defined(BCM_88375_A0)
  10232     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88375_A0r */
  10233         soc_block_list[61],
  10234         soc_iprocreg,
  10235         1,
  10236         0,
  10237         0x18115900,
  10238         0,
  10239         0,
  10240         7,
  10241         soc_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88375_A0r_fields,
  10242         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10243         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10244         -1,
  10245         -1,
  10246     },
  10247 #endif /* chips */
  10248 
  10249 #if defined(BCM_88375_B0)
  10250     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88375_B0r */
  10251         soc_block_list[61],
  10252         soc_iprocreg,
  10253         1,
  10254         0,
  10255         0x18115900,
  10256         0,
  10257         0,
  10258         7,
  10259         soc_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88375_B0r_fields,
  10260         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10261         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10262         -1,
  10263         -1,
  10264     },
  10265 #endif /* chips */
  10266 
  10267 #if defined(BCM_88470_A0)
  10268     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88470_A0r */
  10269         soc_block_list[61],
  10270         soc_iprocreg,
  10271         1,
  10272         0,
  10273         0x18115900,
  10274         0,
  10275         0,
  10276         7,
  10277         soc_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88470_A0r_fields,
  10278         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10279         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10280         -1,
  10281         -1,
  10282     },
  10283 #endif /* chips */
  10284 
  10285 #if defined(BCM_88470_B0)
  10286     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88470_B0r */
  10287         soc_block_list[61],
  10288         soc_iprocreg,
  10289         1,
  10290         0,
  10291         0x18115900,
  10292         0,
  10293         0,
  10294         7,
  10295         soc_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88470_B0r_fields,
  10296         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10298         -1,
  10299         -1,
  10300     },
  10301 #endif /* chips */
  10302 
  10303 #if defined(BCM_88675_B0)
  10304     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88675_B0r */
  10305         soc_block_list[61],
  10306         soc_iprocreg,
  10307         1,
  10308         0,
  10309         0x18115900,
  10310         0,
  10311         0,
  10312         7,
  10313         soc_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88675_B0r_fields,
  10314         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10315         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10316         -1,
  10317         -1,
  10318     },
  10319 #endif /* chips */
  10320 
  10321 #if defined(BCM_88680_A0)
  10322     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88680_A0r */
  10323         soc_block_list[61],
  10324         soc_iprocreg,
  10325         1,
  10326         0,
  10327         0x18115900,
  10328         0,
  10329         0,
  10330         7,
  10331         soc_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88680_A0r_fields,
  10332         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10333         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10334         -1,
  10335         -1,
  10336     },
  10337 #endif /* chips */
  10338 
  10339 #if defined(BCM_88690_A0)
  10340     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88690_A0r */
  10341         soc_block_list[61],
  10342         soc_iprocreg,
  10343         1,
  10344         0,
  10345         0x18115900,
  10346         0,
  10347         0,
  10348         7,
  10349         soc_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88690_A0r_fields,
  10350         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10351         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10352         -1,
  10353         -1,
  10354     },
  10355 #endif /* chips */
  10356 
  10357 #if defined(BCM_88690_B0)
  10358     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88690_B0r */
  10359         soc_block_list[61],
  10360         soc_iprocreg,
  10361         1,
  10362         0,
  10363         0x18115900,
  10364         0,
  10365         0,
  10366         7,
  10367         soc_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88690_B0r_fields,
  10368         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10369         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10370         -1,
  10371         -1,
  10372     },
  10373 #endif /* chips */
  10374 
  10375 #if defined(BCM_88790_A0)
  10376     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88790_A0r */
  10377         soc_block_list[61],
  10378         soc_iprocreg,
  10379         1,
  10380         0,
  10381         0x18115900,
  10382         0,
  10383         0,
  10384         7,
  10385         soc_QSPI_IDM_IDM_ERROR_LOG_CONTROL_BCM88790_A0r_fields,
  10386         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
  10387         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10388         -1,
  10389         -1,
  10390     },
  10391 #endif /* chips */
  10392 
  10393 #if defined(BCM_88675_A0)
  10394     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGSr */
  10395         soc_block_list[61],
  10396         soc_iprocreg,
  10397         1,
  10398         0,
  10399         0x1811591c,
  10400         SOC_REG_FLAG_RO,
  10401         0,
  10402         11,
  10403         soc_QSPI_IDM_IDM_ERROR_LOG_FLAGSr_fields,
  10404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10405         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10406         -1,
  10407         -1,
  10408     },
  10409 #endif /* chips */
  10410 
  10411 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  10412     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
  10413     defined(BCM_56260_B0)
  10414     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM53400_A0r */
  10415         soc_block_list[61],
  10416         soc_iprocreg,
  10417         1,
  10418         0,
  10419         0xf810691c,
  10420         SOC_REG_FLAG_RO,
  10421         0,
  10422         11,
  10423         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS_BCM53400_A0r_fields,
  10424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10425         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10426         -1,
  10427         -1,
  10428     },
  10429 #endif /* chips */
  10430 
  10431 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  10432     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM56160_A0r */
  10433         soc_block_list[61],
  10434         soc_iprocreg,
  10435         1,
  10436         0,
  10437         0x1811f91c,
  10438         SOC_REG_FLAG_RO,
  10439         0,
  10440         11,
  10441         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS_BCM53400_A0r_fields,
  10442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10444         -1,
  10445         -1,
  10446     },
  10447 #endif /* chips */
  10448 
  10449 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  10450     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10451     defined(BCM_56450_B1)
  10452     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM56450_A0r */
  10453         soc_block_list[61],
  10454         soc_iprocreg,
  10455         1,
  10456         0,
  10457         0x1811c91c,
  10458         SOC_REG_FLAG_RO,
  10459         0,
  10460         11,
  10461         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS_BCM56450_A0r_fields,
  10462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10463         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10464         -1,
  10465         -1,
  10466     },
  10467 #endif /* chips */
  10468 
  10469 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  10470     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  10471     defined(BCM_56670_B0)
  10472     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM56560_A0r */
  10473         soc_block_list[61],
  10474         soc_iprocreg,
  10475         1,
  10476         0,
  10477         0x1811591c,
  10478         SOC_REG_FLAG_RO,
  10479         0,
  10480         11,
  10481         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS_BCM53400_A0r_fields,
  10482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10483         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10484         -1,
  10485         -1,
  10486     },
  10487 #endif /* chips */
  10488 
  10489 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10490     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  10491     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  10492     defined(BCM_56980_B0)
  10493     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM56960_A0r */
  10494         soc_block_list[61],
  10495         soc_iprocreg,
  10496         1,
  10497         0,
  10498         0x1811591c,
  10499         SOC_REG_FLAG_RO,
  10500         0,
  10501         11,
  10502         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS_BCM53400_A0r_fields,
  10503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10504         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10505         -1,
  10506         -1,
  10507         3,
  10508     },
  10509 #endif /* chips */
  10510 
  10511 #if defined(BCM_88270_A0)
  10512     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88270_A0r */
  10513         soc_block_list[61],
  10514         soc_iprocreg,
  10515         1,
  10516         0,
  10517         0x1811591c,
  10518         SOC_REG_FLAG_RO,
  10519         0,
  10520         11,
  10521         soc_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88270_A0r_fields,
  10522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10523         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10524         -1,
  10525         -1,
  10526     },
  10527 #endif /* chips */
  10528 
  10529 #if defined(BCM_88375_A0)
  10530     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88375_A0r */
  10531         soc_block_list[61],
  10532         soc_iprocreg,
  10533         1,
  10534         0,
  10535         0x1811591c,
  10536         SOC_REG_FLAG_RO,
  10537         0,
  10538         11,
  10539         soc_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88375_A0r_fields,
  10540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10542         -1,
  10543         -1,
  10544     },
  10545 #endif /* chips */
  10546 
  10547 #if defined(BCM_88375_B0)
  10548     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88375_B0r */
  10549         soc_block_list[61],
  10550         soc_iprocreg,
  10551         1,
  10552         0,
  10553         0x1811591c,
  10554         SOC_REG_FLAG_RO,
  10555         0,
  10556         11,
  10557         soc_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88375_B0r_fields,
  10558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10559         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10560         -1,
  10561         -1,
  10562     },
  10563 #endif /* chips */
  10564 
  10565 #if defined(BCM_88470_A0)
  10566     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88470_A0r */
  10567         soc_block_list[61],
  10568         soc_iprocreg,
  10569         1,
  10570         0,
  10571         0x1811591c,
  10572         SOC_REG_FLAG_RO,
  10573         0,
  10574         11,
  10575         soc_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88470_A0r_fields,
  10576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10577         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10578         -1,
  10579         -1,
  10580     },
  10581 #endif /* chips */
  10582 
  10583 #if defined(BCM_88470_B0)
  10584     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88470_B0r */
  10585         soc_block_list[61],
  10586         soc_iprocreg,
  10587         1,
  10588         0,
  10589         0x1811591c,
  10590         SOC_REG_FLAG_RO,
  10591         0,
  10592         11,
  10593         soc_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88470_B0r_fields,
  10594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10596         -1,
  10597         -1,
  10598     },
  10599 #endif /* chips */
  10600 
  10601 #if defined(BCM_88675_B0)
  10602     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88675_B0r */
  10603         soc_block_list[61],
  10604         soc_iprocreg,
  10605         1,
  10606         0,
  10607         0x1811591c,
  10608         SOC_REG_FLAG_RO,
  10609         0,
  10610         11,
  10611         soc_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88675_B0r_fields,
  10612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10613         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10614         -1,
  10615         -1,
  10616     },
  10617 #endif /* chips */
  10618 
  10619 #if defined(BCM_88680_A0)
  10620     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88680_A0r */
  10621         soc_block_list[61],
  10622         soc_iprocreg,
  10623         1,
  10624         0,
  10625         0x1811591c,
  10626         SOC_REG_FLAG_RO,
  10627         0,
  10628         11,
  10629         soc_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88680_A0r_fields,
  10630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10631         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10632         -1,
  10633         -1,
  10634     },
  10635 #endif /* chips */
  10636 
  10637 #if defined(BCM_88690_A0)
  10638     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88690_A0r */
  10639         soc_block_list[61],
  10640         soc_iprocreg,
  10641         1,
  10642         0,
  10643         0x1811591c,
  10644         SOC_REG_FLAG_RO,
  10645         0,
  10646         11,
  10647         soc_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88690_A0r_fields,
  10648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10649         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10650         -1,
  10651         -1,
  10652     },
  10653 #endif /* chips */
  10654 
  10655 #if defined(BCM_88690_B0)
  10656     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88690_B0r */
  10657         soc_block_list[61],
  10658         soc_iprocreg,
  10659         1,
  10660         0,
  10661         0x1811591c,
  10662         SOC_REG_FLAG_RO,
  10663         0,
  10664         11,
  10665         soc_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88690_B0r_fields,
  10666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10667         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10668         -1,
  10669         -1,
  10670     },
  10671 #endif /* chips */
  10672 
  10673 #if defined(BCM_88790_A0)
  10674     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88790_A0r */
  10675         soc_block_list[61],
  10676         soc_iprocreg,
  10677         1,
  10678         0,
  10679         0x1811591c,
  10680         SOC_REG_FLAG_RO,
  10681         0,
  10682         11,
  10683         soc_QSPI_IDM_IDM_ERROR_LOG_FLAGS_BCM88790_A0r_fields,
  10684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10685         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10686         -1,
  10687         -1,
  10688     },
  10689 #endif /* chips */
  10690 
  10691 #if defined(BCM_88675_A0)
  10692     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_IDr */
  10693         soc_block_list[61],
  10694         soc_iprocreg,
  10695         1,
  10696         0,
  10697         0x18115914,
  10698         SOC_REG_FLAG_RO,
  10699         0,
  10700         2,
  10701         soc_QSPI_IDM_IDM_ERROR_LOG_IDr_fields,
  10702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10703         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10704         -1,
  10705         -1,
  10706     },
  10707 #endif /* chips */
  10708 
  10709 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  10710     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
  10711     defined(BCM_56260_B0)
  10712     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r */
  10713         soc_block_list[61],
  10714         soc_iprocreg,
  10715         1,
  10716         0,
  10717         0xf8106914,
  10718         SOC_REG_FLAG_RO,
  10719         0,
  10720         2,
  10721         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  10722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10723         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10724         -1,
  10725         -1,
  10726     },
  10727 #endif /* chips */
  10728 
  10729 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  10730     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM56160_A0r */
  10731         soc_block_list[61],
  10732         soc_iprocreg,
  10733         1,
  10734         0,
  10735         0x1811f914,
  10736         SOC_REG_FLAG_RO,
  10737         0,
  10738         2,
  10739         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  10740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10741         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10742         -1,
  10743         -1,
  10744     },
  10745 #endif /* chips */
  10746 
  10747 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  10748     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  10749     defined(BCM_56450_B1)
  10750     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM56450_A0r */
  10751         soc_block_list[61],
  10752         soc_iprocreg,
  10753         1,
  10754         0,
  10755         0x1811c914,
  10756         SOC_REG_FLAG_RO,
  10757         0,
  10758         2,
  10759         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM56450_A0r_fields,
  10760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10762         -1,
  10763         -1,
  10764     },
  10765 #endif /* chips */
  10766 
  10767 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  10768     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  10769     defined(BCM_56670_B0)
  10770     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM56560_A0r */
  10771         soc_block_list[61],
  10772         soc_iprocreg,
  10773         1,
  10774         0,
  10775         0x18115914,
  10776         SOC_REG_FLAG_RO,
  10777         0,
  10778         2,
  10779         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  10780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10781         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10782         -1,
  10783         -1,
  10784     },
  10785 #endif /* chips */
  10786 
  10787 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  10788     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  10789     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  10790     defined(BCM_56980_B0)
  10791     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM56960_A0r */
  10792         soc_block_list[61],
  10793         soc_iprocreg,
  10794         1,
  10795         0,
  10796         0x18115914,
  10797         SOC_REG_FLAG_RO,
  10798         0,
  10799         2,
  10800         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  10801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10802         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10803         -1,
  10804         -1,
  10805         3,
  10806     },
  10807 #endif /* chips */
  10808 
  10809 #if defined(BCM_88270_A0)
  10810     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88270_A0r */
  10811         soc_block_list[61],
  10812         soc_iprocreg,
  10813         1,
  10814         0,
  10815         0x18115914,
  10816         SOC_REG_FLAG_RO,
  10817         0,
  10818         2,
  10819         soc_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88270_A0r_fields,
  10820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10821         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10822         -1,
  10823         -1,
  10824     },
  10825 #endif /* chips */
  10826 
  10827 #if defined(BCM_88375_A0)
  10828     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88375_A0r */
  10829         soc_block_list[61],
  10830         soc_iprocreg,
  10831         1,
  10832         0,
  10833         0x18115914,
  10834         SOC_REG_FLAG_RO,
  10835         0,
  10836         2,
  10837         soc_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88375_A0r_fields,
  10838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10839         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10840         -1,
  10841         -1,
  10842     },
  10843 #endif /* chips */
  10844 
  10845 #if defined(BCM_88375_B0)
  10846     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88375_B0r */
  10847         soc_block_list[61],
  10848         soc_iprocreg,
  10849         1,
  10850         0,
  10851         0x18115914,
  10852         SOC_REG_FLAG_RO,
  10853         0,
  10854         2,
  10855         soc_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88375_B0r_fields,
  10856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10857         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10858         -1,
  10859         -1,
  10860     },
  10861 #endif /* chips */
  10862 
  10863 #if defined(BCM_88470_A0)
  10864     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88470_A0r */
  10865         soc_block_list[61],
  10866         soc_iprocreg,
  10867         1,
  10868         0,
  10869         0x18115914,
  10870         SOC_REG_FLAG_RO,
  10871         0,
  10872         2,
  10873         soc_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88470_A0r_fields,
  10874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10875         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10876         -1,
  10877         -1,
  10878     },
  10879 #endif /* chips */
  10880 
  10881 #if defined(BCM_88470_B0)
  10882     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88470_B0r */
  10883         soc_block_list[61],
  10884         soc_iprocreg,
  10885         1,
  10886         0,
  10887         0x18115914,
  10888         SOC_REG_FLAG_RO,
  10889         0,
  10890         2,
  10891         soc_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88470_B0r_fields,
  10892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10893         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10894         -1,
  10895         -1,
  10896     },
  10897 #endif /* chips */
  10898 
  10899 #if defined(BCM_88675_B0)
  10900     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88675_B0r */
  10901         soc_block_list[61],
  10902         soc_iprocreg,
  10903         1,
  10904         0,
  10905         0x18115914,
  10906         SOC_REG_FLAG_RO,
  10907         0,
  10908         2,
  10909         soc_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88675_B0r_fields,
  10910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10912         -1,
  10913         -1,
  10914     },
  10915 #endif /* chips */
  10916 
  10917 #if defined(BCM_88680_A0)
  10918     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88680_A0r */
  10919         soc_block_list[61],
  10920         soc_iprocreg,
  10921         1,
  10922         0,
  10923         0x18115914,
  10924         SOC_REG_FLAG_RO,
  10925         0,
  10926         2,
  10927         soc_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88680_A0r_fields,
  10928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10929         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10930         -1,
  10931         -1,
  10932     },
  10933 #endif /* chips */
  10934 
  10935 #if defined(BCM_88690_A0)
  10936     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88690_A0r */
  10937         soc_block_list[61],
  10938         soc_iprocreg,
  10939         1,
  10940         0,
  10941         0x18115914,
  10942         SOC_REG_FLAG_RO,
  10943         0,
  10944         2,
  10945         soc_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88690_A0r_fields,
  10946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10947         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10948         -1,
  10949         -1,
  10950     },
  10951 #endif /* chips */
  10952 
  10953 #if defined(BCM_88690_B0)
  10954     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88690_B0r */
  10955         soc_block_list[61],
  10956         soc_iprocreg,
  10957         1,
  10958         0,
  10959         0x18115914,
  10960         SOC_REG_FLAG_RO,
  10961         0,
  10962         2,
  10963         soc_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88690_B0r_fields,
  10964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10965         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10966         -1,
  10967         -1,
  10968     },
  10969 #endif /* chips */
  10970 
  10971 #if defined(BCM_88790_A0)
  10972     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88790_A0r */
  10973         soc_block_list[61],
  10974         soc_iprocreg,
  10975         1,
  10976         0,
  10977         0x18115914,
  10978         SOC_REG_FLAG_RO,
  10979         0,
  10980         2,
  10981         soc_QSPI_IDM_IDM_ERROR_LOG_ID_BCM88790_A0r_fields,
  10982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10983         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10984         -1,
  10985         -1,
  10986     },
  10987 #endif /* chips */
  10988 
  10989 #if defined(BCM_88675_A0)
  10990     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUSr */
  10991         soc_block_list[61],
  10992         soc_iprocreg,
  10993         1,
  10994         0,
  10995         0x18115908,
  10996         SOC_REG_FLAG_RO,
  10997         0,
  10998         3,
  10999         soc_QSPI_IDM_IDM_ERROR_LOG_STATUSr_fields,
  11000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11001         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11002         -1,
  11003         -1,
  11004     },
  11005 #endif /* chips */
  11006 
  11007 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  11008     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
  11009     defined(BCM_56260_B0)
  11010     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM53400_A0r */
  11011         soc_block_list[61],
  11012         soc_iprocreg,
  11013         1,
  11014         0,
  11015         0xf8106908,
  11016         SOC_REG_FLAG_RO,
  11017         0,
  11018         3,
  11019         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_BCM53400_A0r_fields,
  11020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11021         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11022         -1,
  11023         -1,
  11024     },
  11025 #endif /* chips */
  11026 
  11027 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  11028     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM56160_A0r */
  11029         soc_block_list[61],
  11030         soc_iprocreg,
  11031         1,
  11032         0,
  11033         0x1811f908,
  11034         SOC_REG_FLAG_RO,
  11035         0,
  11036         3,
  11037         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_BCM53400_A0r_fields,
  11038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11039         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11040         -1,
  11041         -1,
  11042     },
  11043 #endif /* chips */
  11044 
  11045 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  11046     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11047     defined(BCM_56450_B1)
  11048     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM56450_A0r */
  11049         soc_block_list[61],
  11050         soc_iprocreg,
  11051         1,
  11052         0,
  11053         0x1811c908,
  11054         SOC_REG_FLAG_RO,
  11055         0,
  11056         3,
  11057         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_BCM56450_A0r_fields,
  11058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11059         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11060         -1,
  11061         -1,
  11062     },
  11063 #endif /* chips */
  11064 
  11065 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  11066     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  11067     defined(BCM_56670_B0)
  11068     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM56560_A0r */
  11069         soc_block_list[61],
  11070         soc_iprocreg,
  11071         1,
  11072         0,
  11073         0x18115908,
  11074         SOC_REG_FLAG_RO,
  11075         0,
  11076         3,
  11077         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_BCM53400_A0r_fields,
  11078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11079         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11080         -1,
  11081         -1,
  11082     },
  11083 #endif /* chips */
  11084 
  11085 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11086     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  11087     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  11088     defined(BCM_56980_B0)
  11089     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM56960_A0r */
  11090         soc_block_list[61],
  11091         soc_iprocreg,
  11092         1,
  11093         0,
  11094         0x18115908,
  11095         SOC_REG_FLAG_RO,
  11096         0,
  11097         3,
  11098         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_BCM53400_A0r_fields,
  11099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11100         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11101         -1,
  11102         -1,
  11103         3,
  11104     },
  11105 #endif /* chips */
  11106 
  11107 #if defined(BCM_88270_A0)
  11108     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88270_A0r */
  11109         soc_block_list[61],
  11110         soc_iprocreg,
  11111         1,
  11112         0,
  11113         0x18115908,
  11114         SOC_REG_FLAG_RO,
  11115         0,
  11116         3,
  11117         soc_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88270_A0r_fields,
  11118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11119         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11120         -1,
  11121         -1,
  11122     },
  11123 #endif /* chips */
  11124 
  11125 #if defined(BCM_88375_A0)
  11126     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88375_A0r */
  11127         soc_block_list[61],
  11128         soc_iprocreg,
  11129         1,
  11130         0,
  11131         0x18115908,
  11132         SOC_REG_FLAG_RO,
  11133         0,
  11134         3,
  11135         soc_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88375_A0r_fields,
  11136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11138         -1,
  11139         -1,
  11140     },
  11141 #endif /* chips */
  11142 
  11143 #if defined(BCM_88375_B0)
  11144     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88375_B0r */
  11145         soc_block_list[61],
  11146         soc_iprocreg,
  11147         1,
  11148         0,
  11149         0x18115908,
  11150         SOC_REG_FLAG_RO,
  11151         0,
  11152         3,
  11153         soc_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88375_B0r_fields,
  11154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11156         -1,
  11157         -1,
  11158     },
  11159 #endif /* chips */
  11160 
  11161 #if defined(BCM_88470_A0)
  11162     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88470_A0r */
  11163         soc_block_list[61],
  11164         soc_iprocreg,
  11165         1,
  11166         0,
  11167         0x18115908,
  11168         SOC_REG_FLAG_RO,
  11169         0,
  11170         3,
  11171         soc_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88470_A0r_fields,
  11172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11173         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11174         -1,
  11175         -1,
  11176     },
  11177 #endif /* chips */
  11178 
  11179 #if defined(BCM_88470_B0)
  11180     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88470_B0r */
  11181         soc_block_list[61],
  11182         soc_iprocreg,
  11183         1,
  11184         0,
  11185         0x18115908,
  11186         SOC_REG_FLAG_RO,
  11187         0,
  11188         3,
  11189         soc_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88470_B0r_fields,
  11190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11191         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11192         -1,
  11193         -1,
  11194     },
  11195 #endif /* chips */
  11196 
  11197 #if defined(BCM_88675_B0)
  11198     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88675_B0r */
  11199         soc_block_list[61],
  11200         soc_iprocreg,
  11201         1,
  11202         0,
  11203         0x18115908,
  11204         SOC_REG_FLAG_RO,
  11205         0,
  11206         3,
  11207         soc_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88675_B0r_fields,
  11208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11209         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11210         -1,
  11211         -1,
  11212     },
  11213 #endif /* chips */
  11214 
  11215 #if defined(BCM_88680_A0)
  11216     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88680_A0r */
  11217         soc_block_list[61],
  11218         soc_iprocreg,
  11219         1,
  11220         0,
  11221         0x18115908,
  11222         SOC_REG_FLAG_RO,
  11223         0,
  11224         3,
  11225         soc_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88680_A0r_fields,
  11226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11227         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11228         -1,
  11229         -1,
  11230     },
  11231 #endif /* chips */
  11232 
  11233 #if defined(BCM_88690_A0)
  11234     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88690_A0r */
  11235         soc_block_list[61],
  11236         soc_iprocreg,
  11237         1,
  11238         0,
  11239         0x18115908,
  11240         SOC_REG_FLAG_RO,
  11241         0,
  11242         3,
  11243         soc_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88690_A0r_fields,
  11244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11246         -1,
  11247         -1,
  11248     },
  11249 #endif /* chips */
  11250 
  11251 #if defined(BCM_88690_B0)
  11252     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88690_B0r */
  11253         soc_block_list[61],
  11254         soc_iprocreg,
  11255         1,
  11256         0,
  11257         0x18115908,
  11258         SOC_REG_FLAG_RO,
  11259         0,
  11260         3,
  11261         soc_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88690_B0r_fields,
  11262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11264         -1,
  11265         -1,
  11266     },
  11267 #endif /* chips */
  11268 
  11269 #if defined(BCM_88790_A0)
  11270     { /* SOC_REG_INT_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88790_A0r */
  11271         soc_block_list[61],
  11272         soc_iprocreg,
  11273         1,
  11274         0,
  11275         0x18115908,
  11276         SOC_REG_FLAG_RO,
  11277         0,
  11278         3,
  11279         soc_QSPI_IDM_IDM_ERROR_LOG_STATUS_BCM88790_A0r_fields,
  11280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11281         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11282         -1,
  11283         -1,
  11284     },
  11285 #endif /* chips */
  11286 
  11287 #if defined(BCM_88675_A0)
  11288     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUSr */
  11289         soc_block_list[61],
  11290         soc_iprocreg,
  11291         1,
  11292         0,
  11293         0x18115a00,
  11294         SOC_REG_FLAG_RO,
  11295         0,
  11296         3,
  11297         soc_QSPI_IDM_IDM_INTERRUPT_STATUSr_fields,
  11298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11300         -1,
  11301         -1,
  11302     },
  11303 #endif /* chips */
  11304 
  11305 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  11306     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
  11307     defined(BCM_56260_B0)
  11308     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM53400_A0r */
  11309         soc_block_list[61],
  11310         soc_iprocreg,
  11311         1,
  11312         0,
  11313         0xf8106a00,
  11314         SOC_REG_FLAG_RO,
  11315         0,
  11316         3,
  11317         soc_A9JTAG_M0_IDM_IDM_INTERRUPT_STATUS_BCM53400_A0r_fields,
  11318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11319         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11320         -1,
  11321         -1,
  11322     },
  11323 #endif /* chips */
  11324 
  11325 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  11326     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11327     defined(BCM_56450_B1)
  11328     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM56450_A0r */
  11329         soc_block_list[61],
  11330         soc_iprocreg,
  11331         1,
  11332         0,
  11333         0x1811ca00,
  11334         SOC_REG_FLAG_RO,
  11335         0,
  11336         3,
  11337         soc_A9JTAG_M0_IDM_IDM_INTERRUPT_STATUS_BCM56450_A0r_fields,
  11338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11339         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11340         -1,
  11341         -1,
  11342     },
  11343 #endif /* chips */
  11344 
  11345 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11346     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  11347     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  11348     defined(BCM_56980_B0)
  11349     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM56960_A0r */
  11350         soc_block_list[61],
  11351         soc_iprocreg,
  11352         1,
  11353         0,
  11354         0x18115a00,
  11355         SOC_REG_FLAG_RO,
  11356         0,
  11357         3,
  11358         soc_A9JTAG_M0_IDM_IDM_INTERRUPT_STATUS_BCM53400_A0r_fields,
  11359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11360         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11361         -1,
  11362         -1,
  11363         3,
  11364     },
  11365 #endif /* chips */
  11366 
  11367 #if defined(BCM_88270_A0)
  11368     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88270_A0r */
  11369         soc_block_list[61],
  11370         soc_iprocreg,
  11371         1,
  11372         0,
  11373         0x18115a00,
  11374         SOC_REG_FLAG_RO,
  11375         0,
  11376         3,
  11377         soc_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88270_A0r_fields,
  11378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11379         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11380         -1,
  11381         -1,
  11382     },
  11383 #endif /* chips */
  11384 
  11385 #if defined(BCM_88375_A0)
  11386     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88375_A0r */
  11387         soc_block_list[61],
  11388         soc_iprocreg,
  11389         1,
  11390         0,
  11391         0x18115a00,
  11392         SOC_REG_FLAG_RO,
  11393         0,
  11394         3,
  11395         soc_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88375_A0r_fields,
  11396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11397         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11398         -1,
  11399         -1,
  11400     },
  11401 #endif /* chips */
  11402 
  11403 #if defined(BCM_88375_B0)
  11404     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88375_B0r */
  11405         soc_block_list[61],
  11406         soc_iprocreg,
  11407         1,
  11408         0,
  11409         0x18115a00,
  11410         SOC_REG_FLAG_RO,
  11411         0,
  11412         3,
  11413         soc_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88375_B0r_fields,
  11414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11416         -1,
  11417         -1,
  11418     },
  11419 #endif /* chips */
  11420 
  11421 #if defined(BCM_88470_A0)
  11422     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88470_A0r */
  11423         soc_block_list[61],
  11424         soc_iprocreg,
  11425         1,
  11426         0,
  11427         0x18115a00,
  11428         SOC_REG_FLAG_RO,
  11429         0,
  11430         3,
  11431         soc_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88470_A0r_fields,
  11432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11433         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11434         -1,
  11435         -1,
  11436     },
  11437 #endif /* chips */
  11438 
  11439 #if defined(BCM_88470_B0)
  11440     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88470_B0r */
  11441         soc_block_list[61],
  11442         soc_iprocreg,
  11443         1,
  11444         0,
  11445         0x18115a00,
  11446         SOC_REG_FLAG_RO,
  11447         0,
  11448         3,
  11449         soc_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88470_B0r_fields,
  11450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11451         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11452         -1,
  11453         -1,
  11454     },
  11455 #endif /* chips */
  11456 
  11457 #if defined(BCM_88675_B0)
  11458     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88675_B0r */
  11459         soc_block_list[61],
  11460         soc_iprocreg,
  11461         1,
  11462         0,
  11463         0x18115a00,
  11464         SOC_REG_FLAG_RO,
  11465         0,
  11466         3,
  11467         soc_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88675_B0r_fields,
  11468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11469         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11470         -1,
  11471         -1,
  11472     },
  11473 #endif /* chips */
  11474 
  11475 #if defined(BCM_88680_A0)
  11476     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88680_A0r */
  11477         soc_block_list[61],
  11478         soc_iprocreg,
  11479         1,
  11480         0,
  11481         0x18115a00,
  11482         SOC_REG_FLAG_RO,
  11483         0,
  11484         3,
  11485         soc_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88680_A0r_fields,
  11486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11487         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11488         -1,
  11489         -1,
  11490     },
  11491 #endif /* chips */
  11492 
  11493 #if defined(BCM_88690_A0)
  11494     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88690_A0r */
  11495         soc_block_list[61],
  11496         soc_iprocreg,
  11497         1,
  11498         0,
  11499         0x18115a00,
  11500         SOC_REG_FLAG_RO,
  11501         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  11502         3,
  11503         soc_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88690_A0r_fields,
  11504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11505         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11506         -1,
  11507         -1,
  11508     },
  11509 #endif /* chips */
  11510 
  11511 #if defined(BCM_88690_B0)
  11512     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88690_B0r */
  11513         soc_block_list[61],
  11514         soc_iprocreg,
  11515         1,
  11516         0,
  11517         0x18115a00,
  11518         SOC_REG_FLAG_RO,
  11519         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  11520         3,
  11521         soc_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88690_B0r_fields,
  11522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11523         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11524         -1,
  11525         -1,
  11526     },
  11527 #endif /* chips */
  11528 
  11529 #if defined(BCM_88790_A0)
  11530     { /* SOC_REG_INT_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88790_A0r */
  11531         soc_block_list[61],
  11532         soc_iprocreg,
  11533         1,
  11534         0,
  11535         0x18115a00,
  11536         SOC_REG_FLAG_RO,
  11537         0,
  11538         3,
  11539         soc_QSPI_IDM_IDM_INTERRUPT_STATUS_BCM88790_A0r_fields,
  11540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11542         -1,
  11543         -1,
  11544     },
  11545 #endif /* chips */
  11546 
  11547 #if defined(BCM_88675_A0)
  11548     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECTr */
  11549         soc_block_list[61],
  11550         soc_iprocreg,
  11551         1,
  11552         0,
  11553         0x18115408,
  11554         0,
  11555         0,
  11556         11,
  11557         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECTr_fields,
  11558         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11559         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11560         -1,
  11561         -1,
  11562     },
  11563 #endif /* chips */
  11564 
  11565 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  11566     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
  11567     defined(BCM_56260_B0)
  11568     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM53400_A0r */
  11569         soc_block_list[61],
  11570         soc_iprocreg,
  11571         1,
  11572         0,
  11573         0xf8106408,
  11574         0,
  11575         0,
  11576         11,
  11577         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM53400_A0r_fields,
  11578         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11579         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11580         -1,
  11581         -1,
  11582     },
  11583 #endif /* chips */
  11584 
  11585 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  11586     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM56160_A0r */
  11587         soc_block_list[61],
  11588         soc_iprocreg,
  11589         1,
  11590         0,
  11591         0x1811f408,
  11592         0,
  11593         0,
  11594         11,
  11595         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM53400_A0r_fields,
  11596         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11597         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11598         -1,
  11599         -1,
  11600     },
  11601 #endif /* chips */
  11602 
  11603 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  11604     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11605     defined(BCM_56450_B1)
  11606     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM56450_A0r */
  11607         soc_block_list[61],
  11608         soc_iprocreg,
  11609         1,
  11610         0,
  11611         0x1811c408,
  11612         0,
  11613         0,
  11614         10,
  11615         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM56450_A0r_fields,
  11616         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11617         SOC_RESET_MASK_DEC(0x000007fd, 0x00000000)
  11618         -1,
  11619         -1,
  11620     },
  11621 #endif /* chips */
  11622 
  11623 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  11624     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  11625     defined(BCM_56670_B0)
  11626     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM56560_A0r */
  11627         soc_block_list[61],
  11628         soc_iprocreg,
  11629         1,
  11630         0,
  11631         0x18115408,
  11632         0,
  11633         0,
  11634         11,
  11635         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM53400_A0r_fields,
  11636         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11637         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11638         -1,
  11639         -1,
  11640     },
  11641 #endif /* chips */
  11642 
  11643 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11644     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11645     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM56870_A0r */
  11646         soc_block_list[61],
  11647         soc_iprocreg,
  11648         1,
  11649         0,
  11650         0x18115408,
  11651         0,
  11652         0,
  11653         12,
  11654         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM56870_A0r_fields,
  11655         SOC_RESET_VAL_DEC(0x000019fc, 0x00000000)
  11656         SOC_RESET_MASK_DEC(0x00ff1ffc, 0x00000000)
  11657         -1,
  11658         -1,
  11659         3,
  11660     },
  11661 #endif /* chips */
  11662 
  11663 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  11664     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM56960_A0r */
  11665         soc_block_list[61],
  11666         soc_iprocreg,
  11667         1,
  11668         0,
  11669         0x18115408,
  11670         0,
  11671         0,
  11672         11,
  11673         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM53400_A0r_fields,
  11674         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11675         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11676         -1,
  11677         -1,
  11678         3,
  11679     },
  11680 #endif /* chips */
  11681 
  11682 #if defined(BCM_56970_A0)
  11683     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM56970_A0r */
  11684         soc_block_list[61],
  11685         soc_iprocreg,
  11686         1,
  11687         0,
  11688         0x18115408,
  11689         0,
  11690         0,
  11691         13,
  11692         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM56970_A0r_fields,
  11693         SOC_RESET_VAL_DEC(0x000009fd, 0x00000000)
  11694         SOC_RESET_MASK_DEC(0x00ff1ffd, 0x00000000)
  11695         -1,
  11696         -1,
  11697         3,
  11698     },
  11699 #endif /* chips */
  11700 
  11701 #if defined(BCM_88270_A0)
  11702     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88270_A0r */
  11703         soc_block_list[61],
  11704         soc_iprocreg,
  11705         1,
  11706         0,
  11707         0x18115408,
  11708         0,
  11709         0,
  11710         11,
  11711         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88270_A0r_fields,
  11712         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11713         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11714         -1,
  11715         -1,
  11716     },
  11717 #endif /* chips */
  11718 
  11719 #if defined(BCM_88375_A0)
  11720     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88375_A0r */
  11721         soc_block_list[61],
  11722         soc_iprocreg,
  11723         1,
  11724         0,
  11725         0x18115408,
  11726         0,
  11727         0,
  11728         11,
  11729         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88375_A0r_fields,
  11730         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11731         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11732         -1,
  11733         -1,
  11734     },
  11735 #endif /* chips */
  11736 
  11737 #if defined(BCM_88375_B0)
  11738     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88375_B0r */
  11739         soc_block_list[61],
  11740         soc_iprocreg,
  11741         1,
  11742         0,
  11743         0x18115408,
  11744         0,
  11745         0,
  11746         11,
  11747         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88375_B0r_fields,
  11748         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11749         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11750         -1,
  11751         -1,
  11752     },
  11753 #endif /* chips */
  11754 
  11755 #if defined(BCM_88470_A0)
  11756     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88470_A0r */
  11757         soc_block_list[61],
  11758         soc_iprocreg,
  11759         1,
  11760         0,
  11761         0x18115408,
  11762         0,
  11763         0,
  11764         11,
  11765         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88470_A0r_fields,
  11766         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11767         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11768         -1,
  11769         -1,
  11770     },
  11771 #endif /* chips */
  11772 
  11773 #if defined(BCM_88470_B0)
  11774     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88470_B0r */
  11775         soc_block_list[61],
  11776         soc_iprocreg,
  11777         1,
  11778         0,
  11779         0x18115408,
  11780         0,
  11781         0,
  11782         11,
  11783         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88470_B0r_fields,
  11784         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11785         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11786         -1,
  11787         -1,
  11788     },
  11789 #endif /* chips */
  11790 
  11791 #if defined(BCM_88675_B0)
  11792     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88675_B0r */
  11793         soc_block_list[61],
  11794         soc_iprocreg,
  11795         1,
  11796         0,
  11797         0x18115408,
  11798         0,
  11799         0,
  11800         11,
  11801         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88675_B0r_fields,
  11802         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11803         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11804         -1,
  11805         -1,
  11806     },
  11807 #endif /* chips */
  11808 
  11809 #if defined(BCM_88680_A0)
  11810     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88680_A0r */
  11811         soc_block_list[61],
  11812         soc_iprocreg,
  11813         1,
  11814         0,
  11815         0x18115408,
  11816         0,
  11817         0,
  11818         11,
  11819         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88680_A0r_fields,
  11820         SOC_RESET_VAL_DEC(0x000001fd, 0x00000000)
  11821         SOC_RESET_MASK_DEC(0x00ff07fd, 0x00000000)
  11822         -1,
  11823         -1,
  11824     },
  11825 #endif /* chips */
  11826 
  11827 #if defined(BCM_88690_A0)
  11828     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88690_A0r */
  11829         soc_block_list[61],
  11830         soc_iprocreg,
  11831         1,
  11832         0,
  11833         0x18115408,
  11834         0,
  11835         0,
  11836         12,
  11837         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88690_A0r_fields,
  11838         SOC_RESET_VAL_DEC(0x000019fc, 0x00000000)
  11839         SOC_RESET_MASK_DEC(0x00ff1ffc, 0x00000000)
  11840         -1,
  11841         -1,
  11842     },
  11843 #endif /* chips */
  11844 
  11845 #if defined(BCM_88690_B0)
  11846     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88690_B0r */
  11847         soc_block_list[61],
  11848         soc_iprocreg,
  11849         1,
  11850         0,
  11851         0x18115408,
  11852         0,
  11853         0,
  11854         12,
  11855         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88690_B0r_fields,
  11856         SOC_RESET_VAL_DEC(0x000019fc, 0x00000000)
  11857         SOC_RESET_MASK_DEC(0x00ff1ffc, 0x00000000)
  11858         -1,
  11859         -1,
  11860     },
  11861 #endif /* chips */
  11862 
  11863 #if defined(BCM_88790_A0)
  11864     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88790_A0r */
  11865         soc_block_list[61],
  11866         soc_iprocreg,
  11867         1,
  11868         0,
  11869         0x18115408,
  11870         0,
  11871         0,
  11872         12,
  11873         soc_QSPI_IDM_IDM_IO_CONTROL_DIRECT_BCM88790_A0r_fields,
  11874         SOC_RESET_VAL_DEC(0x000019fc, 0x00000000)
  11875         SOC_RESET_MASK_DEC(0x00ff1ffc, 0x00000000)
  11876         -1,
  11877         -1,
  11878     },
  11879 #endif /* chips */
  11880 
  11881 #if defined(BCM_88675_A0)
  11882     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUSr */
  11883         soc_block_list[61],
  11884         soc_iprocreg,
  11885         1,
  11886         0,
  11887         0x18115500,
  11888         SOC_REG_FLAG_RO,
  11889         0,
  11890         5,
  11891         soc_QSPI_IDM_IDM_IO_STATUSr_fields,
  11892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11893         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11894         -1,
  11895         -1,
  11896     },
  11897 #endif /* chips */
  11898 
  11899 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  11900     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
  11901     defined(BCM_56260_B0)
  11902     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM53400_A0r */
  11903         soc_block_list[61],
  11904         soc_iprocreg,
  11905         1,
  11906         0,
  11907         0xf8106500,
  11908         SOC_REG_FLAG_RO,
  11909         0,
  11910         5,
  11911         soc_QSPI_IDM_IDM_IO_STATUS_BCM53400_A0r_fields,
  11912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11913         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11914         -1,
  11915         -1,
  11916     },
  11917 #endif /* chips */
  11918 
  11919 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  11920     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM56160_A0r */
  11921         soc_block_list[61],
  11922         soc_iprocreg,
  11923         1,
  11924         0,
  11925         0x1811f500,
  11926         SOC_REG_FLAG_RO,
  11927         0,
  11928         5,
  11929         soc_QSPI_IDM_IDM_IO_STATUS_BCM53400_A0r_fields,
  11930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11931         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11932         -1,
  11933         -1,
  11934     },
  11935 #endif /* chips */
  11936 
  11937 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  11938     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  11939     defined(BCM_56450_B1)
  11940     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM56450_A0r */
  11941         soc_block_list[61],
  11942         soc_iprocreg,
  11943         1,
  11944         0,
  11945         0x1811c500,
  11946         SOC_REG_FLAG_RO,
  11947         0,
  11948         1,
  11949         soc_DDR_S2_IDM_IO_STATUSr_fields,
  11950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11952         -1,
  11953         -1,
  11954     },
  11955 #endif /* chips */
  11956 
  11957 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  11958     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  11959     defined(BCM_56670_B0)
  11960     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM56560_A0r */
  11961         soc_block_list[61],
  11962         soc_iprocreg,
  11963         1,
  11964         0,
  11965         0x18115500,
  11966         SOC_REG_FLAG_RO,
  11967         0,
  11968         5,
  11969         soc_QSPI_IDM_IDM_IO_STATUS_BCM53400_A0r_fields,
  11970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11971         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11972         -1,
  11973         -1,
  11974     },
  11975 #endif /* chips */
  11976 
  11977 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  11978     defined(BCM_56980_A0) || defined(BCM_56980_B0)
  11979     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM56870_A0r */
  11980         soc_block_list[61],
  11981         soc_iprocreg,
  11982         1,
  11983         0,
  11984         0x18115500,
  11985         SOC_REG_FLAG_RO,
  11986         0,
  11987         6,
  11988         soc_QSPI_IDM_IDM_IO_STATUS_BCM56870_A0r_fields,
  11989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11990         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11991         -1,
  11992         -1,
  11993         3,
  11994     },
  11995 #endif /* chips */
  11996 
  11997 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  11998     defined(BCM_56970_A0)
  11999     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM56960_A0r */
  12000         soc_block_list[61],
  12001         soc_iprocreg,
  12002         1,
  12003         0,
  12004         0x18115500,
  12005         SOC_REG_FLAG_RO,
  12006         0,
  12007         5,
  12008         soc_QSPI_IDM_IDM_IO_STATUS_BCM53400_A0r_fields,
  12009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12010         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12011         -1,
  12012         -1,
  12013         3,
  12014     },
  12015 #endif /* chips */
  12016 
  12017 #if defined(BCM_88270_A0)
  12018     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM88270_A0r */
  12019         soc_block_list[61],
  12020         soc_iprocreg,
  12021         1,
  12022         0,
  12023         0x18115500,
  12024         SOC_REG_FLAG_RO,
  12025         0,
  12026         5,
  12027         soc_QSPI_IDM_IDM_IO_STATUS_BCM88270_A0r_fields,
  12028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12029         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12030         -1,
  12031         -1,
  12032     },
  12033 #endif /* chips */
  12034 
  12035 #if defined(BCM_88375_A0)
  12036     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM88375_A0r */
  12037         soc_block_list[61],
  12038         soc_iprocreg,
  12039         1,
  12040         0,
  12041         0x18115500,
  12042         SOC_REG_FLAG_RO,
  12043         0,
  12044         5,
  12045         soc_QSPI_IDM_IDM_IO_STATUS_BCM88375_A0r_fields,
  12046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12047         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12048         -1,
  12049         -1,
  12050     },
  12051 #endif /* chips */
  12052 
  12053 #if defined(BCM_88375_B0)
  12054     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM88375_B0r */
  12055         soc_block_list[61],
  12056         soc_iprocreg,
  12057         1,
  12058         0,
  12059         0x18115500,
  12060         SOC_REG_FLAG_RO,
  12061         0,
  12062         5,
  12063         soc_QSPI_IDM_IDM_IO_STATUS_BCM88375_B0r_fields,
  12064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12065         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12066         -1,
  12067         -1,
  12068     },
  12069 #endif /* chips */
  12070 
  12071 #if defined(BCM_88470_A0)
  12072     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM88470_A0r */
  12073         soc_block_list[61],
  12074         soc_iprocreg,
  12075         1,
  12076         0,
  12077         0x18115500,
  12078         SOC_REG_FLAG_RO,
  12079         0,
  12080         5,
  12081         soc_QSPI_IDM_IDM_IO_STATUS_BCM88470_A0r_fields,
  12082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12083         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12084         -1,
  12085         -1,
  12086     },
  12087 #endif /* chips */
  12088 
  12089 #if defined(BCM_88470_B0)
  12090     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM88470_B0r */
  12091         soc_block_list[61],
  12092         soc_iprocreg,
  12093         1,
  12094         0,
  12095         0x18115500,
  12096         SOC_REG_FLAG_RO,
  12097         0,
  12098         5,
  12099         soc_QSPI_IDM_IDM_IO_STATUS_BCM88470_B0r_fields,
  12100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12101         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12102         -1,
  12103         -1,
  12104     },
  12105 #endif /* chips */
  12106 
  12107 #if defined(BCM_88675_B0)
  12108     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM88675_B0r */
  12109         soc_block_list[61],
  12110         soc_iprocreg,
  12111         1,
  12112         0,
  12113         0x18115500,
  12114         SOC_REG_FLAG_RO,
  12115         0,
  12116         5,
  12117         soc_QSPI_IDM_IDM_IO_STATUS_BCM88675_B0r_fields,
  12118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12119         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12120         -1,
  12121         -1,
  12122     },
  12123 #endif /* chips */
  12124 
  12125 #if defined(BCM_88680_A0)
  12126     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM88680_A0r */
  12127         soc_block_list[61],
  12128         soc_iprocreg,
  12129         1,
  12130         0,
  12131         0x18115500,
  12132         SOC_REG_FLAG_RO,
  12133         0,
  12134         5,
  12135         soc_QSPI_IDM_IDM_IO_STATUS_BCM88680_A0r_fields,
  12136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12138         -1,
  12139         -1,
  12140     },
  12141 #endif /* chips */
  12142 
  12143 #if defined(BCM_88690_A0)
  12144     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM88690_A0r */
  12145         soc_block_list[61],
  12146         soc_iprocreg,
  12147         1,
  12148         0,
  12149         0x18115500,
  12150         SOC_REG_FLAG_RO,
  12151         0,
  12152         6,
  12153         soc_QSPI_IDM_IDM_IO_STATUS_BCM88690_A0r_fields,
  12154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12156         -1,
  12157         -1,
  12158     },
  12159 #endif /* chips */
  12160 
  12161 #if defined(BCM_88690_B0)
  12162     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM88690_B0r */
  12163         soc_block_list[61],
  12164         soc_iprocreg,
  12165         1,
  12166         0,
  12167         0x18115500,
  12168         SOC_REG_FLAG_RO,
  12169         0,
  12170         6,
  12171         soc_QSPI_IDM_IDM_IO_STATUS_BCM88690_B0r_fields,
  12172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12173         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12174         -1,
  12175         -1,
  12176     },
  12177 #endif /* chips */
  12178 
  12179 #if defined(BCM_88790_A0)
  12180     { /* SOC_REG_INT_QSPI_IDM_IDM_IO_STATUS_BCM88790_A0r */
  12181         soc_block_list[61],
  12182         soc_iprocreg,
  12183         1,
  12184         0,
  12185         0x18115500,
  12186         SOC_REG_FLAG_RO,
  12187         0,
  12188         6,
  12189         soc_QSPI_IDM_IDM_IO_STATUS_BCM88790_A0r_fields,
  12190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12191         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12192         -1,
  12193         -1,
  12194     },
  12195 #endif /* chips */
  12196 
  12197 #if defined(BCM_88675_A0)
  12198     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROLr */
  12199         soc_block_list[61],
  12200         soc_iprocreg,
  12201         1,
  12202         0,
  12203         0x18115800,
  12204         0,
  12205         0,
  12206         2,
  12207         soc_QSPI_IDM_IDM_RESET_CONTROLr_fields,
  12208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12209         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12210         -1,
  12211         -1,
  12212     },
  12213 #endif /* chips */
  12214 
  12215 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  12216     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
  12217     defined(BCM_56260_B0)
  12218     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM53400_A0r */
  12219         soc_block_list[61],
  12220         soc_iprocreg,
  12221         1,
  12222         0,
  12223         0xf8106800,
  12224         0,
  12225         0,
  12226         2,
  12227         soc_A9JTAG_M0_IDM_RESET_CONTROL_BCM53400_A0r_fields,
  12228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12229         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12230         -1,
  12231         -1,
  12232     },
  12233 #endif /* chips */
  12234 
  12235 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  12236     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM56160_A0r */
  12237         soc_block_list[61],
  12238         soc_iprocreg,
  12239         1,
  12240         0,
  12241         0x1811f800,
  12242         0,
  12243         0,
  12244         2,
  12245         soc_A9JTAG_M0_IDM_RESET_CONTROL_BCM53400_A0r_fields,
  12246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12247         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12248         -1,
  12249         -1,
  12250     },
  12251 #endif /* chips */
  12252 
  12253 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  12254     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12255     defined(BCM_56450_B1)
  12256     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM56450_A0r */
  12257         soc_block_list[61],
  12258         soc_iprocreg,
  12259         1,
  12260         0,
  12261         0x1811c800,
  12262         0,
  12263         0,
  12264         2,
  12265         soc_A9JTAG_M0_IDM_RESET_CONTROL_BCM56450_A0r_fields,
  12266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12267         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12268         -1,
  12269         -1,
  12270     },
  12271 #endif /* chips */
  12272 
  12273 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  12274     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  12275     defined(BCM_56670_B0)
  12276     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM56560_A0r */
  12277         soc_block_list[61],
  12278         soc_iprocreg,
  12279         1,
  12280         0,
  12281         0x18115800,
  12282         0,
  12283         0,
  12284         2,
  12285         soc_A9JTAG_M0_IDM_RESET_CONTROL_BCM53400_A0r_fields,
  12286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12287         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12288         -1,
  12289         -1,
  12290     },
  12291 #endif /* chips */
  12292 
  12293 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12294     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  12295     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  12296     defined(BCM_56980_B0)
  12297     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM56960_A0r */
  12298         soc_block_list[61],
  12299         soc_iprocreg,
  12300         1,
  12301         0,
  12302         0x18115800,
  12303         0,
  12304         0,
  12305         2,
  12306         soc_A9JTAG_M0_IDM_RESET_CONTROL_BCM53400_A0r_fields,
  12307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12308         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12309         -1,
  12310         -1,
  12311         3,
  12312     },
  12313 #endif /* chips */
  12314 
  12315 #if defined(BCM_88270_A0)
  12316     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM88270_A0r */
  12317         soc_block_list[61],
  12318         soc_iprocreg,
  12319         1,
  12320         0,
  12321         0x18115800,
  12322         0,
  12323         0,
  12324         2,
  12325         soc_QSPI_IDM_IDM_RESET_CONTROL_BCM88270_A0r_fields,
  12326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12327         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12328         -1,
  12329         -1,
  12330     },
  12331 #endif /* chips */
  12332 
  12333 #if defined(BCM_88375_A0)
  12334     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM88375_A0r */
  12335         soc_block_list[61],
  12336         soc_iprocreg,
  12337         1,
  12338         0,
  12339         0x18115800,
  12340         0,
  12341         0,
  12342         2,
  12343         soc_QSPI_IDM_IDM_RESET_CONTROL_BCM88375_A0r_fields,
  12344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12346         -1,
  12347         -1,
  12348     },
  12349 #endif /* chips */
  12350 
  12351 #if defined(BCM_88375_B0)
  12352     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM88375_B0r */
  12353         soc_block_list[61],
  12354         soc_iprocreg,
  12355         1,
  12356         0,
  12357         0x18115800,
  12358         0,
  12359         0,
  12360         2,
  12361         soc_QSPI_IDM_IDM_RESET_CONTROL_BCM88375_B0r_fields,
  12362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12363         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12364         -1,
  12365         -1,
  12366     },
  12367 #endif /* chips */
  12368 
  12369 #if defined(BCM_88470_A0)
  12370     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM88470_A0r */
  12371         soc_block_list[61],
  12372         soc_iprocreg,
  12373         1,
  12374         0,
  12375         0x18115800,
  12376         0,
  12377         0,
  12378         2,
  12379         soc_QSPI_IDM_IDM_RESET_CONTROL_BCM88470_A0r_fields,
  12380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12382         -1,
  12383         -1,
  12384     },
  12385 #endif /* chips */
  12386 
  12387 #if defined(BCM_88470_B0)
  12388     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM88470_B0r */
  12389         soc_block_list[61],
  12390         soc_iprocreg,
  12391         1,
  12392         0,
  12393         0x18115800,
  12394         0,
  12395         0,
  12396         2,
  12397         soc_QSPI_IDM_IDM_RESET_CONTROL_BCM88470_B0r_fields,
  12398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12399         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12400         -1,
  12401         -1,
  12402     },
  12403 #endif /* chips */
  12404 
  12405 #if defined(BCM_88675_B0)
  12406     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM88675_B0r */
  12407         soc_block_list[61],
  12408         soc_iprocreg,
  12409         1,
  12410         0,
  12411         0x18115800,
  12412         0,
  12413         0,
  12414         2,
  12415         soc_QSPI_IDM_IDM_RESET_CONTROL_BCM88675_B0r_fields,
  12416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12418         -1,
  12419         -1,
  12420     },
  12421 #endif /* chips */
  12422 
  12423 #if defined(BCM_88680_A0)
  12424     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM88680_A0r */
  12425         soc_block_list[61],
  12426         soc_iprocreg,
  12427         1,
  12428         0,
  12429         0x18115800,
  12430         0,
  12431         0,
  12432         2,
  12433         soc_QSPI_IDM_IDM_RESET_CONTROL_BCM88680_A0r_fields,
  12434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12435         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12436         -1,
  12437         -1,
  12438     },
  12439 #endif /* chips */
  12440 
  12441 #if defined(BCM_88690_A0)
  12442     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM88690_A0r */
  12443         soc_block_list[61],
  12444         soc_iprocreg,
  12445         1,
  12446         0,
  12447         0x18115800,
  12448         0,
  12449         0,
  12450         2,
  12451         soc_QSPI_IDM_IDM_RESET_CONTROL_BCM88690_A0r_fields,
  12452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12454         -1,
  12455         -1,
  12456     },
  12457 #endif /* chips */
  12458 
  12459 #if defined(BCM_88690_B0)
  12460     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM88690_B0r */
  12461         soc_block_list[61],
  12462         soc_iprocreg,
  12463         1,
  12464         0,
  12465         0x18115800,
  12466         0,
  12467         0,
  12468         2,
  12469         soc_QSPI_IDM_IDM_RESET_CONTROL_BCM88690_B0r_fields,
  12470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12471         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12472         -1,
  12473         -1,
  12474     },
  12475 #endif /* chips */
  12476 
  12477 #if defined(BCM_88790_A0)
  12478     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_CONTROL_BCM88790_A0r */
  12479         soc_block_list[61],
  12480         soc_iprocreg,
  12481         1,
  12482         0,
  12483         0x18115800,
  12484         0,
  12485         0,
  12486         2,
  12487         soc_QSPI_IDM_IDM_RESET_CONTROL_BCM88790_A0r_fields,
  12488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12490         -1,
  12491         -1,
  12492     },
  12493 #endif /* chips */
  12494 
  12495 #if defined(BCM_88675_A0)
  12496     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_IDr */
  12497         soc_block_list[61],
  12498         soc_iprocreg,
  12499         1,
  12500         0,
  12501         0x18115808,
  12502         SOC_REG_FLAG_RO,
  12503         0,
  12504         2,
  12505         soc_QSPI_IDM_IDM_RESET_READ_IDr_fields,
  12506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12507         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12508         -1,
  12509         -1,
  12510     },
  12511 #endif /* chips */
  12512 
  12513 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  12514     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
  12515     defined(BCM_56260_B0)
  12516     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM53400_A0r */
  12517         soc_block_list[61],
  12518         soc_iprocreg,
  12519         1,
  12520         0,
  12521         0xf8106808,
  12522         SOC_REG_FLAG_RO,
  12523         0,
  12524         2,
  12525         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  12526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12527         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12528         -1,
  12529         -1,
  12530     },
  12531 #endif /* chips */
  12532 
  12533 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  12534     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM56160_A0r */
  12535         soc_block_list[61],
  12536         soc_iprocreg,
  12537         1,
  12538         0,
  12539         0x1811f808,
  12540         SOC_REG_FLAG_RO,
  12541         0,
  12542         2,
  12543         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  12544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12545         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12546         -1,
  12547         -1,
  12548     },
  12549 #endif /* chips */
  12550 
  12551 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  12552     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12553     defined(BCM_56450_B1)
  12554     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM56450_A0r */
  12555         soc_block_list[61],
  12556         soc_iprocreg,
  12557         1,
  12558         0,
  12559         0x1811c808,
  12560         SOC_REG_FLAG_RO,
  12561         0,
  12562         2,
  12563         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM56450_A0r_fields,
  12564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12565         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12566         -1,
  12567         -1,
  12568     },
  12569 #endif /* chips */
  12570 
  12571 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  12572     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  12573     defined(BCM_56670_B0)
  12574     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM56560_A0r */
  12575         soc_block_list[61],
  12576         soc_iprocreg,
  12577         1,
  12578         0,
  12579         0x18115808,
  12580         SOC_REG_FLAG_RO,
  12581         0,
  12582         2,
  12583         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  12584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12585         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12586         -1,
  12587         -1,
  12588     },
  12589 #endif /* chips */
  12590 
  12591 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12592     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  12593     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  12594     defined(BCM_56980_B0)
  12595     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM56960_A0r */
  12596         soc_block_list[61],
  12597         soc_iprocreg,
  12598         1,
  12599         0,
  12600         0x18115808,
  12601         SOC_REG_FLAG_RO,
  12602         0,
  12603         2,
  12604         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  12605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12606         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12607         -1,
  12608         -1,
  12609         3,
  12610     },
  12611 #endif /* chips */
  12612 
  12613 #if defined(BCM_88270_A0)
  12614     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM88270_A0r */
  12615         soc_block_list[61],
  12616         soc_iprocreg,
  12617         1,
  12618         0,
  12619         0x18115808,
  12620         SOC_REG_FLAG_RO,
  12621         0,
  12622         2,
  12623         soc_QSPI_IDM_IDM_RESET_READ_ID_BCM88270_A0r_fields,
  12624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12625         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12626         -1,
  12627         -1,
  12628     },
  12629 #endif /* chips */
  12630 
  12631 #if defined(BCM_88375_A0)
  12632     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM88375_A0r */
  12633         soc_block_list[61],
  12634         soc_iprocreg,
  12635         1,
  12636         0,
  12637         0x18115808,
  12638         SOC_REG_FLAG_RO,
  12639         0,
  12640         2,
  12641         soc_QSPI_IDM_IDM_RESET_READ_ID_BCM88375_A0r_fields,
  12642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12643         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12644         -1,
  12645         -1,
  12646     },
  12647 #endif /* chips */
  12648 
  12649 #if defined(BCM_88375_B0)
  12650     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM88375_B0r */
  12651         soc_block_list[61],
  12652         soc_iprocreg,
  12653         1,
  12654         0,
  12655         0x18115808,
  12656         SOC_REG_FLAG_RO,
  12657         0,
  12658         2,
  12659         soc_QSPI_IDM_IDM_RESET_READ_ID_BCM88375_B0r_fields,
  12660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12661         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12662         -1,
  12663         -1,
  12664     },
  12665 #endif /* chips */
  12666 
  12667 #if defined(BCM_88470_A0)
  12668     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM88470_A0r */
  12669         soc_block_list[61],
  12670         soc_iprocreg,
  12671         1,
  12672         0,
  12673         0x18115808,
  12674         SOC_REG_FLAG_RO,
  12675         0,
  12676         2,
  12677         soc_QSPI_IDM_IDM_RESET_READ_ID_BCM88470_A0r_fields,
  12678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12680         -1,
  12681         -1,
  12682     },
  12683 #endif /* chips */
  12684 
  12685 #if defined(BCM_88470_B0)
  12686     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM88470_B0r */
  12687         soc_block_list[61],
  12688         soc_iprocreg,
  12689         1,
  12690         0,
  12691         0x18115808,
  12692         SOC_REG_FLAG_RO,
  12693         0,
  12694         2,
  12695         soc_QSPI_IDM_IDM_RESET_READ_ID_BCM88470_B0r_fields,
  12696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12698         -1,
  12699         -1,
  12700     },
  12701 #endif /* chips */
  12702 
  12703 #if defined(BCM_88675_B0)
  12704     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM88675_B0r */
  12705         soc_block_list[61],
  12706         soc_iprocreg,
  12707         1,
  12708         0,
  12709         0x18115808,
  12710         SOC_REG_FLAG_RO,
  12711         0,
  12712         2,
  12713         soc_QSPI_IDM_IDM_RESET_READ_ID_BCM88675_B0r_fields,
  12714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12715         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12716         -1,
  12717         -1,
  12718     },
  12719 #endif /* chips */
  12720 
  12721 #if defined(BCM_88680_A0)
  12722     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM88680_A0r */
  12723         soc_block_list[61],
  12724         soc_iprocreg,
  12725         1,
  12726         0,
  12727         0x18115808,
  12728         SOC_REG_FLAG_RO,
  12729         0,
  12730         2,
  12731         soc_QSPI_IDM_IDM_RESET_READ_ID_BCM88680_A0r_fields,
  12732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12733         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12734         -1,
  12735         -1,
  12736     },
  12737 #endif /* chips */
  12738 
  12739 #if defined(BCM_88690_A0)
  12740     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM88690_A0r */
  12741         soc_block_list[61],
  12742         soc_iprocreg,
  12743         1,
  12744         0,
  12745         0x18115808,
  12746         SOC_REG_FLAG_RO,
  12747         0,
  12748         2,
  12749         soc_QSPI_IDM_IDM_RESET_READ_ID_BCM88690_A0r_fields,
  12750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12751         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12752         -1,
  12753         -1,
  12754     },
  12755 #endif /* chips */
  12756 
  12757 #if defined(BCM_88690_B0)
  12758     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM88690_B0r */
  12759         soc_block_list[61],
  12760         soc_iprocreg,
  12761         1,
  12762         0,
  12763         0x18115808,
  12764         SOC_REG_FLAG_RO,
  12765         0,
  12766         2,
  12767         soc_QSPI_IDM_IDM_RESET_READ_ID_BCM88690_B0r_fields,
  12768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12769         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12770         -1,
  12771         -1,
  12772     },
  12773 #endif /* chips */
  12774 
  12775 #if defined(BCM_88790_A0)
  12776     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_READ_ID_BCM88790_A0r */
  12777         soc_block_list[61],
  12778         soc_iprocreg,
  12779         1,
  12780         0,
  12781         0x18115808,
  12782         SOC_REG_FLAG_RO,
  12783         0,
  12784         2,
  12785         soc_QSPI_IDM_IDM_RESET_READ_ID_BCM88790_A0r_fields,
  12786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12787         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12788         -1,
  12789         -1,
  12790     },
  12791 #endif /* chips */
  12792 
  12793 #if defined(BCM_88675_A0)
  12794     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUSr */
  12795         soc_block_list[61],
  12796         soc_iprocreg,
  12797         1,
  12798         0,
  12799         0x18115804,
  12800         SOC_REG_FLAG_RO,
  12801         0,
  12802         5,
  12803         soc_QSPI_IDM_IDM_RESET_STATUSr_fields,
  12804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12805         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12806         -1,
  12807         -1,
  12808     },
  12809 #endif /* chips */
  12810 
  12811 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  12812     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
  12813     defined(BCM_56260_B0)
  12814     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM53400_A0r */
  12815         soc_block_list[61],
  12816         soc_iprocreg,
  12817         1,
  12818         0,
  12819         0xf8106804,
  12820         SOC_REG_FLAG_RO,
  12821         0,
  12822         5,
  12823         soc_A9JTAG_M0_IDM_IDM_RESET_STATUS_BCM53400_A0r_fields,
  12824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12825         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12826         -1,
  12827         -1,
  12828     },
  12829 #endif /* chips */
  12830 
  12831 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  12832     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  12833     defined(BCM_56450_B1)
  12834     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM56450_A0r */
  12835         soc_block_list[61],
  12836         soc_iprocreg,
  12837         1,
  12838         0,
  12839         0x1811c804,
  12840         SOC_REG_FLAG_RO,
  12841         0,
  12842         5,
  12843         soc_A9JTAG_M0_IDM_IDM_RESET_STATUS_BCM56450_A0r_fields,
  12844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12845         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12846         -1,
  12847         -1,
  12848     },
  12849 #endif /* chips */
  12850 
  12851 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  12852     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  12853     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  12854     defined(BCM_56980_B0)
  12855     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM56960_A0r */
  12856         soc_block_list[61],
  12857         soc_iprocreg,
  12858         1,
  12859         0,
  12860         0x18115804,
  12861         SOC_REG_FLAG_RO,
  12862         0,
  12863         5,
  12864         soc_A9JTAG_M0_IDM_IDM_RESET_STATUS_BCM53400_A0r_fields,
  12865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12866         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12867         -1,
  12868         -1,
  12869         3,
  12870     },
  12871 #endif /* chips */
  12872 
  12873 #if defined(BCM_88270_A0)
  12874     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM88270_A0r */
  12875         soc_block_list[61],
  12876         soc_iprocreg,
  12877         1,
  12878         0,
  12879         0x18115804,
  12880         SOC_REG_FLAG_RO,
  12881         0,
  12882         5,
  12883         soc_QSPI_IDM_IDM_RESET_STATUS_BCM88270_A0r_fields,
  12884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12885         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12886         -1,
  12887         -1,
  12888     },
  12889 #endif /* chips */
  12890 
  12891 #if defined(BCM_88375_A0)
  12892     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM88375_A0r */
  12893         soc_block_list[61],
  12894         soc_iprocreg,
  12895         1,
  12896         0,
  12897         0x18115804,
  12898         SOC_REG_FLAG_RO,
  12899         0,
  12900         5,
  12901         soc_QSPI_IDM_IDM_RESET_STATUS_BCM88375_A0r_fields,
  12902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12903         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12904         -1,
  12905         -1,
  12906     },
  12907 #endif /* chips */
  12908 
  12909 #if defined(BCM_88375_B0)
  12910     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM88375_B0r */
  12911         soc_block_list[61],
  12912         soc_iprocreg,
  12913         1,
  12914         0,
  12915         0x18115804,
  12916         SOC_REG_FLAG_RO,
  12917         0,
  12918         5,
  12919         soc_QSPI_IDM_IDM_RESET_STATUS_BCM88375_B0r_fields,
  12920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12921         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12922         -1,
  12923         -1,
  12924     },
  12925 #endif /* chips */
  12926 
  12927 #if defined(BCM_88470_A0)
  12928     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM88470_A0r */
  12929         soc_block_list[61],
  12930         soc_iprocreg,
  12931         1,
  12932         0,
  12933         0x18115804,
  12934         SOC_REG_FLAG_RO,
  12935         0,
  12936         5,
  12937         soc_QSPI_IDM_IDM_RESET_STATUS_BCM88470_A0r_fields,
  12938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12939         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12940         -1,
  12941         -1,
  12942     },
  12943 #endif /* chips */
  12944 
  12945 #if defined(BCM_88470_B0)
  12946     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM88470_B0r */
  12947         soc_block_list[61],
  12948         soc_iprocreg,
  12949         1,
  12950         0,
  12951         0x18115804,
  12952         SOC_REG_FLAG_RO,
  12953         0,
  12954         5,
  12955         soc_QSPI_IDM_IDM_RESET_STATUS_BCM88470_B0r_fields,
  12956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12957         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12958         -1,
  12959         -1,
  12960     },
  12961 #endif /* chips */
  12962 
  12963 #if defined(BCM_88675_B0)
  12964     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM88675_B0r */
  12965         soc_block_list[61],
  12966         soc_iprocreg,
  12967         1,
  12968         0,
  12969         0x18115804,
  12970         SOC_REG_FLAG_RO,
  12971         0,
  12972         5,
  12973         soc_QSPI_IDM_IDM_RESET_STATUS_BCM88675_B0r_fields,
  12974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12975         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12976         -1,
  12977         -1,
  12978     },
  12979 #endif /* chips */
  12980 
  12981 #if defined(BCM_88680_A0)
  12982     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM88680_A0r */
  12983         soc_block_list[61],
  12984         soc_iprocreg,
  12985         1,
  12986         0,
  12987         0x18115804,
  12988         SOC_REG_FLAG_RO,
  12989         0,
  12990         5,
  12991         soc_QSPI_IDM_IDM_RESET_STATUS_BCM88680_A0r_fields,
  12992         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12993         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12994         -1,
  12995         -1,
  12996     },
  12997 #endif /* chips */
  12998 
  12999 #if defined(BCM_88690_A0)
  13000     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM88690_A0r */
  13001         soc_block_list[61],
  13002         soc_iprocreg,
  13003         1,
  13004         0,
  13005         0x18115804,
  13006         SOC_REG_FLAG_RO,
  13007         0,
  13008         5,
  13009         soc_QSPI_IDM_IDM_RESET_STATUS_BCM88690_A0r_fields,
  13010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13011         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13012         -1,
  13013         -1,
  13014     },
  13015 #endif /* chips */
  13016 
  13017 #if defined(BCM_88690_B0)
  13018     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM88690_B0r */
  13019         soc_block_list[61],
  13020         soc_iprocreg,
  13021         1,
  13022         0,
  13023         0x18115804,
  13024         SOC_REG_FLAG_RO,
  13025         0,
  13026         5,
  13027         soc_QSPI_IDM_IDM_RESET_STATUS_BCM88690_B0r_fields,
  13028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13029         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13030         -1,
  13031         -1,
  13032     },
  13033 #endif /* chips */
  13034 
  13035 #if defined(BCM_88790_A0)
  13036     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_STATUS_BCM88790_A0r */
  13037         soc_block_list[61],
  13038         soc_iprocreg,
  13039         1,
  13040         0,
  13041         0x18115804,
  13042         SOC_REG_FLAG_RO,
  13043         0,
  13044         5,
  13045         soc_QSPI_IDM_IDM_RESET_STATUS_BCM88790_A0r_fields,
  13046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13047         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13048         -1,
  13049         -1,
  13050     },
  13051 #endif /* chips */
  13052 
  13053 #if defined(BCM_88675_A0)
  13054     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_IDr */
  13055         soc_block_list[61],
  13056         soc_iprocreg,
  13057         1,
  13058         0,
  13059         0x1811580c,
  13060         SOC_REG_FLAG_RO,
  13061         0,
  13062         2,
  13063         soc_QSPI_IDM_IDM_RESET_WRITE_IDr_fields,
  13064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13065         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13066         -1,
  13067         -1,
  13068     },
  13069 #endif /* chips */
  13070 
  13071 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \
  13072     defined(BCM_53570_B0) || defined(BCM_56260_A0) || \
  13073     defined(BCM_56260_B0)
  13074     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM53400_A0r */
  13075         soc_block_list[61],
  13076         soc_iprocreg,
  13077         1,
  13078         0,
  13079         0xf810680c,
  13080         SOC_REG_FLAG_RO,
  13081         0,
  13082         2,
  13083         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  13084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13085         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13086         -1,
  13087         -1,
  13088     },
  13089 #endif /* chips */
  13090 
  13091 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
  13092     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM56160_A0r */
  13093         soc_block_list[61],
  13094         soc_iprocreg,
  13095         1,
  13096         0,
  13097         0x1811f80c,
  13098         SOC_REG_FLAG_RO,
  13099         0,
  13100         2,
  13101         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  13102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13103         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13104         -1,
  13105         -1,
  13106     },
  13107 #endif /* chips */
  13108 
  13109 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13110     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13111     defined(BCM_56450_B1)
  13112     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM56450_A0r */
  13113         soc_block_list[61],
  13114         soc_iprocreg,
  13115         1,
  13116         0,
  13117         0x1811c80c,
  13118         SOC_REG_FLAG_RO,
  13119         0,
  13120         2,
  13121         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM56450_A0r_fields,
  13122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13123         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13124         -1,
  13125         -1,
  13126     },
  13127 #endif /* chips */
  13128 
  13129 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  13130     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  13131     defined(BCM_56670_B0)
  13132     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM56560_A0r */
  13133         soc_block_list[61],
  13134         soc_iprocreg,
  13135         1,
  13136         0,
  13137         0x1811580c,
  13138         SOC_REG_FLAG_RO,
  13139         0,
  13140         2,
  13141         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  13142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13143         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13144         -1,
  13145         -1,
  13146     },
  13147 #endif /* chips */
  13148 
  13149 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13150     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  13151     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  13152     defined(BCM_56980_B0)
  13153     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM56960_A0r */
  13154         soc_block_list[61],
  13155         soc_iprocreg,
  13156         1,
  13157         0,
  13158         0x1811580c,
  13159         SOC_REG_FLAG_RO,
  13160         0,
  13161         2,
  13162         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
  13163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13164         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13165         -1,
  13166         -1,
  13167         3,
  13168     },
  13169 #endif /* chips */
  13170 
  13171 #if defined(BCM_88270_A0)
  13172     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88270_A0r */
  13173         soc_block_list[61],
  13174         soc_iprocreg,
  13175         1,
  13176         0,
  13177         0x1811580c,
  13178         SOC_REG_FLAG_RO,
  13179         0,
  13180         2,
  13181         soc_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88270_A0r_fields,
  13182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13183         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13184         -1,
  13185         -1,
  13186     },
  13187 #endif /* chips */
  13188 
  13189 #if defined(BCM_88375_A0)
  13190     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88375_A0r */
  13191         soc_block_list[61],
  13192         soc_iprocreg,
  13193         1,
  13194         0,
  13195         0x1811580c,
  13196         SOC_REG_FLAG_RO,
  13197         0,
  13198         2,
  13199         soc_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88375_A0r_fields,
  13200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13201         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13202         -1,
  13203         -1,
  13204     },
  13205 #endif /* chips */
  13206 
  13207 #if defined(BCM_88375_B0)
  13208     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88375_B0r */
  13209         soc_block_list[61],
  13210         soc_iprocreg,
  13211         1,
  13212         0,
  13213         0x1811580c,
  13214         SOC_REG_FLAG_RO,
  13215         0,
  13216         2,
  13217         soc_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88375_B0r_fields,
  13218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13219         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13220         -1,
  13221         -1,
  13222     },
  13223 #endif /* chips */
  13224 
  13225 #if defined(BCM_88470_A0)
  13226     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88470_A0r */
  13227         soc_block_list[61],
  13228         soc_iprocreg,
  13229         1,
  13230         0,
  13231         0x1811580c,
  13232         SOC_REG_FLAG_RO,
  13233         0,
  13234         2,
  13235         soc_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88470_A0r_fields,
  13236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13237         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13238         -1,
  13239         -1,
  13240     },
  13241 #endif /* chips */
  13242 
  13243 #if defined(BCM_88470_B0)
  13244     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88470_B0r */
  13245         soc_block_list[61],
  13246         soc_iprocreg,
  13247         1,
  13248         0,
  13249         0x1811580c,
  13250         SOC_REG_FLAG_RO,
  13251         0,
  13252         2,
  13253         soc_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88470_B0r_fields,
  13254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13255         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13256         -1,
  13257         -1,
  13258     },
  13259 #endif /* chips */
  13260 
  13261 #if defined(BCM_88675_B0)
  13262     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88675_B0r */
  13263         soc_block_list[61],
  13264         soc_iprocreg,
  13265         1,
  13266         0,
  13267         0x1811580c,
  13268         SOC_REG_FLAG_RO,
  13269         0,
  13270         2,
  13271         soc_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88675_B0r_fields,
  13272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13273         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13274         -1,
  13275         -1,
  13276     },
  13277 #endif /* chips */
  13278 
  13279 #if defined(BCM_88680_A0)
  13280     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88680_A0r */
  13281         soc_block_list[61],
  13282         soc_iprocreg,
  13283         1,
  13284         0,
  13285         0x1811580c,
  13286         SOC_REG_FLAG_RO,
  13287         0,
  13288         2,
  13289         soc_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88680_A0r_fields,
  13290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13291         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13292         -1,
  13293         -1,
  13294     },
  13295 #endif /* chips */
  13296 
  13297 #if defined(BCM_88690_A0)
  13298     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88690_A0r */
  13299         soc_block_list[61],
  13300         soc_iprocreg,
  13301         1,
  13302         0,
  13303         0x1811580c,
  13304         SOC_REG_FLAG_RO,
  13305         0,
  13306         2,
  13307         soc_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88690_A0r_fields,
  13308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13309         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13310         -1,
  13311         -1,
  13312     },
  13313 #endif /* chips */
  13314 
  13315 #if defined(BCM_88690_B0)
  13316     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88690_B0r */
  13317         soc_block_list[61],
  13318         soc_iprocreg,
  13319         1,
  13320         0,
  13321         0x1811580c,
  13322         SOC_REG_FLAG_RO,
  13323         0,
  13324         2,
  13325         soc_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88690_B0r_fields,
  13326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13327         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13328         -1,
  13329         -1,
  13330     },
  13331 #endif /* chips */
  13332 
  13333 #if defined(BCM_88790_A0)
  13334     { /* SOC_REG_INT_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88790_A0r */
  13335         soc_block_list[61],
  13336         soc_iprocreg,
  13337         1,
  13338         0,
  13339         0x1811580c,
  13340         SOC_REG_FLAG_RO,
  13341         0,
  13342         2,
  13343         soc_QSPI_IDM_IDM_RESET_WRITE_ID_BCM88790_A0r_fields,
  13344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13346         -1,
  13347         -1,
  13348     },
  13349 #endif /* chips */
  13350 
  13351 #if defined(BCM_88675_A0)
  13352     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00r */
  13353         soc_block_list[61],
  13354         soc_iprocreg,
  13355         1,
  13356         0,
  13357         0x18021340,
  13358         0,
  13359         0,
  13360         2,
  13361         soc_QSPI_MSPI_CDRAM00r_fields,
  13362         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13363         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13364         -1,
  13365         -1,
  13366     },
  13367 #endif /* chips */
  13368 
  13369 #if defined(BCM_88675_A0)
  13370     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01r */
  13371         soc_block_list[61],
  13372         soc_iprocreg,
  13373         1,
  13374         0,
  13375         0x18021344,
  13376         0,
  13377         0,
  13378         2,
  13379         soc_QSPI_MSPI_CDRAM01r_fields,
  13380         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13382         -1,
  13383         -1,
  13384     },
  13385 #endif /* chips */
  13386 
  13387 #if defined(BCM_88675_A0)
  13388     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02r */
  13389         soc_block_list[61],
  13390         soc_iprocreg,
  13391         1,
  13392         0,
  13393         0x18021348,
  13394         0,
  13395         0,
  13396         2,
  13397         soc_QSPI_MSPI_CDRAM02r_fields,
  13398         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13399         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13400         -1,
  13401         -1,
  13402     },
  13403 #endif /* chips */
  13404 
  13405 #if defined(BCM_88675_A0)
  13406     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03r */
  13407         soc_block_list[61],
  13408         soc_iprocreg,
  13409         1,
  13410         0,
  13411         0x1802134c,
  13412         0,
  13413         0,
  13414         2,
  13415         soc_QSPI_MSPI_CDRAM03r_fields,
  13416         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13418         -1,
  13419         -1,
  13420     },
  13421 #endif /* chips */
  13422 
  13423 #if defined(BCM_88675_A0)
  13424     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04r */
  13425         soc_block_list[61],
  13426         soc_iprocreg,
  13427         1,
  13428         0,
  13429         0x18021350,
  13430         0,
  13431         0,
  13432         2,
  13433         soc_QSPI_MSPI_CDRAM04r_fields,
  13434         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13435         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13436         -1,
  13437         -1,
  13438     },
  13439 #endif /* chips */
  13440 
  13441 #if defined(BCM_88675_A0)
  13442     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05r */
  13443         soc_block_list[61],
  13444         soc_iprocreg,
  13445         1,
  13446         0,
  13447         0x18021354,
  13448         0,
  13449         0,
  13450         2,
  13451         soc_QSPI_MSPI_CDRAM05r_fields,
  13452         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13454         -1,
  13455         -1,
  13456     },
  13457 #endif /* chips */
  13458 
  13459 #if defined(BCM_88675_A0)
  13460     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06r */
  13461         soc_block_list[61],
  13462         soc_iprocreg,
  13463         1,
  13464         0,
  13465         0x18021358,
  13466         0,
  13467         0,
  13468         2,
  13469         soc_QSPI_MSPI_CDRAM06r_fields,
  13470         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13471         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13472         -1,
  13473         -1,
  13474     },
  13475 #endif /* chips */
  13476 
  13477 #if defined(BCM_88675_A0)
  13478     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07r */
  13479         soc_block_list[61],
  13480         soc_iprocreg,
  13481         1,
  13482         0,
  13483         0x1802135c,
  13484         0,
  13485         0,
  13486         2,
  13487         soc_QSPI_MSPI_CDRAM07r_fields,
  13488         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13490         -1,
  13491         -1,
  13492     },
  13493 #endif /* chips */
  13494 
  13495 #if defined(BCM_88675_A0)
  13496     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08r */
  13497         soc_block_list[61],
  13498         soc_iprocreg,
  13499         1,
  13500         0,
  13501         0x18021360,
  13502         0,
  13503         0,
  13504         2,
  13505         soc_QSPI_MSPI_CDRAM08r_fields,
  13506         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13507         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13508         -1,
  13509         -1,
  13510     },
  13511 #endif /* chips */
  13512 
  13513 #if defined(BCM_88675_A0)
  13514     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09r */
  13515         soc_block_list[61],
  13516         soc_iprocreg,
  13517         1,
  13518         0,
  13519         0x18021364,
  13520         0,
  13521         0,
  13522         2,
  13523         soc_QSPI_MSPI_CDRAM09r_fields,
  13524         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13526         -1,
  13527         -1,
  13528     },
  13529 #endif /* chips */
  13530 
  13531 #if defined(BCM_88675_A0)
  13532     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10r */
  13533         soc_block_list[61],
  13534         soc_iprocreg,
  13535         1,
  13536         0,
  13537         0x18021368,
  13538         0,
  13539         0,
  13540         2,
  13541         soc_QSPI_MSPI_CDRAM10r_fields,
  13542         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13544         -1,
  13545         -1,
  13546     },
  13547 #endif /* chips */
  13548 
  13549 #if defined(BCM_88675_A0)
  13550     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11r */
  13551         soc_block_list[61],
  13552         soc_iprocreg,
  13553         1,
  13554         0,
  13555         0x1802136c,
  13556         0,
  13557         0,
  13558         2,
  13559         soc_QSPI_MSPI_CDRAM11r_fields,
  13560         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13561         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13562         -1,
  13563         -1,
  13564     },
  13565 #endif /* chips */
  13566 
  13567 #if defined(BCM_88675_A0)
  13568     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12r */
  13569         soc_block_list[61],
  13570         soc_iprocreg,
  13571         1,
  13572         0,
  13573         0x18021370,
  13574         0,
  13575         0,
  13576         2,
  13577         soc_QSPI_MSPI_CDRAM12r_fields,
  13578         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13579         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13580         -1,
  13581         -1,
  13582     },
  13583 #endif /* chips */
  13584 
  13585 #if defined(BCM_88675_A0)
  13586     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13r */
  13587         soc_block_list[61],
  13588         soc_iprocreg,
  13589         1,
  13590         0,
  13591         0x18021374,
  13592         0,
  13593         0,
  13594         2,
  13595         soc_QSPI_MSPI_CDRAM13r_fields,
  13596         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13597         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13598         -1,
  13599         -1,
  13600     },
  13601 #endif /* chips */
  13602 
  13603 #if defined(BCM_88675_A0)
  13604     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14r */
  13605         soc_block_list[61],
  13606         soc_iprocreg,
  13607         1,
  13608         0,
  13609         0x18021378,
  13610         0,
  13611         0,
  13612         2,
  13613         soc_QSPI_MSPI_CDRAM14r_fields,
  13614         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13615         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13616         -1,
  13617         -1,
  13618     },
  13619 #endif /* chips */
  13620 
  13621 #if defined(BCM_88675_A0)
  13622     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15r */
  13623         soc_block_list[61],
  13624         soc_iprocreg,
  13625         1,
  13626         0,
  13627         0x1802137c,
  13628         0,
  13629         0,
  13630         2,
  13631         soc_QSPI_MSPI_CDRAM15r_fields,
  13632         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13633         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13634         -1,
  13635         -1,
  13636     },
  13637 #endif /* chips */
  13638 
  13639 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13640     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13641     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13642     defined(BCM_56260_B0)
  13643     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM53400_A0r */
  13644         soc_block_list[61],
  13645         soc_iprocreg,
  13646         1,
  13647         0,
  13648         0x18047340,
  13649         0,
  13650         0,
  13651         2,
  13652         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  13653         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13654         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13655         -1,
  13656         -1,
  13657     },
  13658 #endif /* chips */
  13659 
  13660 #if defined(BCM_56370_A0)
  13661     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM56370_A0r */
  13662         soc_block_list[61],
  13663         soc_iprocreg,
  13664         1,
  13665         0,
  13666         0x15000340,
  13667         0,
  13668         0,
  13669         2,
  13670         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  13671         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13672         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13673         -1,
  13674         -1,
  13675         3,
  13676     },
  13677 #endif /* chips */
  13678 
  13679 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13680     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13681     defined(BCM_56450_B1)
  13682     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM56450_A0r */
  13683         soc_block_list[61],
  13684         soc_iprocreg,
  13685         1,
  13686         0,
  13687         0x18027340,
  13688         0,
  13689         0,
  13690         2,
  13691         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  13692         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13693         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13694         -1,
  13695         -1,
  13696     },
  13697 #endif /* chips */
  13698 
  13699 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  13700     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  13701     defined(BCM_56670_B0)
  13702     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM56560_A0r */
  13703         soc_block_list[61],
  13704         soc_iprocreg,
  13705         1,
  13706         0,
  13707         0x18021340,
  13708         0,
  13709         0,
  13710         2,
  13711         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  13712         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13713         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13714         -1,
  13715         -1,
  13716     },
  13717 #endif /* chips */
  13718 
  13719 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  13720     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  13721     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  13722     defined(BCM_56980_B0)
  13723     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM56960_A0r */
  13724         soc_block_list[61],
  13725         soc_iprocreg,
  13726         1,
  13727         0,
  13728         0x18021340,
  13729         0,
  13730         0,
  13731         2,
  13732         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  13733         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13734         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13735         -1,
  13736         -1,
  13737         3,
  13738     },
  13739 #endif /* chips */
  13740 
  13741 #if defined(BCM_88270_A0)
  13742     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM88270_A0r */
  13743         soc_block_list[61],
  13744         soc_iprocreg,
  13745         1,
  13746         0,
  13747         0x18021340,
  13748         0,
  13749         0,
  13750         2,
  13751         soc_QSPI_MSPI_CDRAM00_BCM88270_A0r_fields,
  13752         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13753         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13754         -1,
  13755         -1,
  13756     },
  13757 #endif /* chips */
  13758 
  13759 #if defined(BCM_88375_A0)
  13760     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM88375_A0r */
  13761         soc_block_list[61],
  13762         soc_iprocreg,
  13763         1,
  13764         0,
  13765         0x18021340,
  13766         0,
  13767         0,
  13768         2,
  13769         soc_QSPI_MSPI_CDRAM00_BCM88375_A0r_fields,
  13770         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13771         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13772         -1,
  13773         -1,
  13774     },
  13775 #endif /* chips */
  13776 
  13777 #if defined(BCM_88375_B0)
  13778     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM88375_B0r */
  13779         soc_block_list[61],
  13780         soc_iprocreg,
  13781         1,
  13782         0,
  13783         0x18021340,
  13784         0,
  13785         0,
  13786         2,
  13787         soc_QSPI_MSPI_CDRAM00_BCM88375_B0r_fields,
  13788         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13789         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13790         -1,
  13791         -1,
  13792     },
  13793 #endif /* chips */
  13794 
  13795 #if defined(BCM_88470_A0)
  13796     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM88470_A0r */
  13797         soc_block_list[61],
  13798         soc_iprocreg,
  13799         1,
  13800         0,
  13801         0x18021340,
  13802         0,
  13803         0,
  13804         2,
  13805         soc_QSPI_MSPI_CDRAM00_BCM88470_A0r_fields,
  13806         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13807         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13808         -1,
  13809         -1,
  13810     },
  13811 #endif /* chips */
  13812 
  13813 #if defined(BCM_88470_B0)
  13814     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM88470_B0r */
  13815         soc_block_list[61],
  13816         soc_iprocreg,
  13817         1,
  13818         0,
  13819         0x18021340,
  13820         0,
  13821         0,
  13822         2,
  13823         soc_QSPI_MSPI_CDRAM00_BCM88470_B0r_fields,
  13824         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13825         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13826         -1,
  13827         -1,
  13828     },
  13829 #endif /* chips */
  13830 
  13831 #if defined(BCM_88675_B0)
  13832     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM88675_B0r */
  13833         soc_block_list[61],
  13834         soc_iprocreg,
  13835         1,
  13836         0,
  13837         0x18021340,
  13838         0,
  13839         0,
  13840         2,
  13841         soc_QSPI_MSPI_CDRAM00_BCM88675_B0r_fields,
  13842         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13843         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13844         -1,
  13845         -1,
  13846     },
  13847 #endif /* chips */
  13848 
  13849 #if defined(BCM_88680_A0)
  13850     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM88680_A0r */
  13851         soc_block_list[61],
  13852         soc_iprocreg,
  13853         1,
  13854         0,
  13855         0x18021340,
  13856         0,
  13857         0,
  13858         2,
  13859         soc_QSPI_MSPI_CDRAM00_BCM88680_A0r_fields,
  13860         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13861         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13862         -1,
  13863         -1,
  13864     },
  13865 #endif /* chips */
  13866 
  13867 #if defined(BCM_88690_A0)
  13868     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM88690_A0r */
  13869         soc_block_list[61],
  13870         soc_iprocreg,
  13871         1,
  13872         0,
  13873         0x18021340,
  13874         0,
  13875         0,
  13876         2,
  13877         soc_QSPI_MSPI_CDRAM00_BCM88690_A0r_fields,
  13878         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13879         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13880         -1,
  13881         -1,
  13882     },
  13883 #endif /* chips */
  13884 
  13885 #if defined(BCM_88690_B0)
  13886     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM88690_B0r */
  13887         soc_block_list[61],
  13888         soc_iprocreg,
  13889         1,
  13890         0,
  13891         0x18021340,
  13892         0,
  13893         0,
  13894         2,
  13895         soc_QSPI_MSPI_CDRAM00_BCM88690_B0r_fields,
  13896         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13898         -1,
  13899         -1,
  13900     },
  13901 #endif /* chips */
  13902 
  13903 #if defined(BCM_88790_A0)
  13904     { /* SOC_REG_INT_QSPI_MSPI_CDRAM00_BCM88790_A0r */
  13905         soc_block_list[61],
  13906         soc_iprocreg,
  13907         1,
  13908         0,
  13909         0x18021340,
  13910         0,
  13911         0,
  13912         2,
  13913         soc_QSPI_MSPI_CDRAM00_BCM88790_A0r_fields,
  13914         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13916         -1,
  13917         -1,
  13918     },
  13919 #endif /* chips */
  13920 
  13921 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  13922     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  13923     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  13924     defined(BCM_56260_B0)
  13925     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM53400_A0r */
  13926         soc_block_list[61],
  13927         soc_iprocreg,
  13928         1,
  13929         0,
  13930         0x18047344,
  13931         0,
  13932         0,
  13933         2,
  13934         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  13935         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13936         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13937         -1,
  13938         -1,
  13939     },
  13940 #endif /* chips */
  13941 
  13942 #if defined(BCM_56370_A0)
  13943     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM56370_A0r */
  13944         soc_block_list[61],
  13945         soc_iprocreg,
  13946         1,
  13947         0,
  13948         0x15000344,
  13949         0,
  13950         0,
  13951         2,
  13952         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  13953         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13954         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13955         -1,
  13956         -1,
  13957         3,
  13958     },
  13959 #endif /* chips */
  13960 
  13961 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  13962     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  13963     defined(BCM_56450_B1)
  13964     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM56450_A0r */
  13965         soc_block_list[61],
  13966         soc_iprocreg,
  13967         1,
  13968         0,
  13969         0x18027344,
  13970         0,
  13971         0,
  13972         2,
  13973         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  13974         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13975         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13976         -1,
  13977         -1,
  13978     },
  13979 #endif /* chips */
  13980 
  13981 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  13982     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  13983     defined(BCM_56670_B0)
  13984     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM56560_A0r */
  13985         soc_block_list[61],
  13986         soc_iprocreg,
  13987         1,
  13988         0,
  13989         0x18021344,
  13990         0,
  13991         0,
  13992         2,
  13993         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  13994         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  13995         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13996         -1,
  13997         -1,
  13998     },
  13999 #endif /* chips */
  14000 
  14001 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14002     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  14003     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  14004     defined(BCM_56980_B0)
  14005     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM56960_A0r */
  14006         soc_block_list[61],
  14007         soc_iprocreg,
  14008         1,
  14009         0,
  14010         0x18021344,
  14011         0,
  14012         0,
  14013         2,
  14014         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14015         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14016         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14017         -1,
  14018         -1,
  14019         3,
  14020     },
  14021 #endif /* chips */
  14022 
  14023 #if defined(BCM_88270_A0)
  14024     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM88270_A0r */
  14025         soc_block_list[61],
  14026         soc_iprocreg,
  14027         1,
  14028         0,
  14029         0x18021344,
  14030         0,
  14031         0,
  14032         2,
  14033         soc_QSPI_MSPI_CDRAM01_BCM88270_A0r_fields,
  14034         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14035         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14036         -1,
  14037         -1,
  14038     },
  14039 #endif /* chips */
  14040 
  14041 #if defined(BCM_88375_A0)
  14042     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM88375_A0r */
  14043         soc_block_list[61],
  14044         soc_iprocreg,
  14045         1,
  14046         0,
  14047         0x18021344,
  14048         0,
  14049         0,
  14050         2,
  14051         soc_QSPI_MSPI_CDRAM01_BCM88375_A0r_fields,
  14052         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14053         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14054         -1,
  14055         -1,
  14056     },
  14057 #endif /* chips */
  14058 
  14059 #if defined(BCM_88375_B0)
  14060     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM88375_B0r */
  14061         soc_block_list[61],
  14062         soc_iprocreg,
  14063         1,
  14064         0,
  14065         0x18021344,
  14066         0,
  14067         0,
  14068         2,
  14069         soc_QSPI_MSPI_CDRAM01_BCM88375_B0r_fields,
  14070         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14071         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14072         -1,
  14073         -1,
  14074     },
  14075 #endif /* chips */
  14076 
  14077 #if defined(BCM_88470_A0)
  14078     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM88470_A0r */
  14079         soc_block_list[61],
  14080         soc_iprocreg,
  14081         1,
  14082         0,
  14083         0x18021344,
  14084         0,
  14085         0,
  14086         2,
  14087         soc_QSPI_MSPI_CDRAM01_BCM88470_A0r_fields,
  14088         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14089         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14090         -1,
  14091         -1,
  14092     },
  14093 #endif /* chips */
  14094 
  14095 #if defined(BCM_88470_B0)
  14096     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM88470_B0r */
  14097         soc_block_list[61],
  14098         soc_iprocreg,
  14099         1,
  14100         0,
  14101         0x18021344,
  14102         0,
  14103         0,
  14104         2,
  14105         soc_QSPI_MSPI_CDRAM01_BCM88470_B0r_fields,
  14106         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14107         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14108         -1,
  14109         -1,
  14110     },
  14111 #endif /* chips */
  14112 
  14113 #if defined(BCM_88675_B0)
  14114     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM88675_B0r */
  14115         soc_block_list[61],
  14116         soc_iprocreg,
  14117         1,
  14118         0,
  14119         0x18021344,
  14120         0,
  14121         0,
  14122         2,
  14123         soc_QSPI_MSPI_CDRAM01_BCM88675_B0r_fields,
  14124         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14125         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14126         -1,
  14127         -1,
  14128     },
  14129 #endif /* chips */
  14130 
  14131 #if defined(BCM_88680_A0)
  14132     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM88680_A0r */
  14133         soc_block_list[61],
  14134         soc_iprocreg,
  14135         1,
  14136         0,
  14137         0x18021344,
  14138         0,
  14139         0,
  14140         2,
  14141         soc_QSPI_MSPI_CDRAM01_BCM88680_A0r_fields,
  14142         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14143         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14144         -1,
  14145         -1,
  14146     },
  14147 #endif /* chips */
  14148 
  14149 #if defined(BCM_88690_A0)
  14150     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM88690_A0r */
  14151         soc_block_list[61],
  14152         soc_iprocreg,
  14153         1,
  14154         0,
  14155         0x18021344,
  14156         0,
  14157         0,
  14158         2,
  14159         soc_QSPI_MSPI_CDRAM01_BCM88690_A0r_fields,
  14160         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14161         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14162         -1,
  14163         -1,
  14164     },
  14165 #endif /* chips */
  14166 
  14167 #if defined(BCM_88690_B0)
  14168     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM88690_B0r */
  14169         soc_block_list[61],
  14170         soc_iprocreg,
  14171         1,
  14172         0,
  14173         0x18021344,
  14174         0,
  14175         0,
  14176         2,
  14177         soc_QSPI_MSPI_CDRAM01_BCM88690_B0r_fields,
  14178         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14179         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14180         -1,
  14181         -1,
  14182     },
  14183 #endif /* chips */
  14184 
  14185 #if defined(BCM_88790_A0)
  14186     { /* SOC_REG_INT_QSPI_MSPI_CDRAM01_BCM88790_A0r */
  14187         soc_block_list[61],
  14188         soc_iprocreg,
  14189         1,
  14190         0,
  14191         0x18021344,
  14192         0,
  14193         0,
  14194         2,
  14195         soc_QSPI_MSPI_CDRAM01_BCM88790_A0r_fields,
  14196         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14197         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14198         -1,
  14199         -1,
  14200     },
  14201 #endif /* chips */
  14202 
  14203 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14204     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14205     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14206     defined(BCM_56260_B0)
  14207     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM53400_A0r */
  14208         soc_block_list[61],
  14209         soc_iprocreg,
  14210         1,
  14211         0,
  14212         0x18047348,
  14213         0,
  14214         0,
  14215         2,
  14216         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14217         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14218         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14219         -1,
  14220         -1,
  14221     },
  14222 #endif /* chips */
  14223 
  14224 #if defined(BCM_56370_A0)
  14225     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM56370_A0r */
  14226         soc_block_list[61],
  14227         soc_iprocreg,
  14228         1,
  14229         0,
  14230         0x15000348,
  14231         0,
  14232         0,
  14233         2,
  14234         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14235         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14236         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14237         -1,
  14238         -1,
  14239         3,
  14240     },
  14241 #endif /* chips */
  14242 
  14243 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14244     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14245     defined(BCM_56450_B1)
  14246     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM56450_A0r */
  14247         soc_block_list[61],
  14248         soc_iprocreg,
  14249         1,
  14250         0,
  14251         0x18027348,
  14252         0,
  14253         0,
  14254         2,
  14255         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  14256         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14258         -1,
  14259         -1,
  14260     },
  14261 #endif /* chips */
  14262 
  14263 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  14264     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  14265     defined(BCM_56670_B0)
  14266     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM56560_A0r */
  14267         soc_block_list[61],
  14268         soc_iprocreg,
  14269         1,
  14270         0,
  14271         0x18021348,
  14272         0,
  14273         0,
  14274         2,
  14275         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14276         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14277         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14278         -1,
  14279         -1,
  14280     },
  14281 #endif /* chips */
  14282 
  14283 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14284     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  14285     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  14286     defined(BCM_56980_B0)
  14287     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM56960_A0r */
  14288         soc_block_list[61],
  14289         soc_iprocreg,
  14290         1,
  14291         0,
  14292         0x18021348,
  14293         0,
  14294         0,
  14295         2,
  14296         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14297         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14298         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14299         -1,
  14300         -1,
  14301         3,
  14302     },
  14303 #endif /* chips */
  14304 
  14305 #if defined(BCM_88270_A0)
  14306     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM88270_A0r */
  14307         soc_block_list[61],
  14308         soc_iprocreg,
  14309         1,
  14310         0,
  14311         0x18021348,
  14312         0,
  14313         0,
  14314         2,
  14315         soc_QSPI_MSPI_CDRAM02_BCM88270_A0r_fields,
  14316         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14318         -1,
  14319         -1,
  14320     },
  14321 #endif /* chips */
  14322 
  14323 #if defined(BCM_88375_A0)
  14324     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM88375_A0r */
  14325         soc_block_list[61],
  14326         soc_iprocreg,
  14327         1,
  14328         0,
  14329         0x18021348,
  14330         0,
  14331         0,
  14332         2,
  14333         soc_QSPI_MSPI_CDRAM02_BCM88375_A0r_fields,
  14334         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14335         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14336         -1,
  14337         -1,
  14338     },
  14339 #endif /* chips */
  14340 
  14341 #if defined(BCM_88375_B0)
  14342     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM88375_B0r */
  14343         soc_block_list[61],
  14344         soc_iprocreg,
  14345         1,
  14346         0,
  14347         0x18021348,
  14348         0,
  14349         0,
  14350         2,
  14351         soc_QSPI_MSPI_CDRAM02_BCM88375_B0r_fields,
  14352         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14353         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14354         -1,
  14355         -1,
  14356     },
  14357 #endif /* chips */
  14358 
  14359 #if defined(BCM_88470_A0)
  14360     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM88470_A0r */
  14361         soc_block_list[61],
  14362         soc_iprocreg,
  14363         1,
  14364         0,
  14365         0x18021348,
  14366         0,
  14367         0,
  14368         2,
  14369         soc_QSPI_MSPI_CDRAM02_BCM88470_A0r_fields,
  14370         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14371         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14372         -1,
  14373         -1,
  14374     },
  14375 #endif /* chips */
  14376 
  14377 #if defined(BCM_88470_B0)
  14378     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM88470_B0r */
  14379         soc_block_list[61],
  14380         soc_iprocreg,
  14381         1,
  14382         0,
  14383         0x18021348,
  14384         0,
  14385         0,
  14386         2,
  14387         soc_QSPI_MSPI_CDRAM02_BCM88470_B0r_fields,
  14388         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14389         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14390         -1,
  14391         -1,
  14392     },
  14393 #endif /* chips */
  14394 
  14395 #if defined(BCM_88675_B0)
  14396     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM88675_B0r */
  14397         soc_block_list[61],
  14398         soc_iprocreg,
  14399         1,
  14400         0,
  14401         0x18021348,
  14402         0,
  14403         0,
  14404         2,
  14405         soc_QSPI_MSPI_CDRAM02_BCM88675_B0r_fields,
  14406         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14407         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14408         -1,
  14409         -1,
  14410     },
  14411 #endif /* chips */
  14412 
  14413 #if defined(BCM_88680_A0)
  14414     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM88680_A0r */
  14415         soc_block_list[61],
  14416         soc_iprocreg,
  14417         1,
  14418         0,
  14419         0x18021348,
  14420         0,
  14421         0,
  14422         2,
  14423         soc_QSPI_MSPI_CDRAM02_BCM88680_A0r_fields,
  14424         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14425         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14426         -1,
  14427         -1,
  14428     },
  14429 #endif /* chips */
  14430 
  14431 #if defined(BCM_88690_A0)
  14432     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM88690_A0r */
  14433         soc_block_list[61],
  14434         soc_iprocreg,
  14435         1,
  14436         0,
  14437         0x18021348,
  14438         0,
  14439         0,
  14440         2,
  14441         soc_QSPI_MSPI_CDRAM02_BCM88690_A0r_fields,
  14442         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14444         -1,
  14445         -1,
  14446     },
  14447 #endif /* chips */
  14448 
  14449 #if defined(BCM_88690_B0)
  14450     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM88690_B0r */
  14451         soc_block_list[61],
  14452         soc_iprocreg,
  14453         1,
  14454         0,
  14455         0x18021348,
  14456         0,
  14457         0,
  14458         2,
  14459         soc_QSPI_MSPI_CDRAM02_BCM88690_B0r_fields,
  14460         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14462         -1,
  14463         -1,
  14464     },
  14465 #endif /* chips */
  14466 
  14467 #if defined(BCM_88790_A0)
  14468     { /* SOC_REG_INT_QSPI_MSPI_CDRAM02_BCM88790_A0r */
  14469         soc_block_list[61],
  14470         soc_iprocreg,
  14471         1,
  14472         0,
  14473         0x18021348,
  14474         0,
  14475         0,
  14476         2,
  14477         soc_QSPI_MSPI_CDRAM02_BCM88790_A0r_fields,
  14478         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14479         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14480         -1,
  14481         -1,
  14482     },
  14483 #endif /* chips */
  14484 
  14485 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14486     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14487     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14488     defined(BCM_56260_B0)
  14489     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM53400_A0r */
  14490         soc_block_list[61],
  14491         soc_iprocreg,
  14492         1,
  14493         0,
  14494         0x1804734c,
  14495         0,
  14496         0,
  14497         2,
  14498         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14499         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14500         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14501         -1,
  14502         -1,
  14503     },
  14504 #endif /* chips */
  14505 
  14506 #if defined(BCM_56370_A0)
  14507     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM56370_A0r */
  14508         soc_block_list[61],
  14509         soc_iprocreg,
  14510         1,
  14511         0,
  14512         0x1500034c,
  14513         0,
  14514         0,
  14515         2,
  14516         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14517         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14518         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14519         -1,
  14520         -1,
  14521         3,
  14522     },
  14523 #endif /* chips */
  14524 
  14525 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14526     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14527     defined(BCM_56450_B1)
  14528     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM56450_A0r */
  14529         soc_block_list[61],
  14530         soc_iprocreg,
  14531         1,
  14532         0,
  14533         0x1802734c,
  14534         0,
  14535         0,
  14536         2,
  14537         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  14538         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14539         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14540         -1,
  14541         -1,
  14542     },
  14543 #endif /* chips */
  14544 
  14545 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  14546     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  14547     defined(BCM_56670_B0)
  14548     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM56560_A0r */
  14549         soc_block_list[61],
  14550         soc_iprocreg,
  14551         1,
  14552         0,
  14553         0x1802134c,
  14554         0,
  14555         0,
  14556         2,
  14557         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14558         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14559         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14560         -1,
  14561         -1,
  14562     },
  14563 #endif /* chips */
  14564 
  14565 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14566     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  14567     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  14568     defined(BCM_56980_B0)
  14569     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM56960_A0r */
  14570         soc_block_list[61],
  14571         soc_iprocreg,
  14572         1,
  14573         0,
  14574         0x1802134c,
  14575         0,
  14576         0,
  14577         2,
  14578         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14579         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14580         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14581         -1,
  14582         -1,
  14583         3,
  14584     },
  14585 #endif /* chips */
  14586 
  14587 #if defined(BCM_88270_A0)
  14588     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM88270_A0r */
  14589         soc_block_list[61],
  14590         soc_iprocreg,
  14591         1,
  14592         0,
  14593         0x1802134c,
  14594         0,
  14595         0,
  14596         2,
  14597         soc_QSPI_MSPI_CDRAM03_BCM88270_A0r_fields,
  14598         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14599         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14600         -1,
  14601         -1,
  14602     },
  14603 #endif /* chips */
  14604 
  14605 #if defined(BCM_88375_A0)
  14606     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM88375_A0r */
  14607         soc_block_list[61],
  14608         soc_iprocreg,
  14609         1,
  14610         0,
  14611         0x1802134c,
  14612         0,
  14613         0,
  14614         2,
  14615         soc_QSPI_MSPI_CDRAM03_BCM88375_A0r_fields,
  14616         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14618         -1,
  14619         -1,
  14620     },
  14621 #endif /* chips */
  14622 
  14623 #if defined(BCM_88375_B0)
  14624     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM88375_B0r */
  14625         soc_block_list[61],
  14626         soc_iprocreg,
  14627         1,
  14628         0,
  14629         0x1802134c,
  14630         0,
  14631         0,
  14632         2,
  14633         soc_QSPI_MSPI_CDRAM03_BCM88375_B0r_fields,
  14634         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14635         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14636         -1,
  14637         -1,
  14638     },
  14639 #endif /* chips */
  14640 
  14641 #if defined(BCM_88470_A0)
  14642     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM88470_A0r */
  14643         soc_block_list[61],
  14644         soc_iprocreg,
  14645         1,
  14646         0,
  14647         0x1802134c,
  14648         0,
  14649         0,
  14650         2,
  14651         soc_QSPI_MSPI_CDRAM03_BCM88470_A0r_fields,
  14652         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14653         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14654         -1,
  14655         -1,
  14656     },
  14657 #endif /* chips */
  14658 
  14659 #if defined(BCM_88470_B0)
  14660     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM88470_B0r */
  14661         soc_block_list[61],
  14662         soc_iprocreg,
  14663         1,
  14664         0,
  14665         0x1802134c,
  14666         0,
  14667         0,
  14668         2,
  14669         soc_QSPI_MSPI_CDRAM03_BCM88470_B0r_fields,
  14670         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14671         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14672         -1,
  14673         -1,
  14674     },
  14675 #endif /* chips */
  14676 
  14677 #if defined(BCM_88675_B0)
  14678     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM88675_B0r */
  14679         soc_block_list[61],
  14680         soc_iprocreg,
  14681         1,
  14682         0,
  14683         0x1802134c,
  14684         0,
  14685         0,
  14686         2,
  14687         soc_QSPI_MSPI_CDRAM03_BCM88675_B0r_fields,
  14688         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14690         -1,
  14691         -1,
  14692     },
  14693 #endif /* chips */
  14694 
  14695 #if defined(BCM_88680_A0)
  14696     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM88680_A0r */
  14697         soc_block_list[61],
  14698         soc_iprocreg,
  14699         1,
  14700         0,
  14701         0x1802134c,
  14702         0,
  14703         0,
  14704         2,
  14705         soc_QSPI_MSPI_CDRAM03_BCM88680_A0r_fields,
  14706         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14708         -1,
  14709         -1,
  14710     },
  14711 #endif /* chips */
  14712 
  14713 #if defined(BCM_88690_A0)
  14714     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM88690_A0r */
  14715         soc_block_list[61],
  14716         soc_iprocreg,
  14717         1,
  14718         0,
  14719         0x1802134c,
  14720         0,
  14721         0,
  14722         2,
  14723         soc_QSPI_MSPI_CDRAM03_BCM88690_A0r_fields,
  14724         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14726         -1,
  14727         -1,
  14728     },
  14729 #endif /* chips */
  14730 
  14731 #if defined(BCM_88690_B0)
  14732     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM88690_B0r */
  14733         soc_block_list[61],
  14734         soc_iprocreg,
  14735         1,
  14736         0,
  14737         0x1802134c,
  14738         0,
  14739         0,
  14740         2,
  14741         soc_QSPI_MSPI_CDRAM03_BCM88690_B0r_fields,
  14742         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14744         -1,
  14745         -1,
  14746     },
  14747 #endif /* chips */
  14748 
  14749 #if defined(BCM_88790_A0)
  14750     { /* SOC_REG_INT_QSPI_MSPI_CDRAM03_BCM88790_A0r */
  14751         soc_block_list[61],
  14752         soc_iprocreg,
  14753         1,
  14754         0,
  14755         0x1802134c,
  14756         0,
  14757         0,
  14758         2,
  14759         soc_QSPI_MSPI_CDRAM03_BCM88790_A0r_fields,
  14760         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14762         -1,
  14763         -1,
  14764     },
  14765 #endif /* chips */
  14766 
  14767 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  14768     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  14769     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  14770     defined(BCM_56260_B0)
  14771     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM53400_A0r */
  14772         soc_block_list[61],
  14773         soc_iprocreg,
  14774         1,
  14775         0,
  14776         0x18047350,
  14777         0,
  14778         0,
  14779         2,
  14780         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14781         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14782         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14783         -1,
  14784         -1,
  14785     },
  14786 #endif /* chips */
  14787 
  14788 #if defined(BCM_56370_A0)
  14789     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM56370_A0r */
  14790         soc_block_list[61],
  14791         soc_iprocreg,
  14792         1,
  14793         0,
  14794         0x15000350,
  14795         0,
  14796         0,
  14797         2,
  14798         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14799         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14800         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14801         -1,
  14802         -1,
  14803         3,
  14804     },
  14805 #endif /* chips */
  14806 
  14807 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  14808     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  14809     defined(BCM_56450_B1)
  14810     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM56450_A0r */
  14811         soc_block_list[61],
  14812         soc_iprocreg,
  14813         1,
  14814         0,
  14815         0x18027350,
  14816         0,
  14817         0,
  14818         2,
  14819         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  14820         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14821         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14822         -1,
  14823         -1,
  14824     },
  14825 #endif /* chips */
  14826 
  14827 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  14828     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  14829     defined(BCM_56670_B0)
  14830     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM56560_A0r */
  14831         soc_block_list[61],
  14832         soc_iprocreg,
  14833         1,
  14834         0,
  14835         0x18021350,
  14836         0,
  14837         0,
  14838         2,
  14839         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14840         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14842         -1,
  14843         -1,
  14844     },
  14845 #endif /* chips */
  14846 
  14847 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  14848     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  14849     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  14850     defined(BCM_56980_B0)
  14851     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM56960_A0r */
  14852         soc_block_list[61],
  14853         soc_iprocreg,
  14854         1,
  14855         0,
  14856         0x18021350,
  14857         0,
  14858         0,
  14859         2,
  14860         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  14861         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14862         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14863         -1,
  14864         -1,
  14865         3,
  14866     },
  14867 #endif /* chips */
  14868 
  14869 #if defined(BCM_88270_A0)
  14870     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM88270_A0r */
  14871         soc_block_list[61],
  14872         soc_iprocreg,
  14873         1,
  14874         0,
  14875         0x18021350,
  14876         0,
  14877         0,
  14878         2,
  14879         soc_QSPI_MSPI_CDRAM04_BCM88270_A0r_fields,
  14880         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14881         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14882         -1,
  14883         -1,
  14884     },
  14885 #endif /* chips */
  14886 
  14887 #if defined(BCM_88375_A0)
  14888     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM88375_A0r */
  14889         soc_block_list[61],
  14890         soc_iprocreg,
  14891         1,
  14892         0,
  14893         0x18021350,
  14894         0,
  14895         0,
  14896         2,
  14897         soc_QSPI_MSPI_CDRAM04_BCM88375_A0r_fields,
  14898         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14899         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14900         -1,
  14901         -1,
  14902     },
  14903 #endif /* chips */
  14904 
  14905 #if defined(BCM_88375_B0)
  14906     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM88375_B0r */
  14907         soc_block_list[61],
  14908         soc_iprocreg,
  14909         1,
  14910         0,
  14911         0x18021350,
  14912         0,
  14913         0,
  14914         2,
  14915         soc_QSPI_MSPI_CDRAM04_BCM88375_B0r_fields,
  14916         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14917         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14918         -1,
  14919         -1,
  14920     },
  14921 #endif /* chips */
  14922 
  14923 #if defined(BCM_88470_A0)
  14924     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM88470_A0r */
  14925         soc_block_list[61],
  14926         soc_iprocreg,
  14927         1,
  14928         0,
  14929         0x18021350,
  14930         0,
  14931         0,
  14932         2,
  14933         soc_QSPI_MSPI_CDRAM04_BCM88470_A0r_fields,
  14934         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14935         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14936         -1,
  14937         -1,
  14938     },
  14939 #endif /* chips */
  14940 
  14941 #if defined(BCM_88470_B0)
  14942     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM88470_B0r */
  14943         soc_block_list[61],
  14944         soc_iprocreg,
  14945         1,
  14946         0,
  14947         0x18021350,
  14948         0,
  14949         0,
  14950         2,
  14951         soc_QSPI_MSPI_CDRAM04_BCM88470_B0r_fields,
  14952         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14953         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14954         -1,
  14955         -1,
  14956     },
  14957 #endif /* chips */
  14958 
  14959 #if defined(BCM_88675_B0)
  14960     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM88675_B0r */
  14961         soc_block_list[61],
  14962         soc_iprocreg,
  14963         1,
  14964         0,
  14965         0x18021350,
  14966         0,
  14967         0,
  14968         2,
  14969         soc_QSPI_MSPI_CDRAM04_BCM88675_B0r_fields,
  14970         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14971         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14972         -1,
  14973         -1,
  14974     },
  14975 #endif /* chips */
  14976 
  14977 #if defined(BCM_88680_A0)
  14978     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM88680_A0r */
  14979         soc_block_list[61],
  14980         soc_iprocreg,
  14981         1,
  14982         0,
  14983         0x18021350,
  14984         0,
  14985         0,
  14986         2,
  14987         soc_QSPI_MSPI_CDRAM04_BCM88680_A0r_fields,
  14988         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  14989         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14990         -1,
  14991         -1,
  14992     },
  14993 #endif /* chips */
  14994 
  14995 #if defined(BCM_88690_A0)
  14996     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM88690_A0r */
  14997         soc_block_list[61],
  14998         soc_iprocreg,
  14999         1,
  15000         0,
  15001         0x18021350,
  15002         0,
  15003         0,
  15004         2,
  15005         soc_QSPI_MSPI_CDRAM04_BCM88690_A0r_fields,
  15006         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15007         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15008         -1,
  15009         -1,
  15010     },
  15011 #endif /* chips */
  15012 
  15013 #if defined(BCM_88690_B0)
  15014     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM88690_B0r */
  15015         soc_block_list[61],
  15016         soc_iprocreg,
  15017         1,
  15018         0,
  15019         0x18021350,
  15020         0,
  15021         0,
  15022         2,
  15023         soc_QSPI_MSPI_CDRAM04_BCM88690_B0r_fields,
  15024         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15025         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15026         -1,
  15027         -1,
  15028     },
  15029 #endif /* chips */
  15030 
  15031 #if defined(BCM_88790_A0)
  15032     { /* SOC_REG_INT_QSPI_MSPI_CDRAM04_BCM88790_A0r */
  15033         soc_block_list[61],
  15034         soc_iprocreg,
  15035         1,
  15036         0,
  15037         0x18021350,
  15038         0,
  15039         0,
  15040         2,
  15041         soc_QSPI_MSPI_CDRAM04_BCM88790_A0r_fields,
  15042         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15043         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15044         -1,
  15045         -1,
  15046     },
  15047 #endif /* chips */
  15048 
  15049 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15050     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15051     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15052     defined(BCM_56260_B0)
  15053     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM53400_A0r */
  15054         soc_block_list[61],
  15055         soc_iprocreg,
  15056         1,
  15057         0,
  15058         0x18047354,
  15059         0,
  15060         0,
  15061         2,
  15062         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15063         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15064         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15065         -1,
  15066         -1,
  15067     },
  15068 #endif /* chips */
  15069 
  15070 #if defined(BCM_56370_A0)
  15071     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM56370_A0r */
  15072         soc_block_list[61],
  15073         soc_iprocreg,
  15074         1,
  15075         0,
  15076         0x15000354,
  15077         0,
  15078         0,
  15079         2,
  15080         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15081         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15082         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15083         -1,
  15084         -1,
  15085         3,
  15086     },
  15087 #endif /* chips */
  15088 
  15089 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15090     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15091     defined(BCM_56450_B1)
  15092     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM56450_A0r */
  15093         soc_block_list[61],
  15094         soc_iprocreg,
  15095         1,
  15096         0,
  15097         0x18027354,
  15098         0,
  15099         0,
  15100         2,
  15101         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  15102         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15103         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15104         -1,
  15105         -1,
  15106     },
  15107 #endif /* chips */
  15108 
  15109 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  15110     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  15111     defined(BCM_56670_B0)
  15112     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM56560_A0r */
  15113         soc_block_list[61],
  15114         soc_iprocreg,
  15115         1,
  15116         0,
  15117         0x18021354,
  15118         0,
  15119         0,
  15120         2,
  15121         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15122         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15123         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15124         -1,
  15125         -1,
  15126     },
  15127 #endif /* chips */
  15128 
  15129 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15130     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  15131     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  15132     defined(BCM_56980_B0)
  15133     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM56960_A0r */
  15134         soc_block_list[61],
  15135         soc_iprocreg,
  15136         1,
  15137         0,
  15138         0x18021354,
  15139         0,
  15140         0,
  15141         2,
  15142         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15143         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15144         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15145         -1,
  15146         -1,
  15147         3,
  15148     },
  15149 #endif /* chips */
  15150 
  15151 #if defined(BCM_88270_A0)
  15152     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM88270_A0r */
  15153         soc_block_list[61],
  15154         soc_iprocreg,
  15155         1,
  15156         0,
  15157         0x18021354,
  15158         0,
  15159         0,
  15160         2,
  15161         soc_QSPI_MSPI_CDRAM05_BCM88270_A0r_fields,
  15162         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15163         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15164         -1,
  15165         -1,
  15166     },
  15167 #endif /* chips */
  15168 
  15169 #if defined(BCM_88375_A0)
  15170     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM88375_A0r */
  15171         soc_block_list[61],
  15172         soc_iprocreg,
  15173         1,
  15174         0,
  15175         0x18021354,
  15176         0,
  15177         0,
  15178         2,
  15179         soc_QSPI_MSPI_CDRAM05_BCM88375_A0r_fields,
  15180         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15181         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15182         -1,
  15183         -1,
  15184     },
  15185 #endif /* chips */
  15186 
  15187 #if defined(BCM_88375_B0)
  15188     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM88375_B0r */
  15189         soc_block_list[61],
  15190         soc_iprocreg,
  15191         1,
  15192         0,
  15193         0x18021354,
  15194         0,
  15195         0,
  15196         2,
  15197         soc_QSPI_MSPI_CDRAM05_BCM88375_B0r_fields,
  15198         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15199         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15200         -1,
  15201         -1,
  15202     },
  15203 #endif /* chips */
  15204 
  15205 #if defined(BCM_88470_A0)
  15206     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM88470_A0r */
  15207         soc_block_list[61],
  15208         soc_iprocreg,
  15209         1,
  15210         0,
  15211         0x18021354,
  15212         0,
  15213         0,
  15214         2,
  15215         soc_QSPI_MSPI_CDRAM05_BCM88470_A0r_fields,
  15216         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15217         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15218         -1,
  15219         -1,
  15220     },
  15221 #endif /* chips */
  15222 
  15223 #if defined(BCM_88470_B0)
  15224     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM88470_B0r */
  15225         soc_block_list[61],
  15226         soc_iprocreg,
  15227         1,
  15228         0,
  15229         0x18021354,
  15230         0,
  15231         0,
  15232         2,
  15233         soc_QSPI_MSPI_CDRAM05_BCM88470_B0r_fields,
  15234         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15235         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15236         -1,
  15237         -1,
  15238     },
  15239 #endif /* chips */
  15240 
  15241 #if defined(BCM_88675_B0)
  15242     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM88675_B0r */
  15243         soc_block_list[61],
  15244         soc_iprocreg,
  15245         1,
  15246         0,
  15247         0x18021354,
  15248         0,
  15249         0,
  15250         2,
  15251         soc_QSPI_MSPI_CDRAM05_BCM88675_B0r_fields,
  15252         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15253         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15254         -1,
  15255         -1,
  15256     },
  15257 #endif /* chips */
  15258 
  15259 #if defined(BCM_88680_A0)
  15260     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM88680_A0r */
  15261         soc_block_list[61],
  15262         soc_iprocreg,
  15263         1,
  15264         0,
  15265         0x18021354,
  15266         0,
  15267         0,
  15268         2,
  15269         soc_QSPI_MSPI_CDRAM05_BCM88680_A0r_fields,
  15270         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15271         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15272         -1,
  15273         -1,
  15274     },
  15275 #endif /* chips */
  15276 
  15277 #if defined(BCM_88690_A0)
  15278     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM88690_A0r */
  15279         soc_block_list[61],
  15280         soc_iprocreg,
  15281         1,
  15282         0,
  15283         0x18021354,
  15284         0,
  15285         0,
  15286         2,
  15287         soc_QSPI_MSPI_CDRAM05_BCM88690_A0r_fields,
  15288         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15289         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15290         -1,
  15291         -1,
  15292     },
  15293 #endif /* chips */
  15294 
  15295 #if defined(BCM_88690_B0)
  15296     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM88690_B0r */
  15297         soc_block_list[61],
  15298         soc_iprocreg,
  15299         1,
  15300         0,
  15301         0x18021354,
  15302         0,
  15303         0,
  15304         2,
  15305         soc_QSPI_MSPI_CDRAM05_BCM88690_B0r_fields,
  15306         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15307         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15308         -1,
  15309         -1,
  15310     },
  15311 #endif /* chips */
  15312 
  15313 #if defined(BCM_88790_A0)
  15314     { /* SOC_REG_INT_QSPI_MSPI_CDRAM05_BCM88790_A0r */
  15315         soc_block_list[61],
  15316         soc_iprocreg,
  15317         1,
  15318         0,
  15319         0x18021354,
  15320         0,
  15321         0,
  15322         2,
  15323         soc_QSPI_MSPI_CDRAM05_BCM88790_A0r_fields,
  15324         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15325         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15326         -1,
  15327         -1,
  15328     },
  15329 #endif /* chips */
  15330 
  15331 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15332     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15333     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15334     defined(BCM_56260_B0)
  15335     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM53400_A0r */
  15336         soc_block_list[61],
  15337         soc_iprocreg,
  15338         1,
  15339         0,
  15340         0x18047358,
  15341         0,
  15342         0,
  15343         2,
  15344         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15345         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15346         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15347         -1,
  15348         -1,
  15349     },
  15350 #endif /* chips */
  15351 
  15352 #if defined(BCM_56370_A0)
  15353     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM56370_A0r */
  15354         soc_block_list[61],
  15355         soc_iprocreg,
  15356         1,
  15357         0,
  15358         0x15000358,
  15359         0,
  15360         0,
  15361         2,
  15362         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15363         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15364         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15365         -1,
  15366         -1,
  15367         3,
  15368     },
  15369 #endif /* chips */
  15370 
  15371 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15372     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15373     defined(BCM_56450_B1)
  15374     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM56450_A0r */
  15375         soc_block_list[61],
  15376         soc_iprocreg,
  15377         1,
  15378         0,
  15379         0x18027358,
  15380         0,
  15381         0,
  15382         2,
  15383         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  15384         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15385         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15386         -1,
  15387         -1,
  15388     },
  15389 #endif /* chips */
  15390 
  15391 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  15392     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  15393     defined(BCM_56670_B0)
  15394     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM56560_A0r */
  15395         soc_block_list[61],
  15396         soc_iprocreg,
  15397         1,
  15398         0,
  15399         0x18021358,
  15400         0,
  15401         0,
  15402         2,
  15403         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15404         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15405         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15406         -1,
  15407         -1,
  15408     },
  15409 #endif /* chips */
  15410 
  15411 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15412     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  15413     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  15414     defined(BCM_56980_B0)
  15415     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM56960_A0r */
  15416         soc_block_list[61],
  15417         soc_iprocreg,
  15418         1,
  15419         0,
  15420         0x18021358,
  15421         0,
  15422         0,
  15423         2,
  15424         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15425         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15426         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15427         -1,
  15428         -1,
  15429         3,
  15430     },
  15431 #endif /* chips */
  15432 
  15433 #if defined(BCM_88270_A0)
  15434     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM88270_A0r */
  15435         soc_block_list[61],
  15436         soc_iprocreg,
  15437         1,
  15438         0,
  15439         0x18021358,
  15440         0,
  15441         0,
  15442         2,
  15443         soc_QSPI_MSPI_CDRAM06_BCM88270_A0r_fields,
  15444         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15446         -1,
  15447         -1,
  15448     },
  15449 #endif /* chips */
  15450 
  15451 #if defined(BCM_88375_A0)
  15452     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM88375_A0r */
  15453         soc_block_list[61],
  15454         soc_iprocreg,
  15455         1,
  15456         0,
  15457         0x18021358,
  15458         0,
  15459         0,
  15460         2,
  15461         soc_QSPI_MSPI_CDRAM06_BCM88375_A0r_fields,
  15462         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15463         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15464         -1,
  15465         -1,
  15466     },
  15467 #endif /* chips */
  15468 
  15469 #if defined(BCM_88375_B0)
  15470     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM88375_B0r */
  15471         soc_block_list[61],
  15472         soc_iprocreg,
  15473         1,
  15474         0,
  15475         0x18021358,
  15476         0,
  15477         0,
  15478         2,
  15479         soc_QSPI_MSPI_CDRAM06_BCM88375_B0r_fields,
  15480         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15481         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15482         -1,
  15483         -1,
  15484     },
  15485 #endif /* chips */
  15486 
  15487 #if defined(BCM_88470_A0)
  15488     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM88470_A0r */
  15489         soc_block_list[61],
  15490         soc_iprocreg,
  15491         1,
  15492         0,
  15493         0x18021358,
  15494         0,
  15495         0,
  15496         2,
  15497         soc_QSPI_MSPI_CDRAM06_BCM88470_A0r_fields,
  15498         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15499         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15500         -1,
  15501         -1,
  15502     },
  15503 #endif /* chips */
  15504 
  15505 #if defined(BCM_88470_B0)
  15506     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM88470_B0r */
  15507         soc_block_list[61],
  15508         soc_iprocreg,
  15509         1,
  15510         0,
  15511         0x18021358,
  15512         0,
  15513         0,
  15514         2,
  15515         soc_QSPI_MSPI_CDRAM06_BCM88470_B0r_fields,
  15516         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15517         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15518         -1,
  15519         -1,
  15520     },
  15521 #endif /* chips */
  15522 
  15523 #if defined(BCM_88675_B0)
  15524     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM88675_B0r */
  15525         soc_block_list[61],
  15526         soc_iprocreg,
  15527         1,
  15528         0,
  15529         0x18021358,
  15530         0,
  15531         0,
  15532         2,
  15533         soc_QSPI_MSPI_CDRAM06_BCM88675_B0r_fields,
  15534         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15535         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15536         -1,
  15537         -1,
  15538     },
  15539 #endif /* chips */
  15540 
  15541 #if defined(BCM_88680_A0)
  15542     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM88680_A0r */
  15543         soc_block_list[61],
  15544         soc_iprocreg,
  15545         1,
  15546         0,
  15547         0x18021358,
  15548         0,
  15549         0,
  15550         2,
  15551         soc_QSPI_MSPI_CDRAM06_BCM88680_A0r_fields,
  15552         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15553         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15554         -1,
  15555         -1,
  15556     },
  15557 #endif /* chips */
  15558 
  15559 #if defined(BCM_88690_A0)
  15560     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM88690_A0r */
  15561         soc_block_list[61],
  15562         soc_iprocreg,
  15563         1,
  15564         0,
  15565         0x18021358,
  15566         0,
  15567         0,
  15568         2,
  15569         soc_QSPI_MSPI_CDRAM06_BCM88690_A0r_fields,
  15570         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15571         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15572         -1,
  15573         -1,
  15574     },
  15575 #endif /* chips */
  15576 
  15577 #if defined(BCM_88690_B0)
  15578     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM88690_B0r */
  15579         soc_block_list[61],
  15580         soc_iprocreg,
  15581         1,
  15582         0,
  15583         0x18021358,
  15584         0,
  15585         0,
  15586         2,
  15587         soc_QSPI_MSPI_CDRAM06_BCM88690_B0r_fields,
  15588         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15589         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15590         -1,
  15591         -1,
  15592     },
  15593 #endif /* chips */
  15594 
  15595 #if defined(BCM_88790_A0)
  15596     { /* SOC_REG_INT_QSPI_MSPI_CDRAM06_BCM88790_A0r */
  15597         soc_block_list[61],
  15598         soc_iprocreg,
  15599         1,
  15600         0,
  15601         0x18021358,
  15602         0,
  15603         0,
  15604         2,
  15605         soc_QSPI_MSPI_CDRAM06_BCM88790_A0r_fields,
  15606         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15607         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15608         -1,
  15609         -1,
  15610     },
  15611 #endif /* chips */
  15612 
  15613 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15614     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15615     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15616     defined(BCM_56260_B0)
  15617     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM53400_A0r */
  15618         soc_block_list[61],
  15619         soc_iprocreg,
  15620         1,
  15621         0,
  15622         0x1804735c,
  15623         0,
  15624         0,
  15625         2,
  15626         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15627         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15628         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15629         -1,
  15630         -1,
  15631     },
  15632 #endif /* chips */
  15633 
  15634 #if defined(BCM_56370_A0)
  15635     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM56370_A0r */
  15636         soc_block_list[61],
  15637         soc_iprocreg,
  15638         1,
  15639         0,
  15640         0x1500035c,
  15641         0,
  15642         0,
  15643         2,
  15644         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15645         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15646         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15647         -1,
  15648         -1,
  15649         3,
  15650     },
  15651 #endif /* chips */
  15652 
  15653 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15654     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15655     defined(BCM_56450_B1)
  15656     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM56450_A0r */
  15657         soc_block_list[61],
  15658         soc_iprocreg,
  15659         1,
  15660         0,
  15661         0x1802735c,
  15662         0,
  15663         0,
  15664         2,
  15665         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  15666         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15667         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15668         -1,
  15669         -1,
  15670     },
  15671 #endif /* chips */
  15672 
  15673 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  15674     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  15675     defined(BCM_56670_B0)
  15676     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM56560_A0r */
  15677         soc_block_list[61],
  15678         soc_iprocreg,
  15679         1,
  15680         0,
  15681         0x1802135c,
  15682         0,
  15683         0,
  15684         2,
  15685         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15686         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15687         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15688         -1,
  15689         -1,
  15690     },
  15691 #endif /* chips */
  15692 
  15693 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15694     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  15695     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  15696     defined(BCM_56980_B0)
  15697     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM56960_A0r */
  15698         soc_block_list[61],
  15699         soc_iprocreg,
  15700         1,
  15701         0,
  15702         0x1802135c,
  15703         0,
  15704         0,
  15705         2,
  15706         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15707         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15708         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15709         -1,
  15710         -1,
  15711         3,
  15712     },
  15713 #endif /* chips */
  15714 
  15715 #if defined(BCM_88270_A0)
  15716     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM88270_A0r */
  15717         soc_block_list[61],
  15718         soc_iprocreg,
  15719         1,
  15720         0,
  15721         0x1802135c,
  15722         0,
  15723         0,
  15724         2,
  15725         soc_QSPI_MSPI_CDRAM07_BCM88270_A0r_fields,
  15726         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15727         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15728         -1,
  15729         -1,
  15730     },
  15731 #endif /* chips */
  15732 
  15733 #if defined(BCM_88375_A0)
  15734     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM88375_A0r */
  15735         soc_block_list[61],
  15736         soc_iprocreg,
  15737         1,
  15738         0,
  15739         0x1802135c,
  15740         0,
  15741         0,
  15742         2,
  15743         soc_QSPI_MSPI_CDRAM07_BCM88375_A0r_fields,
  15744         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15745         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15746         -1,
  15747         -1,
  15748     },
  15749 #endif /* chips */
  15750 
  15751 #if defined(BCM_88375_B0)
  15752     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM88375_B0r */
  15753         soc_block_list[61],
  15754         soc_iprocreg,
  15755         1,
  15756         0,
  15757         0x1802135c,
  15758         0,
  15759         0,
  15760         2,
  15761         soc_QSPI_MSPI_CDRAM07_BCM88375_B0r_fields,
  15762         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15763         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15764         -1,
  15765         -1,
  15766     },
  15767 #endif /* chips */
  15768 
  15769 #if defined(BCM_88470_A0)
  15770     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM88470_A0r */
  15771         soc_block_list[61],
  15772         soc_iprocreg,
  15773         1,
  15774         0,
  15775         0x1802135c,
  15776         0,
  15777         0,
  15778         2,
  15779         soc_QSPI_MSPI_CDRAM07_BCM88470_A0r_fields,
  15780         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15781         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15782         -1,
  15783         -1,
  15784     },
  15785 #endif /* chips */
  15786 
  15787 #if defined(BCM_88470_B0)
  15788     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM88470_B0r */
  15789         soc_block_list[61],
  15790         soc_iprocreg,
  15791         1,
  15792         0,
  15793         0x1802135c,
  15794         0,
  15795         0,
  15796         2,
  15797         soc_QSPI_MSPI_CDRAM07_BCM88470_B0r_fields,
  15798         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15799         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15800         -1,
  15801         -1,
  15802     },
  15803 #endif /* chips */
  15804 
  15805 #if defined(BCM_88675_B0)
  15806     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM88675_B0r */
  15807         soc_block_list[61],
  15808         soc_iprocreg,
  15809         1,
  15810         0,
  15811         0x1802135c,
  15812         0,
  15813         0,
  15814         2,
  15815         soc_QSPI_MSPI_CDRAM07_BCM88675_B0r_fields,
  15816         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15817         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15818         -1,
  15819         -1,
  15820     },
  15821 #endif /* chips */
  15822 
  15823 #if defined(BCM_88680_A0)
  15824     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM88680_A0r */
  15825         soc_block_list[61],
  15826         soc_iprocreg,
  15827         1,
  15828         0,
  15829         0x1802135c,
  15830         0,
  15831         0,
  15832         2,
  15833         soc_QSPI_MSPI_CDRAM07_BCM88680_A0r_fields,
  15834         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15835         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15836         -1,
  15837         -1,
  15838     },
  15839 #endif /* chips */
  15840 
  15841 #if defined(BCM_88690_A0)
  15842     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM88690_A0r */
  15843         soc_block_list[61],
  15844         soc_iprocreg,
  15845         1,
  15846         0,
  15847         0x1802135c,
  15848         0,
  15849         0,
  15850         2,
  15851         soc_QSPI_MSPI_CDRAM07_BCM88690_A0r_fields,
  15852         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15853         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15854         -1,
  15855         -1,
  15856     },
  15857 #endif /* chips */
  15858 
  15859 #if defined(BCM_88690_B0)
  15860     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM88690_B0r */
  15861         soc_block_list[61],
  15862         soc_iprocreg,
  15863         1,
  15864         0,
  15865         0x1802135c,
  15866         0,
  15867         0,
  15868         2,
  15869         soc_QSPI_MSPI_CDRAM07_BCM88690_B0r_fields,
  15870         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15871         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15872         -1,
  15873         -1,
  15874     },
  15875 #endif /* chips */
  15876 
  15877 #if defined(BCM_88790_A0)
  15878     { /* SOC_REG_INT_QSPI_MSPI_CDRAM07_BCM88790_A0r */
  15879         soc_block_list[61],
  15880         soc_iprocreg,
  15881         1,
  15882         0,
  15883         0x1802135c,
  15884         0,
  15885         0,
  15886         2,
  15887         soc_QSPI_MSPI_CDRAM07_BCM88790_A0r_fields,
  15888         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15889         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15890         -1,
  15891         -1,
  15892     },
  15893 #endif /* chips */
  15894 
  15895 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  15896     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  15897     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  15898     defined(BCM_56260_B0)
  15899     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM53400_A0r */
  15900         soc_block_list[61],
  15901         soc_iprocreg,
  15902         1,
  15903         0,
  15904         0x18047360,
  15905         0,
  15906         0,
  15907         2,
  15908         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15909         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15910         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15911         -1,
  15912         -1,
  15913     },
  15914 #endif /* chips */
  15915 
  15916 #if defined(BCM_56370_A0)
  15917     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM56370_A0r */
  15918         soc_block_list[61],
  15919         soc_iprocreg,
  15920         1,
  15921         0,
  15922         0x15000360,
  15923         0,
  15924         0,
  15925         2,
  15926         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15927         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15928         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15929         -1,
  15930         -1,
  15931         3,
  15932     },
  15933 #endif /* chips */
  15934 
  15935 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  15936     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  15937     defined(BCM_56450_B1)
  15938     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM56450_A0r */
  15939         soc_block_list[61],
  15940         soc_iprocreg,
  15941         1,
  15942         0,
  15943         0x18027360,
  15944         0,
  15945         0,
  15946         2,
  15947         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  15948         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15949         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15950         -1,
  15951         -1,
  15952     },
  15953 #endif /* chips */
  15954 
  15955 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  15956     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  15957     defined(BCM_56670_B0)
  15958     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM56560_A0r */
  15959         soc_block_list[61],
  15960         soc_iprocreg,
  15961         1,
  15962         0,
  15963         0x18021360,
  15964         0,
  15965         0,
  15966         2,
  15967         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15968         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15969         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15970         -1,
  15971         -1,
  15972     },
  15973 #endif /* chips */
  15974 
  15975 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  15976     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  15977     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  15978     defined(BCM_56980_B0)
  15979     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM56960_A0r */
  15980         soc_block_list[61],
  15981         soc_iprocreg,
  15982         1,
  15983         0,
  15984         0x18021360,
  15985         0,
  15986         0,
  15987         2,
  15988         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  15989         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  15990         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15991         -1,
  15992         -1,
  15993         3,
  15994     },
  15995 #endif /* chips */
  15996 
  15997 #if defined(BCM_88270_A0)
  15998     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM88270_A0r */
  15999         soc_block_list[61],
  16000         soc_iprocreg,
  16001         1,
  16002         0,
  16003         0x18021360,
  16004         0,
  16005         0,
  16006         2,
  16007         soc_QSPI_MSPI_CDRAM08_BCM88270_A0r_fields,
  16008         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16009         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16010         -1,
  16011         -1,
  16012     },
  16013 #endif /* chips */
  16014 
  16015 #if defined(BCM_88375_A0)
  16016     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM88375_A0r */
  16017         soc_block_list[61],
  16018         soc_iprocreg,
  16019         1,
  16020         0,
  16021         0x18021360,
  16022         0,
  16023         0,
  16024         2,
  16025         soc_QSPI_MSPI_CDRAM08_BCM88375_A0r_fields,
  16026         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16028         -1,
  16029         -1,
  16030     },
  16031 #endif /* chips */
  16032 
  16033 #if defined(BCM_88375_B0)
  16034     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM88375_B0r */
  16035         soc_block_list[61],
  16036         soc_iprocreg,
  16037         1,
  16038         0,
  16039         0x18021360,
  16040         0,
  16041         0,
  16042         2,
  16043         soc_QSPI_MSPI_CDRAM08_BCM88375_B0r_fields,
  16044         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16045         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16046         -1,
  16047         -1,
  16048     },
  16049 #endif /* chips */
  16050 
  16051 #if defined(BCM_88470_A0)
  16052     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM88470_A0r */
  16053         soc_block_list[61],
  16054         soc_iprocreg,
  16055         1,
  16056         0,
  16057         0x18021360,
  16058         0,
  16059         0,
  16060         2,
  16061         soc_QSPI_MSPI_CDRAM08_BCM88470_A0r_fields,
  16062         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16063         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16064         -1,
  16065         -1,
  16066     },
  16067 #endif /* chips */
  16068 
  16069 #if defined(BCM_88470_B0)
  16070     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM88470_B0r */
  16071         soc_block_list[61],
  16072         soc_iprocreg,
  16073         1,
  16074         0,
  16075         0x18021360,
  16076         0,
  16077         0,
  16078         2,
  16079         soc_QSPI_MSPI_CDRAM08_BCM88470_B0r_fields,
  16080         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16081         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16082         -1,
  16083         -1,
  16084     },
  16085 #endif /* chips */
  16086 
  16087 #if defined(BCM_88675_B0)
  16088     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM88675_B0r */
  16089         soc_block_list[61],
  16090         soc_iprocreg,
  16091         1,
  16092         0,
  16093         0x18021360,
  16094         0,
  16095         0,
  16096         2,
  16097         soc_QSPI_MSPI_CDRAM08_BCM88675_B0r_fields,
  16098         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16099         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16100         -1,
  16101         -1,
  16102     },
  16103 #endif /* chips */
  16104 
  16105 #if defined(BCM_88680_A0)
  16106     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM88680_A0r */
  16107         soc_block_list[61],
  16108         soc_iprocreg,
  16109         1,
  16110         0,
  16111         0x18021360,
  16112         0,
  16113         0,
  16114         2,
  16115         soc_QSPI_MSPI_CDRAM08_BCM88680_A0r_fields,
  16116         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16117         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16118         -1,
  16119         -1,
  16120     },
  16121 #endif /* chips */
  16122 
  16123 #if defined(BCM_88690_A0)
  16124     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM88690_A0r */
  16125         soc_block_list[61],
  16126         soc_iprocreg,
  16127         1,
  16128         0,
  16129         0x18021360,
  16130         0,
  16131         0,
  16132         2,
  16133         soc_QSPI_MSPI_CDRAM08_BCM88690_A0r_fields,
  16134         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16135         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16136         -1,
  16137         -1,
  16138     },
  16139 #endif /* chips */
  16140 
  16141 #if defined(BCM_88690_B0)
  16142     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM88690_B0r */
  16143         soc_block_list[61],
  16144         soc_iprocreg,
  16145         1,
  16146         0,
  16147         0x18021360,
  16148         0,
  16149         0,
  16150         2,
  16151         soc_QSPI_MSPI_CDRAM08_BCM88690_B0r_fields,
  16152         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16153         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16154         -1,
  16155         -1,
  16156     },
  16157 #endif /* chips */
  16158 
  16159 #if defined(BCM_88790_A0)
  16160     { /* SOC_REG_INT_QSPI_MSPI_CDRAM08_BCM88790_A0r */
  16161         soc_block_list[61],
  16162         soc_iprocreg,
  16163         1,
  16164         0,
  16165         0x18021360,
  16166         0,
  16167         0,
  16168         2,
  16169         soc_QSPI_MSPI_CDRAM08_BCM88790_A0r_fields,
  16170         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16171         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16172         -1,
  16173         -1,
  16174     },
  16175 #endif /* chips */
  16176 
  16177 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16178     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16179     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16180     defined(BCM_56260_B0)
  16181     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM53400_A0r */
  16182         soc_block_list[61],
  16183         soc_iprocreg,
  16184         1,
  16185         0,
  16186         0x18047364,
  16187         0,
  16188         0,
  16189         2,
  16190         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16191         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16192         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16193         -1,
  16194         -1,
  16195     },
  16196 #endif /* chips */
  16197 
  16198 #if defined(BCM_56370_A0)
  16199     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM56370_A0r */
  16200         soc_block_list[61],
  16201         soc_iprocreg,
  16202         1,
  16203         0,
  16204         0x15000364,
  16205         0,
  16206         0,
  16207         2,
  16208         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16209         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16210         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16211         -1,
  16212         -1,
  16213         3,
  16214     },
  16215 #endif /* chips */
  16216 
  16217 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16218     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16219     defined(BCM_56450_B1)
  16220     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM56450_A0r */
  16221         soc_block_list[61],
  16222         soc_iprocreg,
  16223         1,
  16224         0,
  16225         0x18027364,
  16226         0,
  16227         0,
  16228         2,
  16229         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  16230         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16231         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16232         -1,
  16233         -1,
  16234     },
  16235 #endif /* chips */
  16236 
  16237 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  16238     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  16239     defined(BCM_56670_B0)
  16240     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM56560_A0r */
  16241         soc_block_list[61],
  16242         soc_iprocreg,
  16243         1,
  16244         0,
  16245         0x18021364,
  16246         0,
  16247         0,
  16248         2,
  16249         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16250         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16251         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16252         -1,
  16253         -1,
  16254     },
  16255 #endif /* chips */
  16256 
  16257 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16258     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  16259     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  16260     defined(BCM_56980_B0)
  16261     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM56960_A0r */
  16262         soc_block_list[61],
  16263         soc_iprocreg,
  16264         1,
  16265         0,
  16266         0x18021364,
  16267         0,
  16268         0,
  16269         2,
  16270         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16271         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16272         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16273         -1,
  16274         -1,
  16275         3,
  16276     },
  16277 #endif /* chips */
  16278 
  16279 #if defined(BCM_88270_A0)
  16280     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM88270_A0r */
  16281         soc_block_list[61],
  16282         soc_iprocreg,
  16283         1,
  16284         0,
  16285         0x18021364,
  16286         0,
  16287         0,
  16288         2,
  16289         soc_QSPI_MSPI_CDRAM09_BCM88270_A0r_fields,
  16290         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16291         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16292         -1,
  16293         -1,
  16294     },
  16295 #endif /* chips */
  16296 
  16297 #if defined(BCM_88375_A0)
  16298     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM88375_A0r */
  16299         soc_block_list[61],
  16300         soc_iprocreg,
  16301         1,
  16302         0,
  16303         0x18021364,
  16304         0,
  16305         0,
  16306         2,
  16307         soc_QSPI_MSPI_CDRAM09_BCM88375_A0r_fields,
  16308         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16309         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16310         -1,
  16311         -1,
  16312     },
  16313 #endif /* chips */
  16314 
  16315 #if defined(BCM_88375_B0)
  16316     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM88375_B0r */
  16317         soc_block_list[61],
  16318         soc_iprocreg,
  16319         1,
  16320         0,
  16321         0x18021364,
  16322         0,
  16323         0,
  16324         2,
  16325         soc_QSPI_MSPI_CDRAM09_BCM88375_B0r_fields,
  16326         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16327         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16328         -1,
  16329         -1,
  16330     },
  16331 #endif /* chips */
  16332 
  16333 #if defined(BCM_88470_A0)
  16334     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM88470_A0r */
  16335         soc_block_list[61],
  16336         soc_iprocreg,
  16337         1,
  16338         0,
  16339         0x18021364,
  16340         0,
  16341         0,
  16342         2,
  16343         soc_QSPI_MSPI_CDRAM09_BCM88470_A0r_fields,
  16344         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16346         -1,
  16347         -1,
  16348     },
  16349 #endif /* chips */
  16350 
  16351 #if defined(BCM_88470_B0)
  16352     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM88470_B0r */
  16353         soc_block_list[61],
  16354         soc_iprocreg,
  16355         1,
  16356         0,
  16357         0x18021364,
  16358         0,
  16359         0,
  16360         2,
  16361         soc_QSPI_MSPI_CDRAM09_BCM88470_B0r_fields,
  16362         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16363         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16364         -1,
  16365         -1,
  16366     },
  16367 #endif /* chips */
  16368 
  16369 #if defined(BCM_88675_B0)
  16370     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM88675_B0r */
  16371         soc_block_list[61],
  16372         soc_iprocreg,
  16373         1,
  16374         0,
  16375         0x18021364,
  16376         0,
  16377         0,
  16378         2,
  16379         soc_QSPI_MSPI_CDRAM09_BCM88675_B0r_fields,
  16380         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16382         -1,
  16383         -1,
  16384     },
  16385 #endif /* chips */
  16386 
  16387 #if defined(BCM_88680_A0)
  16388     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM88680_A0r */
  16389         soc_block_list[61],
  16390         soc_iprocreg,
  16391         1,
  16392         0,
  16393         0x18021364,
  16394         0,
  16395         0,
  16396         2,
  16397         soc_QSPI_MSPI_CDRAM09_BCM88680_A0r_fields,
  16398         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16399         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16400         -1,
  16401         -1,
  16402     },
  16403 #endif /* chips */
  16404 
  16405 #if defined(BCM_88690_A0)
  16406     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM88690_A0r */
  16407         soc_block_list[61],
  16408         soc_iprocreg,
  16409         1,
  16410         0,
  16411         0x18021364,
  16412         0,
  16413         0,
  16414         2,
  16415         soc_QSPI_MSPI_CDRAM09_BCM88690_A0r_fields,
  16416         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16418         -1,
  16419         -1,
  16420     },
  16421 #endif /* chips */
  16422 
  16423 #if defined(BCM_88690_B0)
  16424     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM88690_B0r */
  16425         soc_block_list[61],
  16426         soc_iprocreg,
  16427         1,
  16428         0,
  16429         0x18021364,
  16430         0,
  16431         0,
  16432         2,
  16433         soc_QSPI_MSPI_CDRAM09_BCM88690_B0r_fields,
  16434         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16435         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16436         -1,
  16437         -1,
  16438     },
  16439 #endif /* chips */
  16440 
  16441 #if defined(BCM_88790_A0)
  16442     { /* SOC_REG_INT_QSPI_MSPI_CDRAM09_BCM88790_A0r */
  16443         soc_block_list[61],
  16444         soc_iprocreg,
  16445         1,
  16446         0,
  16447         0x18021364,
  16448         0,
  16449         0,
  16450         2,
  16451         soc_QSPI_MSPI_CDRAM09_BCM88790_A0r_fields,
  16452         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16454         -1,
  16455         -1,
  16456     },
  16457 #endif /* chips */
  16458 
  16459 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16460     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16461     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16462     defined(BCM_56260_B0)
  16463     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM53400_A0r */
  16464         soc_block_list[61],
  16465         soc_iprocreg,
  16466         1,
  16467         0,
  16468         0x18047368,
  16469         0,
  16470         0,
  16471         2,
  16472         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16473         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16474         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16475         -1,
  16476         -1,
  16477     },
  16478 #endif /* chips */
  16479 
  16480 #if defined(BCM_56370_A0)
  16481     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM56370_A0r */
  16482         soc_block_list[61],
  16483         soc_iprocreg,
  16484         1,
  16485         0,
  16486         0x15000368,
  16487         0,
  16488         0,
  16489         2,
  16490         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16491         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16492         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16493         -1,
  16494         -1,
  16495         3,
  16496     },
  16497 #endif /* chips */
  16498 
  16499 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16500     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16501     defined(BCM_56450_B1)
  16502     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM56450_A0r */
  16503         soc_block_list[61],
  16504         soc_iprocreg,
  16505         1,
  16506         0,
  16507         0x18027368,
  16508         0,
  16509         0,
  16510         2,
  16511         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  16512         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16513         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16514         -1,
  16515         -1,
  16516     },
  16517 #endif /* chips */
  16518 
  16519 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  16520     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  16521     defined(BCM_56670_B0)
  16522     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM56560_A0r */
  16523         soc_block_list[61],
  16524         soc_iprocreg,
  16525         1,
  16526         0,
  16527         0x18021368,
  16528         0,
  16529         0,
  16530         2,
  16531         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16532         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16534         -1,
  16535         -1,
  16536     },
  16537 #endif /* chips */
  16538 
  16539 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16540     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  16541     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  16542     defined(BCM_56980_B0)
  16543     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM56960_A0r */
  16544         soc_block_list[61],
  16545         soc_iprocreg,
  16546         1,
  16547         0,
  16548         0x18021368,
  16549         0,
  16550         0,
  16551         2,
  16552         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16553         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16554         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16555         -1,
  16556         -1,
  16557         3,
  16558     },
  16559 #endif /* chips */
  16560 
  16561 #if defined(BCM_88270_A0)
  16562     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM88270_A0r */
  16563         soc_block_list[61],
  16564         soc_iprocreg,
  16565         1,
  16566         0,
  16567         0x18021368,
  16568         0,
  16569         0,
  16570         2,
  16571         soc_QSPI_MSPI_CDRAM10_BCM88270_A0r_fields,
  16572         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16573         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16574         -1,
  16575         -1,
  16576     },
  16577 #endif /* chips */
  16578 
  16579 #if defined(BCM_88375_A0)
  16580     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM88375_A0r */
  16581         soc_block_list[61],
  16582         soc_iprocreg,
  16583         1,
  16584         0,
  16585         0x18021368,
  16586         0,
  16587         0,
  16588         2,
  16589         soc_QSPI_MSPI_CDRAM10_BCM88375_A0r_fields,
  16590         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16591         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16592         -1,
  16593         -1,
  16594     },
  16595 #endif /* chips */
  16596 
  16597 #if defined(BCM_88375_B0)
  16598     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM88375_B0r */
  16599         soc_block_list[61],
  16600         soc_iprocreg,
  16601         1,
  16602         0,
  16603         0x18021368,
  16604         0,
  16605         0,
  16606         2,
  16607         soc_QSPI_MSPI_CDRAM10_BCM88375_B0r_fields,
  16608         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16609         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16610         -1,
  16611         -1,
  16612     },
  16613 #endif /* chips */
  16614 
  16615 #if defined(BCM_88470_A0)
  16616     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM88470_A0r */
  16617         soc_block_list[61],
  16618         soc_iprocreg,
  16619         1,
  16620         0,
  16621         0x18021368,
  16622         0,
  16623         0,
  16624         2,
  16625         soc_QSPI_MSPI_CDRAM10_BCM88470_A0r_fields,
  16626         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16627         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16628         -1,
  16629         -1,
  16630     },
  16631 #endif /* chips */
  16632 
  16633 #if defined(BCM_88470_B0)
  16634     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM88470_B0r */
  16635         soc_block_list[61],
  16636         soc_iprocreg,
  16637         1,
  16638         0,
  16639         0x18021368,
  16640         0,
  16641         0,
  16642         2,
  16643         soc_QSPI_MSPI_CDRAM10_BCM88470_B0r_fields,
  16644         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16646         -1,
  16647         -1,
  16648     },
  16649 #endif /* chips */
  16650 
  16651 #if defined(BCM_88675_B0)
  16652     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM88675_B0r */
  16653         soc_block_list[61],
  16654         soc_iprocreg,
  16655         1,
  16656         0,
  16657         0x18021368,
  16658         0,
  16659         0,
  16660         2,
  16661         soc_QSPI_MSPI_CDRAM10_BCM88675_B0r_fields,
  16662         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16663         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16664         -1,
  16665         -1,
  16666     },
  16667 #endif /* chips */
  16668 
  16669 #if defined(BCM_88680_A0)
  16670     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM88680_A0r */
  16671         soc_block_list[61],
  16672         soc_iprocreg,
  16673         1,
  16674         0,
  16675         0x18021368,
  16676         0,
  16677         0,
  16678         2,
  16679         soc_QSPI_MSPI_CDRAM10_BCM88680_A0r_fields,
  16680         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16681         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16682         -1,
  16683         -1,
  16684     },
  16685 #endif /* chips */
  16686 
  16687 #if defined(BCM_88690_A0)
  16688     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM88690_A0r */
  16689         soc_block_list[61],
  16690         soc_iprocreg,
  16691         1,
  16692         0,
  16693         0x18021368,
  16694         0,
  16695         0,
  16696         2,
  16697         soc_QSPI_MSPI_CDRAM10_BCM88690_A0r_fields,
  16698         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16699         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16700         -1,
  16701         -1,
  16702     },
  16703 #endif /* chips */
  16704 
  16705 #if defined(BCM_88690_B0)
  16706     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM88690_B0r */
  16707         soc_block_list[61],
  16708         soc_iprocreg,
  16709         1,
  16710         0,
  16711         0x18021368,
  16712         0,
  16713         0,
  16714         2,
  16715         soc_QSPI_MSPI_CDRAM10_BCM88690_B0r_fields,
  16716         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16718         -1,
  16719         -1,
  16720     },
  16721 #endif /* chips */
  16722 
  16723 #if defined(BCM_88790_A0)
  16724     { /* SOC_REG_INT_QSPI_MSPI_CDRAM10_BCM88790_A0r */
  16725         soc_block_list[61],
  16726         soc_iprocreg,
  16727         1,
  16728         0,
  16729         0x18021368,
  16730         0,
  16731         0,
  16732         2,
  16733         soc_QSPI_MSPI_CDRAM10_BCM88790_A0r_fields,
  16734         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16736         -1,
  16737         -1,
  16738     },
  16739 #endif /* chips */
  16740 
  16741 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  16742     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  16743     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  16744     defined(BCM_56260_B0)
  16745     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM53400_A0r */
  16746         soc_block_list[61],
  16747         soc_iprocreg,
  16748         1,
  16749         0,
  16750         0x1804736c,
  16751         0,
  16752         0,
  16753         2,
  16754         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16755         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16757         -1,
  16758         -1,
  16759     },
  16760 #endif /* chips */
  16761 
  16762 #if defined(BCM_56370_A0)
  16763     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM56370_A0r */
  16764         soc_block_list[61],
  16765         soc_iprocreg,
  16766         1,
  16767         0,
  16768         0x1500036c,
  16769         0,
  16770         0,
  16771         2,
  16772         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16773         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16774         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16775         -1,
  16776         -1,
  16777         3,
  16778     },
  16779 #endif /* chips */
  16780 
  16781 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  16782     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  16783     defined(BCM_56450_B1)
  16784     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM56450_A0r */
  16785         soc_block_list[61],
  16786         soc_iprocreg,
  16787         1,
  16788         0,
  16789         0x1802736c,
  16790         0,
  16791         0,
  16792         2,
  16793         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  16794         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16796         -1,
  16797         -1,
  16798     },
  16799 #endif /* chips */
  16800 
  16801 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  16802     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  16803     defined(BCM_56670_B0)
  16804     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM56560_A0r */
  16805         soc_block_list[61],
  16806         soc_iprocreg,
  16807         1,
  16808         0,
  16809         0x1802136c,
  16810         0,
  16811         0,
  16812         2,
  16813         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16814         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16815         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16816         -1,
  16817         -1,
  16818     },
  16819 #endif /* chips */
  16820 
  16821 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  16822     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  16823     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  16824     defined(BCM_56980_B0)
  16825     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM56960_A0r */
  16826         soc_block_list[61],
  16827         soc_iprocreg,
  16828         1,
  16829         0,
  16830         0x1802136c,
  16831         0,
  16832         0,
  16833         2,
  16834         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  16835         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16837         -1,
  16838         -1,
  16839         3,
  16840     },
  16841 #endif /* chips */
  16842 
  16843 #if defined(BCM_88270_A0)
  16844     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM88270_A0r */
  16845         soc_block_list[61],
  16846         soc_iprocreg,
  16847         1,
  16848         0,
  16849         0x1802136c,
  16850         0,
  16851         0,
  16852         2,
  16853         soc_QSPI_MSPI_CDRAM11_BCM88270_A0r_fields,
  16854         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16855         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16856         -1,
  16857         -1,
  16858     },
  16859 #endif /* chips */
  16860 
  16861 #if defined(BCM_88375_A0)
  16862     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM88375_A0r */
  16863         soc_block_list[61],
  16864         soc_iprocreg,
  16865         1,
  16866         0,
  16867         0x1802136c,
  16868         0,
  16869         0,
  16870         2,
  16871         soc_QSPI_MSPI_CDRAM11_BCM88375_A0r_fields,
  16872         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16873         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16874         -1,
  16875         -1,
  16876     },
  16877 #endif /* chips */
  16878 
  16879 #if defined(BCM_88375_B0)
  16880     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM88375_B0r */
  16881         soc_block_list[61],
  16882         soc_iprocreg,
  16883         1,
  16884         0,
  16885         0x1802136c,
  16886         0,
  16887         0,
  16888         2,
  16889         soc_QSPI_MSPI_CDRAM11_BCM88375_B0r_fields,
  16890         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16891         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16892         -1,
  16893         -1,
  16894     },
  16895 #endif /* chips */
  16896 
  16897 #if defined(BCM_88470_A0)
  16898     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM88470_A0r */
  16899         soc_block_list[61],
  16900         soc_iprocreg,
  16901         1,
  16902         0,
  16903         0x1802136c,
  16904         0,
  16905         0,
  16906         2,
  16907         soc_QSPI_MSPI_CDRAM11_BCM88470_A0r_fields,
  16908         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16909         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16910         -1,
  16911         -1,
  16912     },
  16913 #endif /* chips */
  16914 
  16915 #if defined(BCM_88470_B0)
  16916     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM88470_B0r */
  16917         soc_block_list[61],
  16918         soc_iprocreg,
  16919         1,
  16920         0,
  16921         0x1802136c,
  16922         0,
  16923         0,
  16924         2,
  16925         soc_QSPI_MSPI_CDRAM11_BCM88470_B0r_fields,
  16926         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16927         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16928         -1,
  16929         -1,
  16930     },
  16931 #endif /* chips */
  16932 
  16933 #if defined(BCM_88675_B0)
  16934     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM88675_B0r */
  16935         soc_block_list[61],
  16936         soc_iprocreg,
  16937         1,
  16938         0,
  16939         0x1802136c,
  16940         0,
  16941         0,
  16942         2,
  16943         soc_QSPI_MSPI_CDRAM11_BCM88675_B0r_fields,
  16944         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16946         -1,
  16947         -1,
  16948     },
  16949 #endif /* chips */
  16950 
  16951 #if defined(BCM_88680_A0)
  16952     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM88680_A0r */
  16953         soc_block_list[61],
  16954         soc_iprocreg,
  16955         1,
  16956         0,
  16957         0x1802136c,
  16958         0,
  16959         0,
  16960         2,
  16961         soc_QSPI_MSPI_CDRAM11_BCM88680_A0r_fields,
  16962         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16964         -1,
  16965         -1,
  16966     },
  16967 #endif /* chips */
  16968 
  16969 #if defined(BCM_88690_A0)
  16970     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM88690_A0r */
  16971         soc_block_list[61],
  16972         soc_iprocreg,
  16973         1,
  16974         0,
  16975         0x1802136c,
  16976         0,
  16977         0,
  16978         2,
  16979         soc_QSPI_MSPI_CDRAM11_BCM88690_A0r_fields,
  16980         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16981         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16982         -1,
  16983         -1,
  16984     },
  16985 #endif /* chips */
  16986 
  16987 #if defined(BCM_88690_B0)
  16988     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM88690_B0r */
  16989         soc_block_list[61],
  16990         soc_iprocreg,
  16991         1,
  16992         0,
  16993         0x1802136c,
  16994         0,
  16995         0,
  16996         2,
  16997         soc_QSPI_MSPI_CDRAM11_BCM88690_B0r_fields,
  16998         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  16999         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17000         -1,
  17001         -1,
  17002     },
  17003 #endif /* chips */
  17004 
  17005 #if defined(BCM_88790_A0)
  17006     { /* SOC_REG_INT_QSPI_MSPI_CDRAM11_BCM88790_A0r */
  17007         soc_block_list[61],
  17008         soc_iprocreg,
  17009         1,
  17010         0,
  17011         0x1802136c,
  17012         0,
  17013         0,
  17014         2,
  17015         soc_QSPI_MSPI_CDRAM11_BCM88790_A0r_fields,
  17016         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17018         -1,
  17019         -1,
  17020     },
  17021 #endif /* chips */
  17022 
  17023 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17024     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17025     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17026     defined(BCM_56260_B0)
  17027     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM53400_A0r */
  17028         soc_block_list[61],
  17029         soc_iprocreg,
  17030         1,
  17031         0,
  17032         0x18047370,
  17033         0,
  17034         0,
  17035         2,
  17036         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17037         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17038         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17039         -1,
  17040         -1,
  17041     },
  17042 #endif /* chips */
  17043 
  17044 #if defined(BCM_56370_A0)
  17045     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM56370_A0r */
  17046         soc_block_list[61],
  17047         soc_iprocreg,
  17048         1,
  17049         0,
  17050         0x15000370,
  17051         0,
  17052         0,
  17053         2,
  17054         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17055         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17056         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17057         -1,
  17058         -1,
  17059         3,
  17060     },
  17061 #endif /* chips */
  17062 
  17063 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17064     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17065     defined(BCM_56450_B1)
  17066     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM56450_A0r */
  17067         soc_block_list[61],
  17068         soc_iprocreg,
  17069         1,
  17070         0,
  17071         0x18027370,
  17072         0,
  17073         0,
  17074         2,
  17075         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  17076         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17078         -1,
  17079         -1,
  17080     },
  17081 #endif /* chips */
  17082 
  17083 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  17084     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  17085     defined(BCM_56670_B0)
  17086     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM56560_A0r */
  17087         soc_block_list[61],
  17088         soc_iprocreg,
  17089         1,
  17090         0,
  17091         0x18021370,
  17092         0,
  17093         0,
  17094         2,
  17095         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17096         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17098         -1,
  17099         -1,
  17100     },
  17101 #endif /* chips */
  17102 
  17103 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  17104     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  17105     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  17106     defined(BCM_56980_B0)
  17107     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM56960_A0r */
  17108         soc_block_list[61],
  17109         soc_iprocreg,
  17110         1,
  17111         0,
  17112         0x18021370,
  17113         0,
  17114         0,
  17115         2,
  17116         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17117         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17118         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17119         -1,
  17120         -1,
  17121         3,
  17122     },
  17123 #endif /* chips */
  17124 
  17125 #if defined(BCM_88270_A0)
  17126     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM88270_A0r */
  17127         soc_block_list[61],
  17128         soc_iprocreg,
  17129         1,
  17130         0,
  17131         0x18021370,
  17132         0,
  17133         0,
  17134         2,
  17135         soc_QSPI_MSPI_CDRAM12_BCM88270_A0r_fields,
  17136         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17138         -1,
  17139         -1,
  17140     },
  17141 #endif /* chips */
  17142 
  17143 #if defined(BCM_88375_A0)
  17144     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM88375_A0r */
  17145         soc_block_list[61],
  17146         soc_iprocreg,
  17147         1,
  17148         0,
  17149         0x18021370,
  17150         0,
  17151         0,
  17152         2,
  17153         soc_QSPI_MSPI_CDRAM12_BCM88375_A0r_fields,
  17154         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17156         -1,
  17157         -1,
  17158     },
  17159 #endif /* chips */
  17160 
  17161 #if defined(BCM_88375_B0)
  17162     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM88375_B0r */
  17163         soc_block_list[61],
  17164         soc_iprocreg,
  17165         1,
  17166         0,
  17167         0x18021370,
  17168         0,
  17169         0,
  17170         2,
  17171         soc_QSPI_MSPI_CDRAM12_BCM88375_B0r_fields,
  17172         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17173         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17174         -1,
  17175         -1,
  17176     },
  17177 #endif /* chips */
  17178 
  17179 #if defined(BCM_88470_A0)
  17180     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM88470_A0r */
  17181         soc_block_list[61],
  17182         soc_iprocreg,
  17183         1,
  17184         0,
  17185         0x18021370,
  17186         0,
  17187         0,
  17188         2,
  17189         soc_QSPI_MSPI_CDRAM12_BCM88470_A0r_fields,
  17190         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17191         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17192         -1,
  17193         -1,
  17194     },
  17195 #endif /* chips */
  17196 
  17197 #if defined(BCM_88470_B0)
  17198     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM88470_B0r */
  17199         soc_block_list[61],
  17200         soc_iprocreg,
  17201         1,
  17202         0,
  17203         0x18021370,
  17204         0,
  17205         0,
  17206         2,
  17207         soc_QSPI_MSPI_CDRAM12_BCM88470_B0r_fields,
  17208         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17209         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17210         -1,
  17211         -1,
  17212     },
  17213 #endif /* chips */
  17214 
  17215 #if defined(BCM_88675_B0)
  17216     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM88675_B0r */
  17217         soc_block_list[61],
  17218         soc_iprocreg,
  17219         1,
  17220         0,
  17221         0x18021370,
  17222         0,
  17223         0,
  17224         2,
  17225         soc_QSPI_MSPI_CDRAM12_BCM88675_B0r_fields,
  17226         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17227         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17228         -1,
  17229         -1,
  17230     },
  17231 #endif /* chips */
  17232 
  17233 #if defined(BCM_88680_A0)
  17234     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM88680_A0r */
  17235         soc_block_list[61],
  17236         soc_iprocreg,
  17237         1,
  17238         0,
  17239         0x18021370,
  17240         0,
  17241         0,
  17242         2,
  17243         soc_QSPI_MSPI_CDRAM12_BCM88680_A0r_fields,
  17244         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17246         -1,
  17247         -1,
  17248     },
  17249 #endif /* chips */
  17250 
  17251 #if defined(BCM_88690_A0)
  17252     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM88690_A0r */
  17253         soc_block_list[61],
  17254         soc_iprocreg,
  17255         1,
  17256         0,
  17257         0x18021370,
  17258         0,
  17259         0,
  17260         2,
  17261         soc_QSPI_MSPI_CDRAM12_BCM88690_A0r_fields,
  17262         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17264         -1,
  17265         -1,
  17266     },
  17267 #endif /* chips */
  17268 
  17269 #if defined(BCM_88690_B0)
  17270     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM88690_B0r */
  17271         soc_block_list[61],
  17272         soc_iprocreg,
  17273         1,
  17274         0,
  17275         0x18021370,
  17276         0,
  17277         0,
  17278         2,
  17279         soc_QSPI_MSPI_CDRAM12_BCM88690_B0r_fields,
  17280         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17281         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17282         -1,
  17283         -1,
  17284     },
  17285 #endif /* chips */
  17286 
  17287 #if defined(BCM_88790_A0)
  17288     { /* SOC_REG_INT_QSPI_MSPI_CDRAM12_BCM88790_A0r */
  17289         soc_block_list[61],
  17290         soc_iprocreg,
  17291         1,
  17292         0,
  17293         0x18021370,
  17294         0,
  17295         0,
  17296         2,
  17297         soc_QSPI_MSPI_CDRAM12_BCM88790_A0r_fields,
  17298         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17300         -1,
  17301         -1,
  17302     },
  17303 #endif /* chips */
  17304 
  17305 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17306     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17307     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17308     defined(BCM_56260_B0)
  17309     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM53400_A0r */
  17310         soc_block_list[61],
  17311         soc_iprocreg,
  17312         1,
  17313         0,
  17314         0x18047374,
  17315         0,
  17316         0,
  17317         2,
  17318         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17319         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17320         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17321         -1,
  17322         -1,
  17323     },
  17324 #endif /* chips */
  17325 
  17326 #if defined(BCM_56370_A0)
  17327     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM56370_A0r */
  17328         soc_block_list[61],
  17329         soc_iprocreg,
  17330         1,
  17331         0,
  17332         0x15000374,
  17333         0,
  17334         0,
  17335         2,
  17336         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17337         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17338         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17339         -1,
  17340         -1,
  17341         3,
  17342     },
  17343 #endif /* chips */
  17344 
  17345 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17346     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17347     defined(BCM_56450_B1)
  17348     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM56450_A0r */
  17349         soc_block_list[61],
  17350         soc_iprocreg,
  17351         1,
  17352         0,
  17353         0x18027374,
  17354         0,
  17355         0,
  17356         2,
  17357         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  17358         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17359         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17360         -1,
  17361         -1,
  17362     },
  17363 #endif /* chips */
  17364 
  17365 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  17366     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  17367     defined(BCM_56670_B0)
  17368     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM56560_A0r */
  17369         soc_block_list[61],
  17370         soc_iprocreg,
  17371         1,
  17372         0,
  17373         0x18021374,
  17374         0,
  17375         0,
  17376         2,
  17377         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17378         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17379         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17380         -1,
  17381         -1,
  17382     },
  17383 #endif /* chips */
  17384 
  17385 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  17386     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  17387     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  17388     defined(BCM_56980_B0)
  17389     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM56960_A0r */
  17390         soc_block_list[61],
  17391         soc_iprocreg,
  17392         1,
  17393         0,
  17394         0x18021374,
  17395         0,
  17396         0,
  17397         2,
  17398         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17399         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17400         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17401         -1,
  17402         -1,
  17403         3,
  17404     },
  17405 #endif /* chips */
  17406 
  17407 #if defined(BCM_88270_A0)
  17408     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM88270_A0r */
  17409         soc_block_list[61],
  17410         soc_iprocreg,
  17411         1,
  17412         0,
  17413         0x18021374,
  17414         0,
  17415         0,
  17416         2,
  17417         soc_QSPI_MSPI_CDRAM13_BCM88270_A0r_fields,
  17418         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17420         -1,
  17421         -1,
  17422     },
  17423 #endif /* chips */
  17424 
  17425 #if defined(BCM_88375_A0)
  17426     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM88375_A0r */
  17427         soc_block_list[61],
  17428         soc_iprocreg,
  17429         1,
  17430         0,
  17431         0x18021374,
  17432         0,
  17433         0,
  17434         2,
  17435         soc_QSPI_MSPI_CDRAM13_BCM88375_A0r_fields,
  17436         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17437         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17438         -1,
  17439         -1,
  17440     },
  17441 #endif /* chips */
  17442 
  17443 #if defined(BCM_88375_B0)
  17444     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM88375_B0r */
  17445         soc_block_list[61],
  17446         soc_iprocreg,
  17447         1,
  17448         0,
  17449         0x18021374,
  17450         0,
  17451         0,
  17452         2,
  17453         soc_QSPI_MSPI_CDRAM13_BCM88375_B0r_fields,
  17454         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17455         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17456         -1,
  17457         -1,
  17458     },
  17459 #endif /* chips */
  17460 
  17461 #if defined(BCM_88470_A0)
  17462     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM88470_A0r */
  17463         soc_block_list[61],
  17464         soc_iprocreg,
  17465         1,
  17466         0,
  17467         0x18021374,
  17468         0,
  17469         0,
  17470         2,
  17471         soc_QSPI_MSPI_CDRAM13_BCM88470_A0r_fields,
  17472         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17473         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17474         -1,
  17475         -1,
  17476     },
  17477 #endif /* chips */
  17478 
  17479 #if defined(BCM_88470_B0)
  17480     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM88470_B0r */
  17481         soc_block_list[61],
  17482         soc_iprocreg,
  17483         1,
  17484         0,
  17485         0x18021374,
  17486         0,
  17487         0,
  17488         2,
  17489         soc_QSPI_MSPI_CDRAM13_BCM88470_B0r_fields,
  17490         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17491         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17492         -1,
  17493         -1,
  17494     },
  17495 #endif /* chips */
  17496 
  17497 #if defined(BCM_88675_B0)
  17498     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM88675_B0r */
  17499         soc_block_list[61],
  17500         soc_iprocreg,
  17501         1,
  17502         0,
  17503         0x18021374,
  17504         0,
  17505         0,
  17506         2,
  17507         soc_QSPI_MSPI_CDRAM13_BCM88675_B0r_fields,
  17508         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17509         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17510         -1,
  17511         -1,
  17512     },
  17513 #endif /* chips */
  17514 
  17515 #if defined(BCM_88680_A0)
  17516     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM88680_A0r */
  17517         soc_block_list[61],
  17518         soc_iprocreg,
  17519         1,
  17520         0,
  17521         0x18021374,
  17522         0,
  17523         0,
  17524         2,
  17525         soc_QSPI_MSPI_CDRAM13_BCM88680_A0r_fields,
  17526         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17527         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17528         -1,
  17529         -1,
  17530     },
  17531 #endif /* chips */
  17532 
  17533 #if defined(BCM_88690_A0)
  17534     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM88690_A0r */
  17535         soc_block_list[61],
  17536         soc_iprocreg,
  17537         1,
  17538         0,
  17539         0x18021374,
  17540         0,
  17541         0,
  17542         2,
  17543         soc_QSPI_MSPI_CDRAM13_BCM88690_A0r_fields,
  17544         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17545         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17546         -1,
  17547         -1,
  17548     },
  17549 #endif /* chips */
  17550 
  17551 #if defined(BCM_88690_B0)
  17552     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM88690_B0r */
  17553         soc_block_list[61],
  17554         soc_iprocreg,
  17555         1,
  17556         0,
  17557         0x18021374,
  17558         0,
  17559         0,
  17560         2,
  17561         soc_QSPI_MSPI_CDRAM13_BCM88690_B0r_fields,
  17562         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17563         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17564         -1,
  17565         -1,
  17566     },
  17567 #endif /* chips */
  17568 
  17569 #if defined(BCM_88790_A0)
  17570     { /* SOC_REG_INT_QSPI_MSPI_CDRAM13_BCM88790_A0r */
  17571         soc_block_list[61],
  17572         soc_iprocreg,
  17573         1,
  17574         0,
  17575         0x18021374,
  17576         0,
  17577         0,
  17578         2,
  17579         soc_QSPI_MSPI_CDRAM13_BCM88790_A0r_fields,
  17580         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17581         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17582         -1,
  17583         -1,
  17584     },
  17585 #endif /* chips */
  17586 
  17587 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17588     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17589     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17590     defined(BCM_56260_B0)
  17591     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM53400_A0r */
  17592         soc_block_list[61],
  17593         soc_iprocreg,
  17594         1,
  17595         0,
  17596         0x18047378,
  17597         0,
  17598         0,
  17599         2,
  17600         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17601         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17602         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17603         -1,
  17604         -1,
  17605     },
  17606 #endif /* chips */
  17607 
  17608 #if defined(BCM_56370_A0)
  17609     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM56370_A0r */
  17610         soc_block_list[61],
  17611         soc_iprocreg,
  17612         1,
  17613         0,
  17614         0x15000378,
  17615         0,
  17616         0,
  17617         2,
  17618         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17619         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17620         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17621         -1,
  17622         -1,
  17623         3,
  17624     },
  17625 #endif /* chips */
  17626 
  17627 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17628     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17629     defined(BCM_56450_B1)
  17630     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM56450_A0r */
  17631         soc_block_list[61],
  17632         soc_iprocreg,
  17633         1,
  17634         0,
  17635         0x18027378,
  17636         0,
  17637         0,
  17638         2,
  17639         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  17640         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17641         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17642         -1,
  17643         -1,
  17644     },
  17645 #endif /* chips */
  17646 
  17647 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  17648     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  17649     defined(BCM_56670_B0)
  17650     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM56560_A0r */
  17651         soc_block_list[61],
  17652         soc_iprocreg,
  17653         1,
  17654         0,
  17655         0x18021378,
  17656         0,
  17657         0,
  17658         2,
  17659         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17660         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17661         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17662         -1,
  17663         -1,
  17664     },
  17665 #endif /* chips */
  17666 
  17667 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  17668     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  17669     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  17670     defined(BCM_56980_B0)
  17671     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM56960_A0r */
  17672         soc_block_list[61],
  17673         soc_iprocreg,
  17674         1,
  17675         0,
  17676         0x18021378,
  17677         0,
  17678         0,
  17679         2,
  17680         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17681         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17682         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17683         -1,
  17684         -1,
  17685         3,
  17686     },
  17687 #endif /* chips */
  17688 
  17689 #if defined(BCM_88270_A0)
  17690     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM88270_A0r */
  17691         soc_block_list[61],
  17692         soc_iprocreg,
  17693         1,
  17694         0,
  17695         0x18021378,
  17696         0,
  17697         0,
  17698         2,
  17699         soc_QSPI_MSPI_CDRAM14_BCM88270_A0r_fields,
  17700         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17701         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17702         -1,
  17703         -1,
  17704     },
  17705 #endif /* chips */
  17706 
  17707 #if defined(BCM_88375_A0)
  17708     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM88375_A0r */
  17709         soc_block_list[61],
  17710         soc_iprocreg,
  17711         1,
  17712         0,
  17713         0x18021378,
  17714         0,
  17715         0,
  17716         2,
  17717         soc_QSPI_MSPI_CDRAM14_BCM88375_A0r_fields,
  17718         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17719         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17720         -1,
  17721         -1,
  17722     },
  17723 #endif /* chips */
  17724 
  17725 #if defined(BCM_88375_B0)
  17726     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM88375_B0r */
  17727         soc_block_list[61],
  17728         soc_iprocreg,
  17729         1,
  17730         0,
  17731         0x18021378,
  17732         0,
  17733         0,
  17734         2,
  17735         soc_QSPI_MSPI_CDRAM14_BCM88375_B0r_fields,
  17736         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17737         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17738         -1,
  17739         -1,
  17740     },
  17741 #endif /* chips */
  17742 
  17743 #if defined(BCM_88470_A0)
  17744     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM88470_A0r */
  17745         soc_block_list[61],
  17746         soc_iprocreg,
  17747         1,
  17748         0,
  17749         0x18021378,
  17750         0,
  17751         0,
  17752         2,
  17753         soc_QSPI_MSPI_CDRAM14_BCM88470_A0r_fields,
  17754         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17755         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17756         -1,
  17757         -1,
  17758     },
  17759 #endif /* chips */
  17760 
  17761 #if defined(BCM_88470_B0)
  17762     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM88470_B0r */
  17763         soc_block_list[61],
  17764         soc_iprocreg,
  17765         1,
  17766         0,
  17767         0x18021378,
  17768         0,
  17769         0,
  17770         2,
  17771         soc_QSPI_MSPI_CDRAM14_BCM88470_B0r_fields,
  17772         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17773         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17774         -1,
  17775         -1,
  17776     },
  17777 #endif /* chips */
  17778 
  17779 #if defined(BCM_88675_B0)
  17780     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM88675_B0r */
  17781         soc_block_list[61],
  17782         soc_iprocreg,
  17783         1,
  17784         0,
  17785         0x18021378,
  17786         0,
  17787         0,
  17788         2,
  17789         soc_QSPI_MSPI_CDRAM14_BCM88675_B0r_fields,
  17790         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17791         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17792         -1,
  17793         -1,
  17794     },
  17795 #endif /* chips */
  17796 
  17797 #if defined(BCM_88680_A0)
  17798     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM88680_A0r */
  17799         soc_block_list[61],
  17800         soc_iprocreg,
  17801         1,
  17802         0,
  17803         0x18021378,
  17804         0,
  17805         0,
  17806         2,
  17807         soc_QSPI_MSPI_CDRAM14_BCM88680_A0r_fields,
  17808         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17809         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17810         -1,
  17811         -1,
  17812     },
  17813 #endif /* chips */
  17814 
  17815 #if defined(BCM_88690_A0)
  17816     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM88690_A0r */
  17817         soc_block_list[61],
  17818         soc_iprocreg,
  17819         1,
  17820         0,
  17821         0x18021378,
  17822         0,
  17823         0,
  17824         2,
  17825         soc_QSPI_MSPI_CDRAM14_BCM88690_A0r_fields,
  17826         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17827         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17828         -1,
  17829         -1,
  17830     },
  17831 #endif /* chips */
  17832 
  17833 #if defined(BCM_88690_B0)
  17834     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM88690_B0r */
  17835         soc_block_list[61],
  17836         soc_iprocreg,
  17837         1,
  17838         0,
  17839         0x18021378,
  17840         0,
  17841         0,
  17842         2,
  17843         soc_QSPI_MSPI_CDRAM14_BCM88690_B0r_fields,
  17844         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17845         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17846         -1,
  17847         -1,
  17848     },
  17849 #endif /* chips */
  17850 
  17851 #if defined(BCM_88790_A0)
  17852     { /* SOC_REG_INT_QSPI_MSPI_CDRAM14_BCM88790_A0r */
  17853         soc_block_list[61],
  17854         soc_iprocreg,
  17855         1,
  17856         0,
  17857         0x18021378,
  17858         0,
  17859         0,
  17860         2,
  17861         soc_QSPI_MSPI_CDRAM14_BCM88790_A0r_fields,
  17862         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17863         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17864         -1,
  17865         -1,
  17866     },
  17867 #endif /* chips */
  17868 
  17869 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  17870     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  17871     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  17872     defined(BCM_56260_B0)
  17873     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM53400_A0r */
  17874         soc_block_list[61],
  17875         soc_iprocreg,
  17876         1,
  17877         0,
  17878         0x1804737c,
  17879         0,
  17880         0,
  17881         2,
  17882         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17883         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17884         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17885         -1,
  17886         -1,
  17887     },
  17888 #endif /* chips */
  17889 
  17890 #if defined(BCM_56370_A0)
  17891     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM56370_A0r */
  17892         soc_block_list[61],
  17893         soc_iprocreg,
  17894         1,
  17895         0,
  17896         0x1500037c,
  17897         0,
  17898         0,
  17899         2,
  17900         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17901         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17902         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17903         -1,
  17904         -1,
  17905         3,
  17906     },
  17907 #endif /* chips */
  17908 
  17909 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  17910     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  17911     defined(BCM_56450_B1)
  17912     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM56450_A0r */
  17913         soc_block_list[61],
  17914         soc_iprocreg,
  17915         1,
  17916         0,
  17917         0x1802737c,
  17918         0,
  17919         0,
  17920         2,
  17921         soc_QSPI_MSPI_CDRAM00_BCM56450_A0r_fields,
  17922         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17923         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17924         -1,
  17925         -1,
  17926     },
  17927 #endif /* chips */
  17928 
  17929 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  17930     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  17931     defined(BCM_56670_B0)
  17932     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM56560_A0r */
  17933         soc_block_list[61],
  17934         soc_iprocreg,
  17935         1,
  17936         0,
  17937         0x1802137c,
  17938         0,
  17939         0,
  17940         2,
  17941         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17942         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17943         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17944         -1,
  17945         -1,
  17946     },
  17947 #endif /* chips */
  17948 
  17949 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  17950     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  17951     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  17952     defined(BCM_56980_B0)
  17953     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM56960_A0r */
  17954         soc_block_list[61],
  17955         soc_iprocreg,
  17956         1,
  17957         0,
  17958         0x1802137c,
  17959         0,
  17960         0,
  17961         2,
  17962         soc_QSPI_MSPI_CDRAM00_BCM53400_A0r_fields,
  17963         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17964         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17965         -1,
  17966         -1,
  17967         3,
  17968     },
  17969 #endif /* chips */
  17970 
  17971 #if defined(BCM_88270_A0)
  17972     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM88270_A0r */
  17973         soc_block_list[61],
  17974         soc_iprocreg,
  17975         1,
  17976         0,
  17977         0x1802137c,
  17978         0,
  17979         0,
  17980         2,
  17981         soc_QSPI_MSPI_CDRAM15_BCM88270_A0r_fields,
  17982         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  17983         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17984         -1,
  17985         -1,
  17986     },
  17987 #endif /* chips */
  17988 
  17989 #if defined(BCM_88375_A0)
  17990     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM88375_A0r */
  17991         soc_block_list[61],
  17992         soc_iprocreg,
  17993         1,
  17994         0,
  17995         0x1802137c,
  17996         0,
  17997         0,
  17998         2,
  17999         soc_QSPI_MSPI_CDRAM15_BCM88375_A0r_fields,
  18000         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  18001         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18002         -1,
  18003         -1,
  18004     },
  18005 #endif /* chips */
  18006 
  18007 #if defined(BCM_88375_B0)
  18008     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM88375_B0r */
  18009         soc_block_list[61],
  18010         soc_iprocreg,
  18011         1,
  18012         0,
  18013         0x1802137c,
  18014         0,
  18015         0,
  18016         2,
  18017         soc_QSPI_MSPI_CDRAM15_BCM88375_B0r_fields,
  18018         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  18019         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18020         -1,
  18021         -1,
  18022     },
  18023 #endif /* chips */
  18024 
  18025 #if defined(BCM_88470_A0)
  18026     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM88470_A0r */
  18027         soc_block_list[61],
  18028         soc_iprocreg,
  18029         1,
  18030         0,
  18031         0x1802137c,
  18032         0,
  18033         0,
  18034         2,
  18035         soc_QSPI_MSPI_CDRAM15_BCM88470_A0r_fields,
  18036         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  18037         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18038         -1,
  18039         -1,
  18040     },
  18041 #endif /* chips */
  18042 
  18043 #if defined(BCM_88470_B0)
  18044     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM88470_B0r */
  18045         soc_block_list[61],
  18046         soc_iprocreg,
  18047         1,
  18048         0,
  18049         0x1802137c,
  18050         0,
  18051         0,
  18052         2,
  18053         soc_QSPI_MSPI_CDRAM15_BCM88470_B0r_fields,
  18054         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  18055         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18056         -1,
  18057         -1,
  18058     },
  18059 #endif /* chips */
  18060 
  18061 #if defined(BCM_88675_B0)
  18062     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM88675_B0r */
  18063         soc_block_list[61],
  18064         soc_iprocreg,
  18065         1,
  18066         0,
  18067         0x1802137c,
  18068         0,
  18069         0,
  18070         2,
  18071         soc_QSPI_MSPI_CDRAM15_BCM88675_B0r_fields,
  18072         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  18073         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18074         -1,
  18075         -1,
  18076     },
  18077 #endif /* chips */
  18078 
  18079 #if defined(BCM_88680_A0)
  18080     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM88680_A0r */
  18081         soc_block_list[61],
  18082         soc_iprocreg,
  18083         1,
  18084         0,
  18085         0x1802137c,
  18086         0,
  18087         0,
  18088         2,
  18089         soc_QSPI_MSPI_CDRAM15_BCM88680_A0r_fields,
  18090         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  18091         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18092         -1,
  18093         -1,
  18094     },
  18095 #endif /* chips */
  18096 
  18097 #if defined(BCM_88690_A0)
  18098     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM88690_A0r */
  18099         soc_block_list[61],
  18100         soc_iprocreg,
  18101         1,
  18102         0,
  18103         0x1802137c,
  18104         0,
  18105         0,
  18106         2,
  18107         soc_QSPI_MSPI_CDRAM15_BCM88690_A0r_fields,
  18108         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  18109         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18110         -1,
  18111         -1,
  18112     },
  18113 #endif /* chips */
  18114 
  18115 #if defined(BCM_88690_B0)
  18116     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM88690_B0r */
  18117         soc_block_list[61],
  18118         soc_iprocreg,
  18119         1,
  18120         0,
  18121         0x1802137c,
  18122         0,
  18123         0,
  18124         2,
  18125         soc_QSPI_MSPI_CDRAM15_BCM88690_B0r_fields,
  18126         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  18127         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18128         -1,
  18129         -1,
  18130     },
  18131 #endif /* chips */
  18132 
  18133 #if defined(BCM_88790_A0)
  18134     { /* SOC_REG_INT_QSPI_MSPI_CDRAM15_BCM88790_A0r */
  18135         soc_block_list[61],
  18136         soc_iprocreg,
  18137         1,
  18138         0,
  18139         0x1802137c,
  18140         0,
  18141         0,
  18142         2,
  18143         soc_QSPI_MSPI_CDRAM15_BCM88790_A0r_fields,
  18144         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  18145         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18146         -1,
  18147         -1,
  18148     },
  18149 #endif /* chips */
  18150 
  18151 #if defined(BCM_88675_A0)
  18152     { /* SOC_REG_INT_QSPI_MSPI_CPTQPr */
  18153         soc_block_list[61],
  18154         soc_iprocreg,
  18155         1,
  18156         0,
  18157         0x18021224,
  18158         SOC_REG_FLAG_RO,
  18159         0,
  18160         2,
  18161         soc_QSPI_MSPI_CPTQPr_fields,
  18162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18163         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18164         -1,
  18165         -1,
  18166     },
  18167 #endif /* chips */
  18168 
  18169 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18170     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18171     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18172     defined(BCM_56260_B0)
  18173     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM53400_A0r */
  18174         soc_block_list[61],
  18175         soc_iprocreg,
  18176         1,
  18177         0,
  18178         0x18047224,
  18179         SOC_REG_FLAG_RO,
  18180         0,
  18181         2,
  18182         soc_QSPI_MSPI_CPTQP_BCM53400_A0r_fields,
  18183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18184         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18185         -1,
  18186         -1,
  18187     },
  18188 #endif /* chips */
  18189 
  18190 #if defined(BCM_56370_A0)
  18191     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM56370_A0r */
  18192         soc_block_list[61],
  18193         soc_iprocreg,
  18194         1,
  18195         0,
  18196         0x15000224,
  18197         SOC_REG_FLAG_RO,
  18198         0,
  18199         2,
  18200         soc_QSPI_MSPI_CPTQP_BCM53400_A0r_fields,
  18201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18202         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18203         -1,
  18204         -1,
  18205         3,
  18206     },
  18207 #endif /* chips */
  18208 
  18209 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  18210     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18211     defined(BCM_56450_B1)
  18212     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM56450_A0r */
  18213         soc_block_list[61],
  18214         soc_iprocreg,
  18215         1,
  18216         0,
  18217         0x18027224,
  18218         SOC_REG_FLAG_RO,
  18219         0,
  18220         2,
  18221         soc_QSPI_MSPI_CPTQP_BCM56450_A0r_fields,
  18222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18223         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18224         -1,
  18225         -1,
  18226     },
  18227 #endif /* chips */
  18228 
  18229 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  18230     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  18231     defined(BCM_56670_B0)
  18232     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM56560_A0r */
  18233         soc_block_list[61],
  18234         soc_iprocreg,
  18235         1,
  18236         0,
  18237         0x18021224,
  18238         SOC_REG_FLAG_RO,
  18239         0,
  18240         2,
  18241         soc_QSPI_MSPI_CPTQP_BCM53400_A0r_fields,
  18242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18243         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18244         -1,
  18245         -1,
  18246     },
  18247 #endif /* chips */
  18248 
  18249 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  18250     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  18251     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  18252     defined(BCM_56980_B0)
  18253     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM56960_A0r */
  18254         soc_block_list[61],
  18255         soc_iprocreg,
  18256         1,
  18257         0,
  18258         0x18021224,
  18259         SOC_REG_FLAG_RO,
  18260         0,
  18261         2,
  18262         soc_QSPI_MSPI_CPTQP_BCM53400_A0r_fields,
  18263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18264         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18265         -1,
  18266         -1,
  18267         3,
  18268     },
  18269 #endif /* chips */
  18270 
  18271 #if defined(BCM_88270_A0)
  18272     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM88270_A0r */
  18273         soc_block_list[61],
  18274         soc_iprocreg,
  18275         1,
  18276         0,
  18277         0x18021224,
  18278         SOC_REG_FLAG_RO,
  18279         0,
  18280         2,
  18281         soc_QSPI_MSPI_CPTQP_BCM88270_A0r_fields,
  18282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18283         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18284         -1,
  18285         -1,
  18286     },
  18287 #endif /* chips */
  18288 
  18289 #if defined(BCM_88375_A0)
  18290     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM88375_A0r */
  18291         soc_block_list[61],
  18292         soc_iprocreg,
  18293         1,
  18294         0,
  18295         0x18021224,
  18296         SOC_REG_FLAG_RO,
  18297         0,
  18298         2,
  18299         soc_QSPI_MSPI_CPTQP_BCM88375_A0r_fields,
  18300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18301         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18302         -1,
  18303         -1,
  18304     },
  18305 #endif /* chips */
  18306 
  18307 #if defined(BCM_88375_B0)
  18308     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM88375_B0r */
  18309         soc_block_list[61],
  18310         soc_iprocreg,
  18311         1,
  18312         0,
  18313         0x18021224,
  18314         SOC_REG_FLAG_RO,
  18315         0,
  18316         2,
  18317         soc_QSPI_MSPI_CPTQP_BCM88375_B0r_fields,
  18318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18319         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18320         -1,
  18321         -1,
  18322     },
  18323 #endif /* chips */
  18324 
  18325 #if defined(BCM_88470_A0)
  18326     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM88470_A0r */
  18327         soc_block_list[61],
  18328         soc_iprocreg,
  18329         1,
  18330         0,
  18331         0x18021224,
  18332         SOC_REG_FLAG_RO,
  18333         0,
  18334         2,
  18335         soc_QSPI_MSPI_CPTQP_BCM88470_A0r_fields,
  18336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18337         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18338         -1,
  18339         -1,
  18340     },
  18341 #endif /* chips */
  18342 
  18343 #if defined(BCM_88470_B0)
  18344     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM88470_B0r */
  18345         soc_block_list[61],
  18346         soc_iprocreg,
  18347         1,
  18348         0,
  18349         0x18021224,
  18350         SOC_REG_FLAG_RO,
  18351         0,
  18352         2,
  18353         soc_QSPI_MSPI_CPTQP_BCM88470_B0r_fields,
  18354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18355         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18356         -1,
  18357         -1,
  18358     },
  18359 #endif /* chips */
  18360 
  18361 #if defined(BCM_88675_B0)
  18362     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM88675_B0r */
  18363         soc_block_list[61],
  18364         soc_iprocreg,
  18365         1,
  18366         0,
  18367         0x18021224,
  18368         SOC_REG_FLAG_RO,
  18369         0,
  18370         2,
  18371         soc_QSPI_MSPI_CPTQP_BCM88675_B0r_fields,
  18372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18373         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18374         -1,
  18375         -1,
  18376     },
  18377 #endif /* chips */
  18378 
  18379 #if defined(BCM_88680_A0)
  18380     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM88680_A0r */
  18381         soc_block_list[61],
  18382         soc_iprocreg,
  18383         1,
  18384         0,
  18385         0x18021224,
  18386         SOC_REG_FLAG_RO,
  18387         0,
  18388         2,
  18389         soc_QSPI_MSPI_CPTQP_BCM88680_A0r_fields,
  18390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18391         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18392         -1,
  18393         -1,
  18394     },
  18395 #endif /* chips */
  18396 
  18397 #if defined(BCM_88690_A0)
  18398     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM88690_A0r */
  18399         soc_block_list[61],
  18400         soc_iprocreg,
  18401         1,
  18402         0,
  18403         0x18021224,
  18404         SOC_REG_FLAG_RO,
  18405         0,
  18406         2,
  18407         soc_QSPI_MSPI_CPTQP_BCM88690_A0r_fields,
  18408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18409         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18410         -1,
  18411         -1,
  18412     },
  18413 #endif /* chips */
  18414 
  18415 #if defined(BCM_88690_B0)
  18416     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM88690_B0r */
  18417         soc_block_list[61],
  18418         soc_iprocreg,
  18419         1,
  18420         0,
  18421         0x18021224,
  18422         SOC_REG_FLAG_RO,
  18423         0,
  18424         2,
  18425         soc_QSPI_MSPI_CPTQP_BCM88690_B0r_fields,
  18426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18428         -1,
  18429         -1,
  18430     },
  18431 #endif /* chips */
  18432 
  18433 #if defined(BCM_88790_A0)
  18434     { /* SOC_REG_INT_QSPI_MSPI_CPTQP_BCM88790_A0r */
  18435         soc_block_list[61],
  18436         soc_iprocreg,
  18437         1,
  18438         0,
  18439         0x18021224,
  18440         SOC_REG_FLAG_RO,
  18441         0,
  18442         2,
  18443         soc_QSPI_MSPI_CPTQP_BCM88790_A0r_fields,
  18444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18446         -1,
  18447         -1,
  18448     },
  18449 #endif /* chips */
  18450 
  18451 #if defined(BCM_88675_A0)
  18452     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GENr */
  18453         soc_block_list[61],
  18454         soc_iprocreg,
  18455         1,
  18456         0,
  18457         0x18021384,
  18458         0,
  18459         0,
  18460         2,
  18461         soc_QSPI_MSPI_DISABLE_FLUSH_GENr_fields,
  18462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18463         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18464         -1,
  18465         -1,
  18466     },
  18467 #endif /* chips */
  18468 
  18469 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18470     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18471     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18472     defined(BCM_56260_B0)
  18473     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM53400_A0r */
  18474         soc_block_list[61],
  18475         soc_iprocreg,
  18476         1,
  18477         0,
  18478         0x18047384,
  18479         0,
  18480         0,
  18481         2,
  18482         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM53400_A0r_fields,
  18483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18484         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18485         -1,
  18486         -1,
  18487     },
  18488 #endif /* chips */
  18489 
  18490 #if defined(BCM_56370_A0)
  18491     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM56370_A0r */
  18492         soc_block_list[61],
  18493         soc_iprocreg,
  18494         1,
  18495         0,
  18496         0x15000384,
  18497         0,
  18498         0,
  18499         2,
  18500         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM53400_A0r_fields,
  18501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18502         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18503         -1,
  18504         -1,
  18505         3,
  18506     },
  18507 #endif /* chips */
  18508 
  18509 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  18510     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18511     defined(BCM_56450_B1)
  18512     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM56450_A0r */
  18513         soc_block_list[61],
  18514         soc_iprocreg,
  18515         1,
  18516         0,
  18517         0x18027384,
  18518         0,
  18519         0,
  18520         2,
  18521         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM56450_A0r_fields,
  18522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18523         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18524         -1,
  18525         -1,
  18526     },
  18527 #endif /* chips */
  18528 
  18529 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  18530     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  18531     defined(BCM_56670_B0)
  18532     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM56560_A0r */
  18533         soc_block_list[61],
  18534         soc_iprocreg,
  18535         1,
  18536         0,
  18537         0x18021384,
  18538         0,
  18539         0,
  18540         2,
  18541         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM53400_A0r_fields,
  18542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18544         -1,
  18545         -1,
  18546     },
  18547 #endif /* chips */
  18548 
  18549 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  18550     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  18551     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  18552     defined(BCM_56980_B0)
  18553     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM56960_A0r */
  18554         soc_block_list[61],
  18555         soc_iprocreg,
  18556         1,
  18557         0,
  18558         0x18021384,
  18559         0,
  18560         0,
  18561         2,
  18562         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM53400_A0r_fields,
  18563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18564         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18565         -1,
  18566         -1,
  18567         3,
  18568     },
  18569 #endif /* chips */
  18570 
  18571 #if defined(BCM_88270_A0)
  18572     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88270_A0r */
  18573         soc_block_list[61],
  18574         soc_iprocreg,
  18575         1,
  18576         0,
  18577         0x18021384,
  18578         0,
  18579         0,
  18580         2,
  18581         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88270_A0r_fields,
  18582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18583         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18584         -1,
  18585         -1,
  18586     },
  18587 #endif /* chips */
  18588 
  18589 #if defined(BCM_88375_A0)
  18590     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88375_A0r */
  18591         soc_block_list[61],
  18592         soc_iprocreg,
  18593         1,
  18594         0,
  18595         0x18021384,
  18596         0,
  18597         0,
  18598         2,
  18599         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88375_A0r_fields,
  18600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18601         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18602         -1,
  18603         -1,
  18604     },
  18605 #endif /* chips */
  18606 
  18607 #if defined(BCM_88375_B0)
  18608     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88375_B0r */
  18609         soc_block_list[61],
  18610         soc_iprocreg,
  18611         1,
  18612         0,
  18613         0x18021384,
  18614         0,
  18615         0,
  18616         2,
  18617         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88375_B0r_fields,
  18618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18619         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18620         -1,
  18621         -1,
  18622     },
  18623 #endif /* chips */
  18624 
  18625 #if defined(BCM_88470_A0)
  18626     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88470_A0r */
  18627         soc_block_list[61],
  18628         soc_iprocreg,
  18629         1,
  18630         0,
  18631         0x18021384,
  18632         0,
  18633         0,
  18634         2,
  18635         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88470_A0r_fields,
  18636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18637         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18638         -1,
  18639         -1,
  18640     },
  18641 #endif /* chips */
  18642 
  18643 #if defined(BCM_88470_B0)
  18644     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88470_B0r */
  18645         soc_block_list[61],
  18646         soc_iprocreg,
  18647         1,
  18648         0,
  18649         0x18021384,
  18650         0,
  18651         0,
  18652         2,
  18653         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88470_B0r_fields,
  18654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18655         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18656         -1,
  18657         -1,
  18658     },
  18659 #endif /* chips */
  18660 
  18661 #if defined(BCM_88675_B0)
  18662     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88675_B0r */
  18663         soc_block_list[61],
  18664         soc_iprocreg,
  18665         1,
  18666         0,
  18667         0x18021384,
  18668         0,
  18669         0,
  18670         2,
  18671         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88675_B0r_fields,
  18672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18673         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18674         -1,
  18675         -1,
  18676     },
  18677 #endif /* chips */
  18678 
  18679 #if defined(BCM_88680_A0)
  18680     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88680_A0r */
  18681         soc_block_list[61],
  18682         soc_iprocreg,
  18683         1,
  18684         0,
  18685         0x18021384,
  18686         0,
  18687         0,
  18688         2,
  18689         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88680_A0r_fields,
  18690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18691         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18692         -1,
  18693         -1,
  18694     },
  18695 #endif /* chips */
  18696 
  18697 #if defined(BCM_88690_A0)
  18698     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88690_A0r */
  18699         soc_block_list[61],
  18700         soc_iprocreg,
  18701         1,
  18702         0,
  18703         0x18021384,
  18704         0,
  18705         0,
  18706         2,
  18707         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88690_A0r_fields,
  18708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18709         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18710         -1,
  18711         -1,
  18712     },
  18713 #endif /* chips */
  18714 
  18715 #if defined(BCM_88690_B0)
  18716     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88690_B0r */
  18717         soc_block_list[61],
  18718         soc_iprocreg,
  18719         1,
  18720         0,
  18721         0x18021384,
  18722         0,
  18723         0,
  18724         2,
  18725         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88690_B0r_fields,
  18726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18727         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18728         -1,
  18729         -1,
  18730     },
  18731 #endif /* chips */
  18732 
  18733 #if defined(BCM_88790_A0)
  18734     { /* SOC_REG_INT_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88790_A0r */
  18735         soc_block_list[61],
  18736         soc_iprocreg,
  18737         1,
  18738         0,
  18739         0x18021384,
  18740         0,
  18741         0,
  18742         2,
  18743         soc_QSPI_MSPI_DISABLE_FLUSH_GEN_BCM88790_A0r_fields,
  18744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18745         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18746         -1,
  18747         -1,
  18748     },
  18749 #endif /* chips */
  18750 
  18751 #if defined(BCM_88675_A0)
  18752     { /* SOC_REG_INT_QSPI_MSPI_ENDQPr */
  18753         soc_block_list[61],
  18754         soc_iprocreg,
  18755         1,
  18756         0,
  18757         0x18021214,
  18758         0,
  18759         0,
  18760         2,
  18761         soc_QSPI_MSPI_ENDQPr_fields,
  18762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18763         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18764         -1,
  18765         -1,
  18766     },
  18767 #endif /* chips */
  18768 
  18769 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  18770     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  18771     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  18772     defined(BCM_56260_B0)
  18773     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM53400_A0r */
  18774         soc_block_list[61],
  18775         soc_iprocreg,
  18776         1,
  18777         0,
  18778         0x18047214,
  18779         0,
  18780         0,
  18781         2,
  18782         soc_QSPI_MSPI_ENDQP_BCM53400_A0r_fields,
  18783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18784         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18785         -1,
  18786         -1,
  18787     },
  18788 #endif /* chips */
  18789 
  18790 #if defined(BCM_56370_A0)
  18791     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM56370_A0r */
  18792         soc_block_list[61],
  18793         soc_iprocreg,
  18794         1,
  18795         0,
  18796         0x15000214,
  18797         0,
  18798         0,
  18799         2,
  18800         soc_QSPI_MSPI_ENDQP_BCM53400_A0r_fields,
  18801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18802         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18803         -1,
  18804         -1,
  18805         3,
  18806     },
  18807 #endif /* chips */
  18808 
  18809 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  18810     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  18811     defined(BCM_56450_B1)
  18812     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM56450_A0r */
  18813         soc_block_list[61],
  18814         soc_iprocreg,
  18815         1,
  18816         0,
  18817         0x18027214,
  18818         0,
  18819         0,
  18820         2,
  18821         soc_QSPI_MSPI_ENDQP_BCM56450_A0r_fields,
  18822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18823         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18824         -1,
  18825         -1,
  18826     },
  18827 #endif /* chips */
  18828 
  18829 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  18830     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  18831     defined(BCM_56670_B0)
  18832     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM56560_A0r */
  18833         soc_block_list[61],
  18834         soc_iprocreg,
  18835         1,
  18836         0,
  18837         0x18021214,
  18838         0,
  18839         0,
  18840         2,
  18841         soc_QSPI_MSPI_ENDQP_BCM53400_A0r_fields,
  18842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18843         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18844         -1,
  18845         -1,
  18846     },
  18847 #endif /* chips */
  18848 
  18849 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  18850     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  18851     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  18852     defined(BCM_56980_B0)
  18853     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM56960_A0r */
  18854         soc_block_list[61],
  18855         soc_iprocreg,
  18856         1,
  18857         0,
  18858         0x18021214,
  18859         0,
  18860         0,
  18861         2,
  18862         soc_QSPI_MSPI_ENDQP_BCM53400_A0r_fields,
  18863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18864         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18865         -1,
  18866         -1,
  18867         3,
  18868     },
  18869 #endif /* chips */
  18870 
  18871 #if defined(BCM_88270_A0)
  18872     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM88270_A0r */
  18873         soc_block_list[61],
  18874         soc_iprocreg,
  18875         1,
  18876         0,
  18877         0x18021214,
  18878         0,
  18879         0,
  18880         2,
  18881         soc_QSPI_MSPI_ENDQP_BCM88270_A0r_fields,
  18882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18883         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18884         -1,
  18885         -1,
  18886     },
  18887 #endif /* chips */
  18888 
  18889 #if defined(BCM_88375_A0)
  18890     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM88375_A0r */
  18891         soc_block_list[61],
  18892         soc_iprocreg,
  18893         1,
  18894         0,
  18895         0x18021214,
  18896         0,
  18897         0,
  18898         2,
  18899         soc_QSPI_MSPI_ENDQP_BCM88375_A0r_fields,
  18900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18901         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18902         -1,
  18903         -1,
  18904     },
  18905 #endif /* chips */
  18906 
  18907 #if defined(BCM_88375_B0)
  18908     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM88375_B0r */
  18909         soc_block_list[61],
  18910         soc_iprocreg,
  18911         1,
  18912         0,
  18913         0x18021214,
  18914         0,
  18915         0,
  18916         2,
  18917         soc_QSPI_MSPI_ENDQP_BCM88375_B0r_fields,
  18918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18919         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18920         -1,
  18921         -1,
  18922     },
  18923 #endif /* chips */
  18924 
  18925 #if defined(BCM_88470_A0)
  18926     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM88470_A0r */
  18927         soc_block_list[61],
  18928         soc_iprocreg,
  18929         1,
  18930         0,
  18931         0x18021214,
  18932         0,
  18933         0,
  18934         2,
  18935         soc_QSPI_MSPI_ENDQP_BCM88470_A0r_fields,
  18936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18937         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18938         -1,
  18939         -1,
  18940     },
  18941 #endif /* chips */
  18942 
  18943 #if defined(BCM_88470_B0)
  18944     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM88470_B0r */
  18945         soc_block_list[61],
  18946         soc_iprocreg,
  18947         1,
  18948         0,
  18949         0x18021214,
  18950         0,
  18951         0,
  18952         2,
  18953         soc_QSPI_MSPI_ENDQP_BCM88470_B0r_fields,
  18954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18956         -1,
  18957         -1,
  18958     },
  18959 #endif /* chips */
  18960 
  18961 #if defined(BCM_88675_B0)
  18962     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM88675_B0r */
  18963         soc_block_list[61],
  18964         soc_iprocreg,
  18965         1,
  18966         0,
  18967         0x18021214,
  18968         0,
  18969         0,
  18970         2,
  18971         soc_QSPI_MSPI_ENDQP_BCM88675_B0r_fields,
  18972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18973         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18974         -1,
  18975         -1,
  18976     },
  18977 #endif /* chips */
  18978 
  18979 #if defined(BCM_88680_A0)
  18980     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM88680_A0r */
  18981         soc_block_list[61],
  18982         soc_iprocreg,
  18983         1,
  18984         0,
  18985         0x18021214,
  18986         0,
  18987         0,
  18988         2,
  18989         soc_QSPI_MSPI_ENDQP_BCM88680_A0r_fields,
  18990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18991         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18992         -1,
  18993         -1,
  18994     },
  18995 #endif /* chips */
  18996 
  18997 #if defined(BCM_88690_A0)
  18998     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM88690_A0r */
  18999         soc_block_list[61],
  19000         soc_iprocreg,
  19001         1,
  19002         0,
  19003         0x18021214,
  19004         0,
  19005         0,
  19006         2,
  19007         soc_QSPI_MSPI_ENDQP_BCM88690_A0r_fields,
  19008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19009         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19010         -1,
  19011         -1,
  19012     },
  19013 #endif /* chips */
  19014 
  19015 #if defined(BCM_88690_B0)
  19016     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM88690_B0r */
  19017         soc_block_list[61],
  19018         soc_iprocreg,
  19019         1,
  19020         0,
  19021         0x18021214,
  19022         0,
  19023         0,
  19024         2,
  19025         soc_QSPI_MSPI_ENDQP_BCM88690_B0r_fields,
  19026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19028         -1,
  19029         -1,
  19030     },
  19031 #endif /* chips */
  19032 
  19033 #if defined(BCM_88790_A0)
  19034     { /* SOC_REG_INT_QSPI_MSPI_ENDQP_BCM88790_A0r */
  19035         soc_block_list[61],
  19036         soc_iprocreg,
  19037         1,
  19038         0,
  19039         0x18021214,
  19040         0,
  19041         0,
  19042         2,
  19043         soc_QSPI_MSPI_ENDQP_BCM88790_A0r_fields,
  19044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19045         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19046         -1,
  19047         -1,
  19048     },
  19049 #endif /* chips */
  19050 
  19051 #if defined(BCM_88675_A0)
  19052     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONEr */
  19053         soc_block_list[61],
  19054         soc_iprocreg,
  19055         1,
  19056         0,
  19057         0x180213b4,
  19058         0,
  19059         0,
  19060         1,
  19061         soc_QSPI_MSPI_INTERRUPT_MSPI_DONEr_fields,
  19062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19063         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19064         -1,
  19065         -1,
  19066     },
  19067 #endif /* chips */
  19068 
  19069 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19070     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19071     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19072     defined(BCM_56260_B0)
  19073     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM53400_A0r */
  19074         soc_block_list[61],
  19075         soc_iprocreg,
  19076         1,
  19077         0,
  19078         0x180473b4,
  19079         0,
  19080         0,
  19081         1,
  19082         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM53400_A0r_fields,
  19083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19084         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19085         -1,
  19086         -1,
  19087     },
  19088 #endif /* chips */
  19089 
  19090 #if defined(BCM_56370_A0)
  19091     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM56370_A0r */
  19092         soc_block_list[61],
  19093         soc_iprocreg,
  19094         1,
  19095         0,
  19096         0x150003b4,
  19097         0,
  19098         0,
  19099         1,
  19100         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM53400_A0r_fields,
  19101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19102         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19103         -1,
  19104         -1,
  19105         3,
  19106     },
  19107 #endif /* chips */
  19108 
  19109 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  19110     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  19111     defined(BCM_56450_B1)
  19112     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM56450_A0r */
  19113         soc_block_list[61],
  19114         soc_iprocreg,
  19115         1,
  19116         0,
  19117         0x180273b4,
  19118         0,
  19119         0,
  19120         1,
  19121         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM56450_A0r_fields,
  19122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19123         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19124         -1,
  19125         -1,
  19126     },
  19127 #endif /* chips */
  19128 
  19129 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  19130     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  19131     defined(BCM_56670_B0)
  19132     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM56560_A0r */
  19133         soc_block_list[61],
  19134         soc_iprocreg,
  19135         1,
  19136         0,
  19137         0x180213b4,
  19138         0,
  19139         0,
  19140         1,
  19141         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM53400_A0r_fields,
  19142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19143         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19144         -1,
  19145         -1,
  19146     },
  19147 #endif /* chips */
  19148 
  19149 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  19150     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  19151     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  19152     defined(BCM_56980_B0)
  19153     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM56960_A0r */
  19154         soc_block_list[61],
  19155         soc_iprocreg,
  19156         1,
  19157         0,
  19158         0x180213b4,
  19159         0,
  19160         0,
  19161         1,
  19162         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM53400_A0r_fields,
  19163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19164         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19165         -1,
  19166         -1,
  19167         3,
  19168     },
  19169 #endif /* chips */
  19170 
  19171 #if defined(BCM_88270_A0)
  19172     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88270_A0r */
  19173         soc_block_list[61],
  19174         soc_iprocreg,
  19175         1,
  19176         0,
  19177         0x180213b4,
  19178         0,
  19179         0,
  19180         1,
  19181         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88270_A0r_fields,
  19182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19183         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19184         -1,
  19185         -1,
  19186     },
  19187 #endif /* chips */
  19188 
  19189 #if defined(BCM_88375_A0)
  19190     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88375_A0r */
  19191         soc_block_list[61],
  19192         soc_iprocreg,
  19193         1,
  19194         0,
  19195         0x180213b4,
  19196         0,
  19197         0,
  19198         1,
  19199         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88375_A0r_fields,
  19200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19201         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19202         -1,
  19203         -1,
  19204     },
  19205 #endif /* chips */
  19206 
  19207 #if defined(BCM_88375_B0)
  19208     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88375_B0r */
  19209         soc_block_list[61],
  19210         soc_iprocreg,
  19211         1,
  19212         0,
  19213         0x180213b4,
  19214         0,
  19215         0,
  19216         1,
  19217         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88375_B0r_fields,
  19218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19219         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19220         -1,
  19221         -1,
  19222     },
  19223 #endif /* chips */
  19224 
  19225 #if defined(BCM_88470_A0)
  19226     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88470_A0r */
  19227         soc_block_list[61],
  19228         soc_iprocreg,
  19229         1,
  19230         0,
  19231         0x180213b4,
  19232         0,
  19233         0,
  19234         1,
  19235         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88470_A0r_fields,
  19236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19237         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19238         -1,
  19239         -1,
  19240     },
  19241 #endif /* chips */
  19242 
  19243 #if defined(BCM_88470_B0)
  19244     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88470_B0r */
  19245         soc_block_list[61],
  19246         soc_iprocreg,
  19247         1,
  19248         0,
  19249         0x180213b4,
  19250         0,
  19251         0,
  19252         1,
  19253         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88470_B0r_fields,
  19254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19255         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19256         -1,
  19257         -1,
  19258     },
  19259 #endif /* chips */
  19260 
  19261 #if defined(BCM_88675_B0)
  19262     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88675_B0r */
  19263         soc_block_list[61],
  19264         soc_iprocreg,
  19265         1,
  19266         0,
  19267         0x180213b4,
  19268         0,
  19269         0,
  19270         1,
  19271         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88675_B0r_fields,
  19272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19273         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19274         -1,
  19275         -1,
  19276     },
  19277 #endif /* chips */
  19278 
  19279 #if defined(BCM_88680_A0)
  19280     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88680_A0r */
  19281         soc_block_list[61],
  19282         soc_iprocreg,
  19283         1,
  19284         0,
  19285         0x180213b4,
  19286         0,
  19287         0,
  19288         1,
  19289         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88680_A0r_fields,
  19290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19291         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19292         -1,
  19293         -1,
  19294     },
  19295 #endif /* chips */
  19296 
  19297 #if defined(BCM_88690_A0)
  19298     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88690_A0r */
  19299         soc_block_list[61],
  19300         soc_iprocreg,
  19301         1,
  19302         0,
  19303         0x180213b4,
  19304         0,
  19305         0,
  19306         1,
  19307         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88690_A0r_fields,
  19308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19309         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19310         -1,
  19311         -1,
  19312     },
  19313 #endif /* chips */
  19314 
  19315 #if defined(BCM_88690_B0)
  19316     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88690_B0r */
  19317         soc_block_list[61],
  19318         soc_iprocreg,
  19319         1,
  19320         0,
  19321         0x180213b4,
  19322         0,
  19323         0,
  19324         1,
  19325         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88690_B0r_fields,
  19326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19327         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19328         -1,
  19329         -1,
  19330     },
  19331 #endif /* chips */
  19332 
  19333 #if defined(BCM_88790_A0)
  19334     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88790_A0r */
  19335         soc_block_list[61],
  19336         soc_iprocreg,
  19337         1,
  19338         0,
  19339         0x180213b4,
  19340         0,
  19341         0,
  19342         1,
  19343         soc_QSPI_MSPI_INTERRUPT_MSPI_DONE_BCM88790_A0r_fields,
  19344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19345         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19346         -1,
  19347         -1,
  19348     },
  19349 #endif /* chips */
  19350 
  19351 #if defined(BCM_88675_A0)
  19352     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONEr */
  19353         soc_block_list[61],
  19354         soc_iprocreg,
  19355         1,
  19356         0,
  19357         0x180213b8,
  19358         0,
  19359         0,
  19360         1,
  19361         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONEr_fields,
  19362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19363         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19364         -1,
  19365         -1,
  19366     },
  19367 #endif /* chips */
  19368 
  19369 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19370     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19371     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19372     defined(BCM_56260_B0)
  19373     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM53400_A0r */
  19374         soc_block_list[61],
  19375         soc_iprocreg,
  19376         1,
  19377         0,
  19378         0x180473b8,
  19379         0,
  19380         0,
  19381         1,
  19382         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM53400_A0r_fields,
  19383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19384         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19385         -1,
  19386         -1,
  19387     },
  19388 #endif /* chips */
  19389 
  19390 #if defined(BCM_56370_A0)
  19391     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM56370_A0r */
  19392         soc_block_list[61],
  19393         soc_iprocreg,
  19394         1,
  19395         0,
  19396         0x150003b8,
  19397         0,
  19398         0,
  19399         1,
  19400         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM53400_A0r_fields,
  19401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19402         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19403         -1,
  19404         -1,
  19405         3,
  19406     },
  19407 #endif /* chips */
  19408 
  19409 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  19410     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  19411     defined(BCM_56450_B1)
  19412     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM56450_A0r */
  19413         soc_block_list[61],
  19414         soc_iprocreg,
  19415         1,
  19416         0,
  19417         0x180273b8,
  19418         0,
  19419         0,
  19420         1,
  19421         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM56450_A0r_fields,
  19422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19423         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19424         -1,
  19425         -1,
  19426     },
  19427 #endif /* chips */
  19428 
  19429 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  19430     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  19431     defined(BCM_56670_B0)
  19432     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM56560_A0r */
  19433         soc_block_list[61],
  19434         soc_iprocreg,
  19435         1,
  19436         0,
  19437         0x180213b8,
  19438         0,
  19439         0,
  19440         1,
  19441         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM53400_A0r_fields,
  19442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19443         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19444         -1,
  19445         -1,
  19446     },
  19447 #endif /* chips */
  19448 
  19449 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  19450     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  19451     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  19452     defined(BCM_56980_B0)
  19453     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM56960_A0r */
  19454         soc_block_list[61],
  19455         soc_iprocreg,
  19456         1,
  19457         0,
  19458         0x180213b8,
  19459         0,
  19460         0,
  19461         1,
  19462         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM53400_A0r_fields,
  19463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19464         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19465         -1,
  19466         -1,
  19467         3,
  19468     },
  19469 #endif /* chips */
  19470 
  19471 #if defined(BCM_88270_A0)
  19472     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88270_A0r */
  19473         soc_block_list[61],
  19474         soc_iprocreg,
  19475         1,
  19476         0,
  19477         0x180213b8,
  19478         0,
  19479         0,
  19480         1,
  19481         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88270_A0r_fields,
  19482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19483         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19484         -1,
  19485         -1,
  19486     },
  19487 #endif /* chips */
  19488 
  19489 #if defined(BCM_88375_A0)
  19490     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88375_A0r */
  19491         soc_block_list[61],
  19492         soc_iprocreg,
  19493         1,
  19494         0,
  19495         0x180213b8,
  19496         0,
  19497         0,
  19498         1,
  19499         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88375_A0r_fields,
  19500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19501         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19502         -1,
  19503         -1,
  19504     },
  19505 #endif /* chips */
  19506 
  19507 #if defined(BCM_88375_B0)
  19508     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88375_B0r */
  19509         soc_block_list[61],
  19510         soc_iprocreg,
  19511         1,
  19512         0,
  19513         0x180213b8,
  19514         0,
  19515         0,
  19516         1,
  19517         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88375_B0r_fields,
  19518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19519         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19520         -1,
  19521         -1,
  19522     },
  19523 #endif /* chips */
  19524 
  19525 #if defined(BCM_88470_A0)
  19526     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88470_A0r */
  19527         soc_block_list[61],
  19528         soc_iprocreg,
  19529         1,
  19530         0,
  19531         0x180213b8,
  19532         0,
  19533         0,
  19534         1,
  19535         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88470_A0r_fields,
  19536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19537         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19538         -1,
  19539         -1,
  19540     },
  19541 #endif /* chips */
  19542 
  19543 #if defined(BCM_88470_B0)
  19544     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88470_B0r */
  19545         soc_block_list[61],
  19546         soc_iprocreg,
  19547         1,
  19548         0,
  19549         0x180213b8,
  19550         0,
  19551         0,
  19552         1,
  19553         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88470_B0r_fields,
  19554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19555         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19556         -1,
  19557         -1,
  19558     },
  19559 #endif /* chips */
  19560 
  19561 #if defined(BCM_88675_B0)
  19562     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88675_B0r */
  19563         soc_block_list[61],
  19564         soc_iprocreg,
  19565         1,
  19566         0,
  19567         0x180213b8,
  19568         0,
  19569         0,
  19570         1,
  19571         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88675_B0r_fields,
  19572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19573         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19574         -1,
  19575         -1,
  19576     },
  19577 #endif /* chips */
  19578 
  19579 #if defined(BCM_88680_A0)
  19580     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88680_A0r */
  19581         soc_block_list[61],
  19582         soc_iprocreg,
  19583         1,
  19584         0,
  19585         0x180213b8,
  19586         0,
  19587         0,
  19588         1,
  19589         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88680_A0r_fields,
  19590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19591         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19592         -1,
  19593         -1,
  19594     },
  19595 #endif /* chips */
  19596 
  19597 #if defined(BCM_88690_A0)
  19598     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88690_A0r */
  19599         soc_block_list[61],
  19600         soc_iprocreg,
  19601         1,
  19602         0,
  19603         0x180213b8,
  19604         0,
  19605         0,
  19606         1,
  19607         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88690_A0r_fields,
  19608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19609         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19610         -1,
  19611         -1,
  19612     },
  19613 #endif /* chips */
  19614 
  19615 #if defined(BCM_88690_B0)
  19616     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88690_B0r */
  19617         soc_block_list[61],
  19618         soc_iprocreg,
  19619         1,
  19620         0,
  19621         0x180213b8,
  19622         0,
  19623         0,
  19624         1,
  19625         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88690_B0r_fields,
  19626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19627         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19628         -1,
  19629         -1,
  19630     },
  19631 #endif /* chips */
  19632 
  19633 #if defined(BCM_88790_A0)
  19634     { /* SOC_REG_INT_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88790_A0r */
  19635         soc_block_list[61],
  19636         soc_iprocreg,
  19637         1,
  19638         0,
  19639         0x180213b8,
  19640         0,
  19641         0,
  19642         1,
  19643         soc_QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_BCM88790_A0r_fields,
  19644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19645         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  19646         -1,
  19647         -1,
  19648     },
  19649 #endif /* chips */
  19650 
  19651 #if defined(BCM_88675_A0)
  19652     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUSr */
  19653         soc_block_list[61],
  19654         soc_iprocreg,
  19655         1,
  19656         0,
  19657         0x18021220,
  19658         0,
  19659         0,
  19660         3,
  19661         soc_QSPI_MSPI_MSPI_STATUSr_fields,
  19662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19663         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19664         -1,
  19665         -1,
  19666     },
  19667 #endif /* chips */
  19668 
  19669 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19670     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19671     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19672     defined(BCM_56260_B0)
  19673     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM53400_A0r */
  19674         soc_block_list[61],
  19675         soc_iprocreg,
  19676         1,
  19677         0,
  19678         0x18047220,
  19679         0,
  19680         0,
  19681         3,
  19682         soc_QSPI_MSPI_MSPI_STATUS_BCM53400_A0r_fields,
  19683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19685         -1,
  19686         -1,
  19687     },
  19688 #endif /* chips */
  19689 
  19690 #if defined(BCM_56370_A0)
  19691     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM56370_A0r */
  19692         soc_block_list[61],
  19693         soc_iprocreg,
  19694         1,
  19695         0,
  19696         0x15000220,
  19697         0,
  19698         0,
  19699         3,
  19700         soc_QSPI_MSPI_MSPI_STATUS_BCM53400_A0r_fields,
  19701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19703         -1,
  19704         -1,
  19705         3,
  19706     },
  19707 #endif /* chips */
  19708 
  19709 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  19710     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  19711     defined(BCM_56450_B1)
  19712     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM56450_A0r */
  19713         soc_block_list[61],
  19714         soc_iprocreg,
  19715         1,
  19716         0,
  19717         0x18027220,
  19718         0,
  19719         0,
  19720         3,
  19721         soc_QSPI_MSPI_MSPI_STATUS_BCM56450_A0r_fields,
  19722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19723         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19724         -1,
  19725         -1,
  19726     },
  19727 #endif /* chips */
  19728 
  19729 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  19730     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  19731     defined(BCM_56670_B0)
  19732     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM56560_A0r */
  19733         soc_block_list[61],
  19734         soc_iprocreg,
  19735         1,
  19736         0,
  19737         0x18021220,
  19738         0,
  19739         0,
  19740         3,
  19741         soc_QSPI_MSPI_MSPI_STATUS_BCM53400_A0r_fields,
  19742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19744         -1,
  19745         -1,
  19746     },
  19747 #endif /* chips */
  19748 
  19749 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  19750     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  19751     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  19752     defined(BCM_56980_B0)
  19753     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM56960_A0r */
  19754         soc_block_list[61],
  19755         soc_iprocreg,
  19756         1,
  19757         0,
  19758         0x18021220,
  19759         0,
  19760         0,
  19761         3,
  19762         soc_QSPI_MSPI_MSPI_STATUS_BCM53400_A0r_fields,
  19763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19764         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19765         -1,
  19766         -1,
  19767         3,
  19768     },
  19769 #endif /* chips */
  19770 
  19771 #if defined(BCM_88270_A0)
  19772     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM88270_A0r */
  19773         soc_block_list[61],
  19774         soc_iprocreg,
  19775         1,
  19776         0,
  19777         0x18021220,
  19778         0,
  19779         0,
  19780         3,
  19781         soc_QSPI_MSPI_MSPI_STATUS_BCM88270_A0r_fields,
  19782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19783         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19784         -1,
  19785         -1,
  19786     },
  19787 #endif /* chips */
  19788 
  19789 #if defined(BCM_88375_A0)
  19790     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM88375_A0r */
  19791         soc_block_list[61],
  19792         soc_iprocreg,
  19793         1,
  19794         0,
  19795         0x18021220,
  19796         0,
  19797         0,
  19798         3,
  19799         soc_QSPI_MSPI_MSPI_STATUS_BCM88375_A0r_fields,
  19800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19801         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19802         -1,
  19803         -1,
  19804     },
  19805 #endif /* chips */
  19806 
  19807 #if defined(BCM_88375_B0)
  19808     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM88375_B0r */
  19809         soc_block_list[61],
  19810         soc_iprocreg,
  19811         1,
  19812         0,
  19813         0x18021220,
  19814         0,
  19815         0,
  19816         3,
  19817         soc_QSPI_MSPI_MSPI_STATUS_BCM88375_B0r_fields,
  19818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19819         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19820         -1,
  19821         -1,
  19822     },
  19823 #endif /* chips */
  19824 
  19825 #if defined(BCM_88470_A0)
  19826     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM88470_A0r */
  19827         soc_block_list[61],
  19828         soc_iprocreg,
  19829         1,
  19830         0,
  19831         0x18021220,
  19832         0,
  19833         0,
  19834         3,
  19835         soc_QSPI_MSPI_MSPI_STATUS_BCM88470_A0r_fields,
  19836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19837         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19838         -1,
  19839         -1,
  19840     },
  19841 #endif /* chips */
  19842 
  19843 #if defined(BCM_88470_B0)
  19844     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM88470_B0r */
  19845         soc_block_list[61],
  19846         soc_iprocreg,
  19847         1,
  19848         0,
  19849         0x18021220,
  19850         0,
  19851         0,
  19852         3,
  19853         soc_QSPI_MSPI_MSPI_STATUS_BCM88470_B0r_fields,
  19854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19855         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19856         -1,
  19857         -1,
  19858     },
  19859 #endif /* chips */
  19860 
  19861 #if defined(BCM_88675_B0)
  19862     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM88675_B0r */
  19863         soc_block_list[61],
  19864         soc_iprocreg,
  19865         1,
  19866         0,
  19867         0x18021220,
  19868         0,
  19869         0,
  19870         3,
  19871         soc_QSPI_MSPI_MSPI_STATUS_BCM88675_B0r_fields,
  19872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19873         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19874         -1,
  19875         -1,
  19876     },
  19877 #endif /* chips */
  19878 
  19879 #if defined(BCM_88680_A0)
  19880     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM88680_A0r */
  19881         soc_block_list[61],
  19882         soc_iprocreg,
  19883         1,
  19884         0,
  19885         0x18021220,
  19886         0,
  19887         0,
  19888         3,
  19889         soc_QSPI_MSPI_MSPI_STATUS_BCM88680_A0r_fields,
  19890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19891         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19892         -1,
  19893         -1,
  19894     },
  19895 #endif /* chips */
  19896 
  19897 #if defined(BCM_88690_A0)
  19898     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM88690_A0r */
  19899         soc_block_list[61],
  19900         soc_iprocreg,
  19901         1,
  19902         0,
  19903         0x18021220,
  19904         0,
  19905         0,
  19906         3,
  19907         soc_QSPI_MSPI_MSPI_STATUS_BCM88690_A0r_fields,
  19908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19909         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19910         -1,
  19911         -1,
  19912     },
  19913 #endif /* chips */
  19914 
  19915 #if defined(BCM_88690_B0)
  19916     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM88690_B0r */
  19917         soc_block_list[61],
  19918         soc_iprocreg,
  19919         1,
  19920         0,
  19921         0x18021220,
  19922         0,
  19923         0,
  19924         3,
  19925         soc_QSPI_MSPI_MSPI_STATUS_BCM88690_B0r_fields,
  19926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19927         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19928         -1,
  19929         -1,
  19930     },
  19931 #endif /* chips */
  19932 
  19933 #if defined(BCM_88790_A0)
  19934     { /* SOC_REG_INT_QSPI_MSPI_MSPI_STATUS_BCM88790_A0r */
  19935         soc_block_list[61],
  19936         soc_iprocreg,
  19937         1,
  19938         0,
  19939         0x18021220,
  19940         0,
  19941         0,
  19942         3,
  19943         soc_QSPI_MSPI_MSPI_STATUS_BCM88790_A0r_fields,
  19944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19946         -1,
  19947         -1,
  19948     },
  19949 #endif /* chips */
  19950 
  19951 #if defined(BCM_88675_A0)
  19952     { /* SOC_REG_INT_QSPI_MSPI_NEWQPr */
  19953         soc_block_list[61],
  19954         soc_iprocreg,
  19955         1,
  19956         0,
  19957         0x18021210,
  19958         0,
  19959         0,
  19960         2,
  19961         soc_QSPI_MSPI_NEWQPr_fields,
  19962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19964         -1,
  19965         -1,
  19966     },
  19967 #endif /* chips */
  19968 
  19969 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  19970     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  19971     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  19972     defined(BCM_56260_B0)
  19973     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM53400_A0r */
  19974         soc_block_list[61],
  19975         soc_iprocreg,
  19976         1,
  19977         0,
  19978         0x18047210,
  19979         0,
  19980         0,
  19981         2,
  19982         soc_QSPI_MSPI_NEWQP_BCM53400_A0r_fields,
  19983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19984         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19985         -1,
  19986         -1,
  19987     },
  19988 #endif /* chips */
  19989 
  19990 #if defined(BCM_56370_A0)
  19991     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM56370_A0r */
  19992         soc_block_list[61],
  19993         soc_iprocreg,
  19994         1,
  19995         0,
  19996         0x15000210,
  19997         0,
  19998         0,
  19999         2,
  20000         soc_QSPI_MSPI_NEWQP_BCM53400_A0r_fields,
  20001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20002         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20003         -1,
  20004         -1,
  20005         3,
  20006     },
  20007 #endif /* chips */
  20008 
  20009 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  20010     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  20011     defined(BCM_56450_B1)
  20012     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM56450_A0r */
  20013         soc_block_list[61],
  20014         soc_iprocreg,
  20015         1,
  20016         0,
  20017         0x18027210,
  20018         0,
  20019         0,
  20020         2,
  20021         soc_QSPI_MSPI_NEWQP_BCM56450_A0r_fields,
  20022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20023         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20024         -1,
  20025         -1,
  20026     },
  20027 #endif /* chips */
  20028 
  20029 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  20030     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  20031     defined(BCM_56670_B0)
  20032     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM56560_A0r */
  20033         soc_block_list[61],
  20034         soc_iprocreg,
  20035         1,
  20036         0,
  20037         0x18021210,
  20038         0,
  20039         0,
  20040         2,
  20041         soc_QSPI_MSPI_NEWQP_BCM53400_A0r_fields,
  20042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20043         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20044         -1,
  20045         -1,
  20046     },
  20047 #endif /* chips */
  20048 
  20049 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  20050     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  20051     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  20052     defined(BCM_56980_B0)
  20053     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM56960_A0r */
  20054         soc_block_list[61],
  20055         soc_iprocreg,
  20056         1,
  20057         0,
  20058         0x18021210,
  20059         0,
  20060         0,
  20061         2,
  20062         soc_QSPI_MSPI_NEWQP_BCM53400_A0r_fields,
  20063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20064         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20065         -1,
  20066         -1,
  20067         3,
  20068     },
  20069 #endif /* chips */
  20070 
  20071 #if defined(BCM_88270_A0)
  20072     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM88270_A0r */
  20073         soc_block_list[61],
  20074         soc_iprocreg,
  20075         1,
  20076         0,
  20077         0x18021210,
  20078         0,
  20079         0,
  20080         2,
  20081         soc_QSPI_MSPI_NEWQP_BCM88270_A0r_fields,
  20082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20083         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20084         -1,
  20085         -1,
  20086     },
  20087 #endif /* chips */
  20088 
  20089 #if defined(BCM_88375_A0)
  20090     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM88375_A0r */
  20091         soc_block_list[61],
  20092         soc_iprocreg,
  20093         1,
  20094         0,
  20095         0x18021210,
  20096         0,
  20097         0,
  20098         2,
  20099         soc_QSPI_MSPI_NEWQP_BCM88375_A0r_fields,
  20100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20101         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20102         -1,
  20103         -1,
  20104     },
  20105 #endif /* chips */
  20106 
  20107 #if defined(BCM_88375_B0)
  20108     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM88375_B0r */
  20109         soc_block_list[61],
  20110         soc_iprocreg,
  20111         1,
  20112         0,
  20113         0x18021210,
  20114         0,
  20115         0,
  20116         2,
  20117         soc_QSPI_MSPI_NEWQP_BCM88375_B0r_fields,
  20118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20119         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20120         -1,
  20121         -1,
  20122     },
  20123 #endif /* chips */
  20124 
  20125 #if defined(BCM_88470_A0)
  20126     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM88470_A0r */
  20127         soc_block_list[61],
  20128         soc_iprocreg,
  20129         1,
  20130         0,
  20131         0x18021210,
  20132         0,
  20133         0,
  20134         2,
  20135         soc_QSPI_MSPI_NEWQP_BCM88470_A0r_fields,
  20136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20138         -1,
  20139         -1,
  20140     },
  20141 #endif /* chips */
  20142 
  20143 #if defined(BCM_88470_B0)
  20144     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM88470_B0r */
  20145         soc_block_list[61],
  20146         soc_iprocreg,
  20147         1,
  20148         0,
  20149         0x18021210,
  20150         0,
  20151         0,
  20152         2,
  20153         soc_QSPI_MSPI_NEWQP_BCM88470_B0r_fields,
  20154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20156         -1,
  20157         -1,
  20158     },
  20159 #endif /* chips */
  20160 
  20161 #if defined(BCM_88675_B0)
  20162     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM88675_B0r */
  20163         soc_block_list[61],
  20164         soc_iprocreg,
  20165         1,
  20166         0,
  20167         0x18021210,
  20168         0,
  20169         0,
  20170         2,
  20171         soc_QSPI_MSPI_NEWQP_BCM88675_B0r_fields,
  20172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20173         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20174         -1,
  20175         -1,
  20176     },
  20177 #endif /* chips */
  20178 
  20179 #if defined(BCM_88680_A0)
  20180     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM88680_A0r */
  20181         soc_block_list[61],
  20182         soc_iprocreg,
  20183         1,
  20184         0,
  20185         0x18021210,
  20186         0,
  20187         0,
  20188         2,
  20189         soc_QSPI_MSPI_NEWQP_BCM88680_A0r_fields,
  20190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20191         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20192         -1,
  20193         -1,
  20194     },
  20195 #endif /* chips */
  20196 
  20197 #if defined(BCM_88690_A0)
  20198     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM88690_A0r */
  20199         soc_block_list[61],
  20200         soc_iprocreg,
  20201         1,
  20202         0,
  20203         0x18021210,
  20204         0,
  20205         0,
  20206         2,
  20207         soc_QSPI_MSPI_NEWQP_BCM88690_A0r_fields,
  20208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20209         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20210         -1,
  20211         -1,
  20212     },
  20213 #endif /* chips */
  20214 
  20215 #if defined(BCM_88690_B0)
  20216     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM88690_B0r */
  20217         soc_block_list[61],
  20218         soc_iprocreg,
  20219         1,
  20220         0,
  20221         0x18021210,
  20222         0,
  20223         0,
  20224         2,
  20225         soc_QSPI_MSPI_NEWQP_BCM88690_B0r_fields,
  20226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20227         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20228         -1,
  20229         -1,
  20230     },
  20231 #endif /* chips */
  20232 
  20233 #if defined(BCM_88790_A0)
  20234     { /* SOC_REG_INT_QSPI_MSPI_NEWQP_BCM88790_A0r */
  20235         soc_block_list[61],
  20236         soc_iprocreg,
  20237         1,
  20238         0,
  20239         0x18021210,
  20240         0,
  20241         0,
  20242         2,
  20243         soc_QSPI_MSPI_NEWQP_BCM88790_A0r_fields,
  20244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20246         -1,
  20247         -1,
  20248     },
  20249 #endif /* chips */
  20250 
  20251 #if defined(BCM_88675_A0)
  20252     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00r */
  20253         soc_block_list[61],
  20254         soc_iprocreg,
  20255         1,
  20256         0,
  20257         0x180212c0,
  20258         0,
  20259         0,
  20260         2,
  20261         soc_QSPI_MSPI_RXRAM00r_fields,
  20262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20264         -1,
  20265         -1,
  20266     },
  20267 #endif /* chips */
  20268 
  20269 #if defined(BCM_88675_A0)
  20270     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01r */
  20271         soc_block_list[61],
  20272         soc_iprocreg,
  20273         1,
  20274         0,
  20275         0x180212c4,
  20276         0,
  20277         0,
  20278         2,
  20279         soc_QSPI_MSPI_RXRAM01r_fields,
  20280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20281         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20282         -1,
  20283         -1,
  20284     },
  20285 #endif /* chips */
  20286 
  20287 #if defined(BCM_88675_A0)
  20288     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02r */
  20289         soc_block_list[61],
  20290         soc_iprocreg,
  20291         1,
  20292         0,
  20293         0x180212c8,
  20294         0,
  20295         0,
  20296         2,
  20297         soc_QSPI_MSPI_RXRAM02r_fields,
  20298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20300         -1,
  20301         -1,
  20302     },
  20303 #endif /* chips */
  20304 
  20305 #if defined(BCM_88675_A0)
  20306     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03r */
  20307         soc_block_list[61],
  20308         soc_iprocreg,
  20309         1,
  20310         0,
  20311         0x180212cc,
  20312         0,
  20313         0,
  20314         2,
  20315         soc_QSPI_MSPI_RXRAM03r_fields,
  20316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20318         -1,
  20319         -1,
  20320     },
  20321 #endif /* chips */
  20322 
  20323 #if defined(BCM_88675_A0)
  20324     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04r */
  20325         soc_block_list[61],
  20326         soc_iprocreg,
  20327         1,
  20328         0,
  20329         0x180212d0,
  20330         0,
  20331         0,
  20332         2,
  20333         soc_QSPI_MSPI_RXRAM04r_fields,
  20334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20335         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20336         -1,
  20337         -1,
  20338     },
  20339 #endif /* chips */
  20340 
  20341 #if defined(BCM_88675_A0)
  20342     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05r */
  20343         soc_block_list[61],
  20344         soc_iprocreg,
  20345         1,
  20346         0,
  20347         0x180212d4,
  20348         0,
  20349         0,
  20350         2,
  20351         soc_QSPI_MSPI_RXRAM05r_fields,
  20352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20353         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20354         -1,
  20355         -1,
  20356     },
  20357 #endif /* chips */
  20358 
  20359 #if defined(BCM_88675_A0)
  20360     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06r */
  20361         soc_block_list[61],
  20362         soc_iprocreg,
  20363         1,
  20364         0,
  20365         0x180212d8,
  20366         0,
  20367         0,
  20368         2,
  20369         soc_QSPI_MSPI_RXRAM06r_fields,
  20370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20371         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20372         -1,
  20373         -1,
  20374     },
  20375 #endif /* chips */
  20376 
  20377 #if defined(BCM_88675_A0)
  20378     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07r */
  20379         soc_block_list[61],
  20380         soc_iprocreg,
  20381         1,
  20382         0,
  20383         0x180212dc,
  20384         0,
  20385         0,
  20386         2,
  20387         soc_QSPI_MSPI_RXRAM07r_fields,
  20388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20389         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20390         -1,
  20391         -1,
  20392     },
  20393 #endif /* chips */
  20394 
  20395 #if defined(BCM_88675_A0)
  20396     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08r */
  20397         soc_block_list[61],
  20398         soc_iprocreg,
  20399         1,
  20400         0,
  20401         0x180212e0,
  20402         0,
  20403         0,
  20404         2,
  20405         soc_QSPI_MSPI_RXRAM08r_fields,
  20406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20407         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20408         -1,
  20409         -1,
  20410     },
  20411 #endif /* chips */
  20412 
  20413 #if defined(BCM_88675_A0)
  20414     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09r */
  20415         soc_block_list[61],
  20416         soc_iprocreg,
  20417         1,
  20418         0,
  20419         0x180212e4,
  20420         0,
  20421         0,
  20422         2,
  20423         soc_QSPI_MSPI_RXRAM09r_fields,
  20424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20425         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20426         -1,
  20427         -1,
  20428     },
  20429 #endif /* chips */
  20430 
  20431 #if defined(BCM_88675_A0)
  20432     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10r */
  20433         soc_block_list[61],
  20434         soc_iprocreg,
  20435         1,
  20436         0,
  20437         0x180212e8,
  20438         0,
  20439         0,
  20440         2,
  20441         soc_QSPI_MSPI_RXRAM10r_fields,
  20442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20444         -1,
  20445         -1,
  20446     },
  20447 #endif /* chips */
  20448 
  20449 #if defined(BCM_88675_A0)
  20450     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11r */
  20451         soc_block_list[61],
  20452         soc_iprocreg,
  20453         1,
  20454         0,
  20455         0x180212ec,
  20456         0,
  20457         0,
  20458         2,
  20459         soc_QSPI_MSPI_RXRAM11r_fields,
  20460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20462         -1,
  20463         -1,
  20464     },
  20465 #endif /* chips */
  20466 
  20467 #if defined(BCM_88675_A0)
  20468     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12r */
  20469         soc_block_list[61],
  20470         soc_iprocreg,
  20471         1,
  20472         0,
  20473         0x180212f0,
  20474         0,
  20475         0,
  20476         2,
  20477         soc_QSPI_MSPI_RXRAM12r_fields,
  20478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20479         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20480         -1,
  20481         -1,
  20482     },
  20483 #endif /* chips */
  20484 
  20485 #if defined(BCM_88675_A0)
  20486     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13r */
  20487         soc_block_list[61],
  20488         soc_iprocreg,
  20489         1,
  20490         0,
  20491         0x180212f4,
  20492         0,
  20493         0,
  20494         2,
  20495         soc_QSPI_MSPI_RXRAM13r_fields,
  20496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20498         -1,
  20499         -1,
  20500     },
  20501 #endif /* chips */
  20502 
  20503 #if defined(BCM_88675_A0)
  20504     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14r */
  20505         soc_block_list[61],
  20506         soc_iprocreg,
  20507         1,
  20508         0,
  20509         0x180212f8,
  20510         0,
  20511         0,
  20512         2,
  20513         soc_QSPI_MSPI_RXRAM14r_fields,
  20514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20516         -1,
  20517         -1,
  20518     },
  20519 #endif /* chips */
  20520 
  20521 #if defined(BCM_88675_A0)
  20522     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15r */
  20523         soc_block_list[61],
  20524         soc_iprocreg,
  20525         1,
  20526         0,
  20527         0x180212fc,
  20528         0,
  20529         0,
  20530         2,
  20531         soc_QSPI_MSPI_RXRAM15r_fields,
  20532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20534         -1,
  20535         -1,
  20536     },
  20537 #endif /* chips */
  20538 
  20539 #if defined(BCM_88675_A0)
  20540     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16r */
  20541         soc_block_list[61],
  20542         soc_iprocreg,
  20543         1,
  20544         0,
  20545         0x18021300,
  20546         0,
  20547         0,
  20548         2,
  20549         soc_QSPI_MSPI_RXRAM16r_fields,
  20550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20551         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20552         -1,
  20553         -1,
  20554     },
  20555 #endif /* chips */
  20556 
  20557 #if defined(BCM_88675_A0)
  20558     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17r */
  20559         soc_block_list[61],
  20560         soc_iprocreg,
  20561         1,
  20562         0,
  20563         0x18021304,
  20564         0,
  20565         0,
  20566         2,
  20567         soc_QSPI_MSPI_RXRAM17r_fields,
  20568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20569         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20570         -1,
  20571         -1,
  20572     },
  20573 #endif /* chips */
  20574 
  20575 #if defined(BCM_88675_A0)
  20576     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18r */
  20577         soc_block_list[61],
  20578         soc_iprocreg,
  20579         1,
  20580         0,
  20581         0x18021308,
  20582         0,
  20583         0,
  20584         2,
  20585         soc_QSPI_MSPI_RXRAM18r_fields,
  20586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20587         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20588         -1,
  20589         -1,
  20590     },
  20591 #endif /* chips */
  20592 
  20593 #if defined(BCM_88675_A0)
  20594     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19r */
  20595         soc_block_list[61],
  20596         soc_iprocreg,
  20597         1,
  20598         0,
  20599         0x1802130c,
  20600         0,
  20601         0,
  20602         2,
  20603         soc_QSPI_MSPI_RXRAM19r_fields,
  20604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20605         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20606         -1,
  20607         -1,
  20608     },
  20609 #endif /* chips */
  20610 
  20611 #if defined(BCM_88675_A0)
  20612     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20r */
  20613         soc_block_list[61],
  20614         soc_iprocreg,
  20615         1,
  20616         0,
  20617         0x18021310,
  20618         0,
  20619         0,
  20620         2,
  20621         soc_QSPI_MSPI_RXRAM20r_fields,
  20622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20623         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20624         -1,
  20625         -1,
  20626     },
  20627 #endif /* chips */
  20628 
  20629 #if defined(BCM_88675_A0)
  20630     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21r */
  20631         soc_block_list[61],
  20632         soc_iprocreg,
  20633         1,
  20634         0,
  20635         0x18021314,
  20636         0,
  20637         0,
  20638         2,
  20639         soc_QSPI_MSPI_RXRAM21r_fields,
  20640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20641         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20642         -1,
  20643         -1,
  20644     },
  20645 #endif /* chips */
  20646 
  20647 #if defined(BCM_88675_A0)
  20648     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22r */
  20649         soc_block_list[61],
  20650         soc_iprocreg,
  20651         1,
  20652         0,
  20653         0x18021318,
  20654         0,
  20655         0,
  20656         2,
  20657         soc_QSPI_MSPI_RXRAM22r_fields,
  20658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20659         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20660         -1,
  20661         -1,
  20662     },
  20663 #endif /* chips */
  20664 
  20665 #if defined(BCM_88675_A0)
  20666     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23r */
  20667         soc_block_list[61],
  20668         soc_iprocreg,
  20669         1,
  20670         0,
  20671         0x1802131c,
  20672         0,
  20673         0,
  20674         2,
  20675         soc_QSPI_MSPI_RXRAM23r_fields,
  20676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20677         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20678         -1,
  20679         -1,
  20680     },
  20681 #endif /* chips */
  20682 
  20683 #if defined(BCM_88675_A0)
  20684     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24r */
  20685         soc_block_list[61],
  20686         soc_iprocreg,
  20687         1,
  20688         0,
  20689         0x18021320,
  20690         0,
  20691         0,
  20692         2,
  20693         soc_QSPI_MSPI_RXRAM24r_fields,
  20694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20695         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20696         -1,
  20697         -1,
  20698     },
  20699 #endif /* chips */
  20700 
  20701 #if defined(BCM_88675_A0)
  20702     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25r */
  20703         soc_block_list[61],
  20704         soc_iprocreg,
  20705         1,
  20706         0,
  20707         0x18021324,
  20708         0,
  20709         0,
  20710         2,
  20711         soc_QSPI_MSPI_RXRAM25r_fields,
  20712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20713         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20714         -1,
  20715         -1,
  20716     },
  20717 #endif /* chips */
  20718 
  20719 #if defined(BCM_88675_A0)
  20720     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26r */
  20721         soc_block_list[61],
  20722         soc_iprocreg,
  20723         1,
  20724         0,
  20725         0x18021328,
  20726         0,
  20727         0,
  20728         2,
  20729         soc_QSPI_MSPI_RXRAM26r_fields,
  20730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20731         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20732         -1,
  20733         -1,
  20734     },
  20735 #endif /* chips */
  20736 
  20737 #if defined(BCM_88675_A0)
  20738     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27r */
  20739         soc_block_list[61],
  20740         soc_iprocreg,
  20741         1,
  20742         0,
  20743         0x1802132c,
  20744         0,
  20745         0,
  20746         2,
  20747         soc_QSPI_MSPI_RXRAM27r_fields,
  20748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20749         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20750         -1,
  20751         -1,
  20752     },
  20753 #endif /* chips */
  20754 
  20755 #if defined(BCM_88675_A0)
  20756     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28r */
  20757         soc_block_list[61],
  20758         soc_iprocreg,
  20759         1,
  20760         0,
  20761         0x18021330,
  20762         0,
  20763         0,
  20764         2,
  20765         soc_QSPI_MSPI_RXRAM28r_fields,
  20766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20767         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20768         -1,
  20769         -1,
  20770     },
  20771 #endif /* chips */
  20772 
  20773 #if defined(BCM_88675_A0)
  20774     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29r */
  20775         soc_block_list[61],
  20776         soc_iprocreg,
  20777         1,
  20778         0,
  20779         0x18021334,
  20780         0,
  20781         0,
  20782         2,
  20783         soc_QSPI_MSPI_RXRAM29r_fields,
  20784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20785         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20786         -1,
  20787         -1,
  20788     },
  20789 #endif /* chips */
  20790 
  20791 #if defined(BCM_88675_A0)
  20792     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30r */
  20793         soc_block_list[61],
  20794         soc_iprocreg,
  20795         1,
  20796         0,
  20797         0x18021338,
  20798         0,
  20799         0,
  20800         2,
  20801         soc_QSPI_MSPI_RXRAM30r_fields,
  20802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20803         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20804         -1,
  20805         -1,
  20806     },
  20807 #endif /* chips */
  20808 
  20809 #if defined(BCM_88675_A0)
  20810     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31r */
  20811         soc_block_list[61],
  20812         soc_iprocreg,
  20813         1,
  20814         0,
  20815         0x1802133c,
  20816         0,
  20817         0,
  20818         2,
  20819         soc_QSPI_MSPI_RXRAM31r_fields,
  20820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20821         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20822         -1,
  20823         -1,
  20824     },
  20825 #endif /* chips */
  20826 
  20827 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  20828     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  20829     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  20830     defined(BCM_56260_B0)
  20831     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM53400_A0r */
  20832         soc_block_list[61],
  20833         soc_iprocreg,
  20834         1,
  20835         0,
  20836         0x180472c0,
  20837         0,
  20838         0,
  20839         2,
  20840         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  20841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20842         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20843         -1,
  20844         -1,
  20845     },
  20846 #endif /* chips */
  20847 
  20848 #if defined(BCM_56370_A0)
  20849     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM56370_A0r */
  20850         soc_block_list[61],
  20851         soc_iprocreg,
  20852         1,
  20853         0,
  20854         0x150002c0,
  20855         0,
  20856         0,
  20857         2,
  20858         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  20859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20860         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20861         -1,
  20862         -1,
  20863         3,
  20864     },
  20865 #endif /* chips */
  20866 
  20867 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  20868     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  20869     defined(BCM_56450_B1)
  20870     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM56450_A0r */
  20871         soc_block_list[61],
  20872         soc_iprocreg,
  20873         1,
  20874         0,
  20875         0x180272c0,
  20876         0,
  20877         0,
  20878         2,
  20879         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  20880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20881         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20882         -1,
  20883         -1,
  20884     },
  20885 #endif /* chips */
  20886 
  20887 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  20888     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  20889     defined(BCM_56670_B0)
  20890     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM56560_A0r */
  20891         soc_block_list[61],
  20892         soc_iprocreg,
  20893         1,
  20894         0,
  20895         0x180212c0,
  20896         0,
  20897         0,
  20898         2,
  20899         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  20900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20901         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20902         -1,
  20903         -1,
  20904     },
  20905 #endif /* chips */
  20906 
  20907 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  20908     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  20909     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  20910     defined(BCM_56980_B0)
  20911     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM56960_A0r */
  20912         soc_block_list[61],
  20913         soc_iprocreg,
  20914         1,
  20915         0,
  20916         0x180212c0,
  20917         0,
  20918         0,
  20919         2,
  20920         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  20921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20922         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20923         -1,
  20924         -1,
  20925         3,
  20926     },
  20927 #endif /* chips */
  20928 
  20929 #if defined(BCM_88270_A0)
  20930     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM88270_A0r */
  20931         soc_block_list[61],
  20932         soc_iprocreg,
  20933         1,
  20934         0,
  20935         0x180212c0,
  20936         0,
  20937         0,
  20938         2,
  20939         soc_QSPI_MSPI_RXRAM00_BCM88270_A0r_fields,
  20940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20941         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20942         -1,
  20943         -1,
  20944     },
  20945 #endif /* chips */
  20946 
  20947 #if defined(BCM_88375_A0)
  20948     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM88375_A0r */
  20949         soc_block_list[61],
  20950         soc_iprocreg,
  20951         1,
  20952         0,
  20953         0x180212c0,
  20954         0,
  20955         0,
  20956         2,
  20957         soc_QSPI_MSPI_RXRAM00_BCM88375_A0r_fields,
  20958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20959         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20960         -1,
  20961         -1,
  20962     },
  20963 #endif /* chips */
  20964 
  20965 #if defined(BCM_88375_B0)
  20966     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM88375_B0r */
  20967         soc_block_list[61],
  20968         soc_iprocreg,
  20969         1,
  20970         0,
  20971         0x180212c0,
  20972         0,
  20973         0,
  20974         2,
  20975         soc_QSPI_MSPI_RXRAM00_BCM88375_B0r_fields,
  20976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20977         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20978         -1,
  20979         -1,
  20980     },
  20981 #endif /* chips */
  20982 
  20983 #if defined(BCM_88470_A0)
  20984     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM88470_A0r */
  20985         soc_block_list[61],
  20986         soc_iprocreg,
  20987         1,
  20988         0,
  20989         0x180212c0,
  20990         0,
  20991         0,
  20992         2,
  20993         soc_QSPI_MSPI_RXRAM00_BCM88470_A0r_fields,
  20994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20995         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20996         -1,
  20997         -1,
  20998     },
  20999 #endif /* chips */
  21000 
  21001 #if defined(BCM_88470_B0)
  21002     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM88470_B0r */
  21003         soc_block_list[61],
  21004         soc_iprocreg,
  21005         1,
  21006         0,
  21007         0x180212c0,
  21008         0,
  21009         0,
  21010         2,
  21011         soc_QSPI_MSPI_RXRAM00_BCM88470_B0r_fields,
  21012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21013         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21014         -1,
  21015         -1,
  21016     },
  21017 #endif /* chips */
  21018 
  21019 #if defined(BCM_88675_B0)
  21020     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM88675_B0r */
  21021         soc_block_list[61],
  21022         soc_iprocreg,
  21023         1,
  21024         0,
  21025         0x180212c0,
  21026         0,
  21027         0,
  21028         2,
  21029         soc_QSPI_MSPI_RXRAM00_BCM88675_B0r_fields,
  21030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21031         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21032         -1,
  21033         -1,
  21034     },
  21035 #endif /* chips */
  21036 
  21037 #if defined(BCM_88680_A0)
  21038     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM88680_A0r */
  21039         soc_block_list[61],
  21040         soc_iprocreg,
  21041         1,
  21042         0,
  21043         0x180212c0,
  21044         0,
  21045         0,
  21046         2,
  21047         soc_QSPI_MSPI_RXRAM00_BCM88680_A0r_fields,
  21048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21049         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21050         -1,
  21051         -1,
  21052     },
  21053 #endif /* chips */
  21054 
  21055 #if defined(BCM_88690_A0)
  21056     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM88690_A0r */
  21057         soc_block_list[61],
  21058         soc_iprocreg,
  21059         1,
  21060         0,
  21061         0x180212c0,
  21062         0,
  21063         0,
  21064         2,
  21065         soc_QSPI_MSPI_RXRAM00_BCM88690_A0r_fields,
  21066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21067         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21068         -1,
  21069         -1,
  21070     },
  21071 #endif /* chips */
  21072 
  21073 #if defined(BCM_88690_B0)
  21074     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM88690_B0r */
  21075         soc_block_list[61],
  21076         soc_iprocreg,
  21077         1,
  21078         0,
  21079         0x180212c0,
  21080         0,
  21081         0,
  21082         2,
  21083         soc_QSPI_MSPI_RXRAM00_BCM88690_B0r_fields,
  21084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21085         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21086         -1,
  21087         -1,
  21088     },
  21089 #endif /* chips */
  21090 
  21091 #if defined(BCM_88790_A0)
  21092     { /* SOC_REG_INT_QSPI_MSPI_RXRAM00_BCM88790_A0r */
  21093         soc_block_list[61],
  21094         soc_iprocreg,
  21095         1,
  21096         0,
  21097         0x180212c0,
  21098         0,
  21099         0,
  21100         2,
  21101         soc_QSPI_MSPI_RXRAM00_BCM88790_A0r_fields,
  21102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21103         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21104         -1,
  21105         -1,
  21106     },
  21107 #endif /* chips */
  21108 
  21109 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21110     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21111     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21112     defined(BCM_56260_B0)
  21113     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM53400_A0r */
  21114         soc_block_list[61],
  21115         soc_iprocreg,
  21116         1,
  21117         0,
  21118         0x180472c4,
  21119         0,
  21120         0,
  21121         2,
  21122         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21124         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21125         -1,
  21126         -1,
  21127     },
  21128 #endif /* chips */
  21129 
  21130 #if defined(BCM_56370_A0)
  21131     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM56370_A0r */
  21132         soc_block_list[61],
  21133         soc_iprocreg,
  21134         1,
  21135         0,
  21136         0x150002c4,
  21137         0,
  21138         0,
  21139         2,
  21140         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21142         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21143         -1,
  21144         -1,
  21145         3,
  21146     },
  21147 #endif /* chips */
  21148 
  21149 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  21150     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  21151     defined(BCM_56450_B1)
  21152     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM56450_A0r */
  21153         soc_block_list[61],
  21154         soc_iprocreg,
  21155         1,
  21156         0,
  21157         0x180272c4,
  21158         0,
  21159         0,
  21160         2,
  21161         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  21162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21163         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21164         -1,
  21165         -1,
  21166     },
  21167 #endif /* chips */
  21168 
  21169 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  21170     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  21171     defined(BCM_56670_B0)
  21172     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM56560_A0r */
  21173         soc_block_list[61],
  21174         soc_iprocreg,
  21175         1,
  21176         0,
  21177         0x180212c4,
  21178         0,
  21179         0,
  21180         2,
  21181         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21183         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21184         -1,
  21185         -1,
  21186     },
  21187 #endif /* chips */
  21188 
  21189 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  21190     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  21191     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  21192     defined(BCM_56980_B0)
  21193     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM56960_A0r */
  21194         soc_block_list[61],
  21195         soc_iprocreg,
  21196         1,
  21197         0,
  21198         0x180212c4,
  21199         0,
  21200         0,
  21201         2,
  21202         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21204         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21205         -1,
  21206         -1,
  21207         3,
  21208     },
  21209 #endif /* chips */
  21210 
  21211 #if defined(BCM_88270_A0)
  21212     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM88270_A0r */
  21213         soc_block_list[61],
  21214         soc_iprocreg,
  21215         1,
  21216         0,
  21217         0x180212c4,
  21218         0,
  21219         0,
  21220         2,
  21221         soc_QSPI_MSPI_RXRAM01_BCM88270_A0r_fields,
  21222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21223         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21224         -1,
  21225         -1,
  21226     },
  21227 #endif /* chips */
  21228 
  21229 #if defined(BCM_88375_A0)
  21230     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM88375_A0r */
  21231         soc_block_list[61],
  21232         soc_iprocreg,
  21233         1,
  21234         0,
  21235         0x180212c4,
  21236         0,
  21237         0,
  21238         2,
  21239         soc_QSPI_MSPI_RXRAM01_BCM88375_A0r_fields,
  21240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21241         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21242         -1,
  21243         -1,
  21244     },
  21245 #endif /* chips */
  21246 
  21247 #if defined(BCM_88375_B0)
  21248     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM88375_B0r */
  21249         soc_block_list[61],
  21250         soc_iprocreg,
  21251         1,
  21252         0,
  21253         0x180212c4,
  21254         0,
  21255         0,
  21256         2,
  21257         soc_QSPI_MSPI_RXRAM01_BCM88375_B0r_fields,
  21258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21259         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21260         -1,
  21261         -1,
  21262     },
  21263 #endif /* chips */
  21264 
  21265 #if defined(BCM_88470_A0)
  21266     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM88470_A0r */
  21267         soc_block_list[61],
  21268         soc_iprocreg,
  21269         1,
  21270         0,
  21271         0x180212c4,
  21272         0,
  21273         0,
  21274         2,
  21275         soc_QSPI_MSPI_RXRAM01_BCM88470_A0r_fields,
  21276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21277         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21278         -1,
  21279         -1,
  21280     },
  21281 #endif /* chips */
  21282 
  21283 #if defined(BCM_88470_B0)
  21284     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM88470_B0r */
  21285         soc_block_list[61],
  21286         soc_iprocreg,
  21287         1,
  21288         0,
  21289         0x180212c4,
  21290         0,
  21291         0,
  21292         2,
  21293         soc_QSPI_MSPI_RXRAM01_BCM88470_B0r_fields,
  21294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21295         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21296         -1,
  21297         -1,
  21298     },
  21299 #endif /* chips */
  21300 
  21301 #if defined(BCM_88675_B0)
  21302     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM88675_B0r */
  21303         soc_block_list[61],
  21304         soc_iprocreg,
  21305         1,
  21306         0,
  21307         0x180212c4,
  21308         0,
  21309         0,
  21310         2,
  21311         soc_QSPI_MSPI_RXRAM01_BCM88675_B0r_fields,
  21312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21313         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21314         -1,
  21315         -1,
  21316     },
  21317 #endif /* chips */
  21318 
  21319 #if defined(BCM_88680_A0)
  21320     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM88680_A0r */
  21321         soc_block_list[61],
  21322         soc_iprocreg,
  21323         1,
  21324         0,
  21325         0x180212c4,
  21326         0,
  21327         0,
  21328         2,
  21329         soc_QSPI_MSPI_RXRAM01_BCM88680_A0r_fields,
  21330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21331         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21332         -1,
  21333         -1,
  21334     },
  21335 #endif /* chips */
  21336 
  21337 #if defined(BCM_88690_A0)
  21338     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM88690_A0r */
  21339         soc_block_list[61],
  21340         soc_iprocreg,
  21341         1,
  21342         0,
  21343         0x180212c4,
  21344         0,
  21345         0,
  21346         2,
  21347         soc_QSPI_MSPI_RXRAM01_BCM88690_A0r_fields,
  21348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21349         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21350         -1,
  21351         -1,
  21352     },
  21353 #endif /* chips */
  21354 
  21355 #if defined(BCM_88690_B0)
  21356     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM88690_B0r */
  21357         soc_block_list[61],
  21358         soc_iprocreg,
  21359         1,
  21360         0,
  21361         0x180212c4,
  21362         0,
  21363         0,
  21364         2,
  21365         soc_QSPI_MSPI_RXRAM01_BCM88690_B0r_fields,
  21366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21367         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21368         -1,
  21369         -1,
  21370     },
  21371 #endif /* chips */
  21372 
  21373 #if defined(BCM_88790_A0)
  21374     { /* SOC_REG_INT_QSPI_MSPI_RXRAM01_BCM88790_A0r */
  21375         soc_block_list[61],
  21376         soc_iprocreg,
  21377         1,
  21378         0,
  21379         0x180212c4,
  21380         0,
  21381         0,
  21382         2,
  21383         soc_QSPI_MSPI_RXRAM01_BCM88790_A0r_fields,
  21384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21385         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21386         -1,
  21387         -1,
  21388     },
  21389 #endif /* chips */
  21390 
  21391 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21392     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21393     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21394     defined(BCM_56260_B0)
  21395     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM53400_A0r */
  21396         soc_block_list[61],
  21397         soc_iprocreg,
  21398         1,
  21399         0,
  21400         0x180472c8,
  21401         0,
  21402         0,
  21403         2,
  21404         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21406         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21407         -1,
  21408         -1,
  21409     },
  21410 #endif /* chips */
  21411 
  21412 #if defined(BCM_56370_A0)
  21413     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM56370_A0r */
  21414         soc_block_list[61],
  21415         soc_iprocreg,
  21416         1,
  21417         0,
  21418         0x150002c8,
  21419         0,
  21420         0,
  21421         2,
  21422         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21424         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21425         -1,
  21426         -1,
  21427         3,
  21428     },
  21429 #endif /* chips */
  21430 
  21431 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  21432     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  21433     defined(BCM_56450_B1)
  21434     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM56450_A0r */
  21435         soc_block_list[61],
  21436         soc_iprocreg,
  21437         1,
  21438         0,
  21439         0x180272c8,
  21440         0,
  21441         0,
  21442         2,
  21443         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  21444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21446         -1,
  21447         -1,
  21448     },
  21449 #endif /* chips */
  21450 
  21451 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  21452     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  21453     defined(BCM_56670_B0)
  21454     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM56560_A0r */
  21455         soc_block_list[61],
  21456         soc_iprocreg,
  21457         1,
  21458         0,
  21459         0x180212c8,
  21460         0,
  21461         0,
  21462         2,
  21463         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21465         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21466         -1,
  21467         -1,
  21468     },
  21469 #endif /* chips */
  21470 
  21471 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  21472     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  21473     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  21474     defined(BCM_56980_B0)
  21475     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM56960_A0r */
  21476         soc_block_list[61],
  21477         soc_iprocreg,
  21478         1,
  21479         0,
  21480         0x180212c8,
  21481         0,
  21482         0,
  21483         2,
  21484         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21486         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21487         -1,
  21488         -1,
  21489         3,
  21490     },
  21491 #endif /* chips */
  21492 
  21493 #if defined(BCM_88270_A0)
  21494     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM88270_A0r */
  21495         soc_block_list[61],
  21496         soc_iprocreg,
  21497         1,
  21498         0,
  21499         0x180212c8,
  21500         0,
  21501         0,
  21502         2,
  21503         soc_QSPI_MSPI_RXRAM02_BCM88270_A0r_fields,
  21504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21505         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21506         -1,
  21507         -1,
  21508     },
  21509 #endif /* chips */
  21510 
  21511 #if defined(BCM_88375_A0)
  21512     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM88375_A0r */
  21513         soc_block_list[61],
  21514         soc_iprocreg,
  21515         1,
  21516         0,
  21517         0x180212c8,
  21518         0,
  21519         0,
  21520         2,
  21521         soc_QSPI_MSPI_RXRAM02_BCM88375_A0r_fields,
  21522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21523         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21524         -1,
  21525         -1,
  21526     },
  21527 #endif /* chips */
  21528 
  21529 #if defined(BCM_88375_B0)
  21530     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM88375_B0r */
  21531         soc_block_list[61],
  21532         soc_iprocreg,
  21533         1,
  21534         0,
  21535         0x180212c8,
  21536         0,
  21537         0,
  21538         2,
  21539         soc_QSPI_MSPI_RXRAM02_BCM88375_B0r_fields,
  21540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21542         -1,
  21543         -1,
  21544     },
  21545 #endif /* chips */
  21546 
  21547 #if defined(BCM_88470_A0)
  21548     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM88470_A0r */
  21549         soc_block_list[61],
  21550         soc_iprocreg,
  21551         1,
  21552         0,
  21553         0x180212c8,
  21554         0,
  21555         0,
  21556         2,
  21557         soc_QSPI_MSPI_RXRAM02_BCM88470_A0r_fields,
  21558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21559         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21560         -1,
  21561         -1,
  21562     },
  21563 #endif /* chips */
  21564 
  21565 #if defined(BCM_88470_B0)
  21566     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM88470_B0r */
  21567         soc_block_list[61],
  21568         soc_iprocreg,
  21569         1,
  21570         0,
  21571         0x180212c8,
  21572         0,
  21573         0,
  21574         2,
  21575         soc_QSPI_MSPI_RXRAM02_BCM88470_B0r_fields,
  21576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21577         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21578         -1,
  21579         -1,
  21580     },
  21581 #endif /* chips */
  21582 
  21583 #if defined(BCM_88675_B0)
  21584     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM88675_B0r */
  21585         soc_block_list[61],
  21586         soc_iprocreg,
  21587         1,
  21588         0,
  21589         0x180212c8,
  21590         0,
  21591         0,
  21592         2,
  21593         soc_QSPI_MSPI_RXRAM02_BCM88675_B0r_fields,
  21594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21596         -1,
  21597         -1,
  21598     },
  21599 #endif /* chips */
  21600 
  21601 #if defined(BCM_88680_A0)
  21602     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM88680_A0r */
  21603         soc_block_list[61],
  21604         soc_iprocreg,
  21605         1,
  21606         0,
  21607         0x180212c8,
  21608         0,
  21609         0,
  21610         2,
  21611         soc_QSPI_MSPI_RXRAM02_BCM88680_A0r_fields,
  21612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21613         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21614         -1,
  21615         -1,
  21616     },
  21617 #endif /* chips */
  21618 
  21619 #if defined(BCM_88690_A0)
  21620     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM88690_A0r */
  21621         soc_block_list[61],
  21622         soc_iprocreg,
  21623         1,
  21624         0,
  21625         0x180212c8,
  21626         0,
  21627         0,
  21628         2,
  21629         soc_QSPI_MSPI_RXRAM02_BCM88690_A0r_fields,
  21630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21631         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21632         -1,
  21633         -1,
  21634     },
  21635 #endif /* chips */
  21636 
  21637 #if defined(BCM_88690_B0)
  21638     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM88690_B0r */
  21639         soc_block_list[61],
  21640         soc_iprocreg,
  21641         1,
  21642         0,
  21643         0x180212c8,
  21644         0,
  21645         0,
  21646         2,
  21647         soc_QSPI_MSPI_RXRAM02_BCM88690_B0r_fields,
  21648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21649         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21650         -1,
  21651         -1,
  21652     },
  21653 #endif /* chips */
  21654 
  21655 #if defined(BCM_88790_A0)
  21656     { /* SOC_REG_INT_QSPI_MSPI_RXRAM02_BCM88790_A0r */
  21657         soc_block_list[61],
  21658         soc_iprocreg,
  21659         1,
  21660         0,
  21661         0x180212c8,
  21662         0,
  21663         0,
  21664         2,
  21665         soc_QSPI_MSPI_RXRAM02_BCM88790_A0r_fields,
  21666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21667         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21668         -1,
  21669         -1,
  21670     },
  21671 #endif /* chips */
  21672 
  21673 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21674     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21675     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21676     defined(BCM_56260_B0)
  21677     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM53400_A0r */
  21678         soc_block_list[61],
  21679         soc_iprocreg,
  21680         1,
  21681         0,
  21682         0x180472cc,
  21683         0,
  21684         0,
  21685         2,
  21686         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21689         -1,
  21690         -1,
  21691     },
  21692 #endif /* chips */
  21693 
  21694 #if defined(BCM_56370_A0)
  21695     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM56370_A0r */
  21696         soc_block_list[61],
  21697         soc_iprocreg,
  21698         1,
  21699         0,
  21700         0x150002cc,
  21701         0,
  21702         0,
  21703         2,
  21704         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21706         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21707         -1,
  21708         -1,
  21709         3,
  21710     },
  21711 #endif /* chips */
  21712 
  21713 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  21714     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  21715     defined(BCM_56450_B1)
  21716     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM56450_A0r */
  21717         soc_block_list[61],
  21718         soc_iprocreg,
  21719         1,
  21720         0,
  21721         0x180272cc,
  21722         0,
  21723         0,
  21724         2,
  21725         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  21726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21727         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21728         -1,
  21729         -1,
  21730     },
  21731 #endif /* chips */
  21732 
  21733 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  21734     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  21735     defined(BCM_56670_B0)
  21736     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM56560_A0r */
  21737         soc_block_list[61],
  21738         soc_iprocreg,
  21739         1,
  21740         0,
  21741         0x180212cc,
  21742         0,
  21743         0,
  21744         2,
  21745         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21747         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21748         -1,
  21749         -1,
  21750     },
  21751 #endif /* chips */
  21752 
  21753 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  21754     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  21755     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  21756     defined(BCM_56980_B0)
  21757     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM56960_A0r */
  21758         soc_block_list[61],
  21759         soc_iprocreg,
  21760         1,
  21761         0,
  21762         0x180212cc,
  21763         0,
  21764         0,
  21765         2,
  21766         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21767         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21768         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21769         -1,
  21770         -1,
  21771         3,
  21772     },
  21773 #endif /* chips */
  21774 
  21775 #if defined(BCM_88270_A0)
  21776     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM88270_A0r */
  21777         soc_block_list[61],
  21778         soc_iprocreg,
  21779         1,
  21780         0,
  21781         0x180212cc,
  21782         0,
  21783         0,
  21784         2,
  21785         soc_QSPI_MSPI_RXRAM03_BCM88270_A0r_fields,
  21786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21787         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21788         -1,
  21789         -1,
  21790     },
  21791 #endif /* chips */
  21792 
  21793 #if defined(BCM_88375_A0)
  21794     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM88375_A0r */
  21795         soc_block_list[61],
  21796         soc_iprocreg,
  21797         1,
  21798         0,
  21799         0x180212cc,
  21800         0,
  21801         0,
  21802         2,
  21803         soc_QSPI_MSPI_RXRAM03_BCM88375_A0r_fields,
  21804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21805         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21806         -1,
  21807         -1,
  21808     },
  21809 #endif /* chips */
  21810 
  21811 #if defined(BCM_88375_B0)
  21812     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM88375_B0r */
  21813         soc_block_list[61],
  21814         soc_iprocreg,
  21815         1,
  21816         0,
  21817         0x180212cc,
  21818         0,
  21819         0,
  21820         2,
  21821         soc_QSPI_MSPI_RXRAM03_BCM88375_B0r_fields,
  21822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21823         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21824         -1,
  21825         -1,
  21826     },
  21827 #endif /* chips */
  21828 
  21829 #if defined(BCM_88470_A0)
  21830     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM88470_A0r */
  21831         soc_block_list[61],
  21832         soc_iprocreg,
  21833         1,
  21834         0,
  21835         0x180212cc,
  21836         0,
  21837         0,
  21838         2,
  21839         soc_QSPI_MSPI_RXRAM03_BCM88470_A0r_fields,
  21840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21842         -1,
  21843         -1,
  21844     },
  21845 #endif /* chips */
  21846 
  21847 #if defined(BCM_88470_B0)
  21848     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM88470_B0r */
  21849         soc_block_list[61],
  21850         soc_iprocreg,
  21851         1,
  21852         0,
  21853         0x180212cc,
  21854         0,
  21855         0,
  21856         2,
  21857         soc_QSPI_MSPI_RXRAM03_BCM88470_B0r_fields,
  21858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21859         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21860         -1,
  21861         -1,
  21862     },
  21863 #endif /* chips */
  21864 
  21865 #if defined(BCM_88675_B0)
  21866     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM88675_B0r */
  21867         soc_block_list[61],
  21868         soc_iprocreg,
  21869         1,
  21870         0,
  21871         0x180212cc,
  21872         0,
  21873         0,
  21874         2,
  21875         soc_QSPI_MSPI_RXRAM03_BCM88675_B0r_fields,
  21876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21878         -1,
  21879         -1,
  21880     },
  21881 #endif /* chips */
  21882 
  21883 #if defined(BCM_88680_A0)
  21884     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM88680_A0r */
  21885         soc_block_list[61],
  21886         soc_iprocreg,
  21887         1,
  21888         0,
  21889         0x180212cc,
  21890         0,
  21891         0,
  21892         2,
  21893         soc_QSPI_MSPI_RXRAM03_BCM88680_A0r_fields,
  21894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21895         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21896         -1,
  21897         -1,
  21898     },
  21899 #endif /* chips */
  21900 
  21901 #if defined(BCM_88690_A0)
  21902     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM88690_A0r */
  21903         soc_block_list[61],
  21904         soc_iprocreg,
  21905         1,
  21906         0,
  21907         0x180212cc,
  21908         0,
  21909         0,
  21910         2,
  21911         soc_QSPI_MSPI_RXRAM03_BCM88690_A0r_fields,
  21912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21913         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21914         -1,
  21915         -1,
  21916     },
  21917 #endif /* chips */
  21918 
  21919 #if defined(BCM_88690_B0)
  21920     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM88690_B0r */
  21921         soc_block_list[61],
  21922         soc_iprocreg,
  21923         1,
  21924         0,
  21925         0x180212cc,
  21926         0,
  21927         0,
  21928         2,
  21929         soc_QSPI_MSPI_RXRAM03_BCM88690_B0r_fields,
  21930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21931         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21932         -1,
  21933         -1,
  21934     },
  21935 #endif /* chips */
  21936 
  21937 #if defined(BCM_88790_A0)
  21938     { /* SOC_REG_INT_QSPI_MSPI_RXRAM03_BCM88790_A0r */
  21939         soc_block_list[61],
  21940         soc_iprocreg,
  21941         1,
  21942         0,
  21943         0x180212cc,
  21944         0,
  21945         0,
  21946         2,
  21947         soc_QSPI_MSPI_RXRAM03_BCM88790_A0r_fields,
  21948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21949         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21950         -1,
  21951         -1,
  21952     },
  21953 #endif /* chips */
  21954 
  21955 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  21956     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  21957     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  21958     defined(BCM_56260_B0)
  21959     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM53400_A0r */
  21960         soc_block_list[61],
  21961         soc_iprocreg,
  21962         1,
  21963         0,
  21964         0x180472d0,
  21965         0,
  21966         0,
  21967         2,
  21968         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21970         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21971         -1,
  21972         -1,
  21973     },
  21974 #endif /* chips */
  21975 
  21976 #if defined(BCM_56370_A0)
  21977     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM56370_A0r */
  21978         soc_block_list[61],
  21979         soc_iprocreg,
  21980         1,
  21981         0,
  21982         0x150002d0,
  21983         0,
  21984         0,
  21985         2,
  21986         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  21987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21988         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21989         -1,
  21990         -1,
  21991         3,
  21992     },
  21993 #endif /* chips */
  21994 
  21995 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  21996     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  21997     defined(BCM_56450_B1)
  21998     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM56450_A0r */
  21999         soc_block_list[61],
  22000         soc_iprocreg,
  22001         1,
  22002         0,
  22003         0x180272d0,
  22004         0,
  22005         0,
  22006         2,
  22007         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  22008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22009         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22010         -1,
  22011         -1,
  22012     },
  22013 #endif /* chips */
  22014 
  22015 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  22016     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  22017     defined(BCM_56670_B0)
  22018     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM56560_A0r */
  22019         soc_block_list[61],
  22020         soc_iprocreg,
  22021         1,
  22022         0,
  22023         0x180212d0,
  22024         0,
  22025         0,
  22026         2,
  22027         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22029         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22030         -1,
  22031         -1,
  22032     },
  22033 #endif /* chips */
  22034 
  22035 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  22036     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  22037     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  22038     defined(BCM_56980_B0)
  22039     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM56960_A0r */
  22040         soc_block_list[61],
  22041         soc_iprocreg,
  22042         1,
  22043         0,
  22044         0x180212d0,
  22045         0,
  22046         0,
  22047         2,
  22048         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22050         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22051         -1,
  22052         -1,
  22053         3,
  22054     },
  22055 #endif /* chips */
  22056 
  22057 #if defined(BCM_88270_A0)
  22058     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM88270_A0r */
  22059         soc_block_list[61],
  22060         soc_iprocreg,
  22061         1,
  22062         0,
  22063         0x180212d0,
  22064         0,
  22065         0,
  22066         2,
  22067         soc_QSPI_MSPI_RXRAM04_BCM88270_A0r_fields,
  22068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22069         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22070         -1,
  22071         -1,
  22072     },
  22073 #endif /* chips */
  22074 
  22075 #if defined(BCM_88375_A0)
  22076     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM88375_A0r */
  22077         soc_block_list[61],
  22078         soc_iprocreg,
  22079         1,
  22080         0,
  22081         0x180212d0,
  22082         0,
  22083         0,
  22084         2,
  22085         soc_QSPI_MSPI_RXRAM04_BCM88375_A0r_fields,
  22086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22087         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22088         -1,
  22089         -1,
  22090     },
  22091 #endif /* chips */
  22092 
  22093 #if defined(BCM_88375_B0)
  22094     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM88375_B0r */
  22095         soc_block_list[61],
  22096         soc_iprocreg,
  22097         1,
  22098         0,
  22099         0x180212d0,
  22100         0,
  22101         0,
  22102         2,
  22103         soc_QSPI_MSPI_RXRAM04_BCM88375_B0r_fields,
  22104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22105         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22106         -1,
  22107         -1,
  22108     },
  22109 #endif /* chips */
  22110 
  22111 #if defined(BCM_88470_A0)
  22112     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM88470_A0r */
  22113         soc_block_list[61],
  22114         soc_iprocreg,
  22115         1,
  22116         0,
  22117         0x180212d0,
  22118         0,
  22119         0,
  22120         2,
  22121         soc_QSPI_MSPI_RXRAM04_BCM88470_A0r_fields,
  22122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22123         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22124         -1,
  22125         -1,
  22126     },
  22127 #endif /* chips */
  22128 
  22129 #if defined(BCM_88470_B0)
  22130     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM88470_B0r */
  22131         soc_block_list[61],
  22132         soc_iprocreg,
  22133         1,
  22134         0,
  22135         0x180212d0,
  22136         0,
  22137         0,
  22138         2,
  22139         soc_QSPI_MSPI_RXRAM04_BCM88470_B0r_fields,
  22140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22141         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22142         -1,
  22143         -1,
  22144     },
  22145 #endif /* chips */
  22146 
  22147 #if defined(BCM_88675_B0)
  22148     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM88675_B0r */
  22149         soc_block_list[61],
  22150         soc_iprocreg,
  22151         1,
  22152         0,
  22153         0x180212d0,
  22154         0,
  22155         0,
  22156         2,
  22157         soc_QSPI_MSPI_RXRAM04_BCM88675_B0r_fields,
  22158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22159         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22160         -1,
  22161         -1,
  22162     },
  22163 #endif /* chips */
  22164 
  22165 #if defined(BCM_88680_A0)
  22166     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM88680_A0r */
  22167         soc_block_list[61],
  22168         soc_iprocreg,
  22169         1,
  22170         0,
  22171         0x180212d0,
  22172         0,
  22173         0,
  22174         2,
  22175         soc_QSPI_MSPI_RXRAM04_BCM88680_A0r_fields,
  22176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22177         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22178         -1,
  22179         -1,
  22180     },
  22181 #endif /* chips */
  22182 
  22183 #if defined(BCM_88690_A0)
  22184     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM88690_A0r */
  22185         soc_block_list[61],
  22186         soc_iprocreg,
  22187         1,
  22188         0,
  22189         0x180212d0,
  22190         0,
  22191         0,
  22192         2,
  22193         soc_QSPI_MSPI_RXRAM04_BCM88690_A0r_fields,
  22194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22195         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22196         -1,
  22197         -1,
  22198     },
  22199 #endif /* chips */
  22200 
  22201 #if defined(BCM_88690_B0)
  22202     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM88690_B0r */
  22203         soc_block_list[61],
  22204         soc_iprocreg,
  22205         1,
  22206         0,
  22207         0x180212d0,
  22208         0,
  22209         0,
  22210         2,
  22211         soc_QSPI_MSPI_RXRAM04_BCM88690_B0r_fields,
  22212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22213         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22214         -1,
  22215         -1,
  22216     },
  22217 #endif /* chips */
  22218 
  22219 #if defined(BCM_88790_A0)
  22220     { /* SOC_REG_INT_QSPI_MSPI_RXRAM04_BCM88790_A0r */
  22221         soc_block_list[61],
  22222         soc_iprocreg,
  22223         1,
  22224         0,
  22225         0x180212d0,
  22226         0,
  22227         0,
  22228         2,
  22229         soc_QSPI_MSPI_RXRAM04_BCM88790_A0r_fields,
  22230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22231         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22232         -1,
  22233         -1,
  22234     },
  22235 #endif /* chips */
  22236 
  22237 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22238     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22239     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22240     defined(BCM_56260_B0)
  22241     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM53400_A0r */
  22242         soc_block_list[61],
  22243         soc_iprocreg,
  22244         1,
  22245         0,
  22246         0x180472d4,
  22247         0,
  22248         0,
  22249         2,
  22250         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22252         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22253         -1,
  22254         -1,
  22255     },
  22256 #endif /* chips */
  22257 
  22258 #if defined(BCM_56370_A0)
  22259     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM56370_A0r */
  22260         soc_block_list[61],
  22261         soc_iprocreg,
  22262         1,
  22263         0,
  22264         0x150002d4,
  22265         0,
  22266         0,
  22267         2,
  22268         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22270         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22271         -1,
  22272         -1,
  22273         3,
  22274     },
  22275 #endif /* chips */
  22276 
  22277 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  22278     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  22279     defined(BCM_56450_B1)
  22280     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM56450_A0r */
  22281         soc_block_list[61],
  22282         soc_iprocreg,
  22283         1,
  22284         0,
  22285         0x180272d4,
  22286         0,
  22287         0,
  22288         2,
  22289         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  22290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22291         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22292         -1,
  22293         -1,
  22294     },
  22295 #endif /* chips */
  22296 
  22297 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  22298     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  22299     defined(BCM_56670_B0)
  22300     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM56560_A0r */
  22301         soc_block_list[61],
  22302         soc_iprocreg,
  22303         1,
  22304         0,
  22305         0x180212d4,
  22306         0,
  22307         0,
  22308         2,
  22309         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22311         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22312         -1,
  22313         -1,
  22314     },
  22315 #endif /* chips */
  22316 
  22317 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  22318     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  22319     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  22320     defined(BCM_56980_B0)
  22321     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM56960_A0r */
  22322         soc_block_list[61],
  22323         soc_iprocreg,
  22324         1,
  22325         0,
  22326         0x180212d4,
  22327         0,
  22328         0,
  22329         2,
  22330         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22333         -1,
  22334         -1,
  22335         3,
  22336     },
  22337 #endif /* chips */
  22338 
  22339 #if defined(BCM_88270_A0)
  22340     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM88270_A0r */
  22341         soc_block_list[61],
  22342         soc_iprocreg,
  22343         1,
  22344         0,
  22345         0x180212d4,
  22346         0,
  22347         0,
  22348         2,
  22349         soc_QSPI_MSPI_RXRAM05_BCM88270_A0r_fields,
  22350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22351         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22352         -1,
  22353         -1,
  22354     },
  22355 #endif /* chips */
  22356 
  22357 #if defined(BCM_88375_A0)
  22358     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM88375_A0r */
  22359         soc_block_list[61],
  22360         soc_iprocreg,
  22361         1,
  22362         0,
  22363         0x180212d4,
  22364         0,
  22365         0,
  22366         2,
  22367         soc_QSPI_MSPI_RXRAM05_BCM88375_A0r_fields,
  22368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22369         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22370         -1,
  22371         -1,
  22372     },
  22373 #endif /* chips */
  22374 
  22375 #if defined(BCM_88375_B0)
  22376     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM88375_B0r */
  22377         soc_block_list[61],
  22378         soc_iprocreg,
  22379         1,
  22380         0,
  22381         0x180212d4,
  22382         0,
  22383         0,
  22384         2,
  22385         soc_QSPI_MSPI_RXRAM05_BCM88375_B0r_fields,
  22386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22387         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22388         -1,
  22389         -1,
  22390     },
  22391 #endif /* chips */
  22392 
  22393 #if defined(BCM_88470_A0)
  22394     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM88470_A0r */
  22395         soc_block_list[61],
  22396         soc_iprocreg,
  22397         1,
  22398         0,
  22399         0x180212d4,
  22400         0,
  22401         0,
  22402         2,
  22403         soc_QSPI_MSPI_RXRAM05_BCM88470_A0r_fields,
  22404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22405         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22406         -1,
  22407         -1,
  22408     },
  22409 #endif /* chips */
  22410 
  22411 #if defined(BCM_88470_B0)
  22412     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM88470_B0r */
  22413         soc_block_list[61],
  22414         soc_iprocreg,
  22415         1,
  22416         0,
  22417         0x180212d4,
  22418         0,
  22419         0,
  22420         2,
  22421         soc_QSPI_MSPI_RXRAM05_BCM88470_B0r_fields,
  22422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22423         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22424         -1,
  22425         -1,
  22426     },
  22427 #endif /* chips */
  22428 
  22429 #if defined(BCM_88675_B0)
  22430     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM88675_B0r */
  22431         soc_block_list[61],
  22432         soc_iprocreg,
  22433         1,
  22434         0,
  22435         0x180212d4,
  22436         0,
  22437         0,
  22438         2,
  22439         soc_QSPI_MSPI_RXRAM05_BCM88675_B0r_fields,
  22440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22441         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22442         -1,
  22443         -1,
  22444     },
  22445 #endif /* chips */
  22446 
  22447 #if defined(BCM_88680_A0)
  22448     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM88680_A0r */
  22449         soc_block_list[61],
  22450         soc_iprocreg,
  22451         1,
  22452         0,
  22453         0x180212d4,
  22454         0,
  22455         0,
  22456         2,
  22457         soc_QSPI_MSPI_RXRAM05_BCM88680_A0r_fields,
  22458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22459         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22460         -1,
  22461         -1,
  22462     },
  22463 #endif /* chips */
  22464 
  22465 #if defined(BCM_88690_A0)
  22466     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM88690_A0r */
  22467         soc_block_list[61],
  22468         soc_iprocreg,
  22469         1,
  22470         0,
  22471         0x180212d4,
  22472         0,
  22473         0,
  22474         2,
  22475         soc_QSPI_MSPI_RXRAM05_BCM88690_A0r_fields,
  22476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22477         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22478         -1,
  22479         -1,
  22480     },
  22481 #endif /* chips */
  22482 
  22483 #if defined(BCM_88690_B0)
  22484     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM88690_B0r */
  22485         soc_block_list[61],
  22486         soc_iprocreg,
  22487         1,
  22488         0,
  22489         0x180212d4,
  22490         0,
  22491         0,
  22492         2,
  22493         soc_QSPI_MSPI_RXRAM05_BCM88690_B0r_fields,
  22494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22495         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22496         -1,
  22497         -1,
  22498     },
  22499 #endif /* chips */
  22500 
  22501 #if defined(BCM_88790_A0)
  22502     { /* SOC_REG_INT_QSPI_MSPI_RXRAM05_BCM88790_A0r */
  22503         soc_block_list[61],
  22504         soc_iprocreg,
  22505         1,
  22506         0,
  22507         0x180212d4,
  22508         0,
  22509         0,
  22510         2,
  22511         soc_QSPI_MSPI_RXRAM05_BCM88790_A0r_fields,
  22512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22513         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22514         -1,
  22515         -1,
  22516     },
  22517 #endif /* chips */
  22518 
  22519 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22520     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22521     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22522     defined(BCM_56260_B0)
  22523     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM53400_A0r */
  22524         soc_block_list[61],
  22525         soc_iprocreg,
  22526         1,
  22527         0,
  22528         0x180472d8,
  22529         0,
  22530         0,
  22531         2,
  22532         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22534         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22535         -1,
  22536         -1,
  22537     },
  22538 #endif /* chips */
  22539 
  22540 #if defined(BCM_56370_A0)
  22541     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM56370_A0r */
  22542         soc_block_list[61],
  22543         soc_iprocreg,
  22544         1,
  22545         0,
  22546         0x150002d8,
  22547         0,
  22548         0,
  22549         2,
  22550         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22552         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22553         -1,
  22554         -1,
  22555         3,
  22556     },
  22557 #endif /* chips */
  22558 
  22559 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  22560     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  22561     defined(BCM_56450_B1)
  22562     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM56450_A0r */
  22563         soc_block_list[61],
  22564         soc_iprocreg,
  22565         1,
  22566         0,
  22567         0x180272d8,
  22568         0,
  22569         0,
  22570         2,
  22571         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  22572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22573         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22574         -1,
  22575         -1,
  22576     },
  22577 #endif /* chips */
  22578 
  22579 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  22580     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  22581     defined(BCM_56670_B0)
  22582     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM56560_A0r */
  22583         soc_block_list[61],
  22584         soc_iprocreg,
  22585         1,
  22586         0,
  22587         0x180212d8,
  22588         0,
  22589         0,
  22590         2,
  22591         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22593         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22594         -1,
  22595         -1,
  22596     },
  22597 #endif /* chips */
  22598 
  22599 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  22600     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  22601     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  22602     defined(BCM_56980_B0)
  22603     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM56960_A0r */
  22604         soc_block_list[61],
  22605         soc_iprocreg,
  22606         1,
  22607         0,
  22608         0x180212d8,
  22609         0,
  22610         0,
  22611         2,
  22612         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22614         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22615         -1,
  22616         -1,
  22617         3,
  22618     },
  22619 #endif /* chips */
  22620 
  22621 #if defined(BCM_88270_A0)
  22622     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM88270_A0r */
  22623         soc_block_list[61],
  22624         soc_iprocreg,
  22625         1,
  22626         0,
  22627         0x180212d8,
  22628         0,
  22629         0,
  22630         2,
  22631         soc_QSPI_MSPI_RXRAM06_BCM88270_A0r_fields,
  22632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22633         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22634         -1,
  22635         -1,
  22636     },
  22637 #endif /* chips */
  22638 
  22639 #if defined(BCM_88375_A0)
  22640     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM88375_A0r */
  22641         soc_block_list[61],
  22642         soc_iprocreg,
  22643         1,
  22644         0,
  22645         0x180212d8,
  22646         0,
  22647         0,
  22648         2,
  22649         soc_QSPI_MSPI_RXRAM06_BCM88375_A0r_fields,
  22650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22651         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22652         -1,
  22653         -1,
  22654     },
  22655 #endif /* chips */
  22656 
  22657 #if defined(BCM_88375_B0)
  22658     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM88375_B0r */
  22659         soc_block_list[61],
  22660         soc_iprocreg,
  22661         1,
  22662         0,
  22663         0x180212d8,
  22664         0,
  22665         0,
  22666         2,
  22667         soc_QSPI_MSPI_RXRAM06_BCM88375_B0r_fields,
  22668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22670         -1,
  22671         -1,
  22672     },
  22673 #endif /* chips */
  22674 
  22675 #if defined(BCM_88470_A0)
  22676     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM88470_A0r */
  22677         soc_block_list[61],
  22678         soc_iprocreg,
  22679         1,
  22680         0,
  22681         0x180212d8,
  22682         0,
  22683         0,
  22684         2,
  22685         soc_QSPI_MSPI_RXRAM06_BCM88470_A0r_fields,
  22686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22687         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22688         -1,
  22689         -1,
  22690     },
  22691 #endif /* chips */
  22692 
  22693 #if defined(BCM_88470_B0)
  22694     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM88470_B0r */
  22695         soc_block_list[61],
  22696         soc_iprocreg,
  22697         1,
  22698         0,
  22699         0x180212d8,
  22700         0,
  22701         0,
  22702         2,
  22703         soc_QSPI_MSPI_RXRAM06_BCM88470_B0r_fields,
  22704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22705         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22706         -1,
  22707         -1,
  22708     },
  22709 #endif /* chips */
  22710 
  22711 #if defined(BCM_88675_B0)
  22712     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM88675_B0r */
  22713         soc_block_list[61],
  22714         soc_iprocreg,
  22715         1,
  22716         0,
  22717         0x180212d8,
  22718         0,
  22719         0,
  22720         2,
  22721         soc_QSPI_MSPI_RXRAM06_BCM88675_B0r_fields,
  22722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22723         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22724         -1,
  22725         -1,
  22726     },
  22727 #endif /* chips */
  22728 
  22729 #if defined(BCM_88680_A0)
  22730     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM88680_A0r */
  22731         soc_block_list[61],
  22732         soc_iprocreg,
  22733         1,
  22734         0,
  22735         0x180212d8,
  22736         0,
  22737         0,
  22738         2,
  22739         soc_QSPI_MSPI_RXRAM06_BCM88680_A0r_fields,
  22740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22741         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22742         -1,
  22743         -1,
  22744     },
  22745 #endif /* chips */
  22746 
  22747 #if defined(BCM_88690_A0)
  22748     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM88690_A0r */
  22749         soc_block_list[61],
  22750         soc_iprocreg,
  22751         1,
  22752         0,
  22753         0x180212d8,
  22754         0,
  22755         0,
  22756         2,
  22757         soc_QSPI_MSPI_RXRAM06_BCM88690_A0r_fields,
  22758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22760         -1,
  22761         -1,
  22762     },
  22763 #endif /* chips */
  22764 
  22765 #if defined(BCM_88690_B0)
  22766     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM88690_B0r */
  22767         soc_block_list[61],
  22768         soc_iprocreg,
  22769         1,
  22770         0,
  22771         0x180212d8,
  22772         0,
  22773         0,
  22774         2,
  22775         soc_QSPI_MSPI_RXRAM06_BCM88690_B0r_fields,
  22776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22778         -1,
  22779         -1,
  22780     },
  22781 #endif /* chips */
  22782 
  22783 #if defined(BCM_88790_A0)
  22784     { /* SOC_REG_INT_QSPI_MSPI_RXRAM06_BCM88790_A0r */
  22785         soc_block_list[61],
  22786         soc_iprocreg,
  22787         1,
  22788         0,
  22789         0x180212d8,
  22790         0,
  22791         0,
  22792         2,
  22793         soc_QSPI_MSPI_RXRAM06_BCM88790_A0r_fields,
  22794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22796         -1,
  22797         -1,
  22798     },
  22799 #endif /* chips */
  22800 
  22801 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  22802     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  22803     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  22804     defined(BCM_56260_B0)
  22805     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM53400_A0r */
  22806         soc_block_list[61],
  22807         soc_iprocreg,
  22808         1,
  22809         0,
  22810         0x180472dc,
  22811         0,
  22812         0,
  22813         2,
  22814         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22816         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22817         -1,
  22818         -1,
  22819     },
  22820 #endif /* chips */
  22821 
  22822 #if defined(BCM_56370_A0)
  22823     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM56370_A0r */
  22824         soc_block_list[61],
  22825         soc_iprocreg,
  22826         1,
  22827         0,
  22828         0x150002dc,
  22829         0,
  22830         0,
  22831         2,
  22832         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22834         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22835         -1,
  22836         -1,
  22837         3,
  22838     },
  22839 #endif /* chips */
  22840 
  22841 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  22842     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  22843     defined(BCM_56450_B1)
  22844     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM56450_A0r */
  22845         soc_block_list[61],
  22846         soc_iprocreg,
  22847         1,
  22848         0,
  22849         0x180272dc,
  22850         0,
  22851         0,
  22852         2,
  22853         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  22854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22855         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22856         -1,
  22857         -1,
  22858     },
  22859 #endif /* chips */
  22860 
  22861 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  22862     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  22863     defined(BCM_56670_B0)
  22864     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM56560_A0r */
  22865         soc_block_list[61],
  22866         soc_iprocreg,
  22867         1,
  22868         0,
  22869         0x180212dc,
  22870         0,
  22871         0,
  22872         2,
  22873         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22875         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22876         -1,
  22877         -1,
  22878     },
  22879 #endif /* chips */
  22880 
  22881 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  22882     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  22883     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  22884     defined(BCM_56980_B0)
  22885     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM56960_A0r */
  22886         soc_block_list[61],
  22887         soc_iprocreg,
  22888         1,
  22889         0,
  22890         0x180212dc,
  22891         0,
  22892         0,
  22893         2,
  22894         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  22895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22896         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22897         -1,
  22898         -1,
  22899         3,
  22900     },
  22901 #endif /* chips */
  22902 
  22903 #if defined(BCM_88270_A0)
  22904     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM88270_A0r */
  22905         soc_block_list[61],
  22906         soc_iprocreg,
  22907         1,
  22908         0,
  22909         0x180212dc,
  22910         0,
  22911         0,
  22912         2,
  22913         soc_QSPI_MSPI_RXRAM07_BCM88270_A0r_fields,
  22914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22916         -1,
  22917         -1,
  22918     },
  22919 #endif /* chips */
  22920 
  22921 #if defined(BCM_88375_A0)
  22922     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM88375_A0r */
  22923         soc_block_list[61],
  22924         soc_iprocreg,
  22925         1,
  22926         0,
  22927         0x180212dc,
  22928         0,
  22929         0,
  22930         2,
  22931         soc_QSPI_MSPI_RXRAM07_BCM88375_A0r_fields,
  22932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22933         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22934         -1,
  22935         -1,
  22936     },
  22937 #endif /* chips */
  22938 
  22939 #if defined(BCM_88375_B0)
  22940     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM88375_B0r */
  22941         soc_block_list[61],
  22942         soc_iprocreg,
  22943         1,
  22944         0,
  22945         0x180212dc,
  22946         0,
  22947         0,
  22948         2,
  22949         soc_QSPI_MSPI_RXRAM07_BCM88375_B0r_fields,
  22950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22952         -1,
  22953         -1,
  22954     },
  22955 #endif /* chips */
  22956 
  22957 #if defined(BCM_88470_A0)
  22958     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM88470_A0r */
  22959         soc_block_list[61],
  22960         soc_iprocreg,
  22961         1,
  22962         0,
  22963         0x180212dc,
  22964         0,
  22965         0,
  22966         2,
  22967         soc_QSPI_MSPI_RXRAM07_BCM88470_A0r_fields,
  22968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22969         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22970         -1,
  22971         -1,
  22972     },
  22973 #endif /* chips */
  22974 
  22975 #if defined(BCM_88470_B0)
  22976     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM88470_B0r */
  22977         soc_block_list[61],
  22978         soc_iprocreg,
  22979         1,
  22980         0,
  22981         0x180212dc,
  22982         0,
  22983         0,
  22984         2,
  22985         soc_QSPI_MSPI_RXRAM07_BCM88470_B0r_fields,
  22986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22987         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22988         -1,
  22989         -1,
  22990     },
  22991 #endif /* chips */
  22992 
  22993 #if defined(BCM_88675_B0)
  22994     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM88675_B0r */
  22995         soc_block_list[61],
  22996         soc_iprocreg,
  22997         1,
  22998         0,
  22999         0x180212dc,
  23000         0,
  23001         0,
  23002         2,
  23003         soc_QSPI_MSPI_RXRAM07_BCM88675_B0r_fields,
  23004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23005         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23006         -1,
  23007         -1,
  23008     },
  23009 #endif /* chips */
  23010 
  23011 #if defined(BCM_88680_A0)
  23012     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM88680_A0r */
  23013         soc_block_list[61],
  23014         soc_iprocreg,
  23015         1,
  23016         0,
  23017         0x180212dc,
  23018         0,
  23019         0,
  23020         2,
  23021         soc_QSPI_MSPI_RXRAM07_BCM88680_A0r_fields,
  23022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23023         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23024         -1,
  23025         -1,
  23026     },
  23027 #endif /* chips */
  23028 
  23029 #if defined(BCM_88690_A0)
  23030     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM88690_A0r */
  23031         soc_block_list[61],
  23032         soc_iprocreg,
  23033         1,
  23034         0,
  23035         0x180212dc,
  23036         0,
  23037         0,
  23038         2,
  23039         soc_QSPI_MSPI_RXRAM07_BCM88690_A0r_fields,
  23040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23041         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23042         -1,
  23043         -1,
  23044     },
  23045 #endif /* chips */
  23046 
  23047 #if defined(BCM_88690_B0)
  23048     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM88690_B0r */
  23049         soc_block_list[61],
  23050         soc_iprocreg,
  23051         1,
  23052         0,
  23053         0x180212dc,
  23054         0,
  23055         0,
  23056         2,
  23057         soc_QSPI_MSPI_RXRAM07_BCM88690_B0r_fields,
  23058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23059         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23060         -1,
  23061         -1,
  23062     },
  23063 #endif /* chips */
  23064 
  23065 #if defined(BCM_88790_A0)
  23066     { /* SOC_REG_INT_QSPI_MSPI_RXRAM07_BCM88790_A0r */
  23067         soc_block_list[61],
  23068         soc_iprocreg,
  23069         1,
  23070         0,
  23071         0x180212dc,
  23072         0,
  23073         0,
  23074         2,
  23075         soc_QSPI_MSPI_RXRAM07_BCM88790_A0r_fields,
  23076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23078         -1,
  23079         -1,
  23080     },
  23081 #endif /* chips */
  23082 
  23083 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23084     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23085     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23086     defined(BCM_56260_B0)
  23087     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM53400_A0r */
  23088         soc_block_list[61],
  23089         soc_iprocreg,
  23090         1,
  23091         0,
  23092         0x180472e0,
  23093         0,
  23094         0,
  23095         2,
  23096         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23098         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23099         -1,
  23100         -1,
  23101     },
  23102 #endif /* chips */
  23103 
  23104 #if defined(BCM_56370_A0)
  23105     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM56370_A0r */
  23106         soc_block_list[61],
  23107         soc_iprocreg,
  23108         1,
  23109         0,
  23110         0x150002e0,
  23111         0,
  23112         0,
  23113         2,
  23114         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23116         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23117         -1,
  23118         -1,
  23119         3,
  23120     },
  23121 #endif /* chips */
  23122 
  23123 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23124     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23125     defined(BCM_56450_B1)
  23126     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM56450_A0r */
  23127         soc_block_list[61],
  23128         soc_iprocreg,
  23129         1,
  23130         0,
  23131         0x180272e0,
  23132         0,
  23133         0,
  23134         2,
  23135         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  23136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23138         -1,
  23139         -1,
  23140     },
  23141 #endif /* chips */
  23142 
  23143 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  23144     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  23145     defined(BCM_56670_B0)
  23146     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM56560_A0r */
  23147         soc_block_list[61],
  23148         soc_iprocreg,
  23149         1,
  23150         0,
  23151         0x180212e0,
  23152         0,
  23153         0,
  23154         2,
  23155         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23157         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23158         -1,
  23159         -1,
  23160     },
  23161 #endif /* chips */
  23162 
  23163 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  23164     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  23165     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  23166     defined(BCM_56980_B0)
  23167     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM56960_A0r */
  23168         soc_block_list[61],
  23169         soc_iprocreg,
  23170         1,
  23171         0,
  23172         0x180212e0,
  23173         0,
  23174         0,
  23175         2,
  23176         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23178         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23179         -1,
  23180         -1,
  23181         3,
  23182     },
  23183 #endif /* chips */
  23184 
  23185 #if defined(BCM_88270_A0)
  23186     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM88270_A0r */
  23187         soc_block_list[61],
  23188         soc_iprocreg,
  23189         1,
  23190         0,
  23191         0x180212e0,
  23192         0,
  23193         0,
  23194         2,
  23195         soc_QSPI_MSPI_RXRAM08_BCM88270_A0r_fields,
  23196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23197         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23198         -1,
  23199         -1,
  23200     },
  23201 #endif /* chips */
  23202 
  23203 #if defined(BCM_88375_A0)
  23204     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM88375_A0r */
  23205         soc_block_list[61],
  23206         soc_iprocreg,
  23207         1,
  23208         0,
  23209         0x180212e0,
  23210         0,
  23211         0,
  23212         2,
  23213         soc_QSPI_MSPI_RXRAM08_BCM88375_A0r_fields,
  23214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23215         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23216         -1,
  23217         -1,
  23218     },
  23219 #endif /* chips */
  23220 
  23221 #if defined(BCM_88375_B0)
  23222     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM88375_B0r */
  23223         soc_block_list[61],
  23224         soc_iprocreg,
  23225         1,
  23226         0,
  23227         0x180212e0,
  23228         0,
  23229         0,
  23230         2,
  23231         soc_QSPI_MSPI_RXRAM08_BCM88375_B0r_fields,
  23232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23233         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23234         -1,
  23235         -1,
  23236     },
  23237 #endif /* chips */
  23238 
  23239 #if defined(BCM_88470_A0)
  23240     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM88470_A0r */
  23241         soc_block_list[61],
  23242         soc_iprocreg,
  23243         1,
  23244         0,
  23245         0x180212e0,
  23246         0,
  23247         0,
  23248         2,
  23249         soc_QSPI_MSPI_RXRAM08_BCM88470_A0r_fields,
  23250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23251         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23252         -1,
  23253         -1,
  23254     },
  23255 #endif /* chips */
  23256 
  23257 #if defined(BCM_88470_B0)
  23258     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM88470_B0r */
  23259         soc_block_list[61],
  23260         soc_iprocreg,
  23261         1,
  23262         0,
  23263         0x180212e0,
  23264         0,
  23265         0,
  23266         2,
  23267         soc_QSPI_MSPI_RXRAM08_BCM88470_B0r_fields,
  23268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23269         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23270         -1,
  23271         -1,
  23272     },
  23273 #endif /* chips */
  23274 
  23275 #if defined(BCM_88675_B0)
  23276     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM88675_B0r */
  23277         soc_block_list[61],
  23278         soc_iprocreg,
  23279         1,
  23280         0,
  23281         0x180212e0,
  23282         0,
  23283         0,
  23284         2,
  23285         soc_QSPI_MSPI_RXRAM08_BCM88675_B0r_fields,
  23286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23287         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23288         -1,
  23289         -1,
  23290     },
  23291 #endif /* chips */
  23292 
  23293 #if defined(BCM_88680_A0)
  23294     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM88680_A0r */
  23295         soc_block_list[61],
  23296         soc_iprocreg,
  23297         1,
  23298         0,
  23299         0x180212e0,
  23300         0,
  23301         0,
  23302         2,
  23303         soc_QSPI_MSPI_RXRAM08_BCM88680_A0r_fields,
  23304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23305         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23306         -1,
  23307         -1,
  23308     },
  23309 #endif /* chips */
  23310 
  23311 #if defined(BCM_88690_A0)
  23312     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM88690_A0r */
  23313         soc_block_list[61],
  23314         soc_iprocreg,
  23315         1,
  23316         0,
  23317         0x180212e0,
  23318         0,
  23319         0,
  23320         2,
  23321         soc_QSPI_MSPI_RXRAM08_BCM88690_A0r_fields,
  23322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23323         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23324         -1,
  23325         -1,
  23326     },
  23327 #endif /* chips */
  23328 
  23329 #if defined(BCM_88690_B0)
  23330     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM88690_B0r */
  23331         soc_block_list[61],
  23332         soc_iprocreg,
  23333         1,
  23334         0,
  23335         0x180212e0,
  23336         0,
  23337         0,
  23338         2,
  23339         soc_QSPI_MSPI_RXRAM08_BCM88690_B0r_fields,
  23340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23341         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23342         -1,
  23343         -1,
  23344     },
  23345 #endif /* chips */
  23346 
  23347 #if defined(BCM_88790_A0)
  23348     { /* SOC_REG_INT_QSPI_MSPI_RXRAM08_BCM88790_A0r */
  23349         soc_block_list[61],
  23350         soc_iprocreg,
  23351         1,
  23352         0,
  23353         0x180212e0,
  23354         0,
  23355         0,
  23356         2,
  23357         soc_QSPI_MSPI_RXRAM08_BCM88790_A0r_fields,
  23358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23359         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23360         -1,
  23361         -1,
  23362     },
  23363 #endif /* chips */
  23364 
  23365 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23366     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23367     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23368     defined(BCM_56260_B0)
  23369     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM53400_A0r */
  23370         soc_block_list[61],
  23371         soc_iprocreg,
  23372         1,
  23373         0,
  23374         0x180472e4,
  23375         0,
  23376         0,
  23377         2,
  23378         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23380         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23381         -1,
  23382         -1,
  23383     },
  23384 #endif /* chips */
  23385 
  23386 #if defined(BCM_56370_A0)
  23387     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM56370_A0r */
  23388         soc_block_list[61],
  23389         soc_iprocreg,
  23390         1,
  23391         0,
  23392         0x150002e4,
  23393         0,
  23394         0,
  23395         2,
  23396         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23398         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23399         -1,
  23400         -1,
  23401         3,
  23402     },
  23403 #endif /* chips */
  23404 
  23405 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23406     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23407     defined(BCM_56450_B1)
  23408     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM56450_A0r */
  23409         soc_block_list[61],
  23410         soc_iprocreg,
  23411         1,
  23412         0,
  23413         0x180272e4,
  23414         0,
  23415         0,
  23416         2,
  23417         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  23418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23420         -1,
  23421         -1,
  23422     },
  23423 #endif /* chips */
  23424 
  23425 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  23426     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  23427     defined(BCM_56670_B0)
  23428     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM56560_A0r */
  23429         soc_block_list[61],
  23430         soc_iprocreg,
  23431         1,
  23432         0,
  23433         0x180212e4,
  23434         0,
  23435         0,
  23436         2,
  23437         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23439         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23440         -1,
  23441         -1,
  23442     },
  23443 #endif /* chips */
  23444 
  23445 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  23446     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  23447     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  23448     defined(BCM_56980_B0)
  23449     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM56960_A0r */
  23450         soc_block_list[61],
  23451         soc_iprocreg,
  23452         1,
  23453         0,
  23454         0x180212e4,
  23455         0,
  23456         0,
  23457         2,
  23458         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23460         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23461         -1,
  23462         -1,
  23463         3,
  23464     },
  23465 #endif /* chips */
  23466 
  23467 #if defined(BCM_88270_A0)
  23468     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM88270_A0r */
  23469         soc_block_list[61],
  23470         soc_iprocreg,
  23471         1,
  23472         0,
  23473         0x180212e4,
  23474         0,
  23475         0,
  23476         2,
  23477         soc_QSPI_MSPI_RXRAM09_BCM88270_A0r_fields,
  23478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23479         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23480         -1,
  23481         -1,
  23482     },
  23483 #endif /* chips */
  23484 
  23485 #if defined(BCM_88375_A0)
  23486     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM88375_A0r */
  23487         soc_block_list[61],
  23488         soc_iprocreg,
  23489         1,
  23490         0,
  23491         0x180212e4,
  23492         0,
  23493         0,
  23494         2,
  23495         soc_QSPI_MSPI_RXRAM09_BCM88375_A0r_fields,
  23496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23498         -1,
  23499         -1,
  23500     },
  23501 #endif /* chips */
  23502 
  23503 #if defined(BCM_88375_B0)
  23504     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM88375_B0r */
  23505         soc_block_list[61],
  23506         soc_iprocreg,
  23507         1,
  23508         0,
  23509         0x180212e4,
  23510         0,
  23511         0,
  23512         2,
  23513         soc_QSPI_MSPI_RXRAM09_BCM88375_B0r_fields,
  23514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23516         -1,
  23517         -1,
  23518     },
  23519 #endif /* chips */
  23520 
  23521 #if defined(BCM_88470_A0)
  23522     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM88470_A0r */
  23523         soc_block_list[61],
  23524         soc_iprocreg,
  23525         1,
  23526         0,
  23527         0x180212e4,
  23528         0,
  23529         0,
  23530         2,
  23531         soc_QSPI_MSPI_RXRAM09_BCM88470_A0r_fields,
  23532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23534         -1,
  23535         -1,
  23536     },
  23537 #endif /* chips */
  23538 
  23539 #if defined(BCM_88470_B0)
  23540     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM88470_B0r */
  23541         soc_block_list[61],
  23542         soc_iprocreg,
  23543         1,
  23544         0,
  23545         0x180212e4,
  23546         0,
  23547         0,
  23548         2,
  23549         soc_QSPI_MSPI_RXRAM09_BCM88470_B0r_fields,
  23550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23551         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23552         -1,
  23553         -1,
  23554     },
  23555 #endif /* chips */
  23556 
  23557 #if defined(BCM_88675_B0)
  23558     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM88675_B0r */
  23559         soc_block_list[61],
  23560         soc_iprocreg,
  23561         1,
  23562         0,
  23563         0x180212e4,
  23564         0,
  23565         0,
  23566         2,
  23567         soc_QSPI_MSPI_RXRAM09_BCM88675_B0r_fields,
  23568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23569         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23570         -1,
  23571         -1,
  23572     },
  23573 #endif /* chips */
  23574 
  23575 #if defined(BCM_88680_A0)
  23576     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM88680_A0r */
  23577         soc_block_list[61],
  23578         soc_iprocreg,
  23579         1,
  23580         0,
  23581         0x180212e4,
  23582         0,
  23583         0,
  23584         2,
  23585         soc_QSPI_MSPI_RXRAM09_BCM88680_A0r_fields,
  23586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23587         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23588         -1,
  23589         -1,
  23590     },
  23591 #endif /* chips */
  23592 
  23593 #if defined(BCM_88690_A0)
  23594     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM88690_A0r */
  23595         soc_block_list[61],
  23596         soc_iprocreg,
  23597         1,
  23598         0,
  23599         0x180212e4,
  23600         0,
  23601         0,
  23602         2,
  23603         soc_QSPI_MSPI_RXRAM09_BCM88690_A0r_fields,
  23604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23605         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23606         -1,
  23607         -1,
  23608     },
  23609 #endif /* chips */
  23610 
  23611 #if defined(BCM_88690_B0)
  23612     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM88690_B0r */
  23613         soc_block_list[61],
  23614         soc_iprocreg,
  23615         1,
  23616         0,
  23617         0x180212e4,
  23618         0,
  23619         0,
  23620         2,
  23621         soc_QSPI_MSPI_RXRAM09_BCM88690_B0r_fields,
  23622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23623         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23624         -1,
  23625         -1,
  23626     },
  23627 #endif /* chips */
  23628 
  23629 #if defined(BCM_88790_A0)
  23630     { /* SOC_REG_INT_QSPI_MSPI_RXRAM09_BCM88790_A0r */
  23631         soc_block_list[61],
  23632         soc_iprocreg,
  23633         1,
  23634         0,
  23635         0x180212e4,
  23636         0,
  23637         0,
  23638         2,
  23639         soc_QSPI_MSPI_RXRAM09_BCM88790_A0r_fields,
  23640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23641         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23642         -1,
  23643         -1,
  23644     },
  23645 #endif /* chips */
  23646 
  23647 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23648     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23649     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23650     defined(BCM_56260_B0)
  23651     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM53400_A0r */
  23652         soc_block_list[61],
  23653         soc_iprocreg,
  23654         1,
  23655         0,
  23656         0x180472e8,
  23657         0,
  23658         0,
  23659         2,
  23660         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23662         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23663         -1,
  23664         -1,
  23665     },
  23666 #endif /* chips */
  23667 
  23668 #if defined(BCM_56370_A0)
  23669     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM56370_A0r */
  23670         soc_block_list[61],
  23671         soc_iprocreg,
  23672         1,
  23673         0,
  23674         0x150002e8,
  23675         0,
  23676         0,
  23677         2,
  23678         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23680         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23681         -1,
  23682         -1,
  23683         3,
  23684     },
  23685 #endif /* chips */
  23686 
  23687 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23688     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23689     defined(BCM_56450_B1)
  23690     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM56450_A0r */
  23691         soc_block_list[61],
  23692         soc_iprocreg,
  23693         1,
  23694         0,
  23695         0x180272e8,
  23696         0,
  23697         0,
  23698         2,
  23699         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  23700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23701         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23702         -1,
  23703         -1,
  23704     },
  23705 #endif /* chips */
  23706 
  23707 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  23708     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  23709     defined(BCM_56670_B0)
  23710     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM56560_A0r */
  23711         soc_block_list[61],
  23712         soc_iprocreg,
  23713         1,
  23714         0,
  23715         0x180212e8,
  23716         0,
  23717         0,
  23718         2,
  23719         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23721         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23722         -1,
  23723         -1,
  23724     },
  23725 #endif /* chips */
  23726 
  23727 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  23728     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  23729     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  23730     defined(BCM_56980_B0)
  23731     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM56960_A0r */
  23732         soc_block_list[61],
  23733         soc_iprocreg,
  23734         1,
  23735         0,
  23736         0x180212e8,
  23737         0,
  23738         0,
  23739         2,
  23740         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23742         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23743         -1,
  23744         -1,
  23745         3,
  23746     },
  23747 #endif /* chips */
  23748 
  23749 #if defined(BCM_88270_A0)
  23750     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM88270_A0r */
  23751         soc_block_list[61],
  23752         soc_iprocreg,
  23753         1,
  23754         0,
  23755         0x180212e8,
  23756         0,
  23757         0,
  23758         2,
  23759         soc_QSPI_MSPI_RXRAM10_BCM88270_A0r_fields,
  23760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23762         -1,
  23763         -1,
  23764     },
  23765 #endif /* chips */
  23766 
  23767 #if defined(BCM_88375_A0)
  23768     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM88375_A0r */
  23769         soc_block_list[61],
  23770         soc_iprocreg,
  23771         1,
  23772         0,
  23773         0x180212e8,
  23774         0,
  23775         0,
  23776         2,
  23777         soc_QSPI_MSPI_RXRAM10_BCM88375_A0r_fields,
  23778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23779         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23780         -1,
  23781         -1,
  23782     },
  23783 #endif /* chips */
  23784 
  23785 #if defined(BCM_88375_B0)
  23786     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM88375_B0r */
  23787         soc_block_list[61],
  23788         soc_iprocreg,
  23789         1,
  23790         0,
  23791         0x180212e8,
  23792         0,
  23793         0,
  23794         2,
  23795         soc_QSPI_MSPI_RXRAM10_BCM88375_B0r_fields,
  23796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23797         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23798         -1,
  23799         -1,
  23800     },
  23801 #endif /* chips */
  23802 
  23803 #if defined(BCM_88470_A0)
  23804     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM88470_A0r */
  23805         soc_block_list[61],
  23806         soc_iprocreg,
  23807         1,
  23808         0,
  23809         0x180212e8,
  23810         0,
  23811         0,
  23812         2,
  23813         soc_QSPI_MSPI_RXRAM10_BCM88470_A0r_fields,
  23814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23815         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23816         -1,
  23817         -1,
  23818     },
  23819 #endif /* chips */
  23820 
  23821 #if defined(BCM_88470_B0)
  23822     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM88470_B0r */
  23823         soc_block_list[61],
  23824         soc_iprocreg,
  23825         1,
  23826         0,
  23827         0x180212e8,
  23828         0,
  23829         0,
  23830         2,
  23831         soc_QSPI_MSPI_RXRAM10_BCM88470_B0r_fields,
  23832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23833         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23834         -1,
  23835         -1,
  23836     },
  23837 #endif /* chips */
  23838 
  23839 #if defined(BCM_88675_B0)
  23840     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM88675_B0r */
  23841         soc_block_list[61],
  23842         soc_iprocreg,
  23843         1,
  23844         0,
  23845         0x180212e8,
  23846         0,
  23847         0,
  23848         2,
  23849         soc_QSPI_MSPI_RXRAM10_BCM88675_B0r_fields,
  23850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23851         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23852         -1,
  23853         -1,
  23854     },
  23855 #endif /* chips */
  23856 
  23857 #if defined(BCM_88680_A0)
  23858     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM88680_A0r */
  23859         soc_block_list[61],
  23860         soc_iprocreg,
  23861         1,
  23862         0,
  23863         0x180212e8,
  23864         0,
  23865         0,
  23866         2,
  23867         soc_QSPI_MSPI_RXRAM10_BCM88680_A0r_fields,
  23868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23869         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23870         -1,
  23871         -1,
  23872     },
  23873 #endif /* chips */
  23874 
  23875 #if defined(BCM_88690_A0)
  23876     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM88690_A0r */
  23877         soc_block_list[61],
  23878         soc_iprocreg,
  23879         1,
  23880         0,
  23881         0x180212e8,
  23882         0,
  23883         0,
  23884         2,
  23885         soc_QSPI_MSPI_RXRAM10_BCM88690_A0r_fields,
  23886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23887         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23888         -1,
  23889         -1,
  23890     },
  23891 #endif /* chips */
  23892 
  23893 #if defined(BCM_88690_B0)
  23894     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM88690_B0r */
  23895         soc_block_list[61],
  23896         soc_iprocreg,
  23897         1,
  23898         0,
  23899         0x180212e8,
  23900         0,
  23901         0,
  23902         2,
  23903         soc_QSPI_MSPI_RXRAM10_BCM88690_B0r_fields,
  23904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23905         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23906         -1,
  23907         -1,
  23908     },
  23909 #endif /* chips */
  23910 
  23911 #if defined(BCM_88790_A0)
  23912     { /* SOC_REG_INT_QSPI_MSPI_RXRAM10_BCM88790_A0r */
  23913         soc_block_list[61],
  23914         soc_iprocreg,
  23915         1,
  23916         0,
  23917         0x180212e8,
  23918         0,
  23919         0,
  23920         2,
  23921         soc_QSPI_MSPI_RXRAM10_BCM88790_A0r_fields,
  23922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23923         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23924         -1,
  23925         -1,
  23926     },
  23927 #endif /* chips */
  23928 
  23929 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  23930     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  23931     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  23932     defined(BCM_56260_B0)
  23933     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM53400_A0r */
  23934         soc_block_list[61],
  23935         soc_iprocreg,
  23936         1,
  23937         0,
  23938         0x180472ec,
  23939         0,
  23940         0,
  23941         2,
  23942         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23944         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23945         -1,
  23946         -1,
  23947     },
  23948 #endif /* chips */
  23949 
  23950 #if defined(BCM_56370_A0)
  23951     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM56370_A0r */
  23952         soc_block_list[61],
  23953         soc_iprocreg,
  23954         1,
  23955         0,
  23956         0x150002ec,
  23957         0,
  23958         0,
  23959         2,
  23960         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  23961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23962         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23963         -1,
  23964         -1,
  23965         3,
  23966     },
  23967 #endif /* chips */
  23968 
  23969 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  23970     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  23971     defined(BCM_56450_B1)
  23972     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM56450_A0r */
  23973         soc_block_list[61],
  23974         soc_iprocreg,
  23975         1,
  23976         0,
  23977         0x180272ec,
  23978         0,
  23979         0,
  23980         2,
  23981         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  23982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23983         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23984         -1,
  23985         -1,
  23986     },
  23987 #endif /* chips */
  23988 
  23989 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  23990     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  23991     defined(BCM_56670_B0)
  23992     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM56560_A0r */
  23993         soc_block_list[61],
  23994         soc_iprocreg,
  23995         1,
  23996         0,
  23997         0x180212ec,
  23998         0,
  23999         0,
  24000         2,
  24001         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24003         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24004         -1,
  24005         -1,
  24006     },
  24007 #endif /* chips */
  24008 
  24009 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  24010     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  24011     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  24012     defined(BCM_56980_B0)
  24013     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM56960_A0r */
  24014         soc_block_list[61],
  24015         soc_iprocreg,
  24016         1,
  24017         0,
  24018         0x180212ec,
  24019         0,
  24020         0,
  24021         2,
  24022         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24024         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24025         -1,
  24026         -1,
  24027         3,
  24028     },
  24029 #endif /* chips */
  24030 
  24031 #if defined(BCM_88270_A0)
  24032     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM88270_A0r */
  24033         soc_block_list[61],
  24034         soc_iprocreg,
  24035         1,
  24036         0,
  24037         0x180212ec,
  24038         0,
  24039         0,
  24040         2,
  24041         soc_QSPI_MSPI_RXRAM11_BCM88270_A0r_fields,
  24042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24043         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24044         -1,
  24045         -1,
  24046     },
  24047 #endif /* chips */
  24048 
  24049 #if defined(BCM_88375_A0)
  24050     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM88375_A0r */
  24051         soc_block_list[61],
  24052         soc_iprocreg,
  24053         1,
  24054         0,
  24055         0x180212ec,
  24056         0,
  24057         0,
  24058         2,
  24059         soc_QSPI_MSPI_RXRAM11_BCM88375_A0r_fields,
  24060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24061         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24062         -1,
  24063         -1,
  24064     },
  24065 #endif /* chips */
  24066 
  24067 #if defined(BCM_88375_B0)
  24068     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM88375_B0r */
  24069         soc_block_list[61],
  24070         soc_iprocreg,
  24071         1,
  24072         0,
  24073         0x180212ec,
  24074         0,
  24075         0,
  24076         2,
  24077         soc_QSPI_MSPI_RXRAM11_BCM88375_B0r_fields,
  24078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24079         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24080         -1,
  24081         -1,
  24082     },
  24083 #endif /* chips */
  24084 
  24085 #if defined(BCM_88470_A0)
  24086     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM88470_A0r */
  24087         soc_block_list[61],
  24088         soc_iprocreg,
  24089         1,
  24090         0,
  24091         0x180212ec,
  24092         0,
  24093         0,
  24094         2,
  24095         soc_QSPI_MSPI_RXRAM11_BCM88470_A0r_fields,
  24096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24098         -1,
  24099         -1,
  24100     },
  24101 #endif /* chips */
  24102 
  24103 #if defined(BCM_88470_B0)
  24104     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM88470_B0r */
  24105         soc_block_list[61],
  24106         soc_iprocreg,
  24107         1,
  24108         0,
  24109         0x180212ec,
  24110         0,
  24111         0,
  24112         2,
  24113         soc_QSPI_MSPI_RXRAM11_BCM88470_B0r_fields,
  24114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24116         -1,
  24117         -1,
  24118     },
  24119 #endif /* chips */
  24120 
  24121 #if defined(BCM_88675_B0)
  24122     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM88675_B0r */
  24123         soc_block_list[61],
  24124         soc_iprocreg,
  24125         1,
  24126         0,
  24127         0x180212ec,
  24128         0,
  24129         0,
  24130         2,
  24131         soc_QSPI_MSPI_RXRAM11_BCM88675_B0r_fields,
  24132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24133         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24134         -1,
  24135         -1,
  24136     },
  24137 #endif /* chips */
  24138 
  24139 #if defined(BCM_88680_A0)
  24140     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM88680_A0r */
  24141         soc_block_list[61],
  24142         soc_iprocreg,
  24143         1,
  24144         0,
  24145         0x180212ec,
  24146         0,
  24147         0,
  24148         2,
  24149         soc_QSPI_MSPI_RXRAM11_BCM88680_A0r_fields,
  24150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24151         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24152         -1,
  24153         -1,
  24154     },
  24155 #endif /* chips */
  24156 
  24157 #if defined(BCM_88690_A0)
  24158     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM88690_A0r */
  24159         soc_block_list[61],
  24160         soc_iprocreg,
  24161         1,
  24162         0,
  24163         0x180212ec,
  24164         0,
  24165         0,
  24166         2,
  24167         soc_QSPI_MSPI_RXRAM11_BCM88690_A0r_fields,
  24168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24169         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24170         -1,
  24171         -1,
  24172     },
  24173 #endif /* chips */
  24174 
  24175 #if defined(BCM_88690_B0)
  24176     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM88690_B0r */
  24177         soc_block_list[61],
  24178         soc_iprocreg,
  24179         1,
  24180         0,
  24181         0x180212ec,
  24182         0,
  24183         0,
  24184         2,
  24185         soc_QSPI_MSPI_RXRAM11_BCM88690_B0r_fields,
  24186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24187         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24188         -1,
  24189         -1,
  24190     },
  24191 #endif /* chips */
  24192 
  24193 #if defined(BCM_88790_A0)
  24194     { /* SOC_REG_INT_QSPI_MSPI_RXRAM11_BCM88790_A0r */
  24195         soc_block_list[61],
  24196         soc_iprocreg,
  24197         1,
  24198         0,
  24199         0x180212ec,
  24200         0,
  24201         0,
  24202         2,
  24203         soc_QSPI_MSPI_RXRAM11_BCM88790_A0r_fields,
  24204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24205         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24206         -1,
  24207         -1,
  24208     },
  24209 #endif /* chips */
  24210 
  24211 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24212     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24213     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24214     defined(BCM_56260_B0)
  24215     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM53400_A0r */
  24216         soc_block_list[61],
  24217         soc_iprocreg,
  24218         1,
  24219         0,
  24220         0x180472f0,
  24221         0,
  24222         0,
  24223         2,
  24224         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24226         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24227         -1,
  24228         -1,
  24229     },
  24230 #endif /* chips */
  24231 
  24232 #if defined(BCM_56370_A0)
  24233     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM56370_A0r */
  24234         soc_block_list[61],
  24235         soc_iprocreg,
  24236         1,
  24237         0,
  24238         0x150002f0,
  24239         0,
  24240         0,
  24241         2,
  24242         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24244         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24245         -1,
  24246         -1,
  24247         3,
  24248     },
  24249 #endif /* chips */
  24250 
  24251 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24252     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24253     defined(BCM_56450_B1)
  24254     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM56450_A0r */
  24255         soc_block_list[61],
  24256         soc_iprocreg,
  24257         1,
  24258         0,
  24259         0x180272f0,
  24260         0,
  24261         0,
  24262         2,
  24263         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  24264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24265         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24266         -1,
  24267         -1,
  24268     },
  24269 #endif /* chips */
  24270 
  24271 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  24272     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  24273     defined(BCM_56670_B0)
  24274     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM56560_A0r */
  24275         soc_block_list[61],
  24276         soc_iprocreg,
  24277         1,
  24278         0,
  24279         0x180212f0,
  24280         0,
  24281         0,
  24282         2,
  24283         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24285         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24286         -1,
  24287         -1,
  24288     },
  24289 #endif /* chips */
  24290 
  24291 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  24292     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  24293     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  24294     defined(BCM_56980_B0)
  24295     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM56960_A0r */
  24296         soc_block_list[61],
  24297         soc_iprocreg,
  24298         1,
  24299         0,
  24300         0x180212f0,
  24301         0,
  24302         0,
  24303         2,
  24304         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24306         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24307         -1,
  24308         -1,
  24309         3,
  24310     },
  24311 #endif /* chips */
  24312 
  24313 #if defined(BCM_88270_A0)
  24314     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM88270_A0r */
  24315         soc_block_list[61],
  24316         soc_iprocreg,
  24317         1,
  24318         0,
  24319         0x180212f0,
  24320         0,
  24321         0,
  24322         2,
  24323         soc_QSPI_MSPI_RXRAM12_BCM88270_A0r_fields,
  24324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24325         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24326         -1,
  24327         -1,
  24328     },
  24329 #endif /* chips */
  24330 
  24331 #if defined(BCM_88375_A0)
  24332     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM88375_A0r */
  24333         soc_block_list[61],
  24334         soc_iprocreg,
  24335         1,
  24336         0,
  24337         0x180212f0,
  24338         0,
  24339         0,
  24340         2,
  24341         soc_QSPI_MSPI_RXRAM12_BCM88375_A0r_fields,
  24342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24343         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24344         -1,
  24345         -1,
  24346     },
  24347 #endif /* chips */
  24348 
  24349 #if defined(BCM_88375_B0)
  24350     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM88375_B0r */
  24351         soc_block_list[61],
  24352         soc_iprocreg,
  24353         1,
  24354         0,
  24355         0x180212f0,
  24356         0,
  24357         0,
  24358         2,
  24359         soc_QSPI_MSPI_RXRAM12_BCM88375_B0r_fields,
  24360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24361         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24362         -1,
  24363         -1,
  24364     },
  24365 #endif /* chips */
  24366 
  24367 #if defined(BCM_88470_A0)
  24368     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM88470_A0r */
  24369         soc_block_list[61],
  24370         soc_iprocreg,
  24371         1,
  24372         0,
  24373         0x180212f0,
  24374         0,
  24375         0,
  24376         2,
  24377         soc_QSPI_MSPI_RXRAM12_BCM88470_A0r_fields,
  24378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24379         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24380         -1,
  24381         -1,
  24382     },
  24383 #endif /* chips */
  24384 
  24385 #if defined(BCM_88470_B0)
  24386     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM88470_B0r */
  24387         soc_block_list[61],
  24388         soc_iprocreg,
  24389         1,
  24390         0,
  24391         0x180212f0,
  24392         0,
  24393         0,
  24394         2,
  24395         soc_QSPI_MSPI_RXRAM12_BCM88470_B0r_fields,
  24396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24397         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24398         -1,
  24399         -1,
  24400     },
  24401 #endif /* chips */
  24402 
  24403 #if defined(BCM_88675_B0)
  24404     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM88675_B0r */
  24405         soc_block_list[61],
  24406         soc_iprocreg,
  24407         1,
  24408         0,
  24409         0x180212f0,
  24410         0,
  24411         0,
  24412         2,
  24413         soc_QSPI_MSPI_RXRAM12_BCM88675_B0r_fields,
  24414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24416         -1,
  24417         -1,
  24418     },
  24419 #endif /* chips */
  24420 
  24421 #if defined(BCM_88680_A0)
  24422     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM88680_A0r */
  24423         soc_block_list[61],
  24424         soc_iprocreg,
  24425         1,
  24426         0,
  24427         0x180212f0,
  24428         0,
  24429         0,
  24430         2,
  24431         soc_QSPI_MSPI_RXRAM12_BCM88680_A0r_fields,
  24432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24433         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24434         -1,
  24435         -1,
  24436     },
  24437 #endif /* chips */
  24438 
  24439 #if defined(BCM_88690_A0)
  24440     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM88690_A0r */
  24441         soc_block_list[61],
  24442         soc_iprocreg,
  24443         1,
  24444         0,
  24445         0x180212f0,
  24446         0,
  24447         0,
  24448         2,
  24449         soc_QSPI_MSPI_RXRAM12_BCM88690_A0r_fields,
  24450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24451         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24452         -1,
  24453         -1,
  24454     },
  24455 #endif /* chips */
  24456 
  24457 #if defined(BCM_88690_B0)
  24458     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM88690_B0r */
  24459         soc_block_list[61],
  24460         soc_iprocreg,
  24461         1,
  24462         0,
  24463         0x180212f0,
  24464         0,
  24465         0,
  24466         2,
  24467         soc_QSPI_MSPI_RXRAM12_BCM88690_B0r_fields,
  24468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24469         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24470         -1,
  24471         -1,
  24472     },
  24473 #endif /* chips */
  24474 
  24475 #if defined(BCM_88790_A0)
  24476     { /* SOC_REG_INT_QSPI_MSPI_RXRAM12_BCM88790_A0r */
  24477         soc_block_list[61],
  24478         soc_iprocreg,
  24479         1,
  24480         0,
  24481         0x180212f0,
  24482         0,
  24483         0,
  24484         2,
  24485         soc_QSPI_MSPI_RXRAM12_BCM88790_A0r_fields,
  24486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24487         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24488         -1,
  24489         -1,
  24490     },
  24491 #endif /* chips */
  24492 
  24493 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24494     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24495     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24496     defined(BCM_56260_B0)
  24497     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM53400_A0r */
  24498         soc_block_list[61],
  24499         soc_iprocreg,
  24500         1,
  24501         0,
  24502         0x180472f4,
  24503         0,
  24504         0,
  24505         2,
  24506         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24508         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24509         -1,
  24510         -1,
  24511     },
  24512 #endif /* chips */
  24513 
  24514 #if defined(BCM_56370_A0)
  24515     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM56370_A0r */
  24516         soc_block_list[61],
  24517         soc_iprocreg,
  24518         1,
  24519         0,
  24520         0x150002f4,
  24521         0,
  24522         0,
  24523         2,
  24524         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24526         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24527         -1,
  24528         -1,
  24529         3,
  24530     },
  24531 #endif /* chips */
  24532 
  24533 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24534     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24535     defined(BCM_56450_B1)
  24536     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM56450_A0r */
  24537         soc_block_list[61],
  24538         soc_iprocreg,
  24539         1,
  24540         0,
  24541         0x180272f4,
  24542         0,
  24543         0,
  24544         2,
  24545         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  24546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24547         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24548         -1,
  24549         -1,
  24550     },
  24551 #endif /* chips */
  24552 
  24553 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  24554     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  24555     defined(BCM_56670_B0)
  24556     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM56560_A0r */
  24557         soc_block_list[61],
  24558         soc_iprocreg,
  24559         1,
  24560         0,
  24561         0x180212f4,
  24562         0,
  24563         0,
  24564         2,
  24565         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24567         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24568         -1,
  24569         -1,
  24570     },
  24571 #endif /* chips */
  24572 
  24573 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  24574     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  24575     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  24576     defined(BCM_56980_B0)
  24577     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM56960_A0r */
  24578         soc_block_list[61],
  24579         soc_iprocreg,
  24580         1,
  24581         0,
  24582         0x180212f4,
  24583         0,
  24584         0,
  24585         2,
  24586         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24588         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24589         -1,
  24590         -1,
  24591         3,
  24592     },
  24593 #endif /* chips */
  24594 
  24595 #if defined(BCM_88270_A0)
  24596     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM88270_A0r */
  24597         soc_block_list[61],
  24598         soc_iprocreg,
  24599         1,
  24600         0,
  24601         0x180212f4,
  24602         0,
  24603         0,
  24604         2,
  24605         soc_QSPI_MSPI_RXRAM13_BCM88270_A0r_fields,
  24606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24607         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24608         -1,
  24609         -1,
  24610     },
  24611 #endif /* chips */
  24612 
  24613 #if defined(BCM_88375_A0)
  24614     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM88375_A0r */
  24615         soc_block_list[61],
  24616         soc_iprocreg,
  24617         1,
  24618         0,
  24619         0x180212f4,
  24620         0,
  24621         0,
  24622         2,
  24623         soc_QSPI_MSPI_RXRAM13_BCM88375_A0r_fields,
  24624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24625         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24626         -1,
  24627         -1,
  24628     },
  24629 #endif /* chips */
  24630 
  24631 #if defined(BCM_88375_B0)
  24632     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM88375_B0r */
  24633         soc_block_list[61],
  24634         soc_iprocreg,
  24635         1,
  24636         0,
  24637         0x180212f4,
  24638         0,
  24639         0,
  24640         2,
  24641         soc_QSPI_MSPI_RXRAM13_BCM88375_B0r_fields,
  24642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24643         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24644         -1,
  24645         -1,
  24646     },
  24647 #endif /* chips */
  24648 
  24649 #if defined(BCM_88470_A0)
  24650     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM88470_A0r */
  24651         soc_block_list[61],
  24652         soc_iprocreg,
  24653         1,
  24654         0,
  24655         0x180212f4,
  24656         0,
  24657         0,
  24658         2,
  24659         soc_QSPI_MSPI_RXRAM13_BCM88470_A0r_fields,
  24660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24661         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24662         -1,
  24663         -1,
  24664     },
  24665 #endif /* chips */
  24666 
  24667 #if defined(BCM_88470_B0)
  24668     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM88470_B0r */
  24669         soc_block_list[61],
  24670         soc_iprocreg,
  24671         1,
  24672         0,
  24673         0x180212f4,
  24674         0,
  24675         0,
  24676         2,
  24677         soc_QSPI_MSPI_RXRAM13_BCM88470_B0r_fields,
  24678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24680         -1,
  24681         -1,
  24682     },
  24683 #endif /* chips */
  24684 
  24685 #if defined(BCM_88675_B0)
  24686     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM88675_B0r */
  24687         soc_block_list[61],
  24688         soc_iprocreg,
  24689         1,
  24690         0,
  24691         0x180212f4,
  24692         0,
  24693         0,
  24694         2,
  24695         soc_QSPI_MSPI_RXRAM13_BCM88675_B0r_fields,
  24696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24698         -1,
  24699         -1,
  24700     },
  24701 #endif /* chips */
  24702 
  24703 #if defined(BCM_88680_A0)
  24704     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM88680_A0r */
  24705         soc_block_list[61],
  24706         soc_iprocreg,
  24707         1,
  24708         0,
  24709         0x180212f4,
  24710         0,
  24711         0,
  24712         2,
  24713         soc_QSPI_MSPI_RXRAM13_BCM88680_A0r_fields,
  24714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24715         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24716         -1,
  24717         -1,
  24718     },
  24719 #endif /* chips */
  24720 
  24721 #if defined(BCM_88690_A0)
  24722     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM88690_A0r */
  24723         soc_block_list[61],
  24724         soc_iprocreg,
  24725         1,
  24726         0,
  24727         0x180212f4,
  24728         0,
  24729         0,
  24730         2,
  24731         soc_QSPI_MSPI_RXRAM13_BCM88690_A0r_fields,
  24732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24733         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24734         -1,
  24735         -1,
  24736     },
  24737 #endif /* chips */
  24738 
  24739 #if defined(BCM_88690_B0)
  24740     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM88690_B0r */
  24741         soc_block_list[61],
  24742         soc_iprocreg,
  24743         1,
  24744         0,
  24745         0x180212f4,
  24746         0,
  24747         0,
  24748         2,
  24749         soc_QSPI_MSPI_RXRAM13_BCM88690_B0r_fields,
  24750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24751         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24752         -1,
  24753         -1,
  24754     },
  24755 #endif /* chips */
  24756 
  24757 #if defined(BCM_88790_A0)
  24758     { /* SOC_REG_INT_QSPI_MSPI_RXRAM13_BCM88790_A0r */
  24759         soc_block_list[61],
  24760         soc_iprocreg,
  24761         1,
  24762         0,
  24763         0x180212f4,
  24764         0,
  24765         0,
  24766         2,
  24767         soc_QSPI_MSPI_RXRAM13_BCM88790_A0r_fields,
  24768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24769         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24770         -1,
  24771         -1,
  24772     },
  24773 #endif /* chips */
  24774 
  24775 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  24776     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  24777     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  24778     defined(BCM_56260_B0)
  24779     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM53400_A0r */
  24780         soc_block_list[61],
  24781         soc_iprocreg,
  24782         1,
  24783         0,
  24784         0x180472f8,
  24785         0,
  24786         0,
  24787         2,
  24788         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24790         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24791         -1,
  24792         -1,
  24793     },
  24794 #endif /* chips */
  24795 
  24796 #if defined(BCM_56370_A0)
  24797     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM56370_A0r */
  24798         soc_block_list[61],
  24799         soc_iprocreg,
  24800         1,
  24801         0,
  24802         0x150002f8,
  24803         0,
  24804         0,
  24805         2,
  24806         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24808         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24809         -1,
  24810         -1,
  24811         3,
  24812     },
  24813 #endif /* chips */
  24814 
  24815 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  24816     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  24817     defined(BCM_56450_B1)
  24818     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM56450_A0r */
  24819         soc_block_list[61],
  24820         soc_iprocreg,
  24821         1,
  24822         0,
  24823         0x180272f8,
  24824         0,
  24825         0,
  24826         2,
  24827         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  24828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24829         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24830         -1,
  24831         -1,
  24832     },
  24833 #endif /* chips */
  24834 
  24835 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  24836     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  24837     defined(BCM_56670_B0)
  24838     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM56560_A0r */
  24839         soc_block_list[61],
  24840         soc_iprocreg,
  24841         1,
  24842         0,
  24843         0x180212f8,
  24844         0,
  24845         0,
  24846         2,
  24847         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24849         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24850         -1,
  24851         -1,
  24852     },
  24853 #endif /* chips */
  24854 
  24855 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  24856     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  24857     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  24858     defined(BCM_56980_B0)
  24859     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM56960_A0r */
  24860         soc_block_list[61],
  24861         soc_iprocreg,
  24862         1,
  24863         0,
  24864         0x180212f8,
  24865         0,
  24866         0,
  24867         2,
  24868         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  24869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24870         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24871         -1,
  24872         -1,
  24873         3,
  24874     },
  24875 #endif /* chips */
  24876 
  24877 #if defined(BCM_88270_A0)
  24878     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM88270_A0r */
  24879         soc_block_list[61],
  24880         soc_iprocreg,
  24881         1,
  24882         0,
  24883         0x180212f8,
  24884         0,
  24885         0,
  24886         2,
  24887         soc_QSPI_MSPI_RXRAM14_BCM88270_A0r_fields,
  24888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24889         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24890         -1,
  24891         -1,
  24892     },
  24893 #endif /* chips */
  24894 
  24895 #if defined(BCM_88375_A0)
  24896     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM88375_A0r */
  24897         soc_block_list[61],
  24898         soc_iprocreg,
  24899         1,
  24900         0,
  24901         0x180212f8,
  24902         0,
  24903         0,
  24904         2,
  24905         soc_QSPI_MSPI_RXRAM14_BCM88375_A0r_fields,
  24906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24907         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24908         -1,
  24909         -1,
  24910     },
  24911 #endif /* chips */
  24912 
  24913 #if defined(BCM_88375_B0)
  24914     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM88375_B0r */
  24915         soc_block_list[61],
  24916         soc_iprocreg,
  24917         1,
  24918         0,
  24919         0x180212f8,
  24920         0,
  24921         0,
  24922         2,
  24923         soc_QSPI_MSPI_RXRAM14_BCM88375_B0r_fields,
  24924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24925         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24926         -1,
  24927         -1,
  24928     },
  24929 #endif /* chips */
  24930 
  24931 #if defined(BCM_88470_A0)
  24932     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM88470_A0r */
  24933         soc_block_list[61],
  24934         soc_iprocreg,
  24935         1,
  24936         0,
  24937         0x180212f8,
  24938         0,
  24939         0,
  24940         2,
  24941         soc_QSPI_MSPI_RXRAM14_BCM88470_A0r_fields,
  24942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24943         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24944         -1,
  24945         -1,
  24946     },
  24947 #endif /* chips */
  24948 
  24949 #if defined(BCM_88470_B0)
  24950     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM88470_B0r */
  24951         soc_block_list[61],
  24952         soc_iprocreg,
  24953         1,
  24954         0,
  24955         0x180212f8,
  24956         0,
  24957         0,
  24958         2,
  24959         soc_QSPI_MSPI_RXRAM14_BCM88470_B0r_fields,
  24960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24961         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24962         -1,
  24963         -1,
  24964     },
  24965 #endif /* chips */
  24966 
  24967 #if defined(BCM_88675_B0)
  24968     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM88675_B0r */
  24969         soc_block_list[61],
  24970         soc_iprocreg,
  24971         1,
  24972         0,
  24973         0x180212f8,
  24974         0,
  24975         0,
  24976         2,
  24977         soc_QSPI_MSPI_RXRAM14_BCM88675_B0r_fields,
  24978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24979         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24980         -1,
  24981         -1,
  24982     },
  24983 #endif /* chips */
  24984 
  24985 #if defined(BCM_88680_A0)
  24986     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM88680_A0r */
  24987         soc_block_list[61],
  24988         soc_iprocreg,
  24989         1,
  24990         0,
  24991         0x180212f8,
  24992         0,
  24993         0,
  24994         2,
  24995         soc_QSPI_MSPI_RXRAM14_BCM88680_A0r_fields,
  24996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24997         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24998         -1,
  24999         -1,
  25000     },
  25001 #endif /* chips */
  25002 
  25003 #if defined(BCM_88690_A0)
  25004     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM88690_A0r */
  25005         soc_block_list[61],
  25006         soc_iprocreg,
  25007         1,
  25008         0,
  25009         0x180212f8,
  25010         0,
  25011         0,
  25012         2,
  25013         soc_QSPI_MSPI_RXRAM14_BCM88690_A0r_fields,
  25014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25016         -1,
  25017         -1,
  25018     },
  25019 #endif /* chips */
  25020 
  25021 #if defined(BCM_88690_B0)
  25022     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM88690_B0r */
  25023         soc_block_list[61],
  25024         soc_iprocreg,
  25025         1,
  25026         0,
  25027         0x180212f8,
  25028         0,
  25029         0,
  25030         2,
  25031         soc_QSPI_MSPI_RXRAM14_BCM88690_B0r_fields,
  25032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25034         -1,
  25035         -1,
  25036     },
  25037 #endif /* chips */
  25038 
  25039 #if defined(BCM_88790_A0)
  25040     { /* SOC_REG_INT_QSPI_MSPI_RXRAM14_BCM88790_A0r */
  25041         soc_block_list[61],
  25042         soc_iprocreg,
  25043         1,
  25044         0,
  25045         0x180212f8,
  25046         0,
  25047         0,
  25048         2,
  25049         soc_QSPI_MSPI_RXRAM14_BCM88790_A0r_fields,
  25050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25051         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25052         -1,
  25053         -1,
  25054     },
  25055 #endif /* chips */
  25056 
  25057 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25058     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25059     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25060     defined(BCM_56260_B0)
  25061     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM53400_A0r */
  25062         soc_block_list[61],
  25063         soc_iprocreg,
  25064         1,
  25065         0,
  25066         0x180472fc,
  25067         0,
  25068         0,
  25069         2,
  25070         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25072         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25073         -1,
  25074         -1,
  25075     },
  25076 #endif /* chips */
  25077 
  25078 #if defined(BCM_56370_A0)
  25079     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM56370_A0r */
  25080         soc_block_list[61],
  25081         soc_iprocreg,
  25082         1,
  25083         0,
  25084         0x150002fc,
  25085         0,
  25086         0,
  25087         2,
  25088         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25090         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25091         -1,
  25092         -1,
  25093         3,
  25094     },
  25095 #endif /* chips */
  25096 
  25097 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  25098     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  25099     defined(BCM_56450_B1)
  25100     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM56450_A0r */
  25101         soc_block_list[61],
  25102         soc_iprocreg,
  25103         1,
  25104         0,
  25105         0x180272fc,
  25106         0,
  25107         0,
  25108         2,
  25109         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  25110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25111         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25112         -1,
  25113         -1,
  25114     },
  25115 #endif /* chips */
  25116 
  25117 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  25118     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  25119     defined(BCM_56670_B0)
  25120     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM56560_A0r */
  25121         soc_block_list[61],
  25122         soc_iprocreg,
  25123         1,
  25124         0,
  25125         0x180212fc,
  25126         0,
  25127         0,
  25128         2,
  25129         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25132         -1,
  25133         -1,
  25134     },
  25135 #endif /* chips */
  25136 
  25137 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  25138     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  25139     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  25140     defined(BCM_56980_B0)
  25141     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM56960_A0r */
  25142         soc_block_list[61],
  25143         soc_iprocreg,
  25144         1,
  25145         0,
  25146         0x180212fc,
  25147         0,
  25148         0,
  25149         2,
  25150         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25152         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25153         -1,
  25154         -1,
  25155         3,
  25156     },
  25157 #endif /* chips */
  25158 
  25159 #if defined(BCM_88270_A0)
  25160     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM88270_A0r */
  25161         soc_block_list[61],
  25162         soc_iprocreg,
  25163         1,
  25164         0,
  25165         0x180212fc,
  25166         0,
  25167         0,
  25168         2,
  25169         soc_QSPI_MSPI_RXRAM15_BCM88270_A0r_fields,
  25170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25171         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25172         -1,
  25173         -1,
  25174     },
  25175 #endif /* chips */
  25176 
  25177 #if defined(BCM_88375_A0)
  25178     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM88375_A0r */
  25179         soc_block_list[61],
  25180         soc_iprocreg,
  25181         1,
  25182         0,
  25183         0x180212fc,
  25184         0,
  25185         0,
  25186         2,
  25187         soc_QSPI_MSPI_RXRAM15_BCM88375_A0r_fields,
  25188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25189         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25190         -1,
  25191         -1,
  25192     },
  25193 #endif /* chips */
  25194 
  25195 #if defined(BCM_88375_B0)
  25196     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM88375_B0r */
  25197         soc_block_list[61],
  25198         soc_iprocreg,
  25199         1,
  25200         0,
  25201         0x180212fc,
  25202         0,
  25203         0,
  25204         2,
  25205         soc_QSPI_MSPI_RXRAM15_BCM88375_B0r_fields,
  25206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25207         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25208         -1,
  25209         -1,
  25210     },
  25211 #endif /* chips */
  25212 
  25213 #if defined(BCM_88470_A0)
  25214     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM88470_A0r */
  25215         soc_block_list[61],
  25216         soc_iprocreg,
  25217         1,
  25218         0,
  25219         0x180212fc,
  25220         0,
  25221         0,
  25222         2,
  25223         soc_QSPI_MSPI_RXRAM15_BCM88470_A0r_fields,
  25224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25225         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25226         -1,
  25227         -1,
  25228     },
  25229 #endif /* chips */
  25230 
  25231 #if defined(BCM_88470_B0)
  25232     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM88470_B0r */
  25233         soc_block_list[61],
  25234         soc_iprocreg,
  25235         1,
  25236         0,
  25237         0x180212fc,
  25238         0,
  25239         0,
  25240         2,
  25241         soc_QSPI_MSPI_RXRAM15_BCM88470_B0r_fields,
  25242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25243         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25244         -1,
  25245         -1,
  25246     },
  25247 #endif /* chips */
  25248 
  25249 #if defined(BCM_88675_B0)
  25250     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM88675_B0r */
  25251         soc_block_list[61],
  25252         soc_iprocreg,
  25253         1,
  25254         0,
  25255         0x180212fc,
  25256         0,
  25257         0,
  25258         2,
  25259         soc_QSPI_MSPI_RXRAM15_BCM88675_B0r_fields,
  25260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25261         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25262         -1,
  25263         -1,
  25264     },
  25265 #endif /* chips */
  25266 
  25267 #if defined(BCM_88680_A0)
  25268     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM88680_A0r */
  25269         soc_block_list[61],
  25270         soc_iprocreg,
  25271         1,
  25272         0,
  25273         0x180212fc,
  25274         0,
  25275         0,
  25276         2,
  25277         soc_QSPI_MSPI_RXRAM15_BCM88680_A0r_fields,
  25278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25279         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25280         -1,
  25281         -1,
  25282     },
  25283 #endif /* chips */
  25284 
  25285 #if defined(BCM_88690_A0)
  25286     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM88690_A0r */
  25287         soc_block_list[61],
  25288         soc_iprocreg,
  25289         1,
  25290         0,
  25291         0x180212fc,
  25292         0,
  25293         0,
  25294         2,
  25295         soc_QSPI_MSPI_RXRAM15_BCM88690_A0r_fields,
  25296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25298         -1,
  25299         -1,
  25300     },
  25301 #endif /* chips */
  25302 
  25303 #if defined(BCM_88690_B0)
  25304     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM88690_B0r */
  25305         soc_block_list[61],
  25306         soc_iprocreg,
  25307         1,
  25308         0,
  25309         0x180212fc,
  25310         0,
  25311         0,
  25312         2,
  25313         soc_QSPI_MSPI_RXRAM15_BCM88690_B0r_fields,
  25314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25315         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25316         -1,
  25317         -1,
  25318     },
  25319 #endif /* chips */
  25320 
  25321 #if defined(BCM_88790_A0)
  25322     { /* SOC_REG_INT_QSPI_MSPI_RXRAM15_BCM88790_A0r */
  25323         soc_block_list[61],
  25324         soc_iprocreg,
  25325         1,
  25326         0,
  25327         0x180212fc,
  25328         0,
  25329         0,
  25330         2,
  25331         soc_QSPI_MSPI_RXRAM15_BCM88790_A0r_fields,
  25332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25333         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25334         -1,
  25335         -1,
  25336     },
  25337 #endif /* chips */
  25338 
  25339 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25340     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25341     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25342     defined(BCM_56260_B0)
  25343     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM53400_A0r */
  25344         soc_block_list[61],
  25345         soc_iprocreg,
  25346         1,
  25347         0,
  25348         0x18047300,
  25349         0,
  25350         0,
  25351         2,
  25352         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25354         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25355         -1,
  25356         -1,
  25357     },
  25358 #endif /* chips */
  25359 
  25360 #if defined(BCM_56370_A0)
  25361     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM56370_A0r */
  25362         soc_block_list[61],
  25363         soc_iprocreg,
  25364         1,
  25365         0,
  25366         0x15000300,
  25367         0,
  25368         0,
  25369         2,
  25370         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25372         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25373         -1,
  25374         -1,
  25375         3,
  25376     },
  25377 #endif /* chips */
  25378 
  25379 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  25380     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  25381     defined(BCM_56450_B1)
  25382     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM56450_A0r */
  25383         soc_block_list[61],
  25384         soc_iprocreg,
  25385         1,
  25386         0,
  25387         0x18027300,
  25388         0,
  25389         0,
  25390         2,
  25391         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  25392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25393         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25394         -1,
  25395         -1,
  25396     },
  25397 #endif /* chips */
  25398 
  25399 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  25400     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  25401     defined(BCM_56670_B0)
  25402     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM56560_A0r */
  25403         soc_block_list[61],
  25404         soc_iprocreg,
  25405         1,
  25406         0,
  25407         0x18021300,
  25408         0,
  25409         0,
  25410         2,
  25411         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25413         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25414         -1,
  25415         -1,
  25416     },
  25417 #endif /* chips */
  25418 
  25419 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  25420     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  25421     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  25422     defined(BCM_56980_B0)
  25423     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM56960_A0r */
  25424         soc_block_list[61],
  25425         soc_iprocreg,
  25426         1,
  25427         0,
  25428         0x18021300,
  25429         0,
  25430         0,
  25431         2,
  25432         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25434         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25435         -1,
  25436         -1,
  25437         3,
  25438     },
  25439 #endif /* chips */
  25440 
  25441 #if defined(BCM_88270_A0)
  25442     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM88270_A0r */
  25443         soc_block_list[61],
  25444         soc_iprocreg,
  25445         1,
  25446         0,
  25447         0x18021300,
  25448         0,
  25449         0,
  25450         2,
  25451         soc_QSPI_MSPI_RXRAM16_BCM88270_A0r_fields,
  25452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25454         -1,
  25455         -1,
  25456     },
  25457 #endif /* chips */
  25458 
  25459 #if defined(BCM_88375_A0)
  25460     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM88375_A0r */
  25461         soc_block_list[61],
  25462         soc_iprocreg,
  25463         1,
  25464         0,
  25465         0x18021300,
  25466         0,
  25467         0,
  25468         2,
  25469         soc_QSPI_MSPI_RXRAM16_BCM88375_A0r_fields,
  25470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25471         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25472         -1,
  25473         -1,
  25474     },
  25475 #endif /* chips */
  25476 
  25477 #if defined(BCM_88375_B0)
  25478     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM88375_B0r */
  25479         soc_block_list[61],
  25480         soc_iprocreg,
  25481         1,
  25482         0,
  25483         0x18021300,
  25484         0,
  25485         0,
  25486         2,
  25487         soc_QSPI_MSPI_RXRAM16_BCM88375_B0r_fields,
  25488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25490         -1,
  25491         -1,
  25492     },
  25493 #endif /* chips */
  25494 
  25495 #if defined(BCM_88470_A0)
  25496     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM88470_A0r */
  25497         soc_block_list[61],
  25498         soc_iprocreg,
  25499         1,
  25500         0,
  25501         0x18021300,
  25502         0,
  25503         0,
  25504         2,
  25505         soc_QSPI_MSPI_RXRAM16_BCM88470_A0r_fields,
  25506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25507         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25508         -1,
  25509         -1,
  25510     },
  25511 #endif /* chips */
  25512 
  25513 #if defined(BCM_88470_B0)
  25514     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM88470_B0r */
  25515         soc_block_list[61],
  25516         soc_iprocreg,
  25517         1,
  25518         0,
  25519         0x18021300,
  25520         0,
  25521         0,
  25522         2,
  25523         soc_QSPI_MSPI_RXRAM16_BCM88470_B0r_fields,
  25524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25526         -1,
  25527         -1,
  25528     },
  25529 #endif /* chips */
  25530 
  25531 #if defined(BCM_88675_B0)
  25532     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM88675_B0r */
  25533         soc_block_list[61],
  25534         soc_iprocreg,
  25535         1,
  25536         0,
  25537         0x18021300,
  25538         0,
  25539         0,
  25540         2,
  25541         soc_QSPI_MSPI_RXRAM16_BCM88675_B0r_fields,
  25542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25544         -1,
  25545         -1,
  25546     },
  25547 #endif /* chips */
  25548 
  25549 #if defined(BCM_88680_A0)
  25550     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM88680_A0r */
  25551         soc_block_list[61],
  25552         soc_iprocreg,
  25553         1,
  25554         0,
  25555         0x18021300,
  25556         0,
  25557         0,
  25558         2,
  25559         soc_QSPI_MSPI_RXRAM16_BCM88680_A0r_fields,
  25560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25561         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25562         -1,
  25563         -1,
  25564     },
  25565 #endif /* chips */
  25566 
  25567 #if defined(BCM_88690_A0)
  25568     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM88690_A0r */
  25569         soc_block_list[61],
  25570         soc_iprocreg,
  25571         1,
  25572         0,
  25573         0x18021300,
  25574         0,
  25575         0,
  25576         2,
  25577         soc_QSPI_MSPI_RXRAM16_BCM88690_A0r_fields,
  25578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25579         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25580         -1,
  25581         -1,
  25582     },
  25583 #endif /* chips */
  25584 
  25585 #if defined(BCM_88690_B0)
  25586     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM88690_B0r */
  25587         soc_block_list[61],
  25588         soc_iprocreg,
  25589         1,
  25590         0,
  25591         0x18021300,
  25592         0,
  25593         0,
  25594         2,
  25595         soc_QSPI_MSPI_RXRAM16_BCM88690_B0r_fields,
  25596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25597         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25598         -1,
  25599         -1,
  25600     },
  25601 #endif /* chips */
  25602 
  25603 #if defined(BCM_88790_A0)
  25604     { /* SOC_REG_INT_QSPI_MSPI_RXRAM16_BCM88790_A0r */
  25605         soc_block_list[61],
  25606         soc_iprocreg,
  25607         1,
  25608         0,
  25609         0x18021300,
  25610         0,
  25611         0,
  25612         2,
  25613         soc_QSPI_MSPI_RXRAM16_BCM88790_A0r_fields,
  25614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25615         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25616         -1,
  25617         -1,
  25618     },
  25619 #endif /* chips */
  25620 
  25621 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25622     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25623     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25624     defined(BCM_56260_B0)
  25625     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM53400_A0r */
  25626         soc_block_list[61],
  25627         soc_iprocreg,
  25628         1,
  25629         0,
  25630         0x18047304,
  25631         0,
  25632         0,
  25633         2,
  25634         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25636         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25637         -1,
  25638         -1,
  25639     },
  25640 #endif /* chips */
  25641 
  25642 #if defined(BCM_56370_A0)
  25643     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM56370_A0r */
  25644         soc_block_list[61],
  25645         soc_iprocreg,
  25646         1,
  25647         0,
  25648         0x15000304,
  25649         0,
  25650         0,
  25651         2,
  25652         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25654         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25655         -1,
  25656         -1,
  25657         3,
  25658     },
  25659 #endif /* chips */
  25660 
  25661 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  25662     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  25663     defined(BCM_56450_B1)
  25664     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM56450_A0r */
  25665         soc_block_list[61],
  25666         soc_iprocreg,
  25667         1,
  25668         0,
  25669         0x18027304,
  25670         0,
  25671         0,
  25672         2,
  25673         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  25674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25675         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25676         -1,
  25677         -1,
  25678     },
  25679 #endif /* chips */
  25680 
  25681 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  25682     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  25683     defined(BCM_56670_B0)
  25684     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM56560_A0r */
  25685         soc_block_list[61],
  25686         soc_iprocreg,
  25687         1,
  25688         0,
  25689         0x18021304,
  25690         0,
  25691         0,
  25692         2,
  25693         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25695         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25696         -1,
  25697         -1,
  25698     },
  25699 #endif /* chips */
  25700 
  25701 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  25702     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  25703     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  25704     defined(BCM_56980_B0)
  25705     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM56960_A0r */
  25706         soc_block_list[61],
  25707         soc_iprocreg,
  25708         1,
  25709         0,
  25710         0x18021304,
  25711         0,
  25712         0,
  25713         2,
  25714         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25716         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25717         -1,
  25718         -1,
  25719         3,
  25720     },
  25721 #endif /* chips */
  25722 
  25723 #if defined(BCM_88270_A0)
  25724     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM88270_A0r */
  25725         soc_block_list[61],
  25726         soc_iprocreg,
  25727         1,
  25728         0,
  25729         0x18021304,
  25730         0,
  25731         0,
  25732         2,
  25733         soc_QSPI_MSPI_RXRAM17_BCM88270_A0r_fields,
  25734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25736         -1,
  25737         -1,
  25738     },
  25739 #endif /* chips */
  25740 
  25741 #if defined(BCM_88375_A0)
  25742     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM88375_A0r */
  25743         soc_block_list[61],
  25744         soc_iprocreg,
  25745         1,
  25746         0,
  25747         0x18021304,
  25748         0,
  25749         0,
  25750         2,
  25751         soc_QSPI_MSPI_RXRAM17_BCM88375_A0r_fields,
  25752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25753         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25754         -1,
  25755         -1,
  25756     },
  25757 #endif /* chips */
  25758 
  25759 #if defined(BCM_88375_B0)
  25760     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM88375_B0r */
  25761         soc_block_list[61],
  25762         soc_iprocreg,
  25763         1,
  25764         0,
  25765         0x18021304,
  25766         0,
  25767         0,
  25768         2,
  25769         soc_QSPI_MSPI_RXRAM17_BCM88375_B0r_fields,
  25770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25771         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25772         -1,
  25773         -1,
  25774     },
  25775 #endif /* chips */
  25776 
  25777 #if defined(BCM_88470_A0)
  25778     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM88470_A0r */
  25779         soc_block_list[61],
  25780         soc_iprocreg,
  25781         1,
  25782         0,
  25783         0x18021304,
  25784         0,
  25785         0,
  25786         2,
  25787         soc_QSPI_MSPI_RXRAM17_BCM88470_A0r_fields,
  25788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25789         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25790         -1,
  25791         -1,
  25792     },
  25793 #endif /* chips */
  25794 
  25795 #if defined(BCM_88470_B0)
  25796     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM88470_B0r */
  25797         soc_block_list[61],
  25798         soc_iprocreg,
  25799         1,
  25800         0,
  25801         0x18021304,
  25802         0,
  25803         0,
  25804         2,
  25805         soc_QSPI_MSPI_RXRAM17_BCM88470_B0r_fields,
  25806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25807         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25808         -1,
  25809         -1,
  25810     },
  25811 #endif /* chips */
  25812 
  25813 #if defined(BCM_88675_B0)
  25814     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM88675_B0r */
  25815         soc_block_list[61],
  25816         soc_iprocreg,
  25817         1,
  25818         0,
  25819         0x18021304,
  25820         0,
  25821         0,
  25822         2,
  25823         soc_QSPI_MSPI_RXRAM17_BCM88675_B0r_fields,
  25824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25825         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25826         -1,
  25827         -1,
  25828     },
  25829 #endif /* chips */
  25830 
  25831 #if defined(BCM_88680_A0)
  25832     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM88680_A0r */
  25833         soc_block_list[61],
  25834         soc_iprocreg,
  25835         1,
  25836         0,
  25837         0x18021304,
  25838         0,
  25839         0,
  25840         2,
  25841         soc_QSPI_MSPI_RXRAM17_BCM88680_A0r_fields,
  25842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25843         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25844         -1,
  25845         -1,
  25846     },
  25847 #endif /* chips */
  25848 
  25849 #if defined(BCM_88690_A0)
  25850     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM88690_A0r */
  25851         soc_block_list[61],
  25852         soc_iprocreg,
  25853         1,
  25854         0,
  25855         0x18021304,
  25856         0,
  25857         0,
  25858         2,
  25859         soc_QSPI_MSPI_RXRAM17_BCM88690_A0r_fields,
  25860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25861         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25862         -1,
  25863         -1,
  25864     },
  25865 #endif /* chips */
  25866 
  25867 #if defined(BCM_88690_B0)
  25868     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM88690_B0r */
  25869         soc_block_list[61],
  25870         soc_iprocreg,
  25871         1,
  25872         0,
  25873         0x18021304,
  25874         0,
  25875         0,
  25876         2,
  25877         soc_QSPI_MSPI_RXRAM17_BCM88690_B0r_fields,
  25878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25879         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25880         -1,
  25881         -1,
  25882     },
  25883 #endif /* chips */
  25884 
  25885 #if defined(BCM_88790_A0)
  25886     { /* SOC_REG_INT_QSPI_MSPI_RXRAM17_BCM88790_A0r */
  25887         soc_block_list[61],
  25888         soc_iprocreg,
  25889         1,
  25890         0,
  25891         0x18021304,
  25892         0,
  25893         0,
  25894         2,
  25895         soc_QSPI_MSPI_RXRAM17_BCM88790_A0r_fields,
  25896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25898         -1,
  25899         -1,
  25900     },
  25901 #endif /* chips */
  25902 
  25903 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  25904     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  25905     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  25906     defined(BCM_56260_B0)
  25907     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM53400_A0r */
  25908         soc_block_list[61],
  25909         soc_iprocreg,
  25910         1,
  25911         0,
  25912         0x18047308,
  25913         0,
  25914         0,
  25915         2,
  25916         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25918         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25919         -1,
  25920         -1,
  25921     },
  25922 #endif /* chips */
  25923 
  25924 #if defined(BCM_56370_A0)
  25925     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM56370_A0r */
  25926         soc_block_list[61],
  25927         soc_iprocreg,
  25928         1,
  25929         0,
  25930         0x15000308,
  25931         0,
  25932         0,
  25933         2,
  25934         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25935         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25936         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25937         -1,
  25938         -1,
  25939         3,
  25940     },
  25941 #endif /* chips */
  25942 
  25943 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  25944     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  25945     defined(BCM_56450_B1)
  25946     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM56450_A0r */
  25947         soc_block_list[61],
  25948         soc_iprocreg,
  25949         1,
  25950         0,
  25951         0x18027308,
  25952         0,
  25953         0,
  25954         2,
  25955         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  25956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25957         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25958         -1,
  25959         -1,
  25960     },
  25961 #endif /* chips */
  25962 
  25963 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  25964     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  25965     defined(BCM_56670_B0)
  25966     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM56560_A0r */
  25967         soc_block_list[61],
  25968         soc_iprocreg,
  25969         1,
  25970         0,
  25971         0x18021308,
  25972         0,
  25973         0,
  25974         2,
  25975         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25977         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25978         -1,
  25979         -1,
  25980     },
  25981 #endif /* chips */
  25982 
  25983 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  25984     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  25985     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  25986     defined(BCM_56980_B0)
  25987     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM56960_A0r */
  25988         soc_block_list[61],
  25989         soc_iprocreg,
  25990         1,
  25991         0,
  25992         0x18021308,
  25993         0,
  25994         0,
  25995         2,
  25996         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  25997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25998         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25999         -1,
  26000         -1,
  26001         3,
  26002     },
  26003 #endif /* chips */
  26004 
  26005 #if defined(BCM_88270_A0)
  26006     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM88270_A0r */
  26007         soc_block_list[61],
  26008         soc_iprocreg,
  26009         1,
  26010         0,
  26011         0x18021308,
  26012         0,
  26013         0,
  26014         2,
  26015         soc_QSPI_MSPI_RXRAM18_BCM88270_A0r_fields,
  26016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26018         -1,
  26019         -1,
  26020     },
  26021 #endif /* chips */
  26022 
  26023 #if defined(BCM_88375_A0)
  26024     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM88375_A0r */
  26025         soc_block_list[61],
  26026         soc_iprocreg,
  26027         1,
  26028         0,
  26029         0x18021308,
  26030         0,
  26031         0,
  26032         2,
  26033         soc_QSPI_MSPI_RXRAM18_BCM88375_A0r_fields,
  26034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26035         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26036         -1,
  26037         -1,
  26038     },
  26039 #endif /* chips */
  26040 
  26041 #if defined(BCM_88375_B0)
  26042     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM88375_B0r */
  26043         soc_block_list[61],
  26044         soc_iprocreg,
  26045         1,
  26046         0,
  26047         0x18021308,
  26048         0,
  26049         0,
  26050         2,
  26051         soc_QSPI_MSPI_RXRAM18_BCM88375_B0r_fields,
  26052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26053         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26054         -1,
  26055         -1,
  26056     },
  26057 #endif /* chips */
  26058 
  26059 #if defined(BCM_88470_A0)
  26060     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM88470_A0r */
  26061         soc_block_list[61],
  26062         soc_iprocreg,
  26063         1,
  26064         0,
  26065         0x18021308,
  26066         0,
  26067         0,
  26068         2,
  26069         soc_QSPI_MSPI_RXRAM18_BCM88470_A0r_fields,
  26070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26071         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26072         -1,
  26073         -1,
  26074     },
  26075 #endif /* chips */
  26076 
  26077 #if defined(BCM_88470_B0)
  26078     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM88470_B0r */
  26079         soc_block_list[61],
  26080         soc_iprocreg,
  26081         1,
  26082         0,
  26083         0x18021308,
  26084         0,
  26085         0,
  26086         2,
  26087         soc_QSPI_MSPI_RXRAM18_BCM88470_B0r_fields,
  26088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26089         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26090         -1,
  26091         -1,
  26092     },
  26093 #endif /* chips */
  26094 
  26095 #if defined(BCM_88675_B0)
  26096     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM88675_B0r */
  26097         soc_block_list[61],
  26098         soc_iprocreg,
  26099         1,
  26100         0,
  26101         0x18021308,
  26102         0,
  26103         0,
  26104         2,
  26105         soc_QSPI_MSPI_RXRAM18_BCM88675_B0r_fields,
  26106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26107         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26108         -1,
  26109         -1,
  26110     },
  26111 #endif /* chips */
  26112 
  26113 #if defined(BCM_88680_A0)
  26114     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM88680_A0r */
  26115         soc_block_list[61],
  26116         soc_iprocreg,
  26117         1,
  26118         0,
  26119         0x18021308,
  26120         0,
  26121         0,
  26122         2,
  26123         soc_QSPI_MSPI_RXRAM18_BCM88680_A0r_fields,
  26124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26125         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26126         -1,
  26127         -1,
  26128     },
  26129 #endif /* chips */
  26130 
  26131 #if defined(BCM_88690_A0)
  26132     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM88690_A0r */
  26133         soc_block_list[61],
  26134         soc_iprocreg,
  26135         1,
  26136         0,
  26137         0x18021308,
  26138         0,
  26139         0,
  26140         2,
  26141         soc_QSPI_MSPI_RXRAM18_BCM88690_A0r_fields,
  26142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26143         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26144         -1,
  26145         -1,
  26146     },
  26147 #endif /* chips */
  26148 
  26149 #if defined(BCM_88690_B0)
  26150     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM88690_B0r */
  26151         soc_block_list[61],
  26152         soc_iprocreg,
  26153         1,
  26154         0,
  26155         0x18021308,
  26156         0,
  26157         0,
  26158         2,
  26159         soc_QSPI_MSPI_RXRAM18_BCM88690_B0r_fields,
  26160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26161         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26162         -1,
  26163         -1,
  26164     },
  26165 #endif /* chips */
  26166 
  26167 #if defined(BCM_88790_A0)
  26168     { /* SOC_REG_INT_QSPI_MSPI_RXRAM18_BCM88790_A0r */
  26169         soc_block_list[61],
  26170         soc_iprocreg,
  26171         1,
  26172         0,
  26173         0x18021308,
  26174         0,
  26175         0,
  26176         2,
  26177         soc_QSPI_MSPI_RXRAM18_BCM88790_A0r_fields,
  26178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26179         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26180         -1,
  26181         -1,
  26182     },
  26183 #endif /* chips */
  26184 
  26185 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  26186     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  26187     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  26188     defined(BCM_56260_B0)
  26189     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM53400_A0r */
  26190         soc_block_list[61],
  26191         soc_iprocreg,
  26192         1,
  26193         0,
  26194         0x1804730c,
  26195         0,
  26196         0,
  26197         2,
  26198         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26200         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26201         -1,
  26202         -1,
  26203     },
  26204 #endif /* chips */
  26205 
  26206 #if defined(BCM_56370_A0)
  26207     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM56370_A0r */
  26208         soc_block_list[61],
  26209         soc_iprocreg,
  26210         1,
  26211         0,
  26212         0x1500030c,
  26213         0,
  26214         0,
  26215         2,
  26216         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26218         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26219         -1,
  26220         -1,
  26221         3,
  26222     },
  26223 #endif /* chips */
  26224 
  26225 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  26226     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  26227     defined(BCM_56450_B1)
  26228     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM56450_A0r */
  26229         soc_block_list[61],
  26230         soc_iprocreg,
  26231         1,
  26232         0,
  26233         0x1802730c,
  26234         0,
  26235         0,
  26236         2,
  26237         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  26238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26239         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26240         -1,
  26241         -1,
  26242     },
  26243 #endif /* chips */
  26244 
  26245 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  26246     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  26247     defined(BCM_56670_B0)
  26248     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM56560_A0r */
  26249         soc_block_list[61],
  26250         soc_iprocreg,
  26251         1,
  26252         0,
  26253         0x1802130c,
  26254         0,
  26255         0,
  26256         2,
  26257         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26259         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26260         -1,
  26261         -1,
  26262     },
  26263 #endif /* chips */
  26264 
  26265 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  26266     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  26267     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  26268     defined(BCM_56980_B0)
  26269     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM56960_A0r */
  26270         soc_block_list[61],
  26271         soc_iprocreg,
  26272         1,
  26273         0,
  26274         0x1802130c,
  26275         0,
  26276         0,
  26277         2,
  26278         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26280         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26281         -1,
  26282         -1,
  26283         3,
  26284     },
  26285 #endif /* chips */
  26286 
  26287 #if defined(BCM_88270_A0)
  26288     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM88270_A0r */
  26289         soc_block_list[61],
  26290         soc_iprocreg,
  26291         1,
  26292         0,
  26293         0x1802130c,
  26294         0,
  26295         0,
  26296         2,
  26297         soc_QSPI_MSPI_RXRAM19_BCM88270_A0r_fields,
  26298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26300         -1,
  26301         -1,
  26302     },
  26303 #endif /* chips */
  26304 
  26305 #if defined(BCM_88375_A0)
  26306     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM88375_A0r */
  26307         soc_block_list[61],
  26308         soc_iprocreg,
  26309         1,
  26310         0,
  26311         0x1802130c,
  26312         0,
  26313         0,
  26314         2,
  26315         soc_QSPI_MSPI_RXRAM19_BCM88375_A0r_fields,
  26316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26318         -1,
  26319         -1,
  26320     },
  26321 #endif /* chips */
  26322 
  26323 #if defined(BCM_88375_B0)
  26324     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM88375_B0r */
  26325         soc_block_list[61],
  26326         soc_iprocreg,
  26327         1,
  26328         0,
  26329         0x1802130c,
  26330         0,
  26331         0,
  26332         2,
  26333         soc_QSPI_MSPI_RXRAM19_BCM88375_B0r_fields,
  26334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26335         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26336         -1,
  26337         -1,
  26338     },
  26339 #endif /* chips */
  26340 
  26341 #if defined(BCM_88470_A0)
  26342     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM88470_A0r */
  26343         soc_block_list[61],
  26344         soc_iprocreg,
  26345         1,
  26346         0,
  26347         0x1802130c,
  26348         0,
  26349         0,
  26350         2,
  26351         soc_QSPI_MSPI_RXRAM19_BCM88470_A0r_fields,
  26352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26353         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26354         -1,
  26355         -1,
  26356     },
  26357 #endif /* chips */
  26358 
  26359 #if defined(BCM_88470_B0)
  26360     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM88470_B0r */
  26361         soc_block_list[61],
  26362         soc_iprocreg,
  26363         1,
  26364         0,
  26365         0x1802130c,
  26366         0,
  26367         0,
  26368         2,
  26369         soc_QSPI_MSPI_RXRAM19_BCM88470_B0r_fields,
  26370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26371         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26372         -1,
  26373         -1,
  26374     },
  26375 #endif /* chips */
  26376 
  26377 #if defined(BCM_88675_B0)
  26378     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM88675_B0r */
  26379         soc_block_list[61],
  26380         soc_iprocreg,
  26381         1,
  26382         0,
  26383         0x1802130c,
  26384         0,
  26385         0,
  26386         2,
  26387         soc_QSPI_MSPI_RXRAM19_BCM88675_B0r_fields,
  26388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26389         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26390         -1,
  26391         -1,
  26392     },
  26393 #endif /* chips */
  26394 
  26395 #if defined(BCM_88680_A0)
  26396     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM88680_A0r */
  26397         soc_block_list[61],
  26398         soc_iprocreg,
  26399         1,
  26400         0,
  26401         0x1802130c,
  26402         0,
  26403         0,
  26404         2,
  26405         soc_QSPI_MSPI_RXRAM19_BCM88680_A0r_fields,
  26406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26407         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26408         -1,
  26409         -1,
  26410     },
  26411 #endif /* chips */
  26412 
  26413 #if defined(BCM_88690_A0)
  26414     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM88690_A0r */
  26415         soc_block_list[61],
  26416         soc_iprocreg,
  26417         1,
  26418         0,
  26419         0x1802130c,
  26420         0,
  26421         0,
  26422         2,
  26423         soc_QSPI_MSPI_RXRAM19_BCM88690_A0r_fields,
  26424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26425         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26426         -1,
  26427         -1,
  26428     },
  26429 #endif /* chips */
  26430 
  26431 #if defined(BCM_88690_B0)
  26432     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM88690_B0r */
  26433         soc_block_list[61],
  26434         soc_iprocreg,
  26435         1,
  26436         0,
  26437         0x1802130c,
  26438         0,
  26439         0,
  26440         2,
  26441         soc_QSPI_MSPI_RXRAM19_BCM88690_B0r_fields,
  26442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26444         -1,
  26445         -1,
  26446     },
  26447 #endif /* chips */
  26448 
  26449 #if defined(BCM_88790_A0)
  26450     { /* SOC_REG_INT_QSPI_MSPI_RXRAM19_BCM88790_A0r */
  26451         soc_block_list[61],
  26452         soc_iprocreg,
  26453         1,
  26454         0,
  26455         0x1802130c,
  26456         0,
  26457         0,
  26458         2,
  26459         soc_QSPI_MSPI_RXRAM19_BCM88790_A0r_fields,
  26460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26462         -1,
  26463         -1,
  26464     },
  26465 #endif /* chips */
  26466 
  26467 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  26468     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  26469     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  26470     defined(BCM_56260_B0)
  26471     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM53400_A0r */
  26472         soc_block_list[61],
  26473         soc_iprocreg,
  26474         1,
  26475         0,
  26476         0x18047310,
  26477         0,
  26478         0,
  26479         2,
  26480         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26482         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26483         -1,
  26484         -1,
  26485     },
  26486 #endif /* chips */
  26487 
  26488 #if defined(BCM_56370_A0)
  26489     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM56370_A0r */
  26490         soc_block_list[61],
  26491         soc_iprocreg,
  26492         1,
  26493         0,
  26494         0x15000310,
  26495         0,
  26496         0,
  26497         2,
  26498         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26500         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26501         -1,
  26502         -1,
  26503         3,
  26504     },
  26505 #endif /* chips */
  26506 
  26507 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  26508     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  26509     defined(BCM_56450_B1)
  26510     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM56450_A0r */
  26511         soc_block_list[61],
  26512         soc_iprocreg,
  26513         1,
  26514         0,
  26515         0x18027310,
  26516         0,
  26517         0,
  26518         2,
  26519         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  26520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26521         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26522         -1,
  26523         -1,
  26524     },
  26525 #endif /* chips */
  26526 
  26527 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  26528     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  26529     defined(BCM_56670_B0)
  26530     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM56560_A0r */
  26531         soc_block_list[61],
  26532         soc_iprocreg,
  26533         1,
  26534         0,
  26535         0x18021310,
  26536         0,
  26537         0,
  26538         2,
  26539         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26542         -1,
  26543         -1,
  26544     },
  26545 #endif /* chips */
  26546 
  26547 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  26548     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  26549     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  26550     defined(BCM_56980_B0)
  26551     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM56960_A0r */
  26552         soc_block_list[61],
  26553         soc_iprocreg,
  26554         1,
  26555         0,
  26556         0x18021310,
  26557         0,
  26558         0,
  26559         2,
  26560         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26562         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26563         -1,
  26564         -1,
  26565         3,
  26566     },
  26567 #endif /* chips */
  26568 
  26569 #if defined(BCM_88270_A0)
  26570     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM88270_A0r */
  26571         soc_block_list[61],
  26572         soc_iprocreg,
  26573         1,
  26574         0,
  26575         0x18021310,
  26576         0,
  26577         0,
  26578         2,
  26579         soc_QSPI_MSPI_RXRAM20_BCM88270_A0r_fields,
  26580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26581         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26582         -1,
  26583         -1,
  26584     },
  26585 #endif /* chips */
  26586 
  26587 #if defined(BCM_88375_A0)
  26588     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM88375_A0r */
  26589         soc_block_list[61],
  26590         soc_iprocreg,
  26591         1,
  26592         0,
  26593         0x18021310,
  26594         0,
  26595         0,
  26596         2,
  26597         soc_QSPI_MSPI_RXRAM20_BCM88375_A0r_fields,
  26598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26599         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26600         -1,
  26601         -1,
  26602     },
  26603 #endif /* chips */
  26604 
  26605 #if defined(BCM_88375_B0)
  26606     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM88375_B0r */
  26607         soc_block_list[61],
  26608         soc_iprocreg,
  26609         1,
  26610         0,
  26611         0x18021310,
  26612         0,
  26613         0,
  26614         2,
  26615         soc_QSPI_MSPI_RXRAM20_BCM88375_B0r_fields,
  26616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26618         -1,
  26619         -1,
  26620     },
  26621 #endif /* chips */
  26622 
  26623 #if defined(BCM_88470_A0)
  26624     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM88470_A0r */
  26625         soc_block_list[61],
  26626         soc_iprocreg,
  26627         1,
  26628         0,
  26629         0x18021310,
  26630         0,
  26631         0,
  26632         2,
  26633         soc_QSPI_MSPI_RXRAM20_BCM88470_A0r_fields,
  26634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26635         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26636         -1,
  26637         -1,
  26638     },
  26639 #endif /* chips */
  26640 
  26641 #if defined(BCM_88470_B0)
  26642     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM88470_B0r */
  26643         soc_block_list[61],
  26644         soc_iprocreg,
  26645         1,
  26646         0,
  26647         0x18021310,
  26648         0,
  26649         0,
  26650         2,
  26651         soc_QSPI_MSPI_RXRAM20_BCM88470_B0r_fields,
  26652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26653         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26654         -1,
  26655         -1,
  26656     },
  26657 #endif /* chips */
  26658 
  26659 #if defined(BCM_88675_B0)
  26660     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM88675_B0r */
  26661         soc_block_list[61],
  26662         soc_iprocreg,
  26663         1,
  26664         0,
  26665         0x18021310,
  26666         0,
  26667         0,
  26668         2,
  26669         soc_QSPI_MSPI_RXRAM20_BCM88675_B0r_fields,
  26670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26671         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26672         -1,
  26673         -1,
  26674     },
  26675 #endif /* chips */
  26676 
  26677 #if defined(BCM_88680_A0)
  26678     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM88680_A0r */
  26679         soc_block_list[61],
  26680         soc_iprocreg,
  26681         1,
  26682         0,
  26683         0x18021310,
  26684         0,
  26685         0,
  26686         2,
  26687         soc_QSPI_MSPI_RXRAM20_BCM88680_A0r_fields,
  26688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26690         -1,
  26691         -1,
  26692     },
  26693 #endif /* chips */
  26694 
  26695 #if defined(BCM_88690_A0)
  26696     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM88690_A0r */
  26697         soc_block_list[61],
  26698         soc_iprocreg,
  26699         1,
  26700         0,
  26701         0x18021310,
  26702         0,
  26703         0,
  26704         2,
  26705         soc_QSPI_MSPI_RXRAM20_BCM88690_A0r_fields,
  26706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26708         -1,
  26709         -1,
  26710     },
  26711 #endif /* chips */
  26712 
  26713 #if defined(BCM_88690_B0)
  26714     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM88690_B0r */
  26715         soc_block_list[61],
  26716         soc_iprocreg,
  26717         1,
  26718         0,
  26719         0x18021310,
  26720         0,
  26721         0,
  26722         2,
  26723         soc_QSPI_MSPI_RXRAM20_BCM88690_B0r_fields,
  26724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26726         -1,
  26727         -1,
  26728     },
  26729 #endif /* chips */
  26730 
  26731 #if defined(BCM_88790_A0)
  26732     { /* SOC_REG_INT_QSPI_MSPI_RXRAM20_BCM88790_A0r */
  26733         soc_block_list[61],
  26734         soc_iprocreg,
  26735         1,
  26736         0,
  26737         0x18021310,
  26738         0,
  26739         0,
  26740         2,
  26741         soc_QSPI_MSPI_RXRAM20_BCM88790_A0r_fields,
  26742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26744         -1,
  26745         -1,
  26746     },
  26747 #endif /* chips */
  26748 
  26749 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  26750     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  26751     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  26752     defined(BCM_56260_B0)
  26753     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM53400_A0r */
  26754         soc_block_list[61],
  26755         soc_iprocreg,
  26756         1,
  26757         0,
  26758         0x18047314,
  26759         0,
  26760         0,
  26761         2,
  26762         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26764         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26765         -1,
  26766         -1,
  26767     },
  26768 #endif /* chips */
  26769 
  26770 #if defined(BCM_56370_A0)
  26771     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM56370_A0r */
  26772         soc_block_list[61],
  26773         soc_iprocreg,
  26774         1,
  26775         0,
  26776         0x15000314,
  26777         0,
  26778         0,
  26779         2,
  26780         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26782         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26783         -1,
  26784         -1,
  26785         3,
  26786     },
  26787 #endif /* chips */
  26788 
  26789 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  26790     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  26791     defined(BCM_56450_B1)
  26792     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM56450_A0r */
  26793         soc_block_list[61],
  26794         soc_iprocreg,
  26795         1,
  26796         0,
  26797         0x18027314,
  26798         0,
  26799         0,
  26800         2,
  26801         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  26802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26803         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26804         -1,
  26805         -1,
  26806     },
  26807 #endif /* chips */
  26808 
  26809 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  26810     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  26811     defined(BCM_56670_B0)
  26812     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM56560_A0r */
  26813         soc_block_list[61],
  26814         soc_iprocreg,
  26815         1,
  26816         0,
  26817         0x18021314,
  26818         0,
  26819         0,
  26820         2,
  26821         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26823         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26824         -1,
  26825         -1,
  26826     },
  26827 #endif /* chips */
  26828 
  26829 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  26830     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  26831     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  26832     defined(BCM_56980_B0)
  26833     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM56960_A0r */
  26834         soc_block_list[61],
  26835         soc_iprocreg,
  26836         1,
  26837         0,
  26838         0x18021314,
  26839         0,
  26840         0,
  26841         2,
  26842         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  26843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26844         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26845         -1,
  26846         -1,
  26847         3,
  26848     },
  26849 #endif /* chips */
  26850 
  26851 #if defined(BCM_88270_A0)
  26852     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM88270_A0r */
  26853         soc_block_list[61],
  26854         soc_iprocreg,
  26855         1,
  26856         0,
  26857         0x18021314,
  26858         0,
  26859         0,
  26860         2,
  26861         soc_QSPI_MSPI_RXRAM21_BCM88270_A0r_fields,
  26862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26863         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26864         -1,
  26865         -1,
  26866     },
  26867 #endif /* chips */
  26868 
  26869 #if defined(BCM_88375_A0)
  26870     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM88375_A0r */
  26871         soc_block_list[61],
  26872         soc_iprocreg,
  26873         1,
  26874         0,
  26875         0x18021314,
  26876         0,
  26877         0,
  26878         2,
  26879         soc_QSPI_MSPI_RXRAM21_BCM88375_A0r_fields,
  26880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26881         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26882         -1,
  26883         -1,
  26884     },
  26885 #endif /* chips */
  26886 
  26887 #if defined(BCM_88375_B0)
  26888     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM88375_B0r */
  26889         soc_block_list[61],
  26890         soc_iprocreg,
  26891         1,
  26892         0,
  26893         0x18021314,
  26894         0,
  26895         0,
  26896         2,
  26897         soc_QSPI_MSPI_RXRAM21_BCM88375_B0r_fields,
  26898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26899         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26900         -1,
  26901         -1,
  26902     },
  26903 #endif /* chips */
  26904 
  26905 #if defined(BCM_88470_A0)
  26906     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM88470_A0r */
  26907         soc_block_list[61],
  26908         soc_iprocreg,
  26909         1,
  26910         0,
  26911         0x18021314,
  26912         0,
  26913         0,
  26914         2,
  26915         soc_QSPI_MSPI_RXRAM21_BCM88470_A0r_fields,
  26916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26917         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26918         -1,
  26919         -1,
  26920     },
  26921 #endif /* chips */
  26922 
  26923 #if defined(BCM_88470_B0)
  26924     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM88470_B0r */
  26925         soc_block_list[61],
  26926         soc_iprocreg,
  26927         1,
  26928         0,
  26929         0x18021314,
  26930         0,
  26931         0,
  26932         2,
  26933         soc_QSPI_MSPI_RXRAM21_BCM88470_B0r_fields,
  26934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26935         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26936         -1,
  26937         -1,
  26938     },
  26939 #endif /* chips */
  26940 
  26941 #if defined(BCM_88675_B0)
  26942     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM88675_B0r */
  26943         soc_block_list[61],
  26944         soc_iprocreg,
  26945         1,
  26946         0,
  26947         0x18021314,
  26948         0,
  26949         0,
  26950         2,
  26951         soc_QSPI_MSPI_RXRAM21_BCM88675_B0r_fields,
  26952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26953         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26954         -1,
  26955         -1,
  26956     },
  26957 #endif /* chips */
  26958 
  26959 #if defined(BCM_88680_A0)
  26960     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM88680_A0r */
  26961         soc_block_list[61],
  26962         soc_iprocreg,
  26963         1,
  26964         0,
  26965         0x18021314,
  26966         0,
  26967         0,
  26968         2,
  26969         soc_QSPI_MSPI_RXRAM21_BCM88680_A0r_fields,
  26970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26971         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26972         -1,
  26973         -1,
  26974     },
  26975 #endif /* chips */
  26976 
  26977 #if defined(BCM_88690_A0)
  26978     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM88690_A0r */
  26979         soc_block_list[61],
  26980         soc_iprocreg,
  26981         1,
  26982         0,
  26983         0x18021314,
  26984         0,
  26985         0,
  26986         2,
  26987         soc_QSPI_MSPI_RXRAM21_BCM88690_A0r_fields,
  26988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26989         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26990         -1,
  26991         -1,
  26992     },
  26993 #endif /* chips */
  26994 
  26995 #if defined(BCM_88690_B0)
  26996     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM88690_B0r */
  26997         soc_block_list[61],
  26998         soc_iprocreg,
  26999         1,
  27000         0,
  27001         0x18021314,
  27002         0,
  27003         0,
  27004         2,
  27005         soc_QSPI_MSPI_RXRAM21_BCM88690_B0r_fields,
  27006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27007         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27008         -1,
  27009         -1,
  27010     },
  27011 #endif /* chips */
  27012 
  27013 #if defined(BCM_88790_A0)
  27014     { /* SOC_REG_INT_QSPI_MSPI_RXRAM21_BCM88790_A0r */
  27015         soc_block_list[61],
  27016         soc_iprocreg,
  27017         1,
  27018         0,
  27019         0x18021314,
  27020         0,
  27021         0,
  27022         2,
  27023         soc_QSPI_MSPI_RXRAM21_BCM88790_A0r_fields,
  27024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27025         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27026         -1,
  27027         -1,
  27028     },
  27029 #endif /* chips */
  27030 
  27031 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27032     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  27033     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  27034     defined(BCM_56260_B0)
  27035     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM53400_A0r */
  27036         soc_block_list[61],
  27037         soc_iprocreg,
  27038         1,
  27039         0,
  27040         0x18047318,
  27041         0,
  27042         0,
  27043         2,
  27044         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27046         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27047         -1,
  27048         -1,
  27049     },
  27050 #endif /* chips */
  27051 
  27052 #if defined(BCM_56370_A0)
  27053     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM56370_A0r */
  27054         soc_block_list[61],
  27055         soc_iprocreg,
  27056         1,
  27057         0,
  27058         0x15000318,
  27059         0,
  27060         0,
  27061         2,
  27062         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27064         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27065         -1,
  27066         -1,
  27067         3,
  27068     },
  27069 #endif /* chips */
  27070 
  27071 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  27072     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27073     defined(BCM_56450_B1)
  27074     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM56450_A0r */
  27075         soc_block_list[61],
  27076         soc_iprocreg,
  27077         1,
  27078         0,
  27079         0x18027318,
  27080         0,
  27081         0,
  27082         2,
  27083         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  27084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27085         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27086         -1,
  27087         -1,
  27088     },
  27089 #endif /* chips */
  27090 
  27091 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  27092     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  27093     defined(BCM_56670_B0)
  27094     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM56560_A0r */
  27095         soc_block_list[61],
  27096         soc_iprocreg,
  27097         1,
  27098         0,
  27099         0x18021318,
  27100         0,
  27101         0,
  27102         2,
  27103         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27105         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27106         -1,
  27107         -1,
  27108     },
  27109 #endif /* chips */
  27110 
  27111 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  27112     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  27113     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  27114     defined(BCM_56980_B0)
  27115     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM56960_A0r */
  27116         soc_block_list[61],
  27117         soc_iprocreg,
  27118         1,
  27119         0,
  27120         0x18021318,
  27121         0,
  27122         0,
  27123         2,
  27124         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27126         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27127         -1,
  27128         -1,
  27129         3,
  27130     },
  27131 #endif /* chips */
  27132 
  27133 #if defined(BCM_88270_A0)
  27134     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM88270_A0r */
  27135         soc_block_list[61],
  27136         soc_iprocreg,
  27137         1,
  27138         0,
  27139         0x18021318,
  27140         0,
  27141         0,
  27142         2,
  27143         soc_QSPI_MSPI_RXRAM22_BCM88270_A0r_fields,
  27144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27145         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27146         -1,
  27147         -1,
  27148     },
  27149 #endif /* chips */
  27150 
  27151 #if defined(BCM_88375_A0)
  27152     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM88375_A0r */
  27153         soc_block_list[61],
  27154         soc_iprocreg,
  27155         1,
  27156         0,
  27157         0x18021318,
  27158         0,
  27159         0,
  27160         2,
  27161         soc_QSPI_MSPI_RXRAM22_BCM88375_A0r_fields,
  27162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27163         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27164         -1,
  27165         -1,
  27166     },
  27167 #endif /* chips */
  27168 
  27169 #if defined(BCM_88375_B0)
  27170     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM88375_B0r */
  27171         soc_block_list[61],
  27172         soc_iprocreg,
  27173         1,
  27174         0,
  27175         0x18021318,
  27176         0,
  27177         0,
  27178         2,
  27179         soc_QSPI_MSPI_RXRAM22_BCM88375_B0r_fields,
  27180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27181         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27182         -1,
  27183         -1,
  27184     },
  27185 #endif /* chips */
  27186 
  27187 #if defined(BCM_88470_A0)
  27188     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM88470_A0r */
  27189         soc_block_list[61],
  27190         soc_iprocreg,
  27191         1,
  27192         0,
  27193         0x18021318,
  27194         0,
  27195         0,
  27196         2,
  27197         soc_QSPI_MSPI_RXRAM22_BCM88470_A0r_fields,
  27198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27199         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27200         -1,
  27201         -1,
  27202     },
  27203 #endif /* chips */
  27204 
  27205 #if defined(BCM_88470_B0)
  27206     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM88470_B0r */
  27207         soc_block_list[61],
  27208         soc_iprocreg,
  27209         1,
  27210         0,
  27211         0x18021318,
  27212         0,
  27213         0,
  27214         2,
  27215         soc_QSPI_MSPI_RXRAM22_BCM88470_B0r_fields,
  27216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27217         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27218         -1,
  27219         -1,
  27220     },
  27221 #endif /* chips */
  27222 
  27223 #if defined(BCM_88675_B0)
  27224     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM88675_B0r */
  27225         soc_block_list[61],
  27226         soc_iprocreg,
  27227         1,
  27228         0,
  27229         0x18021318,
  27230         0,
  27231         0,
  27232         2,
  27233         soc_QSPI_MSPI_RXRAM22_BCM88675_B0r_fields,
  27234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27235         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27236         -1,
  27237         -1,
  27238     },
  27239 #endif /* chips */
  27240 
  27241 #if defined(BCM_88680_A0)
  27242     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM88680_A0r */
  27243         soc_block_list[61],
  27244         soc_iprocreg,
  27245         1,
  27246         0,
  27247         0x18021318,
  27248         0,
  27249         0,
  27250         2,
  27251         soc_QSPI_MSPI_RXRAM22_BCM88680_A0r_fields,
  27252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27253         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27254         -1,
  27255         -1,
  27256     },
  27257 #endif /* chips */
  27258 
  27259 #if defined(BCM_88690_A0)
  27260     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM88690_A0r */
  27261         soc_block_list[61],
  27262         soc_iprocreg,
  27263         1,
  27264         0,
  27265         0x18021318,
  27266         0,
  27267         0,
  27268         2,
  27269         soc_QSPI_MSPI_RXRAM22_BCM88690_A0r_fields,
  27270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27271         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27272         -1,
  27273         -1,
  27274     },
  27275 #endif /* chips */
  27276 
  27277 #if defined(BCM_88690_B0)
  27278     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM88690_B0r */
  27279         soc_block_list[61],
  27280         soc_iprocreg,
  27281         1,
  27282         0,
  27283         0x18021318,
  27284         0,
  27285         0,
  27286         2,
  27287         soc_QSPI_MSPI_RXRAM22_BCM88690_B0r_fields,
  27288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27289         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27290         -1,
  27291         -1,
  27292     },
  27293 #endif /* chips */
  27294 
  27295 #if defined(BCM_88790_A0)
  27296     { /* SOC_REG_INT_QSPI_MSPI_RXRAM22_BCM88790_A0r */
  27297         soc_block_list[61],
  27298         soc_iprocreg,
  27299         1,
  27300         0,
  27301         0x18021318,
  27302         0,
  27303         0,
  27304         2,
  27305         soc_QSPI_MSPI_RXRAM22_BCM88790_A0r_fields,
  27306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27307         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27308         -1,
  27309         -1,
  27310     },
  27311 #endif /* chips */
  27312 
  27313 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27314     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  27315     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  27316     defined(BCM_56260_B0)
  27317     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM53400_A0r */
  27318         soc_block_list[61],
  27319         soc_iprocreg,
  27320         1,
  27321         0,
  27322         0x1804731c,
  27323         0,
  27324         0,
  27325         2,
  27326         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27328         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27329         -1,
  27330         -1,
  27331     },
  27332 #endif /* chips */
  27333 
  27334 #if defined(BCM_56370_A0)
  27335     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM56370_A0r */
  27336         soc_block_list[61],
  27337         soc_iprocreg,
  27338         1,
  27339         0,
  27340         0x1500031c,
  27341         0,
  27342         0,
  27343         2,
  27344         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27346         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27347         -1,
  27348         -1,
  27349         3,
  27350     },
  27351 #endif /* chips */
  27352 
  27353 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  27354     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27355     defined(BCM_56450_B1)
  27356     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM56450_A0r */
  27357         soc_block_list[61],
  27358         soc_iprocreg,
  27359         1,
  27360         0,
  27361         0x1802731c,
  27362         0,
  27363         0,
  27364         2,
  27365         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  27366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27367         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27368         -1,
  27369         -1,
  27370     },
  27371 #endif /* chips */
  27372 
  27373 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  27374     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  27375     defined(BCM_56670_B0)
  27376     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM56560_A0r */
  27377         soc_block_list[61],
  27378         soc_iprocreg,
  27379         1,
  27380         0,
  27381         0x1802131c,
  27382         0,
  27383         0,
  27384         2,
  27385         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27387         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27388         -1,
  27389         -1,
  27390     },
  27391 #endif /* chips */
  27392 
  27393 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  27394     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  27395     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  27396     defined(BCM_56980_B0)
  27397     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM56960_A0r */
  27398         soc_block_list[61],
  27399         soc_iprocreg,
  27400         1,
  27401         0,
  27402         0x1802131c,
  27403         0,
  27404         0,
  27405         2,
  27406         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27408         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27409         -1,
  27410         -1,
  27411         3,
  27412     },
  27413 #endif /* chips */
  27414 
  27415 #if defined(BCM_88270_A0)
  27416     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM88270_A0r */
  27417         soc_block_list[61],
  27418         soc_iprocreg,
  27419         1,
  27420         0,
  27421         0x1802131c,
  27422         0,
  27423         0,
  27424         2,
  27425         soc_QSPI_MSPI_RXRAM23_BCM88270_A0r_fields,
  27426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27428         -1,
  27429         -1,
  27430     },
  27431 #endif /* chips */
  27432 
  27433 #if defined(BCM_88375_A0)
  27434     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM88375_A0r */
  27435         soc_block_list[61],
  27436         soc_iprocreg,
  27437         1,
  27438         0,
  27439         0x1802131c,
  27440         0,
  27441         0,
  27442         2,
  27443         soc_QSPI_MSPI_RXRAM23_BCM88375_A0r_fields,
  27444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27446         -1,
  27447         -1,
  27448     },
  27449 #endif /* chips */
  27450 
  27451 #if defined(BCM_88375_B0)
  27452     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM88375_B0r */
  27453         soc_block_list[61],
  27454         soc_iprocreg,
  27455         1,
  27456         0,
  27457         0x1802131c,
  27458         0,
  27459         0,
  27460         2,
  27461         soc_QSPI_MSPI_RXRAM23_BCM88375_B0r_fields,
  27462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27463         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27464         -1,
  27465         -1,
  27466     },
  27467 #endif /* chips */
  27468 
  27469 #if defined(BCM_88470_A0)
  27470     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM88470_A0r */
  27471         soc_block_list[61],
  27472         soc_iprocreg,
  27473         1,
  27474         0,
  27475         0x1802131c,
  27476         0,
  27477         0,
  27478         2,
  27479         soc_QSPI_MSPI_RXRAM23_BCM88470_A0r_fields,
  27480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27481         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27482         -1,
  27483         -1,
  27484     },
  27485 #endif /* chips */
  27486 
  27487 #if defined(BCM_88470_B0)
  27488     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM88470_B0r */
  27489         soc_block_list[61],
  27490         soc_iprocreg,
  27491         1,
  27492         0,
  27493         0x1802131c,
  27494         0,
  27495         0,
  27496         2,
  27497         soc_QSPI_MSPI_RXRAM23_BCM88470_B0r_fields,
  27498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27499         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27500         -1,
  27501         -1,
  27502     },
  27503 #endif /* chips */
  27504 
  27505 #if defined(BCM_88675_B0)
  27506     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM88675_B0r */
  27507         soc_block_list[61],
  27508         soc_iprocreg,
  27509         1,
  27510         0,
  27511         0x1802131c,
  27512         0,
  27513         0,
  27514         2,
  27515         soc_QSPI_MSPI_RXRAM23_BCM88675_B0r_fields,
  27516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27517         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27518         -1,
  27519         -1,
  27520     },
  27521 #endif /* chips */
  27522 
  27523 #if defined(BCM_88680_A0)
  27524     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM88680_A0r */
  27525         soc_block_list[61],
  27526         soc_iprocreg,
  27527         1,
  27528         0,
  27529         0x1802131c,
  27530         0,
  27531         0,
  27532         2,
  27533         soc_QSPI_MSPI_RXRAM23_BCM88680_A0r_fields,
  27534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27535         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27536         -1,
  27537         -1,
  27538     },
  27539 #endif /* chips */
  27540 
  27541 #if defined(BCM_88690_A0)
  27542     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM88690_A0r */
  27543         soc_block_list[61],
  27544         soc_iprocreg,
  27545         1,
  27546         0,
  27547         0x1802131c,
  27548         0,
  27549         0,
  27550         2,
  27551         soc_QSPI_MSPI_RXRAM23_BCM88690_A0r_fields,
  27552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27553         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27554         -1,
  27555         -1,
  27556     },
  27557 #endif /* chips */
  27558 
  27559 #if defined(BCM_88690_B0)
  27560     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM88690_B0r */
  27561         soc_block_list[61],
  27562         soc_iprocreg,
  27563         1,
  27564         0,
  27565         0x1802131c,
  27566         0,
  27567         0,
  27568         2,
  27569         soc_QSPI_MSPI_RXRAM23_BCM88690_B0r_fields,
  27570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27571         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27572         -1,
  27573         -1,
  27574     },
  27575 #endif /* chips */
  27576 
  27577 #if defined(BCM_88790_A0)
  27578     { /* SOC_REG_INT_QSPI_MSPI_RXRAM23_BCM88790_A0r */
  27579         soc_block_list[61],
  27580         soc_iprocreg,
  27581         1,
  27582         0,
  27583         0x1802131c,
  27584         0,
  27585         0,
  27586         2,
  27587         soc_QSPI_MSPI_RXRAM23_BCM88790_A0r_fields,
  27588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27589         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27590         -1,
  27591         -1,
  27592     },
  27593 #endif /* chips */
  27594 
  27595 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27596     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  27597     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  27598     defined(BCM_56260_B0)
  27599     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM53400_A0r */
  27600         soc_block_list[61],
  27601         soc_iprocreg,
  27602         1,
  27603         0,
  27604         0x18047320,
  27605         0,
  27606         0,
  27607         2,
  27608         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27610         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27611         -1,
  27612         -1,
  27613     },
  27614 #endif /* chips */
  27615 
  27616 #if defined(BCM_56370_A0)
  27617     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM56370_A0r */
  27618         soc_block_list[61],
  27619         soc_iprocreg,
  27620         1,
  27621         0,
  27622         0x15000320,
  27623         0,
  27624         0,
  27625         2,
  27626         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27628         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27629         -1,
  27630         -1,
  27631         3,
  27632     },
  27633 #endif /* chips */
  27634 
  27635 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  27636     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27637     defined(BCM_56450_B1)
  27638     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM56450_A0r */
  27639         soc_block_list[61],
  27640         soc_iprocreg,
  27641         1,
  27642         0,
  27643         0x18027320,
  27644         0,
  27645         0,
  27646         2,
  27647         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  27648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27649         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27650         -1,
  27651         -1,
  27652     },
  27653 #endif /* chips */
  27654 
  27655 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  27656     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  27657     defined(BCM_56670_B0)
  27658     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM56560_A0r */
  27659         soc_block_list[61],
  27660         soc_iprocreg,
  27661         1,
  27662         0,
  27663         0x18021320,
  27664         0,
  27665         0,
  27666         2,
  27667         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27670         -1,
  27671         -1,
  27672     },
  27673 #endif /* chips */
  27674 
  27675 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  27676     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  27677     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  27678     defined(BCM_56980_B0)
  27679     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM56960_A0r */
  27680         soc_block_list[61],
  27681         soc_iprocreg,
  27682         1,
  27683         0,
  27684         0x18021320,
  27685         0,
  27686         0,
  27687         2,
  27688         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27690         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27691         -1,
  27692         -1,
  27693         3,
  27694     },
  27695 #endif /* chips */
  27696 
  27697 #if defined(BCM_88270_A0)
  27698     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM88270_A0r */
  27699         soc_block_list[61],
  27700         soc_iprocreg,
  27701         1,
  27702         0,
  27703         0x18021320,
  27704         0,
  27705         0,
  27706         2,
  27707         soc_QSPI_MSPI_RXRAM24_BCM88270_A0r_fields,
  27708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27709         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27710         -1,
  27711         -1,
  27712     },
  27713 #endif /* chips */
  27714 
  27715 #if defined(BCM_88375_A0)
  27716     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM88375_A0r */
  27717         soc_block_list[61],
  27718         soc_iprocreg,
  27719         1,
  27720         0,
  27721         0x18021320,
  27722         0,
  27723         0,
  27724         2,
  27725         soc_QSPI_MSPI_RXRAM24_BCM88375_A0r_fields,
  27726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27727         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27728         -1,
  27729         -1,
  27730     },
  27731 #endif /* chips */
  27732 
  27733 #if defined(BCM_88375_B0)
  27734     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM88375_B0r */
  27735         soc_block_list[61],
  27736         soc_iprocreg,
  27737         1,
  27738         0,
  27739         0x18021320,
  27740         0,
  27741         0,
  27742         2,
  27743         soc_QSPI_MSPI_RXRAM24_BCM88375_B0r_fields,
  27744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27745         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27746         -1,
  27747         -1,
  27748     },
  27749 #endif /* chips */
  27750 
  27751 #if defined(BCM_88470_A0)
  27752     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM88470_A0r */
  27753         soc_block_list[61],
  27754         soc_iprocreg,
  27755         1,
  27756         0,
  27757         0x18021320,
  27758         0,
  27759         0,
  27760         2,
  27761         soc_QSPI_MSPI_RXRAM24_BCM88470_A0r_fields,
  27762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27763         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27764         -1,
  27765         -1,
  27766     },
  27767 #endif /* chips */
  27768 
  27769 #if defined(BCM_88470_B0)
  27770     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM88470_B0r */
  27771         soc_block_list[61],
  27772         soc_iprocreg,
  27773         1,
  27774         0,
  27775         0x18021320,
  27776         0,
  27777         0,
  27778         2,
  27779         soc_QSPI_MSPI_RXRAM24_BCM88470_B0r_fields,
  27780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27781         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27782         -1,
  27783         -1,
  27784     },
  27785 #endif /* chips */
  27786 
  27787 #if defined(BCM_88675_B0)
  27788     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM88675_B0r */
  27789         soc_block_list[61],
  27790         soc_iprocreg,
  27791         1,
  27792         0,
  27793         0x18021320,
  27794         0,
  27795         0,
  27796         2,
  27797         soc_QSPI_MSPI_RXRAM24_BCM88675_B0r_fields,
  27798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27799         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27800         -1,
  27801         -1,
  27802     },
  27803 #endif /* chips */
  27804 
  27805 #if defined(BCM_88680_A0)
  27806     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM88680_A0r */
  27807         soc_block_list[61],
  27808         soc_iprocreg,
  27809         1,
  27810         0,
  27811         0x18021320,
  27812         0,
  27813         0,
  27814         2,
  27815         soc_QSPI_MSPI_RXRAM24_BCM88680_A0r_fields,
  27816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27817         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27818         -1,
  27819         -1,
  27820     },
  27821 #endif /* chips */
  27822 
  27823 #if defined(BCM_88690_A0)
  27824     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM88690_A0r */
  27825         soc_block_list[61],
  27826         soc_iprocreg,
  27827         1,
  27828         0,
  27829         0x18021320,
  27830         0,
  27831         0,
  27832         2,
  27833         soc_QSPI_MSPI_RXRAM24_BCM88690_A0r_fields,
  27834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27835         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27836         -1,
  27837         -1,
  27838     },
  27839 #endif /* chips */
  27840 
  27841 #if defined(BCM_88690_B0)
  27842     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM88690_B0r */
  27843         soc_block_list[61],
  27844         soc_iprocreg,
  27845         1,
  27846         0,
  27847         0x18021320,
  27848         0,
  27849         0,
  27850         2,
  27851         soc_QSPI_MSPI_RXRAM24_BCM88690_B0r_fields,
  27852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27853         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27854         -1,
  27855         -1,
  27856     },
  27857 #endif /* chips */
  27858 
  27859 #if defined(BCM_88790_A0)
  27860     { /* SOC_REG_INT_QSPI_MSPI_RXRAM24_BCM88790_A0r */
  27861         soc_block_list[61],
  27862         soc_iprocreg,
  27863         1,
  27864         0,
  27865         0x18021320,
  27866         0,
  27867         0,
  27868         2,
  27869         soc_QSPI_MSPI_RXRAM24_BCM88790_A0r_fields,
  27870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27871         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27872         -1,
  27873         -1,
  27874     },
  27875 #endif /* chips */
  27876 
  27877 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  27878     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  27879     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  27880     defined(BCM_56260_B0)
  27881     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM53400_A0r */
  27882         soc_block_list[61],
  27883         soc_iprocreg,
  27884         1,
  27885         0,
  27886         0x18047324,
  27887         0,
  27888         0,
  27889         2,
  27890         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27892         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27893         -1,
  27894         -1,
  27895     },
  27896 #endif /* chips */
  27897 
  27898 #if defined(BCM_56370_A0)
  27899     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM56370_A0r */
  27900         soc_block_list[61],
  27901         soc_iprocreg,
  27902         1,
  27903         0,
  27904         0x15000324,
  27905         0,
  27906         0,
  27907         2,
  27908         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27910         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27911         -1,
  27912         -1,
  27913         3,
  27914     },
  27915 #endif /* chips */
  27916 
  27917 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  27918     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  27919     defined(BCM_56450_B1)
  27920     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM56450_A0r */
  27921         soc_block_list[61],
  27922         soc_iprocreg,
  27923         1,
  27924         0,
  27925         0x18027324,
  27926         0,
  27927         0,
  27928         2,
  27929         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  27930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27931         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27932         -1,
  27933         -1,
  27934     },
  27935 #endif /* chips */
  27936 
  27937 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  27938     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  27939     defined(BCM_56670_B0)
  27940     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM56560_A0r */
  27941         soc_block_list[61],
  27942         soc_iprocreg,
  27943         1,
  27944         0,
  27945         0x18021324,
  27946         0,
  27947         0,
  27948         2,
  27949         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27952         -1,
  27953         -1,
  27954     },
  27955 #endif /* chips */
  27956 
  27957 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  27958     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  27959     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  27960     defined(BCM_56980_B0)
  27961     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM56960_A0r */
  27962         soc_block_list[61],
  27963         soc_iprocreg,
  27964         1,
  27965         0,
  27966         0x18021324,
  27967         0,
  27968         0,
  27969         2,
  27970         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  27971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27972         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27973         -1,
  27974         -1,
  27975         3,
  27976     },
  27977 #endif /* chips */
  27978 
  27979 #if defined(BCM_88270_A0)
  27980     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM88270_A0r */
  27981         soc_block_list[61],
  27982         soc_iprocreg,
  27983         1,
  27984         0,
  27985         0x18021324,
  27986         0,
  27987         0,
  27988         2,
  27989         soc_QSPI_MSPI_RXRAM25_BCM88270_A0r_fields,
  27990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27991         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27992         -1,
  27993         -1,
  27994     },
  27995 #endif /* chips */
  27996 
  27997 #if defined(BCM_88375_A0)
  27998     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM88375_A0r */
  27999         soc_block_list[61],
  28000         soc_iprocreg,
  28001         1,
  28002         0,
  28003         0x18021324,
  28004         0,
  28005         0,
  28006         2,
  28007         soc_QSPI_MSPI_RXRAM25_BCM88375_A0r_fields,
  28008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28009         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28010         -1,
  28011         -1,
  28012     },
  28013 #endif /* chips */
  28014 
  28015 #if defined(BCM_88375_B0)
  28016     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM88375_B0r */
  28017         soc_block_list[61],
  28018         soc_iprocreg,
  28019         1,
  28020         0,
  28021         0x18021324,
  28022         0,
  28023         0,
  28024         2,
  28025         soc_QSPI_MSPI_RXRAM25_BCM88375_B0r_fields,
  28026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28028         -1,
  28029         -1,
  28030     },
  28031 #endif /* chips */
  28032 
  28033 #if defined(BCM_88470_A0)
  28034     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM88470_A0r */
  28035         soc_block_list[61],
  28036         soc_iprocreg,
  28037         1,
  28038         0,
  28039         0x18021324,
  28040         0,
  28041         0,
  28042         2,
  28043         soc_QSPI_MSPI_RXRAM25_BCM88470_A0r_fields,
  28044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28045         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28046         -1,
  28047         -1,
  28048     },
  28049 #endif /* chips */
  28050 
  28051 #if defined(BCM_88470_B0)
  28052     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM88470_B0r */
  28053         soc_block_list[61],
  28054         soc_iprocreg,
  28055         1,
  28056         0,
  28057         0x18021324,
  28058         0,
  28059         0,
  28060         2,
  28061         soc_QSPI_MSPI_RXRAM25_BCM88470_B0r_fields,
  28062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28063         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28064         -1,
  28065         -1,
  28066     },
  28067 #endif /* chips */
  28068 
  28069 #if defined(BCM_88675_B0)
  28070     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM88675_B0r */
  28071         soc_block_list[61],
  28072         soc_iprocreg,
  28073         1,
  28074         0,
  28075         0x18021324,
  28076         0,
  28077         0,
  28078         2,
  28079         soc_QSPI_MSPI_RXRAM25_BCM88675_B0r_fields,
  28080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28081         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28082         -1,
  28083         -1,
  28084     },
  28085 #endif /* chips */
  28086 
  28087 #if defined(BCM_88680_A0)
  28088     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM88680_A0r */
  28089         soc_block_list[61],
  28090         soc_iprocreg,
  28091         1,
  28092         0,
  28093         0x18021324,
  28094         0,
  28095         0,
  28096         2,
  28097         soc_QSPI_MSPI_RXRAM25_BCM88680_A0r_fields,
  28098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28099         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28100         -1,
  28101         -1,
  28102     },
  28103 #endif /* chips */
  28104 
  28105 #if defined(BCM_88690_A0)
  28106     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM88690_A0r */
  28107         soc_block_list[61],
  28108         soc_iprocreg,
  28109         1,
  28110         0,
  28111         0x18021324,
  28112         0,
  28113         0,
  28114         2,
  28115         soc_QSPI_MSPI_RXRAM25_BCM88690_A0r_fields,
  28116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28117         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28118         -1,
  28119         -1,
  28120     },
  28121 #endif /* chips */
  28122 
  28123 #if defined(BCM_88690_B0)
  28124     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM88690_B0r */
  28125         soc_block_list[61],
  28126         soc_iprocreg,
  28127         1,
  28128         0,
  28129         0x18021324,
  28130         0,
  28131         0,
  28132         2,
  28133         soc_QSPI_MSPI_RXRAM25_BCM88690_B0r_fields,
  28134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28135         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28136         -1,
  28137         -1,
  28138     },
  28139 #endif /* chips */
  28140 
  28141 #if defined(BCM_88790_A0)
  28142     { /* SOC_REG_INT_QSPI_MSPI_RXRAM25_BCM88790_A0r */
  28143         soc_block_list[61],
  28144         soc_iprocreg,
  28145         1,
  28146         0,
  28147         0x18021324,
  28148         0,
  28149         0,
  28150         2,
  28151         soc_QSPI_MSPI_RXRAM25_BCM88790_A0r_fields,
  28152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28153         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28154         -1,
  28155         -1,
  28156     },
  28157 #endif /* chips */
  28158 
  28159 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28160     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28161     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28162     defined(BCM_56260_B0)
  28163     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM53400_A0r */
  28164         soc_block_list[61],
  28165         soc_iprocreg,
  28166         1,
  28167         0,
  28168         0x18047328,
  28169         0,
  28170         0,
  28171         2,
  28172         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28174         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28175         -1,
  28176         -1,
  28177     },
  28178 #endif /* chips */
  28179 
  28180 #if defined(BCM_56370_A0)
  28181     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM56370_A0r */
  28182         soc_block_list[61],
  28183         soc_iprocreg,
  28184         1,
  28185         0,
  28186         0x15000328,
  28187         0,
  28188         0,
  28189         2,
  28190         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28192         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28193         -1,
  28194         -1,
  28195         3,
  28196     },
  28197 #endif /* chips */
  28198 
  28199 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  28200     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  28201     defined(BCM_56450_B1)
  28202     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM56450_A0r */
  28203         soc_block_list[61],
  28204         soc_iprocreg,
  28205         1,
  28206         0,
  28207         0x18027328,
  28208         0,
  28209         0,
  28210         2,
  28211         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  28212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28213         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28214         -1,
  28215         -1,
  28216     },
  28217 #endif /* chips */
  28218 
  28219 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  28220     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  28221     defined(BCM_56670_B0)
  28222     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM56560_A0r */
  28223         soc_block_list[61],
  28224         soc_iprocreg,
  28225         1,
  28226         0,
  28227         0x18021328,
  28228         0,
  28229         0,
  28230         2,
  28231         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28233         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28234         -1,
  28235         -1,
  28236     },
  28237 #endif /* chips */
  28238 
  28239 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  28240     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  28241     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  28242     defined(BCM_56980_B0)
  28243     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM56960_A0r */
  28244         soc_block_list[61],
  28245         soc_iprocreg,
  28246         1,
  28247         0,
  28248         0x18021328,
  28249         0,
  28250         0,
  28251         2,
  28252         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28254         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28255         -1,
  28256         -1,
  28257         3,
  28258     },
  28259 #endif /* chips */
  28260 
  28261 #if defined(BCM_88270_A0)
  28262     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM88270_A0r */
  28263         soc_block_list[61],
  28264         soc_iprocreg,
  28265         1,
  28266         0,
  28267         0x18021328,
  28268         0,
  28269         0,
  28270         2,
  28271         soc_QSPI_MSPI_RXRAM26_BCM88270_A0r_fields,
  28272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28273         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28274         -1,
  28275         -1,
  28276     },
  28277 #endif /* chips */
  28278 
  28279 #if defined(BCM_88375_A0)
  28280     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM88375_A0r */
  28281         soc_block_list[61],
  28282         soc_iprocreg,
  28283         1,
  28284         0,
  28285         0x18021328,
  28286         0,
  28287         0,
  28288         2,
  28289         soc_QSPI_MSPI_RXRAM26_BCM88375_A0r_fields,
  28290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28291         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28292         -1,
  28293         -1,
  28294     },
  28295 #endif /* chips */
  28296 
  28297 #if defined(BCM_88375_B0)
  28298     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM88375_B0r */
  28299         soc_block_list[61],
  28300         soc_iprocreg,
  28301         1,
  28302         0,
  28303         0x18021328,
  28304         0,
  28305         0,
  28306         2,
  28307         soc_QSPI_MSPI_RXRAM26_BCM88375_B0r_fields,
  28308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28309         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28310         -1,
  28311         -1,
  28312     },
  28313 #endif /* chips */
  28314 
  28315 #if defined(BCM_88470_A0)
  28316     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM88470_A0r */
  28317         soc_block_list[61],
  28318         soc_iprocreg,
  28319         1,
  28320         0,
  28321         0x18021328,
  28322         0,
  28323         0,
  28324         2,
  28325         soc_QSPI_MSPI_RXRAM26_BCM88470_A0r_fields,
  28326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28327         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28328         -1,
  28329         -1,
  28330     },
  28331 #endif /* chips */
  28332 
  28333 #if defined(BCM_88470_B0)
  28334     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM88470_B0r */
  28335         soc_block_list[61],
  28336         soc_iprocreg,
  28337         1,
  28338         0,
  28339         0x18021328,
  28340         0,
  28341         0,
  28342         2,
  28343         soc_QSPI_MSPI_RXRAM26_BCM88470_B0r_fields,
  28344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28346         -1,
  28347         -1,
  28348     },
  28349 #endif /* chips */
  28350 
  28351 #if defined(BCM_88675_B0)
  28352     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM88675_B0r */
  28353         soc_block_list[61],
  28354         soc_iprocreg,
  28355         1,
  28356         0,
  28357         0x18021328,
  28358         0,
  28359         0,
  28360         2,
  28361         soc_QSPI_MSPI_RXRAM26_BCM88675_B0r_fields,
  28362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28363         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28364         -1,
  28365         -1,
  28366     },
  28367 #endif /* chips */
  28368 
  28369 #if defined(BCM_88680_A0)
  28370     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM88680_A0r */
  28371         soc_block_list[61],
  28372         soc_iprocreg,
  28373         1,
  28374         0,
  28375         0x18021328,
  28376         0,
  28377         0,
  28378         2,
  28379         soc_QSPI_MSPI_RXRAM26_BCM88680_A0r_fields,
  28380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28382         -1,
  28383         -1,
  28384     },
  28385 #endif /* chips */
  28386 
  28387 #if defined(BCM_88690_A0)
  28388     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM88690_A0r */
  28389         soc_block_list[61],
  28390         soc_iprocreg,
  28391         1,
  28392         0,
  28393         0x18021328,
  28394         0,
  28395         0,
  28396         2,
  28397         soc_QSPI_MSPI_RXRAM26_BCM88690_A0r_fields,
  28398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28399         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28400         -1,
  28401         -1,
  28402     },
  28403 #endif /* chips */
  28404 
  28405 #if defined(BCM_88690_B0)
  28406     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM88690_B0r */
  28407         soc_block_list[61],
  28408         soc_iprocreg,
  28409         1,
  28410         0,
  28411         0x18021328,
  28412         0,
  28413         0,
  28414         2,
  28415         soc_QSPI_MSPI_RXRAM26_BCM88690_B0r_fields,
  28416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28418         -1,
  28419         -1,
  28420     },
  28421 #endif /* chips */
  28422 
  28423 #if defined(BCM_88790_A0)
  28424     { /* SOC_REG_INT_QSPI_MSPI_RXRAM26_BCM88790_A0r */
  28425         soc_block_list[61],
  28426         soc_iprocreg,
  28427         1,
  28428         0,
  28429         0x18021328,
  28430         0,
  28431         0,
  28432         2,
  28433         soc_QSPI_MSPI_RXRAM26_BCM88790_A0r_fields,
  28434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28435         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28436         -1,
  28437         -1,
  28438     },
  28439 #endif /* chips */
  28440 
  28441 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28442     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28443     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28444     defined(BCM_56260_B0)
  28445     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM53400_A0r */
  28446         soc_block_list[61],
  28447         soc_iprocreg,
  28448         1,
  28449         0,
  28450         0x1804732c,
  28451         0,
  28452         0,
  28453         2,
  28454         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28456         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28457         -1,
  28458         -1,
  28459     },
  28460 #endif /* chips */
  28461 
  28462 #if defined(BCM_56370_A0)
  28463     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM56370_A0r */
  28464         soc_block_list[61],
  28465         soc_iprocreg,
  28466         1,
  28467         0,
  28468         0x1500032c,
  28469         0,
  28470         0,
  28471         2,
  28472         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28474         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28475         -1,
  28476         -1,
  28477         3,
  28478     },
  28479 #endif /* chips */
  28480 
  28481 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  28482     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  28483     defined(BCM_56450_B1)
  28484     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM56450_A0r */
  28485         soc_block_list[61],
  28486         soc_iprocreg,
  28487         1,
  28488         0,
  28489         0x1802732c,
  28490         0,
  28491         0,
  28492         2,
  28493         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  28494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28495         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28496         -1,
  28497         -1,
  28498     },
  28499 #endif /* chips */
  28500 
  28501 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  28502     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  28503     defined(BCM_56670_B0)
  28504     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM56560_A0r */
  28505         soc_block_list[61],
  28506         soc_iprocreg,
  28507         1,
  28508         0,
  28509         0x1802132c,
  28510         0,
  28511         0,
  28512         2,
  28513         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28516         -1,
  28517         -1,
  28518     },
  28519 #endif /* chips */
  28520 
  28521 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  28522     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  28523     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  28524     defined(BCM_56980_B0)
  28525     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM56960_A0r */
  28526         soc_block_list[61],
  28527         soc_iprocreg,
  28528         1,
  28529         0,
  28530         0x1802132c,
  28531         0,
  28532         0,
  28533         2,
  28534         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28536         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28537         -1,
  28538         -1,
  28539         3,
  28540     },
  28541 #endif /* chips */
  28542 
  28543 #if defined(BCM_88270_A0)
  28544     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM88270_A0r */
  28545         soc_block_list[61],
  28546         soc_iprocreg,
  28547         1,
  28548         0,
  28549         0x1802132c,
  28550         0,
  28551         0,
  28552         2,
  28553         soc_QSPI_MSPI_RXRAM27_BCM88270_A0r_fields,
  28554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28555         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28556         -1,
  28557         -1,
  28558     },
  28559 #endif /* chips */
  28560 
  28561 #if defined(BCM_88375_A0)
  28562     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM88375_A0r */
  28563         soc_block_list[61],
  28564         soc_iprocreg,
  28565         1,
  28566         0,
  28567         0x1802132c,
  28568         0,
  28569         0,
  28570         2,
  28571         soc_QSPI_MSPI_RXRAM27_BCM88375_A0r_fields,
  28572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28573         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28574         -1,
  28575         -1,
  28576     },
  28577 #endif /* chips */
  28578 
  28579 #if defined(BCM_88375_B0)
  28580     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM88375_B0r */
  28581         soc_block_list[61],
  28582         soc_iprocreg,
  28583         1,
  28584         0,
  28585         0x1802132c,
  28586         0,
  28587         0,
  28588         2,
  28589         soc_QSPI_MSPI_RXRAM27_BCM88375_B0r_fields,
  28590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28591         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28592         -1,
  28593         -1,
  28594     },
  28595 #endif /* chips */
  28596 
  28597 #if defined(BCM_88470_A0)
  28598     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM88470_A0r */
  28599         soc_block_list[61],
  28600         soc_iprocreg,
  28601         1,
  28602         0,
  28603         0x1802132c,
  28604         0,
  28605         0,
  28606         2,
  28607         soc_QSPI_MSPI_RXRAM27_BCM88470_A0r_fields,
  28608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28609         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28610         -1,
  28611         -1,
  28612     },
  28613 #endif /* chips */
  28614 
  28615 #if defined(BCM_88470_B0)
  28616     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM88470_B0r */
  28617         soc_block_list[61],
  28618         soc_iprocreg,
  28619         1,
  28620         0,
  28621         0x1802132c,
  28622         0,
  28623         0,
  28624         2,
  28625         soc_QSPI_MSPI_RXRAM27_BCM88470_B0r_fields,
  28626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28627         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28628         -1,
  28629         -1,
  28630     },
  28631 #endif /* chips */
  28632 
  28633 #if defined(BCM_88675_B0)
  28634     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM88675_B0r */
  28635         soc_block_list[61],
  28636         soc_iprocreg,
  28637         1,
  28638         0,
  28639         0x1802132c,
  28640         0,
  28641         0,
  28642         2,
  28643         soc_QSPI_MSPI_RXRAM27_BCM88675_B0r_fields,
  28644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28646         -1,
  28647         -1,
  28648     },
  28649 #endif /* chips */
  28650 
  28651 #if defined(BCM_88680_A0)
  28652     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM88680_A0r */
  28653         soc_block_list[61],
  28654         soc_iprocreg,
  28655         1,
  28656         0,
  28657         0x1802132c,
  28658         0,
  28659         0,
  28660         2,
  28661         soc_QSPI_MSPI_RXRAM27_BCM88680_A0r_fields,
  28662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28663         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28664         -1,
  28665         -1,
  28666     },
  28667 #endif /* chips */
  28668 
  28669 #if defined(BCM_88690_A0)
  28670     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM88690_A0r */
  28671         soc_block_list[61],
  28672         soc_iprocreg,
  28673         1,
  28674         0,
  28675         0x1802132c,
  28676         0,
  28677         0,
  28678         2,
  28679         soc_QSPI_MSPI_RXRAM27_BCM88690_A0r_fields,
  28680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28681         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28682         -1,
  28683         -1,
  28684     },
  28685 #endif /* chips */
  28686 
  28687 #if defined(BCM_88690_B0)
  28688     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM88690_B0r */
  28689         soc_block_list[61],
  28690         soc_iprocreg,
  28691         1,
  28692         0,
  28693         0x1802132c,
  28694         0,
  28695         0,
  28696         2,
  28697         soc_QSPI_MSPI_RXRAM27_BCM88690_B0r_fields,
  28698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28699         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28700         -1,
  28701         -1,
  28702     },
  28703 #endif /* chips */
  28704 
  28705 #if defined(BCM_88790_A0)
  28706     { /* SOC_REG_INT_QSPI_MSPI_RXRAM27_BCM88790_A0r */
  28707         soc_block_list[61],
  28708         soc_iprocreg,
  28709         1,
  28710         0,
  28711         0x1802132c,
  28712         0,
  28713         0,
  28714         2,
  28715         soc_QSPI_MSPI_RXRAM27_BCM88790_A0r_fields,
  28716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28718         -1,
  28719         -1,
  28720     },
  28721 #endif /* chips */
  28722 
  28723 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  28724     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  28725     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  28726     defined(BCM_56260_B0)
  28727     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM53400_A0r */
  28728         soc_block_list[61],
  28729         soc_iprocreg,
  28730         1,
  28731         0,
  28732         0x18047330,
  28733         0,
  28734         0,
  28735         2,
  28736         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28738         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28739         -1,
  28740         -1,
  28741     },
  28742 #endif /* chips */
  28743 
  28744 #if defined(BCM_56370_A0)
  28745     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM56370_A0r */
  28746         soc_block_list[61],
  28747         soc_iprocreg,
  28748         1,
  28749         0,
  28750         0x15000330,
  28751         0,
  28752         0,
  28753         2,
  28754         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28757         -1,
  28758         -1,
  28759         3,
  28760     },
  28761 #endif /* chips */
  28762 
  28763 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  28764     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  28765     defined(BCM_56450_B1)
  28766     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM56450_A0r */
  28767         soc_block_list[61],
  28768         soc_iprocreg,
  28769         1,
  28770         0,
  28771         0x18027330,
  28772         0,
  28773         0,
  28774         2,
  28775         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  28776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28778         -1,
  28779         -1,
  28780     },
  28781 #endif /* chips */
  28782 
  28783 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  28784     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  28785     defined(BCM_56670_B0)
  28786     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM56560_A0r */
  28787         soc_block_list[61],
  28788         soc_iprocreg,
  28789         1,
  28790         0,
  28791         0x18021330,
  28792         0,
  28793         0,
  28794         2,
  28795         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28797         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28798         -1,
  28799         -1,
  28800     },
  28801 #endif /* chips */
  28802 
  28803 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  28804     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  28805     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  28806     defined(BCM_56980_B0)
  28807     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM56960_A0r */
  28808         soc_block_list[61],
  28809         soc_iprocreg,
  28810         1,
  28811         0,
  28812         0x18021330,
  28813         0,
  28814         0,
  28815         2,
  28816         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  28817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28818         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28819         -1,
  28820         -1,
  28821         3,
  28822     },
  28823 #endif /* chips */
  28824 
  28825 #if defined(BCM_88270_A0)
  28826     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM88270_A0r */
  28827         soc_block_list[61],
  28828         soc_iprocreg,
  28829         1,
  28830         0,
  28831         0x18021330,
  28832         0,
  28833         0,
  28834         2,
  28835         soc_QSPI_MSPI_RXRAM28_BCM88270_A0r_fields,
  28836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28837         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28838         -1,
  28839         -1,
  28840     },
  28841 #endif /* chips */
  28842 
  28843 #if defined(BCM_88375_A0)
  28844     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM88375_A0r */
  28845         soc_block_list[61],
  28846         soc_iprocreg,
  28847         1,
  28848         0,
  28849         0x18021330,
  28850         0,
  28851         0,
  28852         2,
  28853         soc_QSPI_MSPI_RXRAM28_BCM88375_A0r_fields,
  28854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28855         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28856         -1,
  28857         -1,
  28858     },
  28859 #endif /* chips */
  28860 
  28861 #if defined(BCM_88375_B0)
  28862     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM88375_B0r */
  28863         soc_block_list[61],
  28864         soc_iprocreg,
  28865         1,
  28866         0,
  28867         0x18021330,
  28868         0,
  28869         0,
  28870         2,
  28871         soc_QSPI_MSPI_RXRAM28_BCM88375_B0r_fields,
  28872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28873         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28874         -1,
  28875         -1,
  28876     },
  28877 #endif /* chips */
  28878 
  28879 #if defined(BCM_88470_A0)
  28880     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM88470_A0r */
  28881         soc_block_list[61],
  28882         soc_iprocreg,
  28883         1,
  28884         0,
  28885         0x18021330,
  28886         0,
  28887         0,
  28888         2,
  28889         soc_QSPI_MSPI_RXRAM28_BCM88470_A0r_fields,
  28890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28891         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28892         -1,
  28893         -1,
  28894     },
  28895 #endif /* chips */
  28896 
  28897 #if defined(BCM_88470_B0)
  28898     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM88470_B0r */
  28899         soc_block_list[61],
  28900         soc_iprocreg,
  28901         1,
  28902         0,
  28903         0x18021330,
  28904         0,
  28905         0,
  28906         2,
  28907         soc_QSPI_MSPI_RXRAM28_BCM88470_B0r_fields,
  28908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28909         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28910         -1,
  28911         -1,
  28912     },
  28913 #endif /* chips */
  28914 
  28915 #if defined(BCM_88675_B0)
  28916     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM88675_B0r */
  28917         soc_block_list[61],
  28918         soc_iprocreg,
  28919         1,
  28920         0,
  28921         0x18021330,
  28922         0,
  28923         0,
  28924         2,
  28925         soc_QSPI_MSPI_RXRAM28_BCM88675_B0r_fields,
  28926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28927         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28928         -1,
  28929         -1,
  28930     },
  28931 #endif /* chips */
  28932 
  28933 #if defined(BCM_88680_A0)
  28934     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM88680_A0r */
  28935         soc_block_list[61],
  28936         soc_iprocreg,
  28937         1,
  28938         0,
  28939         0x18021330,
  28940         0,
  28941         0,
  28942         2,
  28943         soc_QSPI_MSPI_RXRAM28_BCM88680_A0r_fields,
  28944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28946         -1,
  28947         -1,
  28948     },
  28949 #endif /* chips */
  28950 
  28951 #if defined(BCM_88690_A0)
  28952     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM88690_A0r */
  28953         soc_block_list[61],
  28954         soc_iprocreg,
  28955         1,
  28956         0,
  28957         0x18021330,
  28958         0,
  28959         0,
  28960         2,
  28961         soc_QSPI_MSPI_RXRAM28_BCM88690_A0r_fields,
  28962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28964         -1,
  28965         -1,
  28966     },
  28967 #endif /* chips */
  28968 
  28969 #if defined(BCM_88690_B0)
  28970     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM88690_B0r */
  28971         soc_block_list[61],
  28972         soc_iprocreg,
  28973         1,
  28974         0,
  28975         0x18021330,
  28976         0,
  28977         0,
  28978         2,
  28979         soc_QSPI_MSPI_RXRAM28_BCM88690_B0r_fields,
  28980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28981         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28982         -1,
  28983         -1,
  28984     },
  28985 #endif /* chips */
  28986 
  28987 #if defined(BCM_88790_A0)
  28988     { /* SOC_REG_INT_QSPI_MSPI_RXRAM28_BCM88790_A0r */
  28989         soc_block_list[61],
  28990         soc_iprocreg,
  28991         1,
  28992         0,
  28993         0x18021330,
  28994         0,
  28995         0,
  28996         2,
  28997         soc_QSPI_MSPI_RXRAM28_BCM88790_A0r_fields,
  28998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28999         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29000         -1,
  29001         -1,
  29002     },
  29003 #endif /* chips */
  29004 
  29005 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29006     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29007     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29008     defined(BCM_56260_B0)
  29009     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM53400_A0r */
  29010         soc_block_list[61],
  29011         soc_iprocreg,
  29012         1,
  29013         0,
  29014         0x18047334,
  29015         0,
  29016         0,
  29017         2,
  29018         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29020         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29021         -1,
  29022         -1,
  29023     },
  29024 #endif /* chips */
  29025 
  29026 #if defined(BCM_56370_A0)
  29027     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM56370_A0r */
  29028         soc_block_list[61],
  29029         soc_iprocreg,
  29030         1,
  29031         0,
  29032         0x15000334,
  29033         0,
  29034         0,
  29035         2,
  29036         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29038         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29039         -1,
  29040         -1,
  29041         3,
  29042     },
  29043 #endif /* chips */
  29044 
  29045 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  29046     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  29047     defined(BCM_56450_B1)
  29048     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM56450_A0r */
  29049         soc_block_list[61],
  29050         soc_iprocreg,
  29051         1,
  29052         0,
  29053         0x18027334,
  29054         0,
  29055         0,
  29056         2,
  29057         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  29058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29059         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29060         -1,
  29061         -1,
  29062     },
  29063 #endif /* chips */
  29064 
  29065 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  29066     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  29067     defined(BCM_56670_B0)
  29068     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM56560_A0r */
  29069         soc_block_list[61],
  29070         soc_iprocreg,
  29071         1,
  29072         0,
  29073         0x18021334,
  29074         0,
  29075         0,
  29076         2,
  29077         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29079         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29080         -1,
  29081         -1,
  29082     },
  29083 #endif /* chips */
  29084 
  29085 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  29086     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  29087     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  29088     defined(BCM_56980_B0)
  29089     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM56960_A0r */
  29090         soc_block_list[61],
  29091         soc_iprocreg,
  29092         1,
  29093         0,
  29094         0x18021334,
  29095         0,
  29096         0,
  29097         2,
  29098         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29100         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29101         -1,
  29102         -1,
  29103         3,
  29104     },
  29105 #endif /* chips */
  29106 
  29107 #if defined(BCM_88270_A0)
  29108     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM88270_A0r */
  29109         soc_block_list[61],
  29110         soc_iprocreg,
  29111         1,
  29112         0,
  29113         0x18021334,
  29114         0,
  29115         0,
  29116         2,
  29117         soc_QSPI_MSPI_RXRAM29_BCM88270_A0r_fields,
  29118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29119         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29120         -1,
  29121         -1,
  29122     },
  29123 #endif /* chips */
  29124 
  29125 #if defined(BCM_88375_A0)
  29126     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM88375_A0r */
  29127         soc_block_list[61],
  29128         soc_iprocreg,
  29129         1,
  29130         0,
  29131         0x18021334,
  29132         0,
  29133         0,
  29134         2,
  29135         soc_QSPI_MSPI_RXRAM29_BCM88375_A0r_fields,
  29136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29138         -1,
  29139         -1,
  29140     },
  29141 #endif /* chips */
  29142 
  29143 #if defined(BCM_88375_B0)
  29144     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM88375_B0r */
  29145         soc_block_list[61],
  29146         soc_iprocreg,
  29147         1,
  29148         0,
  29149         0x18021334,
  29150         0,
  29151         0,
  29152         2,
  29153         soc_QSPI_MSPI_RXRAM29_BCM88375_B0r_fields,
  29154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29156         -1,
  29157         -1,
  29158     },
  29159 #endif /* chips */
  29160 
  29161 #if defined(BCM_88470_A0)
  29162     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM88470_A0r */
  29163         soc_block_list[61],
  29164         soc_iprocreg,
  29165         1,
  29166         0,
  29167         0x18021334,
  29168         0,
  29169         0,
  29170         2,
  29171         soc_QSPI_MSPI_RXRAM29_BCM88470_A0r_fields,
  29172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29173         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29174         -1,
  29175         -1,
  29176     },
  29177 #endif /* chips */
  29178 
  29179 #if defined(BCM_88470_B0)
  29180     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM88470_B0r */
  29181         soc_block_list[61],
  29182         soc_iprocreg,
  29183         1,
  29184         0,
  29185         0x18021334,
  29186         0,
  29187         0,
  29188         2,
  29189         soc_QSPI_MSPI_RXRAM29_BCM88470_B0r_fields,
  29190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29191         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29192         -1,
  29193         -1,
  29194     },
  29195 #endif /* chips */
  29196 
  29197 #if defined(BCM_88675_B0)
  29198     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM88675_B0r */
  29199         soc_block_list[61],
  29200         soc_iprocreg,
  29201         1,
  29202         0,
  29203         0x18021334,
  29204         0,
  29205         0,
  29206         2,
  29207         soc_QSPI_MSPI_RXRAM29_BCM88675_B0r_fields,
  29208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29209         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29210         -1,
  29211         -1,
  29212     },
  29213 #endif /* chips */
  29214 
  29215 #if defined(BCM_88680_A0)
  29216     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM88680_A0r */
  29217         soc_block_list[61],
  29218         soc_iprocreg,
  29219         1,
  29220         0,
  29221         0x18021334,
  29222         0,
  29223         0,
  29224         2,
  29225         soc_QSPI_MSPI_RXRAM29_BCM88680_A0r_fields,
  29226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29227         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29228         -1,
  29229         -1,
  29230     },
  29231 #endif /* chips */
  29232 
  29233 #if defined(BCM_88690_A0)
  29234     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM88690_A0r */
  29235         soc_block_list[61],
  29236         soc_iprocreg,
  29237         1,
  29238         0,
  29239         0x18021334,
  29240         0,
  29241         0,
  29242         2,
  29243         soc_QSPI_MSPI_RXRAM29_BCM88690_A0r_fields,
  29244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29246         -1,
  29247         -1,
  29248     },
  29249 #endif /* chips */
  29250 
  29251 #if defined(BCM_88690_B0)
  29252     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM88690_B0r */
  29253         soc_block_list[61],
  29254         soc_iprocreg,
  29255         1,
  29256         0,
  29257         0x18021334,
  29258         0,
  29259         0,
  29260         2,
  29261         soc_QSPI_MSPI_RXRAM29_BCM88690_B0r_fields,
  29262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29264         -1,
  29265         -1,
  29266     },
  29267 #endif /* chips */
  29268 
  29269 #if defined(BCM_88790_A0)
  29270     { /* SOC_REG_INT_QSPI_MSPI_RXRAM29_BCM88790_A0r */
  29271         soc_block_list[61],
  29272         soc_iprocreg,
  29273         1,
  29274         0,
  29275         0x18021334,
  29276         0,
  29277         0,
  29278         2,
  29279         soc_QSPI_MSPI_RXRAM29_BCM88790_A0r_fields,
  29280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29281         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29282         -1,
  29283         -1,
  29284     },
  29285 #endif /* chips */
  29286 
  29287 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29288     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29289     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29290     defined(BCM_56260_B0)
  29291     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM53400_A0r */
  29292         soc_block_list[61],
  29293         soc_iprocreg,
  29294         1,
  29295         0,
  29296         0x18047338,
  29297         0,
  29298         0,
  29299         2,
  29300         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29302         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29303         -1,
  29304         -1,
  29305     },
  29306 #endif /* chips */
  29307 
  29308 #if defined(BCM_56370_A0)
  29309     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM56370_A0r */
  29310         soc_block_list[61],
  29311         soc_iprocreg,
  29312         1,
  29313         0,
  29314         0x15000338,
  29315         0,
  29316         0,
  29317         2,
  29318         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29320         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29321         -1,
  29322         -1,
  29323         3,
  29324     },
  29325 #endif /* chips */
  29326 
  29327 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  29328     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  29329     defined(BCM_56450_B1)
  29330     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM56450_A0r */
  29331         soc_block_list[61],
  29332         soc_iprocreg,
  29333         1,
  29334         0,
  29335         0x18027338,
  29336         0,
  29337         0,
  29338         2,
  29339         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  29340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29341         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29342         -1,
  29343         -1,
  29344     },
  29345 #endif /* chips */
  29346 
  29347 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  29348     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  29349     defined(BCM_56670_B0)
  29350     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM56560_A0r */
  29351         soc_block_list[61],
  29352         soc_iprocreg,
  29353         1,
  29354         0,
  29355         0x18021338,
  29356         0,
  29357         0,
  29358         2,
  29359         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29361         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29362         -1,
  29363         -1,
  29364     },
  29365 #endif /* chips */
  29366 
  29367 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  29368     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  29369     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  29370     defined(BCM_56980_B0)
  29371     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM56960_A0r */
  29372         soc_block_list[61],
  29373         soc_iprocreg,
  29374         1,
  29375         0,
  29376         0x18021338,
  29377         0,
  29378         0,
  29379         2,
  29380         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29382         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29383         -1,
  29384         -1,
  29385         3,
  29386     },
  29387 #endif /* chips */
  29388 
  29389 #if defined(BCM_88270_A0)
  29390     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM88270_A0r */
  29391         soc_block_list[61],
  29392         soc_iprocreg,
  29393         1,
  29394         0,
  29395         0x18021338,
  29396         0,
  29397         0,
  29398         2,
  29399         soc_QSPI_MSPI_RXRAM30_BCM88270_A0r_fields,
  29400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29401         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29402         -1,
  29403         -1,
  29404     },
  29405 #endif /* chips */
  29406 
  29407 #if defined(BCM_88375_A0)
  29408     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM88375_A0r */
  29409         soc_block_list[61],
  29410         soc_iprocreg,
  29411         1,
  29412         0,
  29413         0x18021338,
  29414         0,
  29415         0,
  29416         2,
  29417         soc_QSPI_MSPI_RXRAM30_BCM88375_A0r_fields,
  29418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29420         -1,
  29421         -1,
  29422     },
  29423 #endif /* chips */
  29424 
  29425 #if defined(BCM_88375_B0)
  29426     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM88375_B0r */
  29427         soc_block_list[61],
  29428         soc_iprocreg,
  29429         1,
  29430         0,
  29431         0x18021338,
  29432         0,
  29433         0,
  29434         2,
  29435         soc_QSPI_MSPI_RXRAM30_BCM88375_B0r_fields,
  29436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29437         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29438         -1,
  29439         -1,
  29440     },
  29441 #endif /* chips */
  29442 
  29443 #if defined(BCM_88470_A0)
  29444     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM88470_A0r */
  29445         soc_block_list[61],
  29446         soc_iprocreg,
  29447         1,
  29448         0,
  29449         0x18021338,
  29450         0,
  29451         0,
  29452         2,
  29453         soc_QSPI_MSPI_RXRAM30_BCM88470_A0r_fields,
  29454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29455         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29456         -1,
  29457         -1,
  29458     },
  29459 #endif /* chips */
  29460 
  29461 #if defined(BCM_88470_B0)
  29462     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM88470_B0r */
  29463         soc_block_list[61],
  29464         soc_iprocreg,
  29465         1,
  29466         0,
  29467         0x18021338,
  29468         0,
  29469         0,
  29470         2,
  29471         soc_QSPI_MSPI_RXRAM30_BCM88470_B0r_fields,
  29472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29473         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29474         -1,
  29475         -1,
  29476     },
  29477 #endif /* chips */
  29478 
  29479 #if defined(BCM_88675_B0)
  29480     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM88675_B0r */
  29481         soc_block_list[61],
  29482         soc_iprocreg,
  29483         1,
  29484         0,
  29485         0x18021338,
  29486         0,
  29487         0,
  29488         2,
  29489         soc_QSPI_MSPI_RXRAM30_BCM88675_B0r_fields,
  29490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29491         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29492         -1,
  29493         -1,
  29494     },
  29495 #endif /* chips */
  29496 
  29497 #if defined(BCM_88680_A0)
  29498     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM88680_A0r */
  29499         soc_block_list[61],
  29500         soc_iprocreg,
  29501         1,
  29502         0,
  29503         0x18021338,
  29504         0,
  29505         0,
  29506         2,
  29507         soc_QSPI_MSPI_RXRAM30_BCM88680_A0r_fields,
  29508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29509         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29510         -1,
  29511         -1,
  29512     },
  29513 #endif /* chips */
  29514 
  29515 #if defined(BCM_88690_A0)
  29516     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM88690_A0r */
  29517         soc_block_list[61],
  29518         soc_iprocreg,
  29519         1,
  29520         0,
  29521         0x18021338,
  29522         0,
  29523         0,
  29524         2,
  29525         soc_QSPI_MSPI_RXRAM30_BCM88690_A0r_fields,
  29526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29527         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29528         -1,
  29529         -1,
  29530     },
  29531 #endif /* chips */
  29532 
  29533 #if defined(BCM_88690_B0)
  29534     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM88690_B0r */
  29535         soc_block_list[61],
  29536         soc_iprocreg,
  29537         1,
  29538         0,
  29539         0x18021338,
  29540         0,
  29541         0,
  29542         2,
  29543         soc_QSPI_MSPI_RXRAM30_BCM88690_B0r_fields,
  29544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29545         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29546         -1,
  29547         -1,
  29548     },
  29549 #endif /* chips */
  29550 
  29551 #if defined(BCM_88790_A0)
  29552     { /* SOC_REG_INT_QSPI_MSPI_RXRAM30_BCM88790_A0r */
  29553         soc_block_list[61],
  29554         soc_iprocreg,
  29555         1,
  29556         0,
  29557         0x18021338,
  29558         0,
  29559         0,
  29560         2,
  29561         soc_QSPI_MSPI_RXRAM30_BCM88790_A0r_fields,
  29562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29563         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29564         -1,
  29565         -1,
  29566     },
  29567 #endif /* chips */
  29568 
  29569 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29570     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29571     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29572     defined(BCM_56260_B0)
  29573     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM53400_A0r */
  29574         soc_block_list[61],
  29575         soc_iprocreg,
  29576         1,
  29577         0,
  29578         0x1804733c,
  29579         0,
  29580         0,
  29581         2,
  29582         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29584         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29585         -1,
  29586         -1,
  29587     },
  29588 #endif /* chips */
  29589 
  29590 #if defined(BCM_56370_A0)
  29591     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM56370_A0r */
  29592         soc_block_list[61],
  29593         soc_iprocreg,
  29594         1,
  29595         0,
  29596         0x1500033c,
  29597         0,
  29598         0,
  29599         2,
  29600         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29602         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29603         -1,
  29604         -1,
  29605         3,
  29606     },
  29607 #endif /* chips */
  29608 
  29609 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  29610     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  29611     defined(BCM_56450_B1)
  29612     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM56450_A0r */
  29613         soc_block_list[61],
  29614         soc_iprocreg,
  29615         1,
  29616         0,
  29617         0x1802733c,
  29618         0,
  29619         0,
  29620         2,
  29621         soc_QSPI_MSPI_RXRAM00_BCM56450_A0r_fields,
  29622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29623         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29624         -1,
  29625         -1,
  29626     },
  29627 #endif /* chips */
  29628 
  29629 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  29630     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  29631     defined(BCM_56670_B0)
  29632     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM56560_A0r */
  29633         soc_block_list[61],
  29634         soc_iprocreg,
  29635         1,
  29636         0,
  29637         0x1802133c,
  29638         0,
  29639         0,
  29640         2,
  29641         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29643         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29644         -1,
  29645         -1,
  29646     },
  29647 #endif /* chips */
  29648 
  29649 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  29650     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  29651     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  29652     defined(BCM_56980_B0)
  29653     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM56960_A0r */
  29654         soc_block_list[61],
  29655         soc_iprocreg,
  29656         1,
  29657         0,
  29658         0x1802133c,
  29659         0,
  29660         0,
  29661         2,
  29662         soc_QSPI_MSPI_RXRAM00_BCM53400_A0r_fields,
  29663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29664         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29665         -1,
  29666         -1,
  29667         3,
  29668     },
  29669 #endif /* chips */
  29670 
  29671 #if defined(BCM_88270_A0)
  29672     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM88270_A0r */
  29673         soc_block_list[61],
  29674         soc_iprocreg,
  29675         1,
  29676         0,
  29677         0x1802133c,
  29678         0,
  29679         0,
  29680         2,
  29681         soc_QSPI_MSPI_RXRAM31_BCM88270_A0r_fields,
  29682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29683         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29684         -1,
  29685         -1,
  29686     },
  29687 #endif /* chips */
  29688 
  29689 #if defined(BCM_88375_A0)
  29690     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM88375_A0r */
  29691         soc_block_list[61],
  29692         soc_iprocreg,
  29693         1,
  29694         0,
  29695         0x1802133c,
  29696         0,
  29697         0,
  29698         2,
  29699         soc_QSPI_MSPI_RXRAM31_BCM88375_A0r_fields,
  29700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29701         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29702         -1,
  29703         -1,
  29704     },
  29705 #endif /* chips */
  29706 
  29707 #if defined(BCM_88375_B0)
  29708     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM88375_B0r */
  29709         soc_block_list[61],
  29710         soc_iprocreg,
  29711         1,
  29712         0,
  29713         0x1802133c,
  29714         0,
  29715         0,
  29716         2,
  29717         soc_QSPI_MSPI_RXRAM31_BCM88375_B0r_fields,
  29718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29719         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29720         -1,
  29721         -1,
  29722     },
  29723 #endif /* chips */
  29724 
  29725 #if defined(BCM_88470_A0)
  29726     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM88470_A0r */
  29727         soc_block_list[61],
  29728         soc_iprocreg,
  29729         1,
  29730         0,
  29731         0x1802133c,
  29732         0,
  29733         0,
  29734         2,
  29735         soc_QSPI_MSPI_RXRAM31_BCM88470_A0r_fields,
  29736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29737         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29738         -1,
  29739         -1,
  29740     },
  29741 #endif /* chips */
  29742 
  29743 #if defined(BCM_88470_B0)
  29744     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM88470_B0r */
  29745         soc_block_list[61],
  29746         soc_iprocreg,
  29747         1,
  29748         0,
  29749         0x1802133c,
  29750         0,
  29751         0,
  29752         2,
  29753         soc_QSPI_MSPI_RXRAM31_BCM88470_B0r_fields,
  29754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29755         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29756         -1,
  29757         -1,
  29758     },
  29759 #endif /* chips */
  29760 
  29761 #if defined(BCM_88675_B0)
  29762     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM88675_B0r */
  29763         soc_block_list[61],
  29764         soc_iprocreg,
  29765         1,
  29766         0,
  29767         0x1802133c,
  29768         0,
  29769         0,
  29770         2,
  29771         soc_QSPI_MSPI_RXRAM31_BCM88675_B0r_fields,
  29772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29773         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29774         -1,
  29775         -1,
  29776     },
  29777 #endif /* chips */
  29778 
  29779 #if defined(BCM_88680_A0)
  29780     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM88680_A0r */
  29781         soc_block_list[61],
  29782         soc_iprocreg,
  29783         1,
  29784         0,
  29785         0x1802133c,
  29786         0,
  29787         0,
  29788         2,
  29789         soc_QSPI_MSPI_RXRAM31_BCM88680_A0r_fields,
  29790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29791         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29792         -1,
  29793         -1,
  29794     },
  29795 #endif /* chips */
  29796 
  29797 #if defined(BCM_88690_A0)
  29798     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM88690_A0r */
  29799         soc_block_list[61],
  29800         soc_iprocreg,
  29801         1,
  29802         0,
  29803         0x1802133c,
  29804         0,
  29805         0,
  29806         2,
  29807         soc_QSPI_MSPI_RXRAM31_BCM88690_A0r_fields,
  29808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29809         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29810         -1,
  29811         -1,
  29812     },
  29813 #endif /* chips */
  29814 
  29815 #if defined(BCM_88690_B0)
  29816     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM88690_B0r */
  29817         soc_block_list[61],
  29818         soc_iprocreg,
  29819         1,
  29820         0,
  29821         0x1802133c,
  29822         0,
  29823         0,
  29824         2,
  29825         soc_QSPI_MSPI_RXRAM31_BCM88690_B0r_fields,
  29826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29827         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29828         -1,
  29829         -1,
  29830     },
  29831 #endif /* chips */
  29832 
  29833 #if defined(BCM_88790_A0)
  29834     { /* SOC_REG_INT_QSPI_MSPI_RXRAM31_BCM88790_A0r */
  29835         soc_block_list[61],
  29836         soc_iprocreg,
  29837         1,
  29838         0,
  29839         0x1802133c,
  29840         0,
  29841         0,
  29842         2,
  29843         soc_QSPI_MSPI_RXRAM31_BCM88790_A0r_fields,
  29844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29845         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29846         -1,
  29847         -1,
  29848     },
  29849 #endif /* chips */
  29850 
  29851 #if defined(BCM_88675_A0)
  29852     { /* SOC_REG_INT_QSPI_MSPI_SPCR2r */
  29853         soc_block_list[61],
  29854         soc_iprocreg,
  29855         1,
  29856         0,
  29857         0x18021218,
  29858         0,
  29859         0,
  29860         9,
  29861         soc_QSPI_MSPI_SPCR2r_fields,
  29862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29863         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29864         -1,
  29865         -1,
  29866     },
  29867 #endif /* chips */
  29868 
  29869 #if defined(BCM_88675_A0)
  29870     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSBr */
  29871         soc_block_list[61],
  29872         soc_iprocreg,
  29873         1,
  29874         0,
  29875         0x18021200,
  29876         0,
  29877         0,
  29878         2,
  29879         soc_QSPI_MSPI_SPCR0_LSBr_fields,
  29880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29881         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29882         -1,
  29883         -1,
  29884     },
  29885 #endif /* chips */
  29886 
  29887 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  29888     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  29889     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  29890     defined(BCM_56260_B0)
  29891     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM53400_A0r */
  29892         soc_block_list[61],
  29893         soc_iprocreg,
  29894         1,
  29895         0,
  29896         0x18047200,
  29897         0,
  29898         0,
  29899         2,
  29900         soc_QSPI_MSPI_SPCR0_LSB_BCM53400_A0r_fields,
  29901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29902         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29903         -1,
  29904         -1,
  29905     },
  29906 #endif /* chips */
  29907 
  29908 #if defined(BCM_56370_A0)
  29909     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM56370_A0r */
  29910         soc_block_list[61],
  29911         soc_iprocreg,
  29912         1,
  29913         0,
  29914         0x15000200,
  29915         0,
  29916         0,
  29917         2,
  29918         soc_QSPI_MSPI_SPCR0_LSB_BCM53400_A0r_fields,
  29919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29920         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29921         -1,
  29922         -1,
  29923         3,
  29924     },
  29925 #endif /* chips */
  29926 
  29927 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  29928     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  29929     defined(BCM_56450_B1)
  29930     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM56450_A0r */
  29931         soc_block_list[61],
  29932         soc_iprocreg,
  29933         1,
  29934         0,
  29935         0x18027200,
  29936         0,
  29937         0,
  29938         2,
  29939         soc_QSPI_MSPI_SPCR0_LSB_BCM56450_A0r_fields,
  29940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29941         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29942         -1,
  29943         -1,
  29944     },
  29945 #endif /* chips */
  29946 
  29947 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  29948     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  29949     defined(BCM_56670_B0)
  29950     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM56560_A0r */
  29951         soc_block_list[61],
  29952         soc_iprocreg,
  29953         1,
  29954         0,
  29955         0x18021200,
  29956         0,
  29957         0,
  29958         2,
  29959         soc_QSPI_MSPI_SPCR0_LSB_BCM53400_A0r_fields,
  29960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29961         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29962         -1,
  29963         -1,
  29964     },
  29965 #endif /* chips */
  29966 
  29967 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  29968     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  29969     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  29970     defined(BCM_56980_B0)
  29971     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM56960_A0r */
  29972         soc_block_list[61],
  29973         soc_iprocreg,
  29974         1,
  29975         0,
  29976         0x18021200,
  29977         0,
  29978         0,
  29979         2,
  29980         soc_QSPI_MSPI_SPCR0_LSB_BCM53400_A0r_fields,
  29981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29982         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29983         -1,
  29984         -1,
  29985         3,
  29986     },
  29987 #endif /* chips */
  29988 
  29989 #if defined(BCM_88270_A0)
  29990     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM88270_A0r */
  29991         soc_block_list[61],
  29992         soc_iprocreg,
  29993         1,
  29994         0,
  29995         0x18021200,
  29996         0,
  29997         0,
  29998         2,
  29999         soc_QSPI_MSPI_SPCR0_LSB_BCM88270_A0r_fields,
  30000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30001         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30002         -1,
  30003         -1,
  30004     },
  30005 #endif /* chips */
  30006 
  30007 #if defined(BCM_88375_A0)
  30008     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM88375_A0r */
  30009         soc_block_list[61],
  30010         soc_iprocreg,
  30011         1,
  30012         0,
  30013         0x18021200,
  30014         0,
  30015         0,
  30016         2,
  30017         soc_QSPI_MSPI_SPCR0_LSB_BCM88375_A0r_fields,
  30018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30019         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30020         -1,
  30021         -1,
  30022     },
  30023 #endif /* chips */
  30024 
  30025 #if defined(BCM_88375_B0)
  30026     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM88375_B0r */
  30027         soc_block_list[61],
  30028         soc_iprocreg,
  30029         1,
  30030         0,
  30031         0x18021200,
  30032         0,
  30033         0,
  30034         2,
  30035         soc_QSPI_MSPI_SPCR0_LSB_BCM88375_B0r_fields,
  30036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30037         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30038         -1,
  30039         -1,
  30040     },
  30041 #endif /* chips */
  30042 
  30043 #if defined(BCM_88470_A0)
  30044     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM88470_A0r */
  30045         soc_block_list[61],
  30046         soc_iprocreg,
  30047         1,
  30048         0,
  30049         0x18021200,
  30050         0,
  30051         0,
  30052         2,
  30053         soc_QSPI_MSPI_SPCR0_LSB_BCM88470_A0r_fields,
  30054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30055         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30056         -1,
  30057         -1,
  30058     },
  30059 #endif /* chips */
  30060 
  30061 #if defined(BCM_88470_B0)
  30062     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM88470_B0r */
  30063         soc_block_list[61],
  30064         soc_iprocreg,
  30065         1,
  30066         0,
  30067         0x18021200,
  30068         0,
  30069         0,
  30070         2,
  30071         soc_QSPI_MSPI_SPCR0_LSB_BCM88470_B0r_fields,
  30072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30073         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30074         -1,
  30075         -1,
  30076     },
  30077 #endif /* chips */
  30078 
  30079 #if defined(BCM_88675_B0)
  30080     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM88675_B0r */
  30081         soc_block_list[61],
  30082         soc_iprocreg,
  30083         1,
  30084         0,
  30085         0x18021200,
  30086         0,
  30087         0,
  30088         2,
  30089         soc_QSPI_MSPI_SPCR0_LSB_BCM88675_B0r_fields,
  30090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30091         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30092         -1,
  30093         -1,
  30094     },
  30095 #endif /* chips */
  30096 
  30097 #if defined(BCM_88680_A0)
  30098     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM88680_A0r */
  30099         soc_block_list[61],
  30100         soc_iprocreg,
  30101         1,
  30102         0,
  30103         0x18021200,
  30104         0,
  30105         0,
  30106         2,
  30107         soc_QSPI_MSPI_SPCR0_LSB_BCM88680_A0r_fields,
  30108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30109         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30110         -1,
  30111         -1,
  30112     },
  30113 #endif /* chips */
  30114 
  30115 #if defined(BCM_88690_A0)
  30116     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM88690_A0r */
  30117         soc_block_list[61],
  30118         soc_iprocreg,
  30119         1,
  30120         0,
  30121         0x18021200,
  30122         0,
  30123         0,
  30124         2,
  30125         soc_QSPI_MSPI_SPCR0_LSB_BCM88690_A0r_fields,
  30126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30127         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30128         -1,
  30129         -1,
  30130     },
  30131 #endif /* chips */
  30132 
  30133 #if defined(BCM_88690_B0)
  30134     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM88690_B0r */
  30135         soc_block_list[61],
  30136         soc_iprocreg,
  30137         1,
  30138         0,
  30139         0x18021200,
  30140         0,
  30141         0,
  30142         2,
  30143         soc_QSPI_MSPI_SPCR0_LSB_BCM88690_B0r_fields,
  30144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30145         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30146         -1,
  30147         -1,
  30148     },
  30149 #endif /* chips */
  30150 
  30151 #if defined(BCM_88790_A0)
  30152     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_LSB_BCM88790_A0r */
  30153         soc_block_list[61],
  30154         soc_iprocreg,
  30155         1,
  30156         0,
  30157         0x18021200,
  30158         0,
  30159         0,
  30160         2,
  30161         soc_QSPI_MSPI_SPCR0_LSB_BCM88790_A0r_fields,
  30162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30163         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30164         -1,
  30165         -1,
  30166     },
  30167 #endif /* chips */
  30168 
  30169 #if defined(BCM_88675_A0)
  30170     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSBr */
  30171         soc_block_list[61],
  30172         soc_iprocreg,
  30173         1,
  30174         0,
  30175         0x18021204,
  30176         0,
  30177         0,
  30178         6,
  30179         soc_QSPI_MSPI_SPCR0_MSBr_fields,
  30180         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30181         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30182         -1,
  30183         -1,
  30184     },
  30185 #endif /* chips */
  30186 
  30187 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30188     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30189     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30190     defined(BCM_56260_B0)
  30191     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM53400_A0r */
  30192         soc_block_list[61],
  30193         soc_iprocreg,
  30194         1,
  30195         0,
  30196         0x18047204,
  30197         0,
  30198         0,
  30199         6,
  30200         soc_QSPI_MSPI_SPCR0_MSB_BCM53400_A0r_fields,
  30201         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30202         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30203         -1,
  30204         -1,
  30205     },
  30206 #endif /* chips */
  30207 
  30208 #if defined(BCM_56370_A0)
  30209     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM56370_A0r */
  30210         soc_block_list[61],
  30211         soc_iprocreg,
  30212         1,
  30213         0,
  30214         0x15000204,
  30215         0,
  30216         0,
  30217         6,
  30218         soc_QSPI_MSPI_SPCR0_MSB_BCM53400_A0r_fields,
  30219         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30220         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30221         -1,
  30222         -1,
  30223         3,
  30224     },
  30225 #endif /* chips */
  30226 
  30227 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  30228     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30229     defined(BCM_56450_B1)
  30230     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM56450_A0r */
  30231         soc_block_list[61],
  30232         soc_iprocreg,
  30233         1,
  30234         0,
  30235         0x18027204,
  30236         0,
  30237         0,
  30238         6,
  30239         soc_QSPI_MSPI_SPCR0_MSB_BCM56450_A0r_fields,
  30240         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30241         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30242         -1,
  30243         -1,
  30244     },
  30245 #endif /* chips */
  30246 
  30247 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  30248     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  30249     defined(BCM_56670_B0)
  30250     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM56560_A0r */
  30251         soc_block_list[61],
  30252         soc_iprocreg,
  30253         1,
  30254         0,
  30255         0x18021204,
  30256         0,
  30257         0,
  30258         6,
  30259         soc_QSPI_MSPI_SPCR0_MSB_BCM53400_A0r_fields,
  30260         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30261         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30262         -1,
  30263         -1,
  30264     },
  30265 #endif /* chips */
  30266 
  30267 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  30268     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  30269     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  30270     defined(BCM_56980_B0)
  30271     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM56960_A0r */
  30272         soc_block_list[61],
  30273         soc_iprocreg,
  30274         1,
  30275         0,
  30276         0x18021204,
  30277         0,
  30278         0,
  30279         6,
  30280         soc_QSPI_MSPI_SPCR0_MSB_BCM53400_A0r_fields,
  30281         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30282         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30283         -1,
  30284         -1,
  30285         3,
  30286     },
  30287 #endif /* chips */
  30288 
  30289 #if defined(BCM_88270_A0)
  30290     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM88270_A0r */
  30291         soc_block_list[61],
  30292         soc_iprocreg,
  30293         1,
  30294         0,
  30295         0x18021204,
  30296         0,
  30297         0,
  30298         6,
  30299         soc_QSPI_MSPI_SPCR0_MSB_BCM88270_A0r_fields,
  30300         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30301         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30302         -1,
  30303         -1,
  30304     },
  30305 #endif /* chips */
  30306 
  30307 #if defined(BCM_88375_A0)
  30308     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM88375_A0r */
  30309         soc_block_list[61],
  30310         soc_iprocreg,
  30311         1,
  30312         0,
  30313         0x18021204,
  30314         0,
  30315         0,
  30316         6,
  30317         soc_QSPI_MSPI_SPCR0_MSB_BCM88375_A0r_fields,
  30318         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30319         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30320         -1,
  30321         -1,
  30322     },
  30323 #endif /* chips */
  30324 
  30325 #if defined(BCM_88375_B0)
  30326     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM88375_B0r */
  30327         soc_block_list[61],
  30328         soc_iprocreg,
  30329         1,
  30330         0,
  30331         0x18021204,
  30332         0,
  30333         0,
  30334         6,
  30335         soc_QSPI_MSPI_SPCR0_MSB_BCM88375_B0r_fields,
  30336         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30337         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30338         -1,
  30339         -1,
  30340     },
  30341 #endif /* chips */
  30342 
  30343 #if defined(BCM_88470_A0)
  30344     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM88470_A0r */
  30345         soc_block_list[61],
  30346         soc_iprocreg,
  30347         1,
  30348         0,
  30349         0x18021204,
  30350         0,
  30351         0,
  30352         6,
  30353         soc_QSPI_MSPI_SPCR0_MSB_BCM88470_A0r_fields,
  30354         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30355         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30356         -1,
  30357         -1,
  30358     },
  30359 #endif /* chips */
  30360 
  30361 #if defined(BCM_88470_B0)
  30362     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM88470_B0r */
  30363         soc_block_list[61],
  30364         soc_iprocreg,
  30365         1,
  30366         0,
  30367         0x18021204,
  30368         0,
  30369         0,
  30370         6,
  30371         soc_QSPI_MSPI_SPCR0_MSB_BCM88470_B0r_fields,
  30372         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30373         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30374         -1,
  30375         -1,
  30376     },
  30377 #endif /* chips */
  30378 
  30379 #if defined(BCM_88675_B0)
  30380     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM88675_B0r */
  30381         soc_block_list[61],
  30382         soc_iprocreg,
  30383         1,
  30384         0,
  30385         0x18021204,
  30386         0,
  30387         0,
  30388         6,
  30389         soc_QSPI_MSPI_SPCR0_MSB_BCM88675_B0r_fields,
  30390         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30391         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30392         -1,
  30393         -1,
  30394     },
  30395 #endif /* chips */
  30396 
  30397 #if defined(BCM_88680_A0)
  30398     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM88680_A0r */
  30399         soc_block_list[61],
  30400         soc_iprocreg,
  30401         1,
  30402         0,
  30403         0x18021204,
  30404         0,
  30405         0,
  30406         6,
  30407         soc_QSPI_MSPI_SPCR0_MSB_BCM88680_A0r_fields,
  30408         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30409         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30410         -1,
  30411         -1,
  30412     },
  30413 #endif /* chips */
  30414 
  30415 #if defined(BCM_88690_A0)
  30416     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM88690_A0r */
  30417         soc_block_list[61],
  30418         soc_iprocreg,
  30419         1,
  30420         0,
  30421         0x18021204,
  30422         0,
  30423         0,
  30424         6,
  30425         soc_QSPI_MSPI_SPCR0_MSB_BCM88690_A0r_fields,
  30426         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30428         -1,
  30429         -1,
  30430     },
  30431 #endif /* chips */
  30432 
  30433 #if defined(BCM_88690_B0)
  30434     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM88690_B0r */
  30435         soc_block_list[61],
  30436         soc_iprocreg,
  30437         1,
  30438         0,
  30439         0x18021204,
  30440         0,
  30441         0,
  30442         6,
  30443         soc_QSPI_MSPI_SPCR0_MSB_BCM88690_B0r_fields,
  30444         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30446         -1,
  30447         -1,
  30448     },
  30449 #endif /* chips */
  30450 
  30451 #if defined(BCM_88790_A0)
  30452     { /* SOC_REG_INT_QSPI_MSPI_SPCR0_MSB_BCM88790_A0r */
  30453         soc_block_list[61],
  30454         soc_iprocreg,
  30455         1,
  30456         0,
  30457         0x18021204,
  30458         0,
  30459         0,
  30460         6,
  30461         soc_QSPI_MSPI_SPCR0_MSB_BCM88790_A0r_fields,
  30462         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  30463         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30464         -1,
  30465         -1,
  30466     },
  30467 #endif /* chips */
  30468 
  30469 #if defined(BCM_88675_A0)
  30470     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSBr */
  30471         soc_block_list[61],
  30472         soc_iprocreg,
  30473         1,
  30474         0,
  30475         0x18021208,
  30476         0,
  30477         0,
  30478         2,
  30479         soc_QSPI_MSPI_SPCR1_LSBr_fields,
  30480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30481         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30482         -1,
  30483         -1,
  30484     },
  30485 #endif /* chips */
  30486 
  30487 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30488     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30489     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30490     defined(BCM_56260_B0)
  30491     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM53400_A0r */
  30492         soc_block_list[61],
  30493         soc_iprocreg,
  30494         1,
  30495         0,
  30496         0x18047208,
  30497         0,
  30498         0,
  30499         2,
  30500         soc_QSPI_MSPI_SPCR1_LSB_BCM53400_A0r_fields,
  30501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30502         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30503         -1,
  30504         -1,
  30505     },
  30506 #endif /* chips */
  30507 
  30508 #if defined(BCM_56370_A0)
  30509     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM56370_A0r */
  30510         soc_block_list[61],
  30511         soc_iprocreg,
  30512         1,
  30513         0,
  30514         0x15000208,
  30515         0,
  30516         0,
  30517         2,
  30518         soc_QSPI_MSPI_SPCR1_LSB_BCM53400_A0r_fields,
  30519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30520         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30521         -1,
  30522         -1,
  30523         3,
  30524     },
  30525 #endif /* chips */
  30526 
  30527 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  30528     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30529     defined(BCM_56450_B1)
  30530     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM56450_A0r */
  30531         soc_block_list[61],
  30532         soc_iprocreg,
  30533         1,
  30534         0,
  30535         0x18027208,
  30536         0,
  30537         0,
  30538         2,
  30539         soc_QSPI_MSPI_SPCR1_LSB_BCM56450_A0r_fields,
  30540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30542         -1,
  30543         -1,
  30544     },
  30545 #endif /* chips */
  30546 
  30547 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  30548     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  30549     defined(BCM_56670_B0)
  30550     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM56560_A0r */
  30551         soc_block_list[61],
  30552         soc_iprocreg,
  30553         1,
  30554         0,
  30555         0x18021208,
  30556         0,
  30557         0,
  30558         2,
  30559         soc_QSPI_MSPI_SPCR1_LSB_BCM53400_A0r_fields,
  30560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30561         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30562         -1,
  30563         -1,
  30564     },
  30565 #endif /* chips */
  30566 
  30567 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  30568     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  30569     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  30570     defined(BCM_56980_B0)
  30571     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM56960_A0r */
  30572         soc_block_list[61],
  30573         soc_iprocreg,
  30574         1,
  30575         0,
  30576         0x18021208,
  30577         0,
  30578         0,
  30579         2,
  30580         soc_QSPI_MSPI_SPCR1_LSB_BCM53400_A0r_fields,
  30581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30582         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30583         -1,
  30584         -1,
  30585         3,
  30586     },
  30587 #endif /* chips */
  30588 
  30589 #if defined(BCM_88270_A0)
  30590     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM88270_A0r */
  30591         soc_block_list[61],
  30592         soc_iprocreg,
  30593         1,
  30594         0,
  30595         0x18021208,
  30596         0,
  30597         0,
  30598         2,
  30599         soc_QSPI_MSPI_SPCR1_LSB_BCM88270_A0r_fields,
  30600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30601         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30602         -1,
  30603         -1,
  30604     },
  30605 #endif /* chips */
  30606 
  30607 #if defined(BCM_88375_A0)
  30608     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM88375_A0r */
  30609         soc_block_list[61],
  30610         soc_iprocreg,
  30611         1,
  30612         0,
  30613         0x18021208,
  30614         0,
  30615         0,
  30616         2,
  30617         soc_QSPI_MSPI_SPCR1_LSB_BCM88375_A0r_fields,
  30618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30619         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30620         -1,
  30621         -1,
  30622     },
  30623 #endif /* chips */
  30624 
  30625 #if defined(BCM_88375_B0)
  30626     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM88375_B0r */
  30627         soc_block_list[61],
  30628         soc_iprocreg,
  30629         1,
  30630         0,
  30631         0x18021208,
  30632         0,
  30633         0,
  30634         2,
  30635         soc_QSPI_MSPI_SPCR1_LSB_BCM88375_B0r_fields,
  30636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30637         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30638         -1,
  30639         -1,
  30640     },
  30641 #endif /* chips */
  30642 
  30643 #if defined(BCM_88470_A0)
  30644     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM88470_A0r */
  30645         soc_block_list[61],
  30646         soc_iprocreg,
  30647         1,
  30648         0,
  30649         0x18021208,
  30650         0,
  30651         0,
  30652         2,
  30653         soc_QSPI_MSPI_SPCR1_LSB_BCM88470_A0r_fields,
  30654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30655         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30656         -1,
  30657         -1,
  30658     },
  30659 #endif /* chips */
  30660 
  30661 #if defined(BCM_88470_B0)
  30662     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM88470_B0r */
  30663         soc_block_list[61],
  30664         soc_iprocreg,
  30665         1,
  30666         0,
  30667         0x18021208,
  30668         0,
  30669         0,
  30670         2,
  30671         soc_QSPI_MSPI_SPCR1_LSB_BCM88470_B0r_fields,
  30672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30673         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30674         -1,
  30675         -1,
  30676     },
  30677 #endif /* chips */
  30678 
  30679 #if defined(BCM_88675_B0)
  30680     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM88675_B0r */
  30681         soc_block_list[61],
  30682         soc_iprocreg,
  30683         1,
  30684         0,
  30685         0x18021208,
  30686         0,
  30687         0,
  30688         2,
  30689         soc_QSPI_MSPI_SPCR1_LSB_BCM88675_B0r_fields,
  30690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30691         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30692         -1,
  30693         -1,
  30694     },
  30695 #endif /* chips */
  30696 
  30697 #if defined(BCM_88680_A0)
  30698     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM88680_A0r */
  30699         soc_block_list[61],
  30700         soc_iprocreg,
  30701         1,
  30702         0,
  30703         0x18021208,
  30704         0,
  30705         0,
  30706         2,
  30707         soc_QSPI_MSPI_SPCR1_LSB_BCM88680_A0r_fields,
  30708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30709         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30710         -1,
  30711         -1,
  30712     },
  30713 #endif /* chips */
  30714 
  30715 #if defined(BCM_88690_A0)
  30716     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM88690_A0r */
  30717         soc_block_list[61],
  30718         soc_iprocreg,
  30719         1,
  30720         0,
  30721         0x18021208,
  30722         0,
  30723         0,
  30724         2,
  30725         soc_QSPI_MSPI_SPCR1_LSB_BCM88690_A0r_fields,
  30726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30727         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30728         -1,
  30729         -1,
  30730     },
  30731 #endif /* chips */
  30732 
  30733 #if defined(BCM_88690_B0)
  30734     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM88690_B0r */
  30735         soc_block_list[61],
  30736         soc_iprocreg,
  30737         1,
  30738         0,
  30739         0x18021208,
  30740         0,
  30741         0,
  30742         2,
  30743         soc_QSPI_MSPI_SPCR1_LSB_BCM88690_B0r_fields,
  30744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30745         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30746         -1,
  30747         -1,
  30748     },
  30749 #endif /* chips */
  30750 
  30751 #if defined(BCM_88790_A0)
  30752     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_LSB_BCM88790_A0r */
  30753         soc_block_list[61],
  30754         soc_iprocreg,
  30755         1,
  30756         0,
  30757         0x18021208,
  30758         0,
  30759         0,
  30760         2,
  30761         soc_QSPI_MSPI_SPCR1_LSB_BCM88790_A0r_fields,
  30762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30763         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30764         -1,
  30765         -1,
  30766     },
  30767 #endif /* chips */
  30768 
  30769 #if defined(BCM_88675_A0)
  30770     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSBr */
  30771         soc_block_list[61],
  30772         soc_iprocreg,
  30773         1,
  30774         0,
  30775         0x1802120c,
  30776         0,
  30777         0,
  30778         2,
  30779         soc_QSPI_MSPI_SPCR1_MSBr_fields,
  30780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30781         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30782         -1,
  30783         -1,
  30784     },
  30785 #endif /* chips */
  30786 
  30787 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  30788     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  30789     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  30790     defined(BCM_56260_B0)
  30791     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM53400_A0r */
  30792         soc_block_list[61],
  30793         soc_iprocreg,
  30794         1,
  30795         0,
  30796         0x1804720c,
  30797         0,
  30798         0,
  30799         2,
  30800         soc_QSPI_MSPI_SPCR1_MSB_BCM53400_A0r_fields,
  30801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30802         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30803         -1,
  30804         -1,
  30805     },
  30806 #endif /* chips */
  30807 
  30808 #if defined(BCM_56370_A0)
  30809     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM56370_A0r */
  30810         soc_block_list[61],
  30811         soc_iprocreg,
  30812         1,
  30813         0,
  30814         0x1500020c,
  30815         0,
  30816         0,
  30817         2,
  30818         soc_QSPI_MSPI_SPCR1_MSB_BCM53400_A0r_fields,
  30819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30820         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30821         -1,
  30822         -1,
  30823         3,
  30824     },
  30825 #endif /* chips */
  30826 
  30827 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  30828     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  30829     defined(BCM_56450_B1)
  30830     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM56450_A0r */
  30831         soc_block_list[61],
  30832         soc_iprocreg,
  30833         1,
  30834         0,
  30835         0x1802720c,
  30836         0,
  30837         0,
  30838         2,
  30839         soc_QSPI_MSPI_SPCR1_MSB_BCM56450_A0r_fields,
  30840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30842         -1,
  30843         -1,
  30844     },
  30845 #endif /* chips */
  30846 
  30847 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  30848     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  30849     defined(BCM_56670_B0)
  30850     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM56560_A0r */
  30851         soc_block_list[61],
  30852         soc_iprocreg,
  30853         1,
  30854         0,
  30855         0x1802120c,
  30856         0,
  30857         0,
  30858         2,
  30859         soc_QSPI_MSPI_SPCR1_MSB_BCM53400_A0r_fields,
  30860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30861         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30862         -1,
  30863         -1,
  30864     },
  30865 #endif /* chips */
  30866 
  30867 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  30868     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  30869     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  30870     defined(BCM_56980_B0)
  30871     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM56960_A0r */
  30872         soc_block_list[61],
  30873         soc_iprocreg,
  30874         1,
  30875         0,
  30876         0x1802120c,
  30877         0,
  30878         0,
  30879         2,
  30880         soc_QSPI_MSPI_SPCR1_MSB_BCM53400_A0r_fields,
  30881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30882         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30883         -1,
  30884         -1,
  30885         3,
  30886     },
  30887 #endif /* chips */
  30888 
  30889 #if defined(BCM_88270_A0)
  30890     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM88270_A0r */
  30891         soc_block_list[61],
  30892         soc_iprocreg,
  30893         1,
  30894         0,
  30895         0x1802120c,
  30896         0,
  30897         0,
  30898         2,
  30899         soc_QSPI_MSPI_SPCR1_MSB_BCM88270_A0r_fields,
  30900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30901         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30902         -1,
  30903         -1,
  30904     },
  30905 #endif /* chips */
  30906 
  30907 #if defined(BCM_88375_A0)
  30908     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM88375_A0r */
  30909         soc_block_list[61],
  30910         soc_iprocreg,
  30911         1,
  30912         0,
  30913         0x1802120c,
  30914         0,
  30915         0,
  30916         2,
  30917         soc_QSPI_MSPI_SPCR1_MSB_BCM88375_A0r_fields,
  30918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30919         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30920         -1,
  30921         -1,
  30922     },
  30923 #endif /* chips */
  30924 
  30925 #if defined(BCM_88375_B0)
  30926     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM88375_B0r */
  30927         soc_block_list[61],
  30928         soc_iprocreg,
  30929         1,
  30930         0,
  30931         0x1802120c,
  30932         0,
  30933         0,
  30934         2,
  30935         soc_QSPI_MSPI_SPCR1_MSB_BCM88375_B0r_fields,
  30936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30937         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30938         -1,
  30939         -1,
  30940     },
  30941 #endif /* chips */
  30942 
  30943 #if defined(BCM_88470_A0)
  30944     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM88470_A0r */
  30945         soc_block_list[61],
  30946         soc_iprocreg,
  30947         1,
  30948         0,
  30949         0x1802120c,
  30950         0,
  30951         0,
  30952         2,
  30953         soc_QSPI_MSPI_SPCR1_MSB_BCM88470_A0r_fields,
  30954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30956         -1,
  30957         -1,
  30958     },
  30959 #endif /* chips */
  30960 
  30961 #if defined(BCM_88470_B0)
  30962     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM88470_B0r */
  30963         soc_block_list[61],
  30964         soc_iprocreg,
  30965         1,
  30966         0,
  30967         0x1802120c,
  30968         0,
  30969         0,
  30970         2,
  30971         soc_QSPI_MSPI_SPCR1_MSB_BCM88470_B0r_fields,
  30972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30973         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30974         -1,
  30975         -1,
  30976     },
  30977 #endif /* chips */
  30978 
  30979 #if defined(BCM_88675_B0)
  30980     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM88675_B0r */
  30981         soc_block_list[61],
  30982         soc_iprocreg,
  30983         1,
  30984         0,
  30985         0x1802120c,
  30986         0,
  30987         0,
  30988         2,
  30989         soc_QSPI_MSPI_SPCR1_MSB_BCM88675_B0r_fields,
  30990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30991         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30992         -1,
  30993         -1,
  30994     },
  30995 #endif /* chips */
  30996 
  30997 #if defined(BCM_88680_A0)
  30998     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM88680_A0r */
  30999         soc_block_list[61],
  31000         soc_iprocreg,
  31001         1,
  31002         0,
  31003         0x1802120c,
  31004         0,
  31005         0,
  31006         2,
  31007         soc_QSPI_MSPI_SPCR1_MSB_BCM88680_A0r_fields,
  31008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31009         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31010         -1,
  31011         -1,
  31012     },
  31013 #endif /* chips */
  31014 
  31015 #if defined(BCM_88690_A0)
  31016     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM88690_A0r */
  31017         soc_block_list[61],
  31018         soc_iprocreg,
  31019         1,
  31020         0,
  31021         0x1802120c,
  31022         0,
  31023         0,
  31024         2,
  31025         soc_QSPI_MSPI_SPCR1_MSB_BCM88690_A0r_fields,
  31026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31028         -1,
  31029         -1,
  31030     },
  31031 #endif /* chips */
  31032 
  31033 #if defined(BCM_88690_B0)
  31034     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM88690_B0r */
  31035         soc_block_list[61],
  31036         soc_iprocreg,
  31037         1,
  31038         0,
  31039         0x1802120c,
  31040         0,
  31041         0,
  31042         2,
  31043         soc_QSPI_MSPI_SPCR1_MSB_BCM88690_B0r_fields,
  31044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31045         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31046         -1,
  31047         -1,
  31048     },
  31049 #endif /* chips */
  31050 
  31051 #if defined(BCM_88790_A0)
  31052     { /* SOC_REG_INT_QSPI_MSPI_SPCR1_MSB_BCM88790_A0r */
  31053         soc_block_list[61],
  31054         soc_iprocreg,
  31055         1,
  31056         0,
  31057         0x1802120c,
  31058         0,
  31059         0,
  31060         2,
  31061         soc_QSPI_MSPI_SPCR1_MSB_BCM88790_A0r_fields,
  31062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31063         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31064         -1,
  31065         -1,
  31066     },
  31067 #endif /* chips */
  31068 
  31069 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31070     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31071     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31072     defined(BCM_56260_B0)
  31073     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM53400_A0r */
  31074         soc_block_list[61],
  31075         soc_iprocreg,
  31076         1,
  31077         0,
  31078         0x18047218,
  31079         0,
  31080         0,
  31081         9,
  31082         soc_QSPI_MSPI_SPCR2_BCM53400_A0r_fields,
  31083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31084         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31085         -1,
  31086         -1,
  31087     },
  31088 #endif /* chips */
  31089 
  31090 #if defined(BCM_56370_A0)
  31091     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM56370_A0r */
  31092         soc_block_list[61],
  31093         soc_iprocreg,
  31094         1,
  31095         0,
  31096         0x15000218,
  31097         0,
  31098         0,
  31099         9,
  31100         soc_QSPI_MSPI_SPCR2_BCM53400_A0r_fields,
  31101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31102         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31103         -1,
  31104         -1,
  31105         3,
  31106     },
  31107 #endif /* chips */
  31108 
  31109 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  31110     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  31111     defined(BCM_56450_B1)
  31112     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM56450_A0r */
  31113         soc_block_list[61],
  31114         soc_iprocreg,
  31115         1,
  31116         0,
  31117         0x18027218,
  31118         0,
  31119         0,
  31120         9,
  31121         soc_QSPI_MSPI_SPCR2_BCM56450_A0r_fields,
  31122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31123         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31124         -1,
  31125         -1,
  31126     },
  31127 #endif /* chips */
  31128 
  31129 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  31130     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  31131     defined(BCM_56670_B0)
  31132     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM56560_A0r */
  31133         soc_block_list[61],
  31134         soc_iprocreg,
  31135         1,
  31136         0,
  31137         0x18021218,
  31138         0,
  31139         0,
  31140         9,
  31141         soc_QSPI_MSPI_SPCR2_BCM53400_A0r_fields,
  31142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31143         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31144         -1,
  31145         -1,
  31146     },
  31147 #endif /* chips */
  31148 
  31149 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  31150     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  31151     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  31152     defined(BCM_56980_B0)
  31153     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM56960_A0r */
  31154         soc_block_list[61],
  31155         soc_iprocreg,
  31156         1,
  31157         0,
  31158         0x18021218,
  31159         0,
  31160         0,
  31161         9,
  31162         soc_QSPI_MSPI_SPCR2_BCM53400_A0r_fields,
  31163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31164         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31165         -1,
  31166         -1,
  31167         3,
  31168     },
  31169 #endif /* chips */
  31170 
  31171 #if defined(BCM_88270_A0)
  31172     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM88270_A0r */
  31173         soc_block_list[61],
  31174         soc_iprocreg,
  31175         1,
  31176         0,
  31177         0x18021218,
  31178         0,
  31179         0,
  31180         9,
  31181         soc_QSPI_MSPI_SPCR2_BCM88270_A0r_fields,
  31182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31183         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31184         -1,
  31185         -1,
  31186     },
  31187 #endif /* chips */
  31188 
  31189 #if defined(BCM_88375_A0)
  31190     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM88375_A0r */
  31191         soc_block_list[61],
  31192         soc_iprocreg,
  31193         1,
  31194         0,
  31195         0x18021218,
  31196         0,
  31197         0,
  31198         9,
  31199         soc_QSPI_MSPI_SPCR2_BCM88375_A0r_fields,
  31200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31201         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31202         -1,
  31203         -1,
  31204     },
  31205 #endif /* chips */
  31206 
  31207 #if defined(BCM_88375_B0)
  31208     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM88375_B0r */
  31209         soc_block_list[61],
  31210         soc_iprocreg,
  31211         1,
  31212         0,
  31213         0x18021218,
  31214         0,
  31215         0,
  31216         9,
  31217         soc_QSPI_MSPI_SPCR2_BCM88375_B0r_fields,
  31218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31219         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31220         -1,
  31221         -1,
  31222     },
  31223 #endif /* chips */
  31224 
  31225 #if defined(BCM_88470_A0)
  31226     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM88470_A0r */
  31227         soc_block_list[61],
  31228         soc_iprocreg,
  31229         1,
  31230         0,
  31231         0x18021218,
  31232         0,
  31233         0,
  31234         9,
  31235         soc_QSPI_MSPI_SPCR2_BCM88470_A0r_fields,
  31236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31237         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31238         -1,
  31239         -1,
  31240     },
  31241 #endif /* chips */
  31242 
  31243 #if defined(BCM_88470_B0)
  31244     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM88470_B0r */
  31245         soc_block_list[61],
  31246         soc_iprocreg,
  31247         1,
  31248         0,
  31249         0x18021218,
  31250         0,
  31251         0,
  31252         9,
  31253         soc_QSPI_MSPI_SPCR2_BCM88470_B0r_fields,
  31254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31255         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31256         -1,
  31257         -1,
  31258     },
  31259 #endif /* chips */
  31260 
  31261 #if defined(BCM_88675_B0)
  31262     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM88675_B0r */
  31263         soc_block_list[61],
  31264         soc_iprocreg,
  31265         1,
  31266         0,
  31267         0x18021218,
  31268         0,
  31269         0,
  31270         9,
  31271         soc_QSPI_MSPI_SPCR2_BCM88675_B0r_fields,
  31272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31273         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31274         -1,
  31275         -1,
  31276     },
  31277 #endif /* chips */
  31278 
  31279 #if defined(BCM_88680_A0)
  31280     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM88680_A0r */
  31281         soc_block_list[61],
  31282         soc_iprocreg,
  31283         1,
  31284         0,
  31285         0x18021218,
  31286         0,
  31287         0,
  31288         9,
  31289         soc_QSPI_MSPI_SPCR2_BCM88680_A0r_fields,
  31290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31291         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31292         -1,
  31293         -1,
  31294     },
  31295 #endif /* chips */
  31296 
  31297 #if defined(BCM_88690_A0)
  31298     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM88690_A0r */
  31299         soc_block_list[61],
  31300         soc_iprocreg,
  31301         1,
  31302         0,
  31303         0x18021218,
  31304         0,
  31305         0,
  31306         9,
  31307         soc_QSPI_MSPI_SPCR2_BCM88690_A0r_fields,
  31308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31309         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31310         -1,
  31311         -1,
  31312     },
  31313 #endif /* chips */
  31314 
  31315 #if defined(BCM_88690_B0)
  31316     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM88690_B0r */
  31317         soc_block_list[61],
  31318         soc_iprocreg,
  31319         1,
  31320         0,
  31321         0x18021218,
  31322         0,
  31323         0,
  31324         9,
  31325         soc_QSPI_MSPI_SPCR2_BCM88690_B0r_fields,
  31326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31327         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31328         -1,
  31329         -1,
  31330     },
  31331 #endif /* chips */
  31332 
  31333 #if defined(BCM_88790_A0)
  31334     { /* SOC_REG_INT_QSPI_MSPI_SPCR2_BCM88790_A0r */
  31335         soc_block_list[61],
  31336         soc_iprocreg,
  31337         1,
  31338         0,
  31339         0x18021218,
  31340         0,
  31341         0,
  31342         9,
  31343         soc_QSPI_MSPI_SPCR2_BCM88790_A0r_fields,
  31344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31346         -1,
  31347         -1,
  31348     },
  31349 #endif /* chips */
  31350 
  31351 #if defined(BCM_88675_A0)
  31352     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00r */
  31353         soc_block_list[61],
  31354         soc_iprocreg,
  31355         1,
  31356         0,
  31357         0x18021240,
  31358         0,
  31359         0,
  31360         2,
  31361         soc_QSPI_MSPI_TXRAM00r_fields,
  31362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31363         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31364         -1,
  31365         -1,
  31366     },
  31367 #endif /* chips */
  31368 
  31369 #if defined(BCM_88675_A0)
  31370     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01r */
  31371         soc_block_list[61],
  31372         soc_iprocreg,
  31373         1,
  31374         0,
  31375         0x18021244,
  31376         0,
  31377         0,
  31378         2,
  31379         soc_QSPI_MSPI_TXRAM01r_fields,
  31380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31382         -1,
  31383         -1,
  31384     },
  31385 #endif /* chips */
  31386 
  31387 #if defined(BCM_88675_A0)
  31388     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02r */
  31389         soc_block_list[61],
  31390         soc_iprocreg,
  31391         1,
  31392         0,
  31393         0x18021248,
  31394         0,
  31395         0,
  31396         2,
  31397         soc_QSPI_MSPI_TXRAM02r_fields,
  31398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31399         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31400         -1,
  31401         -1,
  31402     },
  31403 #endif /* chips */
  31404 
  31405 #if defined(BCM_88675_A0)
  31406     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03r */
  31407         soc_block_list[61],
  31408         soc_iprocreg,
  31409         1,
  31410         0,
  31411         0x1802124c,
  31412         0,
  31413         0,
  31414         2,
  31415         soc_QSPI_MSPI_TXRAM03r_fields,
  31416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31418         -1,
  31419         -1,
  31420     },
  31421 #endif /* chips */
  31422 
  31423 #if defined(BCM_88675_A0)
  31424     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04r */
  31425         soc_block_list[61],
  31426         soc_iprocreg,
  31427         1,
  31428         0,
  31429         0x18021250,
  31430         0,
  31431         0,
  31432         2,
  31433         soc_QSPI_MSPI_TXRAM04r_fields,
  31434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31435         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31436         -1,
  31437         -1,
  31438     },
  31439 #endif /* chips */
  31440 
  31441 #if defined(BCM_88675_A0)
  31442     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05r */
  31443         soc_block_list[61],
  31444         soc_iprocreg,
  31445         1,
  31446         0,
  31447         0x18021254,
  31448         0,
  31449         0,
  31450         2,
  31451         soc_QSPI_MSPI_TXRAM05r_fields,
  31452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31454         -1,
  31455         -1,
  31456     },
  31457 #endif /* chips */
  31458 
  31459 #if defined(BCM_88675_A0)
  31460     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06r */
  31461         soc_block_list[61],
  31462         soc_iprocreg,
  31463         1,
  31464         0,
  31465         0x18021258,
  31466         0,
  31467         0,
  31468         2,
  31469         soc_QSPI_MSPI_TXRAM06r_fields,
  31470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31471         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31472         -1,
  31473         -1,
  31474     },
  31475 #endif /* chips */
  31476 
  31477 #if defined(BCM_88675_A0)
  31478     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07r */
  31479         soc_block_list[61],
  31480         soc_iprocreg,
  31481         1,
  31482         0,
  31483         0x1802125c,
  31484         0,
  31485         0,
  31486         2,
  31487         soc_QSPI_MSPI_TXRAM07r_fields,
  31488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31490         -1,
  31491         -1,
  31492     },
  31493 #endif /* chips */
  31494 
  31495 #if defined(BCM_88675_A0)
  31496     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08r */
  31497         soc_block_list[61],
  31498         soc_iprocreg,
  31499         1,
  31500         0,
  31501         0x18021260,
  31502         0,
  31503         0,
  31504         2,
  31505         soc_QSPI_MSPI_TXRAM08r_fields,
  31506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31507         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31508         -1,
  31509         -1,
  31510     },
  31511 #endif /* chips */
  31512 
  31513 #if defined(BCM_88675_A0)
  31514     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09r */
  31515         soc_block_list[61],
  31516         soc_iprocreg,
  31517         1,
  31518         0,
  31519         0x18021264,
  31520         0,
  31521         0,
  31522         2,
  31523         soc_QSPI_MSPI_TXRAM09r_fields,
  31524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31526         -1,
  31527         -1,
  31528     },
  31529 #endif /* chips */
  31530 
  31531 #if defined(BCM_88675_A0)
  31532     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10r */
  31533         soc_block_list[61],
  31534         soc_iprocreg,
  31535         1,
  31536         0,
  31537         0x18021268,
  31538         0,
  31539         0,
  31540         2,
  31541         soc_QSPI_MSPI_TXRAM10r_fields,
  31542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31544         -1,
  31545         -1,
  31546     },
  31547 #endif /* chips */
  31548 
  31549 #if defined(BCM_88675_A0)
  31550     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11r */
  31551         soc_block_list[61],
  31552         soc_iprocreg,
  31553         1,
  31554         0,
  31555         0x1802126c,
  31556         0,
  31557         0,
  31558         2,
  31559         soc_QSPI_MSPI_TXRAM11r_fields,
  31560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31561         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31562         -1,
  31563         -1,
  31564     },
  31565 #endif /* chips */
  31566 
  31567 #if defined(BCM_88675_A0)
  31568     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12r */
  31569         soc_block_list[61],
  31570         soc_iprocreg,
  31571         1,
  31572         0,
  31573         0x18021270,
  31574         0,
  31575         0,
  31576         2,
  31577         soc_QSPI_MSPI_TXRAM12r_fields,
  31578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31579         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31580         -1,
  31581         -1,
  31582     },
  31583 #endif /* chips */
  31584 
  31585 #if defined(BCM_88675_A0)
  31586     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13r */
  31587         soc_block_list[61],
  31588         soc_iprocreg,
  31589         1,
  31590         0,
  31591         0x18021274,
  31592         0,
  31593         0,
  31594         2,
  31595         soc_QSPI_MSPI_TXRAM13r_fields,
  31596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31597         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31598         -1,
  31599         -1,
  31600     },
  31601 #endif /* chips */
  31602 
  31603 #if defined(BCM_88675_A0)
  31604     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14r */
  31605         soc_block_list[61],
  31606         soc_iprocreg,
  31607         1,
  31608         0,
  31609         0x18021278,
  31610         0,
  31611         0,
  31612         2,
  31613         soc_QSPI_MSPI_TXRAM14r_fields,
  31614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31615         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31616         -1,
  31617         -1,
  31618     },
  31619 #endif /* chips */
  31620 
  31621 #if defined(BCM_88675_A0)
  31622     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15r */
  31623         soc_block_list[61],
  31624         soc_iprocreg,
  31625         1,
  31626         0,
  31627         0x1802127c,
  31628         0,
  31629         0,
  31630         2,
  31631         soc_QSPI_MSPI_TXRAM15r_fields,
  31632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31633         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31634         -1,
  31635         -1,
  31636     },
  31637 #endif /* chips */
  31638 
  31639 #if defined(BCM_88675_A0)
  31640     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16r */
  31641         soc_block_list[61],
  31642         soc_iprocreg,
  31643         1,
  31644         0,
  31645         0x18021280,
  31646         0,
  31647         0,
  31648         2,
  31649         soc_QSPI_MSPI_TXRAM16r_fields,
  31650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31651         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31652         -1,
  31653         -1,
  31654     },
  31655 #endif /* chips */
  31656 
  31657 #if defined(BCM_88675_A0)
  31658     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17r */
  31659         soc_block_list[61],
  31660         soc_iprocreg,
  31661         1,
  31662         0,
  31663         0x18021284,
  31664         0,
  31665         0,
  31666         2,
  31667         soc_QSPI_MSPI_TXRAM17r_fields,
  31668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31670         -1,
  31671         -1,
  31672     },
  31673 #endif /* chips */
  31674 
  31675 #if defined(BCM_88675_A0)
  31676     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18r */
  31677         soc_block_list[61],
  31678         soc_iprocreg,
  31679         1,
  31680         0,
  31681         0x18021288,
  31682         0,
  31683         0,
  31684         2,
  31685         soc_QSPI_MSPI_TXRAM18r_fields,
  31686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31687         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31688         -1,
  31689         -1,
  31690     },
  31691 #endif /* chips */
  31692 
  31693 #if defined(BCM_88675_A0)
  31694     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19r */
  31695         soc_block_list[61],
  31696         soc_iprocreg,
  31697         1,
  31698         0,
  31699         0x1802128c,
  31700         0,
  31701         0,
  31702         2,
  31703         soc_QSPI_MSPI_TXRAM19r_fields,
  31704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31705         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31706         -1,
  31707         -1,
  31708     },
  31709 #endif /* chips */
  31710 
  31711 #if defined(BCM_88675_A0)
  31712     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20r */
  31713         soc_block_list[61],
  31714         soc_iprocreg,
  31715         1,
  31716         0,
  31717         0x18021290,
  31718         0,
  31719         0,
  31720         2,
  31721         soc_QSPI_MSPI_TXRAM20r_fields,
  31722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31723         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31724         -1,
  31725         -1,
  31726     },
  31727 #endif /* chips */
  31728 
  31729 #if defined(BCM_88675_A0)
  31730     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21r */
  31731         soc_block_list[61],
  31732         soc_iprocreg,
  31733         1,
  31734         0,
  31735         0x18021294,
  31736         0,
  31737         0,
  31738         2,
  31739         soc_QSPI_MSPI_TXRAM21r_fields,
  31740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31741         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31742         -1,
  31743         -1,
  31744     },
  31745 #endif /* chips */
  31746 
  31747 #if defined(BCM_88675_A0)
  31748     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22r */
  31749         soc_block_list[61],
  31750         soc_iprocreg,
  31751         1,
  31752         0,
  31753         0x18021298,
  31754         0,
  31755         0,
  31756         2,
  31757         soc_QSPI_MSPI_TXRAM22r_fields,
  31758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31759         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31760         -1,
  31761         -1,
  31762     },
  31763 #endif /* chips */
  31764 
  31765 #if defined(BCM_88675_A0)
  31766     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23r */
  31767         soc_block_list[61],
  31768         soc_iprocreg,
  31769         1,
  31770         0,
  31771         0x1802129c,
  31772         0,
  31773         0,
  31774         2,
  31775         soc_QSPI_MSPI_TXRAM23r_fields,
  31776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31777         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31778         -1,
  31779         -1,
  31780     },
  31781 #endif /* chips */
  31782 
  31783 #if defined(BCM_88675_A0)
  31784     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24r */
  31785         soc_block_list[61],
  31786         soc_iprocreg,
  31787         1,
  31788         0,
  31789         0x180212a0,
  31790         0,
  31791         0,
  31792         2,
  31793         soc_QSPI_MSPI_TXRAM24r_fields,
  31794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31796         -1,
  31797         -1,
  31798     },
  31799 #endif /* chips */
  31800 
  31801 #if defined(BCM_88675_A0)
  31802     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25r */
  31803         soc_block_list[61],
  31804         soc_iprocreg,
  31805         1,
  31806         0,
  31807         0x180212a4,
  31808         0,
  31809         0,
  31810         2,
  31811         soc_QSPI_MSPI_TXRAM25r_fields,
  31812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31813         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31814         -1,
  31815         -1,
  31816     },
  31817 #endif /* chips */
  31818 
  31819 #if defined(BCM_88675_A0)
  31820     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26r */
  31821         soc_block_list[61],
  31822         soc_iprocreg,
  31823         1,
  31824         0,
  31825         0x180212a8,
  31826         0,
  31827         0,
  31828         2,
  31829         soc_QSPI_MSPI_TXRAM26r_fields,
  31830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31831         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31832         -1,
  31833         -1,
  31834     },
  31835 #endif /* chips */
  31836 
  31837 #if defined(BCM_88675_A0)
  31838     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27r */
  31839         soc_block_list[61],
  31840         soc_iprocreg,
  31841         1,
  31842         0,
  31843         0x180212ac,
  31844         0,
  31845         0,
  31846         2,
  31847         soc_QSPI_MSPI_TXRAM27r_fields,
  31848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31849         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31850         -1,
  31851         -1,
  31852     },
  31853 #endif /* chips */
  31854 
  31855 #if defined(BCM_88675_A0)
  31856     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28r */
  31857         soc_block_list[61],
  31858         soc_iprocreg,
  31859         1,
  31860         0,
  31861         0x180212b0,
  31862         0,
  31863         0,
  31864         2,
  31865         soc_QSPI_MSPI_TXRAM28r_fields,
  31866         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31867         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31868         -1,
  31869         -1,
  31870     },
  31871 #endif /* chips */
  31872 
  31873 #if defined(BCM_88675_A0)
  31874     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29r */
  31875         soc_block_list[61],
  31876         soc_iprocreg,
  31877         1,
  31878         0,
  31879         0x180212b4,
  31880         0,
  31881         0,
  31882         2,
  31883         soc_QSPI_MSPI_TXRAM29r_fields,
  31884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31885         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31886         -1,
  31887         -1,
  31888     },
  31889 #endif /* chips */
  31890 
  31891 #if defined(BCM_88675_A0)
  31892     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30r */
  31893         soc_block_list[61],
  31894         soc_iprocreg,
  31895         1,
  31896         0,
  31897         0x180212b8,
  31898         0,
  31899         0,
  31900         2,
  31901         soc_QSPI_MSPI_TXRAM30r_fields,
  31902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31903         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31904         -1,
  31905         -1,
  31906     },
  31907 #endif /* chips */
  31908 
  31909 #if defined(BCM_88675_A0)
  31910     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31r */
  31911         soc_block_list[61],
  31912         soc_iprocreg,
  31913         1,
  31914         0,
  31915         0x180212bc,
  31916         0,
  31917         0,
  31918         2,
  31919         soc_QSPI_MSPI_TXRAM31r_fields,
  31920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31921         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31922         -1,
  31923         -1,
  31924     },
  31925 #endif /* chips */
  31926 
  31927 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  31928     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  31929     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  31930     defined(BCM_56260_B0)
  31931     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM53400_A0r */
  31932         soc_block_list[61],
  31933         soc_iprocreg,
  31934         1,
  31935         0,
  31936         0x18047240,
  31937         0,
  31938         0,
  31939         2,
  31940         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  31941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31942         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31943         -1,
  31944         -1,
  31945     },
  31946 #endif /* chips */
  31947 
  31948 #if defined(BCM_56370_A0)
  31949     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM56370_A0r */
  31950         soc_block_list[61],
  31951         soc_iprocreg,
  31952         1,
  31953         0,
  31954         0x15000240,
  31955         0,
  31956         0,
  31957         2,
  31958         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  31959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31960         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31961         -1,
  31962         -1,
  31963         3,
  31964     },
  31965 #endif /* chips */
  31966 
  31967 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  31968     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  31969     defined(BCM_56450_B1)
  31970     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM56450_A0r */
  31971         soc_block_list[61],
  31972         soc_iprocreg,
  31973         1,
  31974         0,
  31975         0x18027240,
  31976         0,
  31977         0,
  31978         2,
  31979         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  31980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31981         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31982         -1,
  31983         -1,
  31984     },
  31985 #endif /* chips */
  31986 
  31987 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  31988     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  31989     defined(BCM_56670_B0)
  31990     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM56560_A0r */
  31991         soc_block_list[61],
  31992         soc_iprocreg,
  31993         1,
  31994         0,
  31995         0x18021240,
  31996         0,
  31997         0,
  31998         2,
  31999         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32001         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32002         -1,
  32003         -1,
  32004     },
  32005 #endif /* chips */
  32006 
  32007 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  32008     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  32009     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  32010     defined(BCM_56980_B0)
  32011     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM56960_A0r */
  32012         soc_block_list[61],
  32013         soc_iprocreg,
  32014         1,
  32015         0,
  32016         0x18021240,
  32017         0,
  32018         0,
  32019         2,
  32020         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32023         -1,
  32024         -1,
  32025         3,
  32026     },
  32027 #endif /* chips */
  32028 
  32029 #if defined(BCM_88270_A0)
  32030     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM88270_A0r */
  32031         soc_block_list[61],
  32032         soc_iprocreg,
  32033         1,
  32034         0,
  32035         0x18021240,
  32036         0,
  32037         0,
  32038         2,
  32039         soc_QSPI_MSPI_TXRAM00_BCM88270_A0r_fields,
  32040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32041         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32042         -1,
  32043         -1,
  32044     },
  32045 #endif /* chips */
  32046 
  32047 #if defined(BCM_88375_A0)
  32048     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM88375_A0r */
  32049         soc_block_list[61],
  32050         soc_iprocreg,
  32051         1,
  32052         0,
  32053         0x18021240,
  32054         0,
  32055         0,
  32056         2,
  32057         soc_QSPI_MSPI_TXRAM00_BCM88375_A0r_fields,
  32058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32059         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32060         -1,
  32061         -1,
  32062     },
  32063 #endif /* chips */
  32064 
  32065 #if defined(BCM_88375_B0)
  32066     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM88375_B0r */
  32067         soc_block_list[61],
  32068         soc_iprocreg,
  32069         1,
  32070         0,
  32071         0x18021240,
  32072         0,
  32073         0,
  32074         2,
  32075         soc_QSPI_MSPI_TXRAM00_BCM88375_B0r_fields,
  32076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32078         -1,
  32079         -1,
  32080     },
  32081 #endif /* chips */
  32082 
  32083 #if defined(BCM_88470_A0)
  32084     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM88470_A0r */
  32085         soc_block_list[61],
  32086         soc_iprocreg,
  32087         1,
  32088         0,
  32089         0x18021240,
  32090         0,
  32091         0,
  32092         2,
  32093         soc_QSPI_MSPI_TXRAM00_BCM88470_A0r_fields,
  32094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32096         -1,
  32097         -1,
  32098     },
  32099 #endif /* chips */
  32100 
  32101 #if defined(BCM_88470_B0)
  32102     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM88470_B0r */
  32103         soc_block_list[61],
  32104         soc_iprocreg,
  32105         1,
  32106         0,
  32107         0x18021240,
  32108         0,
  32109         0,
  32110         2,
  32111         soc_QSPI_MSPI_TXRAM00_BCM88470_B0r_fields,
  32112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32113         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32114         -1,
  32115         -1,
  32116     },
  32117 #endif /* chips */
  32118 
  32119 #if defined(BCM_88675_B0)
  32120     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM88675_B0r */
  32121         soc_block_list[61],
  32122         soc_iprocreg,
  32123         1,
  32124         0,
  32125         0x18021240,
  32126         0,
  32127         0,
  32128         2,
  32129         soc_QSPI_MSPI_TXRAM00_BCM88675_B0r_fields,
  32130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32132         -1,
  32133         -1,
  32134     },
  32135 #endif /* chips */
  32136 
  32137 #if defined(BCM_88680_A0)
  32138     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM88680_A0r */
  32139         soc_block_list[61],
  32140         soc_iprocreg,
  32141         1,
  32142         0,
  32143         0x18021240,
  32144         0,
  32145         0,
  32146         2,
  32147         soc_QSPI_MSPI_TXRAM00_BCM88680_A0r_fields,
  32148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32149         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32150         -1,
  32151         -1,
  32152     },
  32153 #endif /* chips */
  32154 
  32155 #if defined(BCM_88690_A0)
  32156     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM88690_A0r */
  32157         soc_block_list[61],
  32158         soc_iprocreg,
  32159         1,
  32160         0,
  32161         0x18021240,
  32162         0,
  32163         0,
  32164         2,
  32165         soc_QSPI_MSPI_TXRAM00_BCM88690_A0r_fields,
  32166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32168         -1,
  32169         -1,
  32170     },
  32171 #endif /* chips */
  32172 
  32173 #if defined(BCM_88690_B0)
  32174     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM88690_B0r */
  32175         soc_block_list[61],
  32176         soc_iprocreg,
  32177         1,
  32178         0,
  32179         0x18021240,
  32180         0,
  32181         0,
  32182         2,
  32183         soc_QSPI_MSPI_TXRAM00_BCM88690_B0r_fields,
  32184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32186         -1,
  32187         -1,
  32188     },
  32189 #endif /* chips */
  32190 
  32191 #if defined(BCM_88790_A0)
  32192     { /* SOC_REG_INT_QSPI_MSPI_TXRAM00_BCM88790_A0r */
  32193         soc_block_list[61],
  32194         soc_iprocreg,
  32195         1,
  32196         0,
  32197         0x18021240,
  32198         0,
  32199         0,
  32200         2,
  32201         soc_QSPI_MSPI_TXRAM00_BCM88790_A0r_fields,
  32202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32203         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32204         -1,
  32205         -1,
  32206     },
  32207 #endif /* chips */
  32208 
  32209 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32210     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32211     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32212     defined(BCM_56260_B0)
  32213     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM53400_A0r */
  32214         soc_block_list[61],
  32215         soc_iprocreg,
  32216         1,
  32217         0,
  32218         0x18047244,
  32219         0,
  32220         0,
  32221         2,
  32222         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32224         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32225         -1,
  32226         -1,
  32227     },
  32228 #endif /* chips */
  32229 
  32230 #if defined(BCM_56370_A0)
  32231     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM56370_A0r */
  32232         soc_block_list[61],
  32233         soc_iprocreg,
  32234         1,
  32235         0,
  32236         0x15000244,
  32237         0,
  32238         0,
  32239         2,
  32240         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32241         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32242         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32243         -1,
  32244         -1,
  32245         3,
  32246     },
  32247 #endif /* chips */
  32248 
  32249 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  32250     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  32251     defined(BCM_56450_B1)
  32252     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM56450_A0r */
  32253         soc_block_list[61],
  32254         soc_iprocreg,
  32255         1,
  32256         0,
  32257         0x18027244,
  32258         0,
  32259         0,
  32260         2,
  32261         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  32262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32264         -1,
  32265         -1,
  32266     },
  32267 #endif /* chips */
  32268 
  32269 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  32270     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  32271     defined(BCM_56670_B0)
  32272     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM56560_A0r */
  32273         soc_block_list[61],
  32274         soc_iprocreg,
  32275         1,
  32276         0,
  32277         0x18021244,
  32278         0,
  32279         0,
  32280         2,
  32281         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32283         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32284         -1,
  32285         -1,
  32286     },
  32287 #endif /* chips */
  32288 
  32289 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  32290     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  32291     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  32292     defined(BCM_56980_B0)
  32293     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM56960_A0r */
  32294         soc_block_list[61],
  32295         soc_iprocreg,
  32296         1,
  32297         0,
  32298         0x18021244,
  32299         0,
  32300         0,
  32301         2,
  32302         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32304         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32305         -1,
  32306         -1,
  32307         3,
  32308     },
  32309 #endif /* chips */
  32310 
  32311 #if defined(BCM_88270_A0)
  32312     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM88270_A0r */
  32313         soc_block_list[61],
  32314         soc_iprocreg,
  32315         1,
  32316         0,
  32317         0x18021244,
  32318         0,
  32319         0,
  32320         2,
  32321         soc_QSPI_MSPI_TXRAM01_BCM88270_A0r_fields,
  32322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32323         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32324         -1,
  32325         -1,
  32326     },
  32327 #endif /* chips */
  32328 
  32329 #if defined(BCM_88375_A0)
  32330     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM88375_A0r */
  32331         soc_block_list[61],
  32332         soc_iprocreg,
  32333         1,
  32334         0,
  32335         0x18021244,
  32336         0,
  32337         0,
  32338         2,
  32339         soc_QSPI_MSPI_TXRAM01_BCM88375_A0r_fields,
  32340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32341         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32342         -1,
  32343         -1,
  32344     },
  32345 #endif /* chips */
  32346 
  32347 #if defined(BCM_88375_B0)
  32348     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM88375_B0r */
  32349         soc_block_list[61],
  32350         soc_iprocreg,
  32351         1,
  32352         0,
  32353         0x18021244,
  32354         0,
  32355         0,
  32356         2,
  32357         soc_QSPI_MSPI_TXRAM01_BCM88375_B0r_fields,
  32358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32359         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32360         -1,
  32361         -1,
  32362     },
  32363 #endif /* chips */
  32364 
  32365 #if defined(BCM_88470_A0)
  32366     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM88470_A0r */
  32367         soc_block_list[61],
  32368         soc_iprocreg,
  32369         1,
  32370         0,
  32371         0x18021244,
  32372         0,
  32373         0,
  32374         2,
  32375         soc_QSPI_MSPI_TXRAM01_BCM88470_A0r_fields,
  32376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32377         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32378         -1,
  32379         -1,
  32380     },
  32381 #endif /* chips */
  32382 
  32383 #if defined(BCM_88470_B0)
  32384     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM88470_B0r */
  32385         soc_block_list[61],
  32386         soc_iprocreg,
  32387         1,
  32388         0,
  32389         0x18021244,
  32390         0,
  32391         0,
  32392         2,
  32393         soc_QSPI_MSPI_TXRAM01_BCM88470_B0r_fields,
  32394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32395         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32396         -1,
  32397         -1,
  32398     },
  32399 #endif /* chips */
  32400 
  32401 #if defined(BCM_88675_B0)
  32402     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM88675_B0r */
  32403         soc_block_list[61],
  32404         soc_iprocreg,
  32405         1,
  32406         0,
  32407         0x18021244,
  32408         0,
  32409         0,
  32410         2,
  32411         soc_QSPI_MSPI_TXRAM01_BCM88675_B0r_fields,
  32412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32413         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32414         -1,
  32415         -1,
  32416     },
  32417 #endif /* chips */
  32418 
  32419 #if defined(BCM_88680_A0)
  32420     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM88680_A0r */
  32421         soc_block_list[61],
  32422         soc_iprocreg,
  32423         1,
  32424         0,
  32425         0x18021244,
  32426         0,
  32427         0,
  32428         2,
  32429         soc_QSPI_MSPI_TXRAM01_BCM88680_A0r_fields,
  32430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32431         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32432         -1,
  32433         -1,
  32434     },
  32435 #endif /* chips */
  32436 
  32437 #if defined(BCM_88690_A0)
  32438     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM88690_A0r */
  32439         soc_block_list[61],
  32440         soc_iprocreg,
  32441         1,
  32442         0,
  32443         0x18021244,
  32444         0,
  32445         0,
  32446         2,
  32447         soc_QSPI_MSPI_TXRAM01_BCM88690_A0r_fields,
  32448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32449         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32450         -1,
  32451         -1,
  32452     },
  32453 #endif /* chips */
  32454 
  32455 #if defined(BCM_88690_B0)
  32456     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM88690_B0r */
  32457         soc_block_list[61],
  32458         soc_iprocreg,
  32459         1,
  32460         0,
  32461         0x18021244,
  32462         0,
  32463         0,
  32464         2,
  32465         soc_QSPI_MSPI_TXRAM01_BCM88690_B0r_fields,
  32466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32467         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32468         -1,
  32469         -1,
  32470     },
  32471 #endif /* chips */
  32472 
  32473 #if defined(BCM_88790_A0)
  32474     { /* SOC_REG_INT_QSPI_MSPI_TXRAM01_BCM88790_A0r */
  32475         soc_block_list[61],
  32476         soc_iprocreg,
  32477         1,
  32478         0,
  32479         0x18021244,
  32480         0,
  32481         0,
  32482         2,
  32483         soc_QSPI_MSPI_TXRAM01_BCM88790_A0r_fields,
  32484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32485         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32486         -1,
  32487         -1,
  32488     },
  32489 #endif /* chips */
  32490 
  32491 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32492     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32493     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32494     defined(BCM_56260_B0)
  32495     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM53400_A0r */
  32496         soc_block_list[61],
  32497         soc_iprocreg,
  32498         1,
  32499         0,
  32500         0x18047248,
  32501         0,
  32502         0,
  32503         2,
  32504         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32506         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32507         -1,
  32508         -1,
  32509     },
  32510 #endif /* chips */
  32511 
  32512 #if defined(BCM_56370_A0)
  32513     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM56370_A0r */
  32514         soc_block_list[61],
  32515         soc_iprocreg,
  32516         1,
  32517         0,
  32518         0x15000248,
  32519         0,
  32520         0,
  32521         2,
  32522         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32524         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32525         -1,
  32526         -1,
  32527         3,
  32528     },
  32529 #endif /* chips */
  32530 
  32531 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  32532     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  32533     defined(BCM_56450_B1)
  32534     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM56450_A0r */
  32535         soc_block_list[61],
  32536         soc_iprocreg,
  32537         1,
  32538         0,
  32539         0x18027248,
  32540         0,
  32541         0,
  32542         2,
  32543         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  32544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32545         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32546         -1,
  32547         -1,
  32548     },
  32549 #endif /* chips */
  32550 
  32551 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  32552     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  32553     defined(BCM_56670_B0)
  32554     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM56560_A0r */
  32555         soc_block_list[61],
  32556         soc_iprocreg,
  32557         1,
  32558         0,
  32559         0x18021248,
  32560         0,
  32561         0,
  32562         2,
  32563         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32565         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32566         -1,
  32567         -1,
  32568     },
  32569 #endif /* chips */
  32570 
  32571 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  32572     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  32573     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  32574     defined(BCM_56980_B0)
  32575     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM56960_A0r */
  32576         soc_block_list[61],
  32577         soc_iprocreg,
  32578         1,
  32579         0,
  32580         0x18021248,
  32581         0,
  32582         0,
  32583         2,
  32584         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32585         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32586         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32587         -1,
  32588         -1,
  32589         3,
  32590     },
  32591 #endif /* chips */
  32592 
  32593 #if defined(BCM_88270_A0)
  32594     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM88270_A0r */
  32595         soc_block_list[61],
  32596         soc_iprocreg,
  32597         1,
  32598         0,
  32599         0x18021248,
  32600         0,
  32601         0,
  32602         2,
  32603         soc_QSPI_MSPI_TXRAM02_BCM88270_A0r_fields,
  32604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32605         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32606         -1,
  32607         -1,
  32608     },
  32609 #endif /* chips */
  32610 
  32611 #if defined(BCM_88375_A0)
  32612     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM88375_A0r */
  32613         soc_block_list[61],
  32614         soc_iprocreg,
  32615         1,
  32616         0,
  32617         0x18021248,
  32618         0,
  32619         0,
  32620         2,
  32621         soc_QSPI_MSPI_TXRAM02_BCM88375_A0r_fields,
  32622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32623         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32624         -1,
  32625         -1,
  32626     },
  32627 #endif /* chips */
  32628 
  32629 #if defined(BCM_88375_B0)
  32630     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM88375_B0r */
  32631         soc_block_list[61],
  32632         soc_iprocreg,
  32633         1,
  32634         0,
  32635         0x18021248,
  32636         0,
  32637         0,
  32638         2,
  32639         soc_QSPI_MSPI_TXRAM02_BCM88375_B0r_fields,
  32640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32641         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32642         -1,
  32643         -1,
  32644     },
  32645 #endif /* chips */
  32646 
  32647 #if defined(BCM_88470_A0)
  32648     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM88470_A0r */
  32649         soc_block_list[61],
  32650         soc_iprocreg,
  32651         1,
  32652         0,
  32653         0x18021248,
  32654         0,
  32655         0,
  32656         2,
  32657         soc_QSPI_MSPI_TXRAM02_BCM88470_A0r_fields,
  32658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32659         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32660         -1,
  32661         -1,
  32662     },
  32663 #endif /* chips */
  32664 
  32665 #if defined(BCM_88470_B0)
  32666     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM88470_B0r */
  32667         soc_block_list[61],
  32668         soc_iprocreg,
  32669         1,
  32670         0,
  32671         0x18021248,
  32672         0,
  32673         0,
  32674         2,
  32675         soc_QSPI_MSPI_TXRAM02_BCM88470_B0r_fields,
  32676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32677         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32678         -1,
  32679         -1,
  32680     },
  32681 #endif /* chips */
  32682 
  32683 #if defined(BCM_88675_B0)
  32684     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM88675_B0r */
  32685         soc_block_list[61],
  32686         soc_iprocreg,
  32687         1,
  32688         0,
  32689         0x18021248,
  32690         0,
  32691         0,
  32692         2,
  32693         soc_QSPI_MSPI_TXRAM02_BCM88675_B0r_fields,
  32694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32695         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32696         -1,
  32697         -1,
  32698     },
  32699 #endif /* chips */
  32700 
  32701 #if defined(BCM_88680_A0)
  32702     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM88680_A0r */
  32703         soc_block_list[61],
  32704         soc_iprocreg,
  32705         1,
  32706         0,
  32707         0x18021248,
  32708         0,
  32709         0,
  32710         2,
  32711         soc_QSPI_MSPI_TXRAM02_BCM88680_A0r_fields,
  32712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32713         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32714         -1,
  32715         -1,
  32716     },
  32717 #endif /* chips */
  32718 
  32719 #if defined(BCM_88690_A0)
  32720     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM88690_A0r */
  32721         soc_block_list[61],
  32722         soc_iprocreg,
  32723         1,
  32724         0,
  32725         0x18021248,
  32726         0,
  32727         0,
  32728         2,
  32729         soc_QSPI_MSPI_TXRAM02_BCM88690_A0r_fields,
  32730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32731         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32732         -1,
  32733         -1,
  32734     },
  32735 #endif /* chips */
  32736 
  32737 #if defined(BCM_88690_B0)
  32738     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM88690_B0r */
  32739         soc_block_list[61],
  32740         soc_iprocreg,
  32741         1,
  32742         0,
  32743         0x18021248,
  32744         0,
  32745         0,
  32746         2,
  32747         soc_QSPI_MSPI_TXRAM02_BCM88690_B0r_fields,
  32748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32749         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32750         -1,
  32751         -1,
  32752     },
  32753 #endif /* chips */
  32754 
  32755 #if defined(BCM_88790_A0)
  32756     { /* SOC_REG_INT_QSPI_MSPI_TXRAM02_BCM88790_A0r */
  32757         soc_block_list[61],
  32758         soc_iprocreg,
  32759         1,
  32760         0,
  32761         0x18021248,
  32762         0,
  32763         0,
  32764         2,
  32765         soc_QSPI_MSPI_TXRAM02_BCM88790_A0r_fields,
  32766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32767         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32768         -1,
  32769         -1,
  32770     },
  32771 #endif /* chips */
  32772 
  32773 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  32774     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  32775     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  32776     defined(BCM_56260_B0)
  32777     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM53400_A0r */
  32778         soc_block_list[61],
  32779         soc_iprocreg,
  32780         1,
  32781         0,
  32782         0x1804724c,
  32783         0,
  32784         0,
  32785         2,
  32786         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32788         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32789         -1,
  32790         -1,
  32791     },
  32792 #endif /* chips */
  32793 
  32794 #if defined(BCM_56370_A0)
  32795     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM56370_A0r */
  32796         soc_block_list[61],
  32797         soc_iprocreg,
  32798         1,
  32799         0,
  32800         0x1500024c,
  32801         0,
  32802         0,
  32803         2,
  32804         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32806         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32807         -1,
  32808         -1,
  32809         3,
  32810     },
  32811 #endif /* chips */
  32812 
  32813 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  32814     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  32815     defined(BCM_56450_B1)
  32816     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM56450_A0r */
  32817         soc_block_list[61],
  32818         soc_iprocreg,
  32819         1,
  32820         0,
  32821         0x1802724c,
  32822         0,
  32823         0,
  32824         2,
  32825         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  32826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32827         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32828         -1,
  32829         -1,
  32830     },
  32831 #endif /* chips */
  32832 
  32833 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  32834     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  32835     defined(BCM_56670_B0)
  32836     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM56560_A0r */
  32837         soc_block_list[61],
  32838         soc_iprocreg,
  32839         1,
  32840         0,
  32841         0x1802124c,
  32842         0,
  32843         0,
  32844         2,
  32845         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32847         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32848         -1,
  32849         -1,
  32850     },
  32851 #endif /* chips */
  32852 
  32853 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  32854     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  32855     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  32856     defined(BCM_56980_B0)
  32857     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM56960_A0r */
  32858         soc_block_list[61],
  32859         soc_iprocreg,
  32860         1,
  32861         0,
  32862         0x1802124c,
  32863         0,
  32864         0,
  32865         2,
  32866         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  32867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32868         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32869         -1,
  32870         -1,
  32871         3,
  32872     },
  32873 #endif /* chips */
  32874 
  32875 #if defined(BCM_88270_A0)
  32876     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM88270_A0r */
  32877         soc_block_list[61],
  32878         soc_iprocreg,
  32879         1,
  32880         0,
  32881         0x1802124c,
  32882         0,
  32883         0,
  32884         2,
  32885         soc_QSPI_MSPI_TXRAM03_BCM88270_A0r_fields,
  32886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32887         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32888         -1,
  32889         -1,
  32890     },
  32891 #endif /* chips */
  32892 
  32893 #if defined(BCM_88375_A0)
  32894     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM88375_A0r */
  32895         soc_block_list[61],
  32896         soc_iprocreg,
  32897         1,
  32898         0,
  32899         0x1802124c,
  32900         0,
  32901         0,
  32902         2,
  32903         soc_QSPI_MSPI_TXRAM03_BCM88375_A0r_fields,
  32904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32905         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32906         -1,
  32907         -1,
  32908     },
  32909 #endif /* chips */
  32910 
  32911 #if defined(BCM_88375_B0)
  32912     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM88375_B0r */
  32913         soc_block_list[61],
  32914         soc_iprocreg,
  32915         1,
  32916         0,
  32917         0x1802124c,
  32918         0,
  32919         0,
  32920         2,
  32921         soc_QSPI_MSPI_TXRAM03_BCM88375_B0r_fields,
  32922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32923         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32924         -1,
  32925         -1,
  32926     },
  32927 #endif /* chips */
  32928 
  32929 #if defined(BCM_88470_A0)
  32930     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM88470_A0r */
  32931         soc_block_list[61],
  32932         soc_iprocreg,
  32933         1,
  32934         0,
  32935         0x1802124c,
  32936         0,
  32937         0,
  32938         2,
  32939         soc_QSPI_MSPI_TXRAM03_BCM88470_A0r_fields,
  32940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32941         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32942         -1,
  32943         -1,
  32944     },
  32945 #endif /* chips */
  32946 
  32947 #if defined(BCM_88470_B0)
  32948     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM88470_B0r */
  32949         soc_block_list[61],
  32950         soc_iprocreg,
  32951         1,
  32952         0,
  32953         0x1802124c,
  32954         0,
  32955         0,
  32956         2,
  32957         soc_QSPI_MSPI_TXRAM03_BCM88470_B0r_fields,
  32958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32959         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32960         -1,
  32961         -1,
  32962     },
  32963 #endif /* chips */
  32964 
  32965 #if defined(BCM_88675_B0)
  32966     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM88675_B0r */
  32967         soc_block_list[61],
  32968         soc_iprocreg,
  32969         1,
  32970         0,
  32971         0x1802124c,
  32972         0,
  32973         0,
  32974         2,
  32975         soc_QSPI_MSPI_TXRAM03_BCM88675_B0r_fields,
  32976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32977         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32978         -1,
  32979         -1,
  32980     },
  32981 #endif /* chips */
  32982 
  32983 #if defined(BCM_88680_A0)
  32984     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM88680_A0r */
  32985         soc_block_list[61],
  32986         soc_iprocreg,
  32987         1,
  32988         0,
  32989         0x1802124c,
  32990         0,
  32991         0,
  32992         2,
  32993         soc_QSPI_MSPI_TXRAM03_BCM88680_A0r_fields,
  32994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32995         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32996         -1,
  32997         -1,
  32998     },
  32999 #endif /* chips */
  33000 
  33001 #if defined(BCM_88690_A0)
  33002     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM88690_A0r */
  33003         soc_block_list[61],
  33004         soc_iprocreg,
  33005         1,
  33006         0,
  33007         0x1802124c,
  33008         0,
  33009         0,
  33010         2,
  33011         soc_QSPI_MSPI_TXRAM03_BCM88690_A0r_fields,
  33012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33013         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33014         -1,
  33015         -1,
  33016     },
  33017 #endif /* chips */
  33018 
  33019 #if defined(BCM_88690_B0)
  33020     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM88690_B0r */
  33021         soc_block_list[61],
  33022         soc_iprocreg,
  33023         1,
  33024         0,
  33025         0x1802124c,
  33026         0,
  33027         0,
  33028         2,
  33029         soc_QSPI_MSPI_TXRAM03_BCM88690_B0r_fields,
  33030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33031         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33032         -1,
  33033         -1,
  33034     },
  33035 #endif /* chips */
  33036 
  33037 #if defined(BCM_88790_A0)
  33038     { /* SOC_REG_INT_QSPI_MSPI_TXRAM03_BCM88790_A0r */
  33039         soc_block_list[61],
  33040         soc_iprocreg,
  33041         1,
  33042         0,
  33043         0x1802124c,
  33044         0,
  33045         0,
  33046         2,
  33047         soc_QSPI_MSPI_TXRAM03_BCM88790_A0r_fields,
  33048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33049         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33050         -1,
  33051         -1,
  33052     },
  33053 #endif /* chips */
  33054 
  33055 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  33056     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  33057     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  33058     defined(BCM_56260_B0)
  33059     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM53400_A0r */
  33060         soc_block_list[61],
  33061         soc_iprocreg,
  33062         1,
  33063         0,
  33064         0x18047250,
  33065         0,
  33066         0,
  33067         2,
  33068         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33070         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33071         -1,
  33072         -1,
  33073     },
  33074 #endif /* chips */
  33075 
  33076 #if defined(BCM_56370_A0)
  33077     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM56370_A0r */
  33078         soc_block_list[61],
  33079         soc_iprocreg,
  33080         1,
  33081         0,
  33082         0x15000250,
  33083         0,
  33084         0,
  33085         2,
  33086         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33088         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33089         -1,
  33090         -1,
  33091         3,
  33092     },
  33093 #endif /* chips */
  33094 
  33095 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  33096     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  33097     defined(BCM_56450_B1)
  33098     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM56450_A0r */
  33099         soc_block_list[61],
  33100         soc_iprocreg,
  33101         1,
  33102         0,
  33103         0x18027250,
  33104         0,
  33105         0,
  33106         2,
  33107         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  33108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33109         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33110         -1,
  33111         -1,
  33112     },
  33113 #endif /* chips */
  33114 
  33115 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  33116     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  33117     defined(BCM_56670_B0)
  33118     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM56560_A0r */
  33119         soc_block_list[61],
  33120         soc_iprocreg,
  33121         1,
  33122         0,
  33123         0x18021250,
  33124         0,
  33125         0,
  33126         2,
  33127         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33129         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33130         -1,
  33131         -1,
  33132     },
  33133 #endif /* chips */
  33134 
  33135 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  33136     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  33137     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  33138     defined(BCM_56980_B0)
  33139     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM56960_A0r */
  33140         soc_block_list[61],
  33141         soc_iprocreg,
  33142         1,
  33143         0,
  33144         0x18021250,
  33145         0,
  33146         0,
  33147         2,
  33148         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33150         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33151         -1,
  33152         -1,
  33153         3,
  33154     },
  33155 #endif /* chips */
  33156 
  33157 #if defined(BCM_88270_A0)
  33158     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM88270_A0r */
  33159         soc_block_list[61],
  33160         soc_iprocreg,
  33161         1,
  33162         0,
  33163         0x18021250,
  33164         0,
  33165         0,
  33166         2,
  33167         soc_QSPI_MSPI_TXRAM04_BCM88270_A0r_fields,
  33168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33169         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33170         -1,
  33171         -1,
  33172     },
  33173 #endif /* chips */
  33174 
  33175 #if defined(BCM_88375_A0)
  33176     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM88375_A0r */
  33177         soc_block_list[61],
  33178         soc_iprocreg,
  33179         1,
  33180         0,
  33181         0x18021250,
  33182         0,
  33183         0,
  33184         2,
  33185         soc_QSPI_MSPI_TXRAM04_BCM88375_A0r_fields,
  33186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33187         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33188         -1,
  33189         -1,
  33190     },
  33191 #endif /* chips */
  33192 
  33193 #if defined(BCM_88375_B0)
  33194     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM88375_B0r */
  33195         soc_block_list[61],
  33196         soc_iprocreg,
  33197         1,
  33198         0,
  33199         0x18021250,
  33200         0,
  33201         0,
  33202         2,
  33203         soc_QSPI_MSPI_TXRAM04_BCM88375_B0r_fields,
  33204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33205         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33206         -1,
  33207         -1,
  33208     },
  33209 #endif /* chips */
  33210 
  33211 #if defined(BCM_88470_A0)
  33212     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM88470_A0r */
  33213         soc_block_list[61],
  33214         soc_iprocreg,
  33215         1,
  33216         0,
  33217         0x18021250,
  33218         0,
  33219         0,
  33220         2,
  33221         soc_QSPI_MSPI_TXRAM04_BCM88470_A0r_fields,
  33222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33223         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33224         -1,
  33225         -1,
  33226     },
  33227 #endif /* chips */
  33228 
  33229 #if defined(BCM_88470_B0)
  33230     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM88470_B0r */
  33231         soc_block_list[61],
  33232         soc_iprocreg,
  33233         1,
  33234         0,
  33235         0x18021250,
  33236         0,
  33237         0,
  33238         2,
  33239         soc_QSPI_MSPI_TXRAM04_BCM88470_B0r_fields,
  33240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33241         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33242         -1,
  33243         -1,
  33244     },
  33245 #endif /* chips */
  33246 
  33247 #if defined(BCM_88675_B0)
  33248     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM88675_B0r */
  33249         soc_block_list[61],
  33250         soc_iprocreg,
  33251         1,
  33252         0,
  33253         0x18021250,
  33254         0,
  33255         0,
  33256         2,
  33257         soc_QSPI_MSPI_TXRAM04_BCM88675_B0r_fields,
  33258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33259         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33260         -1,
  33261         -1,
  33262     },
  33263 #endif /* chips */
  33264 
  33265 #if defined(BCM_88680_A0)
  33266     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM88680_A0r */
  33267         soc_block_list[61],
  33268         soc_iprocreg,
  33269         1,
  33270         0,
  33271         0x18021250,
  33272         0,
  33273         0,
  33274         2,
  33275         soc_QSPI_MSPI_TXRAM04_BCM88680_A0r_fields,
  33276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33277         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33278         -1,
  33279         -1,
  33280     },
  33281 #endif /* chips */
  33282 
  33283 #if defined(BCM_88690_A0)
  33284     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM88690_A0r */
  33285         soc_block_list[61],
  33286         soc_iprocreg,
  33287         1,
  33288         0,
  33289         0x18021250,
  33290         0,
  33291         0,
  33292         2,
  33293         soc_QSPI_MSPI_TXRAM04_BCM88690_A0r_fields,
  33294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33295         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33296         -1,
  33297         -1,
  33298     },
  33299 #endif /* chips */
  33300 
  33301 #if defined(BCM_88690_B0)
  33302     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM88690_B0r */
  33303         soc_block_list[61],
  33304         soc_iprocreg,
  33305         1,
  33306         0,
  33307         0x18021250,
  33308         0,
  33309         0,
  33310         2,
  33311         soc_QSPI_MSPI_TXRAM04_BCM88690_B0r_fields,
  33312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33313         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33314         -1,
  33315         -1,
  33316     },
  33317 #endif /* chips */
  33318 
  33319 #if defined(BCM_88790_A0)
  33320     { /* SOC_REG_INT_QSPI_MSPI_TXRAM04_BCM88790_A0r */
  33321         soc_block_list[61],
  33322         soc_iprocreg,
  33323         1,
  33324         0,
  33325         0x18021250,
  33326         0,
  33327         0,
  33328         2,
  33329         soc_QSPI_MSPI_TXRAM04_BCM88790_A0r_fields,
  33330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33331         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33332         -1,
  33333         -1,
  33334     },
  33335 #endif /* chips */
  33336 
  33337 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  33338     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  33339     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  33340     defined(BCM_56260_B0)
  33341     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM53400_A0r */
  33342         soc_block_list[61],
  33343         soc_iprocreg,
  33344         1,
  33345         0,
  33346         0x18047254,
  33347         0,
  33348         0,
  33349         2,
  33350         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33352         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33353         -1,
  33354         -1,
  33355     },
  33356 #endif /* chips */
  33357 
  33358 #if defined(BCM_56370_A0)
  33359     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM56370_A0r */
  33360         soc_block_list[61],
  33361         soc_iprocreg,
  33362         1,
  33363         0,
  33364         0x15000254,
  33365         0,
  33366         0,
  33367         2,
  33368         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33370         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33371         -1,
  33372         -1,
  33373         3,
  33374     },
  33375 #endif /* chips */
  33376 
  33377 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  33378     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  33379     defined(BCM_56450_B1)
  33380     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM56450_A0r */
  33381         soc_block_list[61],
  33382         soc_iprocreg,
  33383         1,
  33384         0,
  33385         0x18027254,
  33386         0,
  33387         0,
  33388         2,
  33389         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  33390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33391         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33392         -1,
  33393         -1,
  33394     },
  33395 #endif /* chips */
  33396 
  33397 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  33398     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  33399     defined(BCM_56670_B0)
  33400     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM56560_A0r */
  33401         soc_block_list[61],
  33402         soc_iprocreg,
  33403         1,
  33404         0,
  33405         0x18021254,
  33406         0,
  33407         0,
  33408         2,
  33409         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33411         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33412         -1,
  33413         -1,
  33414     },
  33415 #endif /* chips */
  33416 
  33417 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  33418     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  33419     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  33420     defined(BCM_56980_B0)
  33421     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM56960_A0r */
  33422         soc_block_list[61],
  33423         soc_iprocreg,
  33424         1,
  33425         0,
  33426         0x18021254,
  33427         0,
  33428         0,
  33429         2,
  33430         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33432         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33433         -1,
  33434         -1,
  33435         3,
  33436     },
  33437 #endif /* chips */
  33438 
  33439 #if defined(BCM_88270_A0)
  33440     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM88270_A0r */
  33441         soc_block_list[61],
  33442         soc_iprocreg,
  33443         1,
  33444         0,
  33445         0x18021254,
  33446         0,
  33447         0,
  33448         2,
  33449         soc_QSPI_MSPI_TXRAM05_BCM88270_A0r_fields,
  33450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33451         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33452         -1,
  33453         -1,
  33454     },
  33455 #endif /* chips */
  33456 
  33457 #if defined(BCM_88375_A0)
  33458     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM88375_A0r */
  33459         soc_block_list[61],
  33460         soc_iprocreg,
  33461         1,
  33462         0,
  33463         0x18021254,
  33464         0,
  33465         0,
  33466         2,
  33467         soc_QSPI_MSPI_TXRAM05_BCM88375_A0r_fields,
  33468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33469         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33470         -1,
  33471         -1,
  33472     },
  33473 #endif /* chips */
  33474 
  33475 #if defined(BCM_88375_B0)
  33476     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM88375_B0r */
  33477         soc_block_list[61],
  33478         soc_iprocreg,
  33479         1,
  33480         0,
  33481         0x18021254,
  33482         0,
  33483         0,
  33484         2,
  33485         soc_QSPI_MSPI_TXRAM05_BCM88375_B0r_fields,
  33486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33487         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33488         -1,
  33489         -1,
  33490     },
  33491 #endif /* chips */
  33492 
  33493 #if defined(BCM_88470_A0)
  33494     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM88470_A0r */
  33495         soc_block_list[61],
  33496         soc_iprocreg,
  33497         1,
  33498         0,
  33499         0x18021254,
  33500         0,
  33501         0,
  33502         2,
  33503         soc_QSPI_MSPI_TXRAM05_BCM88470_A0r_fields,
  33504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33505         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33506         -1,
  33507         -1,
  33508     },
  33509 #endif /* chips */
  33510 
  33511 #if defined(BCM_88470_B0)
  33512     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM88470_B0r */
  33513         soc_block_list[61],
  33514         soc_iprocreg,
  33515         1,
  33516         0,
  33517         0x18021254,
  33518         0,
  33519         0,
  33520         2,
  33521         soc_QSPI_MSPI_TXRAM05_BCM88470_B0r_fields,
  33522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33523         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33524         -1,
  33525         -1,
  33526     },
  33527 #endif /* chips */
  33528 
  33529 #if defined(BCM_88675_B0)
  33530     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM88675_B0r */
  33531         soc_block_list[61],
  33532         soc_iprocreg,
  33533         1,
  33534         0,
  33535         0x18021254,
  33536         0,
  33537         0,
  33538         2,
  33539         soc_QSPI_MSPI_TXRAM05_BCM88675_B0r_fields,
  33540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33541         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33542         -1,
  33543         -1,
  33544     },
  33545 #endif /* chips */
  33546 
  33547 #if defined(BCM_88680_A0)
  33548     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM88680_A0r */
  33549         soc_block_list[61],
  33550         soc_iprocreg,
  33551         1,
  33552         0,
  33553         0x18021254,
  33554         0,
  33555         0,
  33556         2,
  33557         soc_QSPI_MSPI_TXRAM05_BCM88680_A0r_fields,
  33558         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33559         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33560         -1,
  33561         -1,
  33562     },
  33563 #endif /* chips */
  33564 
  33565 #if defined(BCM_88690_A0)
  33566     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM88690_A0r */
  33567         soc_block_list[61],
  33568         soc_iprocreg,
  33569         1,
  33570         0,
  33571         0x18021254,
  33572         0,
  33573         0,
  33574         2,
  33575         soc_QSPI_MSPI_TXRAM05_BCM88690_A0r_fields,
  33576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33577         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33578         -1,
  33579         -1,
  33580     },
  33581 #endif /* chips */
  33582 
  33583 #if defined(BCM_88690_B0)
  33584     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM88690_B0r */
  33585         soc_block_list[61],
  33586         soc_iprocreg,
  33587         1,
  33588         0,
  33589         0x18021254,
  33590         0,
  33591         0,
  33592         2,
  33593         soc_QSPI_MSPI_TXRAM05_BCM88690_B0r_fields,
  33594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33596         -1,
  33597         -1,
  33598     },
  33599 #endif /* chips */
  33600 
  33601 #if defined(BCM_88790_A0)
  33602     { /* SOC_REG_INT_QSPI_MSPI_TXRAM05_BCM88790_A0r */
  33603         soc_block_list[61],
  33604         soc_iprocreg,
  33605         1,
  33606         0,
  33607         0x18021254,
  33608         0,
  33609         0,
  33610         2,
  33611         soc_QSPI_MSPI_TXRAM05_BCM88790_A0r_fields,
  33612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33613         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33614         -1,
  33615         -1,
  33616     },
  33617 #endif /* chips */
  33618 
  33619 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  33620     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  33621     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  33622     defined(BCM_56260_B0)
  33623     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM53400_A0r */
  33624         soc_block_list[61],
  33625         soc_iprocreg,
  33626         1,
  33627         0,
  33628         0x18047258,
  33629         0,
  33630         0,
  33631         2,
  33632         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33634         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33635         -1,
  33636         -1,
  33637     },
  33638 #endif /* chips */
  33639 
  33640 #if defined(BCM_56370_A0)
  33641     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM56370_A0r */
  33642         soc_block_list[61],
  33643         soc_iprocreg,
  33644         1,
  33645         0,
  33646         0x15000258,
  33647         0,
  33648         0,
  33649         2,
  33650         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33652         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33653         -1,
  33654         -1,
  33655         3,
  33656     },
  33657 #endif /* chips */
  33658 
  33659 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  33660     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  33661     defined(BCM_56450_B1)
  33662     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM56450_A0r */
  33663         soc_block_list[61],
  33664         soc_iprocreg,
  33665         1,
  33666         0,
  33667         0x18027258,
  33668         0,
  33669         0,
  33670         2,
  33671         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  33672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33673         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33674         -1,
  33675         -1,
  33676     },
  33677 #endif /* chips */
  33678 
  33679 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  33680     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  33681     defined(BCM_56670_B0)
  33682     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM56560_A0r */
  33683         soc_block_list[61],
  33684         soc_iprocreg,
  33685         1,
  33686         0,
  33687         0x18021258,
  33688         0,
  33689         0,
  33690         2,
  33691         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33693         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33694         -1,
  33695         -1,
  33696     },
  33697 #endif /* chips */
  33698 
  33699 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  33700     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  33701     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  33702     defined(BCM_56980_B0)
  33703     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM56960_A0r */
  33704         soc_block_list[61],
  33705         soc_iprocreg,
  33706         1,
  33707         0,
  33708         0x18021258,
  33709         0,
  33710         0,
  33711         2,
  33712         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33714         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33715         -1,
  33716         -1,
  33717         3,
  33718     },
  33719 #endif /* chips */
  33720 
  33721 #if defined(BCM_88270_A0)
  33722     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM88270_A0r */
  33723         soc_block_list[61],
  33724         soc_iprocreg,
  33725         1,
  33726         0,
  33727         0x18021258,
  33728         0,
  33729         0,
  33730         2,
  33731         soc_QSPI_MSPI_TXRAM06_BCM88270_A0r_fields,
  33732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33733         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33734         -1,
  33735         -1,
  33736     },
  33737 #endif /* chips */
  33738 
  33739 #if defined(BCM_88375_A0)
  33740     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM88375_A0r */
  33741         soc_block_list[61],
  33742         soc_iprocreg,
  33743         1,
  33744         0,
  33745         0x18021258,
  33746         0,
  33747         0,
  33748         2,
  33749         soc_QSPI_MSPI_TXRAM06_BCM88375_A0r_fields,
  33750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33751         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33752         -1,
  33753         -1,
  33754     },
  33755 #endif /* chips */
  33756 
  33757 #if defined(BCM_88375_B0)
  33758     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM88375_B0r */
  33759         soc_block_list[61],
  33760         soc_iprocreg,
  33761         1,
  33762         0,
  33763         0x18021258,
  33764         0,
  33765         0,
  33766         2,
  33767         soc_QSPI_MSPI_TXRAM06_BCM88375_B0r_fields,
  33768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33769         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33770         -1,
  33771         -1,
  33772     },
  33773 #endif /* chips */
  33774 
  33775 #if defined(BCM_88470_A0)
  33776     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM88470_A0r */
  33777         soc_block_list[61],
  33778         soc_iprocreg,
  33779         1,
  33780         0,
  33781         0x18021258,
  33782         0,
  33783         0,
  33784         2,
  33785         soc_QSPI_MSPI_TXRAM06_BCM88470_A0r_fields,
  33786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33787         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33788         -1,
  33789         -1,
  33790     },
  33791 #endif /* chips */
  33792 
  33793 #if defined(BCM_88470_B0)
  33794     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM88470_B0r */
  33795         soc_block_list[61],
  33796         soc_iprocreg,
  33797         1,
  33798         0,
  33799         0x18021258,
  33800         0,
  33801         0,
  33802         2,
  33803         soc_QSPI_MSPI_TXRAM06_BCM88470_B0r_fields,
  33804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33805         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33806         -1,
  33807         -1,
  33808     },
  33809 #endif /* chips */
  33810 
  33811 #if defined(BCM_88675_B0)
  33812     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM88675_B0r */
  33813         soc_block_list[61],
  33814         soc_iprocreg,
  33815         1,
  33816         0,
  33817         0x18021258,
  33818         0,
  33819         0,
  33820         2,
  33821         soc_QSPI_MSPI_TXRAM06_BCM88675_B0r_fields,
  33822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33823         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33824         -1,
  33825         -1,
  33826     },
  33827 #endif /* chips */
  33828 
  33829 #if defined(BCM_88680_A0)
  33830     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM88680_A0r */
  33831         soc_block_list[61],
  33832         soc_iprocreg,
  33833         1,
  33834         0,
  33835         0x18021258,
  33836         0,
  33837         0,
  33838         2,
  33839         soc_QSPI_MSPI_TXRAM06_BCM88680_A0r_fields,
  33840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33842         -1,
  33843         -1,
  33844     },
  33845 #endif /* chips */
  33846 
  33847 #if defined(BCM_88690_A0)
  33848     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM88690_A0r */
  33849         soc_block_list[61],
  33850         soc_iprocreg,
  33851         1,
  33852         0,
  33853         0x18021258,
  33854         0,
  33855         0,
  33856         2,
  33857         soc_QSPI_MSPI_TXRAM06_BCM88690_A0r_fields,
  33858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33859         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33860         -1,
  33861         -1,
  33862     },
  33863 #endif /* chips */
  33864 
  33865 #if defined(BCM_88690_B0)
  33866     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM88690_B0r */
  33867         soc_block_list[61],
  33868         soc_iprocreg,
  33869         1,
  33870         0,
  33871         0x18021258,
  33872         0,
  33873         0,
  33874         2,
  33875         soc_QSPI_MSPI_TXRAM06_BCM88690_B0r_fields,
  33876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33878         -1,
  33879         -1,
  33880     },
  33881 #endif /* chips */
  33882 
  33883 #if defined(BCM_88790_A0)
  33884     { /* SOC_REG_INT_QSPI_MSPI_TXRAM06_BCM88790_A0r */
  33885         soc_block_list[61],
  33886         soc_iprocreg,
  33887         1,
  33888         0,
  33889         0x18021258,
  33890         0,
  33891         0,
  33892         2,
  33893         soc_QSPI_MSPI_TXRAM06_BCM88790_A0r_fields,
  33894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33895         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33896         -1,
  33897         -1,
  33898     },
  33899 #endif /* chips */
  33900 
  33901 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  33902     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  33903     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  33904     defined(BCM_56260_B0)
  33905     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM53400_A0r */
  33906         soc_block_list[61],
  33907         soc_iprocreg,
  33908         1,
  33909         0,
  33910         0x1804725c,
  33911         0,
  33912         0,
  33913         2,
  33914         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33916         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33917         -1,
  33918         -1,
  33919     },
  33920 #endif /* chips */
  33921 
  33922 #if defined(BCM_56370_A0)
  33923     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM56370_A0r */
  33924         soc_block_list[61],
  33925         soc_iprocreg,
  33926         1,
  33927         0,
  33928         0x1500025c,
  33929         0,
  33930         0,
  33931         2,
  33932         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33934         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33935         -1,
  33936         -1,
  33937         3,
  33938     },
  33939 #endif /* chips */
  33940 
  33941 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  33942     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  33943     defined(BCM_56450_B1)
  33944     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM56450_A0r */
  33945         soc_block_list[61],
  33946         soc_iprocreg,
  33947         1,
  33948         0,
  33949         0x1802725c,
  33950         0,
  33951         0,
  33952         2,
  33953         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  33954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33956         -1,
  33957         -1,
  33958     },
  33959 #endif /* chips */
  33960 
  33961 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  33962     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  33963     defined(BCM_56670_B0)
  33964     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM56560_A0r */
  33965         soc_block_list[61],
  33966         soc_iprocreg,
  33967         1,
  33968         0,
  33969         0x1802125c,
  33970         0,
  33971         0,
  33972         2,
  33973         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33975         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33976         -1,
  33977         -1,
  33978     },
  33979 #endif /* chips */
  33980 
  33981 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  33982     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  33983     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  33984     defined(BCM_56980_B0)
  33985     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM56960_A0r */
  33986         soc_block_list[61],
  33987         soc_iprocreg,
  33988         1,
  33989         0,
  33990         0x1802125c,
  33991         0,
  33992         0,
  33993         2,
  33994         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  33995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33997         -1,
  33998         -1,
  33999         3,
  34000     },
  34001 #endif /* chips */
  34002 
  34003 #if defined(BCM_88270_A0)
  34004     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM88270_A0r */
  34005         soc_block_list[61],
  34006         soc_iprocreg,
  34007         1,
  34008         0,
  34009         0x1802125c,
  34010         0,
  34011         0,
  34012         2,
  34013         soc_QSPI_MSPI_TXRAM07_BCM88270_A0r_fields,
  34014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34016         -1,
  34017         -1,
  34018     },
  34019 #endif /* chips */
  34020 
  34021 #if defined(BCM_88375_A0)
  34022     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM88375_A0r */
  34023         soc_block_list[61],
  34024         soc_iprocreg,
  34025         1,
  34026         0,
  34027         0x1802125c,
  34028         0,
  34029         0,
  34030         2,
  34031         soc_QSPI_MSPI_TXRAM07_BCM88375_A0r_fields,
  34032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34034         -1,
  34035         -1,
  34036     },
  34037 #endif /* chips */
  34038 
  34039 #if defined(BCM_88375_B0)
  34040     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM88375_B0r */
  34041         soc_block_list[61],
  34042         soc_iprocreg,
  34043         1,
  34044         0,
  34045         0x1802125c,
  34046         0,
  34047         0,
  34048         2,
  34049         soc_QSPI_MSPI_TXRAM07_BCM88375_B0r_fields,
  34050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34051         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34052         -1,
  34053         -1,
  34054     },
  34055 #endif /* chips */
  34056 
  34057 #if defined(BCM_88470_A0)
  34058     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM88470_A0r */
  34059         soc_block_list[61],
  34060         soc_iprocreg,
  34061         1,
  34062         0,
  34063         0x1802125c,
  34064         0,
  34065         0,
  34066         2,
  34067         soc_QSPI_MSPI_TXRAM07_BCM88470_A0r_fields,
  34068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34069         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34070         -1,
  34071         -1,
  34072     },
  34073 #endif /* chips */
  34074 
  34075 #if defined(BCM_88470_B0)
  34076     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM88470_B0r */
  34077         soc_block_list[61],
  34078         soc_iprocreg,
  34079         1,
  34080         0,
  34081         0x1802125c,
  34082         0,
  34083         0,
  34084         2,
  34085         soc_QSPI_MSPI_TXRAM07_BCM88470_B0r_fields,
  34086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34087         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34088         -1,
  34089         -1,
  34090     },
  34091 #endif /* chips */
  34092 
  34093 #if defined(BCM_88675_B0)
  34094     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM88675_B0r */
  34095         soc_block_list[61],
  34096         soc_iprocreg,
  34097         1,
  34098         0,
  34099         0x1802125c,
  34100         0,
  34101         0,
  34102         2,
  34103         soc_QSPI_MSPI_TXRAM07_BCM88675_B0r_fields,
  34104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34105         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34106         -1,
  34107         -1,
  34108     },
  34109 #endif /* chips */
  34110 
  34111 #if defined(BCM_88680_A0)
  34112     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM88680_A0r */
  34113         soc_block_list[61],
  34114         soc_iprocreg,
  34115         1,
  34116         0,
  34117         0x1802125c,
  34118         0,
  34119         0,
  34120         2,
  34121         soc_QSPI_MSPI_TXRAM07_BCM88680_A0r_fields,
  34122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34123         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34124         -1,
  34125         -1,
  34126     },
  34127 #endif /* chips */
  34128 
  34129 #if defined(BCM_88690_A0)
  34130     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM88690_A0r */
  34131         soc_block_list[61],
  34132         soc_iprocreg,
  34133         1,
  34134         0,
  34135         0x1802125c,
  34136         0,
  34137         0,
  34138         2,
  34139         soc_QSPI_MSPI_TXRAM07_BCM88690_A0r_fields,
  34140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34141         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34142         -1,
  34143         -1,
  34144     },
  34145 #endif /* chips */
  34146 
  34147 #if defined(BCM_88690_B0)
  34148     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM88690_B0r */
  34149         soc_block_list[61],
  34150         soc_iprocreg,
  34151         1,
  34152         0,
  34153         0x1802125c,
  34154         0,
  34155         0,
  34156         2,
  34157         soc_QSPI_MSPI_TXRAM07_BCM88690_B0r_fields,
  34158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34159         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34160         -1,
  34161         -1,
  34162     },
  34163 #endif /* chips */
  34164 
  34165 #if defined(BCM_88790_A0)
  34166     { /* SOC_REG_INT_QSPI_MSPI_TXRAM07_BCM88790_A0r */
  34167         soc_block_list[61],
  34168         soc_iprocreg,
  34169         1,
  34170         0,
  34171         0x1802125c,
  34172         0,
  34173         0,
  34174         2,
  34175         soc_QSPI_MSPI_TXRAM07_BCM88790_A0r_fields,
  34176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34177         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34178         -1,
  34179         -1,
  34180     },
  34181 #endif /* chips */
  34182 
  34183 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  34184     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  34185     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  34186     defined(BCM_56260_B0)
  34187     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM53400_A0r */
  34188         soc_block_list[61],
  34189         soc_iprocreg,
  34190         1,
  34191         0,
  34192         0x18047260,
  34193         0,
  34194         0,
  34195         2,
  34196         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34198         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34199         -1,
  34200         -1,
  34201     },
  34202 #endif /* chips */
  34203 
  34204 #if defined(BCM_56370_A0)
  34205     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM56370_A0r */
  34206         soc_block_list[61],
  34207         soc_iprocreg,
  34208         1,
  34209         0,
  34210         0x15000260,
  34211         0,
  34212         0,
  34213         2,
  34214         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34216         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34217         -1,
  34218         -1,
  34219         3,
  34220     },
  34221 #endif /* chips */
  34222 
  34223 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  34224     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  34225     defined(BCM_56450_B1)
  34226     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM56450_A0r */
  34227         soc_block_list[61],
  34228         soc_iprocreg,
  34229         1,
  34230         0,
  34231         0x18027260,
  34232         0,
  34233         0,
  34234         2,
  34235         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  34236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34237         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34238         -1,
  34239         -1,
  34240     },
  34241 #endif /* chips */
  34242 
  34243 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  34244     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  34245     defined(BCM_56670_B0)
  34246     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM56560_A0r */
  34247         soc_block_list[61],
  34248         soc_iprocreg,
  34249         1,
  34250         0,
  34251         0x18021260,
  34252         0,
  34253         0,
  34254         2,
  34255         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34258         -1,
  34259         -1,
  34260     },
  34261 #endif /* chips */
  34262 
  34263 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  34264     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  34265     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  34266     defined(BCM_56980_B0)
  34267     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM56960_A0r */
  34268         soc_block_list[61],
  34269         soc_iprocreg,
  34270         1,
  34271         0,
  34272         0x18021260,
  34273         0,
  34274         0,
  34275         2,
  34276         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34278         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34279         -1,
  34280         -1,
  34281         3,
  34282     },
  34283 #endif /* chips */
  34284 
  34285 #if defined(BCM_88270_A0)
  34286     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM88270_A0r */
  34287         soc_block_list[61],
  34288         soc_iprocreg,
  34289         1,
  34290         0,
  34291         0x18021260,
  34292         0,
  34293         0,
  34294         2,
  34295         soc_QSPI_MSPI_TXRAM08_BCM88270_A0r_fields,
  34296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34298         -1,
  34299         -1,
  34300     },
  34301 #endif /* chips */
  34302 
  34303 #if defined(BCM_88375_A0)
  34304     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM88375_A0r */
  34305         soc_block_list[61],
  34306         soc_iprocreg,
  34307         1,
  34308         0,
  34309         0x18021260,
  34310         0,
  34311         0,
  34312         2,
  34313         soc_QSPI_MSPI_TXRAM08_BCM88375_A0r_fields,
  34314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34315         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34316         -1,
  34317         -1,
  34318     },
  34319 #endif /* chips */
  34320 
  34321 #if defined(BCM_88375_B0)
  34322     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM88375_B0r */
  34323         soc_block_list[61],
  34324         soc_iprocreg,
  34325         1,
  34326         0,
  34327         0x18021260,
  34328         0,
  34329         0,
  34330         2,
  34331         soc_QSPI_MSPI_TXRAM08_BCM88375_B0r_fields,
  34332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34333         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34334         -1,
  34335         -1,
  34336     },
  34337 #endif /* chips */
  34338 
  34339 #if defined(BCM_88470_A0)
  34340     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM88470_A0r */
  34341         soc_block_list[61],
  34342         soc_iprocreg,
  34343         1,
  34344         0,
  34345         0x18021260,
  34346         0,
  34347         0,
  34348         2,
  34349         soc_QSPI_MSPI_TXRAM08_BCM88470_A0r_fields,
  34350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34351         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34352         -1,
  34353         -1,
  34354     },
  34355 #endif /* chips */
  34356 
  34357 #if defined(BCM_88470_B0)
  34358     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM88470_B0r */
  34359         soc_block_list[61],
  34360         soc_iprocreg,
  34361         1,
  34362         0,
  34363         0x18021260,
  34364         0,
  34365         0,
  34366         2,
  34367         soc_QSPI_MSPI_TXRAM08_BCM88470_B0r_fields,
  34368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34369         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34370         -1,
  34371         -1,
  34372     },
  34373 #endif /* chips */
  34374 
  34375 #if defined(BCM_88675_B0)
  34376     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM88675_B0r */
  34377         soc_block_list[61],
  34378         soc_iprocreg,
  34379         1,
  34380         0,
  34381         0x18021260,
  34382         0,
  34383         0,
  34384         2,
  34385         soc_QSPI_MSPI_TXRAM08_BCM88675_B0r_fields,
  34386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34387         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34388         -1,
  34389         -1,
  34390     },
  34391 #endif /* chips */
  34392 
  34393 #if defined(BCM_88680_A0)
  34394     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM88680_A0r */
  34395         soc_block_list[61],
  34396         soc_iprocreg,
  34397         1,
  34398         0,
  34399         0x18021260,
  34400         0,
  34401         0,
  34402         2,
  34403         soc_QSPI_MSPI_TXRAM08_BCM88680_A0r_fields,
  34404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34405         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34406         -1,
  34407         -1,
  34408     },
  34409 #endif /* chips */
  34410 
  34411 #if defined(BCM_88690_A0)
  34412     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM88690_A0r */
  34413         soc_block_list[61],
  34414         soc_iprocreg,
  34415         1,
  34416         0,
  34417         0x18021260,
  34418         0,
  34419         0,
  34420         2,
  34421         soc_QSPI_MSPI_TXRAM08_BCM88690_A0r_fields,
  34422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34423         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34424         -1,
  34425         -1,
  34426     },
  34427 #endif /* chips */
  34428 
  34429 #if defined(BCM_88690_B0)
  34430     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM88690_B0r */
  34431         soc_block_list[61],
  34432         soc_iprocreg,
  34433         1,
  34434         0,
  34435         0x18021260,
  34436         0,
  34437         0,
  34438         2,
  34439         soc_QSPI_MSPI_TXRAM08_BCM88690_B0r_fields,
  34440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34441         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34442         -1,
  34443         -1,
  34444     },
  34445 #endif /* chips */
  34446 
  34447 #if defined(BCM_88790_A0)
  34448     { /* SOC_REG_INT_QSPI_MSPI_TXRAM08_BCM88790_A0r */
  34449         soc_block_list[61],
  34450         soc_iprocreg,
  34451         1,
  34452         0,
  34453         0x18021260,
  34454         0,
  34455         0,
  34456         2,
  34457         soc_QSPI_MSPI_TXRAM08_BCM88790_A0r_fields,
  34458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34459         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34460         -1,
  34461         -1,
  34462     },
  34463 #endif /* chips */
  34464 
  34465 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  34466     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  34467     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  34468     defined(BCM_56260_B0)
  34469     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM53400_A0r */
  34470         soc_block_list[61],
  34471         soc_iprocreg,
  34472         1,
  34473         0,
  34474         0x18047264,
  34475         0,
  34476         0,
  34477         2,
  34478         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34480         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34481         -1,
  34482         -1,
  34483     },
  34484 #endif /* chips */
  34485 
  34486 #if defined(BCM_56370_A0)
  34487     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM56370_A0r */
  34488         soc_block_list[61],
  34489         soc_iprocreg,
  34490         1,
  34491         0,
  34492         0x15000264,
  34493         0,
  34494         0,
  34495         2,
  34496         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34498         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34499         -1,
  34500         -1,
  34501         3,
  34502     },
  34503 #endif /* chips */
  34504 
  34505 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  34506     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  34507     defined(BCM_56450_B1)
  34508     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM56450_A0r */
  34509         soc_block_list[61],
  34510         soc_iprocreg,
  34511         1,
  34512         0,
  34513         0x18027264,
  34514         0,
  34515         0,
  34516         2,
  34517         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  34518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34519         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34520         -1,
  34521         -1,
  34522     },
  34523 #endif /* chips */
  34524 
  34525 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  34526     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  34527     defined(BCM_56670_B0)
  34528     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM56560_A0r */
  34529         soc_block_list[61],
  34530         soc_iprocreg,
  34531         1,
  34532         0,
  34533         0x18021264,
  34534         0,
  34535         0,
  34536         2,
  34537         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34539         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34540         -1,
  34541         -1,
  34542     },
  34543 #endif /* chips */
  34544 
  34545 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  34546     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  34547     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  34548     defined(BCM_56980_B0)
  34549     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM56960_A0r */
  34550         soc_block_list[61],
  34551         soc_iprocreg,
  34552         1,
  34553         0,
  34554         0x18021264,
  34555         0,
  34556         0,
  34557         2,
  34558         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34560         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34561         -1,
  34562         -1,
  34563         3,
  34564     },
  34565 #endif /* chips */
  34566 
  34567 #if defined(BCM_88270_A0)
  34568     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM88270_A0r */
  34569         soc_block_list[61],
  34570         soc_iprocreg,
  34571         1,
  34572         0,
  34573         0x18021264,
  34574         0,
  34575         0,
  34576         2,
  34577         soc_QSPI_MSPI_TXRAM09_BCM88270_A0r_fields,
  34578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34579         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34580         -1,
  34581         -1,
  34582     },
  34583 #endif /* chips */
  34584 
  34585 #if defined(BCM_88375_A0)
  34586     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM88375_A0r */
  34587         soc_block_list[61],
  34588         soc_iprocreg,
  34589         1,
  34590         0,
  34591         0x18021264,
  34592         0,
  34593         0,
  34594         2,
  34595         soc_QSPI_MSPI_TXRAM09_BCM88375_A0r_fields,
  34596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34597         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34598         -1,
  34599         -1,
  34600     },
  34601 #endif /* chips */
  34602 
  34603 #if defined(BCM_88375_B0)
  34604     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM88375_B0r */
  34605         soc_block_list[61],
  34606         soc_iprocreg,
  34607         1,
  34608         0,
  34609         0x18021264,
  34610         0,
  34611         0,
  34612         2,
  34613         soc_QSPI_MSPI_TXRAM09_BCM88375_B0r_fields,
  34614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34615         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34616         -1,
  34617         -1,
  34618     },
  34619 #endif /* chips */
  34620 
  34621 #if defined(BCM_88470_A0)
  34622     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM88470_A0r */
  34623         soc_block_list[61],
  34624         soc_iprocreg,
  34625         1,
  34626         0,
  34627         0x18021264,
  34628         0,
  34629         0,
  34630         2,
  34631         soc_QSPI_MSPI_TXRAM09_BCM88470_A0r_fields,
  34632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34633         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34634         -1,
  34635         -1,
  34636     },
  34637 #endif /* chips */
  34638 
  34639 #if defined(BCM_88470_B0)
  34640     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM88470_B0r */
  34641         soc_block_list[61],
  34642         soc_iprocreg,
  34643         1,
  34644         0,
  34645         0x18021264,
  34646         0,
  34647         0,
  34648         2,
  34649         soc_QSPI_MSPI_TXRAM09_BCM88470_B0r_fields,
  34650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34651         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34652         -1,
  34653         -1,
  34654     },
  34655 #endif /* chips */
  34656 
  34657 #if defined(BCM_88675_B0)
  34658     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM88675_B0r */
  34659         soc_block_list[61],
  34660         soc_iprocreg,
  34661         1,
  34662         0,
  34663         0x18021264,
  34664         0,
  34665         0,
  34666         2,
  34667         soc_QSPI_MSPI_TXRAM09_BCM88675_B0r_fields,
  34668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34670         -1,
  34671         -1,
  34672     },
  34673 #endif /* chips */
  34674 
  34675 #if defined(BCM_88680_A0)
  34676     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM88680_A0r */
  34677         soc_block_list[61],
  34678         soc_iprocreg,
  34679         1,
  34680         0,
  34681         0x18021264,
  34682         0,
  34683         0,
  34684         2,
  34685         soc_QSPI_MSPI_TXRAM09_BCM88680_A0r_fields,
  34686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34687         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34688         -1,
  34689         -1,
  34690     },
  34691 #endif /* chips */
  34692 
  34693 #if defined(BCM_88690_A0)
  34694     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM88690_A0r */
  34695         soc_block_list[61],
  34696         soc_iprocreg,
  34697         1,
  34698         0,
  34699         0x18021264,
  34700         0,
  34701         0,
  34702         2,
  34703         soc_QSPI_MSPI_TXRAM09_BCM88690_A0r_fields,
  34704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34705         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34706         -1,
  34707         -1,
  34708     },
  34709 #endif /* chips */
  34710 
  34711 #if defined(BCM_88690_B0)
  34712     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM88690_B0r */
  34713         soc_block_list[61],
  34714         soc_iprocreg,
  34715         1,
  34716         0,
  34717         0x18021264,
  34718         0,
  34719         0,
  34720         2,
  34721         soc_QSPI_MSPI_TXRAM09_BCM88690_B0r_fields,
  34722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34723         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34724         -1,
  34725         -1,
  34726     },
  34727 #endif /* chips */
  34728 
  34729 #if defined(BCM_88790_A0)
  34730     { /* SOC_REG_INT_QSPI_MSPI_TXRAM09_BCM88790_A0r */
  34731         soc_block_list[61],
  34732         soc_iprocreg,
  34733         1,
  34734         0,
  34735         0x18021264,
  34736         0,
  34737         0,
  34738         2,
  34739         soc_QSPI_MSPI_TXRAM09_BCM88790_A0r_fields,
  34740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34741         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34742         -1,
  34743         -1,
  34744     },
  34745 #endif /* chips */
  34746 
  34747 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  34748     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  34749     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  34750     defined(BCM_56260_B0)
  34751     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM53400_A0r */
  34752         soc_block_list[61],
  34753         soc_iprocreg,
  34754         1,
  34755         0,
  34756         0x18047268,
  34757         0,
  34758         0,
  34759         2,
  34760         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34762         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34763         -1,
  34764         -1,
  34765     },
  34766 #endif /* chips */
  34767 
  34768 #if defined(BCM_56370_A0)
  34769     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM56370_A0r */
  34770         soc_block_list[61],
  34771         soc_iprocreg,
  34772         1,
  34773         0,
  34774         0x15000268,
  34775         0,
  34776         0,
  34777         2,
  34778         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34780         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34781         -1,
  34782         -1,
  34783         3,
  34784     },
  34785 #endif /* chips */
  34786 
  34787 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  34788     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  34789     defined(BCM_56450_B1)
  34790     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM56450_A0r */
  34791         soc_block_list[61],
  34792         soc_iprocreg,
  34793         1,
  34794         0,
  34795         0x18027268,
  34796         0,
  34797         0,
  34798         2,
  34799         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  34800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34801         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34802         -1,
  34803         -1,
  34804     },
  34805 #endif /* chips */
  34806 
  34807 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  34808     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  34809     defined(BCM_56670_B0)
  34810     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM56560_A0r */
  34811         soc_block_list[61],
  34812         soc_iprocreg,
  34813         1,
  34814         0,
  34815         0x18021268,
  34816         0,
  34817         0,
  34818         2,
  34819         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34821         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34822         -1,
  34823         -1,
  34824     },
  34825 #endif /* chips */
  34826 
  34827 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  34828     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  34829     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  34830     defined(BCM_56980_B0)
  34831     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM56960_A0r */
  34832         soc_block_list[61],
  34833         soc_iprocreg,
  34834         1,
  34835         0,
  34836         0x18021268,
  34837         0,
  34838         0,
  34839         2,
  34840         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  34841         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34842         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34843         -1,
  34844         -1,
  34845         3,
  34846     },
  34847 #endif /* chips */
  34848 
  34849 #if defined(BCM_88270_A0)
  34850     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM88270_A0r */
  34851         soc_block_list[61],
  34852         soc_iprocreg,
  34853         1,
  34854         0,
  34855         0x18021268,
  34856         0,
  34857         0,
  34858         2,
  34859         soc_QSPI_MSPI_TXRAM10_BCM88270_A0r_fields,
  34860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34861         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34862         -1,
  34863         -1,
  34864     },
  34865 #endif /* chips */
  34866 
  34867 #if defined(BCM_88375_A0)
  34868     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM88375_A0r */
  34869         soc_block_list[61],
  34870         soc_iprocreg,
  34871         1,
  34872         0,
  34873         0x18021268,
  34874         0,
  34875         0,
  34876         2,
  34877         soc_QSPI_MSPI_TXRAM10_BCM88375_A0r_fields,
  34878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34879         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34880         -1,
  34881         -1,
  34882     },
  34883 #endif /* chips */
  34884 
  34885 #if defined(BCM_88375_B0)
  34886     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM88375_B0r */
  34887         soc_block_list[61],
  34888         soc_iprocreg,
  34889         1,
  34890         0,
  34891         0x18021268,
  34892         0,
  34893         0,
  34894         2,
  34895         soc_QSPI_MSPI_TXRAM10_BCM88375_B0r_fields,
  34896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34898         -1,
  34899         -1,
  34900     },
  34901 #endif /* chips */
  34902 
  34903 #if defined(BCM_88470_A0)
  34904     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM88470_A0r */
  34905         soc_block_list[61],
  34906         soc_iprocreg,
  34907         1,
  34908         0,
  34909         0x18021268,
  34910         0,
  34911         0,
  34912         2,
  34913         soc_QSPI_MSPI_TXRAM10_BCM88470_A0r_fields,
  34914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34916         -1,
  34917         -1,
  34918     },
  34919 #endif /* chips */
  34920 
  34921 #if defined(BCM_88470_B0)
  34922     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM88470_B0r */
  34923         soc_block_list[61],
  34924         soc_iprocreg,
  34925         1,
  34926         0,
  34927         0x18021268,
  34928         0,
  34929         0,
  34930         2,
  34931         soc_QSPI_MSPI_TXRAM10_BCM88470_B0r_fields,
  34932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34933         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34934         -1,
  34935         -1,
  34936     },
  34937 #endif /* chips */
  34938 
  34939 #if defined(BCM_88675_B0)
  34940     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM88675_B0r */
  34941         soc_block_list[61],
  34942         soc_iprocreg,
  34943         1,
  34944         0,
  34945         0x18021268,
  34946         0,
  34947         0,
  34948         2,
  34949         soc_QSPI_MSPI_TXRAM10_BCM88675_B0r_fields,
  34950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34952         -1,
  34953         -1,
  34954     },
  34955 #endif /* chips */
  34956 
  34957 #if defined(BCM_88680_A0)
  34958     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM88680_A0r */
  34959         soc_block_list[61],
  34960         soc_iprocreg,
  34961         1,
  34962         0,
  34963         0x18021268,
  34964         0,
  34965         0,
  34966         2,
  34967         soc_QSPI_MSPI_TXRAM10_BCM88680_A0r_fields,
  34968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34969         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34970         -1,
  34971         -1,
  34972     },
  34973 #endif /* chips */
  34974 
  34975 #if defined(BCM_88690_A0)
  34976     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM88690_A0r */
  34977         soc_block_list[61],
  34978         soc_iprocreg,
  34979         1,
  34980         0,
  34981         0x18021268,
  34982         0,
  34983         0,
  34984         2,
  34985         soc_QSPI_MSPI_TXRAM10_BCM88690_A0r_fields,
  34986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34987         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34988         -1,
  34989         -1,
  34990     },
  34991 #endif /* chips */
  34992 
  34993 #if defined(BCM_88690_B0)
  34994     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM88690_B0r */
  34995         soc_block_list[61],
  34996         soc_iprocreg,
  34997         1,
  34998         0,
  34999         0x18021268,
  35000         0,
  35001         0,
  35002         2,
  35003         soc_QSPI_MSPI_TXRAM10_BCM88690_B0r_fields,
  35004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35005         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35006         -1,
  35007         -1,
  35008     },
  35009 #endif /* chips */
  35010 
  35011 #if defined(BCM_88790_A0)
  35012     { /* SOC_REG_INT_QSPI_MSPI_TXRAM10_BCM88790_A0r */
  35013         soc_block_list[61],
  35014         soc_iprocreg,
  35015         1,
  35016         0,
  35017         0x18021268,
  35018         0,
  35019         0,
  35020         2,
  35021         soc_QSPI_MSPI_TXRAM10_BCM88790_A0r_fields,
  35022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35023         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35024         -1,
  35025         -1,
  35026     },
  35027 #endif /* chips */
  35028 
  35029 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35030     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35031     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35032     defined(BCM_56260_B0)
  35033     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM53400_A0r */
  35034         soc_block_list[61],
  35035         soc_iprocreg,
  35036         1,
  35037         0,
  35038         0x1804726c,
  35039         0,
  35040         0,
  35041         2,
  35042         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35044         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35045         -1,
  35046         -1,
  35047     },
  35048 #endif /* chips */
  35049 
  35050 #if defined(BCM_56370_A0)
  35051     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM56370_A0r */
  35052         soc_block_list[61],
  35053         soc_iprocreg,
  35054         1,
  35055         0,
  35056         0x1500026c,
  35057         0,
  35058         0,
  35059         2,
  35060         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35062         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35063         -1,
  35064         -1,
  35065         3,
  35066     },
  35067 #endif /* chips */
  35068 
  35069 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  35070     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  35071     defined(BCM_56450_B1)
  35072     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM56450_A0r */
  35073         soc_block_list[61],
  35074         soc_iprocreg,
  35075         1,
  35076         0,
  35077         0x1802726c,
  35078         0,
  35079         0,
  35080         2,
  35081         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  35082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35083         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35084         -1,
  35085         -1,
  35086     },
  35087 #endif /* chips */
  35088 
  35089 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  35090     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  35091     defined(BCM_56670_B0)
  35092     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM56560_A0r */
  35093         soc_block_list[61],
  35094         soc_iprocreg,
  35095         1,
  35096         0,
  35097         0x1802126c,
  35098         0,
  35099         0,
  35100         2,
  35101         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35103         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35104         -1,
  35105         -1,
  35106     },
  35107 #endif /* chips */
  35108 
  35109 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  35110     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  35111     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  35112     defined(BCM_56980_B0)
  35113     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM56960_A0r */
  35114         soc_block_list[61],
  35115         soc_iprocreg,
  35116         1,
  35117         0,
  35118         0x1802126c,
  35119         0,
  35120         0,
  35121         2,
  35122         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35124         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35125         -1,
  35126         -1,
  35127         3,
  35128     },
  35129 #endif /* chips */
  35130 
  35131 #if defined(BCM_88270_A0)
  35132     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM88270_A0r */
  35133         soc_block_list[61],
  35134         soc_iprocreg,
  35135         1,
  35136         0,
  35137         0x1802126c,
  35138         0,
  35139         0,
  35140         2,
  35141         soc_QSPI_MSPI_TXRAM11_BCM88270_A0r_fields,
  35142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35143         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35144         -1,
  35145         -1,
  35146     },
  35147 #endif /* chips */
  35148 
  35149 #if defined(BCM_88375_A0)
  35150     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM88375_A0r */
  35151         soc_block_list[61],
  35152         soc_iprocreg,
  35153         1,
  35154         0,
  35155         0x1802126c,
  35156         0,
  35157         0,
  35158         2,
  35159         soc_QSPI_MSPI_TXRAM11_BCM88375_A0r_fields,
  35160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35161         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35162         -1,
  35163         -1,
  35164     },
  35165 #endif /* chips */
  35166 
  35167 #if defined(BCM_88375_B0)
  35168     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM88375_B0r */
  35169         soc_block_list[61],
  35170         soc_iprocreg,
  35171         1,
  35172         0,
  35173         0x1802126c,
  35174         0,
  35175         0,
  35176         2,
  35177         soc_QSPI_MSPI_TXRAM11_BCM88375_B0r_fields,
  35178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35179         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35180         -1,
  35181         -1,
  35182     },
  35183 #endif /* chips */
  35184 
  35185 #if defined(BCM_88470_A0)
  35186     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM88470_A0r */
  35187         soc_block_list[61],
  35188         soc_iprocreg,
  35189         1,
  35190         0,
  35191         0x1802126c,
  35192         0,
  35193         0,
  35194         2,
  35195         soc_QSPI_MSPI_TXRAM11_BCM88470_A0r_fields,
  35196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35197         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35198         -1,
  35199         -1,
  35200     },
  35201 #endif /* chips */
  35202 
  35203 #if defined(BCM_88470_B0)
  35204     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM88470_B0r */
  35205         soc_block_list[61],
  35206         soc_iprocreg,
  35207         1,
  35208         0,
  35209         0x1802126c,
  35210         0,
  35211         0,
  35212         2,
  35213         soc_QSPI_MSPI_TXRAM11_BCM88470_B0r_fields,
  35214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35215         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35216         -1,
  35217         -1,
  35218     },
  35219 #endif /* chips */
  35220 
  35221 #if defined(BCM_88675_B0)
  35222     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM88675_B0r */
  35223         soc_block_list[61],
  35224         soc_iprocreg,
  35225         1,
  35226         0,
  35227         0x1802126c,
  35228         0,
  35229         0,
  35230         2,
  35231         soc_QSPI_MSPI_TXRAM11_BCM88675_B0r_fields,
  35232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35233         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35234         -1,
  35235         -1,
  35236     },
  35237 #endif /* chips */
  35238 
  35239 #if defined(BCM_88680_A0)
  35240     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM88680_A0r */
  35241         soc_block_list[61],
  35242         soc_iprocreg,
  35243         1,
  35244         0,
  35245         0x1802126c,
  35246         0,
  35247         0,
  35248         2,
  35249         soc_QSPI_MSPI_TXRAM11_BCM88680_A0r_fields,
  35250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35251         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35252         -1,
  35253         -1,
  35254     },
  35255 #endif /* chips */
  35256 
  35257 #if defined(BCM_88690_A0)
  35258     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM88690_A0r */
  35259         soc_block_list[61],
  35260         soc_iprocreg,
  35261         1,
  35262         0,
  35263         0x1802126c,
  35264         0,
  35265         0,
  35266         2,
  35267         soc_QSPI_MSPI_TXRAM11_BCM88690_A0r_fields,
  35268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35269         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35270         -1,
  35271         -1,
  35272     },
  35273 #endif /* chips */
  35274 
  35275 #if defined(BCM_88690_B0)
  35276     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM88690_B0r */
  35277         soc_block_list[61],
  35278         soc_iprocreg,
  35279         1,
  35280         0,
  35281         0x1802126c,
  35282         0,
  35283         0,
  35284         2,
  35285         soc_QSPI_MSPI_TXRAM11_BCM88690_B0r_fields,
  35286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35287         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35288         -1,
  35289         -1,
  35290     },
  35291 #endif /* chips */
  35292 
  35293 #if defined(BCM_88790_A0)
  35294     { /* SOC_REG_INT_QSPI_MSPI_TXRAM11_BCM88790_A0r */
  35295         soc_block_list[61],
  35296         soc_iprocreg,
  35297         1,
  35298         0,
  35299         0x1802126c,
  35300         0,
  35301         0,
  35302         2,
  35303         soc_QSPI_MSPI_TXRAM11_BCM88790_A0r_fields,
  35304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35305         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35306         -1,
  35307         -1,
  35308     },
  35309 #endif /* chips */
  35310 
  35311 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35312     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35313     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35314     defined(BCM_56260_B0)
  35315     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM53400_A0r */
  35316         soc_block_list[61],
  35317         soc_iprocreg,
  35318         1,
  35319         0,
  35320         0x18047270,
  35321         0,
  35322         0,
  35323         2,
  35324         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35326         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35327         -1,
  35328         -1,
  35329     },
  35330 #endif /* chips */
  35331 
  35332 #if defined(BCM_56370_A0)
  35333     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM56370_A0r */
  35334         soc_block_list[61],
  35335         soc_iprocreg,
  35336         1,
  35337         0,
  35338         0x15000270,
  35339         0,
  35340         0,
  35341         2,
  35342         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35344         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35345         -1,
  35346         -1,
  35347         3,
  35348     },
  35349 #endif /* chips */
  35350 
  35351 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  35352     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  35353     defined(BCM_56450_B1)
  35354     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM56450_A0r */
  35355         soc_block_list[61],
  35356         soc_iprocreg,
  35357         1,
  35358         0,
  35359         0x18027270,
  35360         0,
  35361         0,
  35362         2,
  35363         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  35364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35365         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35366         -1,
  35367         -1,
  35368     },
  35369 #endif /* chips */
  35370 
  35371 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  35372     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  35373     defined(BCM_56670_B0)
  35374     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM56560_A0r */
  35375         soc_block_list[61],
  35376         soc_iprocreg,
  35377         1,
  35378         0,
  35379         0x18021270,
  35380         0,
  35381         0,
  35382         2,
  35383         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35385         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35386         -1,
  35387         -1,
  35388     },
  35389 #endif /* chips */
  35390 
  35391 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  35392     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  35393     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  35394     defined(BCM_56980_B0)
  35395     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM56960_A0r */
  35396         soc_block_list[61],
  35397         soc_iprocreg,
  35398         1,
  35399         0,
  35400         0x18021270,
  35401         0,
  35402         0,
  35403         2,
  35404         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35406         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35407         -1,
  35408         -1,
  35409         3,
  35410     },
  35411 #endif /* chips */
  35412 
  35413 #if defined(BCM_88270_A0)
  35414     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM88270_A0r */
  35415         soc_block_list[61],
  35416         soc_iprocreg,
  35417         1,
  35418         0,
  35419         0x18021270,
  35420         0,
  35421         0,
  35422         2,
  35423         soc_QSPI_MSPI_TXRAM12_BCM88270_A0r_fields,
  35424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35425         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35426         -1,
  35427         -1,
  35428     },
  35429 #endif /* chips */
  35430 
  35431 #if defined(BCM_88375_A0)
  35432     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM88375_A0r */
  35433         soc_block_list[61],
  35434         soc_iprocreg,
  35435         1,
  35436         0,
  35437         0x18021270,
  35438         0,
  35439         0,
  35440         2,
  35441         soc_QSPI_MSPI_TXRAM12_BCM88375_A0r_fields,
  35442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35444         -1,
  35445         -1,
  35446     },
  35447 #endif /* chips */
  35448 
  35449 #if defined(BCM_88375_B0)
  35450     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM88375_B0r */
  35451         soc_block_list[61],
  35452         soc_iprocreg,
  35453         1,
  35454         0,
  35455         0x18021270,
  35456         0,
  35457         0,
  35458         2,
  35459         soc_QSPI_MSPI_TXRAM12_BCM88375_B0r_fields,
  35460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35462         -1,
  35463         -1,
  35464     },
  35465 #endif /* chips */
  35466 
  35467 #if defined(BCM_88470_A0)
  35468     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM88470_A0r */
  35469         soc_block_list[61],
  35470         soc_iprocreg,
  35471         1,
  35472         0,
  35473         0x18021270,
  35474         0,
  35475         0,
  35476         2,
  35477         soc_QSPI_MSPI_TXRAM12_BCM88470_A0r_fields,
  35478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35479         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35480         -1,
  35481         -1,
  35482     },
  35483 #endif /* chips */
  35484 
  35485 #if defined(BCM_88470_B0)
  35486     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM88470_B0r */
  35487         soc_block_list[61],
  35488         soc_iprocreg,
  35489         1,
  35490         0,
  35491         0x18021270,
  35492         0,
  35493         0,
  35494         2,
  35495         soc_QSPI_MSPI_TXRAM12_BCM88470_B0r_fields,
  35496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35498         -1,
  35499         -1,
  35500     },
  35501 #endif /* chips */
  35502 
  35503 #if defined(BCM_88675_B0)
  35504     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM88675_B0r */
  35505         soc_block_list[61],
  35506         soc_iprocreg,
  35507         1,
  35508         0,
  35509         0x18021270,
  35510         0,
  35511         0,
  35512         2,
  35513         soc_QSPI_MSPI_TXRAM12_BCM88675_B0r_fields,
  35514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35516         -1,
  35517         -1,
  35518     },
  35519 #endif /* chips */
  35520 
  35521 #if defined(BCM_88680_A0)
  35522     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM88680_A0r */
  35523         soc_block_list[61],
  35524         soc_iprocreg,
  35525         1,
  35526         0,
  35527         0x18021270,
  35528         0,
  35529         0,
  35530         2,
  35531         soc_QSPI_MSPI_TXRAM12_BCM88680_A0r_fields,
  35532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35534         -1,
  35535         -1,
  35536     },
  35537 #endif /* chips */
  35538 
  35539 #if defined(BCM_88690_A0)
  35540     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM88690_A0r */
  35541         soc_block_list[61],
  35542         soc_iprocreg,
  35543         1,
  35544         0,
  35545         0x18021270,
  35546         0,
  35547         0,
  35548         2,
  35549         soc_QSPI_MSPI_TXRAM12_BCM88690_A0r_fields,
  35550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35551         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35552         -1,
  35553         -1,
  35554     },
  35555 #endif /* chips */
  35556 
  35557 #if defined(BCM_88690_B0)
  35558     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM88690_B0r */
  35559         soc_block_list[61],
  35560         soc_iprocreg,
  35561         1,
  35562         0,
  35563         0x18021270,
  35564         0,
  35565         0,
  35566         2,
  35567         soc_QSPI_MSPI_TXRAM12_BCM88690_B0r_fields,
  35568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35569         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35570         -1,
  35571         -1,
  35572     },
  35573 #endif /* chips */
  35574 
  35575 #if defined(BCM_88790_A0)
  35576     { /* SOC_REG_INT_QSPI_MSPI_TXRAM12_BCM88790_A0r */
  35577         soc_block_list[61],
  35578         soc_iprocreg,
  35579         1,
  35580         0,
  35581         0x18021270,
  35582         0,
  35583         0,
  35584         2,
  35585         soc_QSPI_MSPI_TXRAM12_BCM88790_A0r_fields,
  35586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35587         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35588         -1,
  35589         -1,
  35590     },
  35591 #endif /* chips */
  35592 
  35593 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35594     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35595     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35596     defined(BCM_56260_B0)
  35597     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM53400_A0r */
  35598         soc_block_list[61],
  35599         soc_iprocreg,
  35600         1,
  35601         0,
  35602         0x18047274,
  35603         0,
  35604         0,
  35605         2,
  35606         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35608         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35609         -1,
  35610         -1,
  35611     },
  35612 #endif /* chips */
  35613 
  35614 #if defined(BCM_56370_A0)
  35615     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM56370_A0r */
  35616         soc_block_list[61],
  35617         soc_iprocreg,
  35618         1,
  35619         0,
  35620         0x15000274,
  35621         0,
  35622         0,
  35623         2,
  35624         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35626         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35627         -1,
  35628         -1,
  35629         3,
  35630     },
  35631 #endif /* chips */
  35632 
  35633 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  35634     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  35635     defined(BCM_56450_B1)
  35636     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM56450_A0r */
  35637         soc_block_list[61],
  35638         soc_iprocreg,
  35639         1,
  35640         0,
  35641         0x18027274,
  35642         0,
  35643         0,
  35644         2,
  35645         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  35646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35647         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35648         -1,
  35649         -1,
  35650     },
  35651 #endif /* chips */
  35652 
  35653 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  35654     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  35655     defined(BCM_56670_B0)
  35656     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM56560_A0r */
  35657         soc_block_list[61],
  35658         soc_iprocreg,
  35659         1,
  35660         0,
  35661         0x18021274,
  35662         0,
  35663         0,
  35664         2,
  35665         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35667         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35668         -1,
  35669         -1,
  35670     },
  35671 #endif /* chips */
  35672 
  35673 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  35674     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  35675     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  35676     defined(BCM_56980_B0)
  35677     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM56960_A0r */
  35678         soc_block_list[61],
  35679         soc_iprocreg,
  35680         1,
  35681         0,
  35682         0x18021274,
  35683         0,
  35684         0,
  35685         2,
  35686         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35689         -1,
  35690         -1,
  35691         3,
  35692     },
  35693 #endif /* chips */
  35694 
  35695 #if defined(BCM_88270_A0)
  35696     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM88270_A0r */
  35697         soc_block_list[61],
  35698         soc_iprocreg,
  35699         1,
  35700         0,
  35701         0x18021274,
  35702         0,
  35703         0,
  35704         2,
  35705         soc_QSPI_MSPI_TXRAM13_BCM88270_A0r_fields,
  35706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35708         -1,
  35709         -1,
  35710     },
  35711 #endif /* chips */
  35712 
  35713 #if defined(BCM_88375_A0)
  35714     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM88375_A0r */
  35715         soc_block_list[61],
  35716         soc_iprocreg,
  35717         1,
  35718         0,
  35719         0x18021274,
  35720         0,
  35721         0,
  35722         2,
  35723         soc_QSPI_MSPI_TXRAM13_BCM88375_A0r_fields,
  35724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35726         -1,
  35727         -1,
  35728     },
  35729 #endif /* chips */
  35730 
  35731 #if defined(BCM_88375_B0)
  35732     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM88375_B0r */
  35733         soc_block_list[61],
  35734         soc_iprocreg,
  35735         1,
  35736         0,
  35737         0x18021274,
  35738         0,
  35739         0,
  35740         2,
  35741         soc_QSPI_MSPI_TXRAM13_BCM88375_B0r_fields,
  35742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35744         -1,
  35745         -1,
  35746     },
  35747 #endif /* chips */
  35748 
  35749 #if defined(BCM_88470_A0)
  35750     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM88470_A0r */
  35751         soc_block_list[61],
  35752         soc_iprocreg,
  35753         1,
  35754         0,
  35755         0x18021274,
  35756         0,
  35757         0,
  35758         2,
  35759         soc_QSPI_MSPI_TXRAM13_BCM88470_A0r_fields,
  35760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35762         -1,
  35763         -1,
  35764     },
  35765 #endif /* chips */
  35766 
  35767 #if defined(BCM_88470_B0)
  35768     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM88470_B0r */
  35769         soc_block_list[61],
  35770         soc_iprocreg,
  35771         1,
  35772         0,
  35773         0x18021274,
  35774         0,
  35775         0,
  35776         2,
  35777         soc_QSPI_MSPI_TXRAM13_BCM88470_B0r_fields,
  35778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35779         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35780         -1,
  35781         -1,
  35782     },
  35783 #endif /* chips */
  35784 
  35785 #if defined(BCM_88675_B0)
  35786     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM88675_B0r */
  35787         soc_block_list[61],
  35788         soc_iprocreg,
  35789         1,
  35790         0,
  35791         0x18021274,
  35792         0,
  35793         0,
  35794         2,
  35795         soc_QSPI_MSPI_TXRAM13_BCM88675_B0r_fields,
  35796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35797         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35798         -1,
  35799         -1,
  35800     },
  35801 #endif /* chips */
  35802 
  35803 #if defined(BCM_88680_A0)
  35804     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM88680_A0r */
  35805         soc_block_list[61],
  35806         soc_iprocreg,
  35807         1,
  35808         0,
  35809         0x18021274,
  35810         0,
  35811         0,
  35812         2,
  35813         soc_QSPI_MSPI_TXRAM13_BCM88680_A0r_fields,
  35814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35815         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35816         -1,
  35817         -1,
  35818     },
  35819 #endif /* chips */
  35820 
  35821 #if defined(BCM_88690_A0)
  35822     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM88690_A0r */
  35823         soc_block_list[61],
  35824         soc_iprocreg,
  35825         1,
  35826         0,
  35827         0x18021274,
  35828         0,
  35829         0,
  35830         2,
  35831         soc_QSPI_MSPI_TXRAM13_BCM88690_A0r_fields,
  35832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35833         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35834         -1,
  35835         -1,
  35836     },
  35837 #endif /* chips */
  35838 
  35839 #if defined(BCM_88690_B0)
  35840     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM88690_B0r */
  35841         soc_block_list[61],
  35842         soc_iprocreg,
  35843         1,
  35844         0,
  35845         0x18021274,
  35846         0,
  35847         0,
  35848         2,
  35849         soc_QSPI_MSPI_TXRAM13_BCM88690_B0r_fields,
  35850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35851         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35852         -1,
  35853         -1,
  35854     },
  35855 #endif /* chips */
  35856 
  35857 #if defined(BCM_88790_A0)
  35858     { /* SOC_REG_INT_QSPI_MSPI_TXRAM13_BCM88790_A0r */
  35859         soc_block_list[61],
  35860         soc_iprocreg,
  35861         1,
  35862         0,
  35863         0x18021274,
  35864         0,
  35865         0,
  35866         2,
  35867         soc_QSPI_MSPI_TXRAM13_BCM88790_A0r_fields,
  35868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35869         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35870         -1,
  35871         -1,
  35872     },
  35873 #endif /* chips */
  35874 
  35875 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  35876     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  35877     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  35878     defined(BCM_56260_B0)
  35879     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM53400_A0r */
  35880         soc_block_list[61],
  35881         soc_iprocreg,
  35882         1,
  35883         0,
  35884         0x18047278,
  35885         0,
  35886         0,
  35887         2,
  35888         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35890         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35891         -1,
  35892         -1,
  35893     },
  35894 #endif /* chips */
  35895 
  35896 #if defined(BCM_56370_A0)
  35897     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM56370_A0r */
  35898         soc_block_list[61],
  35899         soc_iprocreg,
  35900         1,
  35901         0,
  35902         0x15000278,
  35903         0,
  35904         0,
  35905         2,
  35906         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35908         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35909         -1,
  35910         -1,
  35911         3,
  35912     },
  35913 #endif /* chips */
  35914 
  35915 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  35916     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  35917     defined(BCM_56450_B1)
  35918     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM56450_A0r */
  35919         soc_block_list[61],
  35920         soc_iprocreg,
  35921         1,
  35922         0,
  35923         0x18027278,
  35924         0,
  35925         0,
  35926         2,
  35927         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  35928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35929         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35930         -1,
  35931         -1,
  35932     },
  35933 #endif /* chips */
  35934 
  35935 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  35936     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  35937     defined(BCM_56670_B0)
  35938     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM56560_A0r */
  35939         soc_block_list[61],
  35940         soc_iprocreg,
  35941         1,
  35942         0,
  35943         0x18021278,
  35944         0,
  35945         0,
  35946         2,
  35947         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35949         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35950         -1,
  35951         -1,
  35952     },
  35953 #endif /* chips */
  35954 
  35955 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  35956     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  35957     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  35958     defined(BCM_56980_B0)
  35959     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM56960_A0r */
  35960         soc_block_list[61],
  35961         soc_iprocreg,
  35962         1,
  35963         0,
  35964         0x18021278,
  35965         0,
  35966         0,
  35967         2,
  35968         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  35969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35970         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35971         -1,
  35972         -1,
  35973         3,
  35974     },
  35975 #endif /* chips */
  35976 
  35977 #if defined(BCM_88270_A0)
  35978     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM88270_A0r */
  35979         soc_block_list[61],
  35980         soc_iprocreg,
  35981         1,
  35982         0,
  35983         0x18021278,
  35984         0,
  35985         0,
  35986         2,
  35987         soc_QSPI_MSPI_TXRAM14_BCM88270_A0r_fields,
  35988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35989         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  35990         -1,
  35991         -1,
  35992     },
  35993 #endif /* chips */
  35994 
  35995 #if defined(BCM_88375_A0)
  35996     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM88375_A0r */
  35997         soc_block_list[61],
  35998         soc_iprocreg,
  35999         1,
  36000         0,
  36001         0x18021278,
  36002         0,
  36003         0,
  36004         2,
  36005         soc_QSPI_MSPI_TXRAM14_BCM88375_A0r_fields,
  36006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36007         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36008         -1,
  36009         -1,
  36010     },
  36011 #endif /* chips */
  36012 
  36013 #if defined(BCM_88375_B0)
  36014     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM88375_B0r */
  36015         soc_block_list[61],
  36016         soc_iprocreg,
  36017         1,
  36018         0,
  36019         0x18021278,
  36020         0,
  36021         0,
  36022         2,
  36023         soc_QSPI_MSPI_TXRAM14_BCM88375_B0r_fields,
  36024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36025         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36026         -1,
  36027         -1,
  36028     },
  36029 #endif /* chips */
  36030 
  36031 #if defined(BCM_88470_A0)
  36032     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM88470_A0r */
  36033         soc_block_list[61],
  36034         soc_iprocreg,
  36035         1,
  36036         0,
  36037         0x18021278,
  36038         0,
  36039         0,
  36040         2,
  36041         soc_QSPI_MSPI_TXRAM14_BCM88470_A0r_fields,
  36042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36043         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36044         -1,
  36045         -1,
  36046     },
  36047 #endif /* chips */
  36048 
  36049 #if defined(BCM_88470_B0)
  36050     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM88470_B0r */
  36051         soc_block_list[61],
  36052         soc_iprocreg,
  36053         1,
  36054         0,
  36055         0x18021278,
  36056         0,
  36057         0,
  36058         2,
  36059         soc_QSPI_MSPI_TXRAM14_BCM88470_B0r_fields,
  36060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36061         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36062         -1,
  36063         -1,
  36064     },
  36065 #endif /* chips */
  36066 
  36067 #if defined(BCM_88675_B0)
  36068     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM88675_B0r */
  36069         soc_block_list[61],
  36070         soc_iprocreg,
  36071         1,
  36072         0,
  36073         0x18021278,
  36074         0,
  36075         0,
  36076         2,
  36077         soc_QSPI_MSPI_TXRAM14_BCM88675_B0r_fields,
  36078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36079         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36080         -1,
  36081         -1,
  36082     },
  36083 #endif /* chips */
  36084 
  36085 #if defined(BCM_88680_A0)
  36086     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM88680_A0r */
  36087         soc_block_list[61],
  36088         soc_iprocreg,
  36089         1,
  36090         0,
  36091         0x18021278,
  36092         0,
  36093         0,
  36094         2,
  36095         soc_QSPI_MSPI_TXRAM14_BCM88680_A0r_fields,
  36096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36098         -1,
  36099         -1,
  36100     },
  36101 #endif /* chips */
  36102 
  36103 #if defined(BCM_88690_A0)
  36104     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM88690_A0r */
  36105         soc_block_list[61],
  36106         soc_iprocreg,
  36107         1,
  36108         0,
  36109         0x18021278,
  36110         0,
  36111         0,
  36112         2,
  36113         soc_QSPI_MSPI_TXRAM14_BCM88690_A0r_fields,
  36114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36116         -1,
  36117         -1,
  36118     },
  36119 #endif /* chips */
  36120 
  36121 #if defined(BCM_88690_B0)
  36122     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM88690_B0r */
  36123         soc_block_list[61],
  36124         soc_iprocreg,
  36125         1,
  36126         0,
  36127         0x18021278,
  36128         0,
  36129         0,
  36130         2,
  36131         soc_QSPI_MSPI_TXRAM14_BCM88690_B0r_fields,
  36132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36133         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36134         -1,
  36135         -1,
  36136     },
  36137 #endif /* chips */
  36138 
  36139 #if defined(BCM_88790_A0)
  36140     { /* SOC_REG_INT_QSPI_MSPI_TXRAM14_BCM88790_A0r */
  36141         soc_block_list[61],
  36142         soc_iprocreg,
  36143         1,
  36144         0,
  36145         0x18021278,
  36146         0,
  36147         0,
  36148         2,
  36149         soc_QSPI_MSPI_TXRAM14_BCM88790_A0r_fields,
  36150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36151         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36152         -1,
  36153         -1,
  36154     },
  36155 #endif /* chips */
  36156 
  36157 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36158     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36159     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36160     defined(BCM_56260_B0)
  36161     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM53400_A0r */
  36162         soc_block_list[61],
  36163         soc_iprocreg,
  36164         1,
  36165         0,
  36166         0x1804727c,
  36167         0,
  36168         0,
  36169         2,
  36170         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36172         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36173         -1,
  36174         -1,
  36175     },
  36176 #endif /* chips */
  36177 
  36178 #if defined(BCM_56370_A0)
  36179     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM56370_A0r */
  36180         soc_block_list[61],
  36181         soc_iprocreg,
  36182         1,
  36183         0,
  36184         0x1500027c,
  36185         0,
  36186         0,
  36187         2,
  36188         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36190         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36191         -1,
  36192         -1,
  36193         3,
  36194     },
  36195 #endif /* chips */
  36196 
  36197 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  36198     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  36199     defined(BCM_56450_B1)
  36200     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM56450_A0r */
  36201         soc_block_list[61],
  36202         soc_iprocreg,
  36203         1,
  36204         0,
  36205         0x1802727c,
  36206         0,
  36207         0,
  36208         2,
  36209         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  36210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36211         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36212         -1,
  36213         -1,
  36214     },
  36215 #endif /* chips */
  36216 
  36217 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  36218     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  36219     defined(BCM_56670_B0)
  36220     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM56560_A0r */
  36221         soc_block_list[61],
  36222         soc_iprocreg,
  36223         1,
  36224         0,
  36225         0x1802127c,
  36226         0,
  36227         0,
  36228         2,
  36229         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36231         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36232         -1,
  36233         -1,
  36234     },
  36235 #endif /* chips */
  36236 
  36237 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  36238     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  36239     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  36240     defined(BCM_56980_B0)
  36241     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM56960_A0r */
  36242         soc_block_list[61],
  36243         soc_iprocreg,
  36244         1,
  36245         0,
  36246         0x1802127c,
  36247         0,
  36248         0,
  36249         2,
  36250         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36252         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36253         -1,
  36254         -1,
  36255         3,
  36256     },
  36257 #endif /* chips */
  36258 
  36259 #if defined(BCM_88270_A0)
  36260     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM88270_A0r */
  36261         soc_block_list[61],
  36262         soc_iprocreg,
  36263         1,
  36264         0,
  36265         0x1802127c,
  36266         0,
  36267         0,
  36268         2,
  36269         soc_QSPI_MSPI_TXRAM15_BCM88270_A0r_fields,
  36270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36271         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36272         -1,
  36273         -1,
  36274     },
  36275 #endif /* chips */
  36276 
  36277 #if defined(BCM_88375_A0)
  36278     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM88375_A0r */
  36279         soc_block_list[61],
  36280         soc_iprocreg,
  36281         1,
  36282         0,
  36283         0x1802127c,
  36284         0,
  36285         0,
  36286         2,
  36287         soc_QSPI_MSPI_TXRAM15_BCM88375_A0r_fields,
  36288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36289         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36290         -1,
  36291         -1,
  36292     },
  36293 #endif /* chips */
  36294 
  36295 #if defined(BCM_88375_B0)
  36296     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM88375_B0r */
  36297         soc_block_list[61],
  36298         soc_iprocreg,
  36299         1,
  36300         0,
  36301         0x1802127c,
  36302         0,
  36303         0,
  36304         2,
  36305         soc_QSPI_MSPI_TXRAM15_BCM88375_B0r_fields,
  36306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36307         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36308         -1,
  36309         -1,
  36310     },
  36311 #endif /* chips */
  36312 
  36313 #if defined(BCM_88470_A0)
  36314     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM88470_A0r */
  36315         soc_block_list[61],
  36316         soc_iprocreg,
  36317         1,
  36318         0,
  36319         0x1802127c,
  36320         0,
  36321         0,
  36322         2,
  36323         soc_QSPI_MSPI_TXRAM15_BCM88470_A0r_fields,
  36324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36325         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36326         -1,
  36327         -1,
  36328     },
  36329 #endif /* chips */
  36330 
  36331 #if defined(BCM_88470_B0)
  36332     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM88470_B0r */
  36333         soc_block_list[61],
  36334         soc_iprocreg,
  36335         1,
  36336         0,
  36337         0x1802127c,
  36338         0,
  36339         0,
  36340         2,
  36341         soc_QSPI_MSPI_TXRAM15_BCM88470_B0r_fields,
  36342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36343         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36344         -1,
  36345         -1,
  36346     },
  36347 #endif /* chips */
  36348 
  36349 #if defined(BCM_88675_B0)
  36350     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM88675_B0r */
  36351         soc_block_list[61],
  36352         soc_iprocreg,
  36353         1,
  36354         0,
  36355         0x1802127c,
  36356         0,
  36357         0,
  36358         2,
  36359         soc_QSPI_MSPI_TXRAM15_BCM88675_B0r_fields,
  36360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36361         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36362         -1,
  36363         -1,
  36364     },
  36365 #endif /* chips */
  36366 
  36367 #if defined(BCM_88680_A0)
  36368     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM88680_A0r */
  36369         soc_block_list[61],
  36370         soc_iprocreg,
  36371         1,
  36372         0,
  36373         0x1802127c,
  36374         0,
  36375         0,
  36376         2,
  36377         soc_QSPI_MSPI_TXRAM15_BCM88680_A0r_fields,
  36378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36379         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36380         -1,
  36381         -1,
  36382     },
  36383 #endif /* chips */
  36384 
  36385 #if defined(BCM_88690_A0)
  36386     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM88690_A0r */
  36387         soc_block_list[61],
  36388         soc_iprocreg,
  36389         1,
  36390         0,
  36391         0x1802127c,
  36392         0,
  36393         0,
  36394         2,
  36395         soc_QSPI_MSPI_TXRAM15_BCM88690_A0r_fields,
  36396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36397         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36398         -1,
  36399         -1,
  36400     },
  36401 #endif /* chips */
  36402 
  36403 #if defined(BCM_88690_B0)
  36404     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM88690_B0r */
  36405         soc_block_list[61],
  36406         soc_iprocreg,
  36407         1,
  36408         0,
  36409         0x1802127c,
  36410         0,
  36411         0,
  36412         2,
  36413         soc_QSPI_MSPI_TXRAM15_BCM88690_B0r_fields,
  36414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36416         -1,
  36417         -1,
  36418     },
  36419 #endif /* chips */
  36420 
  36421 #if defined(BCM_88790_A0)
  36422     { /* SOC_REG_INT_QSPI_MSPI_TXRAM15_BCM88790_A0r */
  36423         soc_block_list[61],
  36424         soc_iprocreg,
  36425         1,
  36426         0,
  36427         0x1802127c,
  36428         0,
  36429         0,
  36430         2,
  36431         soc_QSPI_MSPI_TXRAM15_BCM88790_A0r_fields,
  36432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36433         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36434         -1,
  36435         -1,
  36436     },
  36437 #endif /* chips */
  36438 
  36439 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36440     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36441     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36442     defined(BCM_56260_B0)
  36443     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM53400_A0r */
  36444         soc_block_list[61],
  36445         soc_iprocreg,
  36446         1,
  36447         0,
  36448         0x18047280,
  36449         0,
  36450         0,
  36451         2,
  36452         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36454         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36455         -1,
  36456         -1,
  36457     },
  36458 #endif /* chips */
  36459 
  36460 #if defined(BCM_56370_A0)
  36461     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM56370_A0r */
  36462         soc_block_list[61],
  36463         soc_iprocreg,
  36464         1,
  36465         0,
  36466         0x15000280,
  36467         0,
  36468         0,
  36469         2,
  36470         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36472         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36473         -1,
  36474         -1,
  36475         3,
  36476     },
  36477 #endif /* chips */
  36478 
  36479 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  36480     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  36481     defined(BCM_56450_B1)
  36482     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM56450_A0r */
  36483         soc_block_list[61],
  36484         soc_iprocreg,
  36485         1,
  36486         0,
  36487         0x18027280,
  36488         0,
  36489         0,
  36490         2,
  36491         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  36492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36493         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36494         -1,
  36495         -1,
  36496     },
  36497 #endif /* chips */
  36498 
  36499 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  36500     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  36501     defined(BCM_56670_B0)
  36502     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM56560_A0r */
  36503         soc_block_list[61],
  36504         soc_iprocreg,
  36505         1,
  36506         0,
  36507         0x18021280,
  36508         0,
  36509         0,
  36510         2,
  36511         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36513         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36514         -1,
  36515         -1,
  36516     },
  36517 #endif /* chips */
  36518 
  36519 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  36520     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  36521     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  36522     defined(BCM_56980_B0)
  36523     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM56960_A0r */
  36524         soc_block_list[61],
  36525         soc_iprocreg,
  36526         1,
  36527         0,
  36528         0x18021280,
  36529         0,
  36530         0,
  36531         2,
  36532         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36534         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36535         -1,
  36536         -1,
  36537         3,
  36538     },
  36539 #endif /* chips */
  36540 
  36541 #if defined(BCM_88270_A0)
  36542     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM88270_A0r */
  36543         soc_block_list[61],
  36544         soc_iprocreg,
  36545         1,
  36546         0,
  36547         0x18021280,
  36548         0,
  36549         0,
  36550         2,
  36551         soc_QSPI_MSPI_TXRAM16_BCM88270_A0r_fields,
  36552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36553         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36554         -1,
  36555         -1,
  36556     },
  36557 #endif /* chips */
  36558 
  36559 #if defined(BCM_88375_A0)
  36560     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM88375_A0r */
  36561         soc_block_list[61],
  36562         soc_iprocreg,
  36563         1,
  36564         0,
  36565         0x18021280,
  36566         0,
  36567         0,
  36568         2,
  36569         soc_QSPI_MSPI_TXRAM16_BCM88375_A0r_fields,
  36570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36571         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36572         -1,
  36573         -1,
  36574     },
  36575 #endif /* chips */
  36576 
  36577 #if defined(BCM_88375_B0)
  36578     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM88375_B0r */
  36579         soc_block_list[61],
  36580         soc_iprocreg,
  36581         1,
  36582         0,
  36583         0x18021280,
  36584         0,
  36585         0,
  36586         2,
  36587         soc_QSPI_MSPI_TXRAM16_BCM88375_B0r_fields,
  36588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36589         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36590         -1,
  36591         -1,
  36592     },
  36593 #endif /* chips */
  36594 
  36595 #if defined(BCM_88470_A0)
  36596     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM88470_A0r */
  36597         soc_block_list[61],
  36598         soc_iprocreg,
  36599         1,
  36600         0,
  36601         0x18021280,
  36602         0,
  36603         0,
  36604         2,
  36605         soc_QSPI_MSPI_TXRAM16_BCM88470_A0r_fields,
  36606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36607         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36608         -1,
  36609         -1,
  36610     },
  36611 #endif /* chips */
  36612 
  36613 #if defined(BCM_88470_B0)
  36614     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM88470_B0r */
  36615         soc_block_list[61],
  36616         soc_iprocreg,
  36617         1,
  36618         0,
  36619         0x18021280,
  36620         0,
  36621         0,
  36622         2,
  36623         soc_QSPI_MSPI_TXRAM16_BCM88470_B0r_fields,
  36624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36625         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36626         -1,
  36627         -1,
  36628     },
  36629 #endif /* chips */
  36630 
  36631 #if defined(BCM_88675_B0)
  36632     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM88675_B0r */
  36633         soc_block_list[61],
  36634         soc_iprocreg,
  36635         1,
  36636         0,
  36637         0x18021280,
  36638         0,
  36639         0,
  36640         2,
  36641         soc_QSPI_MSPI_TXRAM16_BCM88675_B0r_fields,
  36642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36643         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36644         -1,
  36645         -1,
  36646     },
  36647 #endif /* chips */
  36648 
  36649 #if defined(BCM_88680_A0)
  36650     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM88680_A0r */
  36651         soc_block_list[61],
  36652         soc_iprocreg,
  36653         1,
  36654         0,
  36655         0x18021280,
  36656         0,
  36657         0,
  36658         2,
  36659         soc_QSPI_MSPI_TXRAM16_BCM88680_A0r_fields,
  36660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36661         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36662         -1,
  36663         -1,
  36664     },
  36665 #endif /* chips */
  36666 
  36667 #if defined(BCM_88690_A0)
  36668     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM88690_A0r */
  36669         soc_block_list[61],
  36670         soc_iprocreg,
  36671         1,
  36672         0,
  36673         0x18021280,
  36674         0,
  36675         0,
  36676         2,
  36677         soc_QSPI_MSPI_TXRAM16_BCM88690_A0r_fields,
  36678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36680         -1,
  36681         -1,
  36682     },
  36683 #endif /* chips */
  36684 
  36685 #if defined(BCM_88690_B0)
  36686     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM88690_B0r */
  36687         soc_block_list[61],
  36688         soc_iprocreg,
  36689         1,
  36690         0,
  36691         0x18021280,
  36692         0,
  36693         0,
  36694         2,
  36695         soc_QSPI_MSPI_TXRAM16_BCM88690_B0r_fields,
  36696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36698         -1,
  36699         -1,
  36700     },
  36701 #endif /* chips */
  36702 
  36703 #if defined(BCM_88790_A0)
  36704     { /* SOC_REG_INT_QSPI_MSPI_TXRAM16_BCM88790_A0r */
  36705         soc_block_list[61],
  36706         soc_iprocreg,
  36707         1,
  36708         0,
  36709         0x18021280,
  36710         0,
  36711         0,
  36712         2,
  36713         soc_QSPI_MSPI_TXRAM16_BCM88790_A0r_fields,
  36714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36715         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36716         -1,
  36717         -1,
  36718     },
  36719 #endif /* chips */
  36720 
  36721 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  36722     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  36723     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  36724     defined(BCM_56260_B0)
  36725     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM53400_A0r */
  36726         soc_block_list[61],
  36727         soc_iprocreg,
  36728         1,
  36729         0,
  36730         0x18047284,
  36731         0,
  36732         0,
  36733         2,
  36734         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36736         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36737         -1,
  36738         -1,
  36739     },
  36740 #endif /* chips */
  36741 
  36742 #if defined(BCM_56370_A0)
  36743     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM56370_A0r */
  36744         soc_block_list[61],
  36745         soc_iprocreg,
  36746         1,
  36747         0,
  36748         0x15000284,
  36749         0,
  36750         0,
  36751         2,
  36752         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36754         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36755         -1,
  36756         -1,
  36757         3,
  36758     },
  36759 #endif /* chips */
  36760 
  36761 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  36762     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  36763     defined(BCM_56450_B1)
  36764     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM56450_A0r */
  36765         soc_block_list[61],
  36766         soc_iprocreg,
  36767         1,
  36768         0,
  36769         0x18027284,
  36770         0,
  36771         0,
  36772         2,
  36773         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  36774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36775         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36776         -1,
  36777         -1,
  36778     },
  36779 #endif /* chips */
  36780 
  36781 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  36782     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  36783     defined(BCM_56670_B0)
  36784     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM56560_A0r */
  36785         soc_block_list[61],
  36786         soc_iprocreg,
  36787         1,
  36788         0,
  36789         0x18021284,
  36790         0,
  36791         0,
  36792         2,
  36793         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36794         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36795         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36796         -1,
  36797         -1,
  36798     },
  36799 #endif /* chips */
  36800 
  36801 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  36802     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  36803     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  36804     defined(BCM_56980_B0)
  36805     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM56960_A0r */
  36806         soc_block_list[61],
  36807         soc_iprocreg,
  36808         1,
  36809         0,
  36810         0x18021284,
  36811         0,
  36812         0,
  36813         2,
  36814         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  36815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36816         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36817         -1,
  36818         -1,
  36819         3,
  36820     },
  36821 #endif /* chips */
  36822 
  36823 #if defined(BCM_88270_A0)
  36824     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM88270_A0r */
  36825         soc_block_list[61],
  36826         soc_iprocreg,
  36827         1,
  36828         0,
  36829         0x18021284,
  36830         0,
  36831         0,
  36832         2,
  36833         soc_QSPI_MSPI_TXRAM17_BCM88270_A0r_fields,
  36834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36835         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36836         -1,
  36837         -1,
  36838     },
  36839 #endif /* chips */
  36840 
  36841 #if defined(BCM_88375_A0)
  36842     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM88375_A0r */
  36843         soc_block_list[61],
  36844         soc_iprocreg,
  36845         1,
  36846         0,
  36847         0x18021284,
  36848         0,
  36849         0,
  36850         2,
  36851         soc_QSPI_MSPI_TXRAM17_BCM88375_A0r_fields,
  36852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36853         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36854         -1,
  36855         -1,
  36856     },
  36857 #endif /* chips */
  36858 
  36859 #if defined(BCM_88375_B0)
  36860     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM88375_B0r */
  36861         soc_block_list[61],
  36862         soc_iprocreg,
  36863         1,
  36864         0,
  36865         0x18021284,
  36866         0,
  36867         0,
  36868         2,
  36869         soc_QSPI_MSPI_TXRAM17_BCM88375_B0r_fields,
  36870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36871         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36872         -1,
  36873         -1,
  36874     },
  36875 #endif /* chips */
  36876 
  36877 #if defined(BCM_88470_A0)
  36878     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM88470_A0r */
  36879         soc_block_list[61],
  36880         soc_iprocreg,
  36881         1,
  36882         0,
  36883         0x18021284,
  36884         0,
  36885         0,
  36886         2,
  36887         soc_QSPI_MSPI_TXRAM17_BCM88470_A0r_fields,
  36888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36889         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36890         -1,
  36891         -1,
  36892     },
  36893 #endif /* chips */
  36894 
  36895 #if defined(BCM_88470_B0)
  36896     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM88470_B0r */
  36897         soc_block_list[61],
  36898         soc_iprocreg,
  36899         1,
  36900         0,
  36901         0x18021284,
  36902         0,
  36903         0,
  36904         2,
  36905         soc_QSPI_MSPI_TXRAM17_BCM88470_B0r_fields,
  36906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36907         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36908         -1,
  36909         -1,
  36910     },
  36911 #endif /* chips */
  36912 
  36913 #if defined(BCM_88675_B0)
  36914     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM88675_B0r */
  36915         soc_block_list[61],
  36916         soc_iprocreg,
  36917         1,
  36918         0,
  36919         0x18021284,
  36920         0,
  36921         0,
  36922         2,
  36923         soc_QSPI_MSPI_TXRAM17_BCM88675_B0r_fields,
  36924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36925         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36926         -1,
  36927         -1,
  36928     },
  36929 #endif /* chips */
  36930 
  36931 #if defined(BCM_88680_A0)
  36932     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM88680_A0r */
  36933         soc_block_list[61],
  36934         soc_iprocreg,
  36935         1,
  36936         0,
  36937         0x18021284,
  36938         0,
  36939         0,
  36940         2,
  36941         soc_QSPI_MSPI_TXRAM17_BCM88680_A0r_fields,
  36942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36943         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36944         -1,
  36945         -1,
  36946     },
  36947 #endif /* chips */
  36948 
  36949 #if defined(BCM_88690_A0)
  36950     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM88690_A0r */
  36951         soc_block_list[61],
  36952         soc_iprocreg,
  36953         1,
  36954         0,
  36955         0x18021284,
  36956         0,
  36957         0,
  36958         2,
  36959         soc_QSPI_MSPI_TXRAM17_BCM88690_A0r_fields,
  36960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36961         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36962         -1,
  36963         -1,
  36964     },
  36965 #endif /* chips */
  36966 
  36967 #if defined(BCM_88690_B0)
  36968     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM88690_B0r */
  36969         soc_block_list[61],
  36970         soc_iprocreg,
  36971         1,
  36972         0,
  36973         0x18021284,
  36974         0,
  36975         0,
  36976         2,
  36977         soc_QSPI_MSPI_TXRAM17_BCM88690_B0r_fields,
  36978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36979         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36980         -1,
  36981         -1,
  36982     },
  36983 #endif /* chips */
  36984 
  36985 #if defined(BCM_88790_A0)
  36986     { /* SOC_REG_INT_QSPI_MSPI_TXRAM17_BCM88790_A0r */
  36987         soc_block_list[61],
  36988         soc_iprocreg,
  36989         1,
  36990         0,
  36991         0x18021284,
  36992         0,
  36993         0,
  36994         2,
  36995         soc_QSPI_MSPI_TXRAM17_BCM88790_A0r_fields,
  36996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36997         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36998         -1,
  36999         -1,
  37000     },
  37001 #endif /* chips */
  37002 
  37003 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37004     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37005     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37006     defined(BCM_56260_B0)
  37007     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM53400_A0r */
  37008         soc_block_list[61],
  37009         soc_iprocreg,
  37010         1,
  37011         0,
  37012         0x18047288,
  37013         0,
  37014         0,
  37015         2,
  37016         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37018         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37019         -1,
  37020         -1,
  37021     },
  37022 #endif /* chips */
  37023 
  37024 #if defined(BCM_56370_A0)
  37025     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM56370_A0r */
  37026         soc_block_list[61],
  37027         soc_iprocreg,
  37028         1,
  37029         0,
  37030         0x15000288,
  37031         0,
  37032         0,
  37033         2,
  37034         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37036         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37037         -1,
  37038         -1,
  37039         3,
  37040     },
  37041 #endif /* chips */
  37042 
  37043 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  37044     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37045     defined(BCM_56450_B1)
  37046     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM56450_A0r */
  37047         soc_block_list[61],
  37048         soc_iprocreg,
  37049         1,
  37050         0,
  37051         0x18027288,
  37052         0,
  37053         0,
  37054         2,
  37055         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  37056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37057         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37058         -1,
  37059         -1,
  37060     },
  37061 #endif /* chips */
  37062 
  37063 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  37064     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  37065     defined(BCM_56670_B0)
  37066     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM56560_A0r */
  37067         soc_block_list[61],
  37068         soc_iprocreg,
  37069         1,
  37070         0,
  37071         0x18021288,
  37072         0,
  37073         0,
  37074         2,
  37075         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37078         -1,
  37079         -1,
  37080     },
  37081 #endif /* chips */
  37082 
  37083 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  37084     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  37085     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  37086     defined(BCM_56980_B0)
  37087     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM56960_A0r */
  37088         soc_block_list[61],
  37089         soc_iprocreg,
  37090         1,
  37091         0,
  37092         0x18021288,
  37093         0,
  37094         0,
  37095         2,
  37096         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37098         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37099         -1,
  37100         -1,
  37101         3,
  37102     },
  37103 #endif /* chips */
  37104 
  37105 #if defined(BCM_88270_A0)
  37106     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM88270_A0r */
  37107         soc_block_list[61],
  37108         soc_iprocreg,
  37109         1,
  37110         0,
  37111         0x18021288,
  37112         0,
  37113         0,
  37114         2,
  37115         soc_QSPI_MSPI_TXRAM18_BCM88270_A0r_fields,
  37116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37117         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37118         -1,
  37119         -1,
  37120     },
  37121 #endif /* chips */
  37122 
  37123 #if defined(BCM_88375_A0)
  37124     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM88375_A0r */
  37125         soc_block_list[61],
  37126         soc_iprocreg,
  37127         1,
  37128         0,
  37129         0x18021288,
  37130         0,
  37131         0,
  37132         2,
  37133         soc_QSPI_MSPI_TXRAM18_BCM88375_A0r_fields,
  37134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37135         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37136         -1,
  37137         -1,
  37138     },
  37139 #endif /* chips */
  37140 
  37141 #if defined(BCM_88375_B0)
  37142     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM88375_B0r */
  37143         soc_block_list[61],
  37144         soc_iprocreg,
  37145         1,
  37146         0,
  37147         0x18021288,
  37148         0,
  37149         0,
  37150         2,
  37151         soc_QSPI_MSPI_TXRAM18_BCM88375_B0r_fields,
  37152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37153         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37154         -1,
  37155         -1,
  37156     },
  37157 #endif /* chips */
  37158 
  37159 #if defined(BCM_88470_A0)
  37160     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM88470_A0r */
  37161         soc_block_list[61],
  37162         soc_iprocreg,
  37163         1,
  37164         0,
  37165         0x18021288,
  37166         0,
  37167         0,
  37168         2,
  37169         soc_QSPI_MSPI_TXRAM18_BCM88470_A0r_fields,
  37170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37171         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37172         -1,
  37173         -1,
  37174     },
  37175 #endif /* chips */
  37176 
  37177 #if defined(BCM_88470_B0)
  37178     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM88470_B0r */
  37179         soc_block_list[61],
  37180         soc_iprocreg,
  37181         1,
  37182         0,
  37183         0x18021288,
  37184         0,
  37185         0,
  37186         2,
  37187         soc_QSPI_MSPI_TXRAM18_BCM88470_B0r_fields,
  37188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37189         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37190         -1,
  37191         -1,
  37192     },
  37193 #endif /* chips */
  37194 
  37195 #if defined(BCM_88675_B0)
  37196     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM88675_B0r */
  37197         soc_block_list[61],
  37198         soc_iprocreg,
  37199         1,
  37200         0,
  37201         0x18021288,
  37202         0,
  37203         0,
  37204         2,
  37205         soc_QSPI_MSPI_TXRAM18_BCM88675_B0r_fields,
  37206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37207         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37208         -1,
  37209         -1,
  37210     },
  37211 #endif /* chips */
  37212 
  37213 #if defined(BCM_88680_A0)
  37214     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM88680_A0r */
  37215         soc_block_list[61],
  37216         soc_iprocreg,
  37217         1,
  37218         0,
  37219         0x18021288,
  37220         0,
  37221         0,
  37222         2,
  37223         soc_QSPI_MSPI_TXRAM18_BCM88680_A0r_fields,
  37224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37225         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37226         -1,
  37227         -1,
  37228     },
  37229 #endif /* chips */
  37230 
  37231 #if defined(BCM_88690_A0)
  37232     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM88690_A0r */
  37233         soc_block_list[61],
  37234         soc_iprocreg,
  37235         1,
  37236         0,
  37237         0x18021288,
  37238         0,
  37239         0,
  37240         2,
  37241         soc_QSPI_MSPI_TXRAM18_BCM88690_A0r_fields,
  37242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37243         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37244         -1,
  37245         -1,
  37246     },
  37247 #endif /* chips */
  37248 
  37249 #if defined(BCM_88690_B0)
  37250     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM88690_B0r */
  37251         soc_block_list[61],
  37252         soc_iprocreg,
  37253         1,
  37254         0,
  37255         0x18021288,
  37256         0,
  37257         0,
  37258         2,
  37259         soc_QSPI_MSPI_TXRAM18_BCM88690_B0r_fields,
  37260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37261         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37262         -1,
  37263         -1,
  37264     },
  37265 #endif /* chips */
  37266 
  37267 #if defined(BCM_88790_A0)
  37268     { /* SOC_REG_INT_QSPI_MSPI_TXRAM18_BCM88790_A0r */
  37269         soc_block_list[61],
  37270         soc_iprocreg,
  37271         1,
  37272         0,
  37273         0x18021288,
  37274         0,
  37275         0,
  37276         2,
  37277         soc_QSPI_MSPI_TXRAM18_BCM88790_A0r_fields,
  37278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37279         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37280         -1,
  37281         -1,
  37282     },
  37283 #endif /* chips */
  37284 
  37285 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37286     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37287     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37288     defined(BCM_56260_B0)
  37289     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM53400_A0r */
  37290         soc_block_list[61],
  37291         soc_iprocreg,
  37292         1,
  37293         0,
  37294         0x1804728c,
  37295         0,
  37296         0,
  37297         2,
  37298         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37300         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37301         -1,
  37302         -1,
  37303     },
  37304 #endif /* chips */
  37305 
  37306 #if defined(BCM_56370_A0)
  37307     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM56370_A0r */
  37308         soc_block_list[61],
  37309         soc_iprocreg,
  37310         1,
  37311         0,
  37312         0x1500028c,
  37313         0,
  37314         0,
  37315         2,
  37316         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37318         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37319         -1,
  37320         -1,
  37321         3,
  37322     },
  37323 #endif /* chips */
  37324 
  37325 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  37326     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37327     defined(BCM_56450_B1)
  37328     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM56450_A0r */
  37329         soc_block_list[61],
  37330         soc_iprocreg,
  37331         1,
  37332         0,
  37333         0x1802728c,
  37334         0,
  37335         0,
  37336         2,
  37337         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  37338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37339         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37340         -1,
  37341         -1,
  37342     },
  37343 #endif /* chips */
  37344 
  37345 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  37346     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  37347     defined(BCM_56670_B0)
  37348     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM56560_A0r */
  37349         soc_block_list[61],
  37350         soc_iprocreg,
  37351         1,
  37352         0,
  37353         0x1802128c,
  37354         0,
  37355         0,
  37356         2,
  37357         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37359         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37360         -1,
  37361         -1,
  37362     },
  37363 #endif /* chips */
  37364 
  37365 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  37366     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  37367     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  37368     defined(BCM_56980_B0)
  37369     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM56960_A0r */
  37370         soc_block_list[61],
  37371         soc_iprocreg,
  37372         1,
  37373         0,
  37374         0x1802128c,
  37375         0,
  37376         0,
  37377         2,
  37378         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37380         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37381         -1,
  37382         -1,
  37383         3,
  37384     },
  37385 #endif /* chips */
  37386 
  37387 #if defined(BCM_88270_A0)
  37388     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM88270_A0r */
  37389         soc_block_list[61],
  37390         soc_iprocreg,
  37391         1,
  37392         0,
  37393         0x1802128c,
  37394         0,
  37395         0,
  37396         2,
  37397         soc_QSPI_MSPI_TXRAM19_BCM88270_A0r_fields,
  37398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37399         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37400         -1,
  37401         -1,
  37402     },
  37403 #endif /* chips */
  37404 
  37405 #if defined(BCM_88375_A0)
  37406     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM88375_A0r */
  37407         soc_block_list[61],
  37408         soc_iprocreg,
  37409         1,
  37410         0,
  37411         0x1802128c,
  37412         0,
  37413         0,
  37414         2,
  37415         soc_QSPI_MSPI_TXRAM19_BCM88375_A0r_fields,
  37416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37417         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37418         -1,
  37419         -1,
  37420     },
  37421 #endif /* chips */
  37422 
  37423 #if defined(BCM_88375_B0)
  37424     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM88375_B0r */
  37425         soc_block_list[61],
  37426         soc_iprocreg,
  37427         1,
  37428         0,
  37429         0x1802128c,
  37430         0,
  37431         0,
  37432         2,
  37433         soc_QSPI_MSPI_TXRAM19_BCM88375_B0r_fields,
  37434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37435         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37436         -1,
  37437         -1,
  37438     },
  37439 #endif /* chips */
  37440 
  37441 #if defined(BCM_88470_A0)
  37442     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM88470_A0r */
  37443         soc_block_list[61],
  37444         soc_iprocreg,
  37445         1,
  37446         0,
  37447         0x1802128c,
  37448         0,
  37449         0,
  37450         2,
  37451         soc_QSPI_MSPI_TXRAM19_BCM88470_A0r_fields,
  37452         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37453         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37454         -1,
  37455         -1,
  37456     },
  37457 #endif /* chips */
  37458 
  37459 #if defined(BCM_88470_B0)
  37460     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM88470_B0r */
  37461         soc_block_list[61],
  37462         soc_iprocreg,
  37463         1,
  37464         0,
  37465         0x1802128c,
  37466         0,
  37467         0,
  37468         2,
  37469         soc_QSPI_MSPI_TXRAM19_BCM88470_B0r_fields,
  37470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37471         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37472         -1,
  37473         -1,
  37474     },
  37475 #endif /* chips */
  37476 
  37477 #if defined(BCM_88675_B0)
  37478     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM88675_B0r */
  37479         soc_block_list[61],
  37480         soc_iprocreg,
  37481         1,
  37482         0,
  37483         0x1802128c,
  37484         0,
  37485         0,
  37486         2,
  37487         soc_QSPI_MSPI_TXRAM19_BCM88675_B0r_fields,
  37488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37490         -1,
  37491         -1,
  37492     },
  37493 #endif /* chips */
  37494 
  37495 #if defined(BCM_88680_A0)
  37496     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM88680_A0r */
  37497         soc_block_list[61],
  37498         soc_iprocreg,
  37499         1,
  37500         0,
  37501         0x1802128c,
  37502         0,
  37503         0,
  37504         2,
  37505         soc_QSPI_MSPI_TXRAM19_BCM88680_A0r_fields,
  37506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37507         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37508         -1,
  37509         -1,
  37510     },
  37511 #endif /* chips */
  37512 
  37513 #if defined(BCM_88690_A0)
  37514     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM88690_A0r */
  37515         soc_block_list[61],
  37516         soc_iprocreg,
  37517         1,
  37518         0,
  37519         0x1802128c,
  37520         0,
  37521         0,
  37522         2,
  37523         soc_QSPI_MSPI_TXRAM19_BCM88690_A0r_fields,
  37524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37526         -1,
  37527         -1,
  37528     },
  37529 #endif /* chips */
  37530 
  37531 #if defined(BCM_88690_B0)
  37532     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM88690_B0r */
  37533         soc_block_list[61],
  37534         soc_iprocreg,
  37535         1,
  37536         0,
  37537         0x1802128c,
  37538         0,
  37539         0,
  37540         2,
  37541         soc_QSPI_MSPI_TXRAM19_BCM88690_B0r_fields,
  37542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37544         -1,
  37545         -1,
  37546     },
  37547 #endif /* chips */
  37548 
  37549 #if defined(BCM_88790_A0)
  37550     { /* SOC_REG_INT_QSPI_MSPI_TXRAM19_BCM88790_A0r */
  37551         soc_block_list[61],
  37552         soc_iprocreg,
  37553         1,
  37554         0,
  37555         0x1802128c,
  37556         0,
  37557         0,
  37558         2,
  37559         soc_QSPI_MSPI_TXRAM19_BCM88790_A0r_fields,
  37560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37561         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37562         -1,
  37563         -1,
  37564     },
  37565 #endif /* chips */
  37566 
  37567 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37568     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37569     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37570     defined(BCM_56260_B0)
  37571     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM53400_A0r */
  37572         soc_block_list[61],
  37573         soc_iprocreg,
  37574         1,
  37575         0,
  37576         0x18047290,
  37577         0,
  37578         0,
  37579         2,
  37580         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37582         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37583         -1,
  37584         -1,
  37585     },
  37586 #endif /* chips */
  37587 
  37588 #if defined(BCM_56370_A0)
  37589     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM56370_A0r */
  37590         soc_block_list[61],
  37591         soc_iprocreg,
  37592         1,
  37593         0,
  37594         0x15000290,
  37595         0,
  37596         0,
  37597         2,
  37598         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37600         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37601         -1,
  37602         -1,
  37603         3,
  37604     },
  37605 #endif /* chips */
  37606 
  37607 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  37608     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37609     defined(BCM_56450_B1)
  37610     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM56450_A0r */
  37611         soc_block_list[61],
  37612         soc_iprocreg,
  37613         1,
  37614         0,
  37615         0x18027290,
  37616         0,
  37617         0,
  37618         2,
  37619         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  37620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37621         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37622         -1,
  37623         -1,
  37624     },
  37625 #endif /* chips */
  37626 
  37627 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  37628     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  37629     defined(BCM_56670_B0)
  37630     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM56560_A0r */
  37631         soc_block_list[61],
  37632         soc_iprocreg,
  37633         1,
  37634         0,
  37635         0x18021290,
  37636         0,
  37637         0,
  37638         2,
  37639         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37641         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37642         -1,
  37643         -1,
  37644     },
  37645 #endif /* chips */
  37646 
  37647 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  37648     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  37649     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  37650     defined(BCM_56980_B0)
  37651     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM56960_A0r */
  37652         soc_block_list[61],
  37653         soc_iprocreg,
  37654         1,
  37655         0,
  37656         0x18021290,
  37657         0,
  37658         0,
  37659         2,
  37660         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37662         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37663         -1,
  37664         -1,
  37665         3,
  37666     },
  37667 #endif /* chips */
  37668 
  37669 #if defined(BCM_88270_A0)
  37670     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM88270_A0r */
  37671         soc_block_list[61],
  37672         soc_iprocreg,
  37673         1,
  37674         0,
  37675         0x18021290,
  37676         0,
  37677         0,
  37678         2,
  37679         soc_QSPI_MSPI_TXRAM20_BCM88270_A0r_fields,
  37680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37681         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37682         -1,
  37683         -1,
  37684     },
  37685 #endif /* chips */
  37686 
  37687 #if defined(BCM_88375_A0)
  37688     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM88375_A0r */
  37689         soc_block_list[61],
  37690         soc_iprocreg,
  37691         1,
  37692         0,
  37693         0x18021290,
  37694         0,
  37695         0,
  37696         2,
  37697         soc_QSPI_MSPI_TXRAM20_BCM88375_A0r_fields,
  37698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37699         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37700         -1,
  37701         -1,
  37702     },
  37703 #endif /* chips */
  37704 
  37705 #if defined(BCM_88375_B0)
  37706     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM88375_B0r */
  37707         soc_block_list[61],
  37708         soc_iprocreg,
  37709         1,
  37710         0,
  37711         0x18021290,
  37712         0,
  37713         0,
  37714         2,
  37715         soc_QSPI_MSPI_TXRAM20_BCM88375_B0r_fields,
  37716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37718         -1,
  37719         -1,
  37720     },
  37721 #endif /* chips */
  37722 
  37723 #if defined(BCM_88470_A0)
  37724     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM88470_A0r */
  37725         soc_block_list[61],
  37726         soc_iprocreg,
  37727         1,
  37728         0,
  37729         0x18021290,
  37730         0,
  37731         0,
  37732         2,
  37733         soc_QSPI_MSPI_TXRAM20_BCM88470_A0r_fields,
  37734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37736         -1,
  37737         -1,
  37738     },
  37739 #endif /* chips */
  37740 
  37741 #if defined(BCM_88470_B0)
  37742     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM88470_B0r */
  37743         soc_block_list[61],
  37744         soc_iprocreg,
  37745         1,
  37746         0,
  37747         0x18021290,
  37748         0,
  37749         0,
  37750         2,
  37751         soc_QSPI_MSPI_TXRAM20_BCM88470_B0r_fields,
  37752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37753         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37754         -1,
  37755         -1,
  37756     },
  37757 #endif /* chips */
  37758 
  37759 #if defined(BCM_88675_B0)
  37760     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM88675_B0r */
  37761         soc_block_list[61],
  37762         soc_iprocreg,
  37763         1,
  37764         0,
  37765         0x18021290,
  37766         0,
  37767         0,
  37768         2,
  37769         soc_QSPI_MSPI_TXRAM20_BCM88675_B0r_fields,
  37770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37771         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37772         -1,
  37773         -1,
  37774     },
  37775 #endif /* chips */
  37776 
  37777 #if defined(BCM_88680_A0)
  37778     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM88680_A0r */
  37779         soc_block_list[61],
  37780         soc_iprocreg,
  37781         1,
  37782         0,
  37783         0x18021290,
  37784         0,
  37785         0,
  37786         2,
  37787         soc_QSPI_MSPI_TXRAM20_BCM88680_A0r_fields,
  37788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37789         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37790         -1,
  37791         -1,
  37792     },
  37793 #endif /* chips */
  37794 
  37795 #if defined(BCM_88690_A0)
  37796     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM88690_A0r */
  37797         soc_block_list[61],
  37798         soc_iprocreg,
  37799         1,
  37800         0,
  37801         0x18021290,
  37802         0,
  37803         0,
  37804         2,
  37805         soc_QSPI_MSPI_TXRAM20_BCM88690_A0r_fields,
  37806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37807         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37808         -1,
  37809         -1,
  37810     },
  37811 #endif /* chips */
  37812 
  37813 #if defined(BCM_88690_B0)
  37814     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM88690_B0r */
  37815         soc_block_list[61],
  37816         soc_iprocreg,
  37817         1,
  37818         0,
  37819         0x18021290,
  37820         0,
  37821         0,
  37822         2,
  37823         soc_QSPI_MSPI_TXRAM20_BCM88690_B0r_fields,
  37824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37825         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37826         -1,
  37827         -1,
  37828     },
  37829 #endif /* chips */
  37830 
  37831 #if defined(BCM_88790_A0)
  37832     { /* SOC_REG_INT_QSPI_MSPI_TXRAM20_BCM88790_A0r */
  37833         soc_block_list[61],
  37834         soc_iprocreg,
  37835         1,
  37836         0,
  37837         0x18021290,
  37838         0,
  37839         0,
  37840         2,
  37841         soc_QSPI_MSPI_TXRAM20_BCM88790_A0r_fields,
  37842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37843         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37844         -1,
  37845         -1,
  37846     },
  37847 #endif /* chips */
  37848 
  37849 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  37850     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  37851     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  37852     defined(BCM_56260_B0)
  37853     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM53400_A0r */
  37854         soc_block_list[61],
  37855         soc_iprocreg,
  37856         1,
  37857         0,
  37858         0x18047294,
  37859         0,
  37860         0,
  37861         2,
  37862         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37864         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37865         -1,
  37866         -1,
  37867     },
  37868 #endif /* chips */
  37869 
  37870 #if defined(BCM_56370_A0)
  37871     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM56370_A0r */
  37872         soc_block_list[61],
  37873         soc_iprocreg,
  37874         1,
  37875         0,
  37876         0x15000294,
  37877         0,
  37878         0,
  37879         2,
  37880         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37881         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37882         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37883         -1,
  37884         -1,
  37885         3,
  37886     },
  37887 #endif /* chips */
  37888 
  37889 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  37890     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  37891     defined(BCM_56450_B1)
  37892     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM56450_A0r */
  37893         soc_block_list[61],
  37894         soc_iprocreg,
  37895         1,
  37896         0,
  37897         0x18027294,
  37898         0,
  37899         0,
  37900         2,
  37901         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  37902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37903         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37904         -1,
  37905         -1,
  37906     },
  37907 #endif /* chips */
  37908 
  37909 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  37910     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  37911     defined(BCM_56670_B0)
  37912     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM56560_A0r */
  37913         soc_block_list[61],
  37914         soc_iprocreg,
  37915         1,
  37916         0,
  37917         0x18021294,
  37918         0,
  37919         0,
  37920         2,
  37921         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37923         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37924         -1,
  37925         -1,
  37926     },
  37927 #endif /* chips */
  37928 
  37929 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  37930     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  37931     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  37932     defined(BCM_56980_B0)
  37933     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM56960_A0r */
  37934         soc_block_list[61],
  37935         soc_iprocreg,
  37936         1,
  37937         0,
  37938         0x18021294,
  37939         0,
  37940         0,
  37941         2,
  37942         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  37943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37944         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37945         -1,
  37946         -1,
  37947         3,
  37948     },
  37949 #endif /* chips */
  37950 
  37951 #if defined(BCM_88270_A0)
  37952     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM88270_A0r */
  37953         soc_block_list[61],
  37954         soc_iprocreg,
  37955         1,
  37956         0,
  37957         0x18021294,
  37958         0,
  37959         0,
  37960         2,
  37961         soc_QSPI_MSPI_TXRAM21_BCM88270_A0r_fields,
  37962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37964         -1,
  37965         -1,
  37966     },
  37967 #endif /* chips */
  37968 
  37969 #if defined(BCM_88375_A0)
  37970     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM88375_A0r */
  37971         soc_block_list[61],
  37972         soc_iprocreg,
  37973         1,
  37974         0,
  37975         0x18021294,
  37976         0,
  37977         0,
  37978         2,
  37979         soc_QSPI_MSPI_TXRAM21_BCM88375_A0r_fields,
  37980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37981         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  37982         -1,
  37983         -1,
  37984     },
  37985 #endif /* chips */
  37986 
  37987 #if defined(BCM_88375_B0)
  37988     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM88375_B0r */
  37989         soc_block_list[61],
  37990         soc_iprocreg,
  37991         1,
  37992         0,
  37993         0x18021294,
  37994         0,
  37995         0,
  37996         2,
  37997         soc_QSPI_MSPI_TXRAM21_BCM88375_B0r_fields,
  37998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37999         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38000         -1,
  38001         -1,
  38002     },
  38003 #endif /* chips */
  38004 
  38005 #if defined(BCM_88470_A0)
  38006     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM88470_A0r */
  38007         soc_block_list[61],
  38008         soc_iprocreg,
  38009         1,
  38010         0,
  38011         0x18021294,
  38012         0,
  38013         0,
  38014         2,
  38015         soc_QSPI_MSPI_TXRAM21_BCM88470_A0r_fields,
  38016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38018         -1,
  38019         -1,
  38020     },
  38021 #endif /* chips */
  38022 
  38023 #if defined(BCM_88470_B0)
  38024     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM88470_B0r */
  38025         soc_block_list[61],
  38026         soc_iprocreg,
  38027         1,
  38028         0,
  38029         0x18021294,
  38030         0,
  38031         0,
  38032         2,
  38033         soc_QSPI_MSPI_TXRAM21_BCM88470_B0r_fields,
  38034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38035         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38036         -1,
  38037         -1,
  38038     },
  38039 #endif /* chips */
  38040 
  38041 #if defined(BCM_88675_B0)
  38042     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM88675_B0r */
  38043         soc_block_list[61],
  38044         soc_iprocreg,
  38045         1,
  38046         0,
  38047         0x18021294,
  38048         0,
  38049         0,
  38050         2,
  38051         soc_QSPI_MSPI_TXRAM21_BCM88675_B0r_fields,
  38052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38053         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38054         -1,
  38055         -1,
  38056     },
  38057 #endif /* chips */
  38058 
  38059 #if defined(BCM_88680_A0)
  38060     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM88680_A0r */
  38061         soc_block_list[61],
  38062         soc_iprocreg,
  38063         1,
  38064         0,
  38065         0x18021294,
  38066         0,
  38067         0,
  38068         2,
  38069         soc_QSPI_MSPI_TXRAM21_BCM88680_A0r_fields,
  38070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38071         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38072         -1,
  38073         -1,
  38074     },
  38075 #endif /* chips */
  38076 
  38077 #if defined(BCM_88690_A0)
  38078     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM88690_A0r */
  38079         soc_block_list[61],
  38080         soc_iprocreg,
  38081         1,
  38082         0,
  38083         0x18021294,
  38084         0,
  38085         0,
  38086         2,
  38087         soc_QSPI_MSPI_TXRAM21_BCM88690_A0r_fields,
  38088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38089         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38090         -1,
  38091         -1,
  38092     },
  38093 #endif /* chips */
  38094 
  38095 #if defined(BCM_88690_B0)
  38096     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM88690_B0r */
  38097         soc_block_list[61],
  38098         soc_iprocreg,
  38099         1,
  38100         0,
  38101         0x18021294,
  38102         0,
  38103         0,
  38104         2,
  38105         soc_QSPI_MSPI_TXRAM21_BCM88690_B0r_fields,
  38106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38107         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38108         -1,
  38109         -1,
  38110     },
  38111 #endif /* chips */
  38112 
  38113 #if defined(BCM_88790_A0)
  38114     { /* SOC_REG_INT_QSPI_MSPI_TXRAM21_BCM88790_A0r */
  38115         soc_block_list[61],
  38116         soc_iprocreg,
  38117         1,
  38118         0,
  38119         0x18021294,
  38120         0,
  38121         0,
  38122         2,
  38123         soc_QSPI_MSPI_TXRAM21_BCM88790_A0r_fields,
  38124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38125         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38126         -1,
  38127         -1,
  38128     },
  38129 #endif /* chips */
  38130 
  38131 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38132     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38133     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38134     defined(BCM_56260_B0)
  38135     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM53400_A0r */
  38136         soc_block_list[61],
  38137         soc_iprocreg,
  38138         1,
  38139         0,
  38140         0x18047298,
  38141         0,
  38142         0,
  38143         2,
  38144         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38146         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38147         -1,
  38148         -1,
  38149     },
  38150 #endif /* chips */
  38151 
  38152 #if defined(BCM_56370_A0)
  38153     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM56370_A0r */
  38154         soc_block_list[61],
  38155         soc_iprocreg,
  38156         1,
  38157         0,
  38158         0x15000298,
  38159         0,
  38160         0,
  38161         2,
  38162         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38164         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38165         -1,
  38166         -1,
  38167         3,
  38168     },
  38169 #endif /* chips */
  38170 
  38171 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  38172     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  38173     defined(BCM_56450_B1)
  38174     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM56450_A0r */
  38175         soc_block_list[61],
  38176         soc_iprocreg,
  38177         1,
  38178         0,
  38179         0x18027298,
  38180         0,
  38181         0,
  38182         2,
  38183         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  38184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38186         -1,
  38187         -1,
  38188     },
  38189 #endif /* chips */
  38190 
  38191 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  38192     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  38193     defined(BCM_56670_B0)
  38194     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM56560_A0r */
  38195         soc_block_list[61],
  38196         soc_iprocreg,
  38197         1,
  38198         0,
  38199         0x18021298,
  38200         0,
  38201         0,
  38202         2,
  38203         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38205         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38206         -1,
  38207         -1,
  38208     },
  38209 #endif /* chips */
  38210 
  38211 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  38212     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  38213     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  38214     defined(BCM_56980_B0)
  38215     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM56960_A0r */
  38216         soc_block_list[61],
  38217         soc_iprocreg,
  38218         1,
  38219         0,
  38220         0x18021298,
  38221         0,
  38222         0,
  38223         2,
  38224         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38226         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38227         -1,
  38228         -1,
  38229         3,
  38230     },
  38231 #endif /* chips */
  38232 
  38233 #if defined(BCM_88270_A0)
  38234     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM88270_A0r */
  38235         soc_block_list[61],
  38236         soc_iprocreg,
  38237         1,
  38238         0,
  38239         0x18021298,
  38240         0,
  38241         0,
  38242         2,
  38243         soc_QSPI_MSPI_TXRAM22_BCM88270_A0r_fields,
  38244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38246         -1,
  38247         -1,
  38248     },
  38249 #endif /* chips */
  38250 
  38251 #if defined(BCM_88375_A0)
  38252     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM88375_A0r */
  38253         soc_block_list[61],
  38254         soc_iprocreg,
  38255         1,
  38256         0,
  38257         0x18021298,
  38258         0,
  38259         0,
  38260         2,
  38261         soc_QSPI_MSPI_TXRAM22_BCM88375_A0r_fields,
  38262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38264         -1,
  38265         -1,
  38266     },
  38267 #endif /* chips */
  38268 
  38269 #if defined(BCM_88375_B0)
  38270     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM88375_B0r */
  38271         soc_block_list[61],
  38272         soc_iprocreg,
  38273         1,
  38274         0,
  38275         0x18021298,
  38276         0,
  38277         0,
  38278         2,
  38279         soc_QSPI_MSPI_TXRAM22_BCM88375_B0r_fields,
  38280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38281         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38282         -1,
  38283         -1,
  38284     },
  38285 #endif /* chips */
  38286 
  38287 #if defined(BCM_88470_A0)
  38288     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM88470_A0r */
  38289         soc_block_list[61],
  38290         soc_iprocreg,
  38291         1,
  38292         0,
  38293         0x18021298,
  38294         0,
  38295         0,
  38296         2,
  38297         soc_QSPI_MSPI_TXRAM22_BCM88470_A0r_fields,
  38298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38300         -1,
  38301         -1,
  38302     },
  38303 #endif /* chips */
  38304 
  38305 #if defined(BCM_88470_B0)
  38306     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM88470_B0r */
  38307         soc_block_list[61],
  38308         soc_iprocreg,
  38309         1,
  38310         0,
  38311         0x18021298,
  38312         0,
  38313         0,
  38314         2,
  38315         soc_QSPI_MSPI_TXRAM22_BCM88470_B0r_fields,
  38316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38318         -1,
  38319         -1,
  38320     },
  38321 #endif /* chips */
  38322 
  38323 #if defined(BCM_88675_B0)
  38324     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM88675_B0r */
  38325         soc_block_list[61],
  38326         soc_iprocreg,
  38327         1,
  38328         0,
  38329         0x18021298,
  38330         0,
  38331         0,
  38332         2,
  38333         soc_QSPI_MSPI_TXRAM22_BCM88675_B0r_fields,
  38334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38335         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38336         -1,
  38337         -1,
  38338     },
  38339 #endif /* chips */
  38340 
  38341 #if defined(BCM_88680_A0)
  38342     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM88680_A0r */
  38343         soc_block_list[61],
  38344         soc_iprocreg,
  38345         1,
  38346         0,
  38347         0x18021298,
  38348         0,
  38349         0,
  38350         2,
  38351         soc_QSPI_MSPI_TXRAM22_BCM88680_A0r_fields,
  38352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38353         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38354         -1,
  38355         -1,
  38356     },
  38357 #endif /* chips */
  38358 
  38359 #if defined(BCM_88690_A0)
  38360     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM88690_A0r */
  38361         soc_block_list[61],
  38362         soc_iprocreg,
  38363         1,
  38364         0,
  38365         0x18021298,
  38366         0,
  38367         0,
  38368         2,
  38369         soc_QSPI_MSPI_TXRAM22_BCM88690_A0r_fields,
  38370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38371         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38372         -1,
  38373         -1,
  38374     },
  38375 #endif /* chips */
  38376 
  38377 #if defined(BCM_88690_B0)
  38378     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM88690_B0r */
  38379         soc_block_list[61],
  38380         soc_iprocreg,
  38381         1,
  38382         0,
  38383         0x18021298,
  38384         0,
  38385         0,
  38386         2,
  38387         soc_QSPI_MSPI_TXRAM22_BCM88690_B0r_fields,
  38388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38389         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38390         -1,
  38391         -1,
  38392     },
  38393 #endif /* chips */
  38394 
  38395 #if defined(BCM_88790_A0)
  38396     { /* SOC_REG_INT_QSPI_MSPI_TXRAM22_BCM88790_A0r */
  38397         soc_block_list[61],
  38398         soc_iprocreg,
  38399         1,
  38400         0,
  38401         0x18021298,
  38402         0,
  38403         0,
  38404         2,
  38405         soc_QSPI_MSPI_TXRAM22_BCM88790_A0r_fields,
  38406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38407         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38408         -1,
  38409         -1,
  38410     },
  38411 #endif /* chips */
  38412 
  38413 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38414     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38415     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38416     defined(BCM_56260_B0)
  38417     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM53400_A0r */
  38418         soc_block_list[61],
  38419         soc_iprocreg,
  38420         1,
  38421         0,
  38422         0x1804729c,
  38423         0,
  38424         0,
  38425         2,
  38426         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38428         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38429         -1,
  38430         -1,
  38431     },
  38432 #endif /* chips */
  38433 
  38434 #if defined(BCM_56370_A0)
  38435     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM56370_A0r */
  38436         soc_block_list[61],
  38437         soc_iprocreg,
  38438         1,
  38439         0,
  38440         0x1500029c,
  38441         0,
  38442         0,
  38443         2,
  38444         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38446         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38447         -1,
  38448         -1,
  38449         3,
  38450     },
  38451 #endif /* chips */
  38452 
  38453 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  38454     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  38455     defined(BCM_56450_B1)
  38456     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM56450_A0r */
  38457         soc_block_list[61],
  38458         soc_iprocreg,
  38459         1,
  38460         0,
  38461         0x1802729c,
  38462         0,
  38463         0,
  38464         2,
  38465         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  38466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38467         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38468         -1,
  38469         -1,
  38470     },
  38471 #endif /* chips */
  38472 
  38473 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  38474     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  38475     defined(BCM_56670_B0)
  38476     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM56560_A0r */
  38477         soc_block_list[61],
  38478         soc_iprocreg,
  38479         1,
  38480         0,
  38481         0x1802129c,
  38482         0,
  38483         0,
  38484         2,
  38485         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38487         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38488         -1,
  38489         -1,
  38490     },
  38491 #endif /* chips */
  38492 
  38493 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  38494     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  38495     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  38496     defined(BCM_56980_B0)
  38497     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM56960_A0r */
  38498         soc_block_list[61],
  38499         soc_iprocreg,
  38500         1,
  38501         0,
  38502         0x1802129c,
  38503         0,
  38504         0,
  38505         2,
  38506         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38508         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38509         -1,
  38510         -1,
  38511         3,
  38512     },
  38513 #endif /* chips */
  38514 
  38515 #if defined(BCM_88270_A0)
  38516     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM88270_A0r */
  38517         soc_block_list[61],
  38518         soc_iprocreg,
  38519         1,
  38520         0,
  38521         0x1802129c,
  38522         0,
  38523         0,
  38524         2,
  38525         soc_QSPI_MSPI_TXRAM23_BCM88270_A0r_fields,
  38526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38527         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38528         -1,
  38529         -1,
  38530     },
  38531 #endif /* chips */
  38532 
  38533 #if defined(BCM_88375_A0)
  38534     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM88375_A0r */
  38535         soc_block_list[61],
  38536         soc_iprocreg,
  38537         1,
  38538         0,
  38539         0x1802129c,
  38540         0,
  38541         0,
  38542         2,
  38543         soc_QSPI_MSPI_TXRAM23_BCM88375_A0r_fields,
  38544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38545         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38546         -1,
  38547         -1,
  38548     },
  38549 #endif /* chips */
  38550 
  38551 #if defined(BCM_88375_B0)
  38552     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM88375_B0r */
  38553         soc_block_list[61],
  38554         soc_iprocreg,
  38555         1,
  38556         0,
  38557         0x1802129c,
  38558         0,
  38559         0,
  38560         2,
  38561         soc_QSPI_MSPI_TXRAM23_BCM88375_B0r_fields,
  38562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38563         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38564         -1,
  38565         -1,
  38566     },
  38567 #endif /* chips */
  38568 
  38569 #if defined(BCM_88470_A0)
  38570     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM88470_A0r */
  38571         soc_block_list[61],
  38572         soc_iprocreg,
  38573         1,
  38574         0,
  38575         0x1802129c,
  38576         0,
  38577         0,
  38578         2,
  38579         soc_QSPI_MSPI_TXRAM23_BCM88470_A0r_fields,
  38580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38581         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38582         -1,
  38583         -1,
  38584     },
  38585 #endif /* chips */
  38586 
  38587 #if defined(BCM_88470_B0)
  38588     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM88470_B0r */
  38589         soc_block_list[61],
  38590         soc_iprocreg,
  38591         1,
  38592         0,
  38593         0x1802129c,
  38594         0,
  38595         0,
  38596         2,
  38597         soc_QSPI_MSPI_TXRAM23_BCM88470_B0r_fields,
  38598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38599         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38600         -1,
  38601         -1,
  38602     },
  38603 #endif /* chips */
  38604 
  38605 #if defined(BCM_88675_B0)
  38606     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM88675_B0r */
  38607         soc_block_list[61],
  38608         soc_iprocreg,
  38609         1,
  38610         0,
  38611         0x1802129c,
  38612         0,
  38613         0,
  38614         2,
  38615         soc_QSPI_MSPI_TXRAM23_BCM88675_B0r_fields,
  38616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38618         -1,
  38619         -1,
  38620     },
  38621 #endif /* chips */
  38622 
  38623 #if defined(BCM_88680_A0)
  38624     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM88680_A0r */
  38625         soc_block_list[61],
  38626         soc_iprocreg,
  38627         1,
  38628         0,
  38629         0x1802129c,
  38630         0,
  38631         0,
  38632         2,
  38633         soc_QSPI_MSPI_TXRAM23_BCM88680_A0r_fields,
  38634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38635         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38636         -1,
  38637         -1,
  38638     },
  38639 #endif /* chips */
  38640 
  38641 #if defined(BCM_88690_A0)
  38642     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM88690_A0r */
  38643         soc_block_list[61],
  38644         soc_iprocreg,
  38645         1,
  38646         0,
  38647         0x1802129c,
  38648         0,
  38649         0,
  38650         2,
  38651         soc_QSPI_MSPI_TXRAM23_BCM88690_A0r_fields,
  38652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38653         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38654         -1,
  38655         -1,
  38656     },
  38657 #endif /* chips */
  38658 
  38659 #if defined(BCM_88690_B0)
  38660     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM88690_B0r */
  38661         soc_block_list[61],
  38662         soc_iprocreg,
  38663         1,
  38664         0,
  38665         0x1802129c,
  38666         0,
  38667         0,
  38668         2,
  38669         soc_QSPI_MSPI_TXRAM23_BCM88690_B0r_fields,
  38670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38671         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38672         -1,
  38673         -1,
  38674     },
  38675 #endif /* chips */
  38676 
  38677 #if defined(BCM_88790_A0)
  38678     { /* SOC_REG_INT_QSPI_MSPI_TXRAM23_BCM88790_A0r */
  38679         soc_block_list[61],
  38680         soc_iprocreg,
  38681         1,
  38682         0,
  38683         0x1802129c,
  38684         0,
  38685         0,
  38686         2,
  38687         soc_QSPI_MSPI_TXRAM23_BCM88790_A0r_fields,
  38688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38690         -1,
  38691         -1,
  38692     },
  38693 #endif /* chips */
  38694 
  38695 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38696     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38697     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38698     defined(BCM_56260_B0)
  38699     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM53400_A0r */
  38700         soc_block_list[61],
  38701         soc_iprocreg,
  38702         1,
  38703         0,
  38704         0x180472a0,
  38705         0,
  38706         0,
  38707         2,
  38708         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38710         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38711         -1,
  38712         -1,
  38713     },
  38714 #endif /* chips */
  38715 
  38716 #if defined(BCM_56370_A0)
  38717     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM56370_A0r */
  38718         soc_block_list[61],
  38719         soc_iprocreg,
  38720         1,
  38721         0,
  38722         0x150002a0,
  38723         0,
  38724         0,
  38725         2,
  38726         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38728         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38729         -1,
  38730         -1,
  38731         3,
  38732     },
  38733 #endif /* chips */
  38734 
  38735 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  38736     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  38737     defined(BCM_56450_B1)
  38738     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM56450_A0r */
  38739         soc_block_list[61],
  38740         soc_iprocreg,
  38741         1,
  38742         0,
  38743         0x180272a0,
  38744         0,
  38745         0,
  38746         2,
  38747         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  38748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38749         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38750         -1,
  38751         -1,
  38752     },
  38753 #endif /* chips */
  38754 
  38755 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  38756     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  38757     defined(BCM_56670_B0)
  38758     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM56560_A0r */
  38759         soc_block_list[61],
  38760         soc_iprocreg,
  38761         1,
  38762         0,
  38763         0x180212a0,
  38764         0,
  38765         0,
  38766         2,
  38767         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38769         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38770         -1,
  38771         -1,
  38772     },
  38773 #endif /* chips */
  38774 
  38775 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  38776     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  38777     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  38778     defined(BCM_56980_B0)
  38779     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM56960_A0r */
  38780         soc_block_list[61],
  38781         soc_iprocreg,
  38782         1,
  38783         0,
  38784         0x180212a0,
  38785         0,
  38786         0,
  38787         2,
  38788         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38790         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38791         -1,
  38792         -1,
  38793         3,
  38794     },
  38795 #endif /* chips */
  38796 
  38797 #if defined(BCM_88270_A0)
  38798     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM88270_A0r */
  38799         soc_block_list[61],
  38800         soc_iprocreg,
  38801         1,
  38802         0,
  38803         0x180212a0,
  38804         0,
  38805         0,
  38806         2,
  38807         soc_QSPI_MSPI_TXRAM24_BCM88270_A0r_fields,
  38808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38809         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38810         -1,
  38811         -1,
  38812     },
  38813 #endif /* chips */
  38814 
  38815 #if defined(BCM_88375_A0)
  38816     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM88375_A0r */
  38817         soc_block_list[61],
  38818         soc_iprocreg,
  38819         1,
  38820         0,
  38821         0x180212a0,
  38822         0,
  38823         0,
  38824         2,
  38825         soc_QSPI_MSPI_TXRAM24_BCM88375_A0r_fields,
  38826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38827         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38828         -1,
  38829         -1,
  38830     },
  38831 #endif /* chips */
  38832 
  38833 #if defined(BCM_88375_B0)
  38834     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM88375_B0r */
  38835         soc_block_list[61],
  38836         soc_iprocreg,
  38837         1,
  38838         0,
  38839         0x180212a0,
  38840         0,
  38841         0,
  38842         2,
  38843         soc_QSPI_MSPI_TXRAM24_BCM88375_B0r_fields,
  38844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38845         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38846         -1,
  38847         -1,
  38848     },
  38849 #endif /* chips */
  38850 
  38851 #if defined(BCM_88470_A0)
  38852     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM88470_A0r */
  38853         soc_block_list[61],
  38854         soc_iprocreg,
  38855         1,
  38856         0,
  38857         0x180212a0,
  38858         0,
  38859         0,
  38860         2,
  38861         soc_QSPI_MSPI_TXRAM24_BCM88470_A0r_fields,
  38862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38863         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38864         -1,
  38865         -1,
  38866     },
  38867 #endif /* chips */
  38868 
  38869 #if defined(BCM_88470_B0)
  38870     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM88470_B0r */
  38871         soc_block_list[61],
  38872         soc_iprocreg,
  38873         1,
  38874         0,
  38875         0x180212a0,
  38876         0,
  38877         0,
  38878         2,
  38879         soc_QSPI_MSPI_TXRAM24_BCM88470_B0r_fields,
  38880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38881         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38882         -1,
  38883         -1,
  38884     },
  38885 #endif /* chips */
  38886 
  38887 #if defined(BCM_88675_B0)
  38888     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM88675_B0r */
  38889         soc_block_list[61],
  38890         soc_iprocreg,
  38891         1,
  38892         0,
  38893         0x180212a0,
  38894         0,
  38895         0,
  38896         2,
  38897         soc_QSPI_MSPI_TXRAM24_BCM88675_B0r_fields,
  38898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38899         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38900         -1,
  38901         -1,
  38902     },
  38903 #endif /* chips */
  38904 
  38905 #if defined(BCM_88680_A0)
  38906     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM88680_A0r */
  38907         soc_block_list[61],
  38908         soc_iprocreg,
  38909         1,
  38910         0,
  38911         0x180212a0,
  38912         0,
  38913         0,
  38914         2,
  38915         soc_QSPI_MSPI_TXRAM24_BCM88680_A0r_fields,
  38916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38917         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38918         -1,
  38919         -1,
  38920     },
  38921 #endif /* chips */
  38922 
  38923 #if defined(BCM_88690_A0)
  38924     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM88690_A0r */
  38925         soc_block_list[61],
  38926         soc_iprocreg,
  38927         1,
  38928         0,
  38929         0x180212a0,
  38930         0,
  38931         0,
  38932         2,
  38933         soc_QSPI_MSPI_TXRAM24_BCM88690_A0r_fields,
  38934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38935         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38936         -1,
  38937         -1,
  38938     },
  38939 #endif /* chips */
  38940 
  38941 #if defined(BCM_88690_B0)
  38942     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM88690_B0r */
  38943         soc_block_list[61],
  38944         soc_iprocreg,
  38945         1,
  38946         0,
  38947         0x180212a0,
  38948         0,
  38949         0,
  38950         2,
  38951         soc_QSPI_MSPI_TXRAM24_BCM88690_B0r_fields,
  38952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38953         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38954         -1,
  38955         -1,
  38956     },
  38957 #endif /* chips */
  38958 
  38959 #if defined(BCM_88790_A0)
  38960     { /* SOC_REG_INT_QSPI_MSPI_TXRAM24_BCM88790_A0r */
  38961         soc_block_list[61],
  38962         soc_iprocreg,
  38963         1,
  38964         0,
  38965         0x180212a0,
  38966         0,
  38967         0,
  38968         2,
  38969         soc_QSPI_MSPI_TXRAM24_BCM88790_A0r_fields,
  38970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38971         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38972         -1,
  38973         -1,
  38974     },
  38975 #endif /* chips */
  38976 
  38977 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  38978     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  38979     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  38980     defined(BCM_56260_B0)
  38981     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM53400_A0r */
  38982         soc_block_list[61],
  38983         soc_iprocreg,
  38984         1,
  38985         0,
  38986         0x180472a4,
  38987         0,
  38988         0,
  38989         2,
  38990         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  38991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38992         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  38993         -1,
  38994         -1,
  38995     },
  38996 #endif /* chips */
  38997 
  38998 #if defined(BCM_56370_A0)
  38999     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM56370_A0r */
  39000         soc_block_list[61],
  39001         soc_iprocreg,
  39002         1,
  39003         0,
  39004         0x150002a4,
  39005         0,
  39006         0,
  39007         2,
  39008         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39010         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39011         -1,
  39012         -1,
  39013         3,
  39014     },
  39015 #endif /* chips */
  39016 
  39017 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  39018     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  39019     defined(BCM_56450_B1)
  39020     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM56450_A0r */
  39021         soc_block_list[61],
  39022         soc_iprocreg,
  39023         1,
  39024         0,
  39025         0x180272a4,
  39026         0,
  39027         0,
  39028         2,
  39029         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  39030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39031         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39032         -1,
  39033         -1,
  39034     },
  39035 #endif /* chips */
  39036 
  39037 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  39038     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  39039     defined(BCM_56670_B0)
  39040     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM56560_A0r */
  39041         soc_block_list[61],
  39042         soc_iprocreg,
  39043         1,
  39044         0,
  39045         0x180212a4,
  39046         0,
  39047         0,
  39048         2,
  39049         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39051         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39052         -1,
  39053         -1,
  39054     },
  39055 #endif /* chips */
  39056 
  39057 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  39058     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  39059     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  39060     defined(BCM_56980_B0)
  39061     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM56960_A0r */
  39062         soc_block_list[61],
  39063         soc_iprocreg,
  39064         1,
  39065         0,
  39066         0x180212a4,
  39067         0,
  39068         0,
  39069         2,
  39070         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39072         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39073         -1,
  39074         -1,
  39075         3,
  39076     },
  39077 #endif /* chips */
  39078 
  39079 #if defined(BCM_88270_A0)
  39080     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM88270_A0r */
  39081         soc_block_list[61],
  39082         soc_iprocreg,
  39083         1,
  39084         0,
  39085         0x180212a4,
  39086         0,
  39087         0,
  39088         2,
  39089         soc_QSPI_MSPI_TXRAM25_BCM88270_A0r_fields,
  39090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39091         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39092         -1,
  39093         -1,
  39094     },
  39095 #endif /* chips */
  39096 
  39097 #if defined(BCM_88375_A0)
  39098     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM88375_A0r */
  39099         soc_block_list[61],
  39100         soc_iprocreg,
  39101         1,
  39102         0,
  39103         0x180212a4,
  39104         0,
  39105         0,
  39106         2,
  39107         soc_QSPI_MSPI_TXRAM25_BCM88375_A0r_fields,
  39108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39109         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39110         -1,
  39111         -1,
  39112     },
  39113 #endif /* chips */
  39114 
  39115 #if defined(BCM_88375_B0)
  39116     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM88375_B0r */
  39117         soc_block_list[61],
  39118         soc_iprocreg,
  39119         1,
  39120         0,
  39121         0x180212a4,
  39122         0,
  39123         0,
  39124         2,
  39125         soc_QSPI_MSPI_TXRAM25_BCM88375_B0r_fields,
  39126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39127         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39128         -1,
  39129         -1,
  39130     },
  39131 #endif /* chips */
  39132 
  39133 #if defined(BCM_88470_A0)
  39134     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM88470_A0r */
  39135         soc_block_list[61],
  39136         soc_iprocreg,
  39137         1,
  39138         0,
  39139         0x180212a4,
  39140         0,
  39141         0,
  39142         2,
  39143         soc_QSPI_MSPI_TXRAM25_BCM88470_A0r_fields,
  39144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39145         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39146         -1,
  39147         -1,
  39148     },
  39149 #endif /* chips */
  39150 
  39151 #if defined(BCM_88470_B0)
  39152     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM88470_B0r */
  39153         soc_block_list[61],
  39154         soc_iprocreg,
  39155         1,
  39156         0,
  39157         0x180212a4,
  39158         0,
  39159         0,
  39160         2,
  39161         soc_QSPI_MSPI_TXRAM25_BCM88470_B0r_fields,
  39162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39163         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39164         -1,
  39165         -1,
  39166     },
  39167 #endif /* chips */
  39168 
  39169 #if defined(BCM_88675_B0)
  39170     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM88675_B0r */
  39171         soc_block_list[61],
  39172         soc_iprocreg,
  39173         1,
  39174         0,
  39175         0x180212a4,
  39176         0,
  39177         0,
  39178         2,
  39179         soc_QSPI_MSPI_TXRAM25_BCM88675_B0r_fields,
  39180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39181         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39182         -1,
  39183         -1,
  39184     },
  39185 #endif /* chips */
  39186 
  39187 #if defined(BCM_88680_A0)
  39188     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM88680_A0r */
  39189         soc_block_list[61],
  39190         soc_iprocreg,
  39191         1,
  39192         0,
  39193         0x180212a4,
  39194         0,
  39195         0,
  39196         2,
  39197         soc_QSPI_MSPI_TXRAM25_BCM88680_A0r_fields,
  39198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39199         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39200         -1,
  39201         -1,
  39202     },
  39203 #endif /* chips */
  39204 
  39205 #if defined(BCM_88690_A0)
  39206     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM88690_A0r */
  39207         soc_block_list[61],
  39208         soc_iprocreg,
  39209         1,
  39210         0,
  39211         0x180212a4,
  39212         0,
  39213         0,
  39214         2,
  39215         soc_QSPI_MSPI_TXRAM25_BCM88690_A0r_fields,
  39216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39217         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39218         -1,
  39219         -1,
  39220     },
  39221 #endif /* chips */
  39222 
  39223 #if defined(BCM_88690_B0)
  39224     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM88690_B0r */
  39225         soc_block_list[61],
  39226         soc_iprocreg,
  39227         1,
  39228         0,
  39229         0x180212a4,
  39230         0,
  39231         0,
  39232         2,
  39233         soc_QSPI_MSPI_TXRAM25_BCM88690_B0r_fields,
  39234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39235         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39236         -1,
  39237         -1,
  39238     },
  39239 #endif /* chips */
  39240 
  39241 #if defined(BCM_88790_A0)
  39242     { /* SOC_REG_INT_QSPI_MSPI_TXRAM25_BCM88790_A0r */
  39243         soc_block_list[61],
  39244         soc_iprocreg,
  39245         1,
  39246         0,
  39247         0x180212a4,
  39248         0,
  39249         0,
  39250         2,
  39251         soc_QSPI_MSPI_TXRAM25_BCM88790_A0r_fields,
  39252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39253         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39254         -1,
  39255         -1,
  39256     },
  39257 #endif /* chips */
  39258 
  39259 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  39260     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  39261     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  39262     defined(BCM_56260_B0)
  39263     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM53400_A0r */
  39264         soc_block_list[61],
  39265         soc_iprocreg,
  39266         1,
  39267         0,
  39268         0x180472a8,
  39269         0,
  39270         0,
  39271         2,
  39272         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39274         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39275         -1,
  39276         -1,
  39277     },
  39278 #endif /* chips */
  39279 
  39280 #if defined(BCM_56370_A0)
  39281     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM56370_A0r */
  39282         soc_block_list[61],
  39283         soc_iprocreg,
  39284         1,
  39285         0,
  39286         0x150002a8,
  39287         0,
  39288         0,
  39289         2,
  39290         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39292         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39293         -1,
  39294         -1,
  39295         3,
  39296     },
  39297 #endif /* chips */
  39298 
  39299 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  39300     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  39301     defined(BCM_56450_B1)
  39302     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM56450_A0r */
  39303         soc_block_list[61],
  39304         soc_iprocreg,
  39305         1,
  39306         0,
  39307         0x180272a8,
  39308         0,
  39309         0,
  39310         2,
  39311         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  39312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39313         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39314         -1,
  39315         -1,
  39316     },
  39317 #endif /* chips */
  39318 
  39319 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  39320     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  39321     defined(BCM_56670_B0)
  39322     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM56560_A0r */
  39323         soc_block_list[61],
  39324         soc_iprocreg,
  39325         1,
  39326         0,
  39327         0x180212a8,
  39328         0,
  39329         0,
  39330         2,
  39331         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39333         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39334         -1,
  39335         -1,
  39336     },
  39337 #endif /* chips */
  39338 
  39339 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  39340     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  39341     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  39342     defined(BCM_56980_B0)
  39343     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM56960_A0r */
  39344         soc_block_list[61],
  39345         soc_iprocreg,
  39346         1,
  39347         0,
  39348         0x180212a8,
  39349         0,
  39350         0,
  39351         2,
  39352         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39354         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39355         -1,
  39356         -1,
  39357         3,
  39358     },
  39359 #endif /* chips */
  39360 
  39361 #if defined(BCM_88270_A0)
  39362     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM88270_A0r */
  39363         soc_block_list[61],
  39364         soc_iprocreg,
  39365         1,
  39366         0,
  39367         0x180212a8,
  39368         0,
  39369         0,
  39370         2,
  39371         soc_QSPI_MSPI_TXRAM26_BCM88270_A0r_fields,
  39372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39373         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39374         -1,
  39375         -1,
  39376     },
  39377 #endif /* chips */
  39378 
  39379 #if defined(BCM_88375_A0)
  39380     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM88375_A0r */
  39381         soc_block_list[61],
  39382         soc_iprocreg,
  39383         1,
  39384         0,
  39385         0x180212a8,
  39386         0,
  39387         0,
  39388         2,
  39389         soc_QSPI_MSPI_TXRAM26_BCM88375_A0r_fields,
  39390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39391         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39392         -1,
  39393         -1,
  39394     },
  39395 #endif /* chips */
  39396 
  39397 #if defined(BCM_88375_B0)
  39398     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM88375_B0r */
  39399         soc_block_list[61],
  39400         soc_iprocreg,
  39401         1,
  39402         0,
  39403         0x180212a8,
  39404         0,
  39405         0,
  39406         2,
  39407         soc_QSPI_MSPI_TXRAM26_BCM88375_B0r_fields,
  39408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39409         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39410         -1,
  39411         -1,
  39412     },
  39413 #endif /* chips */
  39414 
  39415 #if defined(BCM_88470_A0)
  39416     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM88470_A0r */
  39417         soc_block_list[61],
  39418         soc_iprocreg,
  39419         1,
  39420         0,
  39421         0x180212a8,
  39422         0,
  39423         0,
  39424         2,
  39425         soc_QSPI_MSPI_TXRAM26_BCM88470_A0r_fields,
  39426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39428         -1,
  39429         -1,
  39430     },
  39431 #endif /* chips */
  39432 
  39433 #if defined(BCM_88470_B0)
  39434     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM88470_B0r */
  39435         soc_block_list[61],
  39436         soc_iprocreg,
  39437         1,
  39438         0,
  39439         0x180212a8,
  39440         0,
  39441         0,
  39442         2,
  39443         soc_QSPI_MSPI_TXRAM26_BCM88470_B0r_fields,
  39444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39446         -1,
  39447         -1,
  39448     },
  39449 #endif /* chips */
  39450 
  39451 #if defined(BCM_88675_B0)
  39452     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM88675_B0r */
  39453         soc_block_list[61],
  39454         soc_iprocreg,
  39455         1,
  39456         0,
  39457         0x180212a8,
  39458         0,
  39459         0,
  39460         2,
  39461         soc_QSPI_MSPI_TXRAM26_BCM88675_B0r_fields,
  39462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39463         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39464         -1,
  39465         -1,
  39466     },
  39467 #endif /* chips */
  39468 
  39469 #if defined(BCM_88680_A0)
  39470     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM88680_A0r */
  39471         soc_block_list[61],
  39472         soc_iprocreg,
  39473         1,
  39474         0,
  39475         0x180212a8,
  39476         0,
  39477         0,
  39478         2,
  39479         soc_QSPI_MSPI_TXRAM26_BCM88680_A0r_fields,
  39480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39481         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39482         -1,
  39483         -1,
  39484     },
  39485 #endif /* chips */
  39486 
  39487 #if defined(BCM_88690_A0)
  39488     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM88690_A0r */
  39489         soc_block_list[61],
  39490         soc_iprocreg,
  39491         1,
  39492         0,
  39493         0x180212a8,
  39494         0,
  39495         0,
  39496         2,
  39497         soc_QSPI_MSPI_TXRAM26_BCM88690_A0r_fields,
  39498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39499         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39500         -1,
  39501         -1,
  39502     },
  39503 #endif /* chips */
  39504 
  39505 #if defined(BCM_88690_B0)
  39506     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM88690_B0r */
  39507         soc_block_list[61],
  39508         soc_iprocreg,
  39509         1,
  39510         0,
  39511         0x180212a8,
  39512         0,
  39513         0,
  39514         2,
  39515         soc_QSPI_MSPI_TXRAM26_BCM88690_B0r_fields,
  39516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39517         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39518         -1,
  39519         -1,
  39520     },
  39521 #endif /* chips */
  39522 
  39523 #if defined(BCM_88790_A0)
  39524     { /* SOC_REG_INT_QSPI_MSPI_TXRAM26_BCM88790_A0r */
  39525         soc_block_list[61],
  39526         soc_iprocreg,
  39527         1,
  39528         0,
  39529         0x180212a8,
  39530         0,
  39531         0,
  39532         2,
  39533         soc_QSPI_MSPI_TXRAM26_BCM88790_A0r_fields,
  39534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39535         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39536         -1,
  39537         -1,
  39538     },
  39539 #endif /* chips */
  39540 
  39541 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  39542     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  39543     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  39544     defined(BCM_56260_B0)
  39545     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM53400_A0r */
  39546         soc_block_list[61],
  39547         soc_iprocreg,
  39548         1,
  39549         0,
  39550         0x180472ac,
  39551         0,
  39552         0,
  39553         2,
  39554         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39556         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39557         -1,
  39558         -1,
  39559     },
  39560 #endif /* chips */
  39561 
  39562 #if defined(BCM_56370_A0)
  39563     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM56370_A0r */
  39564         soc_block_list[61],
  39565         soc_iprocreg,
  39566         1,
  39567         0,
  39568         0x150002ac,
  39569         0,
  39570         0,
  39571         2,
  39572         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39574         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39575         -1,
  39576         -1,
  39577         3,
  39578     },
  39579 #endif /* chips */
  39580 
  39581 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  39582     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  39583     defined(BCM_56450_B1)
  39584     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM56450_A0r */
  39585         soc_block_list[61],
  39586         soc_iprocreg,
  39587         1,
  39588         0,
  39589         0x180272ac,
  39590         0,
  39591         0,
  39592         2,
  39593         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  39594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39595         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39596         -1,
  39597         -1,
  39598     },
  39599 #endif /* chips */
  39600 
  39601 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  39602     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  39603     defined(BCM_56670_B0)
  39604     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM56560_A0r */
  39605         soc_block_list[61],
  39606         soc_iprocreg,
  39607         1,
  39608         0,
  39609         0x180212ac,
  39610         0,
  39611         0,
  39612         2,
  39613         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39615         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39616         -1,
  39617         -1,
  39618     },
  39619 #endif /* chips */
  39620 
  39621 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  39622     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  39623     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  39624     defined(BCM_56980_B0)
  39625     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM56960_A0r */
  39626         soc_block_list[61],
  39627         soc_iprocreg,
  39628         1,
  39629         0,
  39630         0x180212ac,
  39631         0,
  39632         0,
  39633         2,
  39634         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39636         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39637         -1,
  39638         -1,
  39639         3,
  39640     },
  39641 #endif /* chips */
  39642 
  39643 #if defined(BCM_88270_A0)
  39644     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM88270_A0r */
  39645         soc_block_list[61],
  39646         soc_iprocreg,
  39647         1,
  39648         0,
  39649         0x180212ac,
  39650         0,
  39651         0,
  39652         2,
  39653         soc_QSPI_MSPI_TXRAM27_BCM88270_A0r_fields,
  39654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39655         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39656         -1,
  39657         -1,
  39658     },
  39659 #endif /* chips */
  39660 
  39661 #if defined(BCM_88375_A0)
  39662     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM88375_A0r */
  39663         soc_block_list[61],
  39664         soc_iprocreg,
  39665         1,
  39666         0,
  39667         0x180212ac,
  39668         0,
  39669         0,
  39670         2,
  39671         soc_QSPI_MSPI_TXRAM27_BCM88375_A0r_fields,
  39672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39673         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39674         -1,
  39675         -1,
  39676     },
  39677 #endif /* chips */
  39678 
  39679 #if defined(BCM_88375_B0)
  39680     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM88375_B0r */
  39681         soc_block_list[61],
  39682         soc_iprocreg,
  39683         1,
  39684         0,
  39685         0x180212ac,
  39686         0,
  39687         0,
  39688         2,
  39689         soc_QSPI_MSPI_TXRAM27_BCM88375_B0r_fields,
  39690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39691         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39692         -1,
  39693         -1,
  39694     },
  39695 #endif /* chips */
  39696 
  39697 #if defined(BCM_88470_A0)
  39698     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM88470_A0r */
  39699         soc_block_list[61],
  39700         soc_iprocreg,
  39701         1,
  39702         0,
  39703         0x180212ac,
  39704         0,
  39705         0,
  39706         2,
  39707         soc_QSPI_MSPI_TXRAM27_BCM88470_A0r_fields,
  39708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39709         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39710         -1,
  39711         -1,
  39712     },
  39713 #endif /* chips */
  39714 
  39715 #if defined(BCM_88470_B0)
  39716     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM88470_B0r */
  39717         soc_block_list[61],
  39718         soc_iprocreg,
  39719         1,
  39720         0,
  39721         0x180212ac,
  39722         0,
  39723         0,
  39724         2,
  39725         soc_QSPI_MSPI_TXRAM27_BCM88470_B0r_fields,
  39726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39727         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39728         -1,
  39729         -1,
  39730     },
  39731 #endif /* chips */
  39732 
  39733 #if defined(BCM_88675_B0)
  39734     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM88675_B0r */
  39735         soc_block_list[61],
  39736         soc_iprocreg,
  39737         1,
  39738         0,
  39739         0x180212ac,
  39740         0,
  39741         0,
  39742         2,
  39743         soc_QSPI_MSPI_TXRAM27_BCM88675_B0r_fields,
  39744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39745         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39746         -1,
  39747         -1,
  39748     },
  39749 #endif /* chips */
  39750 
  39751 #if defined(BCM_88680_A0)
  39752     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM88680_A0r */
  39753         soc_block_list[61],
  39754         soc_iprocreg,
  39755         1,
  39756         0,
  39757         0x180212ac,
  39758         0,
  39759         0,
  39760         2,
  39761         soc_QSPI_MSPI_TXRAM27_BCM88680_A0r_fields,
  39762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39763         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39764         -1,
  39765         -1,
  39766     },
  39767 #endif /* chips */
  39768 
  39769 #if defined(BCM_88690_A0)
  39770     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM88690_A0r */
  39771         soc_block_list[61],
  39772         soc_iprocreg,
  39773         1,
  39774         0,
  39775         0x180212ac,
  39776         0,
  39777         0,
  39778         2,
  39779         soc_QSPI_MSPI_TXRAM27_BCM88690_A0r_fields,
  39780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39781         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39782         -1,
  39783         -1,
  39784     },
  39785 #endif /* chips */
  39786 
  39787 #if defined(BCM_88690_B0)
  39788     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM88690_B0r */
  39789         soc_block_list[61],
  39790         soc_iprocreg,
  39791         1,
  39792         0,
  39793         0x180212ac,
  39794         0,
  39795         0,
  39796         2,
  39797         soc_QSPI_MSPI_TXRAM27_BCM88690_B0r_fields,
  39798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39799         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39800         -1,
  39801         -1,
  39802     },
  39803 #endif /* chips */
  39804 
  39805 #if defined(BCM_88790_A0)
  39806     { /* SOC_REG_INT_QSPI_MSPI_TXRAM27_BCM88790_A0r */
  39807         soc_block_list[61],
  39808         soc_iprocreg,
  39809         1,
  39810         0,
  39811         0x180212ac,
  39812         0,
  39813         0,
  39814         2,
  39815         soc_QSPI_MSPI_TXRAM27_BCM88790_A0r_fields,
  39816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39817         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39818         -1,
  39819         -1,
  39820     },
  39821 #endif /* chips */
  39822 
  39823 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  39824     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  39825     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  39826     defined(BCM_56260_B0)
  39827     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM53400_A0r */
  39828         soc_block_list[61],
  39829         soc_iprocreg,
  39830         1,
  39831         0,
  39832         0x180472b0,
  39833         0,
  39834         0,
  39835         2,
  39836         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39838         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39839         -1,
  39840         -1,
  39841     },
  39842 #endif /* chips */
  39843 
  39844 #if defined(BCM_56370_A0)
  39845     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM56370_A0r */
  39846         soc_block_list[61],
  39847         soc_iprocreg,
  39848         1,
  39849         0,
  39850         0x150002b0,
  39851         0,
  39852         0,
  39853         2,
  39854         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39856         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39857         -1,
  39858         -1,
  39859         3,
  39860     },
  39861 #endif /* chips */
  39862 
  39863 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  39864     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  39865     defined(BCM_56450_B1)
  39866     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM56450_A0r */
  39867         soc_block_list[61],
  39868         soc_iprocreg,
  39869         1,
  39870         0,
  39871         0x180272b0,
  39872         0,
  39873         0,
  39874         2,
  39875         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  39876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39878         -1,
  39879         -1,
  39880     },
  39881 #endif /* chips */
  39882 
  39883 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  39884     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  39885     defined(BCM_56670_B0)
  39886     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM56560_A0r */
  39887         soc_block_list[61],
  39888         soc_iprocreg,
  39889         1,
  39890         0,
  39891         0x180212b0,
  39892         0,
  39893         0,
  39894         2,
  39895         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39898         -1,
  39899         -1,
  39900     },
  39901 #endif /* chips */
  39902 
  39903 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  39904     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  39905     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  39906     defined(BCM_56980_B0)
  39907     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM56960_A0r */
  39908         soc_block_list[61],
  39909         soc_iprocreg,
  39910         1,
  39911         0,
  39912         0x180212b0,
  39913         0,
  39914         0,
  39915         2,
  39916         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  39917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39918         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39919         -1,
  39920         -1,
  39921         3,
  39922     },
  39923 #endif /* chips */
  39924 
  39925 #if defined(BCM_88270_A0)
  39926     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM88270_A0r */
  39927         soc_block_list[61],
  39928         soc_iprocreg,
  39929         1,
  39930         0,
  39931         0x180212b0,
  39932         0,
  39933         0,
  39934         2,
  39935         soc_QSPI_MSPI_TXRAM28_BCM88270_A0r_fields,
  39936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39937         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39938         -1,
  39939         -1,
  39940     },
  39941 #endif /* chips */
  39942 
  39943 #if defined(BCM_88375_A0)
  39944     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM88375_A0r */
  39945         soc_block_list[61],
  39946         soc_iprocreg,
  39947         1,
  39948         0,
  39949         0x180212b0,
  39950         0,
  39951         0,
  39952         2,
  39953         soc_QSPI_MSPI_TXRAM28_BCM88375_A0r_fields,
  39954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39956         -1,
  39957         -1,
  39958     },
  39959 #endif /* chips */
  39960 
  39961 #if defined(BCM_88375_B0)
  39962     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM88375_B0r */
  39963         soc_block_list[61],
  39964         soc_iprocreg,
  39965         1,
  39966         0,
  39967         0x180212b0,
  39968         0,
  39969         0,
  39970         2,
  39971         soc_QSPI_MSPI_TXRAM28_BCM88375_B0r_fields,
  39972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39973         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39974         -1,
  39975         -1,
  39976     },
  39977 #endif /* chips */
  39978 
  39979 #if defined(BCM_88470_A0)
  39980     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM88470_A0r */
  39981         soc_block_list[61],
  39982         soc_iprocreg,
  39983         1,
  39984         0,
  39985         0x180212b0,
  39986         0,
  39987         0,
  39988         2,
  39989         soc_QSPI_MSPI_TXRAM28_BCM88470_A0r_fields,
  39990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39991         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39992         -1,
  39993         -1,
  39994     },
  39995 #endif /* chips */
  39996 
  39997 #if defined(BCM_88470_B0)
  39998     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM88470_B0r */
  39999         soc_block_list[61],
  40000         soc_iprocreg,
  40001         1,
  40002         0,
  40003         0x180212b0,
  40004         0,
  40005         0,
  40006         2,
  40007         soc_QSPI_MSPI_TXRAM28_BCM88470_B0r_fields,
  40008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40009         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40010         -1,
  40011         -1,
  40012     },
  40013 #endif /* chips */
  40014 
  40015 #if defined(BCM_88675_B0)
  40016     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM88675_B0r */
  40017         soc_block_list[61],
  40018         soc_iprocreg,
  40019         1,
  40020         0,
  40021         0x180212b0,
  40022         0,
  40023         0,
  40024         2,
  40025         soc_QSPI_MSPI_TXRAM28_BCM88675_B0r_fields,
  40026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40028         -1,
  40029         -1,
  40030     },
  40031 #endif /* chips */
  40032 
  40033 #if defined(BCM_88680_A0)
  40034     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM88680_A0r */
  40035         soc_block_list[61],
  40036         soc_iprocreg,
  40037         1,
  40038         0,
  40039         0x180212b0,
  40040         0,
  40041         0,
  40042         2,
  40043         soc_QSPI_MSPI_TXRAM28_BCM88680_A0r_fields,
  40044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40045         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40046         -1,
  40047         -1,
  40048     },
  40049 #endif /* chips */
  40050 
  40051 #if defined(BCM_88690_A0)
  40052     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM88690_A0r */
  40053         soc_block_list[61],
  40054         soc_iprocreg,
  40055         1,
  40056         0,
  40057         0x180212b0,
  40058         0,
  40059         0,
  40060         2,
  40061         soc_QSPI_MSPI_TXRAM28_BCM88690_A0r_fields,
  40062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40063         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40064         -1,
  40065         -1,
  40066     },
  40067 #endif /* chips */
  40068 
  40069 #if defined(BCM_88690_B0)
  40070     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM88690_B0r */
  40071         soc_block_list[61],
  40072         soc_iprocreg,
  40073         1,
  40074         0,
  40075         0x180212b0,
  40076         0,
  40077         0,
  40078         2,
  40079         soc_QSPI_MSPI_TXRAM28_BCM88690_B0r_fields,
  40080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40081         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40082         -1,
  40083         -1,
  40084     },
  40085 #endif /* chips */
  40086 
  40087 #if defined(BCM_88790_A0)
  40088     { /* SOC_REG_INT_QSPI_MSPI_TXRAM28_BCM88790_A0r */
  40089         soc_block_list[61],
  40090         soc_iprocreg,
  40091         1,
  40092         0,
  40093         0x180212b0,
  40094         0,
  40095         0,
  40096         2,
  40097         soc_QSPI_MSPI_TXRAM28_BCM88790_A0r_fields,
  40098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40099         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40100         -1,
  40101         -1,
  40102     },
  40103 #endif /* chips */
  40104 
  40105 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  40106     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  40107     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  40108     defined(BCM_56260_B0)
  40109     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM53400_A0r */
  40110         soc_block_list[61],
  40111         soc_iprocreg,
  40112         1,
  40113         0,
  40114         0x180472b4,
  40115         0,
  40116         0,
  40117         2,
  40118         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40120         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40121         -1,
  40122         -1,
  40123     },
  40124 #endif /* chips */
  40125 
  40126 #if defined(BCM_56370_A0)
  40127     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM56370_A0r */
  40128         soc_block_list[61],
  40129         soc_iprocreg,
  40130         1,
  40131         0,
  40132         0x150002b4,
  40133         0,
  40134         0,
  40135         2,
  40136         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40138         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40139         -1,
  40140         -1,
  40141         3,
  40142     },
  40143 #endif /* chips */
  40144 
  40145 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  40146     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  40147     defined(BCM_56450_B1)
  40148     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM56450_A0r */
  40149         soc_block_list[61],
  40150         soc_iprocreg,
  40151         1,
  40152         0,
  40153         0x180272b4,
  40154         0,
  40155         0,
  40156         2,
  40157         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  40158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40159         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40160         -1,
  40161         -1,
  40162     },
  40163 #endif /* chips */
  40164 
  40165 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  40166     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  40167     defined(BCM_56670_B0)
  40168     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM56560_A0r */
  40169         soc_block_list[61],
  40170         soc_iprocreg,
  40171         1,
  40172         0,
  40173         0x180212b4,
  40174         0,
  40175         0,
  40176         2,
  40177         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40179         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40180         -1,
  40181         -1,
  40182     },
  40183 #endif /* chips */
  40184 
  40185 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  40186     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  40187     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  40188     defined(BCM_56980_B0)
  40189     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM56960_A0r */
  40190         soc_block_list[61],
  40191         soc_iprocreg,
  40192         1,
  40193         0,
  40194         0x180212b4,
  40195         0,
  40196         0,
  40197         2,
  40198         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40200         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40201         -1,
  40202         -1,
  40203         3,
  40204     },
  40205 #endif /* chips */
  40206 
  40207 #if defined(BCM_88270_A0)
  40208     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM88270_A0r */
  40209         soc_block_list[61],
  40210         soc_iprocreg,
  40211         1,
  40212         0,
  40213         0x180212b4,
  40214         0,
  40215         0,
  40216         2,
  40217         soc_QSPI_MSPI_TXRAM29_BCM88270_A0r_fields,
  40218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40219         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40220         -1,
  40221         -1,
  40222     },
  40223 #endif /* chips */
  40224 
  40225 #if defined(BCM_88375_A0)
  40226     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM88375_A0r */
  40227         soc_block_list[61],
  40228         soc_iprocreg,
  40229         1,
  40230         0,
  40231         0x180212b4,
  40232         0,
  40233         0,
  40234         2,
  40235         soc_QSPI_MSPI_TXRAM29_BCM88375_A0r_fields,
  40236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40237         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40238         -1,
  40239         -1,
  40240     },
  40241 #endif /* chips */
  40242 
  40243 #if defined(BCM_88375_B0)
  40244     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM88375_B0r */
  40245         soc_block_list[61],
  40246         soc_iprocreg,
  40247         1,
  40248         0,
  40249         0x180212b4,
  40250         0,
  40251         0,
  40252         2,
  40253         soc_QSPI_MSPI_TXRAM29_BCM88375_B0r_fields,
  40254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40255         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40256         -1,
  40257         -1,
  40258     },
  40259 #endif /* chips */
  40260 
  40261 #if defined(BCM_88470_A0)
  40262     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM88470_A0r */
  40263         soc_block_list[61],
  40264         soc_iprocreg,
  40265         1,
  40266         0,
  40267         0x180212b4,
  40268         0,
  40269         0,
  40270         2,
  40271         soc_QSPI_MSPI_TXRAM29_BCM88470_A0r_fields,
  40272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40273         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40274         -1,
  40275         -1,
  40276     },
  40277 #endif /* chips */
  40278 
  40279 #if defined(BCM_88470_B0)
  40280     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM88470_B0r */
  40281         soc_block_list[61],
  40282         soc_iprocreg,
  40283         1,
  40284         0,
  40285         0x180212b4,
  40286         0,
  40287         0,
  40288         2,
  40289         soc_QSPI_MSPI_TXRAM29_BCM88470_B0r_fields,
  40290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40291         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40292         -1,
  40293         -1,
  40294     },
  40295 #endif /* chips */
  40296 
  40297 #if defined(BCM_88675_B0)
  40298     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM88675_B0r */
  40299         soc_block_list[61],
  40300         soc_iprocreg,
  40301         1,
  40302         0,
  40303         0x180212b4,
  40304         0,
  40305         0,
  40306         2,
  40307         soc_QSPI_MSPI_TXRAM29_BCM88675_B0r_fields,
  40308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40309         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40310         -1,
  40311         -1,
  40312     },
  40313 #endif /* chips */
  40314 
  40315 #if defined(BCM_88680_A0)
  40316     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM88680_A0r */
  40317         soc_block_list[61],
  40318         soc_iprocreg,
  40319         1,
  40320         0,
  40321         0x180212b4,
  40322         0,
  40323         0,
  40324         2,
  40325         soc_QSPI_MSPI_TXRAM29_BCM88680_A0r_fields,
  40326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40327         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40328         -1,
  40329         -1,
  40330     },
  40331 #endif /* chips */
  40332 
  40333 #if defined(BCM_88690_A0)
  40334     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM88690_A0r */
  40335         soc_block_list[61],
  40336         soc_iprocreg,
  40337         1,
  40338         0,
  40339         0x180212b4,
  40340         0,
  40341         0,
  40342         2,
  40343         soc_QSPI_MSPI_TXRAM29_BCM88690_A0r_fields,
  40344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40346         -1,
  40347         -1,
  40348     },
  40349 #endif /* chips */
  40350 
  40351 #if defined(BCM_88690_B0)
  40352     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM88690_B0r */
  40353         soc_block_list[61],
  40354         soc_iprocreg,
  40355         1,
  40356         0,
  40357         0x180212b4,
  40358         0,
  40359         0,
  40360         2,
  40361         soc_QSPI_MSPI_TXRAM29_BCM88690_B0r_fields,
  40362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40363         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40364         -1,
  40365         -1,
  40366     },
  40367 #endif /* chips */
  40368 
  40369 #if defined(BCM_88790_A0)
  40370     { /* SOC_REG_INT_QSPI_MSPI_TXRAM29_BCM88790_A0r */
  40371         soc_block_list[61],
  40372         soc_iprocreg,
  40373         1,
  40374         0,
  40375         0x180212b4,
  40376         0,
  40377         0,
  40378         2,
  40379         soc_QSPI_MSPI_TXRAM29_BCM88790_A0r_fields,
  40380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40382         -1,
  40383         -1,
  40384     },
  40385 #endif /* chips */
  40386 
  40387 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  40388     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  40389     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  40390     defined(BCM_56260_B0)
  40391     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM53400_A0r */
  40392         soc_block_list[61],
  40393         soc_iprocreg,
  40394         1,
  40395         0,
  40396         0x180472b8,
  40397         0,
  40398         0,
  40399         2,
  40400         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40402         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40403         -1,
  40404         -1,
  40405     },
  40406 #endif /* chips */
  40407 
  40408 #if defined(BCM_56370_A0)
  40409     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM56370_A0r */
  40410         soc_block_list[61],
  40411         soc_iprocreg,
  40412         1,
  40413         0,
  40414         0x150002b8,
  40415         0,
  40416         0,
  40417         2,
  40418         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40420         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40421         -1,
  40422         -1,
  40423         3,
  40424     },
  40425 #endif /* chips */
  40426 
  40427 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  40428     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  40429     defined(BCM_56450_B1)
  40430     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM56450_A0r */
  40431         soc_block_list[61],
  40432         soc_iprocreg,
  40433         1,
  40434         0,
  40435         0x180272b8,
  40436         0,
  40437         0,
  40438         2,
  40439         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  40440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40441         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40442         -1,
  40443         -1,
  40444     },
  40445 #endif /* chips */
  40446 
  40447 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  40448     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  40449     defined(BCM_56670_B0)
  40450     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM56560_A0r */
  40451         soc_block_list[61],
  40452         soc_iprocreg,
  40453         1,
  40454         0,
  40455         0x180212b8,
  40456         0,
  40457         0,
  40458         2,
  40459         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40462         -1,
  40463         -1,
  40464     },
  40465 #endif /* chips */
  40466 
  40467 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  40468     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  40469     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  40470     defined(BCM_56980_B0)
  40471     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM56960_A0r */
  40472         soc_block_list[61],
  40473         soc_iprocreg,
  40474         1,
  40475         0,
  40476         0x180212b8,
  40477         0,
  40478         0,
  40479         2,
  40480         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40482         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40483         -1,
  40484         -1,
  40485         3,
  40486     },
  40487 #endif /* chips */
  40488 
  40489 #if defined(BCM_88270_A0)
  40490     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM88270_A0r */
  40491         soc_block_list[61],
  40492         soc_iprocreg,
  40493         1,
  40494         0,
  40495         0x180212b8,
  40496         0,
  40497         0,
  40498         2,
  40499         soc_QSPI_MSPI_TXRAM30_BCM88270_A0r_fields,
  40500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40501         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40502         -1,
  40503         -1,
  40504     },
  40505 #endif /* chips */
  40506 
  40507 #if defined(BCM_88375_A0)
  40508     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM88375_A0r */
  40509         soc_block_list[61],
  40510         soc_iprocreg,
  40511         1,
  40512         0,
  40513         0x180212b8,
  40514         0,
  40515         0,
  40516         2,
  40517         soc_QSPI_MSPI_TXRAM30_BCM88375_A0r_fields,
  40518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40519         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40520         -1,
  40521         -1,
  40522     },
  40523 #endif /* chips */
  40524 
  40525 #if defined(BCM_88375_B0)
  40526     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM88375_B0r */
  40527         soc_block_list[61],
  40528         soc_iprocreg,
  40529         1,
  40530         0,
  40531         0x180212b8,
  40532         0,
  40533         0,
  40534         2,
  40535         soc_QSPI_MSPI_TXRAM30_BCM88375_B0r_fields,
  40536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40537         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40538         -1,
  40539         -1,
  40540     },
  40541 #endif /* chips */
  40542 
  40543 #if defined(BCM_88470_A0)
  40544     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM88470_A0r */
  40545         soc_block_list[61],
  40546         soc_iprocreg,
  40547         1,
  40548         0,
  40549         0x180212b8,
  40550         0,
  40551         0,
  40552         2,
  40553         soc_QSPI_MSPI_TXRAM30_BCM88470_A0r_fields,
  40554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40555         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40556         -1,
  40557         -1,
  40558     },
  40559 #endif /* chips */
  40560 
  40561 #if defined(BCM_88470_B0)
  40562     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM88470_B0r */
  40563         soc_block_list[61],
  40564         soc_iprocreg,
  40565         1,
  40566         0,
  40567         0x180212b8,
  40568         0,
  40569         0,
  40570         2,
  40571         soc_QSPI_MSPI_TXRAM30_BCM88470_B0r_fields,
  40572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40573         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40574         -1,
  40575         -1,
  40576     },
  40577 #endif /* chips */
  40578 
  40579 #if defined(BCM_88675_B0)
  40580     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM88675_B0r */
  40581         soc_block_list[61],
  40582         soc_iprocreg,
  40583         1,
  40584         0,
  40585         0x180212b8,
  40586         0,
  40587         0,
  40588         2,
  40589         soc_QSPI_MSPI_TXRAM30_BCM88675_B0r_fields,
  40590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40591         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40592         -1,
  40593         -1,
  40594     },
  40595 #endif /* chips */
  40596 
  40597 #if defined(BCM_88680_A0)
  40598     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM88680_A0r */
  40599         soc_block_list[61],
  40600         soc_iprocreg,
  40601         1,
  40602         0,
  40603         0x180212b8,
  40604         0,
  40605         0,
  40606         2,
  40607         soc_QSPI_MSPI_TXRAM30_BCM88680_A0r_fields,
  40608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40609         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40610         -1,
  40611         -1,
  40612     },
  40613 #endif /* chips */
  40614 
  40615 #if defined(BCM_88690_A0)
  40616     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM88690_A0r */
  40617         soc_block_list[61],
  40618         soc_iprocreg,
  40619         1,
  40620         0,
  40621         0x180212b8,
  40622         0,
  40623         0,
  40624         2,
  40625         soc_QSPI_MSPI_TXRAM30_BCM88690_A0r_fields,
  40626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40627         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40628         -1,
  40629         -1,
  40630     },
  40631 #endif /* chips */
  40632 
  40633 #if defined(BCM_88690_B0)
  40634     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM88690_B0r */
  40635         soc_block_list[61],
  40636         soc_iprocreg,
  40637         1,
  40638         0,
  40639         0x180212b8,
  40640         0,
  40641         0,
  40642         2,
  40643         soc_QSPI_MSPI_TXRAM30_BCM88690_B0r_fields,
  40644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40646         -1,
  40647         -1,
  40648     },
  40649 #endif /* chips */
  40650 
  40651 #if defined(BCM_88790_A0)
  40652     { /* SOC_REG_INT_QSPI_MSPI_TXRAM30_BCM88790_A0r */
  40653         soc_block_list[61],
  40654         soc_iprocreg,
  40655         1,
  40656         0,
  40657         0x180212b8,
  40658         0,
  40659         0,
  40660         2,
  40661         soc_QSPI_MSPI_TXRAM30_BCM88790_A0r_fields,
  40662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40663         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40664         -1,
  40665         -1,
  40666     },
  40667 #endif /* chips */
  40668 
  40669 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  40670     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  40671     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  40672     defined(BCM_56260_B0)
  40673     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM53400_A0r */
  40674         soc_block_list[61],
  40675         soc_iprocreg,
  40676         1,
  40677         0,
  40678         0x180472bc,
  40679         0,
  40680         0,
  40681         2,
  40682         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40685         -1,
  40686         -1,
  40687     },
  40688 #endif /* chips */
  40689 
  40690 #if defined(BCM_56370_A0)
  40691     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM56370_A0r */
  40692         soc_block_list[61],
  40693         soc_iprocreg,
  40694         1,
  40695         0,
  40696         0x150002bc,
  40697         0,
  40698         0,
  40699         2,
  40700         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40703         -1,
  40704         -1,
  40705         3,
  40706     },
  40707 #endif /* chips */
  40708 
  40709 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  40710     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  40711     defined(BCM_56450_B1)
  40712     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM56450_A0r */
  40713         soc_block_list[61],
  40714         soc_iprocreg,
  40715         1,
  40716         0,
  40717         0x180272bc,
  40718         0,
  40719         0,
  40720         2,
  40721         soc_QSPI_MSPI_TXRAM00_BCM56450_A0r_fields,
  40722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40723         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40724         -1,
  40725         -1,
  40726     },
  40727 #endif /* chips */
  40728 
  40729 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  40730     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  40731     defined(BCM_56670_B0)
  40732     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM56560_A0r */
  40733         soc_block_list[61],
  40734         soc_iprocreg,
  40735         1,
  40736         0,
  40737         0x180212bc,
  40738         0,
  40739         0,
  40740         2,
  40741         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40744         -1,
  40745         -1,
  40746     },
  40747 #endif /* chips */
  40748 
  40749 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  40750     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  40751     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  40752     defined(BCM_56980_B0)
  40753     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM56960_A0r */
  40754         soc_block_list[61],
  40755         soc_iprocreg,
  40756         1,
  40757         0,
  40758         0x180212bc,
  40759         0,
  40760         0,
  40761         2,
  40762         soc_QSPI_MSPI_TXRAM00_BCM53400_A0r_fields,
  40763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40764         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40765         -1,
  40766         -1,
  40767         3,
  40768     },
  40769 #endif /* chips */
  40770 
  40771 #if defined(BCM_88270_A0)
  40772     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM88270_A0r */
  40773         soc_block_list[61],
  40774         soc_iprocreg,
  40775         1,
  40776         0,
  40777         0x180212bc,
  40778         0,
  40779         0,
  40780         2,
  40781         soc_QSPI_MSPI_TXRAM31_BCM88270_A0r_fields,
  40782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40783         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40784         -1,
  40785         -1,
  40786     },
  40787 #endif /* chips */
  40788 
  40789 #if defined(BCM_88375_A0)
  40790     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM88375_A0r */
  40791         soc_block_list[61],
  40792         soc_iprocreg,
  40793         1,
  40794         0,
  40795         0x180212bc,
  40796         0,
  40797         0,
  40798         2,
  40799         soc_QSPI_MSPI_TXRAM31_BCM88375_A0r_fields,
  40800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40801         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40802         -1,
  40803         -1,
  40804     },
  40805 #endif /* chips */
  40806 
  40807 #if defined(BCM_88375_B0)
  40808     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM88375_B0r */
  40809         soc_block_list[61],
  40810         soc_iprocreg,
  40811         1,
  40812         0,
  40813         0x180212bc,
  40814         0,
  40815         0,
  40816         2,
  40817         soc_QSPI_MSPI_TXRAM31_BCM88375_B0r_fields,
  40818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40819         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40820         -1,
  40821         -1,
  40822     },
  40823 #endif /* chips */
  40824 
  40825 #if defined(BCM_88470_A0)
  40826     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM88470_A0r */
  40827         soc_block_list[61],
  40828         soc_iprocreg,
  40829         1,
  40830         0,
  40831         0x180212bc,
  40832         0,
  40833         0,
  40834         2,
  40835         soc_QSPI_MSPI_TXRAM31_BCM88470_A0r_fields,
  40836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40837         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40838         -1,
  40839         -1,
  40840     },
  40841 #endif /* chips */
  40842 
  40843 #if defined(BCM_88470_B0)
  40844     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM88470_B0r */
  40845         soc_block_list[61],
  40846         soc_iprocreg,
  40847         1,
  40848         0,
  40849         0x180212bc,
  40850         0,
  40851         0,
  40852         2,
  40853         soc_QSPI_MSPI_TXRAM31_BCM88470_B0r_fields,
  40854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40855         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40856         -1,
  40857         -1,
  40858     },
  40859 #endif /* chips */
  40860 
  40861 #if defined(BCM_88675_B0)
  40862     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM88675_B0r */
  40863         soc_block_list[61],
  40864         soc_iprocreg,
  40865         1,
  40866         0,
  40867         0x180212bc,
  40868         0,
  40869         0,
  40870         2,
  40871         soc_QSPI_MSPI_TXRAM31_BCM88675_B0r_fields,
  40872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40873         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40874         -1,
  40875         -1,
  40876     },
  40877 #endif /* chips */
  40878 
  40879 #if defined(BCM_88680_A0)
  40880     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM88680_A0r */
  40881         soc_block_list[61],
  40882         soc_iprocreg,
  40883         1,
  40884         0,
  40885         0x180212bc,
  40886         0,
  40887         0,
  40888         2,
  40889         soc_QSPI_MSPI_TXRAM31_BCM88680_A0r_fields,
  40890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40891         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40892         -1,
  40893         -1,
  40894     },
  40895 #endif /* chips */
  40896 
  40897 #if defined(BCM_88690_A0)
  40898     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM88690_A0r */
  40899         soc_block_list[61],
  40900         soc_iprocreg,
  40901         1,
  40902         0,
  40903         0x180212bc,
  40904         0,
  40905         0,
  40906         2,
  40907         soc_QSPI_MSPI_TXRAM31_BCM88690_A0r_fields,
  40908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40909         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40910         -1,
  40911         -1,
  40912     },
  40913 #endif /* chips */
  40914 
  40915 #if defined(BCM_88690_B0)
  40916     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM88690_B0r */
  40917         soc_block_list[61],
  40918         soc_iprocreg,
  40919         1,
  40920         0,
  40921         0x180212bc,
  40922         0,
  40923         0,
  40924         2,
  40925         soc_QSPI_MSPI_TXRAM31_BCM88690_B0r_fields,
  40926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40927         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40928         -1,
  40929         -1,
  40930     },
  40931 #endif /* chips */
  40932 
  40933 #if defined(BCM_88790_A0)
  40934     { /* SOC_REG_INT_QSPI_MSPI_TXRAM31_BCM88790_A0r */
  40935         soc_block_list[61],
  40936         soc_iprocreg,
  40937         1,
  40938         0,
  40939         0x180212bc,
  40940         0,
  40941         0,
  40942         2,
  40943         soc_QSPI_MSPI_TXRAM31_BCM88790_A0r_fields,
  40944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40946         -1,
  40947         -1,
  40948     },
  40949 #endif /* chips */
  40950 
  40951 #if defined(BCM_88675_A0)
  40952     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCKr */
  40953         soc_block_list[61],
  40954         soc_iprocreg,
  40955         1,
  40956         0,
  40957         0x18021380,
  40958         0,
  40959         0,
  40960         2,
  40961         soc_QSPI_MSPI_WRITE_LOCKr_fields,
  40962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40964         -1,
  40965         -1,
  40966     },
  40967 #endif /* chips */
  40968 
  40969 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  40970     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  40971     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  40972     defined(BCM_56260_B0)
  40973     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM53400_A0r */
  40974         soc_block_list[61],
  40975         soc_iprocreg,
  40976         1,
  40977         0,
  40978         0x18047380,
  40979         0,
  40980         0,
  40981         2,
  40982         soc_QSPI_MSPI_WRITE_LOCK_BCM53400_A0r_fields,
  40983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40984         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40985         -1,
  40986         -1,
  40987     },
  40988 #endif /* chips */
  40989 
  40990 #if defined(BCM_56370_A0)
  40991     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM56370_A0r */
  40992         soc_block_list[61],
  40993         soc_iprocreg,
  40994         1,
  40995         0,
  40996         0x15000380,
  40997         0,
  40998         0,
  40999         2,
  41000         soc_QSPI_MSPI_WRITE_LOCK_BCM53400_A0r_fields,
  41001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41002         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41003         -1,
  41004         -1,
  41005         3,
  41006     },
  41007 #endif /* chips */
  41008 
  41009 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  41010     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41011     defined(BCM_56450_B1)
  41012     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM56450_A0r */
  41013         soc_block_list[61],
  41014         soc_iprocreg,
  41015         1,
  41016         0,
  41017         0x18027380,
  41018         0,
  41019         0,
  41020         2,
  41021         soc_QSPI_MSPI_WRITE_LOCK_BCM56450_A0r_fields,
  41022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41023         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41024         -1,
  41025         -1,
  41026     },
  41027 #endif /* chips */
  41028 
  41029 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  41030     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  41031     defined(BCM_56670_B0)
  41032     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM56560_A0r */
  41033         soc_block_list[61],
  41034         soc_iprocreg,
  41035         1,
  41036         0,
  41037         0x18021380,
  41038         0,
  41039         0,
  41040         2,
  41041         soc_QSPI_MSPI_WRITE_LOCK_BCM53400_A0r_fields,
  41042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41043         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41044         -1,
  41045         -1,
  41046     },
  41047 #endif /* chips */
  41048 
  41049 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  41050     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  41051     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  41052     defined(BCM_56980_B0)
  41053     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM56960_A0r */
  41054         soc_block_list[61],
  41055         soc_iprocreg,
  41056         1,
  41057         0,
  41058         0x18021380,
  41059         0,
  41060         0,
  41061         2,
  41062         soc_QSPI_MSPI_WRITE_LOCK_BCM53400_A0r_fields,
  41063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41064         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41065         -1,
  41066         -1,
  41067         3,
  41068     },
  41069 #endif /* chips */
  41070 
  41071 #if defined(BCM_88270_A0)
  41072     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM88270_A0r */
  41073         soc_block_list[61],
  41074         soc_iprocreg,
  41075         1,
  41076         0,
  41077         0x18021380,
  41078         0,
  41079         0,
  41080         2,
  41081         soc_QSPI_MSPI_WRITE_LOCK_BCM88270_A0r_fields,
  41082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41083         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41084         -1,
  41085         -1,
  41086     },
  41087 #endif /* chips */
  41088 
  41089 #if defined(BCM_88375_A0)
  41090     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM88375_A0r */
  41091         soc_block_list[61],
  41092         soc_iprocreg,
  41093         1,
  41094         0,
  41095         0x18021380,
  41096         0,
  41097         0,
  41098         2,
  41099         soc_QSPI_MSPI_WRITE_LOCK_BCM88375_A0r_fields,
  41100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41101         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41102         -1,
  41103         -1,
  41104     },
  41105 #endif /* chips */
  41106 
  41107 #if defined(BCM_88375_B0)
  41108     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM88375_B0r */
  41109         soc_block_list[61],
  41110         soc_iprocreg,
  41111         1,
  41112         0,
  41113         0x18021380,
  41114         0,
  41115         0,
  41116         2,
  41117         soc_QSPI_MSPI_WRITE_LOCK_BCM88375_B0r_fields,
  41118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41119         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41120         -1,
  41121         -1,
  41122     },
  41123 #endif /* chips */
  41124 
  41125 #if defined(BCM_88470_A0)
  41126     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM88470_A0r */
  41127         soc_block_list[61],
  41128         soc_iprocreg,
  41129         1,
  41130         0,
  41131         0x18021380,
  41132         0,
  41133         0,
  41134         2,
  41135         soc_QSPI_MSPI_WRITE_LOCK_BCM88470_A0r_fields,
  41136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41137         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41138         -1,
  41139         -1,
  41140     },
  41141 #endif /* chips */
  41142 
  41143 #if defined(BCM_88470_B0)
  41144     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM88470_B0r */
  41145         soc_block_list[61],
  41146         soc_iprocreg,
  41147         1,
  41148         0,
  41149         0x18021380,
  41150         0,
  41151         0,
  41152         2,
  41153         soc_QSPI_MSPI_WRITE_LOCK_BCM88470_B0r_fields,
  41154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41155         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41156         -1,
  41157         -1,
  41158     },
  41159 #endif /* chips */
  41160 
  41161 #if defined(BCM_88675_B0)
  41162     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM88675_B0r */
  41163         soc_block_list[61],
  41164         soc_iprocreg,
  41165         1,
  41166         0,
  41167         0x18021380,
  41168         0,
  41169         0,
  41170         2,
  41171         soc_QSPI_MSPI_WRITE_LOCK_BCM88675_B0r_fields,
  41172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41173         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41174         -1,
  41175         -1,
  41176     },
  41177 #endif /* chips */
  41178 
  41179 #if defined(BCM_88680_A0)
  41180     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM88680_A0r */
  41181         soc_block_list[61],
  41182         soc_iprocreg,
  41183         1,
  41184         0,
  41185         0x18021380,
  41186         0,
  41187         0,
  41188         2,
  41189         soc_QSPI_MSPI_WRITE_LOCK_BCM88680_A0r_fields,
  41190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41191         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41192         -1,
  41193         -1,
  41194     },
  41195 #endif /* chips */
  41196 
  41197 #if defined(BCM_88690_A0)
  41198     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM88690_A0r */
  41199         soc_block_list[61],
  41200         soc_iprocreg,
  41201         1,
  41202         0,
  41203         0x18021380,
  41204         0,
  41205         0,
  41206         2,
  41207         soc_QSPI_MSPI_WRITE_LOCK_BCM88690_A0r_fields,
  41208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41209         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41210         -1,
  41211         -1,
  41212     },
  41213 #endif /* chips */
  41214 
  41215 #if defined(BCM_88690_B0)
  41216     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM88690_B0r */
  41217         soc_block_list[61],
  41218         soc_iprocreg,
  41219         1,
  41220         0,
  41221         0x18021380,
  41222         0,
  41223         0,
  41224         2,
  41225         soc_QSPI_MSPI_WRITE_LOCK_BCM88690_B0r_fields,
  41226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41227         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41228         -1,
  41229         -1,
  41230     },
  41231 #endif /* chips */
  41232 
  41233 #if defined(BCM_88790_A0)
  41234     { /* SOC_REG_INT_QSPI_MSPI_WRITE_LOCK_BCM88790_A0r */
  41235         soc_block_list[61],
  41236         soc_iprocreg,
  41237         1,
  41238         0,
  41239         0x18021380,
  41240         0,
  41241         0,
  41242         2,
  41243         soc_QSPI_MSPI_WRITE_LOCK_BCM88790_A0r_fields,
  41244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41246         -1,
  41247         -1,
  41248     },
  41249 #endif /* chips */
  41250 
  41251 #if defined(BCM_88675_A0)
  41252     { /* SOC_REG_INT_QSPI_RAF_CTRLr */
  41253         soc_block_list[61],
  41254         soc_iprocreg,
  41255         1,
  41256         0,
  41257         0x18021108,
  41258         0,
  41259         0,
  41260         3,
  41261         soc_QSPI_RAF_CTRLr_fields,
  41262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41264         -1,
  41265         -1,
  41266     },
  41267 #endif /* chips */
  41268 
  41269 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  41270     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  41271     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  41272     defined(BCM_56260_B0)
  41273     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM53400_A0r */
  41274         soc_block_list[61],
  41275         soc_iprocreg,
  41276         1,
  41277         0,
  41278         0x18047108,
  41279         0,
  41280         0,
  41281         3,
  41282         soc_QSPI_RAF_CTRL_BCM53400_A0r_fields,
  41283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41284         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41285         -1,
  41286         -1,
  41287     },
  41288 #endif /* chips */
  41289 
  41290 #if defined(BCM_56370_A0)
  41291     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM56370_A0r */
  41292         soc_block_list[61],
  41293         soc_iprocreg,
  41294         1,
  41295         0,
  41296         0x15000108,
  41297         0,
  41298         0,
  41299         3,
  41300         soc_QSPI_RAF_CTRL_BCM53400_A0r_fields,
  41301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41302         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41303         -1,
  41304         -1,
  41305         3,
  41306     },
  41307 #endif /* chips */
  41308 
  41309 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  41310     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41311     defined(BCM_56450_B1)
  41312     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM56450_A0r */
  41313         soc_block_list[61],
  41314         soc_iprocreg,
  41315         1,
  41316         0,
  41317         0x18027108,
  41318         0,
  41319         0,
  41320         3,
  41321         soc_QSPI_RAF_CTRL_BCM56450_A0r_fields,
  41322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41323         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41324         -1,
  41325         -1,
  41326     },
  41327 #endif /* chips */
  41328 
  41329 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  41330     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  41331     defined(BCM_56670_B0)
  41332     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM56560_A0r */
  41333         soc_block_list[61],
  41334         soc_iprocreg,
  41335         1,
  41336         0,
  41337         0x18021108,
  41338         0,
  41339         0,
  41340         3,
  41341         soc_QSPI_RAF_CTRL_BCM53400_A0r_fields,
  41342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41343         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41344         -1,
  41345         -1,
  41346     },
  41347 #endif /* chips */
  41348 
  41349 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  41350     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  41351     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  41352     defined(BCM_56980_B0)
  41353     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM56960_A0r */
  41354         soc_block_list[61],
  41355         soc_iprocreg,
  41356         1,
  41357         0,
  41358         0x18021108,
  41359         0,
  41360         0,
  41361         3,
  41362         soc_QSPI_RAF_CTRL_BCM53400_A0r_fields,
  41363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41364         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41365         -1,
  41366         -1,
  41367         3,
  41368     },
  41369 #endif /* chips */
  41370 
  41371 #if defined(BCM_88270_A0)
  41372     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM88270_A0r */
  41373         soc_block_list[61],
  41374         soc_iprocreg,
  41375         1,
  41376         0,
  41377         0x18021108,
  41378         0,
  41379         0,
  41380         3,
  41381         soc_QSPI_RAF_CTRL_BCM88270_A0r_fields,
  41382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41383         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41384         -1,
  41385         -1,
  41386     },
  41387 #endif /* chips */
  41388 
  41389 #if defined(BCM_88375_A0)
  41390     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM88375_A0r */
  41391         soc_block_list[61],
  41392         soc_iprocreg,
  41393         1,
  41394         0,
  41395         0x18021108,
  41396         0,
  41397         0,
  41398         3,
  41399         soc_QSPI_RAF_CTRL_BCM88375_A0r_fields,
  41400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41401         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41402         -1,
  41403         -1,
  41404     },
  41405 #endif /* chips */
  41406 
  41407 #if defined(BCM_88375_B0)
  41408     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM88375_B0r */
  41409         soc_block_list[61],
  41410         soc_iprocreg,
  41411         1,
  41412         0,
  41413         0x18021108,
  41414         0,
  41415         0,
  41416         3,
  41417         soc_QSPI_RAF_CTRL_BCM88375_B0r_fields,
  41418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41420         -1,
  41421         -1,
  41422     },
  41423 #endif /* chips */
  41424 
  41425 #if defined(BCM_88470_A0)
  41426     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM88470_A0r */
  41427         soc_block_list[61],
  41428         soc_iprocreg,
  41429         1,
  41430         0,
  41431         0x18021108,
  41432         0,
  41433         0,
  41434         3,
  41435         soc_QSPI_RAF_CTRL_BCM88470_A0r_fields,
  41436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41437         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41438         -1,
  41439         -1,
  41440     },
  41441 #endif /* chips */
  41442 
  41443 #if defined(BCM_88470_B0)
  41444     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM88470_B0r */
  41445         soc_block_list[61],
  41446         soc_iprocreg,
  41447         1,
  41448         0,
  41449         0x18021108,
  41450         0,
  41451         0,
  41452         3,
  41453         soc_QSPI_RAF_CTRL_BCM88470_B0r_fields,
  41454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41455         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41456         -1,
  41457         -1,
  41458     },
  41459 #endif /* chips */
  41460 
  41461 #if defined(BCM_88675_B0)
  41462     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM88675_B0r */
  41463         soc_block_list[61],
  41464         soc_iprocreg,
  41465         1,
  41466         0,
  41467         0x18021108,
  41468         0,
  41469         0,
  41470         3,
  41471         soc_QSPI_RAF_CTRL_BCM88675_B0r_fields,
  41472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41473         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41474         -1,
  41475         -1,
  41476     },
  41477 #endif /* chips */
  41478 
  41479 #if defined(BCM_88680_A0)
  41480     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM88680_A0r */
  41481         soc_block_list[61],
  41482         soc_iprocreg,
  41483         1,
  41484         0,
  41485         0x18021108,
  41486         0,
  41487         0,
  41488         3,
  41489         soc_QSPI_RAF_CTRL_BCM88680_A0r_fields,
  41490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41491         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41492         -1,
  41493         -1,
  41494     },
  41495 #endif /* chips */
  41496 
  41497 #if defined(BCM_88690_A0)
  41498     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM88690_A0r */
  41499         soc_block_list[61],
  41500         soc_iprocreg,
  41501         1,
  41502         0,
  41503         0x18021108,
  41504         0,
  41505         0,
  41506         3,
  41507         soc_QSPI_RAF_CTRL_BCM88690_A0r_fields,
  41508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41509         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41510         -1,
  41511         -1,
  41512     },
  41513 #endif /* chips */
  41514 
  41515 #if defined(BCM_88690_B0)
  41516     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM88690_B0r */
  41517         soc_block_list[61],
  41518         soc_iprocreg,
  41519         1,
  41520         0,
  41521         0x18021108,
  41522         0,
  41523         0,
  41524         3,
  41525         soc_QSPI_RAF_CTRL_BCM88690_B0r_fields,
  41526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41527         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41528         -1,
  41529         -1,
  41530     },
  41531 #endif /* chips */
  41532 
  41533 #if defined(BCM_88790_A0)
  41534     { /* SOC_REG_INT_QSPI_RAF_CTRL_BCM88790_A0r */
  41535         soc_block_list[61],
  41536         soc_iprocreg,
  41537         1,
  41538         0,
  41539         0x18021108,
  41540         0,
  41541         0,
  41542         3,
  41543         soc_QSPI_RAF_CTRL_BCM88790_A0r_fields,
  41544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41545         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41546         -1,
  41547         -1,
  41548     },
  41549 #endif /* chips */
  41550 
  41551 #if defined(BCM_88675_A0)
  41552     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDRr */
  41553         soc_block_list[61],
  41554         soc_iprocreg,
  41555         1,
  41556         0,
  41557         0x18021120,
  41558         SOC_REG_FLAG_RO,
  41559         0,
  41560         1,
  41561         soc_QSPI_RAF_CURR_ADDRr_fields,
  41562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41563         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41564         -1,
  41565         -1,
  41566     },
  41567 #endif /* chips */
  41568 
  41569 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  41570     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  41571     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  41572     defined(BCM_56260_B0)
  41573     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM53400_A0r */
  41574         soc_block_list[61],
  41575         soc_iprocreg,
  41576         1,
  41577         0,
  41578         0x18047120,
  41579         SOC_REG_FLAG_RO,
  41580         0,
  41581         1,
  41582         soc_QSPI_RAF_CURR_ADDR_BCM53400_A0r_fields,
  41583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41584         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41585         -1,
  41586         -1,
  41587     },
  41588 #endif /* chips */
  41589 
  41590 #if defined(BCM_56370_A0)
  41591     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM56370_A0r */
  41592         soc_block_list[61],
  41593         soc_iprocreg,
  41594         1,
  41595         0,
  41596         0x15000120,
  41597         SOC_REG_FLAG_RO,
  41598         0,
  41599         1,
  41600         soc_QSPI_RAF_CURR_ADDR_BCM53400_A0r_fields,
  41601         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41602         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41603         -1,
  41604         -1,
  41605         3,
  41606     },
  41607 #endif /* chips */
  41608 
  41609 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  41610     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  41611     defined(BCM_56450_B1)
  41612     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM56450_A0r */
  41613         soc_block_list[61],
  41614         soc_iprocreg,
  41615         1,
  41616         0,
  41617         0x18027120,
  41618         SOC_REG_FLAG_RO,
  41619         0,
  41620         1,
  41621         soc_QSPI_RAF_CURR_ADDR_BCM56450_A0r_fields,
  41622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41623         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41624         -1,
  41625         -1,
  41626     },
  41627 #endif /* chips */
  41628 
  41629 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  41630     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  41631     defined(BCM_56670_B0)
  41632     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM56560_A0r */
  41633         soc_block_list[61],
  41634         soc_iprocreg,
  41635         1,
  41636         0,
  41637         0x18021120,
  41638         SOC_REG_FLAG_RO,
  41639         0,
  41640         1,
  41641         soc_QSPI_RAF_CURR_ADDR_BCM53400_A0r_fields,
  41642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41643         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41644         -1,
  41645         -1,
  41646     },
  41647 #endif /* chips */
  41648 
  41649 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  41650     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  41651     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  41652     defined(BCM_56980_B0)
  41653     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM56960_A0r */
  41654         soc_block_list[61],
  41655         soc_iprocreg,
  41656         1,
  41657         0,
  41658         0x18021120,
  41659         SOC_REG_FLAG_RO,
  41660         0,
  41661         1,
  41662         soc_QSPI_RAF_CURR_ADDR_BCM53400_A0r_fields,
  41663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41664         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41665         -1,
  41666         -1,
  41667         3,
  41668     },
  41669 #endif /* chips */
  41670 
  41671 #if defined(BCM_88270_A0)
  41672     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM88270_A0r */
  41673         soc_block_list[61],
  41674         soc_iprocreg,
  41675         1,
  41676         0,
  41677         0x18021120,
  41678         SOC_REG_FLAG_RO,
  41679         0,
  41680         1,
  41681         soc_QSPI_RAF_CURR_ADDR_BCM88270_A0r_fields,
  41682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41683         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41684         -1,
  41685         -1,
  41686     },
  41687 #endif /* chips */
  41688 
  41689 #if defined(BCM_88375_A0)
  41690     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM88375_A0r */
  41691         soc_block_list[61],
  41692         soc_iprocreg,
  41693         1,
  41694         0,
  41695         0x18021120,
  41696         SOC_REG_FLAG_RO,
  41697         0,
  41698         1,
  41699         soc_QSPI_RAF_CURR_ADDR_BCM88375_A0r_fields,
  41700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41701         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41702         -1,
  41703         -1,
  41704     },
  41705 #endif /* chips */
  41706 
  41707 #if defined(BCM_88375_B0)
  41708     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM88375_B0r */
  41709         soc_block_list[61],
  41710         soc_iprocreg,
  41711         1,
  41712         0,
  41713         0x18021120,
  41714         SOC_REG_FLAG_RO,
  41715         0,
  41716         1,
  41717         soc_QSPI_RAF_CURR_ADDR_BCM88375_B0r_fields,
  41718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41719         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41720         -1,
  41721         -1,
  41722     },
  41723 #endif /* chips */
  41724 
  41725 #if defined(BCM_88470_A0)
  41726     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM88470_A0r */
  41727         soc_block_list[61],
  41728         soc_iprocreg,
  41729         1,
  41730         0,
  41731         0x18021120,
  41732         SOC_REG_FLAG_RO,
  41733         0,
  41734         1,
  41735         soc_QSPI_RAF_CURR_ADDR_BCM88470_A0r_fields,
  41736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41737         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41738         -1,
  41739         -1,
  41740     },
  41741 #endif /* chips */
  41742 
  41743 #if defined(BCM_88470_B0)
  41744     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM88470_B0r */
  41745         soc_block_list[61],
  41746         soc_iprocreg,
  41747         1,
  41748         0,
  41749         0x18021120,
  41750         SOC_REG_FLAG_RO,
  41751         0,
  41752         1,
  41753         soc_QSPI_RAF_CURR_ADDR_BCM88470_B0r_fields,
  41754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41755         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41756         -1,
  41757         -1,
  41758     },
  41759 #endif /* chips */
  41760 
  41761 #if defined(BCM_88675_B0)
  41762     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM88675_B0r */
  41763         soc_block_list[61],
  41764         soc_iprocreg,
  41765         1,
  41766         0,
  41767         0x18021120,
  41768         SOC_REG_FLAG_RO,
  41769         0,
  41770         1,
  41771         soc_QSPI_RAF_CURR_ADDR_BCM88675_B0r_fields,
  41772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41773         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41774         -1,
  41775         -1,
  41776     },
  41777 #endif /* chips */
  41778 
  41779 #if defined(BCM_88680_A0)
  41780     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM88680_A0r */
  41781         soc_block_list[61],
  41782         soc_iprocreg,
  41783         1,
  41784         0,
  41785         0x18021120,
  41786         SOC_REG_FLAG_RO,
  41787         0,
  41788         1,
  41789         soc_QSPI_RAF_CURR_ADDR_BCM88680_A0r_fields,
  41790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41791         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41792         -1,
  41793         -1,
  41794     },
  41795 #endif /* chips */
  41796 
  41797 #if defined(BCM_88690_A0)
  41798     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM88690_A0r */
  41799         soc_block_list[61],
  41800         soc_iprocreg,
  41801         1,
  41802         0,
  41803         0x18021120,
  41804         SOC_REG_FLAG_RO,
  41805         0,
  41806         1,
  41807         soc_QSPI_RAF_CURR_ADDR_BCM88690_A0r_fields,
  41808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41809         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41810         -1,
  41811         -1,
  41812     },
  41813 #endif /* chips */
  41814 
  41815 #if defined(BCM_88690_B0)
  41816     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM88690_B0r */
  41817         soc_block_list[61],
  41818         soc_iprocreg,
  41819         1,
  41820         0,
  41821         0x18021120,
  41822         SOC_REG_FLAG_RO,
  41823         0,
  41824         1,
  41825         soc_QSPI_RAF_CURR_ADDR_BCM88690_B0r_fields,
  41826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41827         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41828         -1,
  41829         -1,
  41830     },
  41831 #endif /* chips */
  41832 
  41833 #if defined(BCM_88790_A0)
  41834     { /* SOC_REG_INT_QSPI_RAF_CURR_ADDR_BCM88790_A0r */
  41835         soc_block_list[61],
  41836         soc_iprocreg,
  41837         1,
  41838         0,
  41839         0x18021120,
  41840         SOC_REG_FLAG_RO,
  41841         0,
  41842         1,
  41843         soc_QSPI_RAF_CURR_ADDR_BCM88790_A0r_fields,
  41844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41845         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41846         -1,
  41847         -1,
  41848     },
  41849 #endif /* chips */
  41850 
  41851 #if defined(BCM_88790_A0)
  41852     { /* SOC_REG_INT_QSPI_RAF_ECC_LOGr */
  41853         soc_block_list[61],
  41854         soc_iprocreg,
  41855         1,
  41856         0,
  41857         0x18021124,
  41858         SOC_REG_FLAG_RO,
  41859         0,
  41860         5,
  41861         soc_QSPI_RAF_ECC_LOGr_fields,
  41862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41863         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  41864         -1,
  41865         -1,
  41866     },
  41867 #endif /* chips */
  41868 
  41869 #if defined(BCM_56370_A0)
  41870     { /* SOC_REG_INT_QSPI_RAF_ECC_LOG_BCM56370_A0r */
  41871         soc_block_list[61],
  41872         soc_iprocreg,
  41873         1,
  41874         0,
  41875         0x15000124,
  41876         SOC_REG_FLAG_RO,
  41877         0,
  41878         5,
  41879         soc_QSPI_RAF_ECC_LOG_BCM56970_A0r_fields,
  41880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41881         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  41882         -1,
  41883         -1,
  41884         3,
  41885     },
  41886 #endif /* chips */
  41887 
  41888 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  41889     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  41890     defined(BCM_56980_B0)
  41891     { /* SOC_REG_INT_QSPI_RAF_ECC_LOG_BCM56970_A0r */
  41892         soc_block_list[61],
  41893         soc_iprocreg,
  41894         1,
  41895         0,
  41896         0x18021124,
  41897         SOC_REG_FLAG_RO,
  41898         0,
  41899         5,
  41900         soc_QSPI_RAF_ECC_LOG_BCM56970_A0r_fields,
  41901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41902         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  41903         -1,
  41904         -1,
  41905         3,
  41906     },
  41907 #endif /* chips */
  41908 
  41909 #if defined(BCM_88690_A0)
  41910     { /* SOC_REG_INT_QSPI_RAF_ECC_LOG_BCM88690_A0r */
  41911         soc_block_list[61],
  41912         soc_iprocreg,
  41913         1,
  41914         0,
  41915         0x18021124,
  41916         SOC_REG_FLAG_RO,
  41917         0,
  41918         5,
  41919         soc_QSPI_RAF_ECC_LOG_BCM88690_A0r_fields,
  41920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41921         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  41922         -1,
  41923         -1,
  41924     },
  41925 #endif /* chips */
  41926 
  41927 #if defined(BCM_88690_B0)
  41928     { /* SOC_REG_INT_QSPI_RAF_ECC_LOG_BCM88690_B0r */
  41929         soc_block_list[61],
  41930         soc_iprocreg,
  41931         1,
  41932         0,
  41933         0x18021124,
  41934         SOC_REG_FLAG_RO,
  41935         0,
  41936         5,
  41937         soc_QSPI_RAF_ECC_LOG_BCM88690_B0r_fields,
  41938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41939         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  41940         -1,
  41941         -1,
  41942     },
  41943 #endif /* chips */
  41944 
  41945 #if defined(BCM_88675_A0)
  41946     { /* SOC_REG_INT_QSPI_RAF_FULLNESSr */
  41947         soc_block_list[61],
  41948         soc_iprocreg,
  41949         1,
  41950         0,
  41951         0x1802110c,
  41952         SOC_REG_FLAG_RO,
  41953         0,
  41954         2,
  41955         soc_QSPI_RAF_FULLNESSr_fields,
  41956         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41957         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41958         -1,
  41959         -1,
  41960     },
  41961 #endif /* chips */
  41962 
  41963 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  41964     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  41965     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  41966     defined(BCM_56260_B0)
  41967     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM53400_A0r */
  41968         soc_block_list[61],
  41969         soc_iprocreg,
  41970         1,
  41971         0,
  41972         0x1804710c,
  41973         SOC_REG_FLAG_RO,
  41974         0,
  41975         2,
  41976         soc_QSPI_RAF_FULLNESS_BCM53400_A0r_fields,
  41977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41978         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41979         -1,
  41980         -1,
  41981     },
  41982 #endif /* chips */
  41983 
  41984 #if defined(BCM_56370_A0)
  41985     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM56370_A0r */
  41986         soc_block_list[61],
  41987         soc_iprocreg,
  41988         1,
  41989         0,
  41990         0x1500010c,
  41991         SOC_REG_FLAG_RO,
  41992         0,
  41993         2,
  41994         soc_QSPI_RAF_FULLNESS_BCM53400_A0r_fields,
  41995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41997         -1,
  41998         -1,
  41999         3,
  42000     },
  42001 #endif /* chips */
  42002 
  42003 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  42004     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42005     defined(BCM_56450_B1)
  42006     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM56450_A0r */
  42007         soc_block_list[61],
  42008         soc_iprocreg,
  42009         1,
  42010         0,
  42011         0x1802710c,
  42012         SOC_REG_FLAG_RO,
  42013         0,
  42014         2,
  42015         soc_QSPI_RAF_FULLNESS_BCM56450_A0r_fields,
  42016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42018         -1,
  42019         -1,
  42020     },
  42021 #endif /* chips */
  42022 
  42023 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  42024     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  42025     defined(BCM_56670_B0)
  42026     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM56560_A0r */
  42027         soc_block_list[61],
  42028         soc_iprocreg,
  42029         1,
  42030         0,
  42031         0x1802110c,
  42032         SOC_REG_FLAG_RO,
  42033         0,
  42034         2,
  42035         soc_QSPI_RAF_FULLNESS_BCM53400_A0r_fields,
  42036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42037         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42038         -1,
  42039         -1,
  42040     },
  42041 #endif /* chips */
  42042 
  42043 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  42044     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  42045     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  42046     defined(BCM_56980_B0)
  42047     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM56960_A0r */
  42048         soc_block_list[61],
  42049         soc_iprocreg,
  42050         1,
  42051         0,
  42052         0x1802110c,
  42053         SOC_REG_FLAG_RO,
  42054         0,
  42055         2,
  42056         soc_QSPI_RAF_FULLNESS_BCM53400_A0r_fields,
  42057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42058         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42059         -1,
  42060         -1,
  42061         3,
  42062     },
  42063 #endif /* chips */
  42064 
  42065 #if defined(BCM_88270_A0)
  42066     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM88270_A0r */
  42067         soc_block_list[61],
  42068         soc_iprocreg,
  42069         1,
  42070         0,
  42071         0x1802110c,
  42072         SOC_REG_FLAG_RO,
  42073         0,
  42074         2,
  42075         soc_QSPI_RAF_FULLNESS_BCM88270_A0r_fields,
  42076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42078         -1,
  42079         -1,
  42080     },
  42081 #endif /* chips */
  42082 
  42083 #if defined(BCM_88375_A0)
  42084     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM88375_A0r */
  42085         soc_block_list[61],
  42086         soc_iprocreg,
  42087         1,
  42088         0,
  42089         0x1802110c,
  42090         SOC_REG_FLAG_RO,
  42091         0,
  42092         2,
  42093         soc_QSPI_RAF_FULLNESS_BCM88375_A0r_fields,
  42094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42096         -1,
  42097         -1,
  42098     },
  42099 #endif /* chips */
  42100 
  42101 #if defined(BCM_88375_B0)
  42102     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM88375_B0r */
  42103         soc_block_list[61],
  42104         soc_iprocreg,
  42105         1,
  42106         0,
  42107         0x1802110c,
  42108         SOC_REG_FLAG_RO,
  42109         0,
  42110         2,
  42111         soc_QSPI_RAF_FULLNESS_BCM88375_B0r_fields,
  42112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42113         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42114         -1,
  42115         -1,
  42116     },
  42117 #endif /* chips */
  42118 
  42119 #if defined(BCM_88470_A0)
  42120     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM88470_A0r */
  42121         soc_block_list[61],
  42122         soc_iprocreg,
  42123         1,
  42124         0,
  42125         0x1802110c,
  42126         SOC_REG_FLAG_RO,
  42127         0,
  42128         2,
  42129         soc_QSPI_RAF_FULLNESS_BCM88470_A0r_fields,
  42130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42132         -1,
  42133         -1,
  42134     },
  42135 #endif /* chips */
  42136 
  42137 #if defined(BCM_88470_B0)
  42138     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM88470_B0r */
  42139         soc_block_list[61],
  42140         soc_iprocreg,
  42141         1,
  42142         0,
  42143         0x1802110c,
  42144         SOC_REG_FLAG_RO,
  42145         0,
  42146         2,
  42147         soc_QSPI_RAF_FULLNESS_BCM88470_B0r_fields,
  42148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42149         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42150         -1,
  42151         -1,
  42152     },
  42153 #endif /* chips */
  42154 
  42155 #if defined(BCM_88675_B0)
  42156     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM88675_B0r */
  42157         soc_block_list[61],
  42158         soc_iprocreg,
  42159         1,
  42160         0,
  42161         0x1802110c,
  42162         SOC_REG_FLAG_RO,
  42163         0,
  42164         2,
  42165         soc_QSPI_RAF_FULLNESS_BCM88675_B0r_fields,
  42166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42168         -1,
  42169         -1,
  42170     },
  42171 #endif /* chips */
  42172 
  42173 #if defined(BCM_88680_A0)
  42174     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM88680_A0r */
  42175         soc_block_list[61],
  42176         soc_iprocreg,
  42177         1,
  42178         0,
  42179         0x1802110c,
  42180         SOC_REG_FLAG_RO,
  42181         0,
  42182         2,
  42183         soc_QSPI_RAF_FULLNESS_BCM88680_A0r_fields,
  42184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42186         -1,
  42187         -1,
  42188     },
  42189 #endif /* chips */
  42190 
  42191 #if defined(BCM_88690_A0)
  42192     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM88690_A0r */
  42193         soc_block_list[61],
  42194         soc_iprocreg,
  42195         1,
  42196         0,
  42197         0x1802110c,
  42198         SOC_REG_FLAG_RO,
  42199         0,
  42200         2,
  42201         soc_QSPI_RAF_FULLNESS_BCM88690_A0r_fields,
  42202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42203         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42204         -1,
  42205         -1,
  42206     },
  42207 #endif /* chips */
  42208 
  42209 #if defined(BCM_88690_B0)
  42210     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM88690_B0r */
  42211         soc_block_list[61],
  42212         soc_iprocreg,
  42213         1,
  42214         0,
  42215         0x1802110c,
  42216         SOC_REG_FLAG_RO,
  42217         0,
  42218         2,
  42219         soc_QSPI_RAF_FULLNESS_BCM88690_B0r_fields,
  42220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42221         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42222         -1,
  42223         -1,
  42224     },
  42225 #endif /* chips */
  42226 
  42227 #if defined(BCM_88790_A0)
  42228     { /* SOC_REG_INT_QSPI_RAF_FULLNESS_BCM88790_A0r */
  42229         soc_block_list[61],
  42230         soc_iprocreg,
  42231         1,
  42232         0,
  42233         0x1802110c,
  42234         SOC_REG_FLAG_RO,
  42235         0,
  42236         2,
  42237         soc_QSPI_RAF_FULLNESS_BCM88790_A0r_fields,
  42238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42239         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42240         -1,
  42241         -1,
  42242     },
  42243 #endif /* chips */
  42244 
  42245 #if defined(BCM_88790_A0)
  42246     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_ECC_2B_UNCORRECTABLE_ERR_DETECTEDr */
  42247         soc_block_list[61],
  42248         soc_iprocreg,
  42249         1,
  42250         0,
  42251         0x180213bc,
  42252         0,
  42253         0,
  42254         2,
  42255         soc_QSPI_RAF_INTERRUPT_ECC_2B_UNCORRECTABLE_ERR_DETECTEDr_fields,
  42256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42257         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  42258         -1,
  42259         -1,
  42260     },
  42261 #endif /* chips */
  42262 
  42263 #if defined(BCM_56370_A0)
  42264     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_ECC_2B_UNCORRECTABLE_ERR_DETECTED_BCM56370_A0r */
  42265         soc_block_list[61],
  42266         soc_iprocreg,
  42267         1,
  42268         0,
  42269         0x150003bc,
  42270         0,
  42271         0,
  42272         2,
  42273         soc_QSPI_RAF_INTERRUPT_ECC_2B_UNCORRECTABLE_ERR_DETECTED_BCM56970_A0r_fields,
  42274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42275         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  42276         -1,
  42277         -1,
  42278         3,
  42279     },
  42280 #endif /* chips */
  42281 
  42282 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  42283     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  42284     defined(BCM_56980_B0)
  42285     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_ECC_2B_UNCORRECTABLE_ERR_DETECTED_BCM56970_A0r */
  42286         soc_block_list[61],
  42287         soc_iprocreg,
  42288         1,
  42289         0,
  42290         0x180213bc,
  42291         0,
  42292         0,
  42293         2,
  42294         soc_QSPI_RAF_INTERRUPT_ECC_2B_UNCORRECTABLE_ERR_DETECTED_BCM56970_A0r_fields,
  42295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42296         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  42297         -1,
  42298         -1,
  42299         3,
  42300     },
  42301 #endif /* chips */
  42302 
  42303 #if defined(BCM_88690_A0)
  42304     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_ECC_2B_UNCORRECTABLE_ERR_DETECTED_BCM88690_A0r */
  42305         soc_block_list[61],
  42306         soc_iprocreg,
  42307         1,
  42308         0,
  42309         0x180213bc,
  42310         0,
  42311         0,
  42312         2,
  42313         soc_QSPI_RAF_INTERRUPT_ECC_2B_UNCORRECTABLE_ERR_DETECTED_BCM88690_A0r_fields,
  42314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42315         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  42316         -1,
  42317         -1,
  42318     },
  42319 #endif /* chips */
  42320 
  42321 #if defined(BCM_88690_B0)
  42322     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_ECC_2B_UNCORRECTABLE_ERR_DETECTED_BCM88690_B0r */
  42323         soc_block_list[61],
  42324         soc_iprocreg,
  42325         1,
  42326         0,
  42327         0x180213bc,
  42328         0,
  42329         0,
  42330         2,
  42331         soc_QSPI_RAF_INTERRUPT_ECC_2B_UNCORRECTABLE_ERR_DETECTED_BCM88690_B0r_fields,
  42332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42333         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  42334         -1,
  42335         -1,
  42336     },
  42337 #endif /* chips */
  42338 
  42339 #if defined(BCM_88675_A0)
  42340     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHEDr */
  42341         soc_block_list[61],
  42342         soc_iprocreg,
  42343         1,
  42344         0,
  42345         0x180213a0,
  42346         0,
  42347         0,
  42348         1,
  42349         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHEDr_fields,
  42350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42351         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42352         -1,
  42353         -1,
  42354     },
  42355 #endif /* chips */
  42356 
  42357 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  42358     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  42359     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  42360     defined(BCM_56260_B0)
  42361     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM53400_A0r */
  42362         soc_block_list[61],
  42363         soc_iprocreg,
  42364         1,
  42365         0,
  42366         0x180473a0,
  42367         0,
  42368         0,
  42369         1,
  42370         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM53400_A0r_fields,
  42371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42372         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42373         -1,
  42374         -1,
  42375     },
  42376 #endif /* chips */
  42377 
  42378 #if defined(BCM_56370_A0)
  42379     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM56370_A0r */
  42380         soc_block_list[61],
  42381         soc_iprocreg,
  42382         1,
  42383         0,
  42384         0x150003a0,
  42385         0,
  42386         0,
  42387         1,
  42388         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM53400_A0r_fields,
  42389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42390         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42391         -1,
  42392         -1,
  42393         3,
  42394     },
  42395 #endif /* chips */
  42396 
  42397 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  42398     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42399     defined(BCM_56450_B1)
  42400     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM56450_A0r */
  42401         soc_block_list[61],
  42402         soc_iprocreg,
  42403         1,
  42404         0,
  42405         0x180273a0,
  42406         0,
  42407         0,
  42408         1,
  42409         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM56450_A0r_fields,
  42410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42411         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42412         -1,
  42413         -1,
  42414     },
  42415 #endif /* chips */
  42416 
  42417 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  42418     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  42419     defined(BCM_56670_B0)
  42420     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM56560_A0r */
  42421         soc_block_list[61],
  42422         soc_iprocreg,
  42423         1,
  42424         0,
  42425         0x180213a0,
  42426         0,
  42427         0,
  42428         1,
  42429         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM53400_A0r_fields,
  42430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42431         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42432         -1,
  42433         -1,
  42434     },
  42435 #endif /* chips */
  42436 
  42437 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  42438     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  42439     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  42440     defined(BCM_56980_B0)
  42441     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM56960_A0r */
  42442         soc_block_list[61],
  42443         soc_iprocreg,
  42444         1,
  42445         0,
  42446         0x180213a0,
  42447         0,
  42448         0,
  42449         1,
  42450         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM53400_A0r_fields,
  42451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42452         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42453         -1,
  42454         -1,
  42455         3,
  42456     },
  42457 #endif /* chips */
  42458 
  42459 #if defined(BCM_88270_A0)
  42460     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88270_A0r */
  42461         soc_block_list[61],
  42462         soc_iprocreg,
  42463         1,
  42464         0,
  42465         0x180213a0,
  42466         0,
  42467         0,
  42468         1,
  42469         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88270_A0r_fields,
  42470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42471         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42472         -1,
  42473         -1,
  42474     },
  42475 #endif /* chips */
  42476 
  42477 #if defined(BCM_88375_A0)
  42478     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88375_A0r */
  42479         soc_block_list[61],
  42480         soc_iprocreg,
  42481         1,
  42482         0,
  42483         0x180213a0,
  42484         0,
  42485         0,
  42486         1,
  42487         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88375_A0r_fields,
  42488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42489         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42490         -1,
  42491         -1,
  42492     },
  42493 #endif /* chips */
  42494 
  42495 #if defined(BCM_88375_B0)
  42496     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88375_B0r */
  42497         soc_block_list[61],
  42498         soc_iprocreg,
  42499         1,
  42500         0,
  42501         0x180213a0,
  42502         0,
  42503         0,
  42504         1,
  42505         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88375_B0r_fields,
  42506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42507         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42508         -1,
  42509         -1,
  42510     },
  42511 #endif /* chips */
  42512 
  42513 #if defined(BCM_88470_A0)
  42514     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88470_A0r */
  42515         soc_block_list[61],
  42516         soc_iprocreg,
  42517         1,
  42518         0,
  42519         0x180213a0,
  42520         0,
  42521         0,
  42522         1,
  42523         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88470_A0r_fields,
  42524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42525         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42526         -1,
  42527         -1,
  42528     },
  42529 #endif /* chips */
  42530 
  42531 #if defined(BCM_88470_B0)
  42532     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88470_B0r */
  42533         soc_block_list[61],
  42534         soc_iprocreg,
  42535         1,
  42536         0,
  42537         0x180213a0,
  42538         0,
  42539         0,
  42540         1,
  42541         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88470_B0r_fields,
  42542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42543         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42544         -1,
  42545         -1,
  42546     },
  42547 #endif /* chips */
  42548 
  42549 #if defined(BCM_88675_B0)
  42550     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88675_B0r */
  42551         soc_block_list[61],
  42552         soc_iprocreg,
  42553         1,
  42554         0,
  42555         0x180213a0,
  42556         0,
  42557         0,
  42558         1,
  42559         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88675_B0r_fields,
  42560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42561         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42562         -1,
  42563         -1,
  42564     },
  42565 #endif /* chips */
  42566 
  42567 #if defined(BCM_88680_A0)
  42568     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88680_A0r */
  42569         soc_block_list[61],
  42570         soc_iprocreg,
  42571         1,
  42572         0,
  42573         0x180213a0,
  42574         0,
  42575         0,
  42576         1,
  42577         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88680_A0r_fields,
  42578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42579         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42580         -1,
  42581         -1,
  42582     },
  42583 #endif /* chips */
  42584 
  42585 #if defined(BCM_88690_A0)
  42586     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88690_A0r */
  42587         soc_block_list[61],
  42588         soc_iprocreg,
  42589         1,
  42590         0,
  42591         0x180213a0,
  42592         0,
  42593         0,
  42594         1,
  42595         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88690_A0r_fields,
  42596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42597         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42598         -1,
  42599         -1,
  42600     },
  42601 #endif /* chips */
  42602 
  42603 #if defined(BCM_88690_B0)
  42604     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88690_B0r */
  42605         soc_block_list[61],
  42606         soc_iprocreg,
  42607         1,
  42608         0,
  42609         0x180213a0,
  42610         0,
  42611         0,
  42612         1,
  42613         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88690_B0r_fields,
  42614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42615         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42616         -1,
  42617         -1,
  42618     },
  42619 #endif /* chips */
  42620 
  42621 #if defined(BCM_88790_A0)
  42622     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88790_A0r */
  42623         soc_block_list[61],
  42624         soc_iprocreg,
  42625         1,
  42626         0,
  42627         0x180213a0,
  42628         0,
  42629         0,
  42630         1,
  42631         soc_QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_BCM88790_A0r_fields,
  42632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42633         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42634         -1,
  42635         -1,
  42636     },
  42637 #endif /* chips */
  42638 
  42639 #if defined(BCM_88675_A0)
  42640     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENTr */
  42641         soc_block_list[61],
  42642         soc_iprocreg,
  42643         1,
  42644         0,
  42645         0x180213a8,
  42646         0,
  42647         0,
  42648         1,
  42649         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENTr_fields,
  42650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42651         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42652         -1,
  42653         -1,
  42654     },
  42655 #endif /* chips */
  42656 
  42657 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  42658     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  42659     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  42660     defined(BCM_56260_B0)
  42661     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM53400_A0r */
  42662         soc_block_list[61],
  42663         soc_iprocreg,
  42664         1,
  42665         0,
  42666         0x180473a8,
  42667         0,
  42668         0,
  42669         1,
  42670         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM53400_A0r_fields,
  42671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42672         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42673         -1,
  42674         -1,
  42675     },
  42676 #endif /* chips */
  42677 
  42678 #if defined(BCM_56370_A0)
  42679     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM56370_A0r */
  42680         soc_block_list[61],
  42681         soc_iprocreg,
  42682         1,
  42683         0,
  42684         0x150003a8,
  42685         0,
  42686         0,
  42687         1,
  42688         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM53400_A0r_fields,
  42689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42690         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42691         -1,
  42692         -1,
  42693         3,
  42694     },
  42695 #endif /* chips */
  42696 
  42697 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  42698     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42699     defined(BCM_56450_B1)
  42700     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM56450_A0r */
  42701         soc_block_list[61],
  42702         soc_iprocreg,
  42703         1,
  42704         0,
  42705         0x180273a8,
  42706         0,
  42707         0,
  42708         1,
  42709         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM56450_A0r_fields,
  42710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42711         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42712         -1,
  42713         -1,
  42714     },
  42715 #endif /* chips */
  42716 
  42717 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  42718     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  42719     defined(BCM_56670_B0)
  42720     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM56560_A0r */
  42721         soc_block_list[61],
  42722         soc_iprocreg,
  42723         1,
  42724         0,
  42725         0x180213a8,
  42726         0,
  42727         0,
  42728         1,
  42729         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM53400_A0r_fields,
  42730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42731         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42732         -1,
  42733         -1,
  42734     },
  42735 #endif /* chips */
  42736 
  42737 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  42738     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  42739     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  42740     defined(BCM_56980_B0)
  42741     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM56960_A0r */
  42742         soc_block_list[61],
  42743         soc_iprocreg,
  42744         1,
  42745         0,
  42746         0x180213a8,
  42747         0,
  42748         0,
  42749         1,
  42750         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM53400_A0r_fields,
  42751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42752         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42753         -1,
  42754         -1,
  42755         3,
  42756     },
  42757 #endif /* chips */
  42758 
  42759 #if defined(BCM_88270_A0)
  42760     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88270_A0r */
  42761         soc_block_list[61],
  42762         soc_iprocreg,
  42763         1,
  42764         0,
  42765         0x180213a8,
  42766         0,
  42767         0,
  42768         1,
  42769         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88270_A0r_fields,
  42770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42771         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42772         -1,
  42773         -1,
  42774     },
  42775 #endif /* chips */
  42776 
  42777 #if defined(BCM_88375_A0)
  42778     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88375_A0r */
  42779         soc_block_list[61],
  42780         soc_iprocreg,
  42781         1,
  42782         0,
  42783         0x180213a8,
  42784         0,
  42785         0,
  42786         1,
  42787         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88375_A0r_fields,
  42788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42789         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42790         -1,
  42791         -1,
  42792     },
  42793 #endif /* chips */
  42794 
  42795 #if defined(BCM_88375_B0)
  42796     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88375_B0r */
  42797         soc_block_list[61],
  42798         soc_iprocreg,
  42799         1,
  42800         0,
  42801         0x180213a8,
  42802         0,
  42803         0,
  42804         1,
  42805         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88375_B0r_fields,
  42806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42807         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42808         -1,
  42809         -1,
  42810     },
  42811 #endif /* chips */
  42812 
  42813 #if defined(BCM_88470_A0)
  42814     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88470_A0r */
  42815         soc_block_list[61],
  42816         soc_iprocreg,
  42817         1,
  42818         0,
  42819         0x180213a8,
  42820         0,
  42821         0,
  42822         1,
  42823         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88470_A0r_fields,
  42824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42825         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42826         -1,
  42827         -1,
  42828     },
  42829 #endif /* chips */
  42830 
  42831 #if defined(BCM_88470_B0)
  42832     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88470_B0r */
  42833         soc_block_list[61],
  42834         soc_iprocreg,
  42835         1,
  42836         0,
  42837         0x180213a8,
  42838         0,
  42839         0,
  42840         1,
  42841         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88470_B0r_fields,
  42842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42843         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42844         -1,
  42845         -1,
  42846     },
  42847 #endif /* chips */
  42848 
  42849 #if defined(BCM_88675_B0)
  42850     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88675_B0r */
  42851         soc_block_list[61],
  42852         soc_iprocreg,
  42853         1,
  42854         0,
  42855         0x180213a8,
  42856         0,
  42857         0,
  42858         1,
  42859         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88675_B0r_fields,
  42860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42861         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42862         -1,
  42863         -1,
  42864     },
  42865 #endif /* chips */
  42866 
  42867 #if defined(BCM_88680_A0)
  42868     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88680_A0r */
  42869         soc_block_list[61],
  42870         soc_iprocreg,
  42871         1,
  42872         0,
  42873         0x180213a8,
  42874         0,
  42875         0,
  42876         1,
  42877         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88680_A0r_fields,
  42878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42879         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42880         -1,
  42881         -1,
  42882     },
  42883 #endif /* chips */
  42884 
  42885 #if defined(BCM_88690_A0)
  42886     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88690_A0r */
  42887         soc_block_list[61],
  42888         soc_iprocreg,
  42889         1,
  42890         0,
  42891         0x180213a8,
  42892         0,
  42893         0,
  42894         1,
  42895         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88690_A0r_fields,
  42896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42897         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42898         -1,
  42899         -1,
  42900     },
  42901 #endif /* chips */
  42902 
  42903 #if defined(BCM_88690_B0)
  42904     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88690_B0r */
  42905         soc_block_list[61],
  42906         soc_iprocreg,
  42907         1,
  42908         0,
  42909         0x180213a8,
  42910         0,
  42911         0,
  42912         1,
  42913         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88690_B0r_fields,
  42914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42915         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42916         -1,
  42917         -1,
  42918     },
  42919 #endif /* chips */
  42920 
  42921 #if defined(BCM_88790_A0)
  42922     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88790_A0r */
  42923         soc_block_list[61],
  42924         soc_iprocreg,
  42925         1,
  42926         0,
  42927         0x180213a8,
  42928         0,
  42929         0,
  42930         1,
  42931         soc_QSPI_RAF_INTERRUPT_LR_IMPATIENT_BCM88790_A0r_fields,
  42932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42933         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42934         -1,
  42935         -1,
  42936     },
  42937 #endif /* chips */
  42938 
  42939 #if defined(BCM_88675_A0)
  42940     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREADr */
  42941         soc_block_list[61],
  42942         soc_iprocreg,
  42943         1,
  42944         0,
  42945         0x180213b0,
  42946         0,
  42947         0,
  42948         1,
  42949         soc_QSPI_RAF_INTERRUPT_LR_OVERREADr_fields,
  42950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42951         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42952         -1,
  42953         -1,
  42954     },
  42955 #endif /* chips */
  42956 
  42957 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  42958     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  42959     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  42960     defined(BCM_56260_B0)
  42961     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM53400_A0r */
  42962         soc_block_list[61],
  42963         soc_iprocreg,
  42964         1,
  42965         0,
  42966         0x180473b0,
  42967         0,
  42968         0,
  42969         1,
  42970         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM53400_A0r_fields,
  42971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42972         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42973         -1,
  42974         -1,
  42975     },
  42976 #endif /* chips */
  42977 
  42978 #if defined(BCM_56370_A0)
  42979     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM56370_A0r */
  42980         soc_block_list[61],
  42981         soc_iprocreg,
  42982         1,
  42983         0,
  42984         0x150003b0,
  42985         0,
  42986         0,
  42987         1,
  42988         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM53400_A0r_fields,
  42989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42990         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  42991         -1,
  42992         -1,
  42993         3,
  42994     },
  42995 #endif /* chips */
  42996 
  42997 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  42998     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  42999     defined(BCM_56450_B1)
  43000     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM56450_A0r */
  43001         soc_block_list[61],
  43002         soc_iprocreg,
  43003         1,
  43004         0,
  43005         0x180273b0,
  43006         0,
  43007         0,
  43008         1,
  43009         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM56450_A0r_fields,
  43010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43011         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43012         -1,
  43013         -1,
  43014     },
  43015 #endif /* chips */
  43016 
  43017 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  43018     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  43019     defined(BCM_56670_B0)
  43020     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM56560_A0r */
  43021         soc_block_list[61],
  43022         soc_iprocreg,
  43023         1,
  43024         0,
  43025         0x180213b0,
  43026         0,
  43027         0,
  43028         1,
  43029         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM53400_A0r_fields,
  43030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43031         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43032         -1,
  43033         -1,
  43034     },
  43035 #endif /* chips */
  43036 
  43037 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  43038     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  43039     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  43040     defined(BCM_56980_B0)
  43041     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM56960_A0r */
  43042         soc_block_list[61],
  43043         soc_iprocreg,
  43044         1,
  43045         0,
  43046         0x180213b0,
  43047         0,
  43048         0,
  43049         1,
  43050         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM53400_A0r_fields,
  43051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43052         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43053         -1,
  43054         -1,
  43055         3,
  43056     },
  43057 #endif /* chips */
  43058 
  43059 #if defined(BCM_88270_A0)
  43060     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88270_A0r */
  43061         soc_block_list[61],
  43062         soc_iprocreg,
  43063         1,
  43064         0,
  43065         0x180213b0,
  43066         0,
  43067         0,
  43068         1,
  43069         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88270_A0r_fields,
  43070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43071         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43072         -1,
  43073         -1,
  43074     },
  43075 #endif /* chips */
  43076 
  43077 #if defined(BCM_88375_A0)
  43078     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88375_A0r */
  43079         soc_block_list[61],
  43080         soc_iprocreg,
  43081         1,
  43082         0,
  43083         0x180213b0,
  43084         0,
  43085         0,
  43086         1,
  43087         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88375_A0r_fields,
  43088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43089         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43090         -1,
  43091         -1,
  43092     },
  43093 #endif /* chips */
  43094 
  43095 #if defined(BCM_88375_B0)
  43096     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88375_B0r */
  43097         soc_block_list[61],
  43098         soc_iprocreg,
  43099         1,
  43100         0,
  43101         0x180213b0,
  43102         0,
  43103         0,
  43104         1,
  43105         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88375_B0r_fields,
  43106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43107         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43108         -1,
  43109         -1,
  43110     },
  43111 #endif /* chips */
  43112 
  43113 #if defined(BCM_88470_A0)
  43114     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88470_A0r */
  43115         soc_block_list[61],
  43116         soc_iprocreg,
  43117         1,
  43118         0,
  43119         0x180213b0,
  43120         0,
  43121         0,
  43122         1,
  43123         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88470_A0r_fields,
  43124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43125         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43126         -1,
  43127         -1,
  43128     },
  43129 #endif /* chips */
  43130 
  43131 #if defined(BCM_88470_B0)
  43132     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88470_B0r */
  43133         soc_block_list[61],
  43134         soc_iprocreg,
  43135         1,
  43136         0,
  43137         0x180213b0,
  43138         0,
  43139         0,
  43140         1,
  43141         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88470_B0r_fields,
  43142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43143         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43144         -1,
  43145         -1,
  43146     },
  43147 #endif /* chips */
  43148 
  43149 #if defined(BCM_88675_B0)
  43150     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88675_B0r */
  43151         soc_block_list[61],
  43152         soc_iprocreg,
  43153         1,
  43154         0,
  43155         0x180213b0,
  43156         0,
  43157         0,
  43158         1,
  43159         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88675_B0r_fields,
  43160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43161         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43162         -1,
  43163         -1,
  43164     },
  43165 #endif /* chips */
  43166 
  43167 #if defined(BCM_88680_A0)
  43168     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88680_A0r */
  43169         soc_block_list[61],
  43170         soc_iprocreg,
  43171         1,
  43172         0,
  43173         0x180213b0,
  43174         0,
  43175         0,
  43176         1,
  43177         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88680_A0r_fields,
  43178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43179         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43180         -1,
  43181         -1,
  43182     },
  43183 #endif /* chips */
  43184 
  43185 #if defined(BCM_88690_A0)
  43186     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88690_A0r */
  43187         soc_block_list[61],
  43188         soc_iprocreg,
  43189         1,
  43190         0,
  43191         0x180213b0,
  43192         0,
  43193         0,
  43194         1,
  43195         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88690_A0r_fields,
  43196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43197         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43198         -1,
  43199         -1,
  43200     },
  43201 #endif /* chips */
  43202 
  43203 #if defined(BCM_88690_B0)
  43204     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88690_B0r */
  43205         soc_block_list[61],
  43206         soc_iprocreg,
  43207         1,
  43208         0,
  43209         0x180213b0,
  43210         0,
  43211         0,
  43212         1,
  43213         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88690_B0r_fields,
  43214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43215         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43216         -1,
  43217         -1,
  43218     },
  43219 #endif /* chips */
  43220 
  43221 #if defined(BCM_88790_A0)
  43222     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88790_A0r */
  43223         soc_block_list[61],
  43224         soc_iprocreg,
  43225         1,
  43226         0,
  43227         0x180213b0,
  43228         0,
  43229         0,
  43230         1,
  43231         soc_QSPI_RAF_INTERRUPT_LR_OVERREAD_BCM88790_A0r_fields,
  43232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43233         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43234         -1,
  43235         -1,
  43236     },
  43237 #endif /* chips */
  43238 
  43239 #if defined(BCM_88675_A0)
  43240     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONEr */
  43241         soc_block_list[61],
  43242         soc_iprocreg,
  43243         1,
  43244         0,
  43245         0x180213ac,
  43246         0,
  43247         0,
  43248         1,
  43249         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONEr_fields,
  43250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43251         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43252         -1,
  43253         -1,
  43254     },
  43255 #endif /* chips */
  43256 
  43257 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  43258     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  43259     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  43260     defined(BCM_56260_B0)
  43261     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM53400_A0r */
  43262         soc_block_list[61],
  43263         soc_iprocreg,
  43264         1,
  43265         0,
  43266         0x180473ac,
  43267         0,
  43268         0,
  43269         1,
  43270         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM53400_A0r_fields,
  43271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43272         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43273         -1,
  43274         -1,
  43275     },
  43276 #endif /* chips */
  43277 
  43278 #if defined(BCM_56370_A0)
  43279     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM56370_A0r */
  43280         soc_block_list[61],
  43281         soc_iprocreg,
  43282         1,
  43283         0,
  43284         0x150003ac,
  43285         0,
  43286         0,
  43287         1,
  43288         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM53400_A0r_fields,
  43289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43290         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43291         -1,
  43292         -1,
  43293         3,
  43294     },
  43295 #endif /* chips */
  43296 
  43297 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  43298     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43299     defined(BCM_56450_B1)
  43300     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM56450_A0r */
  43301         soc_block_list[61],
  43302         soc_iprocreg,
  43303         1,
  43304         0,
  43305         0x180273ac,
  43306         0,
  43307         0,
  43308         1,
  43309         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM56450_A0r_fields,
  43310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43311         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43312         -1,
  43313         -1,
  43314     },
  43315 #endif /* chips */
  43316 
  43317 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  43318     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  43319     defined(BCM_56670_B0)
  43320     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM56560_A0r */
  43321         soc_block_list[61],
  43322         soc_iprocreg,
  43323         1,
  43324         0,
  43325         0x180213ac,
  43326         0,
  43327         0,
  43328         1,
  43329         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM53400_A0r_fields,
  43330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43331         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43332         -1,
  43333         -1,
  43334     },
  43335 #endif /* chips */
  43336 
  43337 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  43338     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  43339     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  43340     defined(BCM_56980_B0)
  43341     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM56960_A0r */
  43342         soc_block_list[61],
  43343         soc_iprocreg,
  43344         1,
  43345         0,
  43346         0x180213ac,
  43347         0,
  43348         0,
  43349         1,
  43350         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM53400_A0r_fields,
  43351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43352         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43353         -1,
  43354         -1,
  43355         3,
  43356     },
  43357 #endif /* chips */
  43358 
  43359 #if defined(BCM_88270_A0)
  43360     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88270_A0r */
  43361         soc_block_list[61],
  43362         soc_iprocreg,
  43363         1,
  43364         0,
  43365         0x180213ac,
  43366         0,
  43367         0,
  43368         1,
  43369         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88270_A0r_fields,
  43370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43371         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43372         -1,
  43373         -1,
  43374     },
  43375 #endif /* chips */
  43376 
  43377 #if defined(BCM_88375_A0)
  43378     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88375_A0r */
  43379         soc_block_list[61],
  43380         soc_iprocreg,
  43381         1,
  43382         0,
  43383         0x180213ac,
  43384         0,
  43385         0,
  43386         1,
  43387         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88375_A0r_fields,
  43388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43389         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43390         -1,
  43391         -1,
  43392     },
  43393 #endif /* chips */
  43394 
  43395 #if defined(BCM_88375_B0)
  43396     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88375_B0r */
  43397         soc_block_list[61],
  43398         soc_iprocreg,
  43399         1,
  43400         0,
  43401         0x180213ac,
  43402         0,
  43403         0,
  43404         1,
  43405         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88375_B0r_fields,
  43406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43407         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43408         -1,
  43409         -1,
  43410     },
  43411 #endif /* chips */
  43412 
  43413 #if defined(BCM_88470_A0)
  43414     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88470_A0r */
  43415         soc_block_list[61],
  43416         soc_iprocreg,
  43417         1,
  43418         0,
  43419         0x180213ac,
  43420         0,
  43421         0,
  43422         1,
  43423         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88470_A0r_fields,
  43424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43425         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43426         -1,
  43427         -1,
  43428     },
  43429 #endif /* chips */
  43430 
  43431 #if defined(BCM_88470_B0)
  43432     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88470_B0r */
  43433         soc_block_list[61],
  43434         soc_iprocreg,
  43435         1,
  43436         0,
  43437         0x180213ac,
  43438         0,
  43439         0,
  43440         1,
  43441         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88470_B0r_fields,
  43442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43443         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43444         -1,
  43445         -1,
  43446     },
  43447 #endif /* chips */
  43448 
  43449 #if defined(BCM_88675_B0)
  43450     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88675_B0r */
  43451         soc_block_list[61],
  43452         soc_iprocreg,
  43453         1,
  43454         0,
  43455         0x180213ac,
  43456         0,
  43457         0,
  43458         1,
  43459         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88675_B0r_fields,
  43460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43461         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43462         -1,
  43463         -1,
  43464     },
  43465 #endif /* chips */
  43466 
  43467 #if defined(BCM_88680_A0)
  43468     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88680_A0r */
  43469         soc_block_list[61],
  43470         soc_iprocreg,
  43471         1,
  43472         0,
  43473         0x180213ac,
  43474         0,
  43475         0,
  43476         1,
  43477         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88680_A0r_fields,
  43478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43479         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43480         -1,
  43481         -1,
  43482     },
  43483 #endif /* chips */
  43484 
  43485 #if defined(BCM_88690_A0)
  43486     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88690_A0r */
  43487         soc_block_list[61],
  43488         soc_iprocreg,
  43489         1,
  43490         0,
  43491         0x180213ac,
  43492         0,
  43493         0,
  43494         1,
  43495         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88690_A0r_fields,
  43496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43497         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43498         -1,
  43499         -1,
  43500     },
  43501 #endif /* chips */
  43502 
  43503 #if defined(BCM_88690_B0)
  43504     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88690_B0r */
  43505         soc_block_list[61],
  43506         soc_iprocreg,
  43507         1,
  43508         0,
  43509         0x180213ac,
  43510         0,
  43511         0,
  43512         1,
  43513         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88690_B0r_fields,
  43514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43515         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43516         -1,
  43517         -1,
  43518     },
  43519 #endif /* chips */
  43520 
  43521 #if defined(BCM_88790_A0)
  43522     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88790_A0r */
  43523         soc_block_list[61],
  43524         soc_iprocreg,
  43525         1,
  43526         0,
  43527         0x180213ac,
  43528         0,
  43529         0,
  43530         1,
  43531         soc_QSPI_RAF_INTERRUPT_LR_SESSION_DONE_BCM88790_A0r_fields,
  43532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43533         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43534         -1,
  43535         -1,
  43536     },
  43537 #endif /* chips */
  43538 
  43539 #if defined(BCM_88675_A0)
  43540     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATEDr */
  43541         soc_block_list[61],
  43542         soc_iprocreg,
  43543         1,
  43544         0,
  43545         0x180213a4,
  43546         0,
  43547         0,
  43548         1,
  43549         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATEDr_fields,
  43550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43551         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43552         -1,
  43553         -1,
  43554     },
  43555 #endif /* chips */
  43556 
  43557 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  43558     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  43559     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  43560     defined(BCM_56260_B0)
  43561     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM53400_A0r */
  43562         soc_block_list[61],
  43563         soc_iprocreg,
  43564         1,
  43565         0,
  43566         0x180473a4,
  43567         0,
  43568         0,
  43569         1,
  43570         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM53400_A0r_fields,
  43571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43572         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43573         -1,
  43574         -1,
  43575     },
  43576 #endif /* chips */
  43577 
  43578 #if defined(BCM_56370_A0)
  43579     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM56370_A0r */
  43580         soc_block_list[61],
  43581         soc_iprocreg,
  43582         1,
  43583         0,
  43584         0x150003a4,
  43585         0,
  43586         0,
  43587         1,
  43588         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM53400_A0r_fields,
  43589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43590         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43591         -1,
  43592         -1,
  43593         3,
  43594     },
  43595 #endif /* chips */
  43596 
  43597 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  43598     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43599     defined(BCM_56450_B1)
  43600     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM56450_A0r */
  43601         soc_block_list[61],
  43602         soc_iprocreg,
  43603         1,
  43604         0,
  43605         0x180273a4,
  43606         0,
  43607         0,
  43608         1,
  43609         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM56450_A0r_fields,
  43610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43611         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43612         -1,
  43613         -1,
  43614     },
  43615 #endif /* chips */
  43616 
  43617 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  43618     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  43619     defined(BCM_56670_B0)
  43620     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM56560_A0r */
  43621         soc_block_list[61],
  43622         soc_iprocreg,
  43623         1,
  43624         0,
  43625         0x180213a4,
  43626         0,
  43627         0,
  43628         1,
  43629         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM53400_A0r_fields,
  43630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43631         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43632         -1,
  43633         -1,
  43634     },
  43635 #endif /* chips */
  43636 
  43637 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  43638     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  43639     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  43640     defined(BCM_56980_B0)
  43641     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM56960_A0r */
  43642         soc_block_list[61],
  43643         soc_iprocreg,
  43644         1,
  43645         0,
  43646         0x180213a4,
  43647         0,
  43648         0,
  43649         1,
  43650         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM53400_A0r_fields,
  43651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43652         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43653         -1,
  43654         -1,
  43655         3,
  43656     },
  43657 #endif /* chips */
  43658 
  43659 #if defined(BCM_88270_A0)
  43660     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88270_A0r */
  43661         soc_block_list[61],
  43662         soc_iprocreg,
  43663         1,
  43664         0,
  43665         0x180213a4,
  43666         0,
  43667         0,
  43668         1,
  43669         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88270_A0r_fields,
  43670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43671         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43672         -1,
  43673         -1,
  43674     },
  43675 #endif /* chips */
  43676 
  43677 #if defined(BCM_88375_A0)
  43678     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88375_A0r */
  43679         soc_block_list[61],
  43680         soc_iprocreg,
  43681         1,
  43682         0,
  43683         0x180213a4,
  43684         0,
  43685         0,
  43686         1,
  43687         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88375_A0r_fields,
  43688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43689         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43690         -1,
  43691         -1,
  43692     },
  43693 #endif /* chips */
  43694 
  43695 #if defined(BCM_88375_B0)
  43696     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88375_B0r */
  43697         soc_block_list[61],
  43698         soc_iprocreg,
  43699         1,
  43700         0,
  43701         0x180213a4,
  43702         0,
  43703         0,
  43704         1,
  43705         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88375_B0r_fields,
  43706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43707         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43708         -1,
  43709         -1,
  43710     },
  43711 #endif /* chips */
  43712 
  43713 #if defined(BCM_88470_A0)
  43714     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88470_A0r */
  43715         soc_block_list[61],
  43716         soc_iprocreg,
  43717         1,
  43718         0,
  43719         0x180213a4,
  43720         0,
  43721         0,
  43722         1,
  43723         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88470_A0r_fields,
  43724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43725         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43726         -1,
  43727         -1,
  43728     },
  43729 #endif /* chips */
  43730 
  43731 #if defined(BCM_88470_B0)
  43732     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88470_B0r */
  43733         soc_block_list[61],
  43734         soc_iprocreg,
  43735         1,
  43736         0,
  43737         0x180213a4,
  43738         0,
  43739         0,
  43740         1,
  43741         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88470_B0r_fields,
  43742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43743         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43744         -1,
  43745         -1,
  43746     },
  43747 #endif /* chips */
  43748 
  43749 #if defined(BCM_88675_B0)
  43750     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88675_B0r */
  43751         soc_block_list[61],
  43752         soc_iprocreg,
  43753         1,
  43754         0,
  43755         0x180213a4,
  43756         0,
  43757         0,
  43758         1,
  43759         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88675_B0r_fields,
  43760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43761         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43762         -1,
  43763         -1,
  43764     },
  43765 #endif /* chips */
  43766 
  43767 #if defined(BCM_88680_A0)
  43768     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88680_A0r */
  43769         soc_block_list[61],
  43770         soc_iprocreg,
  43771         1,
  43772         0,
  43773         0x180213a4,
  43774         0,
  43775         0,
  43776         1,
  43777         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88680_A0r_fields,
  43778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43779         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43780         -1,
  43781         -1,
  43782     },
  43783 #endif /* chips */
  43784 
  43785 #if defined(BCM_88690_A0)
  43786     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88690_A0r */
  43787         soc_block_list[61],
  43788         soc_iprocreg,
  43789         1,
  43790         0,
  43791         0x180213a4,
  43792         0,
  43793         0,
  43794         1,
  43795         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88690_A0r_fields,
  43796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43797         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43798         -1,
  43799         -1,
  43800     },
  43801 #endif /* chips */
  43802 
  43803 #if defined(BCM_88690_B0)
  43804     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88690_B0r */
  43805         soc_block_list[61],
  43806         soc_iprocreg,
  43807         1,
  43808         0,
  43809         0x180213a4,
  43810         0,
  43811         0,
  43812         1,
  43813         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88690_B0r_fields,
  43814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43815         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43816         -1,
  43817         -1,
  43818     },
  43819 #endif /* chips */
  43820 
  43821 #if defined(BCM_88790_A0)
  43822     { /* SOC_REG_INT_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88790_A0r */
  43823         soc_block_list[61],
  43824         soc_iprocreg,
  43825         1,
  43826         0,
  43827         0x180213a4,
  43828         0,
  43829         0,
  43830         1,
  43831         soc_QSPI_RAF_INTERRUPT_LR_TRUNCATED_BCM88790_A0r_fields,
  43832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43833         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  43834         -1,
  43835         -1,
  43836     },
  43837 #endif /* chips */
  43838 
  43839 #if defined(BCM_88675_A0)
  43840     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDSr */
  43841         soc_block_list[61],
  43842         soc_iprocreg,
  43843         1,
  43844         0,
  43845         0x18021104,
  43846         0,
  43847         0,
  43848         1,
  43849         soc_QSPI_RAF_NUM_WORDSr_fields,
  43850         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43851         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43852         -1,
  43853         -1,
  43854     },
  43855 #endif /* chips */
  43856 
  43857 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  43858     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  43859     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  43860     defined(BCM_56260_B0)
  43861     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM53400_A0r */
  43862         soc_block_list[61],
  43863         soc_iprocreg,
  43864         1,
  43865         0,
  43866         0x18047104,
  43867         0,
  43868         0,
  43869         1,
  43870         soc_QSPI_RAF_NUM_WORDS_BCM53400_A0r_fields,
  43871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43872         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43873         -1,
  43874         -1,
  43875     },
  43876 #endif /* chips */
  43877 
  43878 #if defined(BCM_56370_A0)
  43879     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM56370_A0r */
  43880         soc_block_list[61],
  43881         soc_iprocreg,
  43882         1,
  43883         0,
  43884         0x15000104,
  43885         0,
  43886         0,
  43887         1,
  43888         soc_QSPI_RAF_NUM_WORDS_BCM53400_A0r_fields,
  43889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43890         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43891         -1,
  43892         -1,
  43893         3,
  43894     },
  43895 #endif /* chips */
  43896 
  43897 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  43898     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  43899     defined(BCM_56450_B1)
  43900     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM56450_A0r */
  43901         soc_block_list[61],
  43902         soc_iprocreg,
  43903         1,
  43904         0,
  43905         0x18027104,
  43906         0,
  43907         0,
  43908         1,
  43909         soc_QSPI_RAF_NUM_WORDS_BCM56450_A0r_fields,
  43910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43912         -1,
  43913         -1,
  43914     },
  43915 #endif /* chips */
  43916 
  43917 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  43918     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  43919     defined(BCM_56670_B0)
  43920     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM56560_A0r */
  43921         soc_block_list[61],
  43922         soc_iprocreg,
  43923         1,
  43924         0,
  43925         0x18021104,
  43926         0,
  43927         0,
  43928         1,
  43929         soc_QSPI_RAF_NUM_WORDS_BCM53400_A0r_fields,
  43930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43931         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43932         -1,
  43933         -1,
  43934     },
  43935 #endif /* chips */
  43936 
  43937 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  43938     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  43939     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  43940     defined(BCM_56980_B0)
  43941     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM56960_A0r */
  43942         soc_block_list[61],
  43943         soc_iprocreg,
  43944         1,
  43945         0,
  43946         0x18021104,
  43947         0,
  43948         0,
  43949         1,
  43950         soc_QSPI_RAF_NUM_WORDS_BCM53400_A0r_fields,
  43951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43952         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43953         -1,
  43954         -1,
  43955         3,
  43956     },
  43957 #endif /* chips */
  43958 
  43959 #if defined(BCM_88270_A0)
  43960     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM88270_A0r */
  43961         soc_block_list[61],
  43962         soc_iprocreg,
  43963         1,
  43964         0,
  43965         0x18021104,
  43966         0,
  43967         0,
  43968         1,
  43969         soc_QSPI_RAF_NUM_WORDS_BCM88270_A0r_fields,
  43970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43971         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43972         -1,
  43973         -1,
  43974     },
  43975 #endif /* chips */
  43976 
  43977 #if defined(BCM_88375_A0)
  43978     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM88375_A0r */
  43979         soc_block_list[61],
  43980         soc_iprocreg,
  43981         1,
  43982         0,
  43983         0x18021104,
  43984         0,
  43985         0,
  43986         1,
  43987         soc_QSPI_RAF_NUM_WORDS_BCM88375_A0r_fields,
  43988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43989         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  43990         -1,
  43991         -1,
  43992     },
  43993 #endif /* chips */
  43994 
  43995 #if defined(BCM_88375_B0)
  43996     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM88375_B0r */
  43997         soc_block_list[61],
  43998         soc_iprocreg,
  43999         1,
  44000         0,
  44001         0x18021104,
  44002         0,
  44003         0,
  44004         1,
  44005         soc_QSPI_RAF_NUM_WORDS_BCM88375_B0r_fields,
  44006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44007         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44008         -1,
  44009         -1,
  44010     },
  44011 #endif /* chips */
  44012 
  44013 #if defined(BCM_88470_A0)
  44014     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM88470_A0r */
  44015         soc_block_list[61],
  44016         soc_iprocreg,
  44017         1,
  44018         0,
  44019         0x18021104,
  44020         0,
  44021         0,
  44022         1,
  44023         soc_QSPI_RAF_NUM_WORDS_BCM88470_A0r_fields,
  44024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44025         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44026         -1,
  44027         -1,
  44028     },
  44029 #endif /* chips */
  44030 
  44031 #if defined(BCM_88470_B0)
  44032     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM88470_B0r */
  44033         soc_block_list[61],
  44034         soc_iprocreg,
  44035         1,
  44036         0,
  44037         0x18021104,
  44038         0,
  44039         0,
  44040         1,
  44041         soc_QSPI_RAF_NUM_WORDS_BCM88470_B0r_fields,
  44042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44043         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44044         -1,
  44045         -1,
  44046     },
  44047 #endif /* chips */
  44048 
  44049 #if defined(BCM_88675_B0)
  44050     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM88675_B0r */
  44051         soc_block_list[61],
  44052         soc_iprocreg,
  44053         1,
  44054         0,
  44055         0x18021104,
  44056         0,
  44057         0,
  44058         1,
  44059         soc_QSPI_RAF_NUM_WORDS_BCM88675_B0r_fields,
  44060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44061         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44062         -1,
  44063         -1,
  44064     },
  44065 #endif /* chips */
  44066 
  44067 #if defined(BCM_88680_A0)
  44068     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM88680_A0r */
  44069         soc_block_list[61],
  44070         soc_iprocreg,
  44071         1,
  44072         0,
  44073         0x18021104,
  44074         0,
  44075         0,
  44076         1,
  44077         soc_QSPI_RAF_NUM_WORDS_BCM88680_A0r_fields,
  44078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44079         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44080         -1,
  44081         -1,
  44082     },
  44083 #endif /* chips */
  44084 
  44085 #if defined(BCM_88690_A0)
  44086     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM88690_A0r */
  44087         soc_block_list[61],
  44088         soc_iprocreg,
  44089         1,
  44090         0,
  44091         0x18021104,
  44092         0,
  44093         0,
  44094         1,
  44095         soc_QSPI_RAF_NUM_WORDS_BCM88690_A0r_fields,
  44096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44098         -1,
  44099         -1,
  44100     },
  44101 #endif /* chips */
  44102 
  44103 #if defined(BCM_88690_B0)
  44104     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM88690_B0r */
  44105         soc_block_list[61],
  44106         soc_iprocreg,
  44107         1,
  44108         0,
  44109         0x18021104,
  44110         0,
  44111         0,
  44112         1,
  44113         soc_QSPI_RAF_NUM_WORDS_BCM88690_B0r_fields,
  44114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44116         -1,
  44117         -1,
  44118     },
  44119 #endif /* chips */
  44120 
  44121 #if defined(BCM_88790_A0)
  44122     { /* SOC_REG_INT_QSPI_RAF_NUM_WORDS_BCM88790_A0r */
  44123         soc_block_list[61],
  44124         soc_iprocreg,
  44125         1,
  44126         0,
  44127         0x18021104,
  44128         0,
  44129         0,
  44130         1,
  44131         soc_QSPI_RAF_NUM_WORDS_BCM88790_A0r_fields,
  44132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44133         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44134         -1,
  44135         -1,
  44136     },
  44137 #endif /* chips */
  44138 
  44139 #if defined(BCM_88675_A0)
  44140     { /* SOC_REG_INT_QSPI_RAF_READ_DATAr */
  44141         soc_block_list[61],
  44142         soc_iprocreg,
  44143         1,
  44144         0,
  44145         0x18021118,
  44146         SOC_REG_FLAG_RO,
  44147         0,
  44148         1,
  44149         soc_QSPI_RAF_READ_DATAr_fields,
  44150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44151         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44152         -1,
  44153         -1,
  44154     },
  44155 #endif /* chips */
  44156 
  44157 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  44158     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  44159     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  44160     defined(BCM_56260_B0)
  44161     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM53400_A0r */
  44162         soc_block_list[61],
  44163         soc_iprocreg,
  44164         1,
  44165         0,
  44166         0x18047118,
  44167         SOC_REG_FLAG_RO,
  44168         0,
  44169         1,
  44170         soc_CMIC_BS0_INPUT_TIME_0_BCM53400_A0r_fields,
  44171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44172         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44173         -1,
  44174         -1,
  44175     },
  44176 #endif /* chips */
  44177 
  44178 #if defined(BCM_56370_A0)
  44179     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM56370_A0r */
  44180         soc_block_list[61],
  44181         soc_iprocreg,
  44182         1,
  44183         0,
  44184         0x15000118,
  44185         SOC_REG_FLAG_RO,
  44186         0,
  44187         1,
  44188         soc_CMIC_BS0_INPUT_TIME_0_BCM53400_A0r_fields,
  44189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44190         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44191         -1,
  44192         -1,
  44193         3,
  44194     },
  44195 #endif /* chips */
  44196 
  44197 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  44198     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44199     defined(BCM_56450_B1)
  44200     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM56450_A0r */
  44201         soc_block_list[61],
  44202         soc_iprocreg,
  44203         1,
  44204         0,
  44205         0x18027118,
  44206         SOC_REG_FLAG_RO,
  44207         0,
  44208         1,
  44209         soc_CMIC_BS_INPUT_TIME_0_BCM56640_A0r_fields,
  44210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44211         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44212         -1,
  44213         -1,
  44214     },
  44215 #endif /* chips */
  44216 
  44217 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  44218     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  44219     defined(BCM_56670_B0)
  44220     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM56560_A0r */
  44221         soc_block_list[61],
  44222         soc_iprocreg,
  44223         1,
  44224         0,
  44225         0x18021118,
  44226         SOC_REG_FLAG_RO,
  44227         0,
  44228         1,
  44229         soc_CMIC_BS0_INPUT_TIME_0_BCM53400_A0r_fields,
  44230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44231         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44232         -1,
  44233         -1,
  44234     },
  44235 #endif /* chips */
  44236 
  44237 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  44238     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  44239     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  44240     defined(BCM_56980_B0)
  44241     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM56960_A0r */
  44242         soc_block_list[61],
  44243         soc_iprocreg,
  44244         1,
  44245         0,
  44246         0x18021118,
  44247         SOC_REG_FLAG_RO,
  44248         0,
  44249         1,
  44250         soc_CMIC_BS0_INPUT_TIME_0_BCM53400_A0r_fields,
  44251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44252         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44253         -1,
  44254         -1,
  44255         3,
  44256     },
  44257 #endif /* chips */
  44258 
  44259 #if defined(BCM_88270_A0)
  44260     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM88270_A0r */
  44261         soc_block_list[61],
  44262         soc_iprocreg,
  44263         1,
  44264         0,
  44265         0x18021118,
  44266         SOC_REG_FLAG_RO,
  44267         0,
  44268         1,
  44269         soc_QSPI_RAF_READ_DATA_BCM88270_A0r_fields,
  44270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44271         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44272         -1,
  44273         -1,
  44274     },
  44275 #endif /* chips */
  44276 
  44277 #if defined(BCM_88375_A0)
  44278     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM88375_A0r */
  44279         soc_block_list[61],
  44280         soc_iprocreg,
  44281         1,
  44282         0,
  44283         0x18021118,
  44284         SOC_REG_FLAG_RO,
  44285         0,
  44286         1,
  44287         soc_QSPI_RAF_READ_DATA_BCM88375_A0r_fields,
  44288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44289         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44290         -1,
  44291         -1,
  44292     },
  44293 #endif /* chips */
  44294 
  44295 #if defined(BCM_88375_B0)
  44296     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM88375_B0r */
  44297         soc_block_list[61],
  44298         soc_iprocreg,
  44299         1,
  44300         0,
  44301         0x18021118,
  44302         SOC_REG_FLAG_RO,
  44303         0,
  44304         1,
  44305         soc_QSPI_RAF_READ_DATA_BCM88375_B0r_fields,
  44306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44307         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44308         -1,
  44309         -1,
  44310     },
  44311 #endif /* chips */
  44312 
  44313 #if defined(BCM_88470_A0)
  44314     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM88470_A0r */
  44315         soc_block_list[61],
  44316         soc_iprocreg,
  44317         1,
  44318         0,
  44319         0x18021118,
  44320         SOC_REG_FLAG_RO,
  44321         0,
  44322         1,
  44323         soc_QSPI_RAF_READ_DATA_BCM88470_A0r_fields,
  44324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44325         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44326         -1,
  44327         -1,
  44328     },
  44329 #endif /* chips */
  44330 
  44331 #if defined(BCM_88470_B0)
  44332     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM88470_B0r */
  44333         soc_block_list[61],
  44334         soc_iprocreg,
  44335         1,
  44336         0,
  44337         0x18021118,
  44338         SOC_REG_FLAG_RO,
  44339         0,
  44340         1,
  44341         soc_QSPI_RAF_READ_DATA_BCM88470_B0r_fields,
  44342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44343         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44344         -1,
  44345         -1,
  44346     },
  44347 #endif /* chips */
  44348 
  44349 #if defined(BCM_88675_B0)
  44350     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM88675_B0r */
  44351         soc_block_list[61],
  44352         soc_iprocreg,
  44353         1,
  44354         0,
  44355         0x18021118,
  44356         SOC_REG_FLAG_RO,
  44357         0,
  44358         1,
  44359         soc_QSPI_RAF_READ_DATA_BCM88675_B0r_fields,
  44360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44361         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44362         -1,
  44363         -1,
  44364     },
  44365 #endif /* chips */
  44366 
  44367 #if defined(BCM_88680_A0)
  44368     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM88680_A0r */
  44369         soc_block_list[61],
  44370         soc_iprocreg,
  44371         1,
  44372         0,
  44373         0x18021118,
  44374         SOC_REG_FLAG_RO,
  44375         0,
  44376         1,
  44377         soc_QSPI_RAF_READ_DATA_BCM88680_A0r_fields,
  44378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44379         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44380         -1,
  44381         -1,
  44382     },
  44383 #endif /* chips */
  44384 
  44385 #if defined(BCM_88690_A0)
  44386     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM88690_A0r */
  44387         soc_block_list[61],
  44388         soc_iprocreg,
  44389         1,
  44390         0,
  44391         0x18021118,
  44392         SOC_REG_FLAG_RO,
  44393         0,
  44394         1,
  44395         soc_QSPI_RAF_READ_DATA_BCM88690_A0r_fields,
  44396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44397         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44398         -1,
  44399         -1,
  44400     },
  44401 #endif /* chips */
  44402 
  44403 #if defined(BCM_88690_B0)
  44404     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM88690_B0r */
  44405         soc_block_list[61],
  44406         soc_iprocreg,
  44407         1,
  44408         0,
  44409         0x18021118,
  44410         SOC_REG_FLAG_RO,
  44411         0,
  44412         1,
  44413         soc_QSPI_RAF_READ_DATA_BCM88690_B0r_fields,
  44414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44416         -1,
  44417         -1,
  44418     },
  44419 #endif /* chips */
  44420 
  44421 #if defined(BCM_88790_A0)
  44422     { /* SOC_REG_INT_QSPI_RAF_READ_DATA_BCM88790_A0r */
  44423         soc_block_list[61],
  44424         soc_iprocreg,
  44425         1,
  44426         0,
  44427         0x18021118,
  44428         SOC_REG_FLAG_RO,
  44429         0,
  44430         1,
  44431         soc_QSPI_RAF_READ_DATA_BCM88790_A0r_fields,
  44432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44433         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44434         -1,
  44435         -1,
  44436     },
  44437 #endif /* chips */
  44438 
  44439 #if defined(BCM_88675_A0)
  44440     { /* SOC_REG_INT_QSPI_RAF_START_ADDRr */
  44441         soc_block_list[61],
  44442         soc_iprocreg,
  44443         1,
  44444         0,
  44445         0x18021100,
  44446         0,
  44447         0,
  44448         1,
  44449         soc_QSPI_RAF_START_ADDRr_fields,
  44450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44451         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44452         -1,
  44453         -1,
  44454     },
  44455 #endif /* chips */
  44456 
  44457 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  44458     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  44459     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  44460     defined(BCM_56260_B0)
  44461     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM53400_A0r */
  44462         soc_block_list[61],
  44463         soc_iprocreg,
  44464         1,
  44465         0,
  44466         0x18047100,
  44467         0,
  44468         0,
  44469         1,
  44470         soc_QSPI_RAF_START_ADDR_BCM53400_A0r_fields,
  44471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44472         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44473         -1,
  44474         -1,
  44475     },
  44476 #endif /* chips */
  44477 
  44478 #if defined(BCM_56370_A0)
  44479     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM56370_A0r */
  44480         soc_block_list[61],
  44481         soc_iprocreg,
  44482         1,
  44483         0,
  44484         0x15000100,
  44485         0,
  44486         0,
  44487         1,
  44488         soc_QSPI_RAF_START_ADDR_BCM53400_A0r_fields,
  44489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44490         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44491         -1,
  44492         -1,
  44493         3,
  44494     },
  44495 #endif /* chips */
  44496 
  44497 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  44498     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44499     defined(BCM_56450_B1)
  44500     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM56450_A0r */
  44501         soc_block_list[61],
  44502         soc_iprocreg,
  44503         1,
  44504         0,
  44505         0x18027100,
  44506         0,
  44507         0,
  44508         1,
  44509         soc_CMIC_SER0_START_ADDR_0_BCM56640_A0r_fields,
  44510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44511         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44512         -1,
  44513         -1,
  44514     },
  44515 #endif /* chips */
  44516 
  44517 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  44518     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  44519     defined(BCM_56670_B0)
  44520     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM56560_A0r */
  44521         soc_block_list[61],
  44522         soc_iprocreg,
  44523         1,
  44524         0,
  44525         0x18021100,
  44526         0,
  44527         0,
  44528         1,
  44529         soc_QSPI_RAF_START_ADDR_BCM53400_A0r_fields,
  44530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44531         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44532         -1,
  44533         -1,
  44534     },
  44535 #endif /* chips */
  44536 
  44537 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  44538     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  44539     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  44540     defined(BCM_56980_B0)
  44541     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM56960_A0r */
  44542         soc_block_list[61],
  44543         soc_iprocreg,
  44544         1,
  44545         0,
  44546         0x18021100,
  44547         0,
  44548         0,
  44549         1,
  44550         soc_QSPI_RAF_START_ADDR_BCM53400_A0r_fields,
  44551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44552         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44553         -1,
  44554         -1,
  44555         3,
  44556     },
  44557 #endif /* chips */
  44558 
  44559 #if defined(BCM_88270_A0)
  44560     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM88270_A0r */
  44561         soc_block_list[61],
  44562         soc_iprocreg,
  44563         1,
  44564         0,
  44565         0x18021100,
  44566         0,
  44567         0,
  44568         1,
  44569         soc_QSPI_RAF_START_ADDR_BCM88270_A0r_fields,
  44570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44571         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44572         -1,
  44573         -1,
  44574     },
  44575 #endif /* chips */
  44576 
  44577 #if defined(BCM_88375_A0)
  44578     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM88375_A0r */
  44579         soc_block_list[61],
  44580         soc_iprocreg,
  44581         1,
  44582         0,
  44583         0x18021100,
  44584         0,
  44585         0,
  44586         1,
  44587         soc_QSPI_RAF_START_ADDR_BCM88375_A0r_fields,
  44588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44589         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44590         -1,
  44591         -1,
  44592     },
  44593 #endif /* chips */
  44594 
  44595 #if defined(BCM_88375_B0)
  44596     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM88375_B0r */
  44597         soc_block_list[61],
  44598         soc_iprocreg,
  44599         1,
  44600         0,
  44601         0x18021100,
  44602         0,
  44603         0,
  44604         1,
  44605         soc_QSPI_RAF_START_ADDR_BCM88375_B0r_fields,
  44606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44607         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44608         -1,
  44609         -1,
  44610     },
  44611 #endif /* chips */
  44612 
  44613 #if defined(BCM_88470_A0)
  44614     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM88470_A0r */
  44615         soc_block_list[61],
  44616         soc_iprocreg,
  44617         1,
  44618         0,
  44619         0x18021100,
  44620         0,
  44621         0,
  44622         1,
  44623         soc_QSPI_RAF_START_ADDR_BCM88470_A0r_fields,
  44624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44625         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44626         -1,
  44627         -1,
  44628     },
  44629 #endif /* chips */
  44630 
  44631 #if defined(BCM_88470_B0)
  44632     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM88470_B0r */
  44633         soc_block_list[61],
  44634         soc_iprocreg,
  44635         1,
  44636         0,
  44637         0x18021100,
  44638         0,
  44639         0,
  44640         1,
  44641         soc_QSPI_RAF_START_ADDR_BCM88470_B0r_fields,
  44642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44643         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44644         -1,
  44645         -1,
  44646     },
  44647 #endif /* chips */
  44648 
  44649 #if defined(BCM_88675_B0)
  44650     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM88675_B0r */
  44651         soc_block_list[61],
  44652         soc_iprocreg,
  44653         1,
  44654         0,
  44655         0x18021100,
  44656         0,
  44657         0,
  44658         1,
  44659         soc_QSPI_RAF_START_ADDR_BCM88675_B0r_fields,
  44660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44661         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44662         -1,
  44663         -1,
  44664     },
  44665 #endif /* chips */
  44666 
  44667 #if defined(BCM_88680_A0)
  44668     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM88680_A0r */
  44669         soc_block_list[61],
  44670         soc_iprocreg,
  44671         1,
  44672         0,
  44673         0x18021100,
  44674         0,
  44675         0,
  44676         1,
  44677         soc_QSPI_RAF_START_ADDR_BCM88680_A0r_fields,
  44678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44680         -1,
  44681         -1,
  44682     },
  44683 #endif /* chips */
  44684 
  44685 #if defined(BCM_88690_A0)
  44686     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM88690_A0r */
  44687         soc_block_list[61],
  44688         soc_iprocreg,
  44689         1,
  44690         0,
  44691         0x18021100,
  44692         0,
  44693         0,
  44694         1,
  44695         soc_QSPI_RAF_START_ADDR_BCM88690_A0r_fields,
  44696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44698         -1,
  44699         -1,
  44700     },
  44701 #endif /* chips */
  44702 
  44703 #if defined(BCM_88690_B0)
  44704     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM88690_B0r */
  44705         soc_block_list[61],
  44706         soc_iprocreg,
  44707         1,
  44708         0,
  44709         0x18021100,
  44710         0,
  44711         0,
  44712         1,
  44713         soc_QSPI_RAF_START_ADDR_BCM88690_B0r_fields,
  44714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44715         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44716         -1,
  44717         -1,
  44718     },
  44719 #endif /* chips */
  44720 
  44721 #if defined(BCM_88790_A0)
  44722     { /* SOC_REG_INT_QSPI_RAF_START_ADDR_BCM88790_A0r */
  44723         soc_block_list[61],
  44724         soc_iprocreg,
  44725         1,
  44726         0,
  44727         0x18021100,
  44728         0,
  44729         0,
  44730         1,
  44731         soc_QSPI_RAF_START_ADDR_BCM88790_A0r_fields,
  44732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44733         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44734         -1,
  44735         -1,
  44736     },
  44737 #endif /* chips */
  44738 
  44739 #if defined(BCM_88675_A0)
  44740     { /* SOC_REG_INT_QSPI_RAF_STATUSr */
  44741         soc_block_list[61],
  44742         soc_iprocreg,
  44743         1,
  44744         0,
  44745         0x18021114,
  44746         SOC_REG_FLAG_RO,
  44747         0,
  44748         4,
  44749         soc_QSPI_RAF_STATUSr_fields,
  44750         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44751         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44752         -1,
  44753         -1,
  44754     },
  44755 #endif /* chips */
  44756 
  44757 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  44758     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  44759     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  44760     defined(BCM_56260_B0)
  44761     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM53400_A0r */
  44762         soc_block_list[61],
  44763         soc_iprocreg,
  44764         1,
  44765         0,
  44766         0x18047114,
  44767         SOC_REG_FLAG_RO,
  44768         0,
  44769         4,
  44770         soc_QSPI_RAF_STATUS_BCM53400_A0r_fields,
  44771         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44772         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44773         -1,
  44774         -1,
  44775     },
  44776 #endif /* chips */
  44777 
  44778 #if defined(BCM_56370_A0)
  44779     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM56370_A0r */
  44780         soc_block_list[61],
  44781         soc_iprocreg,
  44782         1,
  44783         0,
  44784         0x15000114,
  44785         SOC_REG_FLAG_RO,
  44786         0,
  44787         4,
  44788         soc_QSPI_RAF_STATUS_BCM53400_A0r_fields,
  44789         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44790         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44791         -1,
  44792         -1,
  44793         3,
  44794     },
  44795 #endif /* chips */
  44796 
  44797 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  44798     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  44799     defined(BCM_56450_B1)
  44800     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM56450_A0r */
  44801         soc_block_list[61],
  44802         soc_iprocreg,
  44803         1,
  44804         0,
  44805         0x18027114,
  44806         SOC_REG_FLAG_RO,
  44807         0,
  44808         4,
  44809         soc_QSPI_RAF_STATUS_BCM56450_A0r_fields,
  44810         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44811         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44812         -1,
  44813         -1,
  44814     },
  44815 #endif /* chips */
  44816 
  44817 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  44818     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  44819     defined(BCM_56670_B0)
  44820     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM56560_A0r */
  44821         soc_block_list[61],
  44822         soc_iprocreg,
  44823         1,
  44824         0,
  44825         0x18021114,
  44826         SOC_REG_FLAG_RO,
  44827         0,
  44828         4,
  44829         soc_QSPI_RAF_STATUS_BCM53400_A0r_fields,
  44830         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44831         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44832         -1,
  44833         -1,
  44834     },
  44835 #endif /* chips */
  44836 
  44837 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  44838     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  44839     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  44840     defined(BCM_56980_B0)
  44841     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM56960_A0r */
  44842         soc_block_list[61],
  44843         soc_iprocreg,
  44844         1,
  44845         0,
  44846         0x18021114,
  44847         SOC_REG_FLAG_RO,
  44848         0,
  44849         4,
  44850         soc_QSPI_RAF_STATUS_BCM53400_A0r_fields,
  44851         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44852         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44853         -1,
  44854         -1,
  44855         3,
  44856     },
  44857 #endif /* chips */
  44858 
  44859 #if defined(BCM_88270_A0)
  44860     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM88270_A0r */
  44861         soc_block_list[61],
  44862         soc_iprocreg,
  44863         1,
  44864         0,
  44865         0x18021114,
  44866         SOC_REG_FLAG_RO,
  44867         0,
  44868         4,
  44869         soc_QSPI_RAF_STATUS_BCM88270_A0r_fields,
  44870         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44871         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44872         -1,
  44873         -1,
  44874     },
  44875 #endif /* chips */
  44876 
  44877 #if defined(BCM_88375_A0)
  44878     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM88375_A0r */
  44879         soc_block_list[61],
  44880         soc_iprocreg,
  44881         1,
  44882         0,
  44883         0x18021114,
  44884         SOC_REG_FLAG_RO,
  44885         0,
  44886         4,
  44887         soc_QSPI_RAF_STATUS_BCM88375_A0r_fields,
  44888         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44889         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44890         -1,
  44891         -1,
  44892     },
  44893 #endif /* chips */
  44894 
  44895 #if defined(BCM_88375_B0)
  44896     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM88375_B0r */
  44897         soc_block_list[61],
  44898         soc_iprocreg,
  44899         1,
  44900         0,
  44901         0x18021114,
  44902         SOC_REG_FLAG_RO,
  44903         0,
  44904         4,
  44905         soc_QSPI_RAF_STATUS_BCM88375_B0r_fields,
  44906         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44907         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44908         -1,
  44909         -1,
  44910     },
  44911 #endif /* chips */
  44912 
  44913 #if defined(BCM_88470_A0)
  44914     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM88470_A0r */
  44915         soc_block_list[61],
  44916         soc_iprocreg,
  44917         1,
  44918         0,
  44919         0x18021114,
  44920         SOC_REG_FLAG_RO,
  44921         0,
  44922         4,
  44923         soc_QSPI_RAF_STATUS_BCM88470_A0r_fields,
  44924         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44925         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44926         -1,
  44927         -1,
  44928     },
  44929 #endif /* chips */
  44930 
  44931 #if defined(BCM_88470_B0)
  44932     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM88470_B0r */
  44933         soc_block_list[61],
  44934         soc_iprocreg,
  44935         1,
  44936         0,
  44937         0x18021114,
  44938         SOC_REG_FLAG_RO,
  44939         0,
  44940         4,
  44941         soc_QSPI_RAF_STATUS_BCM88470_B0r_fields,
  44942         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44943         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44944         -1,
  44945         -1,
  44946     },
  44947 #endif /* chips */
  44948 
  44949 #if defined(BCM_88675_B0)
  44950     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM88675_B0r */
  44951         soc_block_list[61],
  44952         soc_iprocreg,
  44953         1,
  44954         0,
  44955         0x18021114,
  44956         SOC_REG_FLAG_RO,
  44957         0,
  44958         4,
  44959         soc_QSPI_RAF_STATUS_BCM88675_B0r_fields,
  44960         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44961         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44962         -1,
  44963         -1,
  44964     },
  44965 #endif /* chips */
  44966 
  44967 #if defined(BCM_88680_A0)
  44968     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM88680_A0r */
  44969         soc_block_list[61],
  44970         soc_iprocreg,
  44971         1,
  44972         0,
  44973         0x18021114,
  44974         SOC_REG_FLAG_RO,
  44975         0,
  44976         4,
  44977         soc_QSPI_RAF_STATUS_BCM88680_A0r_fields,
  44978         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44979         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44980         -1,
  44981         -1,
  44982     },
  44983 #endif /* chips */
  44984 
  44985 #if defined(BCM_88690_A0)
  44986     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM88690_A0r */
  44987         soc_block_list[61],
  44988         soc_iprocreg,
  44989         1,
  44990         0,
  44991         0x18021114,
  44992         SOC_REG_FLAG_RO,
  44993         0,
  44994         4,
  44995         soc_QSPI_RAF_STATUS_BCM88690_A0r_fields,
  44996         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  44997         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44998         -1,
  44999         -1,
  45000     },
  45001 #endif /* chips */
  45002 
  45003 #if defined(BCM_88690_B0)
  45004     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM88690_B0r */
  45005         soc_block_list[61],
  45006         soc_iprocreg,
  45007         1,
  45008         0,
  45009         0x18021114,
  45010         SOC_REG_FLAG_RO,
  45011         0,
  45012         4,
  45013         soc_QSPI_RAF_STATUS_BCM88690_B0r_fields,
  45014         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  45015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45016         -1,
  45017         -1,
  45018     },
  45019 #endif /* chips */
  45020 
  45021 #if defined(BCM_88790_A0)
  45022     { /* SOC_REG_INT_QSPI_RAF_STATUS_BCM88790_A0r */
  45023         soc_block_list[61],
  45024         soc_iprocreg,
  45025         1,
  45026         0,
  45027         0x18021114,
  45028         SOC_REG_FLAG_RO,
  45029         0,
  45030         4,
  45031         soc_QSPI_RAF_STATUS_BCM88790_A0r_fields,
  45032         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  45033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45034         -1,
  45035         -1,
  45036     },
  45037 #endif /* chips */
  45038 
  45039 #if defined(BCM_88675_A0)
  45040     { /* SOC_REG_INT_QSPI_RAF_WATERMARKr */
  45041         soc_block_list[61],
  45042         soc_iprocreg,
  45043         1,
  45044         0,
  45045         0x18021110,
  45046         0,
  45047         0,
  45048         2,
  45049         soc_QSPI_RAF_WATERMARKr_fields,
  45050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45051         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45052         -1,
  45053         -1,
  45054     },
  45055 #endif /* chips */
  45056 
  45057 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  45058     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  45059     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  45060     defined(BCM_56260_B0)
  45061     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM53400_A0r */
  45062         soc_block_list[61],
  45063         soc_iprocreg,
  45064         1,
  45065         0,
  45066         0x18047110,
  45067         0,
  45068         0,
  45069         2,
  45070         soc_QSPI_RAF_WATERMARK_BCM53400_A0r_fields,
  45071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45072         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45073         -1,
  45074         -1,
  45075     },
  45076 #endif /* chips */
  45077 
  45078 #if defined(BCM_56370_A0)
  45079     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM56370_A0r */
  45080         soc_block_list[61],
  45081         soc_iprocreg,
  45082         1,
  45083         0,
  45084         0x15000110,
  45085         0,
  45086         0,
  45087         2,
  45088         soc_QSPI_RAF_WATERMARK_BCM53400_A0r_fields,
  45089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45090         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45091         -1,
  45092         -1,
  45093         3,
  45094     },
  45095 #endif /* chips */
  45096 
  45097 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  45098     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45099     defined(BCM_56450_B1)
  45100     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM56450_A0r */
  45101         soc_block_list[61],
  45102         soc_iprocreg,
  45103         1,
  45104         0,
  45105         0x18027110,
  45106         0,
  45107         0,
  45108         2,
  45109         soc_QSPI_RAF_WATERMARK_BCM56450_A0r_fields,
  45110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45111         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45112         -1,
  45113         -1,
  45114     },
  45115 #endif /* chips */
  45116 
  45117 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  45118     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  45119     defined(BCM_56670_B0)
  45120     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM56560_A0r */
  45121         soc_block_list[61],
  45122         soc_iprocreg,
  45123         1,
  45124         0,
  45125         0x18021110,
  45126         0,
  45127         0,
  45128         2,
  45129         soc_QSPI_RAF_WATERMARK_BCM53400_A0r_fields,
  45130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45132         -1,
  45133         -1,
  45134     },
  45135 #endif /* chips */
  45136 
  45137 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  45138     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  45139     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  45140     defined(BCM_56980_B0)
  45141     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM56960_A0r */
  45142         soc_block_list[61],
  45143         soc_iprocreg,
  45144         1,
  45145         0,
  45146         0x18021110,
  45147         0,
  45148         0,
  45149         2,
  45150         soc_QSPI_RAF_WATERMARK_BCM53400_A0r_fields,
  45151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45152         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45153         -1,
  45154         -1,
  45155         3,
  45156     },
  45157 #endif /* chips */
  45158 
  45159 #if defined(BCM_88270_A0)
  45160     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM88270_A0r */
  45161         soc_block_list[61],
  45162         soc_iprocreg,
  45163         1,
  45164         0,
  45165         0x18021110,
  45166         0,
  45167         0,
  45168         2,
  45169         soc_QSPI_RAF_WATERMARK_BCM88270_A0r_fields,
  45170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45171         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45172         -1,
  45173         -1,
  45174     },
  45175 #endif /* chips */
  45176 
  45177 #if defined(BCM_88375_A0)
  45178     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM88375_A0r */
  45179         soc_block_list[61],
  45180         soc_iprocreg,
  45181         1,
  45182         0,
  45183         0x18021110,
  45184         0,
  45185         0,
  45186         2,
  45187         soc_QSPI_RAF_WATERMARK_BCM88375_A0r_fields,
  45188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45189         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45190         -1,
  45191         -1,
  45192     },
  45193 #endif /* chips */
  45194 
  45195 #if defined(BCM_88375_B0)
  45196     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM88375_B0r */
  45197         soc_block_list[61],
  45198         soc_iprocreg,
  45199         1,
  45200         0,
  45201         0x18021110,
  45202         0,
  45203         0,
  45204         2,
  45205         soc_QSPI_RAF_WATERMARK_BCM88375_B0r_fields,
  45206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45207         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45208         -1,
  45209         -1,
  45210     },
  45211 #endif /* chips */
  45212 
  45213 #if defined(BCM_88470_A0)
  45214     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM88470_A0r */
  45215         soc_block_list[61],
  45216         soc_iprocreg,
  45217         1,
  45218         0,
  45219         0x18021110,
  45220         0,
  45221         0,
  45222         2,
  45223         soc_QSPI_RAF_WATERMARK_BCM88470_A0r_fields,
  45224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45225         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45226         -1,
  45227         -1,
  45228     },
  45229 #endif /* chips */
  45230 
  45231 #if defined(BCM_88470_B0)
  45232     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM88470_B0r */
  45233         soc_block_list[61],
  45234         soc_iprocreg,
  45235         1,
  45236         0,
  45237         0x18021110,
  45238         0,
  45239         0,
  45240         2,
  45241         soc_QSPI_RAF_WATERMARK_BCM88470_B0r_fields,
  45242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45243         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45244         -1,
  45245         -1,
  45246     },
  45247 #endif /* chips */
  45248 
  45249 #if defined(BCM_88675_B0)
  45250     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM88675_B0r */
  45251         soc_block_list[61],
  45252         soc_iprocreg,
  45253         1,
  45254         0,
  45255         0x18021110,
  45256         0,
  45257         0,
  45258         2,
  45259         soc_QSPI_RAF_WATERMARK_BCM88675_B0r_fields,
  45260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45261         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45262         -1,
  45263         -1,
  45264     },
  45265 #endif /* chips */
  45266 
  45267 #if defined(BCM_88680_A0)
  45268     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM88680_A0r */
  45269         soc_block_list[61],
  45270         soc_iprocreg,
  45271         1,
  45272         0,
  45273         0x18021110,
  45274         0,
  45275         0,
  45276         2,
  45277         soc_QSPI_RAF_WATERMARK_BCM88680_A0r_fields,
  45278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45279         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45280         -1,
  45281         -1,
  45282     },
  45283 #endif /* chips */
  45284 
  45285 #if defined(BCM_88690_A0)
  45286     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM88690_A0r */
  45287         soc_block_list[61],
  45288         soc_iprocreg,
  45289         1,
  45290         0,
  45291         0x18021110,
  45292         0,
  45293         0,
  45294         2,
  45295         soc_QSPI_RAF_WATERMARK_BCM88690_A0r_fields,
  45296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45298         -1,
  45299         -1,
  45300     },
  45301 #endif /* chips */
  45302 
  45303 #if defined(BCM_88690_B0)
  45304     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM88690_B0r */
  45305         soc_block_list[61],
  45306         soc_iprocreg,
  45307         1,
  45308         0,
  45309         0x18021110,
  45310         0,
  45311         0,
  45312         2,
  45313         soc_QSPI_RAF_WATERMARK_BCM88690_B0r_fields,
  45314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45315         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45316         -1,
  45317         -1,
  45318     },
  45319 #endif /* chips */
  45320 
  45321 #if defined(BCM_88790_A0)
  45322     { /* SOC_REG_INT_QSPI_RAF_WATERMARK_BCM88790_A0r */
  45323         soc_block_list[61],
  45324         soc_iprocreg,
  45325         1,
  45326         0,
  45327         0x18021110,
  45328         0,
  45329         0,
  45330         2,
  45331         soc_QSPI_RAF_WATERMARK_BCM88790_A0r_fields,
  45332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45333         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45334         -1,
  45335         -1,
  45336     },
  45337 #endif /* chips */
  45338 
  45339 #if defined(BCM_88675_A0)
  45340     { /* SOC_REG_INT_QSPI_RAF_WORD_CNTr */
  45341         soc_block_list[61],
  45342         soc_iprocreg,
  45343         1,
  45344         0,
  45345         0x1802111c,
  45346         SOC_REG_FLAG_RO,
  45347         0,
  45348         1,
  45349         soc_QSPI_RAF_WORD_CNTr_fields,
  45350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45351         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45352         -1,
  45353         -1,
  45354     },
  45355 #endif /* chips */
  45356 
  45357 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
  45358     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
  45359     defined(BCM_56160_A0) || defined(BCM_56260_A0) || \
  45360     defined(BCM_56260_B0)
  45361     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM53400_A0r */
  45362         soc_block_list[61],
  45363         soc_iprocreg,
  45364         1,
  45365         0,
  45366         0x1804711c,
  45367         SOC_REG_FLAG_RO,
  45368         0,
  45369         1,
  45370         soc_QSPI_RAF_WORD_CNT_BCM53400_A0r_fields,
  45371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45372         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45373         -1,
  45374         -1,
  45375     },
  45376 #endif /* chips */
  45377 
  45378 #if defined(BCM_56370_A0)
  45379     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM56370_A0r */
  45380         soc_block_list[61],
  45381         soc_iprocreg,
  45382         1,
  45383         0,
  45384         0x1500011c,
  45385         SOC_REG_FLAG_RO,
  45386         0,
  45387         1,
  45388         soc_QSPI_RAF_WORD_CNT_BCM53400_A0r_fields,
  45389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45390         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45391         -1,
  45392         -1,
  45393         3,
  45394     },
  45395 #endif /* chips */
  45396 
  45397 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \
  45398     defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45399     defined(BCM_56450_B1)
  45400     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM56450_A0r */
  45401         soc_block_list[61],
  45402         soc_iprocreg,
  45403         1,
  45404         0,
  45405         0x1802711c,
  45406         SOC_REG_FLAG_RO,
  45407         0,
  45408         1,
  45409         soc_QSPI_RAF_WORD_CNT_BCM56450_A0r_fields,
  45410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45411         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45412         -1,
  45413         -1,
  45414     },
  45415 #endif /* chips */
  45416 
  45417 #if defined(BCM_56270_A0) || defined(BCM_56560_A0) || \
  45418     defined(BCM_56560_B0) || defined(BCM_56670_A0) || \
  45419     defined(BCM_56670_B0)
  45420     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM56560_A0r */
  45421         soc_block_list[61],
  45422         soc_iprocreg,
  45423         1,
  45424         0,
  45425         0x1802111c,
  45426         SOC_REG_FLAG_RO,
  45427         0,
  45428         1,
  45429         soc_QSPI_RAF_WORD_CNT_BCM53400_A0r_fields,
  45430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45431         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45432         -1,
  45433         -1,
  45434     },
  45435 #endif /* chips */
  45436 
  45437 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \
  45438     defined(BCM_56960_A0) || defined(BCM_56965_A0) || \
  45439     defined(BCM_56970_A0) || defined(BCM_56980_A0) || \
  45440     defined(BCM_56980_B0)
  45441     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM56960_A0r */
  45442         soc_block_list[61],
  45443         soc_iprocreg,
  45444         1,
  45445         0,
  45446         0x1802111c,
  45447         SOC_REG_FLAG_RO,
  45448         0,
  45449         1,
  45450         soc_QSPI_RAF_WORD_CNT_BCM53400_A0r_fields,
  45451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45452         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45453         -1,
  45454         -1,
  45455         3,
  45456     },
  45457 #endif /* chips */
  45458 
  45459 #if defined(BCM_88270_A0)
  45460     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM88270_A0r */
  45461         soc_block_list[61],
  45462         soc_iprocreg,
  45463         1,
  45464         0,
  45465         0x1802111c,
  45466         SOC_REG_FLAG_RO,
  45467         0,
  45468         1,
  45469         soc_QSPI_RAF_WORD_CNT_BCM88270_A0r_fields,
  45470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45471         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45472         -1,
  45473         -1,
  45474     },
  45475 #endif /* chips */
  45476 
  45477 #if defined(BCM_88375_A0)
  45478     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM88375_A0r */
  45479         soc_block_list[61],
  45480         soc_iprocreg,
  45481         1,
  45482         0,
  45483         0x1802111c,
  45484         SOC_REG_FLAG_RO,
  45485         0,
  45486         1,
  45487         soc_QSPI_RAF_WORD_CNT_BCM88375_A0r_fields,
  45488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45490         -1,
  45491         -1,
  45492     },
  45493 #endif /* chips */
  45494 
  45495 #if defined(BCM_88375_B0)
  45496     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM88375_B0r */
  45497         soc_block_list[61],
  45498         soc_iprocreg,
  45499         1,
  45500         0,
  45501         0x1802111c,
  45502         SOC_REG_FLAG_RO,
  45503         0,
  45504         1,
  45505         soc_QSPI_RAF_WORD_CNT_BCM88375_B0r_fields,
  45506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45507         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45508         -1,
  45509         -1,
  45510     },
  45511 #endif /* chips */
  45512 
  45513 #if defined(BCM_88470_A0)
  45514     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM88470_A0r */
  45515         soc_block_list[61],
  45516         soc_iprocreg,
  45517         1,
  45518         0,
  45519         0x1802111c,
  45520         SOC_REG_FLAG_RO,
  45521         0,
  45522         1,
  45523         soc_QSPI_RAF_WORD_CNT_BCM88470_A0r_fields,
  45524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45525         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45526         -1,
  45527         -1,
  45528     },
  45529 #endif /* chips */
  45530 
  45531 #if defined(BCM_88470_B0)
  45532     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM88470_B0r */
  45533         soc_block_list[61],
  45534         soc_iprocreg,
  45535         1,
  45536         0,
  45537         0x1802111c,
  45538         SOC_REG_FLAG_RO,
  45539         0,
  45540         1,
  45541         soc_QSPI_RAF_WORD_CNT_BCM88470_B0r_fields,
  45542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45544         -1,
  45545         -1,
  45546     },
  45547 #endif /* chips */
  45548 
  45549 #if defined(BCM_88675_B0)
  45550     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM88675_B0r */
  45551         soc_block_list[61],
  45552         soc_iprocreg,
  45553         1,
  45554         0,
  45555         0x1802111c,
  45556         SOC_REG_FLAG_RO,
  45557         0,
  45558         1,
  45559         soc_QSPI_RAF_WORD_CNT_BCM88675_B0r_fields,
  45560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45561         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45562         -1,
  45563         -1,
  45564     },
  45565 #endif /* chips */
  45566 
  45567 #if defined(BCM_88680_A0)
  45568     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM88680_A0r */
  45569         soc_block_list[61],
  45570         soc_iprocreg,
  45571         1,
  45572         0,
  45573         0x1802111c,
  45574         SOC_REG_FLAG_RO,
  45575         0,
  45576         1,
  45577         soc_QSPI_RAF_WORD_CNT_BCM88680_A0r_fields,
  45578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45579         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45580         -1,
  45581         -1,
  45582     },
  45583 #endif /* chips */
  45584 
  45585 #if defined(BCM_88690_A0)
  45586     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM88690_A0r */
  45587         soc_block_list[61],
  45588         soc_iprocreg,
  45589         1,
  45590         0,
  45591         0x1802111c,
  45592         SOC_REG_FLAG_RO,
  45593         0,
  45594         1,
  45595         soc_QSPI_RAF_WORD_CNT_BCM88690_A0r_fields,
  45596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45597         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45598         -1,
  45599         -1,
  45600     },
  45601 #endif /* chips */
  45602 
  45603 #if defined(BCM_88690_B0)
  45604     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM88690_B0r */
  45605         soc_block_list[61],
  45606         soc_iprocreg,
  45607         1,
  45608         0,
  45609         0x1802111c,
  45610         SOC_REG_FLAG_RO,
  45611         0,
  45612         1,
  45613         soc_QSPI_RAF_WORD_CNT_BCM88690_B0r_fields,
  45614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45615         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45616         -1,
  45617         -1,
  45618     },
  45619 #endif /* chips */
  45620 
  45621 #if defined(BCM_88790_A0)
  45622     { /* SOC_REG_INT_QSPI_RAF_WORD_CNT_BCM88790_A0r */
  45623         soc_block_list[61],
  45624         soc_iprocreg,
  45625         1,
  45626         0,
  45627         0x1802111c,
  45628         SOC_REG_FLAG_RO,
  45629         0,
  45630         1,
  45631         soc_QSPI_RAF_WORD_CNT_BCM88790_A0r_fields,
  45632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45633         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45634         -1,
  45635         -1,
  45636     },
  45637 #endif /* chips */
  45638 
  45639 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45640     { /* SOC_REG_INT_QSTRUCT_FAP0_WATERMARKr */
  45641         soc_block_list[4],
  45642         soc_genreg,
  45643         1,
  45644         0,
  45645         0x2a080048,
  45646         0,
  45647         0,
  45648         1,
  45649         soc_QSTRUCT_FAP0_WATERMARKr_fields,
  45650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45652         -1,
  45653         -1,
  45654     },
  45655 #endif /* chips */
  45656 
  45657 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45658     defined(BCM_56450_B1)
  45659     { /* SOC_REG_INT_QSTRUCT_FAP0_WATERMARK_BCM56450_A0r */
  45660         soc_block_list[4],
  45661         soc_genreg,
  45662         1,
  45663         0,
  45664         0xaa004600,
  45665         0,
  45666         0,
  45667         1,
  45668         soc_QSTRUCT_FAP0_WATERMARK_BCM56450_A0r_fields,
  45669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45670         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45671         -1,
  45672         -1,
  45673     },
  45674 #endif /* chips */
  45675 
  45676 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45677     { /* SOC_REG_INT_QSTRUCT_FAP1_WATERMARKr */
  45678         soc_block_list[4],
  45679         soc_genreg,
  45680         1,
  45681         0,
  45682         0x2a080049,
  45683         0,
  45684         0,
  45685         1,
  45686         soc_QSTRUCT_FAP0_WATERMARKr_fields,
  45687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45688         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45689         -1,
  45690         -1,
  45691     },
  45692 #endif /* chips */
  45693 
  45694 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45695     defined(BCM_56450_B1)
  45696     { /* SOC_REG_INT_QSTRUCT_FAP1_WATERMARK_BCM56450_A0r */
  45697         soc_block_list[4],
  45698         soc_genreg,
  45699         1,
  45700         0,
  45701         0xaa004700,
  45702         0,
  45703         0,
  45704         1,
  45705         soc_QSTRUCT_FAP0_WATERMARK_BCM56450_A0r_fields,
  45706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45707         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45708         -1,
  45709         -1,
  45710     },
  45711 #endif /* chips */
  45712 
  45713 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45714     { /* SOC_REG_INT_QSTRUCT_FAP2_WATERMARKr */
  45715         soc_block_list[4],
  45716         soc_genreg,
  45717         1,
  45718         0,
  45719         0x2a08004a,
  45720         0,
  45721         0,
  45722         1,
  45723         soc_QSTRUCT_FAP0_WATERMARKr_fields,
  45724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45725         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45726         -1,
  45727         -1,
  45728     },
  45729 #endif /* chips */
  45730 
  45731 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45732     defined(BCM_56450_B1)
  45733     { /* SOC_REG_INT_QSTRUCT_FAP2_WATERMARK_BCM56450_A0r */
  45734         soc_block_list[4],
  45735         soc_genreg,
  45736         1,
  45737         0,
  45738         0xaa004800,
  45739         0,
  45740         0,
  45741         1,
  45742         soc_QSTRUCT_FAP0_WATERMARK_BCM56450_A0r_fields,
  45743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45744         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45745         -1,
  45746         -1,
  45747     },
  45748 #endif /* chips */
  45749 
  45750 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45751     { /* SOC_REG_INT_QSTRUCT_FAP3_WATERMARKr */
  45752         soc_block_list[4],
  45753         soc_genreg,
  45754         1,
  45755         0,
  45756         0x2a08004b,
  45757         0,
  45758         0,
  45759         1,
  45760         soc_QSTRUCT_FAP0_WATERMARKr_fields,
  45761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45762         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45763         -1,
  45764         -1,
  45765     },
  45766 #endif /* chips */
  45767 
  45768 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45769     defined(BCM_56450_B1)
  45770     { /* SOC_REG_INT_QSTRUCT_FAP3_WATERMARK_BCM56450_A0r */
  45771         soc_block_list[4],
  45772         soc_genreg,
  45773         1,
  45774         0,
  45775         0xaa004900,
  45776         0,
  45777         0,
  45778         1,
  45779         soc_QSTRUCT_FAP0_WATERMARK_BCM56450_A0r_fields,
  45780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45782         -1,
  45783         -1,
  45784     },
  45785 #endif /* chips */
  45786 
  45787 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  45788     { /* SOC_REG_INT_QSTRUCT_FAPCONFIGr */
  45789         soc_block_list[4],
  45790         soc_genreg,
  45791         2,
  45792         0,
  45793         0xaa000000,
  45794         SOC_REG_FLAG_ARRAY,
  45795         0,
  45796         1,
  45797         soc_QSTRUCT_FAPCONFIGr_fields,
  45798         SOC_RESET_VAL_DEC(0x00004600, 0x00000000)
  45799         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  45800         -1,
  45801         -1,
  45802     },
  45803 #endif /* chips */
  45804 
  45805 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45806     { /* SOC_REG_INT_QSTRUCT_FAPCONFIG_0r */
  45807         soc_block_list[4],
  45808         soc_genreg,
  45809         1,
  45810         0,
  45811         0x2a080000,
  45812         0,
  45813         0,
  45814         1,
  45815         soc_QSTRUCT_FAPCONFIG_0r_fields,
  45816         SOC_RESET_VAL_DEC(0x00011800, 0x00000000)
  45817         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45818         -1,
  45819         -1,
  45820     },
  45821 #endif /* chips */
  45822 
  45823 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45824     { /* SOC_REG_INT_QSTRUCT_FAPCONFIG_1r */
  45825         soc_block_list[4],
  45826         soc_genreg,
  45827         1,
  45828         0,
  45829         0x2a080001,
  45830         0,
  45831         0,
  45832         1,
  45833         soc_QSTRUCT_FAPCONFIG_0r_fields,
  45834         SOC_RESET_VAL_DEC(0x00011800, 0x00000000)
  45835         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45836         -1,
  45837         -1,
  45838     },
  45839 #endif /* chips */
  45840 
  45841 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45842     { /* SOC_REG_INT_QSTRUCT_FAPCONFIG_2r */
  45843         soc_block_list[4],
  45844         soc_genreg,
  45845         1,
  45846         0,
  45847         0x2a080002,
  45848         0,
  45849         0,
  45850         1,
  45851         soc_QSTRUCT_FAPCONFIG_0r_fields,
  45852         SOC_RESET_VAL_DEC(0x00011800, 0x00000000)
  45853         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45854         -1,
  45855         -1,
  45856     },
  45857 #endif /* chips */
  45858 
  45859 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45860     { /* SOC_REG_INT_QSTRUCT_FAPCONFIG_3r */
  45861         soc_block_list[4],
  45862         soc_genreg,
  45863         1,
  45864         0,
  45865         0x2a080003,
  45866         0,
  45867         0,
  45868         1,
  45869         soc_QSTRUCT_FAPCONFIG_0r_fields,
  45870         SOC_RESET_VAL_DEC(0x00011800, 0x00000000)
  45871         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45872         -1,
  45873         -1,
  45874     },
  45875 #endif /* chips */
  45876 
  45877 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45878     defined(BCM_56450_B1)
  45879     { /* SOC_REG_INT_QSTRUCT_FAPCONFIG_0_BCM56450_A0r */
  45880         soc_block_list[4],
  45881         soc_genreg,
  45882         1,
  45883         0,
  45884         0xaa000000,
  45885         0,
  45886         0,
  45887         1,
  45888         soc_QSTRUCT_FAPCONFIG_0_BCM56450_A0r_fields,
  45889         SOC_RESET_VAL_DEC(0x00011800, 0x00000000)
  45890         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45891         -1,
  45892         -1,
  45893     },
  45894 #endif /* chips */
  45895 
  45896 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45897     defined(BCM_56450_B1)
  45898     { /* SOC_REG_INT_QSTRUCT_FAPCONFIG_1_BCM56450_A0r */
  45899         soc_block_list[4],
  45900         soc_genreg,
  45901         1,
  45902         0,
  45903         0xaa000100,
  45904         0,
  45905         0,
  45906         1,
  45907         soc_QSTRUCT_FAPCONFIG_0_BCM56450_A0r_fields,
  45908         SOC_RESET_VAL_DEC(0x00011800, 0x00000000)
  45909         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45910         -1,
  45911         -1,
  45912     },
  45913 #endif /* chips */
  45914 
  45915 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45916     defined(BCM_56450_B1)
  45917     { /* SOC_REG_INT_QSTRUCT_FAPCONFIG_2_BCM56450_A0r */
  45918         soc_block_list[4],
  45919         soc_genreg,
  45920         1,
  45921         0,
  45922         0xaa000200,
  45923         0,
  45924         0,
  45925         1,
  45926         soc_QSTRUCT_FAPCONFIG_0_BCM56450_A0r_fields,
  45927         SOC_RESET_VAL_DEC(0x00011800, 0x00000000)
  45928         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45929         -1,
  45930         -1,
  45931     },
  45932 #endif /* chips */
  45933 
  45934 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  45935     defined(BCM_56450_B1)
  45936     { /* SOC_REG_INT_QSTRUCT_FAPCONFIG_3_BCM56450_A0r */
  45937         soc_block_list[4],
  45938         soc_genreg,
  45939         1,
  45940         0,
  45941         0xaa000300,
  45942         0,
  45943         0,
  45944         1,
  45945         soc_QSTRUCT_FAPCONFIG_0_BCM56450_A0r_fields,
  45946         SOC_RESET_VAL_DEC(0x00011800, 0x00000000)
  45947         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45948         -1,
  45949         -1,
  45950     },
  45951 #endif /* chips */
  45952 
  45953 #if defined(BCM_56270_A0)
  45954     { /* SOC_REG_INT_QSTRUCT_FAPCONFIG_BCM56270_A0r */
  45955         soc_block_list[4],
  45956         soc_genreg,
  45957         2,
  45958         0,
  45959         0xaa000000,
  45960         SOC_REG_FLAG_ARRAY,
  45961         0,
  45962         1,
  45963         soc_QSTRUCT_FAPCONFIG_BCM56270_A0r_fields,
  45964         SOC_RESET_VAL_DEC(0x00000f00, 0x00000000)
  45965         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  45966         -1,
  45967         -1,
  45968     },
  45969 #endif /* chips */
  45970 
  45971 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  45972     { /* SOC_REG_INT_QSTRUCT_FAPFULLRESETPOINTr */
  45973         soc_block_list[4],
  45974         soc_genreg,
  45975         2,
  45976         0,
  45977         0xaa000600,
  45978         SOC_REG_FLAG_ARRAY,
  45979         0,
  45980         1,
  45981         soc_QSTRUCT_FAPFULLRESETPOINTr_fields,
  45982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45983         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  45984         -1,
  45985         -1,
  45986     },
  45987 #endif /* chips */
  45988 
  45989 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  45990     { /* SOC_REG_INT_QSTRUCT_FAPFULLRESETPOINT_0r */
  45991         soc_block_list[4],
  45992         soc_genreg,
  45993         1,
  45994         0,
  45995         0x2a08000c,
  45996         0,
  45997         0,
  45998         1,
  45999         soc_QSTRUCT_FAPFULLRESETPOINT_0r_fields,
  46000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46001         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46002         -1,
  46003         -1,
  46004     },
  46005 #endif /* chips */
  46006 
  46007 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46008     { /* SOC_REG_INT_QSTRUCT_FAPFULLRESETPOINT_1r */
  46009         soc_block_list[4],
  46010         soc_genreg,
  46011         1,
  46012         0,
  46013         0x2a08000d,
  46014         0,
  46015         0,
  46016         1,
  46017         soc_QSTRUCT_FAPFULLRESETPOINT_0r_fields,
  46018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46019         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46020         -1,
  46021         -1,
  46022     },
  46023 #endif /* chips */
  46024 
  46025 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46026     { /* SOC_REG_INT_QSTRUCT_FAPFULLRESETPOINT_2r */
  46027         soc_block_list[4],
  46028         soc_genreg,
  46029         1,
  46030         0,
  46031         0x2a08000e,
  46032         0,
  46033         0,
  46034         1,
  46035         soc_QSTRUCT_FAPFULLRESETPOINT_0r_fields,
  46036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46037         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46038         -1,
  46039         -1,
  46040     },
  46041 #endif /* chips */
  46042 
  46043 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46044     { /* SOC_REG_INT_QSTRUCT_FAPFULLRESETPOINT_3r */
  46045         soc_block_list[4],
  46046         soc_genreg,
  46047         1,
  46048         0,
  46049         0x2a08000f,
  46050         0,
  46051         0,
  46052         1,
  46053         soc_QSTRUCT_FAPFULLRESETPOINT_0r_fields,
  46054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46055         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46056         -1,
  46057         -1,
  46058     },
  46059 #endif /* chips */
  46060 
  46061 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46062     defined(BCM_56450_B1)
  46063     { /* SOC_REG_INT_QSTRUCT_FAPFULLRESETPOINT_0_BCM56450_A0r */
  46064         soc_block_list[4],
  46065         soc_genreg,
  46066         1,
  46067         0,
  46068         0xaa000c00,
  46069         0,
  46070         0,
  46071         1,
  46072         soc_QSTRUCT_FAPFULLRESETPOINT_0_BCM56450_A0r_fields,
  46073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46074         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46075         -1,
  46076         -1,
  46077     },
  46078 #endif /* chips */
  46079 
  46080 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46081     defined(BCM_56450_B1)
  46082     { /* SOC_REG_INT_QSTRUCT_FAPFULLRESETPOINT_1_BCM56450_A0r */
  46083         soc_block_list[4],
  46084         soc_genreg,
  46085         1,
  46086         0,
  46087         0xaa000d00,
  46088         0,
  46089         0,
  46090         1,
  46091         soc_QSTRUCT_FAPFULLRESETPOINT_0_BCM56450_A0r_fields,
  46092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46093         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46094         -1,
  46095         -1,
  46096     },
  46097 #endif /* chips */
  46098 
  46099 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46100     defined(BCM_56450_B1)
  46101     { /* SOC_REG_INT_QSTRUCT_FAPFULLRESETPOINT_2_BCM56450_A0r */
  46102         soc_block_list[4],
  46103         soc_genreg,
  46104         1,
  46105         0,
  46106         0xaa000e00,
  46107         0,
  46108         0,
  46109         1,
  46110         soc_QSTRUCT_FAPFULLRESETPOINT_0_BCM56450_A0r_fields,
  46111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46112         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46113         -1,
  46114         -1,
  46115     },
  46116 #endif /* chips */
  46117 
  46118 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46119     defined(BCM_56450_B1)
  46120     { /* SOC_REG_INT_QSTRUCT_FAPFULLRESETPOINT_3_BCM56450_A0r */
  46121         soc_block_list[4],
  46122         soc_genreg,
  46123         1,
  46124         0,
  46125         0xaa000f00,
  46126         0,
  46127         0,
  46128         1,
  46129         soc_QSTRUCT_FAPFULLRESETPOINT_0_BCM56450_A0r_fields,
  46130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46131         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46132         -1,
  46133         -1,
  46134     },
  46135 #endif /* chips */
  46136 
  46137 #if defined(BCM_56270_A0)
  46138     { /* SOC_REG_INT_QSTRUCT_FAPFULLRESETPOINT_BCM56270_A0r */
  46139         soc_block_list[4],
  46140         soc_genreg,
  46141         2,
  46142         0,
  46143         0xaa000600,
  46144         SOC_REG_FLAG_ARRAY,
  46145         0,
  46146         1,
  46147         soc_QSTRUCT_FAPFULLRESETPOINT_BCM56270_A0r_fields,
  46148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46150         -1,
  46151         -1,
  46152     },
  46153 #endif /* chips */
  46154 
  46155 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46156     { /* SOC_REG_INT_QSTRUCT_FAPFULLSETPOINTr */
  46157         soc_block_list[4],
  46158         soc_genreg,
  46159         2,
  46160         0,
  46161         0xaa000400,
  46162         SOC_REG_FLAG_ARRAY,
  46163         0,
  46164         1,
  46165         soc_QSTRUCT_FAPFULLSETPOINTr_fields,
  46166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46167         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46168         -1,
  46169         -1,
  46170     },
  46171 #endif /* chips */
  46172 
  46173 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46174     { /* SOC_REG_INT_QSTRUCT_FAPFULLSETPOINT_0r */
  46175         soc_block_list[4],
  46176         soc_genreg,
  46177         1,
  46178         0,
  46179         0x2a080008,
  46180         0,
  46181         0,
  46182         1,
  46183         soc_QSTRUCT_FAPFULLSETPOINT_0r_fields,
  46184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46185         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46186         -1,
  46187         -1,
  46188     },
  46189 #endif /* chips */
  46190 
  46191 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46192     { /* SOC_REG_INT_QSTRUCT_FAPFULLSETPOINT_1r */
  46193         soc_block_list[4],
  46194         soc_genreg,
  46195         1,
  46196         0,
  46197         0x2a080009,
  46198         0,
  46199         0,
  46200         1,
  46201         soc_QSTRUCT_FAPFULLSETPOINT_0r_fields,
  46202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46203         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46204         -1,
  46205         -1,
  46206     },
  46207 #endif /* chips */
  46208 
  46209 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46210     { /* SOC_REG_INT_QSTRUCT_FAPFULLSETPOINT_2r */
  46211         soc_block_list[4],
  46212         soc_genreg,
  46213         1,
  46214         0,
  46215         0x2a08000a,
  46216         0,
  46217         0,
  46218         1,
  46219         soc_QSTRUCT_FAPFULLSETPOINT_0r_fields,
  46220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46221         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46222         -1,
  46223         -1,
  46224     },
  46225 #endif /* chips */
  46226 
  46227 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46228     { /* SOC_REG_INT_QSTRUCT_FAPFULLSETPOINT_3r */
  46229         soc_block_list[4],
  46230         soc_genreg,
  46231         1,
  46232         0,
  46233         0x2a08000b,
  46234         0,
  46235         0,
  46236         1,
  46237         soc_QSTRUCT_FAPFULLSETPOINT_0r_fields,
  46238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46239         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46240         -1,
  46241         -1,
  46242     },
  46243 #endif /* chips */
  46244 
  46245 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46246     defined(BCM_56450_B1)
  46247     { /* SOC_REG_INT_QSTRUCT_FAPFULLSETPOINT_0_BCM56450_A0r */
  46248         soc_block_list[4],
  46249         soc_genreg,
  46250         1,
  46251         0,
  46252         0xaa000800,
  46253         0,
  46254         0,
  46255         1,
  46256         soc_QSTRUCT_FAPFULLSETPOINT_0_BCM56450_A0r_fields,
  46257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46258         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46259         -1,
  46260         -1,
  46261     },
  46262 #endif /* chips */
  46263 
  46264 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46265     defined(BCM_56450_B1)
  46266     { /* SOC_REG_INT_QSTRUCT_FAPFULLSETPOINT_1_BCM56450_A0r */
  46267         soc_block_list[4],
  46268         soc_genreg,
  46269         1,
  46270         0,
  46271         0xaa000900,
  46272         0,
  46273         0,
  46274         1,
  46275         soc_QSTRUCT_FAPFULLSETPOINT_0_BCM56450_A0r_fields,
  46276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46277         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46278         -1,
  46279         -1,
  46280     },
  46281 #endif /* chips */
  46282 
  46283 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46284     defined(BCM_56450_B1)
  46285     { /* SOC_REG_INT_QSTRUCT_FAPFULLSETPOINT_2_BCM56450_A0r */
  46286         soc_block_list[4],
  46287         soc_genreg,
  46288         1,
  46289         0,
  46290         0xaa000a00,
  46291         0,
  46292         0,
  46293         1,
  46294         soc_QSTRUCT_FAPFULLSETPOINT_0_BCM56450_A0r_fields,
  46295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46296         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46297         -1,
  46298         -1,
  46299     },
  46300 #endif /* chips */
  46301 
  46302 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46303     defined(BCM_56450_B1)
  46304     { /* SOC_REG_INT_QSTRUCT_FAPFULLSETPOINT_3_BCM56450_A0r */
  46305         soc_block_list[4],
  46306         soc_genreg,
  46307         1,
  46308         0,
  46309         0xaa000b00,
  46310         0,
  46311         0,
  46312         1,
  46313         soc_QSTRUCT_FAPFULLSETPOINT_0_BCM56450_A0r_fields,
  46314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46315         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46316         -1,
  46317         -1,
  46318     },
  46319 #endif /* chips */
  46320 
  46321 #if defined(BCM_56270_A0)
  46322     { /* SOC_REG_INT_QSTRUCT_FAPFULLSETPOINT_BCM56270_A0r */
  46323         soc_block_list[4],
  46324         soc_genreg,
  46325         2,
  46326         0,
  46327         0xaa000400,
  46328         SOC_REG_FLAG_ARRAY,
  46329         0,
  46330         1,
  46331         soc_QSTRUCT_FAPFULLSETPOINT_BCM56270_A0r_fields,
  46332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46333         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46334         -1,
  46335         -1,
  46336     },
  46337 #endif /* chips */
  46338 
  46339 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  46340     defined(BCM_56270_A0)
  46341     { /* SOC_REG_INT_QSTRUCT_FAPINITr */
  46342         soc_block_list[4],
  46343         soc_genreg,
  46344         2,
  46345         0,
  46346         0xaa000200,
  46347         SOC_REG_FLAG_ARRAY,
  46348         0,
  46349         1,
  46350         soc_MMU_ENQ_FAPINIT_0_BCM56260_A0r_fields,
  46351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46352         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  46353         -1,
  46354         -1,
  46355     },
  46356 #endif /* chips */
  46357 
  46358 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46359     { /* SOC_REG_INT_QSTRUCT_FAPINIT_0r */
  46360         soc_block_list[4],
  46361         soc_genreg,
  46362         1,
  46363         0,
  46364         0x2a080004,
  46365         0,
  46366         0,
  46367         1,
  46368         soc_MMU_ENQ_FAPINIT_0r_fields,
  46369         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46370         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  46371         -1,
  46372         -1,
  46373     },
  46374 #endif /* chips */
  46375 
  46376 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46377     { /* SOC_REG_INT_QSTRUCT_FAPINIT_1r */
  46378         soc_block_list[4],
  46379         soc_genreg,
  46380         1,
  46381         0,
  46382         0x2a080005,
  46383         0,
  46384         0,
  46385         1,
  46386         soc_MMU_ENQ_FAPINIT_0r_fields,
  46387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46388         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  46389         -1,
  46390         -1,
  46391     },
  46392 #endif /* chips */
  46393 
  46394 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46395     { /* SOC_REG_INT_QSTRUCT_FAPINIT_2r */
  46396         soc_block_list[4],
  46397         soc_genreg,
  46398         1,
  46399         0,
  46400         0x2a080006,
  46401         0,
  46402         0,
  46403         1,
  46404         soc_MMU_ENQ_FAPINIT_0r_fields,
  46405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46406         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  46407         -1,
  46408         -1,
  46409     },
  46410 #endif /* chips */
  46411 
  46412 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46413     { /* SOC_REG_INT_QSTRUCT_FAPINIT_3r */
  46414         soc_block_list[4],
  46415         soc_genreg,
  46416         1,
  46417         0,
  46418         0x2a080007,
  46419         0,
  46420         0,
  46421         1,
  46422         soc_MMU_ENQ_FAPINIT_0r_fields,
  46423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46424         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  46425         -1,
  46426         -1,
  46427     },
  46428 #endif /* chips */
  46429 
  46430 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46431     defined(BCM_56450_B1)
  46432     { /* SOC_REG_INT_QSTRUCT_FAPINIT_0_BCM56450_A0r */
  46433         soc_block_list[4],
  46434         soc_genreg,
  46435         1,
  46436         0,
  46437         0xaa000400,
  46438         0,
  46439         0,
  46440         1,
  46441         soc_MMU_ENQ_FAPINIT_0_BCM56450_A0r_fields,
  46442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46443         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  46444         -1,
  46445         -1,
  46446     },
  46447 #endif /* chips */
  46448 
  46449 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46450     defined(BCM_56450_B1)
  46451     { /* SOC_REG_INT_QSTRUCT_FAPINIT_1_BCM56450_A0r */
  46452         soc_block_list[4],
  46453         soc_genreg,
  46454         1,
  46455         0,
  46456         0xaa000500,
  46457         0,
  46458         0,
  46459         1,
  46460         soc_MMU_ENQ_FAPINIT_0_BCM56450_A0r_fields,
  46461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46462         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  46463         -1,
  46464         -1,
  46465     },
  46466 #endif /* chips */
  46467 
  46468 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46469     defined(BCM_56450_B1)
  46470     { /* SOC_REG_INT_QSTRUCT_FAPINIT_2_BCM56450_A0r */
  46471         soc_block_list[4],
  46472         soc_genreg,
  46473         1,
  46474         0,
  46475         0xaa000600,
  46476         0,
  46477         0,
  46478         1,
  46479         soc_MMU_ENQ_FAPINIT_0_BCM56450_A0r_fields,
  46480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46481         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  46482         -1,
  46483         -1,
  46484     },
  46485 #endif /* chips */
  46486 
  46487 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46488     defined(BCM_56450_B1)
  46489     { /* SOC_REG_INT_QSTRUCT_FAPINIT_3_BCM56450_A0r */
  46490         soc_block_list[4],
  46491         soc_genreg,
  46492         1,
  46493         0,
  46494         0xaa000700,
  46495         0,
  46496         0,
  46497         1,
  46498         soc_MMU_ENQ_FAPINIT_0_BCM56450_A0r_fields,
  46499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46500         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  46501         -1,
  46502         -1,
  46503     },
  46504 #endif /* chips */
  46505 
  46506 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46507     { /* SOC_REG_INT_QSTRUCT_FAPOTPCONFIGr */
  46508         soc_block_list[4],
  46509         soc_genreg,
  46510         2,
  46511         0,
  46512         0xaa000a00,
  46513         SOC_REG_FLAG_ARRAY |
  46514                           SOC_REG_FLAG_RO,
  46515         0,
  46516         1,
  46517         soc_QSTRUCT_FAPOTPCONFIGr_fields,
  46518         SOC_RESET_VAL_DEC(0x00004600, 0x00000000)
  46519         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  46520         -1,
  46521         -1,
  46522     },
  46523 #endif /* chips */
  46524 
  46525 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46526     { /* SOC_REG_INT_QSTRUCT_FAPOTPCONFIG_0r */
  46527         soc_block_list[4],
  46528         soc_genreg,
  46529         1,
  46530         0,
  46531         0x2a080014,
  46532         SOC_REG_FLAG_RO,
  46533         0,
  46534         1,
  46535         soc_QSTRUCT_FAPOTPCONFIG_0r_fields,
  46536         SOC_RESET_VAL_DEC(0x00004600, 0x00000000)
  46537         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46538         -1,
  46539         -1,
  46540     },
  46541 #endif /* chips */
  46542 
  46543 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46544     { /* SOC_REG_INT_QSTRUCT_FAPOTPCONFIG_1r */
  46545         soc_block_list[4],
  46546         soc_genreg,
  46547         1,
  46548         0,
  46549         0x2a080015,
  46550         SOC_REG_FLAG_RO,
  46551         0,
  46552         1,
  46553         soc_QSTRUCT_FAPOTPCONFIG_0r_fields,
  46554         SOC_RESET_VAL_DEC(0x00004600, 0x00000000)
  46555         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46556         -1,
  46557         -1,
  46558     },
  46559 #endif /* chips */
  46560 
  46561 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46562     { /* SOC_REG_INT_QSTRUCT_FAPOTPCONFIG_2r */
  46563         soc_block_list[4],
  46564         soc_genreg,
  46565         1,
  46566         0,
  46567         0x2a080016,
  46568         SOC_REG_FLAG_RO,
  46569         0,
  46570         1,
  46571         soc_QSTRUCT_FAPOTPCONFIG_0r_fields,
  46572         SOC_RESET_VAL_DEC(0x00004600, 0x00000000)
  46573         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46574         -1,
  46575         -1,
  46576     },
  46577 #endif /* chips */
  46578 
  46579 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46580     { /* SOC_REG_INT_QSTRUCT_FAPOTPCONFIG_3r */
  46581         soc_block_list[4],
  46582         soc_genreg,
  46583         1,
  46584         0,
  46585         0x2a080017,
  46586         SOC_REG_FLAG_RO,
  46587         0,
  46588         1,
  46589         soc_QSTRUCT_FAPOTPCONFIG_0r_fields,
  46590         SOC_RESET_VAL_DEC(0x00004600, 0x00000000)
  46591         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46592         -1,
  46593         -1,
  46594     },
  46595 #endif /* chips */
  46596 
  46597 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46598     defined(BCM_56450_B1)
  46599     { /* SOC_REG_INT_QSTRUCT_FAPOTPCONFIG_0_BCM56450_A0r */
  46600         soc_block_list[4],
  46601         soc_genreg,
  46602         1,
  46603         0,
  46604         0xaa001400,
  46605         SOC_REG_FLAG_RO,
  46606         0,
  46607         1,
  46608         soc_QSTRUCT_FAPOTPCONFIG_0_BCM56450_A0r_fields,
  46609         SOC_RESET_VAL_DEC(0x00004600, 0x00000000)
  46610         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46611         -1,
  46612         -1,
  46613     },
  46614 #endif /* chips */
  46615 
  46616 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46617     defined(BCM_56450_B1)
  46618     { /* SOC_REG_INT_QSTRUCT_FAPOTPCONFIG_1_BCM56450_A0r */
  46619         soc_block_list[4],
  46620         soc_genreg,
  46621         1,
  46622         0,
  46623         0xaa001500,
  46624         SOC_REG_FLAG_RO,
  46625         0,
  46626         1,
  46627         soc_QSTRUCT_FAPOTPCONFIG_0_BCM56450_A0r_fields,
  46628         SOC_RESET_VAL_DEC(0x00004600, 0x00000000)
  46629         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46630         -1,
  46631         -1,
  46632     },
  46633 #endif /* chips */
  46634 
  46635 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46636     defined(BCM_56450_B1)
  46637     { /* SOC_REG_INT_QSTRUCT_FAPOTPCONFIG_2_BCM56450_A0r */
  46638         soc_block_list[4],
  46639         soc_genreg,
  46640         1,
  46641         0,
  46642         0xaa001600,
  46643         SOC_REG_FLAG_RO,
  46644         0,
  46645         1,
  46646         soc_QSTRUCT_FAPOTPCONFIG_0_BCM56450_A0r_fields,
  46647         SOC_RESET_VAL_DEC(0x00004600, 0x00000000)
  46648         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46649         -1,
  46650         -1,
  46651     },
  46652 #endif /* chips */
  46653 
  46654 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46655     defined(BCM_56450_B1)
  46656     { /* SOC_REG_INT_QSTRUCT_FAPOTPCONFIG_3_BCM56450_A0r */
  46657         soc_block_list[4],
  46658         soc_genreg,
  46659         1,
  46660         0,
  46661         0xaa001700,
  46662         SOC_REG_FLAG_RO,
  46663         0,
  46664         1,
  46665         soc_QSTRUCT_FAPOTPCONFIG_0_BCM56450_A0r_fields,
  46666         SOC_RESET_VAL_DEC(0x00004600, 0x00000000)
  46667         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46668         -1,
  46669         -1,
  46670     },
  46671 #endif /* chips */
  46672 
  46673 #if defined(BCM_56270_A0)
  46674     { /* SOC_REG_INT_QSTRUCT_FAPOTPCONFIG_BCM56270_A0r */
  46675         soc_block_list[4],
  46676         soc_genreg,
  46677         2,
  46678         0,
  46679         0xaa000a00,
  46680         SOC_REG_FLAG_ARRAY |
  46681                           SOC_REG_FLAG_RO,
  46682         0,
  46683         1,
  46684         soc_QSTRUCT_FAPOTPCONFIG_BCM56270_A0r_fields,
  46685         SOC_RESET_VAL_DEC(0x00000f00, 0x00000000)
  46686         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  46687         -1,
  46688         -1,
  46689     },
  46690 #endif /* chips */
  46691 
  46692 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46693     { /* SOC_REG_INT_QSTRUCT_FAPREADPOINTERr */
  46694         soc_block_list[4],
  46695         soc_genreg,
  46696         2,
  46697         0,
  46698         0xaa000800,
  46699         SOC_REG_FLAG_ARRAY |
  46700                           SOC_REG_FLAG_RO,
  46701         0,
  46702         2,
  46703         soc_QSTRUCT_FAPREADPOINTERr_fields,
  46704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46706         -1,
  46707         -1,
  46708     },
  46709 #endif /* chips */
  46710 
  46711 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46712     { /* SOC_REG_INT_QSTRUCT_FAPREADPOINTER_0r */
  46713         soc_block_list[4],
  46714         soc_genreg,
  46715         1,
  46716         0,
  46717         0x2a080010,
  46718         SOC_REG_FLAG_RO,
  46719         0,
  46720         2,
  46721         soc_QSTRUCT_FAPREADPOINTER_0r_fields,
  46722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46723         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46724         -1,
  46725         -1,
  46726     },
  46727 #endif /* chips */
  46728 
  46729 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46730     { /* SOC_REG_INT_QSTRUCT_FAPREADPOINTER_1r */
  46731         soc_block_list[4],
  46732         soc_genreg,
  46733         1,
  46734         0,
  46735         0x2a080011,
  46736         SOC_REG_FLAG_RO,
  46737         0,
  46738         2,
  46739         soc_QSTRUCT_FAPREADPOINTER_0r_fields,
  46740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46741         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46742         -1,
  46743         -1,
  46744     },
  46745 #endif /* chips */
  46746 
  46747 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46748     { /* SOC_REG_INT_QSTRUCT_FAPREADPOINTER_2r */
  46749         soc_block_list[4],
  46750         soc_genreg,
  46751         1,
  46752         0,
  46753         0x2a080012,
  46754         SOC_REG_FLAG_RO,
  46755         0,
  46756         2,
  46757         soc_QSTRUCT_FAPREADPOINTER_0r_fields,
  46758         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46759         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46760         -1,
  46761         -1,
  46762     },
  46763 #endif /* chips */
  46764 
  46765 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46766     { /* SOC_REG_INT_QSTRUCT_FAPREADPOINTER_3r */
  46767         soc_block_list[4],
  46768         soc_genreg,
  46769         1,
  46770         0,
  46771         0x2a080013,
  46772         SOC_REG_FLAG_RO,
  46773         0,
  46774         2,
  46775         soc_QSTRUCT_FAPREADPOINTER_0r_fields,
  46776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46777         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46778         -1,
  46779         -1,
  46780     },
  46781 #endif /* chips */
  46782 
  46783 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46784     defined(BCM_56450_B1)
  46785     { /* SOC_REG_INT_QSTRUCT_FAPREADPOINTER_0_BCM56450_A0r */
  46786         soc_block_list[4],
  46787         soc_genreg,
  46788         1,
  46789         0,
  46790         0xaa001000,
  46791         SOC_REG_FLAG_RO,
  46792         0,
  46793         2,
  46794         soc_QSTRUCT_FAPREADPOINTER_0_BCM56450_A0r_fields,
  46795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46796         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46797         -1,
  46798         -1,
  46799     },
  46800 #endif /* chips */
  46801 
  46802 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46803     defined(BCM_56450_B1)
  46804     { /* SOC_REG_INT_QSTRUCT_FAPREADPOINTER_1_BCM56450_A0r */
  46805         soc_block_list[4],
  46806         soc_genreg,
  46807         1,
  46808         0,
  46809         0xaa001100,
  46810         SOC_REG_FLAG_RO,
  46811         0,
  46812         2,
  46813         soc_QSTRUCT_FAPREADPOINTER_0_BCM56450_A0r_fields,
  46814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46815         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46816         -1,
  46817         -1,
  46818     },
  46819 #endif /* chips */
  46820 
  46821 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46822     defined(BCM_56450_B1)
  46823     { /* SOC_REG_INT_QSTRUCT_FAPREADPOINTER_2_BCM56450_A0r */
  46824         soc_block_list[4],
  46825         soc_genreg,
  46826         1,
  46827         0,
  46828         0xaa001200,
  46829         SOC_REG_FLAG_RO,
  46830         0,
  46831         2,
  46832         soc_QSTRUCT_FAPREADPOINTER_0_BCM56450_A0r_fields,
  46833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46835         -1,
  46836         -1,
  46837     },
  46838 #endif /* chips */
  46839 
  46840 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46841     defined(BCM_56450_B1)
  46842     { /* SOC_REG_INT_QSTRUCT_FAPREADPOINTER_3_BCM56450_A0r */
  46843         soc_block_list[4],
  46844         soc_genreg,
  46845         1,
  46846         0,
  46847         0xaa001300,
  46848         SOC_REG_FLAG_RO,
  46849         0,
  46850         2,
  46851         soc_QSTRUCT_FAPREADPOINTER_0_BCM56450_A0r_fields,
  46852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46853         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46854         -1,
  46855         -1,
  46856     },
  46857 #endif /* chips */
  46858 
  46859 #if defined(BCM_56270_A0)
  46860     { /* SOC_REG_INT_QSTRUCT_FAPREADPOINTER_BCM56270_A0r */
  46861         soc_block_list[4],
  46862         soc_genreg,
  46863         2,
  46864         0,
  46865         0xaa000800,
  46866         SOC_REG_FLAG_ARRAY |
  46867                           SOC_REG_FLAG_RO,
  46868         0,
  46869         2,
  46870         soc_QSTRUCT_FAPREADPOINTER_BCM56270_A0r_fields,
  46871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46872         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46873         -1,
  46874         -1,
  46875     },
  46876 #endif /* chips */
  46877 
  46878 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  46879     { /* SOC_REG_INT_QSTRUCT_FAPSTACKSTATUSr */
  46880         soc_block_list[4],
  46881         soc_genreg,
  46882         2,
  46883         0,
  46884         0xaa000c00,
  46885         SOC_REG_FLAG_ARRAY |
  46886                           SOC_REG_FLAG_RO,
  46887         0,
  46888         2,
  46889         soc_QSTRUCT_FAPSTACKSTATUSr_fields,
  46890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46891         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46892         -1,
  46893         -1,
  46894     },
  46895 #endif /* chips */
  46896 
  46897 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46898     { /* SOC_REG_INT_QSTRUCT_FAPSTACKSTATUS_0r */
  46899         soc_block_list[4],
  46900         soc_genreg,
  46901         1,
  46902         0,
  46903         0x2a080018,
  46904         SOC_REG_FLAG_RO,
  46905         0,
  46906         2,
  46907         soc_QSTRUCT_FAPSTACKSTATUS_0r_fields,
  46908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46909         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46910         -1,
  46911         -1,
  46912     },
  46913 #endif /* chips */
  46914 
  46915 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46916     { /* SOC_REG_INT_QSTRUCT_FAPSTACKSTATUS_1r */
  46917         soc_block_list[4],
  46918         soc_genreg,
  46919         1,
  46920         0,
  46921         0x2a080019,
  46922         SOC_REG_FLAG_RO,
  46923         0,
  46924         2,
  46925         soc_QSTRUCT_FAPSTACKSTATUS_0r_fields,
  46926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46927         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46928         -1,
  46929         -1,
  46930     },
  46931 #endif /* chips */
  46932 
  46933 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46934     { /* SOC_REG_INT_QSTRUCT_FAPSTACKSTATUS_2r */
  46935         soc_block_list[4],
  46936         soc_genreg,
  46937         1,
  46938         0,
  46939         0x2a08001a,
  46940         SOC_REG_FLAG_RO,
  46941         0,
  46942         2,
  46943         soc_QSTRUCT_FAPSTACKSTATUS_0r_fields,
  46944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46945         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46946         -1,
  46947         -1,
  46948     },
  46949 #endif /* chips */
  46950 
  46951 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  46952     { /* SOC_REG_INT_QSTRUCT_FAPSTACKSTATUS_3r */
  46953         soc_block_list[4],
  46954         soc_genreg,
  46955         1,
  46956         0,
  46957         0x2a08001b,
  46958         SOC_REG_FLAG_RO,
  46959         0,
  46960         2,
  46961         soc_QSTRUCT_FAPSTACKSTATUS_0r_fields,
  46962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46963         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46964         -1,
  46965         -1,
  46966     },
  46967 #endif /* chips */
  46968 
  46969 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46970     defined(BCM_56450_B1)
  46971     { /* SOC_REG_INT_QSTRUCT_FAPSTACKSTATUS_0_BCM56450_A0r */
  46972         soc_block_list[4],
  46973         soc_genreg,
  46974         1,
  46975         0,
  46976         0xaa001800,
  46977         SOC_REG_FLAG_RO,
  46978         0,
  46979         2,
  46980         soc_QSTRUCT_FAPSTACKSTATUS_0_BCM56450_A0r_fields,
  46981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46982         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  46983         -1,
  46984         -1,
  46985     },
  46986 #endif /* chips */
  46987 
  46988 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  46989     defined(BCM_56450_B1)
  46990     { /* SOC_REG_INT_QSTRUCT_FAPSTACKSTATUS_1_BCM56450_A0r */
  46991         soc_block_list[4],
  46992         soc_genreg,
  46993         1,
  46994         0,
  46995         0xaa001900,
  46996         SOC_REG_FLAG_RO,
  46997         0,
  46998         2,
  46999         soc_QSTRUCT_FAPSTACKSTATUS_0_BCM56450_A0r_fields,
  47000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47001         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47002         -1,
  47003         -1,
  47004     },
  47005 #endif /* chips */
  47006 
  47007 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47008     defined(BCM_56450_B1)
  47009     { /* SOC_REG_INT_QSTRUCT_FAPSTACKSTATUS_2_BCM56450_A0r */
  47010         soc_block_list[4],
  47011         soc_genreg,
  47012         1,
  47013         0,
  47014         0xaa001a00,
  47015         SOC_REG_FLAG_RO,
  47016         0,
  47017         2,
  47018         soc_QSTRUCT_FAPSTACKSTATUS_0_BCM56450_A0r_fields,
  47019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47020         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47021         -1,
  47022         -1,
  47023     },
  47024 #endif /* chips */
  47025 
  47026 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47027     defined(BCM_56450_B1)
  47028     { /* SOC_REG_INT_QSTRUCT_FAPSTACKSTATUS_3_BCM56450_A0r */
  47029         soc_block_list[4],
  47030         soc_genreg,
  47031         1,
  47032         0,
  47033         0xaa001b00,
  47034         SOC_REG_FLAG_RO,
  47035         0,
  47036         2,
  47037         soc_QSTRUCT_FAPSTACKSTATUS_0_BCM56450_A0r_fields,
  47038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47039         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47040         -1,
  47041         -1,
  47042     },
  47043 #endif /* chips */
  47044 
  47045 #if defined(BCM_56270_A0)
  47046     { /* SOC_REG_INT_QSTRUCT_FAPSTACKSTATUS_BCM56270_A0r */
  47047         soc_block_list[4],
  47048         soc_genreg,
  47049         2,
  47050         0,
  47051         0xaa000c00,
  47052         SOC_REG_FLAG_ARRAY |
  47053                           SOC_REG_FLAG_RO,
  47054         0,
  47055         2,
  47056         soc_MMU_ENQ_FAPSTACKSTATUS_0_BCM56260_A0r_fields,
  47057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47058         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47059         -1,
  47060         -1,
  47061     },
  47062 #endif /* chips */
  47063 
  47064 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47065     { /* SOC_REG_INT_QSTRUCT_FAP_BITMAP_ECC_DEBUGr */
  47066         soc_block_list[4],
  47067         soc_genreg,
  47068         1,
  47069         0,
  47070         0x2a080050,
  47071         0,
  47072         0,
  47073         8,
  47074         soc_QSTRUCT_FAP_BITMAP_ECC_DEBUGr_fields,
  47075         SOC_RESET_VAL_DEC(0x00000055, 0x00000000)
  47076         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47077         -1,
  47078         -1,
  47079     },
  47080 #endif /* chips */
  47081 
  47082 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47083     { /* SOC_REG_INT_QSTRUCT_FAP_BITMAP_ECC_DEBUG_BCM56260_A0r */
  47084         soc_block_list[4],
  47085         soc_genreg,
  47086         1,
  47087         0,
  47088         0xaa002500,
  47089         0,
  47090         0,
  47091         4,
  47092         soc_QSTRUCT_FAP_BITMAP_ECC_DEBUG_BCM56260_A0r_fields,
  47093         SOC_RESET_VAL_DEC(0x00000009, 0x00000000)
  47094         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47095         -1,
  47096         -1,
  47097     },
  47098 #endif /* chips */
  47099 
  47100 #if defined(BCM_56270_A0)
  47101     { /* SOC_REG_INT_QSTRUCT_FAP_BITMAP_ECC_DEBUG_BCM56270_A0r */
  47102         soc_block_list[4],
  47103         soc_genreg,
  47104         1,
  47105         0,
  47106         0xaa002400,
  47107         0,
  47108         0,
  47109         4,
  47110         soc_QSTRUCT_FAP_BITMAP_ECC_DEBUG_BCM56260_A0r_fields,
  47111         SOC_RESET_VAL_DEC(0x00000009, 0x00000000)
  47112         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47113         -1,
  47114         -1,
  47115     },
  47116 #endif /* chips */
  47117 
  47118 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47119     defined(BCM_56450_B1)
  47120     { /* SOC_REG_INT_QSTRUCT_FAP_BITMAP_ECC_DEBUG_BCM56450_A0r */
  47121         soc_block_list[4],
  47122         soc_genreg,
  47123         1,
  47124         0,
  47125         0xaa004e00,
  47126         0,
  47127         0,
  47128         8,
  47129         soc_QSTRUCT_FAP_BITMAP_ECC_DEBUG_BCM56450_A0r_fields,
  47130         SOC_RESET_VAL_DEC(0x00000055, 0x00000000)
  47131         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47132         -1,
  47133         -1,
  47134     },
  47135 #endif /* chips */
  47136 
  47137 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47138     { /* SOC_REG_INT_QSTRUCT_FAP_MEMDEBUGr */
  47139         soc_block_list[4],
  47140         soc_genreg,
  47141         1,
  47142         0,
  47143         0x2a08001c,
  47144         0,
  47145         0,
  47146         6,
  47147         soc_QSTRUCT_FAP_MEMDEBUGr_fields,
  47148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47149         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47150         -1,
  47151         -1,
  47152     },
  47153 #endif /* chips */
  47154 
  47155 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47156     defined(BCM_56450_B1)
  47157     { /* SOC_REG_INT_QSTRUCT_FAP_MEMDEBUG_BCM56450_A0r */
  47158         soc_block_list[4],
  47159         soc_genreg,
  47160         1,
  47161         0,
  47162         0xaa001c00,
  47163         0,
  47164         0,
  47165         2,
  47166         soc_MMU_ENQ_FAP_MEMDEBUG_0_BCM56450_A0r_fields,
  47167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47168         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47169         -1,
  47170         -1,
  47171     },
  47172 #endif /* chips */
  47173 
  47174 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47175     { /* SOC_REG_INT_QSTRUCT_FAP_MEMDEBUG_BITMAPr */
  47176         soc_block_list[4],
  47177         soc_genreg,
  47178         1,
  47179         0,
  47180         0xaa000e00,
  47181         0,
  47182         0,
  47183         1,
  47184         soc_PKTHDRMEMDEBUG_BCM56560_A0r_fields,
  47185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47186         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47187         -1,
  47188         -1,
  47189     },
  47190 #endif /* chips */
  47191 
  47192 #if defined(BCM_56270_A0)
  47193     { /* SOC_REG_INT_QSTRUCT_FAP_MEMDEBUG_BITMAP_BCM56270_A0r */
  47194         soc_block_list[4],
  47195         soc_genreg,
  47196         1,
  47197         0,
  47198         0xaa000e00,
  47199         0,
  47200         0,
  47201         1,
  47202         soc_AGINGCTRMEMDEBUG_BCM53400_A0r_fields,
  47203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47204         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47205         -1,
  47206         -1,
  47207     },
  47208 #endif /* chips */
  47209 
  47210 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47211     { /* SOC_REG_INT_QSTRUCT_FAP_MEMDEBUG_STACKr */
  47212         soc_block_list[4],
  47213         soc_genreg,
  47214         1,
  47215         0,
  47216         0xaa001000,
  47217         0,
  47218         0,
  47219         1,
  47220         soc_ING_VLAN_TAG_ACTION_PROFILE_DATA_DBGCTRLr_fields,
  47221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47222         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47223         -1,
  47224         -1,
  47225     },
  47226 #endif /* chips */
  47227 
  47228 #if defined(BCM_56270_A0)
  47229     { /* SOC_REG_INT_QSTRUCT_FAP_MEMDEBUG_STACK_BCM56270_A0r */
  47230         soc_block_list[4],
  47231         soc_genreg,
  47232         1,
  47233         0,
  47234         0xaa001000,
  47235         0,
  47236         0,
  47237         1,
  47238         soc_DSCP_CONTROLr_fields,
  47239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47240         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47241         -1,
  47242         -1,
  47243     },
  47244 #endif /* chips */
  47245 
  47246 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47247     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ECC_STATUSr */
  47248         soc_block_list[4],
  47249         soc_genreg,
  47250         2,
  47251         0,
  47252         0xaa001600,
  47253         SOC_REG_FLAG_ARRAY,
  47254         0,
  47255         2,
  47256         soc_QSTRUCT_FAP_MEM_ECC_STATUSr_fields,
  47257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47258         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  47259         -1,
  47260         -1,
  47261     },
  47262 #endif /* chips */
  47263 
  47264 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47265     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ECC_STATUS_0r */
  47266         soc_block_list[4],
  47267         soc_genreg,
  47268         1,
  47269         0,
  47270         0x2a08003a,
  47271         0,
  47272         0,
  47273         2,
  47274         soc_QSTRUCT_FAP_MEM_ECC_STATUS_0r_fields,
  47275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47276         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  47277         -1,
  47278         -1,
  47279     },
  47280 #endif /* chips */
  47281 
  47282 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47283     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ECC_STATUS_1r */
  47284         soc_block_list[4],
  47285         soc_genreg,
  47286         1,
  47287         0,
  47288         0x2a08003b,
  47289         0,
  47290         0,
  47291         2,
  47292         soc_QSTRUCT_FAP_MEM_ECC_STATUS_0r_fields,
  47293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47294         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  47295         -1,
  47296         -1,
  47297     },
  47298 #endif /* chips */
  47299 
  47300 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47301     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ECC_STATUS_2r */
  47302         soc_block_list[4],
  47303         soc_genreg,
  47304         1,
  47305         0,
  47306         0x2a08003c,
  47307         0,
  47308         0,
  47309         2,
  47310         soc_QSTRUCT_FAP_MEM_ECC_STATUS_0r_fields,
  47311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47312         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  47313         -1,
  47314         -1,
  47315     },
  47316 #endif /* chips */
  47317 
  47318 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47319     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ECC_STATUS_3r */
  47320         soc_block_list[4],
  47321         soc_genreg,
  47322         1,
  47323         0,
  47324         0x2a08003d,
  47325         0,
  47326         0,
  47327         2,
  47328         soc_QSTRUCT_FAP_MEM_ECC_STATUS_0r_fields,
  47329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47330         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  47331         -1,
  47332         -1,
  47333     },
  47334 #endif /* chips */
  47335 
  47336 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47337     defined(BCM_56450_B1)
  47338     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ECC_STATUS_0_BCM56450_A0r */
  47339         soc_block_list[4],
  47340         soc_genreg,
  47341         1,
  47342         0,
  47343         0xaa003800,
  47344         0,
  47345         0,
  47346         2,
  47347         soc_QSTRUCT_FAP_MEM_ECC_STATUS_0_BCM56450_A0r_fields,
  47348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47349         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  47350         -1,
  47351         -1,
  47352     },
  47353 #endif /* chips */
  47354 
  47355 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47356     defined(BCM_56450_B1)
  47357     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ECC_STATUS_1_BCM56450_A0r */
  47358         soc_block_list[4],
  47359         soc_genreg,
  47360         1,
  47361         0,
  47362         0xaa003900,
  47363         0,
  47364         0,
  47365         2,
  47366         soc_QSTRUCT_FAP_MEM_ECC_STATUS_0_BCM56450_A0r_fields,
  47367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47368         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  47369         -1,
  47370         -1,
  47371     },
  47372 #endif /* chips */
  47373 
  47374 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47375     defined(BCM_56450_B1)
  47376     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ECC_STATUS_2_BCM56450_A0r */
  47377         soc_block_list[4],
  47378         soc_genreg,
  47379         1,
  47380         0,
  47381         0xaa003a00,
  47382         0,
  47383         0,
  47384         2,
  47385         soc_QSTRUCT_FAP_MEM_ECC_STATUS_0_BCM56450_A0r_fields,
  47386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47387         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  47388         -1,
  47389         -1,
  47390     },
  47391 #endif /* chips */
  47392 
  47393 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47394     defined(BCM_56450_B1)
  47395     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ECC_STATUS_3_BCM56450_A0r */
  47396         soc_block_list[4],
  47397         soc_genreg,
  47398         1,
  47399         0,
  47400         0xaa003b00,
  47401         0,
  47402         0,
  47403         2,
  47404         soc_QSTRUCT_FAP_MEM_ECC_STATUS_0_BCM56450_A0r_fields,
  47405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47406         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  47407         -1,
  47408         -1,
  47409     },
  47410 #endif /* chips */
  47411 
  47412 #if defined(BCM_56270_A0)
  47413     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ECC_STATUS_BCM56270_A0r */
  47414         soc_block_list[4],
  47415         soc_genreg,
  47416         2,
  47417         0,
  47418         0xaa001500,
  47419         SOC_REG_FLAG_ARRAY,
  47420         0,
  47421         2,
  47422         soc_QSTRUCT_FAP_MEM_ECC_STATUS_BCM56270_A0r_fields,
  47423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47424         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  47425         -1,
  47426         -1,
  47427     },
  47428 #endif /* chips */
  47429 
  47430 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47431     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ERRORr */
  47432         soc_block_list[4],
  47433         soc_genreg,
  47434         1,
  47435         0,
  47436         0x2a080044,
  47437         0,
  47438         0,
  47439         21,
  47440         soc_QSTRUCT_FAP_MEM_ERRORr_fields,
  47441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47442         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  47443         -1,
  47444         -1,
  47445     },
  47446 #endif /* chips */
  47447 
  47448 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47449     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ERROR_BCM56260_A0r */
  47450         soc_block_list[4],
  47451         soc_genreg,
  47452         1,
  47453         0,
  47454         0xaa001c00,
  47455         0,
  47456         0,
  47457         15,
  47458         soc_QSTRUCT_FAP_MEM_ERROR_BCM56260_A0r_fields,
  47459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47460         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  47461         -1,
  47462         -1,
  47463     },
  47464 #endif /* chips */
  47465 
  47466 #if defined(BCM_56270_A0)
  47467     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ERROR_BCM56270_A0r */
  47468         soc_block_list[4],
  47469         soc_genreg,
  47470         1,
  47471         0,
  47472         0xaa001b00,
  47473         0,
  47474         0,
  47475         15,
  47476         soc_QSTRUCT_FAP_MEM_ERROR_BCM56260_A0r_fields,
  47477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47478         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  47479         -1,
  47480         -1,
  47481     },
  47482 #endif /* chips */
  47483 
  47484 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47485     defined(BCM_56450_B1)
  47486     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ERROR_BCM56450_A0r */
  47487         soc_block_list[4],
  47488         soc_genreg,
  47489         1,
  47490         0,
  47491         0xaa004200,
  47492         0,
  47493         0,
  47494         21,
  47495         soc_QSTRUCT_FAP_MEM_ERROR_BCM56450_A0r_fields,
  47496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47497         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  47498         -1,
  47499         -1,
  47500     },
  47501 #endif /* chips */
  47502 
  47503 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47504     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ERROR_MASKr */
  47505         soc_block_list[4],
  47506         soc_genreg,
  47507         1,
  47508         0,
  47509         0x2a080045,
  47510         0,
  47511         0,
  47512         21,
  47513         soc_QSTRUCT_FAP_MEM_ERROR_MASKr_fields,
  47514         SOC_RESET_VAL_DEC(0x001fffff, 0x00000000)
  47515         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  47516         -1,
  47517         -1,
  47518     },
  47519 #endif /* chips */
  47520 
  47521 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47522     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ERROR_MASK_BCM56260_A0r */
  47523         soc_block_list[4],
  47524         soc_genreg,
  47525         1,
  47526         0,
  47527         0xaa001d00,
  47528         0,
  47529         0,
  47530         15,
  47531         soc_QSTRUCT_FAP_MEM_ERROR_MASK_BCM56260_A0r_fields,
  47532         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  47533         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  47534         -1,
  47535         -1,
  47536     },
  47537 #endif /* chips */
  47538 
  47539 #if defined(BCM_56270_A0)
  47540     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ERROR_MASK_BCM56270_A0r */
  47541         soc_block_list[4],
  47542         soc_genreg,
  47543         1,
  47544         0,
  47545         0xaa001c00,
  47546         0,
  47547         0,
  47548         15,
  47549         soc_QSTRUCT_FAP_MEM_ERROR_MASK_BCM56260_A0r_fields,
  47550         SOC_RESET_VAL_DEC(0x00007fff, 0x00000000)
  47551         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  47552         -1,
  47553         -1,
  47554     },
  47555 #endif /* chips */
  47556 
  47557 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47558     defined(BCM_56450_B1)
  47559     { /* SOC_REG_INT_QSTRUCT_FAP_MEM_ERROR_MASK_BCM56450_A0r */
  47560         soc_block_list[4],
  47561         soc_genreg,
  47562         1,
  47563         0,
  47564         0xaa004300,
  47565         0,
  47566         0,
  47567         21,
  47568         soc_QSTRUCT_FAP_MEM_ERROR_MASK_BCM56450_A0r_fields,
  47569         SOC_RESET_VAL_DEC(0x001fffff, 0x00000000)
  47570         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  47571         -1,
  47572         -1,
  47573     },
  47574 #endif /* chips */
  47575 
  47576 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47577     { /* SOC_REG_INT_QSTRUCT_FAP_STACK_ECC_DEBUGr */
  47578         soc_block_list[4],
  47579         soc_genreg,
  47580         1,
  47581         0,
  47582         0x2a08004f,
  47583         0,
  47584         0,
  47585         8,
  47586         soc_QSTRUCT_FAP_STACK_ECC_DEBUGr_fields,
  47587         SOC_RESET_VAL_DEC(0x00000055, 0x00000000)
  47588         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47589         -1,
  47590         -1,
  47591     },
  47592 #endif /* chips */
  47593 
  47594 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47595     { /* SOC_REG_INT_QSTRUCT_FAP_STACK_ECC_DEBUG_BCM56260_A0r */
  47596         soc_block_list[4],
  47597         soc_genreg,
  47598         1,
  47599         0,
  47600         0xaa002400,
  47601         0,
  47602         0,
  47603         4,
  47604         soc_QSTRUCT_FAP_STACK_ECC_DEBUG_BCM56260_A0r_fields,
  47605         SOC_RESET_VAL_DEC(0x00000009, 0x00000000)
  47606         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47607         -1,
  47608         -1,
  47609     },
  47610 #endif /* chips */
  47611 
  47612 #if defined(BCM_56270_A0)
  47613     { /* SOC_REG_INT_QSTRUCT_FAP_STACK_ECC_DEBUG_BCM56270_A0r */
  47614         soc_block_list[4],
  47615         soc_genreg,
  47616         1,
  47617         0,
  47618         0xaa002300,
  47619         0,
  47620         0,
  47621         4,
  47622         soc_QSTRUCT_FAP_STACK_ECC_DEBUG_BCM56260_A0r_fields,
  47623         SOC_RESET_VAL_DEC(0x00000009, 0x00000000)
  47624         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47625         -1,
  47626         -1,
  47627     },
  47628 #endif /* chips */
  47629 
  47630 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47631     defined(BCM_56450_B1)
  47632     { /* SOC_REG_INT_QSTRUCT_FAP_STACK_ECC_DEBUG_BCM56450_A0r */
  47633         soc_block_list[4],
  47634         soc_genreg,
  47635         1,
  47636         0,
  47637         0xaa004d00,
  47638         0,
  47639         0,
  47640         8,
  47641         soc_QSTRUCT_FAP_STACK_ECC_DEBUG_BCM56450_A0r_fields,
  47642         SOC_RESET_VAL_DEC(0x00000055, 0x00000000)
  47643         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  47644         -1,
  47645         -1,
  47646     },
  47647 #endif /* chips */
  47648 
  47649 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47650     { /* SOC_REG_INT_QSTRUCT_FAP_WATERMARKr */
  47651         soc_block_list[4],
  47652         soc_genreg,
  47653         2,
  47654         0,
  47655         0xaa002000,
  47656         SOC_REG_FLAG_ARRAY,
  47657         0,
  47658         1,
  47659         soc_QSTRUCT_FAP_WATERMARKr_fields,
  47660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47661         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47662         -1,
  47663         -1,
  47664     },
  47665 #endif /* chips */
  47666 
  47667 #if defined(BCM_56270_A0)
  47668     { /* SOC_REG_INT_QSTRUCT_FAP_WATERMARK_BCM56270_A0r */
  47669         soc_block_list[4],
  47670         soc_genreg,
  47671         2,
  47672         0,
  47673         0xaa001f00,
  47674         SOC_REG_FLAG_ARRAY,
  47675         0,
  47676         1,
  47677         soc_QSTRUCT_FAP_WATERMARK_BCM56270_A0r_fields,
  47678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47679         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47680         -1,
  47681         -1,
  47682     },
  47683 #endif /* chips */
  47684 
  47685 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47686     { /* SOC_REG_INT_QSTRUCT_INTERRUPTr */
  47687         soc_block_list[4],
  47688         soc_genreg,
  47689         1,
  47690         0,
  47691         0x2a080046,
  47692         0,
  47693         0,
  47694         4,
  47695         soc_QSTRUCT_INTERRUPTr_fields,
  47696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47697         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  47698         -1,
  47699         -1,
  47700     },
  47701 #endif /* chips */
  47702 
  47703 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47704     { /* SOC_REG_INT_QSTRUCT_INTERRUPT_BCM56260_A0r */
  47705         soc_block_list[4],
  47706         soc_genreg,
  47707         1,
  47708         0,
  47709         0xaa001e00,
  47710         0,
  47711         0,
  47712         3,
  47713         soc_QSTRUCT_INTERRUPT_BCM56260_A0r_fields,
  47714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47715         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  47716         -1,
  47717         -1,
  47718     },
  47719 #endif /* chips */
  47720 
  47721 #if defined(BCM_56270_A0)
  47722     { /* SOC_REG_INT_QSTRUCT_INTERRUPT_BCM56270_A0r */
  47723         soc_block_list[4],
  47724         soc_genreg,
  47725         1,
  47726         0,
  47727         0xaa001d00,
  47728         0,
  47729         0,
  47730         3,
  47731         soc_QSTRUCT_INTERRUPT_BCM56260_A0r_fields,
  47732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47733         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  47734         -1,
  47735         -1,
  47736     },
  47737 #endif /* chips */
  47738 
  47739 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47740     defined(BCM_56450_B1)
  47741     { /* SOC_REG_INT_QSTRUCT_INTERRUPT_BCM56450_A0r */
  47742         soc_block_list[4],
  47743         soc_genreg,
  47744         1,
  47745         0,
  47746         0xaa004400,
  47747         0,
  47748         0,
  47749         4,
  47750         soc_QSTRUCT_INTERRUPT_BCM56450_A0r_fields,
  47751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47752         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  47753         -1,
  47754         -1,
  47755     },
  47756 #endif /* chips */
  47757 
  47758 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47759     { /* SOC_REG_INT_QSTRUCT_INTERRUPT_MASKr */
  47760         soc_block_list[4],
  47761         soc_genreg,
  47762         1,
  47763         0,
  47764         0x2a080047,
  47765         0,
  47766         0,
  47767         4,
  47768         soc_QSTRUCT_INTERRUPT_MASKr_fields,
  47769         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  47770         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  47771         -1,
  47772         -1,
  47773     },
  47774 #endif /* chips */
  47775 
  47776 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47777     { /* SOC_REG_INT_QSTRUCT_INTERRUPT_MASK_BCM56260_A0r */
  47778         soc_block_list[4],
  47779         soc_genreg,
  47780         1,
  47781         0,
  47782         0xaa001f00,
  47783         0,
  47784         0,
  47785         3,
  47786         soc_QSTRUCT_INTERRUPT_MASK_BCM56260_A0r_fields,
  47787         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  47788         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  47789         -1,
  47790         -1,
  47791     },
  47792 #endif /* chips */
  47793 
  47794 #if defined(BCM_56270_A0)
  47795     { /* SOC_REG_INT_QSTRUCT_INTERRUPT_MASK_BCM56270_A0r */
  47796         soc_block_list[4],
  47797         soc_genreg,
  47798         1,
  47799         0,
  47800         0xaa001e00,
  47801         0,
  47802         0,
  47803         3,
  47804         soc_QSTRUCT_INTERRUPT_MASK_BCM56260_A0r_fields,
  47805         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  47806         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  47807         -1,
  47808         -1,
  47809     },
  47810 #endif /* chips */
  47811 
  47812 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47813     defined(BCM_56450_B1)
  47814     { /* SOC_REG_INT_QSTRUCT_INTERRUPT_MASK_BCM56450_A0r */
  47815         soc_block_list[4],
  47816         soc_genreg,
  47817         1,
  47818         0,
  47819         0xaa004500,
  47820         0,
  47821         0,
  47822         4,
  47823         soc_QSTRUCT_INTERRUPT_MASK_BCM56450_A0r_fields,
  47824         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  47825         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  47826         -1,
  47827         -1,
  47828     },
  47829 #endif /* chips */
  47830 
  47831 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47832     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ECC_DEBUGr */
  47833         soc_block_list[4],
  47834         soc_genreg,
  47835         1,
  47836         0,
  47837         0x2a08004e,
  47838         0,
  47839         0,
  47840         16,
  47841         soc_QSTRUCT_QBLOCK_NEXT_ECC_DEBUGr_fields,
  47842         SOC_RESET_VAL_DEC(0x00005555, 0x00000000)
  47843         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47844         -1,
  47845         -1,
  47846     },
  47847 #endif /* chips */
  47848 
  47849 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47850     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ECC_DEBUG_BCM56260_A0r */
  47851         soc_block_list[4],
  47852         soc_genreg,
  47853         1,
  47854         0,
  47855         0xaa002300,
  47856         0,
  47857         0,
  47858         2,
  47859         soc_QSTRUCT_QBLOCK_NEXT_ECC_DEBUG_BCM56260_A0r_fields,
  47860         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  47861         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  47862         -1,
  47863         -1,
  47864     },
  47865 #endif /* chips */
  47866 
  47867 #if defined(BCM_56270_A0)
  47868     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ECC_DEBUG_BCM56270_A0r */
  47869         soc_block_list[4],
  47870         soc_genreg,
  47871         1,
  47872         0,
  47873         0xaa002200,
  47874         0,
  47875         0,
  47876         2,
  47877         soc_QSTRUCT_QBLOCK_NEXT_ECC_DEBUG_BCM56260_A0r_fields,
  47878         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  47879         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  47880         -1,
  47881         -1,
  47882     },
  47883 #endif /* chips */
  47884 
  47885 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47886     defined(BCM_56450_B1)
  47887     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ECC_DEBUG_BCM56450_A0r */
  47888         soc_block_list[4],
  47889         soc_genreg,
  47890         1,
  47891         0,
  47892         0xaa004c00,
  47893         0,
  47894         0,
  47895         16,
  47896         soc_QSTRUCT_QBLOCK_NEXT_ECC_DEBUG_BCM56450_A0r_fields,
  47897         SOC_RESET_VAL_DEC(0x00005555, 0x00000000)
  47898         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47899         -1,
  47900         -1,
  47901     },
  47902 #endif /* chips */
  47903 
  47904 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47905     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ERRORr */
  47906         soc_block_list[4],
  47907         soc_genreg,
  47908         1,
  47909         0,
  47910         0x2a080042,
  47911         0,
  47912         0,
  47913         16,
  47914         soc_QSTRUCT_QBLOCK_NEXT_ERRORr_fields,
  47915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47916         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47917         -1,
  47918         -1,
  47919     },
  47920 #endif /* chips */
  47921 
  47922 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47923     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ERROR_0r */
  47924         soc_block_list[4],
  47925         soc_genreg,
  47926         1,
  47927         0,
  47928         0xaa001a00,
  47929         0,
  47930         0,
  47931         2,
  47932         soc_QSTRUCT_QBLOCK_NEXT_ERROR_0r_fields,
  47933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47934         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  47935         -1,
  47936         -1,
  47937     },
  47938 #endif /* chips */
  47939 
  47940 #if defined(BCM_56270_A0)
  47941     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ERROR_0_BCM56270_A0r */
  47942         soc_block_list[4],
  47943         soc_genreg,
  47944         1,
  47945         0,
  47946         0xaa001900,
  47947         0,
  47948         0,
  47949         2,
  47950         soc_QSTRUCT_QBLOCK_NEXT_ERROR_0r_fields,
  47951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47952         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  47953         -1,
  47954         -1,
  47955     },
  47956 #endif /* chips */
  47957 
  47958 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  47959     defined(BCM_56450_B1)
  47960     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ERROR_BCM56450_A0r */
  47961         soc_block_list[4],
  47962         soc_genreg,
  47963         1,
  47964         0,
  47965         0xaa004000,
  47966         0,
  47967         0,
  47968         16,
  47969         soc_QSTRUCT_QBLOCK_NEXT_ERROR_BCM56450_A0r_fields,
  47970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47971         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47972         -1,
  47973         -1,
  47974     },
  47975 #endif /* chips */
  47976 
  47977 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  47978     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ERROR_MASKr */
  47979         soc_block_list[4],
  47980         soc_genreg,
  47981         1,
  47982         0,
  47983         0x2a080043,
  47984         0,
  47985         0,
  47986         16,
  47987         soc_QSTRUCT_QBLOCK_NEXT_ERROR_MASKr_fields,
  47988         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  47989         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  47990         -1,
  47991         -1,
  47992     },
  47993 #endif /* chips */
  47994 
  47995 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  47996     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ERROR_MASK_0r */
  47997         soc_block_list[4],
  47998         soc_genreg,
  47999         1,
  48000         0,
  48001         0xaa001b00,
  48002         0,
  48003         0,
  48004         2,
  48005         soc_QSTRUCT_QBLOCK_NEXT_ERROR_MASK_0r_fields,
  48006         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  48007         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  48008         -1,
  48009         -1,
  48010     },
  48011 #endif /* chips */
  48012 
  48013 #if defined(BCM_56270_A0)
  48014     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ERROR_MASK_0_BCM56270_A0r */
  48015         soc_block_list[4],
  48016         soc_genreg,
  48017         1,
  48018         0,
  48019         0xaa001a00,
  48020         0,
  48021         0,
  48022         2,
  48023         soc_QSTRUCT_QBLOCK_NEXT_ERROR_MASK_0r_fields,
  48024         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  48025         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  48026         -1,
  48027         -1,
  48028     },
  48029 #endif /* chips */
  48030 
  48031 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48032     defined(BCM_56450_B1)
  48033     { /* SOC_REG_INT_QSTRUCT_QBLOCK_NEXT_ERROR_MASK_BCM56450_A0r */
  48034         soc_block_list[4],
  48035         soc_genreg,
  48036         1,
  48037         0,
  48038         0xaa004100,
  48039         0,
  48040         0,
  48041         16,
  48042         soc_QSTRUCT_QBLOCK_NEXT_ERROR_MASK_BCM56450_A0r_fields,
  48043         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  48044         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48045         -1,
  48046         -1,
  48047     },
  48048 #endif /* chips */
  48049 
  48050 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48051     { /* SOC_REG_INT_QSTRUCT_QENTRY_ECC_DEBUGr */
  48052         soc_block_list[4],
  48053         soc_genreg,
  48054         1,
  48055         0,
  48056         0xaa002200,
  48057         0,
  48058         0,
  48059         2,
  48060         soc_QSTRUCT_QENTRY_ECC_DEBUGr_fields,
  48061         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  48062         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  48063         -1,
  48064         -1,
  48065     },
  48066 #endif /* chips */
  48067 
  48068 #if defined(BCM_56270_A0)
  48069     { /* SOC_REG_INT_QSTRUCT_QENTRY_ECC_DEBUG_BCM56270_A0r */
  48070         soc_block_list[4],
  48071         soc_genreg,
  48072         1,
  48073         0,
  48074         0xaa002100,
  48075         0,
  48076         0,
  48077         2,
  48078         soc_QSTRUCT_QENTRY_ECC_DEBUGr_fields,
  48079         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  48080         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  48081         -1,
  48082         -1,
  48083     },
  48084 #endif /* chips */
  48085 
  48086 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48087     { /* SOC_REG_INT_QSTRUCT_QENTRY_ERROR_0r */
  48088         soc_block_list[4],
  48089         soc_genreg,
  48090         1,
  48091         0,
  48092         0xaa001800,
  48093         0,
  48094         0,
  48095         2,
  48096         soc_QSTRUCT_QBLOCK_NEXT_ERROR_0r_fields,
  48097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48098         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  48099         -1,
  48100         -1,
  48101     },
  48102 #endif /* chips */
  48103 
  48104 #if defined(BCM_56270_A0)
  48105     { /* SOC_REG_INT_QSTRUCT_QENTRY_ERROR_0_BCM56270_A0r */
  48106         soc_block_list[4],
  48107         soc_genreg,
  48108         1,
  48109         0,
  48110         0xaa001700,
  48111         0,
  48112         0,
  48113         2,
  48114         soc_QSTRUCT_QBLOCK_NEXT_ERROR_0r_fields,
  48115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48116         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  48117         -1,
  48118         -1,
  48119     },
  48120 #endif /* chips */
  48121 
  48122 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
  48123     { /* SOC_REG_INT_QSTRUCT_QENTRY_ERROR_MASK_0r */
  48124         soc_block_list[4],
  48125         soc_genreg,
  48126         1,
  48127         0,
  48128         0xaa001900,
  48129         0,
  48130         0,
  48131         2,
  48132         soc_QSTRUCT_QBLOCK_NEXT_ERROR_MASK_0r_fields,
  48133         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  48134         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  48135         -1,
  48136         -1,
  48137     },
  48138 #endif /* chips */
  48139 
  48140 #if defined(BCM_56270_A0)
  48141     { /* SOC_REG_INT_QSTRUCT_QENTRY_ERROR_MASK_0_BCM56270_A0r */
  48142         soc_block_list[4],
  48143         soc_genreg,
  48144         1,
  48145         0,
  48146         0xaa001800,
  48147         0,
  48148         0,
  48149         2,
  48150         soc_QSTRUCT_QBLOCK_NEXT_ERROR_MASK_0r_fields,
  48151         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  48152         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  48153         -1,
  48154         -1,
  48155     },
  48156 #endif /* chips */
  48157 
  48158 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48159     { /* SOC_REG_INT_QSTRUCT_QENTRY_LOWER_ECC_DEBUGr */
  48160         soc_block_list[4],
  48161         soc_genreg,
  48162         1,
  48163         0,
  48164         0x2a08004d,
  48165         0,
  48166         0,
  48167         16,
  48168         soc_QSTRUCT_QENTRY_LOWER_ECC_DEBUGr_fields,
  48169         SOC_RESET_VAL_DEC(0x00005555, 0x00000000)
  48170         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48171         -1,
  48172         -1,
  48173     },
  48174 #endif /* chips */
  48175 
  48176 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48177     defined(BCM_56450_B1)
  48178     { /* SOC_REG_INT_QSTRUCT_QENTRY_LOWER_ECC_DEBUG_BCM56450_A0r */
  48179         soc_block_list[4],
  48180         soc_genreg,
  48181         1,
  48182         0,
  48183         0xaa004b00,
  48184         0,
  48185         0,
  48186         16,
  48187         soc_QSTRUCT_QENTRY_LOWER_ECC_DEBUG_BCM56450_A0r_fields,
  48188         SOC_RESET_VAL_DEC(0x00005555, 0x00000000)
  48189         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48190         -1,
  48191         -1,
  48192     },
  48193 #endif /* chips */
  48194 
  48195 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48196     { /* SOC_REG_INT_QSTRUCT_QENTRY_LOWER_ERRORr */
  48197         soc_block_list[4],
  48198         soc_genreg,
  48199         1,
  48200         0,
  48201         0x2a080040,
  48202         0,
  48203         0,
  48204         16,
  48205         soc_QSTRUCT_QBLOCK_NEXT_ERRORr_fields,
  48206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48207         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48208         -1,
  48209         -1,
  48210     },
  48211 #endif /* chips */
  48212 
  48213 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48214     defined(BCM_56450_B1)
  48215     { /* SOC_REG_INT_QSTRUCT_QENTRY_LOWER_ERROR_BCM56450_A0r */
  48216         soc_block_list[4],
  48217         soc_genreg,
  48218         1,
  48219         0,
  48220         0xaa003e00,
  48221         0,
  48222         0,
  48223         16,
  48224         soc_QSTRUCT_QBLOCK_NEXT_ERROR_BCM56450_A0r_fields,
  48225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48226         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48227         -1,
  48228         -1,
  48229     },
  48230 #endif /* chips */
  48231 
  48232 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48233     { /* SOC_REG_INT_QSTRUCT_QENTRY_LOWER_ERROR_MASKr */
  48234         soc_block_list[4],
  48235         soc_genreg,
  48236         1,
  48237         0,
  48238         0x2a080041,
  48239         0,
  48240         0,
  48241         16,
  48242         soc_QSTRUCT_QBLOCK_NEXT_ERROR_MASKr_fields,
  48243         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  48244         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48245         -1,
  48246         -1,
  48247     },
  48248 #endif /* chips */
  48249 
  48250 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48251     defined(BCM_56450_B1)
  48252     { /* SOC_REG_INT_QSTRUCT_QENTRY_LOWER_ERROR_MASK_BCM56450_A0r */
  48253         soc_block_list[4],
  48254         soc_genreg,
  48255         1,
  48256         0,
  48257         0xaa003f00,
  48258         0,
  48259         0,
  48260         16,
  48261         soc_QSTRUCT_QBLOCK_NEXT_ERROR_MASK_BCM56450_A0r_fields,
  48262         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  48263         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48264         -1,
  48265         -1,
  48266     },
  48267 #endif /* chips */
  48268 
  48269 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48270     { /* SOC_REG_INT_QSTRUCT_QENTRY_UPPER_ECC_DEBUGr */
  48271         soc_block_list[4],
  48272         soc_genreg,
  48273         1,
  48274         0,
  48275         0x2a08004c,
  48276         0,
  48277         0,
  48278         16,
  48279         soc_QSTRUCT_QENTRY_UPPER_ECC_DEBUGr_fields,
  48280         SOC_RESET_VAL_DEC(0x00005555, 0x00000000)
  48281         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48282         -1,
  48283         -1,
  48284     },
  48285 #endif /* chips */
  48286 
  48287 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48288     defined(BCM_56450_B1)
  48289     { /* SOC_REG_INT_QSTRUCT_QENTRY_UPPER_ECC_DEBUG_BCM56450_A0r */
  48290         soc_block_list[4],
  48291         soc_genreg,
  48292         1,
  48293         0,
  48294         0xaa004a00,
  48295         0,
  48296         0,
  48297         16,
  48298         soc_QSTRUCT_QENTRY_UPPER_ECC_DEBUG_BCM56450_A0r_fields,
  48299         SOC_RESET_VAL_DEC(0x00005555, 0x00000000)
  48300         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48301         -1,
  48302         -1,
  48303     },
  48304 #endif /* chips */
  48305 
  48306 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48307     { /* SOC_REG_INT_QSTRUCT_QENTRY_UPPER_ERRORr */
  48308         soc_block_list[4],
  48309         soc_genreg,
  48310         1,
  48311         0,
  48312         0x2a08003e,
  48313         0,
  48314         0,
  48315         16,
  48316         soc_QSTRUCT_QBLOCK_NEXT_ERRORr_fields,
  48317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48318         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48319         -1,
  48320         -1,
  48321     },
  48322 #endif /* chips */
  48323 
  48324 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48325     defined(BCM_56450_B1)
  48326     { /* SOC_REG_INT_QSTRUCT_QENTRY_UPPER_ERROR_BCM56450_A0r */
  48327         soc_block_list[4],
  48328         soc_genreg,
  48329         1,
  48330         0,
  48331         0xaa003c00,
  48332         0,
  48333         0,
  48334         16,
  48335         soc_QSTRUCT_QBLOCK_NEXT_ERROR_BCM56450_A0r_fields,
  48336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48337         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48338         -1,
  48339         -1,
  48340     },
  48341 #endif /* chips */
  48342 
  48343 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48344     { /* SOC_REG_INT_QSTRUCT_QENTRY_UPPER_ERROR_MASKr */
  48345         soc_block_list[4],
  48346         soc_genreg,
  48347         1,
  48348         0,
  48349         0x2a08003f,
  48350         0,
  48351         0,
  48352         16,
  48353         soc_QSTRUCT_QBLOCK_NEXT_ERROR_MASKr_fields,
  48354         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  48355         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48356         -1,
  48357         -1,
  48358     },
  48359 #endif /* chips */
  48360 
  48361 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  48362     defined(BCM_56450_B1)
  48363     { /* SOC_REG_INT_QSTRUCT_QENTRY_UPPER_ERROR_MASK_BCM56450_A0r */
  48364         soc_block_list[4],
  48365         soc_genreg,
  48366         1,
  48367         0,
  48368         0xaa003d00,
  48369         0,
  48370         0,
  48371         16,
  48372         soc_QSTRUCT_QBLOCK_NEXT_ERROR_MASK_BCM56450_A0r_fields,
  48373         SOC_RESET_VAL_DEC(0x0000ffff, 0x00000000)
  48374         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  48375         -1,
  48376         -1,
  48377     },
  48378 #endif /* chips */
  48379 
  48380 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48381     { /* SOC_REG_INT_QUAD0_SERDES_CTRLr */
  48382         soc_block_list[2],
  48383         soc_genreg,
  48384         1,
  48385         0,
  48386         0x80043,
  48387         0,
  48388         0,
  48389         12,
  48390         soc_QUAD0_SERDES_CTRLr_fields,
  48391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48392         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48393         -1,
  48394         -1,
  48395     },
  48396 #endif /* chips */
  48397 
  48398 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48399     { /* SOC_REG_INT_QUAD0_SERDES_STATUS0r */
  48400         soc_block_list[2],
  48401         soc_genreg,
  48402         1,
  48403         0,
  48404         0x80045,
  48405         SOC_REG_FLAG_RO,
  48406         0,
  48407         9,
  48408         soc_QUAD0_SERDES_STATUS0r_fields,
  48409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48410         SOC_RESET_MASK_DEC(0xe0000000, 0x00000000)
  48411         -1,
  48412         -1,
  48413     },
  48414 #endif /* chips */
  48415 
  48416 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48417     { /* SOC_REG_INT_QUAD0_SERDES_STATUS1r */
  48418         soc_block_list[2],
  48419         soc_genreg,
  48420         1,
  48421         0,
  48422         0x80046,
  48423         SOC_REG_FLAG_RO,
  48424         0,
  48425         3,
  48426         soc_QUAD0_SERDES_STATUS1r_fields,
  48427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48428         SOC_RESET_MASK_DEC(0xffffff00, 0x00000000)
  48429         -1,
  48430         -1,
  48431     },
  48432 #endif /* chips */
  48433 
  48434 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48435     { /* SOC_REG_INT_QUAD1_SERDES_CTRLr */
  48436         soc_block_list[2],
  48437         soc_genreg,
  48438         1,
  48439         0,
  48440         0x80044,
  48441         0,
  48442         0,
  48443         12,
  48444         soc_QUAD0_SERDES_CTRLr_fields,
  48445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48446         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48447         -1,
  48448         -1,
  48449     },
  48450 #endif /* chips */
  48451 
  48452 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48453     { /* SOC_REG_INT_QUAD1_SERDES_STATUS0r */
  48454         soc_block_list[2],
  48455         soc_genreg,
  48456         1,
  48457         0,
  48458         0x80047,
  48459         SOC_REG_FLAG_RO,
  48460         0,
  48461         9,
  48462         soc_QUAD0_SERDES_STATUS0r_fields,
  48463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48464         SOC_RESET_MASK_DEC(0xe0000000, 0x00000000)
  48465         -1,
  48466         -1,
  48467     },
  48468 #endif /* chips */
  48469 
  48470 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  48471     { /* SOC_REG_INT_QUAD1_SERDES_STATUS1r */
  48472         soc_block_list[2],
  48473         soc_genreg,
  48474         1,
  48475         0,
  48476         0x80048,
  48477         SOC_REG_FLAG_RO,
  48478         0,
  48479         3,
  48480         soc_QUAD0_SERDES_STATUS1r_fields,
  48481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48482         SOC_RESET_MASK_DEC(0xffffff00, 0x00000000)
  48483         -1,
  48484         -1,
  48485     },
  48486 #endif /* chips */
  48487 
  48488 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  48489     { /* SOC_REG_INT_Q_SCHED_CPU_L0_NODE_CONFIGr */
  48490         soc_block_list[125],
  48491         soc_genreg,
  48492         1,
  48493         0,
  48494         0x36001a00,
  48495         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48496         0,
  48497         3,
  48498         soc_Q_SCHED_CPU_L0_NODE_CONFIGr_fields,
  48499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48500         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  48501         -1,
  48502         -1,
  48503         3,
  48504     },
  48505 #endif /* chips */
  48506 
  48507 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  48508     { /* SOC_REG_INT_Q_SCHED_CPU_L0_NODE_CONFIG_BCM56870_A0r */
  48509         soc_block_list[125],
  48510         soc_genreg,
  48511         1,
  48512         0,
  48513         0x12005a00,
  48514         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48515         0,
  48516         3,
  48517         soc_Q_SCHED_CPU_L0_NODE_CONFIGr_fields,
  48518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48519         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  48520         -1,
  48521         -1,
  48522         3,
  48523     },
  48524 #endif /* chips */
  48525 
  48526 #if defined(BCM_56970_A0)
  48527     { /* SOC_REG_INT_Q_SCHED_CPU_L0_NODE_CONFIG_BCM56970_A0r */
  48528         soc_block_list[125],
  48529         soc_genreg,
  48530         1,
  48531         0,
  48532         0x12001a00,
  48533         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48534         0,
  48535         3,
  48536         soc_Q_SCHED_CPU_L0_NODE_CONFIGr_fields,
  48537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48538         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  48539         -1,
  48540         -1,
  48541         3,
  48542     },
  48543 #endif /* chips */
  48544 
  48545 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  48546     { /* SOC_REG_INT_Q_SCHED_CPU_L1_MC_QUEUE_CONFIGr */
  48547         soc_block_list[125],
  48548         soc_genreg,
  48549         1,
  48550         0,
  48551         0x36001c00,
  48552         SOC_REG_FLAG_64_BITS |
  48553                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48554         0,
  48555         1,
  48556         soc_Q_SCHED_CPU_L1_MC_QUEUE_CONFIGr_fields,
  48557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48558         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  48559         -1,
  48560         -1,
  48561         3,
  48562     },
  48563 #endif /* chips */
  48564 
  48565 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  48566     { /* SOC_REG_INT_Q_SCHED_CPU_L1_MC_QUEUE_CONFIG_BCM56870_A0r */
  48567         soc_block_list[125],
  48568         soc_genreg,
  48569         1,
  48570         0,
  48571         0x12005c00,
  48572         SOC_REG_FLAG_64_BITS |
  48573                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48574         0,
  48575         1,
  48576         soc_Q_SCHED_CPU_L1_MC_QUEUE_CONFIGr_fields,
  48577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48578         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  48579         -1,
  48580         -1,
  48581         3,
  48582     },
  48583 #endif /* chips */
  48584 
  48585 #if defined(BCM_56970_A0)
  48586     { /* SOC_REG_INT_Q_SCHED_CPU_L1_MC_QUEUE_CONFIG_BCM56970_A0r */
  48587         soc_block_list[125],
  48588         soc_genreg,
  48589         1,
  48590         0,
  48591         0x12001c00,
  48592         SOC_REG_FLAG_64_BITS |
  48593                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48594         0,
  48595         1,
  48596         soc_Q_SCHED_CPU_L1_MC_QUEUE_CONFIGr_fields,
  48597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48598         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  48599         -1,
  48600         -1,
  48601         3,
  48602     },
  48603 #endif /* chips */
  48604 
  48605 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  48606     { /* SOC_REG_INT_Q_SCHED_CPU_L1_MC_QUEUE_L0_MAPPINGr */
  48607         soc_block_list[125],
  48608         soc_genreg,
  48609         48,
  48610         0,
  48611         0x36001d00,
  48612         SOC_REG_FLAG_ARRAY |
  48613                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48614         0,
  48615         1,
  48616         soc_Q_SCHED_CPU_L1_MC_QUEUE_L0_MAPPINGr_fields,
  48617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48618         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  48619         -1,
  48620         -1,
  48621         3,
  48622     },
  48623 #endif /* chips */
  48624 
  48625 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  48626     { /* SOC_REG_INT_Q_SCHED_CPU_L1_MC_QUEUE_L0_MAPPING_BCM56870_A0r */
  48627         soc_block_list[125],
  48628         soc_genreg,
  48629         48,
  48630         0,
  48631         0x12005d00,
  48632         SOC_REG_FLAG_ARRAY |
  48633                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48634         0,
  48635         1,
  48636         soc_Q_SCHED_CPU_L1_MC_QUEUE_L0_MAPPINGr_fields,
  48637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48638         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  48639         -1,
  48640         -1,
  48641         3,
  48642     },
  48643 #endif /* chips */
  48644 
  48645 #if defined(BCM_56970_A0)
  48646     { /* SOC_REG_INT_Q_SCHED_CPU_L1_MC_QUEUE_L0_MAPPING_BCM56970_A0r */
  48647         soc_block_list[125],
  48648         soc_genreg,
  48649         48,
  48650         0,
  48651         0x12001d00,
  48652         SOC_REG_FLAG_ARRAY |
  48653                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48654         0,
  48655         1,
  48656         soc_Q_SCHED_CPU_L1_MC_QUEUE_L0_MAPPINGr_fields,
  48657         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48658         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  48659         -1,
  48660         -1,
  48661         3,
  48662     },
  48663 #endif /* chips */
  48664 
  48665 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  48666     { /* SOC_REG_INT_Q_SCHED_CPU_L1_MC_QUEUE_MASKr */
  48667         soc_block_list[125],
  48668         soc_genreg,
  48669         1,
  48670         0,
  48671         0x36001b00,
  48672         SOC_REG_FLAG_64_BITS |
  48673                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48674         0,
  48675         1,
  48676         soc_Q_SCHED_CPU_L1_MC_QUEUE_MASKr_fields,
  48677         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48678         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  48679         -1,
  48680         -1,
  48681         3,
  48682     },
  48683 #endif /* chips */
  48684 
  48685 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  48686     { /* SOC_REG_INT_Q_SCHED_CPU_L1_MC_QUEUE_MASK_BCM56870_A0r */
  48687         soc_block_list[125],
  48688         soc_genreg,
  48689         1,
  48690         0,
  48691         0x12005b00,
  48692         SOC_REG_FLAG_64_BITS |
  48693                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48694         0,
  48695         1,
  48696         soc_Q_SCHED_CPU_L1_MC_QUEUE_MASKr_fields,
  48697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48698         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  48699         -1,
  48700         -1,
  48701         3,
  48702     },
  48703 #endif /* chips */
  48704 
  48705 #if defined(BCM_56970_A0)
  48706     { /* SOC_REG_INT_Q_SCHED_CPU_L1_MC_QUEUE_MASK_BCM56970_A0r */
  48707         soc_block_list[125],
  48708         soc_genreg,
  48709         1,
  48710         0,
  48711         0x12001b00,
  48712         SOC_REG_FLAG_64_BITS |
  48713                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48714         0,
  48715         1,
  48716         soc_Q_SCHED_CPU_L1_MC_QUEUE_MASKr_fields,
  48717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48718         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  48719         -1,
  48720         -1,
  48721         3,
  48722     },
  48723 #endif /* chips */
  48724 
  48725 #if defined(BCM_56370_A0)
  48726     { /* SOC_REG_INT_Q_SCHED_CPU_L2_NODE_CONFIGr */
  48727         soc_block_list[125],
  48728         soc_genreg,
  48729         1,
  48730         0,
  48731         0x12005000,
  48732         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48733         0,
  48734         3,
  48735         soc_Q_SCHED_CPU_L0_NODE_CONFIGr_fields,
  48736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48737         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  48738         -1,
  48739         -1,
  48740         3,
  48741     },
  48742 #endif /* chips */
  48743 
  48744 #if defined(BCM_56370_A0)
  48745     { /* SOC_REG_INT_Q_SCHED_CPU_L3_MC_QUEUE_CONFIGr */
  48746         soc_block_list[125],
  48747         soc_genreg,
  48748         1,
  48749         0,
  48750         0x12005200,
  48751         SOC_REG_FLAG_64_BITS |
  48752                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48753         0,
  48754         1,
  48755         soc_Q_SCHED_CPU_L1_MC_QUEUE_CONFIGr_fields,
  48756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48757         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  48758         -1,
  48759         -1,
  48760         3,
  48761     },
  48762 #endif /* chips */
  48763 
  48764 #if defined(BCM_56370_A0)
  48765     { /* SOC_REG_INT_Q_SCHED_CPU_L3_MC_QUEUE_L2_MAPPINGr */
  48766         soc_block_list[125],
  48767         soc_genreg,
  48768         48,
  48769         0,
  48770         0x12005300,
  48771         SOC_REG_FLAG_ARRAY |
  48772                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48773         0,
  48774         1,
  48775         soc_Q_SCHED_CPU_L1_MC_QUEUE_L0_MAPPINGr_fields,
  48776         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48777         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  48778         -1,
  48779         -1,
  48780         3,
  48781     },
  48782 #endif /* chips */
  48783 
  48784 #if defined(BCM_56370_A0)
  48785     { /* SOC_REG_INT_Q_SCHED_CPU_L3_MC_QUEUE_MASKr */
  48786         soc_block_list[125],
  48787         soc_genreg,
  48788         1,
  48789         0,
  48790         0x12005100,
  48791         SOC_REG_FLAG_64_BITS |
  48792                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48793         0,
  48794         1,
  48795         soc_Q_SCHED_CPU_L1_MC_QUEUE_MASKr_fields,
  48796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48797         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  48798         -1,
  48799         -1,
  48800         3,
  48801     },
  48802 #endif /* chips */
  48803 
  48804 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  48805     { /* SOC_REG_INT_Q_SCHED_CPU_PORT_CONFIGr */
  48806         soc_block_list[125],
  48807         soc_genreg,
  48808         1,
  48809         0,
  48810         0x36001900,
  48811         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48812         0,
  48813         2,
  48814         soc_Q_SCHED_CPU_PORT_CONFIGr_fields,
  48815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48816         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  48817         -1,
  48818         -1,
  48819         3,
  48820     },
  48821 #endif /* chips */
  48822 
  48823 #if defined(BCM_56370_A0)
  48824     { /* SOC_REG_INT_Q_SCHED_CPU_PORT_CONFIG_BCM56370_A0r */
  48825         soc_block_list[125],
  48826         soc_genreg,
  48827         1,
  48828         0,
  48829         0x12004f00,
  48830         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48831         0,
  48832         2,
  48833         soc_Q_SCHED_CPU_PORT_CONFIGr_fields,
  48834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48835         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  48836         -1,
  48837         -1,
  48838         3,
  48839     },
  48840 #endif /* chips */
  48841 
  48842 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  48843     { /* SOC_REG_INT_Q_SCHED_CPU_PORT_CONFIG_BCM56870_A0r */
  48844         soc_block_list[125],
  48845         soc_genreg,
  48846         1,
  48847         0,
  48848         0x12005900,
  48849         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48850         0,
  48851         2,
  48852         soc_Q_SCHED_CPU_PORT_CONFIGr_fields,
  48853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48854         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  48855         -1,
  48856         -1,
  48857         3,
  48858     },
  48859 #endif /* chips */
  48860 
  48861 #if defined(BCM_56970_A0)
  48862     { /* SOC_REG_INT_Q_SCHED_CPU_PORT_CONFIG_BCM56970_A0r */
  48863         soc_block_list[125],
  48864         soc_genreg,
  48865         1,
  48866         0,
  48867         0x12001900,
  48868         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48869         0,
  48870         2,
  48871         soc_Q_SCHED_CPU_PORT_CONFIGr_fields,
  48872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48873         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  48874         -1,
  48875         -1,
  48876         3,
  48877     },
  48878 #endif /* chips */
  48879 
  48880 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  48881     defined(BCM_56870_A0)
  48882     { /* SOC_REG_INT_Q_SCHED_DD_CHIP_CONFIG0r */
  48883         soc_block_list[125],
  48884         soc_genreg,
  48885         1,
  48886         0,
  48887         0x12000600,
  48888         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48889         0,
  48890         5,
  48891         soc_Q_SCHED_DD_CHIP_CONFIG0r_fields,
  48892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48893         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  48894         -1,
  48895         -1,
  48896         3,
  48897     },
  48898 #endif /* chips */
  48899 
  48900 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  48901     { /* SOC_REG_INT_Q_SCHED_DD_CHIP_CONFIG1r */
  48902         soc_block_list[125],
  48903         soc_genreg,
  48904         1,
  48905         0,
  48906         0x36000400,
  48907         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48908         0,
  48909         5,
  48910         soc_Q_SCHED_DD_CHIP_CONFIG1r_fields,
  48911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48912         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  48913         -1,
  48914         -1,
  48915         3,
  48916     },
  48917 #endif /* chips */
  48918 
  48919 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  48920     { /* SOC_REG_INT_Q_SCHED_DD_CHIP_CONFIG2r */
  48921         soc_block_list[125],
  48922         soc_genreg,
  48923         1,
  48924         0,
  48925         0x36000500,
  48926         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48927         0,
  48928         1,
  48929         soc_Q_SCHED_DD_CHIP_CONFIG2r_fields,
  48930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48931         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48932         -1,
  48933         -1,
  48934         3,
  48935     },
  48936 #endif /* chips */
  48937 
  48938 #if defined(BCM_56370_A0)
  48939     { /* SOC_REG_INT_Q_SCHED_DD_CHIP_CONFIG3r */
  48940         soc_block_list[125],
  48941         soc_genreg,
  48942         1,
  48943         0,
  48944         0x12000800,
  48945         SOC_REG_FLAG_64_BITS |
  48946                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48947         0,
  48948         16,
  48949         soc_Q_SCHED_DD_CHIP_CONFIG3r_fields,
  48950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48951         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  48952         -1,
  48953         -1,
  48954         3,
  48955     },
  48956 #endif /* chips */
  48957 
  48958 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  48959     defined(BCM_56870_A0)
  48960     { /* SOC_REG_INT_Q_SCHED_DD_CHIP_CONFIG1_BCM56870_A0r */
  48961         soc_block_list[125],
  48962         soc_genreg,
  48963         1,
  48964         0,
  48965         0x12000700,
  48966         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48967         0,
  48968         6,
  48969         soc_Q_SCHED_DD_CHIP_CONFIG1_BCM56870_A0r_fields,
  48970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48971         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  48972         -1,
  48973         -1,
  48974         3,
  48975     },
  48976 #endif /* chips */
  48977 
  48978 #if defined(BCM_56970_A0)
  48979     { /* SOC_REG_INT_Q_SCHED_DD_CHIP_CONFIG1_BCM56970_A0r */
  48980         soc_block_list[125],
  48981         soc_genreg,
  48982         1,
  48983         0,
  48984         0x12000400,
  48985         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  48986         0,
  48987         5,
  48988         soc_Q_SCHED_DD_CHIP_CONFIG1r_fields,
  48989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48990         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  48991         -1,
  48992         -1,
  48993         3,
  48994     },
  48995 #endif /* chips */
  48996 
  48997 #if defined(BCM_56370_A0)
  48998     { /* SOC_REG_INT_Q_SCHED_DD_CHIP_CONFIG2_BCM56370_A0r */
  48999         soc_block_list[125],
  49000         soc_genreg,
  49001         1,
  49002         0,
  49003         0x12000900,
  49004         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49005         0,
  49006         1,
  49007         soc_Q_SCHED_DD_CHIP_CONFIG2r_fields,
  49008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49009         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  49010         -1,
  49011         -1,
  49012         3,
  49013     },
  49014 #endif /* chips */
  49015 
  49016 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49017     { /* SOC_REG_INT_Q_SCHED_DD_CHIP_CONFIG2_BCM56870_A0r */
  49018         soc_block_list[125],
  49019         soc_genreg,
  49020         1,
  49021         0,
  49022         0x12000800,
  49023         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49024         0,
  49025         1,
  49026         soc_Q_SCHED_DD_CHIP_CONFIG2r_fields,
  49027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49028         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  49029         -1,
  49030         -1,
  49031         3,
  49032     },
  49033 #endif /* chips */
  49034 
  49035 #if defined(BCM_56970_A0)
  49036     { /* SOC_REG_INT_Q_SCHED_DD_CHIP_CONFIG2_BCM56970_A0r */
  49037         soc_block_list[125],
  49038         soc_genreg,
  49039         1,
  49040         0,
  49041         0x12000500,
  49042         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49043         0,
  49044         1,
  49045         soc_Q_SCHED_DD_CHIP_CONFIG2r_fields,
  49046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49047         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  49048         -1,
  49049         -1,
  49050         3,
  49051     },
  49052 #endif /* chips */
  49053 
  49054 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49055     { /* SOC_REG_INT_Q_SCHED_DD_PORT_CONFIGr */
  49056         soc_block_list[125],
  49057         soc_portreg,
  49058         1,
  49059         0,
  49060         0x34800e00,
  49061         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49062         0,
  49063         1,
  49064         soc_Q_SCHED_DD_PORT_CONFIGr_fields,
  49065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49066         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49067         -1,
  49068         82,
  49069         3,
  49070     },
  49071 #endif /* chips */
  49072 
  49073 #if defined(BCM_56370_A0)
  49074     { /* SOC_REG_INT_Q_SCHED_DD_PORT_CONFIG_BCM56370_A0r */
  49075         soc_block_list[125],
  49076         soc_portreg,
  49077         1,
  49078         0,
  49079         0x10803b00,
  49080         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49081         0,
  49082         1,
  49083         soc_Q_SCHED_DD_PORT_CONFIG_BCM56370_A0r_fields,
  49084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49085         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  49086         -1,
  49087         113,
  49088         3,
  49089     },
  49090 #endif /* chips */
  49091 
  49092 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49093     { /* SOC_REG_INT_Q_SCHED_DD_PORT_CONFIG_BCM56870_A0r */
  49094         soc_block_list[125],
  49095         soc_portreg,
  49096         1,
  49097         0,
  49098         0x10805000,
  49099         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49100         0,
  49101         1,
  49102         soc_Q_SCHED_DD_PORT_CONFIGr_fields,
  49103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49104         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49105         -1,
  49106         97,
  49107         3,
  49108     },
  49109 #endif /* chips */
  49110 
  49111 #if defined(BCM_56970_A0)
  49112     { /* SOC_REG_INT_Q_SCHED_DD_PORT_CONFIG_BCM56970_A0r */
  49113         soc_block_list[125],
  49114         soc_portreg,
  49115         1,
  49116         0,
  49117         0x10800e00,
  49118         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49119         0,
  49120         1,
  49121         soc_Q_SCHED_DD_PORT_CONFIGr_fields,
  49122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49123         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49124         -1,
  49125         82,
  49126         3,
  49127     },
  49128 #endif /* chips */
  49129 
  49130 #if defined(BCM_56370_A0)
  49131     { /* SOC_REG_INT_Q_SCHED_DD_PORT_CONFIG_HIQr */
  49132         soc_block_list[125],
  49133         soc_portreg,
  49134         1,
  49135         0,
  49136         0x10803a00,
  49137         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49138         0,
  49139         1,
  49140         soc_Q_SCHED_DD_PORT_CONFIG_HIQr_fields,
  49141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49142         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  49143         -1,
  49144         85,
  49145         3,
  49146     },
  49147 #endif /* chips */
  49148 
  49149 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49150     { /* SOC_REG_INT_Q_SCHED_DD_TIMERr */
  49151         soc_block_list[125],
  49152         soc_portreg,
  49153         10,
  49154         0,
  49155         0x10801e00,
  49156         SOC_REG_FLAG_ARRAY |
  49157                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49158         0,
  49159         1,
  49160         soc_Q_SCHED_DD_TIMER_Ar_fields,
  49161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49162         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49163         -1,
  49164         97,
  49165         3,
  49166     },
  49167 #endif /* chips */
  49168 
  49169 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49170     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_Ar */
  49171         soc_block_list[125],
  49172         soc_portreg,
  49173         1,
  49174         0,
  49175         0x34800800,
  49176         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49177         0,
  49178         1,
  49179         soc_Q_SCHED_DD_TIMER_Ar_fields,
  49180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49182         -1,
  49183         82,
  49184         3,
  49185     },
  49186 #endif /* chips */
  49187 
  49188 #if defined(BCM_56970_A0)
  49189     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_A_BCM56970_A0r */
  49190         soc_block_list[125],
  49191         soc_portreg,
  49192         1,
  49193         0,
  49194         0x10800800,
  49195         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49196         0,
  49197         1,
  49198         soc_Q_SCHED_DD_TIMER_Ar_fields,
  49199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49200         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49201         -1,
  49202         82,
  49203         3,
  49204     },
  49205 #endif /* chips */
  49206 
  49207 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49208     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_Br */
  49209         soc_block_list[125],
  49210         soc_portreg,
  49211         1,
  49212         0,
  49213         0x34800900,
  49214         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49215         0,
  49216         1,
  49217         soc_Q_SCHED_DD_TIMER_Ar_fields,
  49218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49219         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49220         -1,
  49221         82,
  49222         3,
  49223     },
  49224 #endif /* chips */
  49225 
  49226 #if defined(BCM_56370_A0)
  49227     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_BCM56370_A0r */
  49228         soc_block_list[125],
  49229         soc_portreg,
  49230         16,
  49231         0,
  49232         0x10802600,
  49233         SOC_REG_FLAG_ARRAY |
  49234                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49235         0,
  49236         1,
  49237         soc_Q_SCHED_DD_TIMER_Ar_fields,
  49238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49239         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49240         -1,
  49241         113,
  49242         3,
  49243     },
  49244 #endif /* chips */
  49245 
  49246 #if defined(BCM_56970_A0)
  49247     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_B_BCM56970_A0r */
  49248         soc_block_list[125],
  49249         soc_portreg,
  49250         1,
  49251         0,
  49252         0x10800900,
  49253         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49254         0,
  49255         1,
  49256         soc_Q_SCHED_DD_TIMER_Ar_fields,
  49257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49258         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49259         -1,
  49260         82,
  49261         3,
  49262     },
  49263 #endif /* chips */
  49264 
  49265 #if defined(BCM_56370_A0)
  49266     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_ENABLEr */
  49267         soc_block_list[125],
  49268         soc_portreg,
  49269         1,
  49270         0,
  49271         0x10800b00,
  49272         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49273         0,
  49274         1,
  49275         soc_Q_SCHED_DD_TIMER_ENABLEr_fields,
  49276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49277         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  49278         -1,
  49279         113,
  49280         3,
  49281     },
  49282 #endif /* chips */
  49283 
  49284 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49285     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_ENABLE_Ar */
  49286         soc_block_list[125],
  49287         soc_pipereg,
  49288         1,
  49289         0,
  49290         0x35800600,
  49291         SOC_REG_FLAG_64_BITS |
  49292                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49293         0,
  49294         1,
  49295         soc_Q_SCHED_DD_TIMER_ENABLE_Ar_fields,
  49296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49298         -1,
  49299         -1,
  49300         3,
  49301     },
  49302 #endif /* chips */
  49303 
  49304 #if defined(BCM_56970_A0)
  49305     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_ENABLE_A_BCM56970_A0r */
  49306         soc_block_list[125],
  49307         soc_pipereg,
  49308         1,
  49309         0,
  49310         0x11800600,
  49311         SOC_REG_FLAG_64_BITS |
  49312                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49313         0,
  49314         1,
  49315         soc_Q_SCHED_DD_TIMER_ENABLE_Ar_fields,
  49316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49318         -1,
  49319         -1,
  49320         3,
  49321     },
  49322 #endif /* chips */
  49323 
  49324 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49325     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_ENABLE_Br */
  49326         soc_block_list[125],
  49327         soc_pipereg,
  49328         1,
  49329         0,
  49330         0x35800700,
  49331         SOC_REG_FLAG_64_BITS |
  49332                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49333         0,
  49334         1,
  49335         soc_Q_SCHED_DD_TIMER_ENABLE_Ar_fields,
  49336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49337         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49338         -1,
  49339         -1,
  49340         3,
  49341     },
  49342 #endif /* chips */
  49343 
  49344 #if defined(BCM_56970_A0)
  49345     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_ENABLE_B_BCM56970_A0r */
  49346         soc_block_list[125],
  49347         soc_pipereg,
  49348         1,
  49349         0,
  49350         0x11800700,
  49351         SOC_REG_FLAG_64_BITS |
  49352                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49353         0,
  49354         1,
  49355         soc_Q_SCHED_DD_TIMER_ENABLE_Ar_fields,
  49356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49357         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49358         -1,
  49359         -1,
  49360         3,
  49361     },
  49362 #endif /* chips */
  49363 
  49364 #if defined(BCM_56370_A0)
  49365     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_ENABLE_HIQr */
  49366         soc_block_list[125],
  49367         soc_portreg,
  49368         1,
  49369         0,
  49370         0x10800a00,
  49371         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49372         0,
  49373         1,
  49374         soc_Q_SCHED_DD_TIMER_ENABLE_HIQr_fields,
  49375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49376         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  49377         -1,
  49378         85,
  49379         3,
  49380     },
  49381 #endif /* chips */
  49382 
  49383 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49384     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_ENABLE_SPLIT0r */
  49385         soc_block_list[125],
  49386         soc_pipereg,
  49387         10,
  49388         0,
  49389         0x11800900,
  49390         SOC_REG_FLAG_64_BITS |
  49391                           SOC_REG_FLAG_ARRAY |
  49392                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49393         0,
  49394         1,
  49395         soc_Q_SCHED_DD_TIMER_ENABLE_SPLIT0r_fields,
  49396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49397         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  49398         -1,
  49399         -1,
  49400         3,
  49401     },
  49402 #endif /* chips */
  49403 
  49404 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49405     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_ENABLE_SPLIT1r */
  49406         soc_block_list[125],
  49407         soc_pipereg,
  49408         10,
  49409         0,
  49410         0x11801400,
  49411         SOC_REG_FLAG_ARRAY |
  49412                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49413         0,
  49414         1,
  49415         soc_Q_SCHED_DD_TIMER_ENABLE_SPLIT1r_fields,
  49416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49417         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49418         -1,
  49419         -1,
  49420         3,
  49421     },
  49422 #endif /* chips */
  49423 
  49424 #if defined(BCM_56370_A0)
  49425     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_HIQr */
  49426         soc_block_list[125],
  49427         soc_portreg,
  49428         26,
  49429         0,
  49430         0x10800c00,
  49431         SOC_REG_FLAG_ARRAY |
  49432                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49433         0,
  49434         1,
  49435         soc_Q_SCHED_DD_TIMER_Ar_fields,
  49436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49437         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  49438         -1,
  49439         85,
  49440         3,
  49441     },
  49442 #endif /* chips */
  49443 
  49444 #if defined(BCM_56370_A0)
  49445     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUSr */
  49446         soc_block_list[125],
  49447         soc_portreg,
  49448         1,
  49449         0,
  49450         0x10803700,
  49451         SOC_REG_FLAG_RO |
  49452                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49453         0,
  49454         1,
  49455         soc_Q_SCHED_DD_TIMER_STATUSr_fields,
  49456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49457         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  49458         -1,
  49459         113,
  49460         3,
  49461     },
  49462 #endif /* chips */
  49463 
  49464 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49465     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_Ar */
  49466         soc_block_list[125],
  49467         soc_pipereg,
  49468         1,
  49469         0,
  49470         0x35800a00,
  49471         SOC_REG_FLAG_64_BITS |
  49472                           SOC_REG_FLAG_RO |
  49473                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49474         0,
  49475         1,
  49476         soc_Q_SCHED_DD_TIMER_STATUS_Ar_fields,
  49477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49478         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49479         -1,
  49480         -1,
  49481         3,
  49482     },
  49483 #endif /* chips */
  49484 
  49485 #if defined(BCM_56970_A0)
  49486     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_A_BCM56970_A0r */
  49487         soc_block_list[125],
  49488         soc_pipereg,
  49489         1,
  49490         0,
  49491         0x11800a00,
  49492         SOC_REG_FLAG_64_BITS |
  49493                           SOC_REG_FLAG_RO |
  49494                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49495         0,
  49496         1,
  49497         soc_Q_SCHED_DD_TIMER_STATUS_Ar_fields,
  49498         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49499         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49500         -1,
  49501         -1,
  49502         3,
  49503     },
  49504 #endif /* chips */
  49505 
  49506 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49507     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_A_MASKr */
  49508         soc_block_list[125],
  49509         soc_pipereg,
  49510         1,
  49511         0,
  49512         0x35800c00,
  49513         SOC_REG_FLAG_64_BITS |
  49514                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49515         0,
  49516         1,
  49517         soc_Q_SCHED_DD_TIMER_STATUS_A_MASKr_fields,
  49518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49519         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49520         -1,
  49521         -1,
  49522         3,
  49523     },
  49524 #endif /* chips */
  49525 
  49526 #if defined(BCM_56970_A0)
  49527     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_A_MASK_BCM56970_A0r */
  49528         soc_block_list[125],
  49529         soc_pipereg,
  49530         1,
  49531         0,
  49532         0x11800c00,
  49533         SOC_REG_FLAG_64_BITS |
  49534                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49535         0,
  49536         1,
  49537         soc_Q_SCHED_DD_TIMER_STATUS_A_MASKr_fields,
  49538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49539         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49540         -1,
  49541         -1,
  49542         3,
  49543     },
  49544 #endif /* chips */
  49545 
  49546 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49547     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_Br */
  49548         soc_block_list[125],
  49549         soc_pipereg,
  49550         1,
  49551         0,
  49552         0x35800b00,
  49553         SOC_REG_FLAG_64_BITS |
  49554                           SOC_REG_FLAG_RO |
  49555                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49556         0,
  49557         1,
  49558         soc_Q_SCHED_DD_TIMER_STATUS_Ar_fields,
  49559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49560         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49561         -1,
  49562         -1,
  49563         3,
  49564     },
  49565 #endif /* chips */
  49566 
  49567 #if defined(BCM_56970_A0)
  49568     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_B_BCM56970_A0r */
  49569         soc_block_list[125],
  49570         soc_pipereg,
  49571         1,
  49572         0,
  49573         0x11800b00,
  49574         SOC_REG_FLAG_64_BITS |
  49575                           SOC_REG_FLAG_RO |
  49576                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49577         0,
  49578         1,
  49579         soc_Q_SCHED_DD_TIMER_STATUS_Ar_fields,
  49580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49581         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49582         -1,
  49583         -1,
  49584         3,
  49585     },
  49586 #endif /* chips */
  49587 
  49588 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49589     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_B_MASKr */
  49590         soc_block_list[125],
  49591         soc_pipereg,
  49592         1,
  49593         0,
  49594         0x35800d00,
  49595         SOC_REG_FLAG_64_BITS |
  49596                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49597         0,
  49598         1,
  49599         soc_Q_SCHED_DD_TIMER_STATUS_A_MASKr_fields,
  49600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49601         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49602         -1,
  49603         -1,
  49604         3,
  49605     },
  49606 #endif /* chips */
  49607 
  49608 #if defined(BCM_56970_A0)
  49609     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_B_MASK_BCM56970_A0r */
  49610         soc_block_list[125],
  49611         soc_pipereg,
  49612         1,
  49613         0,
  49614         0x11800d00,
  49615         SOC_REG_FLAG_64_BITS |
  49616                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49617         0,
  49618         1,
  49619         soc_Q_SCHED_DD_TIMER_STATUS_A_MASKr_fields,
  49620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49621         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  49622         -1,
  49623         -1,
  49624         3,
  49625     },
  49626 #endif /* chips */
  49627 
  49628 #if defined(BCM_56370_A0)
  49629     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_HIQr */
  49630         soc_block_list[125],
  49631         soc_portreg,
  49632         1,
  49633         0,
  49634         0x10803600,
  49635         SOC_REG_FLAG_RO |
  49636                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49637         0,
  49638         1,
  49639         soc_Q_SCHED_DD_TIMER_STATUS_HIQr_fields,
  49640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49641         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  49642         -1,
  49643         85,
  49644         3,
  49645     },
  49646 #endif /* chips */
  49647 
  49648 #if defined(BCM_56370_A0)
  49649     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_MASKr */
  49650         soc_block_list[125],
  49651         soc_portreg,
  49652         1,
  49653         0,
  49654         0x10803900,
  49655         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49656         0,
  49657         1,
  49658         soc_Q_SCHED_DD_TIMER_STATUS_MASKr_fields,
  49659         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49660         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  49661         -1,
  49662         113,
  49663         3,
  49664     },
  49665 #endif /* chips */
  49666 
  49667 #if defined(BCM_56370_A0)
  49668     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_MASK_HIQr */
  49669         soc_block_list[125],
  49670         soc_portreg,
  49671         1,
  49672         0,
  49673         0x10803800,
  49674         SOC_REG_FLAG_64_BITS |
  49675                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49676         0,
  49677         1,
  49678         soc_Q_SCHED_DD_TIMER_STATUS_MASK_HIQr_fields,
  49679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49680         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  49681         -1,
  49682         85,
  49683         3,
  49684     },
  49685 #endif /* chips */
  49686 
  49687 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49688     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_MASK_SPLIT0r */
  49689         soc_block_list[125],
  49690         soc_pipereg,
  49691         10,
  49692         0,
  49693         0x11803c00,
  49694         SOC_REG_FLAG_64_BITS |
  49695                           SOC_REG_FLAG_ARRAY |
  49696                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49697         0,
  49698         1,
  49699         soc_Q_SCHED_DD_TIMER_STATUS_MASK_SPLIT0r_fields,
  49700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49701         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  49702         -1,
  49703         -1,
  49704         3,
  49705     },
  49706 #endif /* chips */
  49707 
  49708 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49709     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_MASK_SPLIT1r */
  49710         soc_block_list[125],
  49711         soc_pipereg,
  49712         10,
  49713         0,
  49714         0x11804600,
  49715         SOC_REG_FLAG_ARRAY |
  49716                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49717         0,
  49718         1,
  49719         soc_Q_SCHED_DD_TIMER_STATUS_MASK_SPLIT1r_fields,
  49720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49721         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49722         -1,
  49723         -1,
  49724         3,
  49725     },
  49726 #endif /* chips */
  49727 
  49728 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49729     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_SPLIT0r */
  49730         soc_block_list[125],
  49731         soc_pipereg,
  49732         10,
  49733         0,
  49734         0x11802800,
  49735         SOC_REG_FLAG_64_BITS |
  49736                           SOC_REG_FLAG_ARRAY |
  49737                           SOC_REG_FLAG_RO |
  49738                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49739         0,
  49740         1,
  49741         soc_Q_SCHED_DD_TIMER_STATUS_SPLIT0r_fields,
  49742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49743         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  49744         -1,
  49745         -1,
  49746         3,
  49747     },
  49748 #endif /* chips */
  49749 
  49750 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49751     { /* SOC_REG_INT_Q_SCHED_DD_TIMER_STATUS_SPLIT1r */
  49752         soc_block_list[125],
  49753         soc_pipereg,
  49754         10,
  49755         0,
  49756         0x11803200,
  49757         SOC_REG_FLAG_ARRAY |
  49758                           SOC_REG_FLAG_RO |
  49759                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49760         0,
  49761         1,
  49762         soc_Q_SCHED_DD_TIMER_STATUS_SPLIT1r_fields,
  49763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49764         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49765         -1,
  49766         -1,
  49767         3,
  49768     },
  49769 #endif /* chips */
  49770 
  49771 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49772     { /* SOC_REG_INT_Q_SCHED_DEBUG_FORCE_CPU_COSMASKr */
  49773         soc_block_list[125],
  49774         soc_genreg,
  49775         1,
  49776         0,
  49777         0x36000f00,
  49778         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49779         0,
  49780         1,
  49781         soc_Q_SCHED_DEBUG_FORCE_CPU_COSMASKr_fields,
  49782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49783         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49784         -1,
  49785         -1,
  49786         3,
  49787     },
  49788 #endif /* chips */
  49789 
  49790 #if defined(BCM_56370_A0)
  49791     { /* SOC_REG_INT_Q_SCHED_DEBUG_FORCE_CPU_COSMASK_BCM56370_A0r */
  49792         soc_block_list[125],
  49793         soc_genreg,
  49794         1,
  49795         0,
  49796         0x12003c00,
  49797         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49798         0,
  49799         1,
  49800         soc_Q_SCHED_DEBUG_FORCE_CPU_COSMASKr_fields,
  49801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49802         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49803         -1,
  49804         -1,
  49805         3,
  49806     },
  49807 #endif /* chips */
  49808 
  49809 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49810     { /* SOC_REG_INT_Q_SCHED_DEBUG_FORCE_CPU_COSMASK_BCM56870_A0r */
  49811         soc_block_list[125],
  49812         soc_genreg,
  49813         1,
  49814         0,
  49815         0x12005000,
  49816         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49817         0,
  49818         1,
  49819         soc_Q_SCHED_DEBUG_FORCE_CPU_COSMASKr_fields,
  49820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49821         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49822         -1,
  49823         -1,
  49824         3,
  49825     },
  49826 #endif /* chips */
  49827 
  49828 #if defined(BCM_56970_A0)
  49829     { /* SOC_REG_INT_Q_SCHED_DEBUG_FORCE_CPU_COSMASK_BCM56970_A0r */
  49830         soc_block_list[125],
  49831         soc_genreg,
  49832         1,
  49833         0,
  49834         0x12000f00,
  49835         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49836         0,
  49837         1,
  49838         soc_Q_SCHED_DEBUG_FORCE_CPU_COSMASKr_fields,
  49839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49840         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  49841         -1,
  49842         -1,
  49843         3,
  49844     },
  49845 #endif /* chips */
  49846 
  49847 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49848     { /* SOC_REG_INT_Q_SCHED_ENABLE_ECCP_MEMr */
  49849         soc_block_list[125],
  49850         soc_pipereg,
  49851         1,
  49852         0,
  49853         0x35801400,
  49854         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49855         0,
  49856         9,
  49857         soc_Q_SCHED_ENABLE_ECCP_MEMr_fields,
  49858         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  49859         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49860         -1,
  49861         -1,
  49862         3,
  49863     },
  49864 #endif /* chips */
  49865 
  49866 #if defined(BCM_56370_A0)
  49867     { /* SOC_REG_INT_Q_SCHED_ENABLE_ECCP_MEM_BCM56370_A0r */
  49868         soc_block_list[125],
  49869         soc_pipereg,
  49870         1,
  49871         0,
  49872         0x11804200,
  49873         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49874         0,
  49875         13,
  49876         soc_Q_SCHED_ENABLE_ECCP_MEM_BCM56370_A0r_fields,
  49877         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  49878         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  49879         -1,
  49880         -1,
  49881         3,
  49882     },
  49883 #endif /* chips */
  49884 
  49885 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49886     { /* SOC_REG_INT_Q_SCHED_ENABLE_ECCP_MEM_BCM56870_A0r */
  49887         soc_block_list[125],
  49888         soc_pipereg,
  49889         1,
  49890         0,
  49891         0x11805400,
  49892         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49893         0,
  49894         7,
  49895         soc_Q_SCHED_ENABLE_ECCP_MEM_BCM56870_A0r_fields,
  49896         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  49897         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  49898         -1,
  49899         -1,
  49900         3,
  49901     },
  49902 #endif /* chips */
  49903 
  49904 #if defined(BCM_56970_A0)
  49905     { /* SOC_REG_INT_Q_SCHED_ENABLE_ECCP_MEM_BCM56970_A0r */
  49906         soc_block_list[125],
  49907         soc_pipereg,
  49908         1,
  49909         0,
  49910         0x11801400,
  49911         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49912         0,
  49913         9,
  49914         soc_Q_SCHED_ENABLE_ECCP_MEMr_fields,
  49915         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  49916         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49917         -1,
  49918         -1,
  49919         3,
  49920     },
  49921 #endif /* chips */
  49922 
  49923 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  49924     { /* SOC_REG_INT_Q_SCHED_EN_COR_ERR_RPTr */
  49925         soc_block_list[125],
  49926         soc_pipereg,
  49927         1,
  49928         0,
  49929         0x35801300,
  49930         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49931         0,
  49932         9,
  49933         soc_Q_SCHED_EN_COR_ERR_RPTr_fields,
  49934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49935         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49936         -1,
  49937         -1,
  49938         3,
  49939     },
  49940 #endif /* chips */
  49941 
  49942 #if defined(BCM_56370_A0)
  49943     { /* SOC_REG_INT_Q_SCHED_EN_COR_ERR_RPT_BCM56370_A0r */
  49944         soc_block_list[125],
  49945         soc_pipereg,
  49946         1,
  49947         0,
  49948         0x11804100,
  49949         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49950         0,
  49951         13,
  49952         soc_Q_SCHED_EN_COR_ERR_RPT_BCM56370_A0r_fields,
  49953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49954         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  49955         -1,
  49956         -1,
  49957         3,
  49958     },
  49959 #endif /* chips */
  49960 
  49961 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  49962     { /* SOC_REG_INT_Q_SCHED_EN_COR_ERR_RPT_BCM56870_A0r */
  49963         soc_block_list[125],
  49964         soc_pipereg,
  49965         1,
  49966         0,
  49967         0x11805300,
  49968         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49969         0,
  49970         7,
  49971         soc_Q_SCHED_EN_COR_ERR_RPT_BCM56870_A0r_fields,
  49972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49973         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  49974         -1,
  49975         -1,
  49976         3,
  49977     },
  49978 #endif /* chips */
  49979 
  49980 #if defined(BCM_56970_A0)
  49981     { /* SOC_REG_INT_Q_SCHED_EN_COR_ERR_RPT_BCM56970_A0r */
  49982         soc_block_list[125],
  49983         soc_pipereg,
  49984         1,
  49985         0,
  49986         0x11801300,
  49987         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  49988         0,
  49989         9,
  49990         soc_Q_SCHED_EN_COR_ERR_RPTr_fields,
  49991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49992         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49993         -1,
  49994         -1,
  49995         3,
  49996     },
  49997 #endif /* chips */
  49998 
  49999 #if defined(BCM_56370_A0)
  50000     { /* SOC_REG_INT_Q_SCHED_INTERNAL_FLUSH_DISABLE_CONFIGr */
  50001         soc_block_list[125],
  50002         soc_portreg,
  50003         1,
  50004         0,
  50005         0x10808300,
  50006         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50007         0,
  50008         1,
  50009         soc_Q_SCHED_INTERNAL_FLUSH_DISABLE_CONFIGr_fields,
  50010         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50011         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50012         -1,
  50013         111,
  50014         3,
  50015     },
  50016 #endif /* chips */
  50017 
  50018 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  50019     { /* SOC_REG_INT_Q_SCHED_L0_MEMORY_TMr */
  50020         soc_block_list[125],
  50021         soc_pipereg,
  50022         1,
  50023         0,
  50024         0x35801000,
  50025         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50026         0,
  50027         10,
  50028         soc_Q_SCHED_L0_MEMORY_TMr_fields,
  50029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50030         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50031         -1,
  50032         -1,
  50033         3,
  50034     },
  50035 #endif /* chips */
  50036 
  50037 #if defined(BCM_56370_A0)
  50038     { /* SOC_REG_INT_Q_SCHED_L0_MEMORY_TM_BCM56370_A0r */
  50039         soc_block_list[125],
  50040         soc_pipereg,
  50041         1,
  50042         0,
  50043         0x11803d00,
  50044         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50045         0,
  50046         4,
  50047         soc_Q_SCHED_L0_MEMORY_TM_BCM56870_A0r_fields,
  50048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50049         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  50050         -1,
  50051         -1,
  50052         3,
  50053     },
  50054 #endif /* chips */
  50055 
  50056 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  50057     { /* SOC_REG_INT_Q_SCHED_L0_MEMORY_TM_BCM56870_A0r */
  50058         soc_block_list[125],
  50059         soc_pipereg,
  50060         1,
  50061         0,
  50062         0x11805100,
  50063         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50064         0,
  50065         4,
  50066         soc_Q_SCHED_L0_MEMORY_TM_BCM56870_A0r_fields,
  50067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50068         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  50069         -1,
  50070         -1,
  50071         3,
  50072     },
  50073 #endif /* chips */
  50074 
  50075 #if defined(BCM_56970_A0)
  50076     { /* SOC_REG_INT_Q_SCHED_L0_MEMORY_TM_BCM56970_A0r */
  50077         soc_block_list[125],
  50078         soc_pipereg,
  50079         1,
  50080         0,
  50081         0x11801000,
  50082         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50083         0,
  50084         10,
  50085         soc_Q_SCHED_L0_MEMORY_TMr_fields,
  50086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50087         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50088         -1,
  50089         -1,
  50090         3,
  50091     },
  50092 #endif /* chips */
  50093 
  50094 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  50095     { /* SOC_REG_INT_Q_SCHED_L0_NODE_CONFIGr */
  50096         soc_block_list[125],
  50097         soc_portreg,
  50098         1,
  50099         0,
  50100         0x34801600,
  50101         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50102         0,
  50103         3,
  50104         soc_Q_SCHED_CPU_L0_NODE_CONFIGr_fields,
  50105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50106         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  50107         -1,
  50108         82,
  50109         3,
  50110     },
  50111 #endif /* chips */
  50112 
  50113 #if defined(BCM_56370_A0)
  50114     { /* SOC_REG_INT_Q_SCHED_L0_NODE_CONFIG_BCM56370_A0r */
  50115         soc_block_list[125],
  50116         soc_portreg,
  50117         1,
  50118         0,
  50119         0x10804400,
  50120         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50121         0,
  50122         3,
  50123         soc_Q_SCHED_L0_NODE_CONFIGr_fields,
  50124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50125         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  50126         -1,
  50127         113,
  50128         3,
  50129     },
  50130 #endif /* chips */
  50131 
  50132 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  50133     { /* SOC_REG_INT_Q_SCHED_L0_NODE_CONFIG_BCM56870_A0r */
  50134         soc_block_list[125],
  50135         soc_portreg,
  50136         1,
  50137         0,
  50138         0x10805600,
  50139         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50140         0,
  50141         3,
  50142         soc_Q_SCHED_CPU_L0_NODE_CONFIGr_fields,
  50143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50144         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  50145         -1,
  50146         97,
  50147         3,
  50148     },
  50149 #endif /* chips */
  50150 
  50151 #if defined(BCM_56970_A0)
  50152     { /* SOC_REG_INT_Q_SCHED_L0_NODE_CONFIG_BCM56970_A0r */
  50153         soc_block_list[125],
  50154         soc_portreg,
  50155         1,
  50156         0,
  50157         0x10801600,
  50158         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50159         0,
  50160         3,
  50161         soc_Q_SCHED_CPU_L0_NODE_CONFIGr_fields,
  50162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50163         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  50164         -1,
  50165         82,
  50166         3,
  50167     },
  50168 #endif /* chips */
  50169 
  50170 #if defined(BCM_56370_A0)
  50171     { /* SOC_REG_INT_Q_SCHED_L0_NODE_CONFIG_HIQr */
  50172         soc_block_list[125],
  50173         soc_portreg,
  50174         1,
  50175         0,
  50176         0x10804500,
  50177         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50178         0,
  50179         3,
  50180         soc_Q_SCHED_L0_NODE_CONFIG_HIQr_fields,
  50181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50182         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  50183         -1,
  50184         85,
  50185         3,
  50186     },
  50187 #endif /* chips */
  50188 
  50189 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  50190     { /* SOC_REG_INT_Q_SCHED_L1_MC_QUEUE_CONFIGr */
  50191         soc_block_list[125],
  50192         soc_portreg,
  50193         1,
  50194         0,
  50195         0x34801800,
  50196         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50197         0,
  50198         2,
  50199         soc_Q_SCHED_L1_MC_QUEUE_CONFIGr_fields,
  50200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50201         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  50202         -1,
  50203         82,
  50204         3,
  50205     },
  50206 #endif /* chips */
  50207 
  50208 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  50209     { /* SOC_REG_INT_Q_SCHED_L1_MC_QUEUE_CONFIG_BCM56870_A0r */
  50210         soc_block_list[125],
  50211         soc_portreg,
  50212         1,
  50213         0,
  50214         0x10805800,
  50215         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50216         0,
  50217         2,
  50218         soc_Q_SCHED_L1_MC_QUEUE_CONFIGr_fields,
  50219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50220         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  50221         -1,
  50222         97,
  50223         3,
  50224     },
  50225 #endif /* chips */
  50226 
  50227 #if defined(BCM_56970_A0)
  50228     { /* SOC_REG_INT_Q_SCHED_L1_MC_QUEUE_CONFIG_BCM56970_A0r */
  50229         soc_block_list[125],
  50230         soc_portreg,
  50231         1,
  50232         0,
  50233         0x10801800,
  50234         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50235         0,
  50236         2,
  50237         soc_Q_SCHED_L1_MC_QUEUE_CONFIGr_fields,
  50238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50239         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  50240         -1,
  50241         82,
  50242         3,
  50243     },
  50244 #endif /* chips */
  50245 
  50246 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  50247     { /* SOC_REG_INT_Q_SCHED_L1_MEMORY_TMr */
  50248         soc_block_list[125],
  50249         soc_pipereg,
  50250         1,
  50251         0,
  50252         0x35801100,
  50253         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50254         0,
  50255         11,
  50256         soc_Q_SCHED_L1_MEMORY_TMr_fields,
  50257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50258         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50259         -1,
  50260         -1,
  50261         3,
  50262     },
  50263 #endif /* chips */
  50264 
  50265 #if defined(BCM_56370_A0)
  50266     { /* SOC_REG_INT_Q_SCHED_L1_MEMORY_TM_BCM56370_A0r */
  50267         soc_block_list[125],
  50268         soc_pipereg,
  50269         1,
  50270         0,
  50271         0x11803e00,
  50272         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50273         0,
  50274         5,
  50275         soc_Q_SCHED_L1_MEMORY_TM_BCM56870_A0r_fields,
  50276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50277         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50278         -1,
  50279         -1,
  50280         3,
  50281     },
  50282 #endif /* chips */
  50283 
  50284 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  50285     { /* SOC_REG_INT_Q_SCHED_L1_MEMORY_TM_BCM56870_A0r */
  50286         soc_block_list[125],
  50287         soc_pipereg,
  50288         1,
  50289         0,
  50290         0x11805200,
  50291         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50292         0,
  50293         5,
  50294         soc_Q_SCHED_L1_MEMORY_TM_BCM56870_A0r_fields,
  50295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50296         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50297         -1,
  50298         -1,
  50299         3,
  50300     },
  50301 #endif /* chips */
  50302 
  50303 #if defined(BCM_56970_A0)
  50304     { /* SOC_REG_INT_Q_SCHED_L1_MEMORY_TM_BCM56970_A0r */
  50305         soc_block_list[125],
  50306         soc_pipereg,
  50307         1,
  50308         0,
  50309         0x11801100,
  50310         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50311         0,
  50312         11,
  50313         soc_Q_SCHED_L1_MEMORY_TMr_fields,
  50314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50315         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50316         -1,
  50317         -1,
  50318         3,
  50319     },
  50320 #endif /* chips */
  50321 
  50322 #if defined(BCM_56370_A0)
  50323     { /* SOC_REG_INT_Q_SCHED_L1_NODE_CONFIGr */
  50324         soc_block_list[125],
  50325         soc_portreg,
  50326         1,
  50327         0,
  50328         0x10804600,
  50329         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50330         0,
  50331         3,
  50332         soc_Q_SCHED_L1_NODE_CONFIGr_fields,
  50333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50334         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  50335         -1,
  50336         113,
  50337         3,
  50338     },
  50339 #endif /* chips */
  50340 
  50341 #if defined(BCM_56370_A0)
  50342     { /* SOC_REG_INT_Q_SCHED_L1_NODE_CONFIG_HIQr */
  50343         soc_block_list[125],
  50344         soc_portreg,
  50345         1,
  50346         0,
  50347         0x10804700,
  50348         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50349         0,
  50350         3,
  50351         soc_Q_SCHED_L1_NODE_CONFIG_HIQr_fields,
  50352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50353         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50354         -1,
  50355         85,
  50356         3,
  50357     },
  50358 #endif /* chips */
  50359 
  50360 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  50361     { /* SOC_REG_INT_Q_SCHED_L1_UC_QUEUE_CONFIGr */
  50362         soc_block_list[125],
  50363         soc_portreg,
  50364         1,
  50365         0,
  50366         0x34801700,
  50367         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50368         0,
  50369         2,
  50370         soc_Q_SCHED_L1_MC_QUEUE_CONFIGr_fields,
  50371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50372         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  50373         -1,
  50374         82,
  50375         3,
  50376     },
  50377 #endif /* chips */
  50378 
  50379 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  50380     { /* SOC_REG_INT_Q_SCHED_L1_UC_QUEUE_CONFIG_BCM56870_A0r */
  50381         soc_block_list[125],
  50382         soc_portreg,
  50383         1,
  50384         0,
  50385         0x10805700,
  50386         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50387         0,
  50388         2,
  50389         soc_Q_SCHED_L1_MC_QUEUE_CONFIGr_fields,
  50390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50391         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  50392         -1,
  50393         97,
  50394         3,
  50395     },
  50396 #endif /* chips */
  50397 
  50398 #if defined(BCM_56970_A0)
  50399     { /* SOC_REG_INT_Q_SCHED_L1_UC_QUEUE_CONFIG_BCM56970_A0r */
  50400         soc_block_list[125],
  50401         soc_portreg,
  50402         1,
  50403         0,
  50404         0x10801700,
  50405         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50406         0,
  50407         2,
  50408         soc_Q_SCHED_L1_MC_QUEUE_CONFIGr_fields,
  50409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50410         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  50411         -1,
  50412         82,
  50413         3,
  50414     },
  50415 #endif /* chips */
  50416 
  50417 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  50418     { /* SOC_REG_INT_Q_SCHED_L2_MEMORY_TMr */
  50419         soc_block_list[125],
  50420         soc_pipereg,
  50421         1,
  50422         0,
  50423         0x35801200,
  50424         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50425         0,
  50426         10,
  50427         soc_Q_SCHED_L2_MEMORY_TMr_fields,
  50428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50429         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50430         -1,
  50431         -1,
  50432         3,
  50433     },
  50434 #endif /* chips */
  50435 
  50436 #if defined(BCM_56370_A0)
  50437     { /* SOC_REG_INT_Q_SCHED_L2_MEMORY_TM_BCM56370_A0r */
  50438         soc_block_list[125],
  50439         soc_pipereg,
  50440         1,
  50441         0,
  50442         0x11803f00,
  50443         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50444         0,
  50445         5,
  50446         soc_Q_SCHED_L2_MEMORY_TM_BCM56370_A0r_fields,
  50447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50448         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50449         -1,
  50450         -1,
  50451         3,
  50452     },
  50453 #endif /* chips */
  50454 
  50455 #if defined(BCM_56970_A0)
  50456     { /* SOC_REG_INT_Q_SCHED_L2_MEMORY_TM_BCM56970_A0r */
  50457         soc_block_list[125],
  50458         soc_pipereg,
  50459         1,
  50460         0,
  50461         0x11801200,
  50462         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50463         0,
  50464         10,
  50465         soc_Q_SCHED_L2_MEMORY_TMr_fields,
  50466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50467         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50468         -1,
  50469         -1,
  50470         3,
  50471     },
  50472 #endif /* chips */
  50473 
  50474 #if defined(BCM_56370_A0)
  50475     { /* SOC_REG_INT_Q_SCHED_L2_NODE_CONFIG_HIQ_SPLIT0r */
  50476         soc_block_list[125],
  50477         soc_portreg,
  50478         1,
  50479         0,
  50480         0x10804900,
  50481         SOC_REG_FLAG_64_BITS |
  50482                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50483         0,
  50484         2,
  50485         soc_Q_SCHED_L2_NODE_CONFIG_HIQ_SPLIT0r_fields,
  50486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50487         SOC_RESET_MASK_DEC(0xffffffff, 0x000fffff)
  50488         -1,
  50489         85,
  50490         3,
  50491     },
  50492 #endif /* chips */
  50493 
  50494 #if defined(BCM_56370_A0)
  50495     { /* SOC_REG_INT_Q_SCHED_L2_NODE_CONFIG_HIQ_SPLIT1r */
  50496         soc_block_list[125],
  50497         soc_portreg,
  50498         1,
  50499         0,
  50500         0x10804a00,
  50501         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50502         0,
  50503         1,
  50504         soc_Q_SCHED_L2_NODE_CONFIG_HIQ_SPLIT1r_fields,
  50505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50506         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  50507         -1,
  50508         85,
  50509         3,
  50510     },
  50511 #endif /* chips */
  50512 
  50513 #if defined(BCM_56370_A0)
  50514     { /* SOC_REG_INT_Q_SCHED_L2_NODE_CONFIG_NORMQr */
  50515         soc_block_list[125],
  50516         soc_portreg,
  50517         1,
  50518         0,
  50519         0x10804800,
  50520         SOC_REG_FLAG_64_BITS |
  50521                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50522         0,
  50523         3,
  50524         soc_Q_SCHED_L2_NODE_CONFIG_NORMQr_fields,
  50525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50526         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  50527         -1,
  50528         113,
  50529         3,
  50530     },
  50531 #endif /* chips */
  50532 
  50533 #if defined(BCM_56370_A0)
  50534     { /* SOC_REG_INT_Q_SCHED_L3_MC_NODE_CONFIG_HIQr */
  50535         soc_block_list[125],
  50536         soc_portreg,
  50537         1,
  50538         0,
  50539         0x10804e00,
  50540         SOC_REG_FLAG_64_BITS |
  50541                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50542         0,
  50543         2,
  50544         soc_Q_SCHED_L3_MC_NODE_CONFIG_HIQr_fields,
  50545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50546         SOC_RESET_MASK_DEC(0xffffffff, 0x000fffff)
  50547         -1,
  50548         85,
  50549         3,
  50550     },
  50551 #endif /* chips */
  50552 
  50553 #if defined(BCM_56370_A0)
  50554     { /* SOC_REG_INT_Q_SCHED_L3_MC_NODE_CONFIG_NORMQr */
  50555         soc_block_list[125],
  50556         soc_portreg,
  50557         1,
  50558         0,
  50559         0x10804d00,
  50560         SOC_REG_FLAG_64_BITS |
  50561                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50562         0,
  50563         2,
  50564         soc_HSP_SCHED_L2_MC_CPU_QUEUE_CONFIG0r_fields,
  50565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50566         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50567         -1,
  50568         113,
  50569         3,
  50570     },
  50571 #endif /* chips */
  50572 
  50573 #if defined(BCM_56370_A0)
  50574     { /* SOC_REG_INT_Q_SCHED_L3_MEMORY_TMr */
  50575         soc_block_list[125],
  50576         soc_pipereg,
  50577         1,
  50578         0,
  50579         0x11804000,
  50580         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50581         0,
  50582         5,
  50583         soc_Q_SCHED_L3_MEMORY_TMr_fields,
  50584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50585         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50586         -1,
  50587         -1,
  50588         3,
  50589     },
  50590 #endif /* chips */
  50591 
  50592 #if defined(BCM_56370_A0)
  50593     { /* SOC_REG_INT_Q_SCHED_L3_UC_NODE_CONFIG_HIQr */
  50594         soc_block_list[125],
  50595         soc_portreg,
  50596         1,
  50597         0,
  50598         0x10804c00,
  50599         SOC_REG_FLAG_64_BITS |
  50600                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50601         0,
  50602         2,
  50603         soc_Q_SCHED_L3_MC_NODE_CONFIG_HIQr_fields,
  50604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50605         SOC_RESET_MASK_DEC(0xffffffff, 0x000fffff)
  50606         -1,
  50607         85,
  50608         3,
  50609     },
  50610 #endif /* chips */
  50611 
  50612 #if defined(BCM_56370_A0)
  50613     { /* SOC_REG_INT_Q_SCHED_L3_UC_NODE_CONFIG_NORMQr */
  50614         soc_block_list[125],
  50615         soc_portreg,
  50616         1,
  50617         0,
  50618         0x10804b00,
  50619         SOC_REG_FLAG_64_BITS |
  50620                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50621         0,
  50622         2,
  50623         soc_HSP_SCHED_L2_MC_CPU_QUEUE_CONFIG0r_fields,
  50624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50625         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50626         -1,
  50627         113,
  50628         3,
  50629     },
  50630 #endif /* chips */
  50631 
  50632 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  50633     { /* SOC_REG_INT_Q_SCHED_PORT_CONFIGr */
  50634         soc_block_list[125],
  50635         soc_portreg,
  50636         1,
  50637         0,
  50638         0x34801500,
  50639         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50640         0,
  50641         1,
  50642         soc_Q_SCHED_PORT_CONFIGr_fields,
  50643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50644         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50645         -1,
  50646         82,
  50647         3,
  50648     },
  50649 #endif /* chips */
  50650 
  50651 #if defined(BCM_56370_A0)
  50652     { /* SOC_REG_INT_Q_SCHED_PORT_CONFIG_BCM56370_A0r */
  50653         soc_block_list[125],
  50654         soc_portreg,
  50655         1,
  50656         0,
  50657         0x10804300,
  50658         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50659         0,
  50660         1,
  50661         soc_Q_SCHED_PORT_CONFIGr_fields,
  50662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50663         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50664         -1,
  50665         111,
  50666         3,
  50667     },
  50668 #endif /* chips */
  50669 
  50670 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  50671     { /* SOC_REG_INT_Q_SCHED_PORT_CONFIG_BCM56870_A0r */
  50672         soc_block_list[125],
  50673         soc_portreg,
  50674         1,
  50675         0,
  50676         0x10805500,
  50677         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50678         0,
  50679         1,
  50680         soc_Q_SCHED_PORT_CONFIGr_fields,
  50681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50682         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50683         -1,
  50684         97,
  50685         3,
  50686     },
  50687 #endif /* chips */
  50688 
  50689 #if defined(BCM_56970_A0)
  50690     { /* SOC_REG_INT_Q_SCHED_PORT_CONFIG_BCM56970_A0r */
  50691         soc_block_list[125],
  50692         soc_portreg,
  50693         1,
  50694         0,
  50695         0x10801500,
  50696         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50697         0,
  50698         1,
  50699         soc_Q_SCHED_PORT_CONFIGr_fields,
  50700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50701         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  50702         -1,
  50703         82,
  50704         3,
  50705     },
  50706 #endif /* chips */
  50707 
  50708 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  50709     { /* SOC_REG_INT_Q_SCHED_PORT_EMPTY_STATUSr */
  50710         soc_block_list[125],
  50711         soc_pipereg,
  50712         1,
  50713         0,
  50714         0x35800200,
  50715         SOC_REG_FLAG_64_BITS |
  50716                           SOC_REG_FLAG_RO |
  50717                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50718         0,
  50719         1,
  50720         soc_Q_SCHED_PORT_EMPTY_STATUSr_fields,
  50721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50722         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  50723         -1,
  50724         -1,
  50725         3,
  50726     },
  50727 #endif /* chips */
  50728 
  50729 #if defined(BCM_56970_A0)
  50730     { /* SOC_REG_INT_Q_SCHED_PORT_EMPTY_STATUS_BCM56970_A0r */
  50731         soc_block_list[125],
  50732         soc_pipereg,
  50733         1,
  50734         0,
  50735         0x11800200,
  50736         SOC_REG_FLAG_64_BITS |
  50737                           SOC_REG_FLAG_RO |
  50738                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50739         0,
  50740         1,
  50741         soc_Q_SCHED_PORT_EMPTY_STATUSr_fields,
  50742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  50744         -1,
  50745         -1,
  50746         3,
  50747     },
  50748 #endif /* chips */
  50749 
  50750 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  50751     defined(BCM_56870_A0)
  50752     { /* SOC_REG_INT_Q_SCHED_PORT_EMPTY_STATUS_SPLIT0r */
  50753         soc_block_list[125],
  50754         soc_pipereg,
  50755         1,
  50756         0,
  50757         0x11800300,
  50758         SOC_REG_FLAG_64_BITS |
  50759                           SOC_REG_FLAG_RO |
  50760                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50761         0,
  50762         1,
  50763         soc_Q_SCHED_PORT_EMPTY_STATUS_SPLIT0r_fields,
  50764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50765         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  50766         -1,
  50767         -1,
  50768         3,
  50769     },
  50770 #endif /* chips */
  50771 
  50772 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  50773     { /* SOC_REG_INT_Q_SCHED_PORT_EMPTY_STATUS_SPLIT1r */
  50774         soc_block_list[125],
  50775         soc_pipereg,
  50776         1,
  50777         0,
  50778         0x11800400,
  50779         SOC_REG_FLAG_RO |
  50780                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50781         0,
  50782         1,
  50783         soc_Q_SCHED_PORT_EMPTY_STATUS_SPLIT1r_fields,
  50784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50785         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50786         -1,
  50787         -1,
  50788         3,
  50789     },
  50790 #endif /* chips */
  50791 
  50792 #if defined(BCM_56370_A0)
  50793     { /* SOC_REG_INT_Q_SCHED_PORT_EMPTY_STATUS_SPLIT1_BCM56370_A0r */
  50794         soc_block_list[125],
  50795         soc_pipereg,
  50796         1,
  50797         0,
  50798         0x11800400,
  50799         SOC_REG_FLAG_RO |
  50800                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50801         0,
  50802         1,
  50803         soc_Q_SCHED_PORT_EMPTY_STATUS_SPLIT1_BCM56370_A0r_fields,
  50804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50805         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50806         -1,
  50807         -1,
  50808         3,
  50809     },
  50810 #endif /* chips */
  50811 
  50812 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  50813     { /* SOC_REG_INT_Q_SCHED_PORT_FLUSHr */
  50814         soc_block_list[125],
  50815         soc_pipereg,
  50816         1,
  50817         0,
  50818         0x35800100,
  50819         SOC_REG_FLAG_64_BITS |
  50820                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50821         0,
  50822         1,
  50823         soc_Q_SCHED_PORT_FLUSHr_fields,
  50824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50825         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  50826         -1,
  50827         -1,
  50828         3,
  50829     },
  50830 #endif /* chips */
  50831 
  50832 #if defined(BCM_56970_A0)
  50833     { /* SOC_REG_INT_Q_SCHED_PORT_FLUSH_BCM56970_A0r */
  50834         soc_block_list[125],
  50835         soc_pipereg,
  50836         1,
  50837         0,
  50838         0x11800100,
  50839         SOC_REG_FLAG_64_BITS |
  50840                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50841         0,
  50842         1,
  50843         soc_Q_SCHED_PORT_FLUSHr_fields,
  50844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50845         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  50846         -1,
  50847         -1,
  50848         3,
  50849     },
  50850 #endif /* chips */
  50851 
  50852 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  50853     defined(BCM_56870_A0)
  50854     { /* SOC_REG_INT_Q_SCHED_PORT_FLUSH_SPLIT0r */
  50855         soc_block_list[125],
  50856         soc_pipereg,
  50857         1,
  50858         0,
  50859         0x11800100,
  50860         SOC_REG_FLAG_64_BITS |
  50861                           (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50862         0,
  50863         1,
  50864         soc_Q_SCHED_PORT_FLUSH_SPLIT0r_fields,
  50865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50866         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  50867         -1,
  50868         -1,
  50869         3,
  50870     },
  50871 #endif /* chips */
  50872 
  50873 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  50874     { /* SOC_REG_INT_Q_SCHED_PORT_FLUSH_SPLIT1r */
  50875         soc_block_list[125],
  50876         soc_pipereg,
  50877         1,
  50878         0,
  50879         0x11800200,
  50880         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50881         0,
  50882         1,
  50883         soc_Q_SCHED_PORT_FLUSH_SPLIT1r_fields,
  50884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50885         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50886         -1,
  50887         -1,
  50888         3,
  50889     },
  50890 #endif /* chips */
  50891 
  50892 #if defined(BCM_56370_A0)
  50893     { /* SOC_REG_INT_Q_SCHED_PORT_FLUSH_SPLIT1_BCM56370_A0r */
  50894         soc_block_list[125],
  50895         soc_pipereg,
  50896         1,
  50897         0,
  50898         0x11800200,
  50899         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50900         0,
  50901         1,
  50902         soc_Q_SCHED_PORT_FLUSH_SPLIT1_BCM56370_A0r_fields,
  50903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50904         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50905         -1,
  50906         -1,
  50907         3,
  50908     },
  50909 #endif /* chips */
  50910 
  50911 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  50912     { /* SOC_REG_INT_Q_SCHED_RQE_SNAPSHOTr */
  50913         soc_block_list[125],
  50914         soc_pipereg,
  50915         1,
  50916         0,
  50917         0x35800300,
  50918         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50919         0,
  50920         2,
  50921         soc_Q_SCHED_RQE_SNAPSHOTr_fields,
  50922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50923         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50924         -1,
  50925         -1,
  50926         3,
  50927     },
  50928 #endif /* chips */
  50929 
  50930 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
  50931     defined(BCM_56870_A0)
  50932     { /* SOC_REG_INT_Q_SCHED_RQE_SNAPSHOT_BCM56870_A0r */
  50933         soc_block_list[125],
  50934         soc_pipereg,
  50935         1,
  50936         0,
  50937         0x11800500,
  50938         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50939         0,
  50940         2,
  50941         soc_Q_SCHED_RQE_SNAPSHOTr_fields,
  50942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50943         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50944         -1,
  50945         -1,
  50946         3,
  50947     },
  50948 #endif /* chips */
  50949 
  50950 #if defined(BCM_56970_A0)
  50951     { /* SOC_REG_INT_Q_SCHED_RQE_SNAPSHOT_BCM56970_A0r */
  50952         soc_block_list[125],
  50953         soc_pipereg,
  50954         1,
  50955         0,
  50956         0x11800300,
  50957         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50958         0,
  50959         2,
  50960         soc_Q_SCHED_RQE_SNAPSHOTr_fields,
  50961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50962         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  50963         -1,
  50964         -1,
  50965         3,
  50966     },
  50967 #endif /* chips */
  50968 
  50969 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
  50970     { /* SOC_REG_INT_Q_SCHED_SPECIAL_CONFIGr */
  50971         soc_block_list[125],
  50972         soc_pipereg,
  50973         1,
  50974         0,
  50975         0x35800000,
  50976         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50977         0,
  50978         6,
  50979         soc_Q_SCHED_SPECIAL_CONFIGr_fields,
  50980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50981         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  50982         -1,
  50983         -1,
  50984         3,
  50985     },
  50986 #endif /* chips */
  50987 
  50988 #if defined(BCM_56370_A0)
  50989     { /* SOC_REG_INT_Q_SCHED_SPECIAL_CONFIG_BCM56370_A0r */
  50990         soc_block_list[125],
  50991         soc_pipereg,
  50992         1,
  50993         0,
  50994         0x11800000,
  50995         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  50996         0,
  50997         7,
  50998         soc_Q_SCHED_SPECIAL_CONFIG_BCM56370_A0r_fields,
  50999         SOC_RESET_VAL_DEC(0x000002c0, 0x00000000)
  51000         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  51001         -1,
  51002         -1,
  51003         3,
  51004     },
  51005 #endif /* chips */
  51006 
  51007 #if defined(BCM_56770_A0) || defined(BCM_56870_A0)
  51008     { /* SOC_REG_INT_Q_SCHED_SPECIAL_CONFIG_BCM56870_A0r */
  51009         soc_block_list[125],
  51010         soc_pipereg,
  51011         1,
  51012         0,
  51013         0x11800000,
  51014         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  51015         0,
  51016         6,
  51017         soc_Q_SCHED_SPECIAL_CONFIG_BCM56870_A0r_fields,
  51018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51019         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  51020         -1,
  51021         -1,
  51022         3,
  51023     },
  51024 #endif /* chips */
  51025 
  51026 #if defined(BCM_56970_A0)
  51027     { /* SOC_REG_INT_Q_SCHED_SPECIAL_CONFIG_BCM56970_A0r */
  51028         soc_block_list[125],
  51029         soc_pipereg,
  51030         1,
  51031         0,
  51032         0x11800000,
  51033         (20 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  51034         0,
  51035         6,
  51036         soc_Q_SCHED_SPECIAL_CONFIG_BCM56970_A0r_fields,
  51037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51038         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  51039         -1,
  51040         -1,
  51041         3,
  51042     },
  51043 #endif /* chips */
  51044